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sparc-tdep.c
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/* Target-dependent code for SPARC.
Copyright (C) 2003-2015 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "arch-utils.h"
#include "dis-asm.h"
#include "dwarf2-frame.h"
#include "floatformat.h"
#include "frame.h"
#include "frame-base.h"
#include "frame-unwind.h"
#include "gdbcore.h"
#include "gdbtypes.h"
#include "inferior.h"
#include "symtab.h"
#include "objfiles.h"
#include "osabi.h"
#include "regcache.h"
#include "target.h"
#include "value.h"
#include "sparc-tdep.h"
#include "sparc-ravenscar-thread.h"
struct regset;
/* This file implements the SPARC 32-bit ABI as defined by the section
"Low-Level System Information" of the SPARC Compliance Definition
(SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
lists changes with respect to the original 32-bit psABI as defined
in the "System V ABI, SPARC Processor Supplement".
Note that if we talk about SunOS, we mean SunOS 4.x, which was
BSD-based, which is sometimes (retroactively?) referred to as
Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
suffering from severe version number inflation). Solaris 2.x is
also known as SunOS 5.x, since that's what uname(1) says. Solaris
2.x is SVR4-based. */
/* Please use the sparc32_-prefix for 32-bit specific code, the
sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
code that can handle both. The 64-bit specific code lives in
sparc64-tdep.c; don't add any here. */
/* The SPARC Floating-Point Quad-Precision format is similar to
big-endian IA-64 Quad-Precision format. */
#define floatformats_sparc_quad floatformats_ia64_quad
/* The stack pointer is offset from the stack frame by a BIAS of 2047
(0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
hosts, so undefine it first. */
#undef BIAS
#define BIAS 2047
/* Macros to extract fields from SPARC instructions. */
#define X_OP(i) (((i) >> 30) & 0x3)
#define X_RD(i) (((i) >> 25) & 0x1f)
#define X_A(i) (((i) >> 29) & 1)
#define X_COND(i) (((i) >> 25) & 0xf)
#define X_OP2(i) (((i) >> 22) & 0x7)
#define X_IMM22(i) ((i) & 0x3fffff)
#define X_OP3(i) (((i) >> 19) & 0x3f)
#define X_RS1(i) (((i) >> 14) & 0x1f)
#define X_RS2(i) ((i) & 0x1f)
#define X_I(i) (((i) >> 13) & 1)
/* Sign extension macros. */
#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
#define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
#define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
/* Macros to identify some instructions. */
/* RETURN (RETT in V8) */
#define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
/* Fetch the instruction at PC. Instructions are always big-endian
even if the processor operates in little-endian mode. */
unsigned long
sparc_fetch_instruction (CORE_ADDR pc)
{
gdb_byte buf[4];
unsigned long insn;
int i;
/* If we can't read the instruction at PC, return zero. */
if (target_read_memory (pc, buf, sizeof (buf)))
return 0;
insn = 0;
for (i = 0; i < sizeof (buf); i++)
insn = (insn << 8) | buf[i];
return insn;
}
/* Return non-zero if the instruction corresponding to PC is an "unimp"
instruction. */
static int
sparc_is_unimp_insn (CORE_ADDR pc)
{
const unsigned long insn = sparc_fetch_instruction (pc);
return ((insn & 0xc1c00000) == 0);
}
/* Return non-zero if the instruction corresponding to PC is an
"annulled" branch, i.e. the annul bit is set. */
int
sparc_is_annulled_branch_insn (CORE_ADDR pc)
{
/* The branch instructions featuring an annul bit can be identified
by the following bit patterns:
OP=0
OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
OP2=2: Branch on Integer Condition Codes (Bcc).
OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
OP2=6: Branch on FP Condition Codes (FBcc).
OP2=3 && Bit28=0:
Branch on Integer Register with Prediction (BPr).
This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
coprocessor branch instructions (Op2=7). */
const unsigned long insn = sparc_fetch_instruction (pc);
const unsigned op2 = X_OP2 (insn);
if ((X_OP (insn) == 0)
&& ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6)
|| ((op2 == 3) && ((insn & 0x10000000) == 0))))
return X_A (insn);
else
return 0;
}
/* OpenBSD/sparc includes StackGhost, which according to the author's
website http://stackghost.cerias.purdue.edu "... transparently and
automatically protects applications' stack frames; more
specifically, it guards the return pointers. The protection
mechanisms require no application source or binary modification and
imposes only a negligible performance penalty."
The same website provides the following description of how
StackGhost works:
"StackGhost interfaces with the kernel trap handler that would
normally write out registers to the stack and the handler that
would read them back in. By XORing a cookie into the
return-address saved in the user stack when it is actually written
to the stack, and then XOR it out when the return-address is pulled
from the stack, StackGhost can cause attacker corrupted return
pointers to behave in a manner the attacker cannot predict.
StackGhost can also use several unused bits in the return pointer
to detect a smashed return pointer and abort the process."
For GDB this means that whenever we're reading %i7 from a stack
frame's window save area, we'll have to XOR the cookie.
More information on StackGuard can be found on in:
Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
Stack Protection." 2001. Published in USENIX Security Symposium
'01. */
/* Fetch StackGhost Per-Process XOR cookie. */
ULONGEST
sparc_fetch_wcookie (struct gdbarch *gdbarch)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
struct target_ops *ops = ¤t_target;
gdb_byte buf[8];
int len;
len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
if (len == -1)
return 0;
/* We should have either an 32-bit or an 64-bit cookie. */
gdb_assert (len == 4 || len == 8);
return extract_unsigned_integer (buf, len, byte_order);
}
/* The functions on this page are intended to be used to classify
function arguments. */
/* Check whether TYPE is "Integral or Pointer". */
static int
sparc_integral_or_pointer_p (const struct type *type)
{
int len = TYPE_LENGTH (type);
switch (TYPE_CODE (type))
{
case TYPE_CODE_INT:
case TYPE_CODE_BOOL:
case TYPE_CODE_CHAR:
case TYPE_CODE_ENUM:
case TYPE_CODE_RANGE:
/* We have byte, half-word, word and extended-word/doubleword
integral types. The doubleword is an extension to the
original 32-bit ABI by the SCD 2.4.x. */
return (len == 1 || len == 2 || len == 4 || len == 8);
case TYPE_CODE_PTR:
case TYPE_CODE_REF:
/* Allow either 32-bit or 64-bit pointers. */
return (len == 4 || len == 8);
default:
break;
}
return 0;
}
/* Check whether TYPE is "Floating". */
static int
sparc_floating_p (const struct type *type)
{
switch (TYPE_CODE (type))
{
case TYPE_CODE_FLT:
{
int len = TYPE_LENGTH (type);
return (len == 4 || len == 8 || len == 16);
}
default:
break;
}
return 0;
}
/* Check whether TYPE is "Complex Floating". */
static int
sparc_complex_floating_p (const struct type *type)
{
switch (TYPE_CODE (type))
{
case TYPE_CODE_COMPLEX:
{
int len = TYPE_LENGTH (type);
return (len == 8 || len == 16 || len == 32);
}
default:
break;
}
return 0;
}
/* Check whether TYPE is "Structure or Union".
In terms of Ada subprogram calls, arrays are treated the same as
struct and union types. So this function also returns non-zero
for array types. */
static int
sparc_structure_or_union_p (const struct type *type)
{
switch (TYPE_CODE (type))
{
case TYPE_CODE_STRUCT:
case TYPE_CODE_UNION:
case TYPE_CODE_ARRAY:
return 1;
default:
break;
}
return 0;
}
/* Register information. */
static const char *sparc32_register_names[] =
{
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
"i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
};
/* Total number of registers. */
#define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
/* We provide the aliases %d0..%d30 for the floating registers as
"psuedo" registers. */
static const char *sparc32_pseudo_register_names[] =
{
"d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
"d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
};
/* Total number of pseudo registers. */
#define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
/* Return the name of register REGNUM. */
static const char *
sparc32_register_name (struct gdbarch *gdbarch, int regnum)
{
if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
return sparc32_register_names[regnum];
if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
return NULL;
}
/* Construct types for ISA-specific registers. */
static struct type *
sparc_psr_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (!tdep->sparc_psr_type)
{
struct type *type;
type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4);
append_flags_type_flag (type, 5, "ET");
append_flags_type_flag (type, 6, "PS");
append_flags_type_flag (type, 7, "S");
append_flags_type_flag (type, 12, "EF");
append_flags_type_flag (type, 13, "EC");
tdep->sparc_psr_type = type;
}
return tdep->sparc_psr_type;
}
static struct type *
sparc_fsr_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (!tdep->sparc_fsr_type)
{
struct type *type;
type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4);
append_flags_type_flag (type, 0, "NXA");
append_flags_type_flag (type, 1, "DZA");
append_flags_type_flag (type, 2, "UFA");
append_flags_type_flag (type, 3, "OFA");
append_flags_type_flag (type, 4, "NVA");
append_flags_type_flag (type, 5, "NXC");
append_flags_type_flag (type, 6, "DZC");
append_flags_type_flag (type, 7, "UFC");
append_flags_type_flag (type, 8, "OFC");
append_flags_type_flag (type, 9, "NVC");
append_flags_type_flag (type, 22, "NS");
append_flags_type_flag (type, 23, "NXM");
append_flags_type_flag (type, 24, "DZM");
append_flags_type_flag (type, 25, "UFM");
append_flags_type_flag (type, 26, "OFM");
append_flags_type_flag (type, 27, "NVM");
tdep->sparc_fsr_type = type;
}
return tdep->sparc_fsr_type;
}
/* Return the GDB type object for the "standard" data type of data in
register REGNUM. */
static struct type *
sparc32_register_type (struct gdbarch *gdbarch, int regnum)
{
if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
return builtin_type (gdbarch)->builtin_float;
if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
return builtin_type (gdbarch)->builtin_double;
if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
return builtin_type (gdbarch)->builtin_data_ptr;
if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
return builtin_type (gdbarch)->builtin_func_ptr;
if (regnum == SPARC32_PSR_REGNUM)
return sparc_psr_type (gdbarch);
if (regnum == SPARC32_FSR_REGNUM)
return sparc_fsr_type (gdbarch);
return builtin_type (gdbarch)->builtin_int32;
}
static enum register_status
sparc32_pseudo_register_read (struct gdbarch *gdbarch,
struct regcache *regcache,
int regnum, gdb_byte *buf)
{
enum register_status status;
gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
status = regcache_raw_read (regcache, regnum, buf);
if (status == REG_VALID)
status = regcache_raw_read (regcache, regnum + 1, buf + 4);
return status;
}
static void
sparc32_pseudo_register_write (struct gdbarch *gdbarch,
struct regcache *regcache,
int regnum, const gdb_byte *buf)
{
gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
regcache_raw_write (regcache, regnum, buf);
regcache_raw_write (regcache, regnum + 1, buf + 4);
}
/* Implement the stack_frame_destroyed_p gdbarch method. */
int
sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
/* This function must return true if we are one instruction after an
instruction that destroyed the stack frame of the current
function. The SPARC instructions used to restore the callers
stack frame are RESTORE and RETURN/RETT.
Of these RETURN/RETT is a branch instruction and thus we return
true if we are in its delay slot.
RESTORE is almost always found in the delay slot of a branch
instruction that transfers control to the caller, such as JMPL.
Thus the next instruction is in the caller frame and we don't
need to do anything about it. */
unsigned int insn = sparc_fetch_instruction (pc - 4);
return X_RETTURN (insn);
}
static CORE_ADDR
sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
{
/* The ABI requires double-word alignment. */
return address & ~0x7;
}
static CORE_ADDR
sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
CORE_ADDR funcaddr,
struct value **args, int nargs,
struct type *value_type,
CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
struct regcache *regcache)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
*bp_addr = sp - 4;
*real_pc = funcaddr;
if (using_struct_return (gdbarch, NULL, value_type))
{
gdb_byte buf[4];
/* This is an UNIMP instruction. */
store_unsigned_integer (buf, 4, byte_order,
TYPE_LENGTH (value_type) & 0x1fff);
write_memory (sp - 8, buf, 4);
return sp - 8;
}
return sp - 4;
}
static CORE_ADDR
sparc32_store_arguments (struct regcache *regcache, int nargs,
struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* Number of words in the "parameter array". */
int num_elements = 0;
int element = 0;
int i;
for (i = 0; i < nargs; i++)
{
struct type *type = value_type (args[i]);
int len = TYPE_LENGTH (type);
if (sparc_structure_or_union_p (type)
|| (sparc_floating_p (type) && len == 16)
|| sparc_complex_floating_p (type))
{
/* Structure, Union and Quad-Precision Arguments. */
sp -= len;
/* Use doubleword alignment for these values. That's always
correct, and wasting a few bytes shouldn't be a problem. */
sp &= ~0x7;
write_memory (sp, value_contents (args[i]), len);
args[i] = value_from_pointer (lookup_pointer_type (type), sp);
num_elements++;
}
else if (sparc_floating_p (type))
{
/* Floating arguments. */
gdb_assert (len == 4 || len == 8);
num_elements += (len / 4);
}
else
{
/* Integral and pointer arguments. */
gdb_assert (sparc_integral_or_pointer_p (type));
if (len < 4)
args[i] = value_cast (builtin_type (gdbarch)->builtin_int32,
args[i]);
num_elements += ((len + 3) / 4);
}
}
/* Always allocate at least six words. */
sp -= max (6, num_elements) * 4;
/* The psABI says that "Software convention requires space for the
struct/union return value pointer, even if the word is unused." */
sp -= 4;
/* The psABI says that "Although software convention and the
operating system require every stack frame to be doubleword
aligned." */
sp &= ~0x7;
for (i = 0; i < nargs; i++)
{
const bfd_byte *valbuf = value_contents (args[i]);
struct type *type = value_type (args[i]);
int len = TYPE_LENGTH (type);
gdb_assert (len == 4 || len == 8);
if (element < 6)
{
int regnum = SPARC_O0_REGNUM + element;
regcache_cooked_write (regcache, regnum, valbuf);
if (len > 4 && element < 5)
regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
}
/* Always store the argument in memory. */
write_memory (sp + 4 + element * 4, valbuf, len);
element += len / 4;
}
gdb_assert (element == num_elements);
if (struct_return)
{
gdb_byte buf[4];
store_unsigned_integer (buf, 4, byte_order, struct_addr);
write_memory (sp, buf, 4);
}
return sp;
}
static CORE_ADDR
sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
/* Set return address. */
regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
/* Set up function arguments. */
sp = sparc32_store_arguments (regcache, nargs, args, sp,
struct_return, struct_addr);
/* Allocate the 16-word window save area. */
sp -= 16 * 4;
/* Stack should be doubleword aligned at this point. */
gdb_assert (sp % 8 == 0);
/* Finally, update the stack pointer. */
regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
return sp;
}
/* Use the program counter to determine the contents and size of a
breakpoint instruction. Return a pointer to a string of bytes that
encode a breakpoint instruction, store the length of the string in
*LEN and optionally adjust *PC to point to the correct memory
location for inserting the breakpoint. */
static const gdb_byte *
sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
{
static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
*len = sizeof (break_insn);
return break_insn;
}
/* Allocate and initialize a frame cache. */
static struct sparc_frame_cache *
sparc_alloc_frame_cache (void)
{
struct sparc_frame_cache *cache;
cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
/* Base address. */
cache->base = 0;
cache->pc = 0;
/* Frameless until proven otherwise. */
cache->frameless_p = 1;
cache->frame_offset = 0;
cache->saved_regs_mask = 0;
cache->copied_regs_mask = 0;
cache->struct_return_p = 0;
return cache;
}
/* GCC generates several well-known sequences of instructions at the begining
of each function prologue when compiling with -fstack-check. If one of
such sequences starts at START_PC, then return the address of the
instruction immediately past this sequence. Otherwise, return START_PC. */
static CORE_ADDR
sparc_skip_stack_check (const CORE_ADDR start_pc)
{
CORE_ADDR pc = start_pc;
unsigned long insn;
int offset_stack_checking_sequence = 0;
int probing_loop = 0;
/* With GCC, all stack checking sequences begin with the same two
instructions, plus an optional one in the case of a probing loop:
sethi <some immediate>, %g1
sub %sp, %g1, %g1
or:
sethi <some immediate>, %g1
sethi <some immediate>, %g4
sub %sp, %g1, %g1
or:
sethi <some immediate>, %g1
sub %sp, %g1, %g1
sethi <some immediate>, %g4
If the optional instruction is found (setting g4), assume that a
probing loop will follow. */
/* sethi <some immediate>, %g1 */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
return start_pc;
/* optional: sethi <some immediate>, %g4 */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
{
probing_loop = 1;
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
}
/* sub %sp, %g1, %g1 */
if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
&& X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
return start_pc;
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
/* optional: sethi <some immediate>, %g4 */
if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
{
probing_loop = 1;
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
}
/* First possible sequence:
[first two instructions above]
clr [%g1 - some immediate] */
/* clr [%g1 - some immediate] */
if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
&& X_RS1 (insn) == 1 && X_RD (insn) == 0)
{
/* Valid stack-check sequence, return the new PC. */
return pc;
}
/* Second possible sequence: A small number of probes.
[first two instructions above]
clr [%g1]
add %g1, -<some immediate>, %g1
clr [%g1]
[repeat the two instructions above any (small) number of times]
clr [%g1 - some immediate] */
/* clr [%g1] */
else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
&& X_RS1 (insn) == 1 && X_RD (insn) == 0)
{
while (1)
{
/* add %g1, -<some immediate>, %g1 */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
&& X_RS1 (insn) == 1 && X_RD (insn) == 1))
break;
/* clr [%g1] */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
&& X_RD (insn) == 0 && X_RS1 (insn) == 1))
return start_pc;
}
/* clr [%g1 - some immediate] */
if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
&& X_RS1 (insn) == 1 && X_RD (insn) == 0))
return start_pc;
/* We found a valid stack-check sequence, return the new PC. */
return pc;
}
/* Third sequence: A probing loop.
[first three instructions above]
sub %g1, %g4, %g4
cmp %g1, %g4
be <disp>
add %g1, -<some immediate>, %g1
ba <disp>
clr [%g1]
And an optional last probe for the remainder:
clr [%g4 - some immediate] */
if (probing_loop)
{
/* sub %g1, %g4, %g4 */
if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
&& X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
return start_pc;
/* cmp %g1, %g4 */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
&& X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
return start_pc;
/* be <disp> */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
return start_pc;
/* add %g1, -<some immediate>, %g1 */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
&& X_RS1 (insn) == 1 && X_RD (insn) == 1))
return start_pc;
/* ba <disp> */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
return start_pc;
/* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4
&& X_RD (insn) == 0 && X_RS1 (insn) == 1
&& (!X_I(insn) || X_SIMM13 (insn) == 0)))
return start_pc;
/* We found a valid stack-check sequence, return the new PC. */
/* optional: clr [%g4 - some immediate] */
insn = sparc_fetch_instruction (pc);
pc = pc + 4;
if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
&& X_RS1 (insn) == 4 && X_RD (insn) == 0))
return pc - 4;
else
return pc;
}
/* No stack check code in our prologue, return the start_pc. */
return start_pc;
}
/* Record the effect of a SAVE instruction on CACHE. */
void
sparc_record_save_insn (struct sparc_frame_cache *cache)
{
/* The frame is set up. */
cache->frameless_p = 0;
/* The frame pointer contains the CFA. */
cache->frame_offset = 0;
/* The `local' and `in' registers are all saved. */
cache->saved_regs_mask = 0xffff;
/* The `out' registers are all renamed. */
cache->copied_regs_mask = 0xff;
}
/* Do a full analysis of the prologue at PC and update CACHE accordingly.
Bail out early if CURRENT_PC is reached. Return the address where
the analysis stopped.
We handle both the traditional register window model and the single
register window (aka flat) model. */
CORE_ADDR
sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
CORE_ADDR current_pc, struct sparc_frame_cache *cache)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
unsigned long insn;
int offset = 0;
int dest = -1;
pc = sparc_skip_stack_check (pc);
if (current_pc <= pc)
return current_pc;
/* We have to handle to "Procedure Linkage Table" (PLT) special. On
SPARC the linker usually defines a symbol (typically
_PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
This symbol makes us end up here with PC pointing at the start of
the PLT and CURRENT_PC probably pointing at a PLT entry. If we
would do our normal prologue analysis, we would probably conclude
that we've got a frame when in reality we don't, since the
dynamic linker patches up the first PLT with some code that
starts with a SAVE instruction. Patch up PC such that it points
at the start of our PLT entry. */
if (tdep->plt_entry_size > 0 && in_plt_section (current_pc))
pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
insn = sparc_fetch_instruction (pc);
/* Recognize store insns and record their sources. */
while (X_OP (insn) == 3
&& (X_OP3 (insn) == 0x4 /* stw */
|| X_OP3 (insn) == 0x7 /* std */
|| X_OP3 (insn) == 0xe) /* stx */
&& X_RS1 (insn) == SPARC_SP_REGNUM)
{
int regnum = X_RD (insn);
/* Recognize stores into the corresponding stack slots. */
if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
&& ((X_I (insn)
&& X_SIMM13 (insn) == (X_OP3 (insn) == 0xe
? (regnum - SPARC_L0_REGNUM) * 8 + BIAS
: (regnum - SPARC_L0_REGNUM) * 4))
|| (!X_I (insn) && regnum == SPARC_L0_REGNUM)))
{
cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM));
if (X_OP3 (insn) == 0x7)
cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM));
}
offset += 4;
insn = sparc_fetch_instruction (pc + offset);
}
/* Recognize a SETHI insn and record its destination. */
if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
{
dest = X_RD (insn);
offset += 4;
insn = sparc_fetch_instruction (pc + offset);
}
/* Allow for an arithmetic operation on DEST or %g1. */
if (X_OP (insn) == 2 && X_I (insn)
&& (X_RD (insn) == 1 || X_RD (insn) == dest))
{
offset += 4;
insn = sparc_fetch_instruction (pc + offset);
}
/* Check for the SAVE instruction that sets up the frame. */
if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
{
sparc_record_save_insn (cache);
offset += 4;
return pc + offset;
}
/* Check for an arithmetic operation on %sp. */
if (X_OP (insn) == 2
&& (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
&& X_RS1 (insn) == SPARC_SP_REGNUM
&& X_RD (insn) == SPARC_SP_REGNUM)
{
if (X_I (insn))
{
cache->frame_offset = X_SIMM13 (insn);
if (X_OP3 (insn) == 0)
cache->frame_offset = -cache->frame_offset;
}
offset += 4;
insn = sparc_fetch_instruction (pc + offset);
/* Check for an arithmetic operation that sets up the frame. */
if (X_OP (insn) == 2
&& (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
&& X_RS1 (insn) == SPARC_SP_REGNUM
&& X_RD (insn) == SPARC_FP_REGNUM)
{
cache->frameless_p = 0;
cache->frame_offset = 0;
/* We could check that the amount subtracted to %sp above is the
same as the one added here, but this seems superfluous. */
cache->copied_regs_mask |= 0x40;
offset += 4;
insn = sparc_fetch_instruction (pc + offset);
}