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sh64-tdep.c
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/* Target-dependent code for Renesas Super-H, for GDB.
Copyright (C) 1993-2015 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Contributed by Steve Chamberlain
#include "defs.h"
#include "frame.h"
#include "frame-base.h"
#include "frame-unwind.h"
#include "dwarf2-frame.h"
#include "symtab.h"
#include "gdbtypes.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "value.h"
#include "dis-asm.h"
#include "inferior.h"
#include "arch-utils.h"
#include "regcache.h"
#include "osabi.h"
#include "valprint.h"
#include "elf-bfd.h"
/* sh flags */
#include "elf/sh.h"
/* Register numbers shared with the simulator. */
#include "gdb/sim-sh.h"
#include "language.h"
#include "sh64-tdep.h"
/* Information that is dependent on the processor variant. */
enum sh_abi
{
SH_ABI_UNKNOWN,
SH_ABI_32,
SH_ABI_64
};
struct gdbarch_tdep
{
enum sh_abi sh_abi;
};
struct sh64_frame_cache
{
/* Base address. */
CORE_ADDR base;
LONGEST sp_offset;
CORE_ADDR pc;
/* Flag showing that a frame has been created in the prologue code. */
int uses_fp;
int media_mode;
/* Saved registers. */
CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
CORE_ADDR saved_sp;
};
/* Registers of SH5 */
enum
{
R0_REGNUM = 0,
DEFAULT_RETURN_REGNUM = 2,
STRUCT_RETURN_REGNUM = 2,
ARG0_REGNUM = 2,
ARGLAST_REGNUM = 9,
FLOAT_ARGLAST_REGNUM = 11,
MEDIA_FP_REGNUM = 14,
PR_REGNUM = 18,
SR_REGNUM = 65,
DR0_REGNUM = 141,
DR_LAST_REGNUM = 172,
/* FPP stands for Floating Point Pair, to avoid confusion with
GDB's gdbarch_fp0_regnum, which is the number of the first Floating
point register. Unfortunately on the sh5, the floating point
registers are called FR, and the floating point pairs are called FP. */
FPP0_REGNUM = 173,
FPP_LAST_REGNUM = 204,
FV0_REGNUM = 205,
FV_LAST_REGNUM = 220,
R0_C_REGNUM = 221,
R_LAST_C_REGNUM = 236,
PC_C_REGNUM = 237,
GBR_C_REGNUM = 238,
MACH_C_REGNUM = 239,
MACL_C_REGNUM = 240,
PR_C_REGNUM = 241,
T_C_REGNUM = 242,
FPSCR_C_REGNUM = 243,
FPUL_C_REGNUM = 244,
FP0_C_REGNUM = 245,
FP_LAST_C_REGNUM = 260,
DR0_C_REGNUM = 261,
DR_LAST_C_REGNUM = 268,
FV0_C_REGNUM = 269,
FV_LAST_C_REGNUM = 272,
FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
SSR_REGNUM = SIM_SH64_SSR_REGNUM,
SPC_REGNUM = SIM_SH64_SPC_REGNUM,
TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
};
static const char *
sh64_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] =
{
/* SH MEDIA MODE (ISA 32) */
/* general registers (64-bit) 0-63 */
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
/* pc (64-bit) 64 */
"pc",
/* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
"sr", "ssr", "spc",
/* target registers (64-bit) 68-75 */
"tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
/* floating point state control register (32-bit) 76 */
"fpscr",
/* single precision floating point registers (32-bit) 77-140 */
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
"fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
"fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
"fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
"fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
/* double precision registers (pseudo) 141-172 */
"dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
"dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
"dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
"dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
/* floating point pairs (pseudo) 173-204 */
"fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
"fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
"fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
"fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
/* floating point vectors (4 floating point regs) (pseudo) 205-220 */
"fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
"fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
/* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
"r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
"r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
"pc_c",
"gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
"fpscr_c", "fpul_c",
"fr0_c", "fr1_c", "fr2_c", "fr3_c",
"fr4_c", "fr5_c", "fr6_c", "fr7_c",
"fr8_c", "fr9_c", "fr10_c", "fr11_c",
"fr12_c", "fr13_c", "fr14_c", "fr15_c",
"dr0_c", "dr2_c", "dr4_c", "dr6_c",
"dr8_c", "dr10_c", "dr12_c", "dr14_c",
"fv0_c", "fv4_c", "fv8_c", "fv12_c",
/* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
#define NUM_PSEUDO_REGS_SH_MEDIA 80
#define NUM_PSEUDO_REGS_SH_COMPACT 51
/* Macros and functions for setting and testing a bit in a minimal
symbol that marks it as 32-bit function. The MSB of the minimal
symbol's "info" field is used for this purpose.
gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
i.e. refers to a 32-bit function, and sets a "special" bit in a
minimal symbol to mark it as a 32-bit function
MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
#define MSYMBOL_IS_SPECIAL(msym) \
MSYMBOL_TARGET_FLAG_1 (msym)
static void
sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
{
if (msym == NULL)
return;
if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
{
MSYMBOL_TARGET_FLAG_1 (msym) = 1;
SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
}
}
/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
are some macros to test, set, or clear bit 0 of addresses. */
#define IS_ISA32_ADDR(addr) ((addr) & 1)
#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
static int
pc_is_isa32 (bfd_vma memaddr)
{
struct bound_minimal_symbol sym;
/* If bit 0 of the address is set, assume this is a
ISA32 (shmedia) address. */
if (IS_ISA32_ADDR (memaddr))
return 1;
/* A flag indicating that this is a ISA32 function is stored by elfread.c in
the high bit of the info field. Use this to decide if the function is
ISA16 or ISA32. */
sym = lookup_minimal_symbol_by_pc (memaddr);
if (sym.minsym)
return MSYMBOL_IS_SPECIAL (sym.minsym);
else
return 0;
}
static const unsigned char *
sh64_breakpoint_from_pc (struct gdbarch *gdbarch,
CORE_ADDR *pcptr, int *lenptr)
{
/* The BRK instruction for shmedia is
01101111 11110101 11111111 11110000
which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
/* The BRK instruction for shcompact is
00000000 00111011
which translates in big endian mode to 0x0, 0x3b
and in little endian mode to 0x3b, 0x0 */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
if (pc_is_isa32 (*pcptr))
{
static unsigned char big_breakpoint_media[] = {
0x6f, 0xf5, 0xff, 0xf0
};
*pcptr = UNMAKE_ISA32_ADDR (*pcptr);
*lenptr = sizeof (big_breakpoint_media);
return big_breakpoint_media;
}
else
{
static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
*lenptr = sizeof (big_breakpoint_compact);
return big_breakpoint_compact;
}
}
else
{
if (pc_is_isa32 (*pcptr))
{
static unsigned char little_breakpoint_media[] = {
0xf0, 0xff, 0xf5, 0x6f
};
*pcptr = UNMAKE_ISA32_ADDR (*pcptr);
*lenptr = sizeof (little_breakpoint_media);
return little_breakpoint_media;
}
else
{
static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
*lenptr = sizeof (little_breakpoint_compact);
return little_breakpoint_compact;
}
}
}
/* Prologue looks like
[mov.l <regs>,@-r15]...
[sts.l pr,@-r15]
[mov.l r14,@-r15]
[mov r15,r14]
Actually it can be more complicated than this. For instance, with
newer gcc's:
mov.l r14,@-r15
add #-12,r15
mov r15,r14
mov r4,r1
mov r5,r2
mov.l r6,@(4,r14)
mov.l r7,@(8,r14)
mov.b r1,@r14
mov r14,r1
mov r14,r1
add #2,r1
mov.w r2,@r1
*/
/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
with l=1 and n = 18 0110101111110001010010100aaa0000 */
#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
/* STS.L PR,@-r0 0100000000100010
r0-4-->r0, PR-->(r0) */
#define IS_STS_R0(x) ((x) == 0x4022)
/* STS PR, Rm 0000mmmm00101010
PR-->Rm */
#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
Rm-->(dispx4+r15) */
#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
/* MOV.L R14,@(disp,r15) 000111111110dddd
R14-->(dispx4+r15) */
#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
R18-->(dispx8+R14) */
#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
R18-->(dispx8+R15) */
#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
R18-->(dispx4+R15) */
#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
R14-->(dispx8+R15) */
#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
R14-->(dispx4+R15) */
#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
R15 + imm --> R15 */
#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
R15 + imm --> R15 */
#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
R15 + R63 --> R14 */
#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
R15 + R63 --> R14 */
#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
#define IS_MOV_SP_FP_MEDIA(x) \
(IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
/* MOV #imm, R0 1110 0000 ssss ssss
#imm-->R0 */
#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
/* ADD r15,r0 0011 0000 1111 1100
r15+r0-->r0 */
#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
/* MOV.L R14 @-R0 0010 0000 1110 0110
R14-->(R0-4), R0-4-->R0 */
#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
where Rm is one of r2-r9 which are the argument registers. */
/* FIXME: Recognize the float and double register moves too! */
#define IS_MEDIA_IND_ARG_MOV(x) \
((((x) & 0xfc0ffc0f) == 0x0009fc00) \
&& (((x) & 0x03f00000) >= 0x00200000 \
&& ((x) & 0x03f00000) <= 0x00900000))
/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
where Rm is one of r2-r9 which are the argument registers. */
#define IS_MEDIA_ARG_MOV(x) \
(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
&& (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
#define IS_MEDIA_MOV_TO_R14(x) \
((((x) & 0xfffffc0f) == 0xa0e00000) \
|| (((x) & 0xfffffc0f) == 0xa4e00000) \
|| (((x) & 0xfffffc0f) == 0xa8e00000) \
|| (((x) & 0xfffffc0f) == 0xb4e00000) \
|| (((x) & 0xfffffc0f) == 0xbce00000))
/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
where Rm is r2-r9 */
#define IS_COMPACT_IND_ARG_MOV(x) \
((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
&& (((x) & 0x00f0) <= 0x0090))
/* compact direct arg move!
MOV.L Rn, @r14 0010 1110 mmmm 0010 */
#define IS_COMPACT_ARG_MOV(x) \
(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
&& ((x) & 0x00f0) <= 0x0090))
/* MOV.B Rm, @R14 0010 1110 mmmm 0000
MOV.W Rm, @R14 0010 1110 mmmm 0001 */
#define IS_COMPACT_MOV_TO_R14(x) \
((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
#define IS_JSR_R0(x) ((x) == 0x400b)
#define IS_NOP(x) ((x) == 0x0009)
/* MOV r15,r14 0110111011110011
r15-->r14 */
#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
/* ADD #imm,r15 01111111iiiiiiii
r15+imm-->r15 */
#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
/* Skip any prologue before the guts of a function. */
/* Skip the prologue using the debug information. If this fails we'll
fall back on the 'guess' method below. */
static CORE_ADDR
after_prologue (CORE_ADDR pc)
{
struct symtab_and_line sal;
CORE_ADDR func_addr, func_end;
/* If we can not find the symbol in the partial symbol table, then
there is no hope we can determine the function's start address
with this code. */
if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
return 0;
/* Get the line associated with FUNC_ADDR. */
sal = find_pc_line (func_addr, 0);
/* There are only two cases to consider. First, the end of the source line
is within the function bounds. In that case we return the end of the
source line. Second is the end of the source line extends beyond the
bounds of the current function. We need to use the slow code to
examine instructions in that case. */
if (sal.end < func_end)
return sal.end;
else
return 0;
}
static CORE_ADDR
look_for_args_moves (struct gdbarch *gdbarch,
CORE_ADDR start_pc, int media_mode)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR here, end;
int w;
int insn_size = (media_mode ? 4 : 2);
for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
{
if (media_mode)
{
w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
insn_size, byte_order);
here += insn_size;
if (IS_MEDIA_IND_ARG_MOV (w))
{
/* This must be followed by a store to r14, so the argument
is where the debug info says it is. This can happen after
the SP has been saved, unfortunately. */
int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
insn_size, byte_order);
here += insn_size;
if (IS_MEDIA_MOV_TO_R14 (next_insn))
start_pc = here;
}
else if (IS_MEDIA_ARG_MOV (w))
{
/* These instructions store directly the argument in r14. */
start_pc = here;
}
else
break;
}
else
{
w = read_memory_integer (here, insn_size, byte_order);
w = w & 0xffff;
here += insn_size;
if (IS_COMPACT_IND_ARG_MOV (w))
{
/* This must be followed by a store to r14, so the argument
is where the debug info says it is. This can happen after
the SP has been saved, unfortunately. */
int next_insn = 0xffff & read_memory_integer (here, insn_size,
byte_order);
here += insn_size;
if (IS_COMPACT_MOV_TO_R14 (next_insn))
start_pc = here;
}
else if (IS_COMPACT_ARG_MOV (w))
{
/* These instructions store directly the argument in r14. */
start_pc = here;
}
else if (IS_MOVL_R0 (w))
{
/* There is a function that gcc calls to get the arguments
passed correctly to the function. Only after this
function call the arguments will be found at the place
where they are supposed to be. This happens in case the
argument has to be stored into a 64-bit register (for
instance doubles, long longs). SHcompact doesn't have
access to the full 64-bits, so we store the register in
stack slot and store the address of the stack slot in
the register, then do a call through a wrapper that
loads the memory value into the register. A SHcompact
callee calls an argument decoder
(GCC_shcompact_incoming_args) that stores the 64-bit
value in a stack slot and stores the address of the
stack slot in the register. GCC thinks the argument is
just passed by transparent reference, but this is only
true after the argument decoder is called. Such a call
needs to be considered part of the prologue. */
/* This must be followed by a JSR @r0 instruction and by
a NOP instruction. After these, the prologue is over! */
int next_insn = 0xffff & read_memory_integer (here, insn_size,
byte_order);
here += insn_size;
if (IS_JSR_R0 (next_insn))
{
next_insn = 0xffff & read_memory_integer (here, insn_size,
byte_order);
here += insn_size;
if (IS_NOP (next_insn))
start_pc = here;
}
}
else
break;
}
}
return start_pc;
}
static CORE_ADDR
sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR here, end;
int updated_fp = 0;
int insn_size = 4;
int media_mode = 1;
if (!start_pc)
return 0;
if (pc_is_isa32 (start_pc) == 0)
{
insn_size = 2;
media_mode = 0;
}
for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
{
if (media_mode)
{
int w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
insn_size, byte_order);
here += insn_size;
if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
|| IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
|| IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w)
|| IS_PTABSL_R18 (w))
{
start_pc = here;
}
else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
{
start_pc = here;
updated_fp = 1;
}
else
if (updated_fp)
{
/* Don't bail out yet, we may have arguments stored in
registers here, according to the debug info, so that
gdb can print the frames correctly. */
start_pc = look_for_args_moves (gdbarch,
here - insn_size, media_mode);
break;
}
}
else
{
int w = 0xffff & read_memory_integer (here, insn_size, byte_order);
here += insn_size;
if (IS_STS_R0 (w) || IS_STS_PR (w)
|| IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
|| IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
{
start_pc = here;
}
else if (IS_MOV_SP_FP (w))
{
start_pc = here;
updated_fp = 1;
}
else
if (updated_fp)
{
/* Don't bail out yet, we may have arguments stored in
registers here, according to the debug info, so that
gdb can print the frames correctly. */
start_pc = look_for_args_moves (gdbarch,
here - insn_size, media_mode);
break;
}
}
}
return start_pc;
}
static CORE_ADDR
sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR post_prologue_pc;
/* See if we can determine the end of the prologue via the symbol table.
If so, then return either PC, or the PC after the prologue, whichever
is greater. */
post_prologue_pc = after_prologue (pc);
/* If after_prologue returned a useful address, then use it. Else
fall back on the instruction skipping code. */
if (post_prologue_pc != 0)
return max (pc, post_prologue_pc);
else
return sh64_skip_prologue_hard_way (gdbarch, pc);
}
/* Should call_function allocate stack space for a struct return? */
static int
sh64_use_struct_convention (struct type *type)
{
return (TYPE_LENGTH (type) > 8);
}
/* For vectors of 4 floating point registers. */
static int
sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
{
int fp_regnum;
fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4;
return fp_regnum;
}
/* For double precision floating point registers, i.e 2 fp regs. */
static int
sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
{
int fp_regnum;
fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2;
return fp_regnum;
}
/* For pairs of floating point registers. */
static int
sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum)
{
int fp_regnum;
fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2;
return fp_regnum;
}
/* *INDENT-OFF* */
/*
SH COMPACT MODE (ISA 16) (all pseudo) 221-272
GDB_REGNUM BASE_REGNUM
r0_c 221 0
r1_c 222 1
r2_c 223 2
r3_c 224 3
r4_c 225 4
r5_c 226 5
r6_c 227 6
r7_c 228 7
r8_c 229 8
r9_c 230 9
r10_c 231 10
r11_c 232 11
r12_c 233 12
r13_c 234 13
r14_c 235 14
r15_c 236 15
pc_c 237 64
gbr_c 238 16
mach_c 239 17
macl_c 240 17
pr_c 241 18
t_c 242 19
fpscr_c 243 76
fpul_c 244 109
fr0_c 245 77
fr1_c 246 78
fr2_c 247 79
fr3_c 248 80
fr4_c 249 81
fr5_c 250 82
fr6_c 251 83
fr7_c 252 84
fr8_c 253 85
fr9_c 254 86
fr10_c 255 87
fr11_c 256 88
fr12_c 257 89
fr13_c 258 90
fr14_c 259 91
fr15_c 260 92
dr0_c 261 77
dr2_c 262 79
dr4_c 263 81
dr6_c 264 83
dr8_c 265 85
dr10_c 266 87
dr12_c 267 89
dr14_c 268 91
fv0_c 269 77
fv4_c 270 81
fv8_c 271 85
fv12_c 272 91
*/
/* *INDENT-ON* */
static int
sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr)
{
int base_regnum = reg_nr;
/* general register N maps to general register N */
if (reg_nr >= R0_C_REGNUM
&& reg_nr <= R_LAST_C_REGNUM)
base_regnum = reg_nr - R0_C_REGNUM;
/* floating point register N maps to floating point register N */
else if (reg_nr >= FP0_C_REGNUM
&& reg_nr <= FP_LAST_C_REGNUM)
base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch);
/* double prec register N maps to base regnum for double prec register N */
else if (reg_nr >= DR0_C_REGNUM
&& reg_nr <= DR_LAST_C_REGNUM)
base_regnum = sh64_dr_reg_base_num (gdbarch,
DR0_REGNUM + reg_nr - DR0_C_REGNUM);
/* vector N maps to base regnum for vector register N */
else if (reg_nr >= FV0_C_REGNUM
&& reg_nr <= FV_LAST_C_REGNUM)
base_regnum = sh64_fv_reg_base_num (gdbarch,
FV0_REGNUM + reg_nr - FV0_C_REGNUM);
else if (reg_nr == PC_C_REGNUM)
base_regnum = gdbarch_pc_regnum (gdbarch);
else if (reg_nr == GBR_C_REGNUM)
base_regnum = 16;
else if (reg_nr == MACH_C_REGNUM
|| reg_nr == MACL_C_REGNUM)
base_regnum = 17;
else if (reg_nr == PR_C_REGNUM)
base_regnum = PR_REGNUM;
else if (reg_nr == T_C_REGNUM)
base_regnum = 19;
else if (reg_nr == FPSCR_C_REGNUM)
base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
else if (reg_nr == FPUL_C_REGNUM)
base_regnum = gdbarch_fp0_regnum (gdbarch) + 32;
return base_regnum;
}
static int
sign_extend (int value, int bits)
{
value = value & ((1 << bits) - 1);
return (value & (1 << (bits - 1))
? value | (~((1 << bits) - 1))
: value);
}
static void
sh64_analyze_prologue (struct gdbarch *gdbarch,
struct sh64_frame_cache *cache,
CORE_ADDR func_pc,
CORE_ADDR current_pc)
{
int pc;
int opc;
int insn;
int r0_val = 0;
int insn_size;
int gdb_register_number;
int register_number;
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
cache->sp_offset = 0;
/* Loop around examining the prologue insns until we find something
that does not appear to be part of the prologue. But give up
after 20 of them, since we're getting silly then. */
pc = func_pc;
if (cache->media_mode)
insn_size = 4;
else
insn_size = 2;
opc = pc + (insn_size * 28);
if (opc > current_pc)
opc = current_pc;
for ( ; pc <= opc; pc += insn_size)
{
insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
: pc,
insn_size, byte_order);
if (!cache->media_mode)
{
if (IS_STS_PR (insn))
{
int next_insn = read_memory_integer (pc + insn_size,
insn_size, byte_order);
if (IS_MOV_TO_R15 (next_insn))
{
cache->saved_regs[PR_REGNUM]
= cache->sp_offset - ((((next_insn & 0xf) ^ 0x8)
- 0x8) << 2);
pc += insn_size;
}
}
else if (IS_MOV_R14 (insn))
cache->saved_regs[MEDIA_FP_REGNUM] =
cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
else if (IS_MOV_R0 (insn))
{
/* Put in R0 the offset from SP at which to store some
registers. We are interested in this value, because it
will tell us where the given registers are stored within
the frame. */
r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
}
else if (IS_ADD_SP_R0 (insn))
{
/* This instruction still prepares r0, but we don't care.
We already have the offset in r0_val. */
}
else if (IS_STS_R0 (insn))
{
/* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
r0_val -= 4;
}
else if (IS_MOV_R14_R0 (insn))
{
/* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
- (r0_val - 4);
r0_val -= 4;
}
else if (IS_ADD_SP (insn))
cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
else if (IS_MOV_SP_FP (insn))
break;
}
else
{
if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
cache->sp_offset -=
sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
else if (IS_STQ_R18_R15 (insn))
cache->saved_regs[PR_REGNUM]
= cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
9) << 3);
else if (IS_STL_R18_R15 (insn))
cache->saved_regs[PR_REGNUM]
= cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
9) << 2);
else if (IS_STQ_R14_R15 (insn))
cache->saved_regs[MEDIA_FP_REGNUM]
= cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
9) << 3);
else if (IS_STL_R14_R15 (insn))
cache->saved_regs[MEDIA_FP_REGNUM]
= cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
9) << 2);
else if (IS_MOV_SP_FP_MEDIA (insn))
break;
}
}
if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0)
cache->uses_fp = 1;
}
static CORE_ADDR
sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
{
return sp & ~7;
}
/* Function: push_dummy_call
Setup the function arguments for calling a function in the inferior.
On the Renesas SH architecture, there are four registers (R4 to R7)
which are dedicated for passing function arguments. Up to the first
four arguments (depending on size) may go into these registers.
The rest go on the stack.
Arguments that are smaller than 4 bytes will still take up a whole
register or a whole 32-bit word on the stack, and will be
right-justified in the register or the stack word. This includes
chars, shorts, and small aggregate types.
Arguments that are larger than 4 bytes may be split between two or