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sh-tdep.c
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/* Target-dependent code for Renesas Super-H, for GDB.
Copyright (C) 1993-2015 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Contributed by Steve Chamberlain
#include "defs.h"
#include "frame.h"
#include "frame-base.h"
#include "frame-unwind.h"
#include "dwarf2-frame.h"
#include "symtab.h"
#include "gdbtypes.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "value.h"
#include "dis-asm.h"
#include "inferior.h"
#include "arch-utils.h"
#include "floatformat.h"
#include "regcache.h"
#include "doublest.h"
#include "osabi.h"
#include "reggroups.h"
#include "regset.h"
#include "objfiles.h"
#include "sh-tdep.h"
#include "sh64-tdep.h"
#include "elf-bfd.h"
#include "solib-svr4.h"
/* sh flags */
#include "elf/sh.h"
#include "dwarf2.h"
/* registers numbers shared with the simulator. */
#include "gdb/sim-sh.h"
/* List of "set sh ..." and "show sh ..." commands. */
static struct cmd_list_element *setshcmdlist = NULL;
static struct cmd_list_element *showshcmdlist = NULL;
static const char sh_cc_gcc[] = "gcc";
static const char sh_cc_renesas[] = "renesas";
static const char *const sh_cc_enum[] = {
sh_cc_gcc,
sh_cc_renesas,
NULL
};
static const char *sh_active_calling_convention = sh_cc_gcc;
#define SH_NUM_REGS 67
struct sh_frame_cache
{
/* Base address. */
CORE_ADDR base;
LONGEST sp_offset;
CORE_ADDR pc;
/* Flag showing that a frame has been created in the prologue code. */
int uses_fp;
/* Saved registers. */
CORE_ADDR saved_regs[SH_NUM_REGS];
CORE_ADDR saved_sp;
};
static int
sh_is_renesas_calling_convention (struct type *func_type)
{
int val = 0;
if (func_type)
{
func_type = check_typedef (func_type);
if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
&& TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
val = 1;
}
if (sh_active_calling_convention == sh_cc_renesas)
val = 1;
return val;
}
static const char *
sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"ssr", "spc",
"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
"", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"fpul", "fpscr",
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
"ssr", "spc",
"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
"", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"fpul", "fpscr",
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
"", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
/* general registers 0-15 */
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
/* 16 - 22 */
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
/* 23, 24 */
"fpul", "fpscr",
/* floating point registers 25 - 40 */
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
/* 41, 42 */
"", "",
/* 43 - 62. Banked registers. The bank number used is determined by
the bank register (63). */
"r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
"r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
"machb", "ivnb", "prb", "gbrb", "maclb",
/* 63: register bank number, not a real register but used to
communicate the register bank currently get/set. This register
is hidden to the user, who manipulates it using the pseudo
register called "bank" (67). See below. */
"",
/* 64 - 66 */
"ibcr", "ibnr", "tbr",
/* 67: register bank number, the user visible pseudo register. */
"bank",
/* double precision (pseudo) 68 - 75 */
"dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
/* general registers 0-15 */
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
/* 16 - 22 */
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
/* 23, 24 */
"", "",
/* floating point registers 25 - 40 */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
/* 41, 42 */
"", "",
/* 43 - 62. Banked registers. The bank number used is determined by
the bank register (63). */
"r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
"r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
"machb", "ivnb", "prb", "gbrb", "maclb",
/* 63: register bank number, not a real register but used to
communicate the register bank currently get/set. This register
is hidden to the user, who manipulates it using the pseudo
register called "bank" (67). See below. */
"",
/* 64 - 66 */
"ibcr", "ibnr", "tbr",
/* 67: register bank number, the user visible pseudo register. */
"bank",
/* double precision (pseudo) 68 - 75 */
"", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"", "dsr",
"a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
"y0", "y1", "", "", "", "", "", "mod",
"", "",
"rs", "re", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"", "dsr",
"a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
"y0", "y1", "", "", "", "", "", "mod",
"ssr", "spc",
"rs", "re", "", "", "", "", "", "",
"r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
/* general registers 0-15 */
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
/* 16 - 22 */
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
/* 23, 24 */
"fpul", "fpscr",
/* floating point registers 25 - 40 */
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
/* 41, 42 */
"ssr", "spc",
/* bank 0 43 - 50 */
"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
/* bank 1 51 - 58 */
"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
/* 59 - 66 */
"", "", "", "", "", "", "", "",
/* pseudo bank register. */
"",
/* double precision (pseudo) 68 - 75 */
"dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
/* vectors (pseudo) 76 - 79 */
"fv0", "fv4", "fv8", "fv12",
/* FIXME: missing XF */
/* FIXME: missing XD */
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
/* general registers 0-15 */
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
/* 16 - 22 */
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
/* 23, 24 */
"", "",
/* floating point registers 25 - 40 -- not for nofpu target */
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
/* 41, 42 */
"ssr", "spc",
/* bank 0 43 - 50 */
"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
/* bank 1 51 - 58 */
"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
/* 59 - 66 */
"", "", "", "", "", "", "", "",
/* pseudo bank register. */
"",
/* double precision (pseudo) 68 - 75 -- not for nofpu target */
"", "", "", "", "", "", "", "",
/* vectors (pseudo) 76 - 79 -- not for nofpu target */
"", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const char *
sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
{
static char *register_names[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
"", "dsr",
"a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
"y0", "y1", "", "", "", "", "", "mod",
"ssr", "spc",
"rs", "re", "", "", "", "", "", "",
"r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
};
if (reg_nr < 0)
return NULL;
if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
return NULL;
return register_names[reg_nr];
}
static const unsigned char *
sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
{
/* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
static unsigned char breakpoint[] = { 0xc3, 0xc3 };
/* For remote stub targets, trapa #20 is used. */
if (strcmp (target_shortname, "remote") == 0)
{
static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
*lenptr = sizeof (big_remote_breakpoint);
return big_remote_breakpoint;
}
else
{
*lenptr = sizeof (little_remote_breakpoint);
return little_remote_breakpoint;
}
}
*lenptr = sizeof (breakpoint);
return breakpoint;
}
/* Prologue looks like
mov.l r14,@-r15
sts.l pr,@-r15
mov.l <regs>,@-r15
sub <room_for_loca_vars>,r15
mov r15,r14
Actually it can be more complicated than this but that's it, basically. */
#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
/* JSR @Rm 0100mmmm00001011 */
#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
/* STS.L PR,@-r15 0100111100100010
r15-4-->r15, PR-->(r15) */
#define IS_STS(x) ((x) == 0x4f22)
/* STS.L MACL,@-r15 0100111100010010
r15-4-->r15, MACL-->(r15) */
#define IS_MACL_STS(x) ((x) == 0x4f12)
/* MOV.L Rm,@-r15 00101111mmmm0110
r15-4-->r15, Rm-->(R15) */
#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
/* MOV r15,r14 0110111011110011
r15-->r14 */
#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
/* ADD #imm,r15 01111111iiiiiiii
r15+imm-->r15 */
#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
#define IS_SHLL_R3(x) ((x) == 0x4300)
/* ADD r3,r15 0011111100111100
r15+r3-->r15 */
#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
make this entirely clear. */
/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
#define IS_MOV_ARG_TO_REG(x) \
(((x) & 0xf00f) == 0x6003 && \
((x) & 0x00f0) >= 0x0040 && \
((x) & 0x00f0) <= 0x0070)
/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
#define IS_MOV_ARG_TO_IND_R14(x) \
(((x) & 0xff0f) == 0x2e02 && \
((x) & 0x00f0) >= 0x0040 && \
((x) & 0x00f0) <= 0x0070)
/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
(((x) & 0xff00) == 0x1e00 && \
((x) & 0x00f0) >= 0x0040 && \
((x) & 0x00f0) <= 0x0070)
/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
/* SUB Rn,R15 00111111nnnn1000 */
#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
#define FPSCR_SZ (1 << 20)
/* The following instructions are used for epilogue testing. */
#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
#define IS_RTS(x) ((x) == 0x000b)
#define IS_LDS(x) ((x) == 0x4f26)
#define IS_MACL_LDS(x) ((x) == 0x4f16)
#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
static CORE_ADDR
sh_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR pc, CORE_ADDR limit_pc,
struct sh_frame_cache *cache, ULONGEST fpscr)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST inst;
int offset;
int sav_offset = 0;
int r3_val = 0;
int reg, sav_reg = -1;
cache->uses_fp = 0;
for (; pc < limit_pc; pc += 2)
{
inst = read_memory_unsigned_integer (pc, 2, byte_order);
/* See where the registers will be saved to. */
if (IS_PUSH (inst))
{
cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
cache->sp_offset += 4;
}
else if (IS_STS (inst))
{
cache->saved_regs[PR_REGNUM] = cache->sp_offset;
cache->sp_offset += 4;
}
else if (IS_MACL_STS (inst))
{
cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
cache->sp_offset += 4;
}
else if (IS_MOV_R3 (inst))
{
r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
}
else if (IS_SHLL_R3 (inst))
{
r3_val <<= 1;
}
else if (IS_ADD_R3SP (inst))
{
cache->sp_offset += -r3_val;
}
else if (IS_ADD_IMM_SP (inst))
{
offset = ((inst & 0xff) ^ 0x80) - 0x80;
cache->sp_offset -= offset;
}
else if (IS_MOVW_PCREL_TO_REG (inst))
{
if (sav_reg < 0)
{
reg = GET_TARGET_REG (inst);
if (reg < 14)
{
sav_reg = reg;
offset = (inst & 0xff) << 1;
sav_offset =
read_memory_integer ((pc + 4) + offset, 2, byte_order);
}
}
}
else if (IS_MOVL_PCREL_TO_REG (inst))
{
if (sav_reg < 0)
{
reg = GET_TARGET_REG (inst);
if (reg < 14)
{
sav_reg = reg;
offset = (inst & 0xff) << 2;
sav_offset =
read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
4, byte_order);
}
}
}
else if (IS_MOVI20 (inst)
&& (pc + 2 < limit_pc))
{
if (sav_reg < 0)
{
reg = GET_TARGET_REG (inst);
if (reg < 14)
{
sav_reg = reg;
sav_offset = GET_SOURCE_REG (inst) << 16;
/* MOVI20 is a 32 bit instruction! */
pc += 2;
sav_offset
|= read_memory_unsigned_integer (pc, 2, byte_order);
/* Now sav_offset contains an unsigned 20 bit value.
It must still get sign extended. */
if (sav_offset & 0x00080000)
sav_offset |= 0xfff00000;
}
}
}
else if (IS_SUB_REG_FROM_SP (inst))
{
reg = GET_SOURCE_REG (inst);
if (sav_reg > 0 && reg == sav_reg)
{
sav_reg = -1;
}
cache->sp_offset += sav_offset;
}
else if (IS_FPUSH (inst))
{
if (fpscr & FPSCR_SZ)
{
cache->sp_offset += 8;
}
else
{
cache->sp_offset += 4;
}
}
else if (IS_MOV_SP_FP (inst))
{
pc += 2;
/* Don't go any further than six more instructions. */
limit_pc = min (limit_pc, pc + (2 * 6));
cache->uses_fp = 1;
/* At this point, only allow argument register moves to other
registers or argument register moves to @(X,fp) which are
moving the register arguments onto the stack area allocated
by a former add somenumber to SP call. Don't allow moving
to an fp indirect address above fp + cache->sp_offset. */
for (; pc < limit_pc; pc += 2)
{
inst = read_memory_integer (pc, 2, byte_order);
if (IS_MOV_ARG_TO_IND_R14 (inst))
{
reg = GET_SOURCE_REG (inst);
if (cache->sp_offset > 0)
cache->saved_regs[reg] = cache->sp_offset;
}
else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
{
reg = GET_SOURCE_REG (inst);
offset = (inst & 0xf) * 4;
if (cache->sp_offset > offset)
cache->saved_regs[reg] = cache->sp_offset - offset;
}
else if (IS_MOV_ARG_TO_REG (inst))
continue;
else
break;
}
break;
}
else if (IS_JSR (inst))
{
/* We have found a jsr that has been scheduled into the prologue.
If we continue the scan and return a pc someplace after this,
then setting a breakpoint on this function will cause it to
appear to be called after the function it is calling via the
jsr, which will be very confusing. Most likely the next
instruction is going to be IS_MOV_SP_FP in the delay slot. If
so, note that before returning the current pc. */
if (pc + 2 < limit_pc)
{
inst = read_memory_integer (pc + 2, 2, byte_order);
if (IS_MOV_SP_FP (inst))
cache->uses_fp = 1;
}
break;
}
#if 0 /* This used to just stop when it found an instruction
that was not considered part of the prologue. Now,
we just keep going looking for likely
instructions. */
else
break;
#endif
}
return pc;
}
/* Skip any prologue before the guts of a function. */
static CORE_ADDR
sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc;
struct sh_frame_cache cache;
/* See if we can determine the end of the prologue via the symbol table.
If so, then return either PC, or the PC after the prologue, whichever
is greater. */
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
{
post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr);
if (post_prologue_pc != 0)
return max (pc, post_prologue_pc);
}
/* Can't determine prologue from the symbol table, need to examine
instructions. */
/* Find an upper limit on the function prologue using the debug
information. If the debug information could not be used to provide
that bound, then use an arbitrary large number as the upper bound. */
limit_pc = skip_prologue_using_sal (gdbarch, pc);
if (limit_pc == 0)
/* Don't go any further than 28 instructions. */
limit_pc = pc + (2 * 28);
/* Do not allow limit_pc to be past the function end, if we know
where that end is... */
if (func_end_addr != 0)
limit_pc = min (limit_pc, func_end_addr);
cache.sp_offset = -4;
post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0);
if (cache.uses_fp)
pc = post_prologue_pc;
return pc;
}
/* The ABI says:
Aggregate types not bigger than 8 bytes that have the same size and
alignment as one of the integer scalar types are returned in the
same registers as the integer type they match.
For example, a 2-byte aligned structure with size 2 bytes has the
same size and alignment as a short int, and will be returned in R0.
A 4-byte aligned structure with size 8 bytes has the same size and
alignment as a long long int, and will be returned in R0 and R1.
When an aggregate type is returned in R0 and R1, R0 contains the
first four bytes of the aggregate, and R1 contains the
remainder. If the size of the aggregate type is not a multiple of 4
bytes, the aggregate is tail-padded up to a multiple of 4
bytes. The value of the padding is undefined. For little-endian
targets the padding will appear at the most significant end of the
last element, for big-endian targets the padding appears at the
least significant end of the last element.
All other aggregate types are returned by address. The caller
function passes the address of an area large enough to hold the
aggregate value in R2. The called function stores the result in
this location.
To reiterate, structs smaller than 8 bytes could also be returned
in memory, if they don't pass the "same size and alignment as an
integer type" rule.
For example, in
struct s { char c[3]; } wibble;
struct s foo(void) { return wibble; }
the return value from foo() will be in memory, not
in R0, because there is no 3-byte integer type.
Similarly, in
struct s { char c[2]; } wibble;
struct s foo(void) { return wibble; }
because a struct containing two chars has alignment 1, that matches
type char, but size 2, that matches type short. There's no integer
type that has alignment 1 and size 2, so the struct is returned in
memory. */
static int
sh_use_struct_convention (int renesas_abi, struct type *type)
{
int len = TYPE_LENGTH (type);
int nelem = TYPE_NFIELDS (type);
/* The Renesas ABI returns aggregate types always on stack. */
if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION))
return 1;
/* Non-power of 2 length types and types bigger than 8 bytes (which don't
fit in two registers anyway) use struct convention. */
if (len != 1 && len != 2 && len != 4 && len != 8)
return 1;
/* Scalar types and aggregate types with exactly one field are aligned
by definition. They are returned in registers. */
if (nelem <= 1)
return 0;
/* If the first field in the aggregate has the same length as the entire
aggregate type, the type is returned in registers. */
if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
return 0;
/* If the size of the aggregate is 8 bytes and the first field is
of size 4 bytes its alignment is equal to long long's alignment,
so it's returned in registers. */
if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
return 0;
/* Otherwise use struct convention. */
return 1;
}
static int
sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
{
/* The Renesas ABI returns long longs/doubles etc. always on stack. */
if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
return 1;
return sh_use_struct_convention (renesas_abi, type);
}
static CORE_ADDR
sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
{
return sp & ~3;
}
/* Function: push_dummy_call (formerly push_arguments)
Setup the function arguments for calling a function in the inferior.
On the Renesas SH architecture, there are four registers (R4 to R7)
which are dedicated for passing function arguments. Up to the first
four arguments (depending on size) may go into these registers.
The rest go on the stack.
MVS: Except on SH variants that have floating point registers.
In that case, float and double arguments are passed in the same
manner, but using FP registers instead of GP registers.
Arguments that are smaller than 4 bytes will still take up a whole
register or a whole 32-bit word on the stack, and will be
right-justified in the register or the stack word. This includes
chars, shorts, and small aggregate types.
Arguments that are larger than 4 bytes may be split between two or
more registers. If there are not enough registers free, an argument
may be passed partly in a register (or registers), and partly on the
stack. This includes doubles, long longs, and larger aggregates.
As far as I know, there is no upper limit to the size of aggregates
that will be passed in this way; in other words, the convention of
passing a pointer to a large aggregate instead of a copy is not used.
MVS: The above appears to be true for the SH variants that do not
have an FPU, however those that have an FPU appear to copy the
aggregate argument onto the stack (and not place it in registers)
if it is larger than 16 bytes (four GP registers).
An exceptional case exists for struct arguments (and possibly other
aggregates such as arrays) if the size is larger than 4 bytes but
not a multiple of 4 bytes. In this case the argument is never split
between the registers and the stack, but instead is copied in its
entirety onto the stack, AND also copied into as many registers as
there is room for. In other words, space in registers permitting,
two copies of the same argument are passed in. As far as I can tell,
only the one on the stack is used, although that may be a function
of the level of compiler optimization. I suspect this is a compiler
bug. Arguments of these odd sizes are left-justified within the
word (as opposed to arguments smaller than 4 bytes, which are
right-justified).
If the function is to return an aggregate type such as a struct, it
is either returned in the normal return value register R0 (if its
size is no greater than one byte), or else the caller must allocate
space into which the callee will copy the return value (if the size
is greater than one byte). In this case, a pointer to the return
value location is passed into the callee in register R2, which does
not displace any of the other arguments passed in via registers R4
to R7. */
/* Helper function to justify value in register according to endianess. */
static const gdb_byte *
sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
{
static gdb_byte valbuf[4];
memset (valbuf, 0, sizeof (valbuf));
if (len < 4)
{
/* value gets right-justified in the register or stack word. */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
memcpy (valbuf + (4 - len), value_contents (val), len);
else
memcpy (valbuf, value_contents (val), len);
return valbuf;
}
return value_contents (val);
}
/* Helper function to eval number of bytes to allocate on stack. */
static CORE_ADDR
sh_stack_allocsize (int nargs, struct value **args)
{
int stack_alloc = 0;
while (nargs-- > 0)
stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
return stack_alloc;
}
/* Helper functions for getting the float arguments right. Registers usage
depends on the ABI and the endianess. The comments should enlighten how
it's intended to work. */
/* This array stores which of the float arg registers are already in use. */
static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
/* This function just resets the above array to "no reg used so far". */
static void
sh_init_flt_argreg (void)
{
memset (flt_argreg_array, 0, sizeof flt_argreg_array);
}
/* This function returns the next register to use for float arg passing.
It returns either a valid value between FLOAT_ARG0_REGNUM and
FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
Note that register number 0 in flt_argreg_array corresponds with the
real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
29) the parity of the register number is preserved, which is important
for the double register passing test (see the "argreg & 1" test below). */
static int
sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
{
int argreg;
/* First search for the next free register. */
for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
++argreg)
if (!flt_argreg_array[argreg])
break;
/* No register left? */
if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
return FLOAT_ARGLAST_REGNUM + 1;
if (len == 8)
{
/* Doubles are always starting in a even register number. */
if (argreg & 1)
{
/* In gcc ABI, the skipped register is lost for further argument
passing now. Not so in Renesas ABI. */
if (!sh_is_renesas_calling_convention (func_type))
flt_argreg_array[argreg] = 1;
++argreg;
/* No register left? */
if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
return FLOAT_ARGLAST_REGNUM + 1;
}
/* Also mark the next register as used. */
flt_argreg_array[argreg + 1] = 1;
}
else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
&& !sh_is_renesas_calling_convention (func_type))
{
/* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
if (!flt_argreg_array[argreg + 1])
++argreg;
}