forked from gbenson/binutils-gdb
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathrs6000-tdep.c
6272 lines (5464 loc) · 208 KB
/
rs6000-tdep.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* Target-dependent code for GDB, the GNU debugger.
Copyright (C) 1986-2015 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "inferior.h"
#include "infrun.h"
#include "symtab.h"
#include "target.h"
#include "gdbcore.h"
#include "gdbcmd.h"
#include "objfiles.h"
#include "arch-utils.h"
#include "regcache.h"
#include "regset.h"
#include "doublest.h"
#include "value.h"
#include "parser-defs.h"
#include "osabi.h"
#include "infcall.h"
#include "sim-regno.h"
#include "gdb/sim-ppc.h"
#include "reggroups.h"
#include "dwarf2-frame.h"
#include "target-descriptions.h"
#include "user-regs.h"
#include "record-full.h"
#include "auxv.h"
#include "libbfd.h" /* for bfd_default_set_arch_mach */
#include "coff/internal.h" /* for libcoff.h */
#include "libcoff.h" /* for xcoff_data */
#include "coff/xcoff.h"
#include "libxcoff.h"
#include "elf-bfd.h"
#include "elf/ppc.h"
#include "elf/ppc64.h"
#include "solib-svr4.h"
#include "ppc-tdep.h"
#include "ppc-ravenscar-thread.h"
#include "dis-asm.h"
#include "trad-frame.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "features/rs6000/powerpc-32.c"
#include "features/rs6000/powerpc-altivec32.c"
#include "features/rs6000/powerpc-vsx32.c"
#include "features/rs6000/powerpc-403.c"
#include "features/rs6000/powerpc-403gc.c"
#include "features/rs6000/powerpc-405.c"
#include "features/rs6000/powerpc-505.c"
#include "features/rs6000/powerpc-601.c"
#include "features/rs6000/powerpc-602.c"
#include "features/rs6000/powerpc-603.c"
#include "features/rs6000/powerpc-604.c"
#include "features/rs6000/powerpc-64.c"
#include "features/rs6000/powerpc-altivec64.c"
#include "features/rs6000/powerpc-vsx64.c"
#include "features/rs6000/powerpc-7400.c"
#include "features/rs6000/powerpc-750.c"
#include "features/rs6000/powerpc-860.c"
#include "features/rs6000/powerpc-e500.c"
#include "features/rs6000/rs6000.c"
/* Determine if regnum is an SPE pseudo-register. */
#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_ev0_regnum \
&& (regnum) < (tdep)->ppc_ev0_regnum + 32)
/* Determine if regnum is a decimal float pseudo-register. */
#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_dl0_regnum \
&& (regnum) < (tdep)->ppc_dl0_regnum + 16)
/* Determine if regnum is a POWER7 VSX register. */
#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_vsr0_regnum \
&& (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
/* Determine if regnum is a POWER7 Extended FP register. */
#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_efpr0_regnum \
&& (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
/* The list of available "set powerpc ..." and "show powerpc ..."
commands. */
static struct cmd_list_element *setpowerpccmdlist = NULL;
static struct cmd_list_element *showpowerpccmdlist = NULL;
static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
static const char *const powerpc_vector_strings[] =
{
"auto",
"generic",
"altivec",
"spe",
NULL
};
/* A variable that can be configured by the user. */
static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
static const char *powerpc_vector_abi_string = "auto";
/* To be used by skip_prologue. */
struct rs6000_framedata
{
int offset; /* total size of frame --- the distance
by which we decrement sp to allocate
the frame */
int saved_gpr; /* smallest # of saved gpr */
unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
int saved_fpr; /* smallest # of saved fpr */
int saved_vr; /* smallest # of saved vr */
int saved_ev; /* smallest # of saved ev */
int alloca_reg; /* alloca register number (frame ptr) */
char frameless; /* true if frameless functions. */
char nosavedpc; /* true if pc not saved. */
char used_bl; /* true if link register clobbered */
int gpr_offset; /* offset of saved gprs from prev sp */
int fpr_offset; /* offset of saved fprs from prev sp */
int vr_offset; /* offset of saved vrs from prev sp */
int ev_offset; /* offset of saved evs from prev sp */
int lr_offset; /* offset of saved lr */
int lr_register; /* register of saved lr, if trustworthy */
int cr_offset; /* offset of saved cr */
int vrsave_offset; /* offset of saved vrsave register */
};
/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
int
vsx_register_p (struct gdbarch *gdbarch, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->ppc_vsr0_regnum < 0)
return 0;
else
return (regno >= tdep->ppc_vsr0_upper_regnum && regno
<= tdep->ppc_vsr0_upper_regnum + 31);
}
/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
int
altivec_register_p (struct gdbarch *gdbarch, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
return 0;
else
return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
}
/* Return true if REGNO is an SPE register, false otherwise. */
int
spe_register_p (struct gdbarch *gdbarch, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* Is it a reference to EV0 -- EV31, and do we have those? */
if (IS_SPE_PSEUDOREG (tdep, regno))
return 1;
/* Is it a reference to one of the raw upper GPR halves? */
if (tdep->ppc_ev0_upper_regnum >= 0
&& tdep->ppc_ev0_upper_regnum <= regno
&& regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
return 1;
/* Is it a reference to the 64-bit accumulator, and do we have that? */
if (tdep->ppc_acc_regnum >= 0
&& tdep->ppc_acc_regnum == regno)
return 1;
/* Is it a reference to the SPE floating-point status and control register,
and do we have that? */
if (tdep->ppc_spefscr_regnum >= 0
&& tdep->ppc_spefscr_regnum == regno)
return 1;
return 0;
}
/* Return non-zero if the architecture described by GDBARCH has
floating-point registers (f0 --- f31 and fpscr). */
int
ppc_floating_point_unit_p (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
return (tdep->ppc_fp0_regnum >= 0
&& tdep->ppc_fpscr_regnum >= 0);
}
/* Return non-zero if the architecture described by GDBARCH has
VSX registers (vsr0 --- vsr63). */
static int
ppc_vsx_support_p (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
return tdep->ppc_vsr0_regnum >= 0;
}
/* Return non-zero if the architecture described by GDBARCH has
Altivec registers (vr0 --- vr31, vrsave and vscr). */
int
ppc_altivec_support_p (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
return (tdep->ppc_vr0_regnum >= 0
&& tdep->ppc_vrsave_regnum >= 0);
}
/* Check that TABLE[GDB_REGNO] is not already initialized, and then
set it to SIM_REGNO.
This is a helper function for init_sim_regno_table, constructing
the table mapping GDB register numbers to sim register numbers; we
initialize every element in that table to -1 before we start
filling it in. */
static void
set_sim_regno (int *table, int gdb_regno, int sim_regno)
{
/* Make sure we don't try to assign any given GDB register a sim
register number more than once. */
gdb_assert (table[gdb_regno] == -1);
table[gdb_regno] = sim_regno;
}
/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
numbers to simulator register numbers, based on the values placed
in the ARCH->tdep->ppc_foo_regnum members. */
static void
init_sim_regno_table (struct gdbarch *arch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
int total_regs = gdbarch_num_regs (arch);
int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
int i;
static const char *const segment_regs[] = {
"sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
};
/* Presume that all registers not explicitly mentioned below are
unavailable from the sim. */
for (i = 0; i < total_regs; i++)
sim_regno[i] = -1;
/* General-purpose registers. */
for (i = 0; i < ppc_num_gprs; i++)
set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
/* Floating-point registers. */
if (tdep->ppc_fp0_regnum >= 0)
for (i = 0; i < ppc_num_fprs; i++)
set_sim_regno (sim_regno,
tdep->ppc_fp0_regnum + i,
sim_ppc_f0_regnum + i);
if (tdep->ppc_fpscr_regnum >= 0)
set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
/* Segment registers. */
for (i = 0; i < ppc_num_srs; i++)
{
int gdb_regno;
gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
if (gdb_regno >= 0)
set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
}
/* Altivec registers. */
if (tdep->ppc_vr0_regnum >= 0)
{
for (i = 0; i < ppc_num_vrs; i++)
set_sim_regno (sim_regno,
tdep->ppc_vr0_regnum + i,
sim_ppc_vr0_regnum + i);
/* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
we can treat this more like the other cases. */
set_sim_regno (sim_regno,
tdep->ppc_vr0_regnum + ppc_num_vrs,
sim_ppc_vscr_regnum);
}
/* vsave is a special-purpose register, so the code below handles it. */
/* SPE APU (E500) registers. */
if (tdep->ppc_ev0_upper_regnum >= 0)
for (i = 0; i < ppc_num_gprs; i++)
set_sim_regno (sim_regno,
tdep->ppc_ev0_upper_regnum + i,
sim_ppc_rh0_regnum + i);
if (tdep->ppc_acc_regnum >= 0)
set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
/* spefscr is a special-purpose register, so the code below handles it. */
#ifdef WITH_SIM
/* Now handle all special-purpose registers. Verify that they
haven't mistakenly been assigned numbers by any of the above
code. */
for (i = 0; i < sim_ppc_num_sprs; i++)
{
const char *spr_name = sim_spr_register_name (i);
int gdb_regno = -1;
if (spr_name != NULL)
gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
if (gdb_regno != -1)
set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
}
#endif
/* Drop the initialized array into place. */
tdep->sim_regno = sim_regno;
}
/* Given a GDB register number REG, return the corresponding SIM
register number. */
static int
rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int sim_regno;
if (tdep->sim_regno == NULL)
init_sim_regno_table (gdbarch);
gdb_assert (0 <= reg
&& reg <= gdbarch_num_regs (gdbarch)
+ gdbarch_num_pseudo_regs (gdbarch));
sim_regno = tdep->sim_regno[reg];
if (sim_regno >= 0)
return sim_regno;
else
return LEGACY_SIM_REGNO_IGNORE;
}
/* Register set support functions. */
/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
Write the register to REGCACHE. */
void
ppc_supply_reg (struct regcache *regcache, int regnum,
const gdb_byte *regs, size_t offset, int regsize)
{
if (regnum != -1 && offset != -1)
{
if (regsize > 4)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int gdb_regsize = register_size (gdbarch, regnum);
if (gdb_regsize < regsize
&& gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
offset += regsize - gdb_regsize;
}
regcache_raw_supply (regcache, regnum, regs + offset);
}
}
/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
in a field REGSIZE wide. Zero pad as necessary. */
void
ppc_collect_reg (const struct regcache *regcache, int regnum,
gdb_byte *regs, size_t offset, int regsize)
{
if (regnum != -1 && offset != -1)
{
if (regsize > 4)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int gdb_regsize = register_size (gdbarch, regnum);
if (gdb_regsize < regsize)
{
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
memset (regs + offset, 0, regsize - gdb_regsize);
offset += regsize - gdb_regsize;
}
else
memset (regs + offset + regsize - gdb_regsize, 0,
regsize - gdb_regsize);
}
}
regcache_raw_collect (regcache, regnum, regs + offset);
}
}
static int
ppc_greg_offset (struct gdbarch *gdbarch,
struct gdbarch_tdep *tdep,
const struct ppc_reg_offsets *offsets,
int regnum,
int *regsize)
{
*regsize = offsets->gpr_size;
if (regnum >= tdep->ppc_gp0_regnum
&& regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
return (offsets->r0_offset
+ (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
if (regnum == gdbarch_pc_regnum (gdbarch))
return offsets->pc_offset;
if (regnum == tdep->ppc_ps_regnum)
return offsets->ps_offset;
if (regnum == tdep->ppc_lr_regnum)
return offsets->lr_offset;
if (regnum == tdep->ppc_ctr_regnum)
return offsets->ctr_offset;
*regsize = offsets->xr_size;
if (regnum == tdep->ppc_cr_regnum)
return offsets->cr_offset;
if (regnum == tdep->ppc_xer_regnum)
return offsets->xer_offset;
if (regnum == tdep->ppc_mq_regnum)
return offsets->mq_offset;
return -1;
}
static int
ppc_fpreg_offset (struct gdbarch_tdep *tdep,
const struct ppc_reg_offsets *offsets,
int regnum)
{
if (regnum >= tdep->ppc_fp0_regnum
&& regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
if (regnum == tdep->ppc_fpscr_regnum)
return offsets->fpscr_offset;
return -1;
}
static int
ppc_vrreg_offset (struct gdbarch_tdep *tdep,
const struct ppc_reg_offsets *offsets,
int regnum)
{
if (regnum >= tdep->ppc_vr0_regnum
&& regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
if (regnum == tdep->ppc_vrsave_regnum - 1)
return offsets->vscr_offset;
if (regnum == tdep->ppc_vrsave_regnum)
return offsets->vrsave_offset;
return -1;
}
/* Supply register REGNUM in the general-purpose register set REGSET
from the buffer specified by GREGS and LEN to register cache
REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
void
ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *gregs, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const struct ppc_reg_offsets *offsets = regset->regmap;
size_t offset;
int regsize;
if (regnum == -1)
{
int i;
int gpr_size = offsets->gpr_size;
for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
i < tdep->ppc_gp0_regnum + ppc_num_gprs;
i++, offset += gpr_size)
ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
gregs, offsets->pc_offset, gpr_size);
ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
gregs, offsets->ps_offset, gpr_size);
ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
gregs, offsets->lr_offset, gpr_size);
ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
gregs, offsets->ctr_offset, gpr_size);
ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
gregs, offsets->cr_offset, offsets->xr_size);
ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
gregs, offsets->xer_offset, offsets->xr_size);
ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
gregs, offsets->mq_offset, offsets->xr_size);
return;
}
offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
}
/* Supply register REGNUM in the floating-point register set REGSET
from the buffer specified by FPREGS and LEN to register cache
REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
void
ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *fpregs, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
if (!ppc_floating_point_unit_p (gdbarch))
return;
tdep = gdbarch_tdep (gdbarch);
offsets = regset->regmap;
if (regnum == -1)
{
int i;
for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
i < tdep->ppc_fp0_regnum + ppc_num_fprs;
i++, offset += 8)
ppc_supply_reg (regcache, i, fpregs, offset, 8);
ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
fpregs, offsets->fpscr_offset, offsets->fpscr_size);
return;
}
offset = ppc_fpreg_offset (tdep, offsets, regnum);
ppc_supply_reg (regcache, regnum, fpregs, offset,
regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
}
/* Supply register REGNUM in the VSX register set REGSET
from the buffer specified by VSXREGS and LEN to register cache
REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
void
ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *vsxregs, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep;
if (!ppc_vsx_support_p (gdbarch))
return;
tdep = gdbarch_tdep (gdbarch);
if (regnum == -1)
{
int i;
for (i = tdep->ppc_vsr0_upper_regnum;
i < tdep->ppc_vsr0_upper_regnum + 32;
i++)
ppc_supply_reg (regcache, i, vsxregs, 0, 8);
return;
}
else
ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
}
/* Supply register REGNUM in the Altivec register set REGSET
from the buffer specified by VRREGS and LEN to register cache
REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
void
ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *vrregs, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
if (!ppc_altivec_support_p (gdbarch))
return;
tdep = gdbarch_tdep (gdbarch);
offsets = regset->regmap;
if (regnum == -1)
{
int i;
for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
i < tdep->ppc_vr0_regnum + ppc_num_vrs;
i++, offset += 16)
ppc_supply_reg (regcache, i, vrregs, offset, 16);
ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
vrregs, offsets->vscr_offset, 4);
ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
vrregs, offsets->vrsave_offset, 4);
return;
}
offset = ppc_vrreg_offset (tdep, offsets, regnum);
if (regnum != tdep->ppc_vrsave_regnum
&& regnum != tdep->ppc_vrsave_regnum - 1)
ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
else
ppc_supply_reg (regcache, regnum,
vrregs, offset, 4);
}
/* Collect register REGNUM in the general-purpose register set
REGSET from register cache REGCACHE into the buffer specified by
GREGS and LEN. If REGNUM is -1, do this for all registers in
REGSET. */
void
ppc_collect_gregset (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *gregs, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const struct ppc_reg_offsets *offsets = regset->regmap;
size_t offset;
int regsize;
if (regnum == -1)
{
int i;
int gpr_size = offsets->gpr_size;
for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
i < tdep->ppc_gp0_regnum + ppc_num_gprs;
i++, offset += gpr_size)
ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
gregs, offsets->pc_offset, gpr_size);
ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
gregs, offsets->ps_offset, gpr_size);
ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
gregs, offsets->lr_offset, gpr_size);
ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
gregs, offsets->ctr_offset, gpr_size);
ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
gregs, offsets->cr_offset, offsets->xr_size);
ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
gregs, offsets->xer_offset, offsets->xr_size);
ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
gregs, offsets->mq_offset, offsets->xr_size);
return;
}
offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
}
/* Collect register REGNUM in the floating-point register set
REGSET from register cache REGCACHE into the buffer specified by
FPREGS and LEN. If REGNUM is -1, do this for all registers in
REGSET. */
void
ppc_collect_fpregset (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *fpregs, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
if (!ppc_floating_point_unit_p (gdbarch))
return;
tdep = gdbarch_tdep (gdbarch);
offsets = regset->regmap;
if (regnum == -1)
{
int i;
for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
i < tdep->ppc_fp0_regnum + ppc_num_fprs;
i++, offset += 8)
ppc_collect_reg (regcache, i, fpregs, offset, 8);
ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
fpregs, offsets->fpscr_offset, offsets->fpscr_size);
return;
}
offset = ppc_fpreg_offset (tdep, offsets, regnum);
ppc_collect_reg (regcache, regnum, fpregs, offset,
regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
}
/* Collect register REGNUM in the VSX register set
REGSET from register cache REGCACHE into the buffer specified by
VSXREGS and LEN. If REGNUM is -1, do this for all registers in
REGSET. */
void
ppc_collect_vsxregset (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *vsxregs, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep;
if (!ppc_vsx_support_p (gdbarch))
return;
tdep = gdbarch_tdep (gdbarch);
if (regnum == -1)
{
int i;
for (i = tdep->ppc_vsr0_upper_regnum;
i < tdep->ppc_vsr0_upper_regnum + 32;
i++)
ppc_collect_reg (regcache, i, vsxregs, 0, 8);
return;
}
else
ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
}
/* Collect register REGNUM in the Altivec register set
REGSET from register cache REGCACHE into the buffer specified by
VRREGS and LEN. If REGNUM is -1, do this for all registers in
REGSET. */
void
ppc_collect_vrregset (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *vrregs, size_t len)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
if (!ppc_altivec_support_p (gdbarch))
return;
tdep = gdbarch_tdep (gdbarch);
offsets = regset->regmap;
if (regnum == -1)
{
int i;
for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
i < tdep->ppc_vr0_regnum + ppc_num_vrs;
i++, offset += 16)
ppc_collect_reg (regcache, i, vrregs, offset, 16);
ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
vrregs, offsets->vscr_offset, 4);
ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
vrregs, offsets->vrsave_offset, 4);
return;
}
offset = ppc_vrreg_offset (tdep, offsets, regnum);
if (regnum != tdep->ppc_vrsave_regnum
&& regnum != tdep->ppc_vrsave_regnum - 1)
ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
else
ppc_collect_reg (regcache, regnum,
vrregs, offset, 4);
}
static int
insn_changes_sp_or_jumps (unsigned long insn)
{
int opcode = (insn >> 26) & 0x03f;
int sd = (insn >> 21) & 0x01f;
int a = (insn >> 16) & 0x01f;
int subcode = (insn >> 1) & 0x3ff;
/* Changes the stack pointer. */
/* NOTE: There are many ways to change the value of a given register.
The ways below are those used when the register is R1, the SP,
in a funtion's epilogue. */
if (opcode == 31 && subcode == 444 && a == 1)
return 1; /* mr R1,Rn */
if (opcode == 14 && sd == 1)
return 1; /* addi R1,Rn,simm */
if (opcode == 58 && sd == 1)
return 1; /* ld R1,ds(Rn) */
/* Transfers control. */
if (opcode == 18)
return 1; /* b */
if (opcode == 16)
return 1; /* bc */
if (opcode == 19 && subcode == 16)
return 1; /* bclr */
if (opcode == 19 && subcode == 528)
return 1; /* bcctr */
return 0;
}
/* Return true if we are in the function's epilogue, i.e. after the
instruction that destroyed the function's stack frame.
1) scan forward from the point of execution:
a) If you find an instruction that modifies the stack pointer
or transfers control (except a return), execution is not in
an epilogue, return.
b) Stop scanning if you find a return instruction or reach the
end of the function or reach the hard limit for the size of
an epilogue.
2) scan backward from the point of execution:
a) If you find an instruction that modifies the stack pointer,
execution *is* in an epilogue, return.
b) Stop scanning if you reach an instruction that transfers
control or the beginning of the function or reach the hard
limit for the size of an epilogue. */
static int
rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm,
struct gdbarch *gdbarch, CORE_ADDR pc)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
bfd_byte insn_buf[PPC_INSN_SIZE];
CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
unsigned long insn;
/* Find the search limits based on function boundaries and hard limit. */
if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
return 0;
epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
if (epilogue_start < func_start) epilogue_start = func_start;
epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
if (epilogue_end > func_end) epilogue_end = func_end;
/* Scan forward until next 'blr'. */
for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
{
if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
return 0;
insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
if (insn == 0x4e800020)
break;
/* Assume a bctr is a tail call unless it points strictly within
this function. */
if (insn == 0x4e800420)
{
CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
tdep->ppc_ctr_regnum);
if (ctr > func_start && ctr < func_end)
return 0;
else
break;
}
if (insn_changes_sp_or_jumps (insn))
return 0;
}
/* Scan backward until adjustment to stack pointer (R1). */
for (scan_pc = pc - PPC_INSN_SIZE;
scan_pc >= epilogue_start;
scan_pc -= PPC_INSN_SIZE)
{
if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
return 0;
insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
if (insn_changes_sp_or_jumps (insn))
return 1;
}
return 0;
}
/* Implement the stack_frame_destroyed_p gdbarch method. */
static int
rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
return rs6000_in_function_epilogue_frame_p (get_current_frame (),
gdbarch, pc);
}
/* Get the ith function argument for the current function. */
static CORE_ADDR
rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
struct type *type)
{
return get_frame_register_unsigned (frame, 3 + argi);
}
/* Sequence of bytes for breakpoint instruction. */
static const unsigned char *
rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
int *bp_size)
{
static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
*bp_size = 4;
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
return big_breakpoint;
else
return little_breakpoint;
}
/* Instruction masks for displaced stepping. */
#define BRANCH_MASK 0xfc000000
#define BP_MASK 0xFC0007FE
#define B_INSN 0x48000000
#define BC_INSN 0x40000000
#define BXL_INSN 0x4c000000
#define BP_INSN 0x7C000008
/* Instruction masks used during single-stepping of atomic
sequences. */
#define LWARX_MASK 0xfc0007fe
#define LWARX_INSTRUCTION 0x7c000028
#define LDARX_INSTRUCTION 0x7c0000A8
#define STWCX_MASK 0xfc0007ff
#define STWCX_INSTRUCTION 0x7c00012d
#define STDCX_INSTRUCTION 0x7c0001ad
/* We can't displaced step atomic sequences. Otherwise this is just
like simple_displaced_step_copy_insn. */
static struct displaced_step_closure *
ppc_displaced_step_copy_insn (struct gdbarch *gdbarch,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
size_t len = gdbarch_max_insn_length (gdbarch);
gdb_byte *buf = xmalloc (len);
struct cleanup *old_chain = make_cleanup (xfree, buf);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int insn;
read_memory (from, buf, len);