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rl78-tdep.c
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/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
Copyright (C) 2011-2015 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "arch-utils.h"
#include "prologue-value.h"
#include "target.h"
#include "regcache.h"
#include "opcode/rl78.h"
#include "dis-asm.h"
#include "gdbtypes.h"
#include "frame.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "value.h"
#include "gdbcore.h"
#include "dwarf2-frame.h"
#include "reggroups.h"
#include "elf/rl78.h"
#include "elf-bfd.h"
/* Register Banks. */
enum
{
RL78_BANK0 = 0,
RL78_BANK1 = 1,
RL78_BANK2 = 2,
RL78_BANK3 = 3,
RL78_NUMBANKS = 4,
RL78_REGS_PER_BANK = 8
};
/* Register Numbers. */
enum
{
/* All general purpose registers are 8 bits wide. */
RL78_RAW_BANK0_R0_REGNUM = 0,
RL78_RAW_BANK0_R1_REGNUM,
RL78_RAW_BANK0_R2_REGNUM,
RL78_RAW_BANK0_R3_REGNUM,
RL78_RAW_BANK0_R4_REGNUM,
RL78_RAW_BANK0_R5_REGNUM,
RL78_RAW_BANK0_R6_REGNUM,
RL78_RAW_BANK0_R7_REGNUM,
RL78_RAW_BANK1_R0_REGNUM,
RL78_RAW_BANK1_R1_REGNUM,
RL78_RAW_BANK1_R2_REGNUM,
RL78_RAW_BANK1_R3_REGNUM,
RL78_RAW_BANK1_R4_REGNUM,
RL78_RAW_BANK1_R5_REGNUM,
RL78_RAW_BANK1_R6_REGNUM,
RL78_RAW_BANK1_R7_REGNUM,
RL78_RAW_BANK2_R0_REGNUM,
RL78_RAW_BANK2_R1_REGNUM,
RL78_RAW_BANK2_R2_REGNUM,
RL78_RAW_BANK2_R3_REGNUM,
RL78_RAW_BANK2_R4_REGNUM,
RL78_RAW_BANK2_R5_REGNUM,
RL78_RAW_BANK2_R6_REGNUM,
RL78_RAW_BANK2_R7_REGNUM,
RL78_RAW_BANK3_R0_REGNUM,
RL78_RAW_BANK3_R1_REGNUM,
RL78_RAW_BANK3_R2_REGNUM,
RL78_RAW_BANK3_R3_REGNUM,
RL78_RAW_BANK3_R4_REGNUM,
RL78_RAW_BANK3_R5_REGNUM,
RL78_RAW_BANK3_R6_REGNUM,
RL78_RAW_BANK3_R7_REGNUM,
RL78_PSW_REGNUM, /* 8 bits */
RL78_ES_REGNUM, /* 8 bits */
RL78_CS_REGNUM, /* 8 bits */
RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
/* Fixed address SFRs (some of those above are SFRs too.) */
RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
RL78_PMC_REGNUM, /* 8 bits */
RL78_MEM_REGNUM, /* 8 bits ?? */
RL78_NUM_REGS,
/* Pseudo registers. */
RL78_PC_REGNUM = RL78_NUM_REGS,
RL78_SP_REGNUM,
RL78_X_REGNUM,
RL78_A_REGNUM,
RL78_C_REGNUM,
RL78_B_REGNUM,
RL78_E_REGNUM,
RL78_D_REGNUM,
RL78_L_REGNUM,
RL78_H_REGNUM,
RL78_AX_REGNUM,
RL78_BC_REGNUM,
RL78_DE_REGNUM,
RL78_HL_REGNUM,
RL78_BANK0_R0_REGNUM,
RL78_BANK0_R1_REGNUM,
RL78_BANK0_R2_REGNUM,
RL78_BANK0_R3_REGNUM,
RL78_BANK0_R4_REGNUM,
RL78_BANK0_R5_REGNUM,
RL78_BANK0_R6_REGNUM,
RL78_BANK0_R7_REGNUM,
RL78_BANK1_R0_REGNUM,
RL78_BANK1_R1_REGNUM,
RL78_BANK1_R2_REGNUM,
RL78_BANK1_R3_REGNUM,
RL78_BANK1_R4_REGNUM,
RL78_BANK1_R5_REGNUM,
RL78_BANK1_R6_REGNUM,
RL78_BANK1_R7_REGNUM,
RL78_BANK2_R0_REGNUM,
RL78_BANK2_R1_REGNUM,
RL78_BANK2_R2_REGNUM,
RL78_BANK2_R3_REGNUM,
RL78_BANK2_R4_REGNUM,
RL78_BANK2_R5_REGNUM,
RL78_BANK2_R6_REGNUM,
RL78_BANK2_R7_REGNUM,
RL78_BANK3_R0_REGNUM,
RL78_BANK3_R1_REGNUM,
RL78_BANK3_R2_REGNUM,
RL78_BANK3_R3_REGNUM,
RL78_BANK3_R4_REGNUM,
RL78_BANK3_R5_REGNUM,
RL78_BANK3_R6_REGNUM,
RL78_BANK3_R7_REGNUM,
RL78_BANK0_RP0_REGNUM,
RL78_BANK0_RP1_REGNUM,
RL78_BANK0_RP2_REGNUM,
RL78_BANK0_RP3_REGNUM,
RL78_BANK1_RP0_REGNUM,
RL78_BANK1_RP1_REGNUM,
RL78_BANK1_RP2_REGNUM,
RL78_BANK1_RP3_REGNUM,
RL78_BANK2_RP0_REGNUM,
RL78_BANK2_RP1_REGNUM,
RL78_BANK2_RP2_REGNUM,
RL78_BANK2_RP3_REGNUM,
RL78_BANK3_RP0_REGNUM,
RL78_BANK3_RP1_REGNUM,
RL78_BANK3_RP2_REGNUM,
RL78_BANK3_RP3_REGNUM,
/* These are the same as the above 16 registers, but have
a pointer type for use as base registers in expression
evaluation. These are not user visible registers. */
RL78_BANK0_RP0_PTR_REGNUM,
RL78_BANK0_RP1_PTR_REGNUM,
RL78_BANK0_RP2_PTR_REGNUM,
RL78_BANK0_RP3_PTR_REGNUM,
RL78_BANK1_RP0_PTR_REGNUM,
RL78_BANK1_RP1_PTR_REGNUM,
RL78_BANK1_RP2_PTR_REGNUM,
RL78_BANK1_RP3_PTR_REGNUM,
RL78_BANK2_RP0_PTR_REGNUM,
RL78_BANK2_RP1_PTR_REGNUM,
RL78_BANK2_RP2_PTR_REGNUM,
RL78_BANK2_RP3_PTR_REGNUM,
RL78_BANK3_RP0_PTR_REGNUM,
RL78_BANK3_RP1_PTR_REGNUM,
RL78_BANK3_RP2_PTR_REGNUM,
RL78_BANK3_RP3_PTR_REGNUM,
RL78_NUM_TOTAL_REGS,
RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
};
#define RL78_SP_ADDR 0xffff8
/* Architecture specific data. */
struct gdbarch_tdep
{
/* The ELF header flags specify the multilib used. */
int elf_flags;
struct type *rl78_void,
*rl78_uint8,
*rl78_int8,
*rl78_uint16,
*rl78_int16,
*rl78_uint32,
*rl78_int32,
*rl78_data_pointer,
*rl78_code_pointer,
*rl78_psw_type;
};
/* This structure holds the results of a prologue analysis. */
struct rl78_prologue
{
/* The offset from the frame base to the stack pointer --- always
zero or negative.
Calling this a "size" is a bit misleading, but given that the
stack grows downwards, using offsets for everything keeps one
from going completely sign-crazy: you never change anything's
sign for an ADD instruction; always change the second operand's
sign for a SUB instruction; and everything takes care of
itself. */
int frame_size;
/* Non-zero if this function has initialized the frame pointer from
the stack pointer, zero otherwise. */
int has_frame_ptr;
/* If has_frame_ptr is non-zero, this is the offset from the frame
base to where the frame pointer points. This is always zero or
negative. */
int frame_ptr_offset;
/* The address of the first instruction at which the frame has been
set up and the arguments are where the debug info says they are
--- as best as we can tell. */
CORE_ADDR prologue_end;
/* reg_offset[R] is the offset from the CFA at which register R is
saved, or 1 if register R has not been saved. (Real values are
always zero or negative.) */
int reg_offset[RL78_NUM_TOTAL_REGS];
};
/* Implement the "register_type" gdbarch method. */
static struct type *
rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (reg_nr == RL78_PC_REGNUM)
return tdep->rl78_code_pointer;
else if (reg_nr == RL78_RAW_PC_REGNUM)
return tdep->rl78_uint32;
else if (reg_nr == RL78_PSW_REGNUM)
return (tdep->rl78_psw_type);
else if (reg_nr <= RL78_MEM_REGNUM
|| (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
|| (RL78_BANK0_R0_REGNUM <= reg_nr
&& reg_nr <= RL78_BANK3_R7_REGNUM))
return tdep->rl78_int8;
else if (reg_nr == RL78_SP_REGNUM
|| (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
&& reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
return tdep->rl78_data_pointer;
else
return tdep->rl78_int16;
}
/* Implement the "register_name" gdbarch method. */
static const char *
rl78_register_name (struct gdbarch *gdbarch, int regnr)
{
static const char *const reg_names[] =
{
"", /* bank0_r0 */
"", /* bank0_r1 */
"", /* bank0_r2 */
"", /* bank0_r3 */
"", /* bank0_r4 */
"", /* bank0_r5 */
"", /* bank0_r6 */
"", /* bank0_r7 */
"", /* bank1_r0 */
"", /* bank1_r1 */
"", /* bank1_r2 */
"", /* bank1_r3 */
"", /* bank1_r4 */
"", /* bank1_r5 */
"", /* bank1_r6 */
"", /* bank1_r7 */
"", /* bank2_r0 */
"", /* bank2_r1 */
"", /* bank2_r2 */
"", /* bank2_r3 */
"", /* bank2_r4 */
"", /* bank2_r5 */
"", /* bank2_r6 */
"", /* bank2_r7 */
"", /* bank3_r0 */
"", /* bank3_r1 */
"", /* bank3_r2 */
"", /* bank3_r3 */
"", /* bank3_r4 */
"", /* bank3_r5 */
"", /* bank3_r6 */
"", /* bank3_r7 */
"psw",
"es",
"cs",
"",
"", /* spl */
"", /* sph */
"pmc",
"mem",
"pc",
"sp",
"x",
"a",
"c",
"b",
"e",
"d",
"l",
"h",
"ax",
"bc",
"de",
"hl",
"bank0_r0",
"bank0_r1",
"bank0_r2",
"bank0_r3",
"bank0_r4",
"bank0_r5",
"bank0_r6",
"bank0_r7",
"bank1_r0",
"bank1_r1",
"bank1_r2",
"bank1_r3",
"bank1_r4",
"bank1_r5",
"bank1_r6",
"bank1_r7",
"bank2_r0",
"bank2_r1",
"bank2_r2",
"bank2_r3",
"bank2_r4",
"bank2_r5",
"bank2_r6",
"bank2_r7",
"bank3_r0",
"bank3_r1",
"bank3_r2",
"bank3_r3",
"bank3_r4",
"bank3_r5",
"bank3_r6",
"bank3_r7",
"bank0_rp0",
"bank0_rp1",
"bank0_rp2",
"bank0_rp3",
"bank1_rp0",
"bank1_rp1",
"bank1_rp2",
"bank1_rp3",
"bank2_rp0",
"bank2_rp1",
"bank2_rp2",
"bank2_rp3",
"bank3_rp0",
"bank3_rp1",
"bank3_rp2",
"bank3_rp3",
/* The 16 register slots would be named
bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
want these to be user visible registers. */
"", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
};
return reg_names[regnr];
}
/* Implement the "register_name" gdbarch method for the g10 variant. */
static const char *
rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
{
static const char *const reg_names[] =
{
"", /* bank0_r0 */
"", /* bank0_r1 */
"", /* bank0_r2 */
"", /* bank0_r3 */
"", /* bank0_r4 */
"", /* bank0_r5 */
"", /* bank0_r6 */
"", /* bank0_r7 */
"", /* bank1_r0 */
"", /* bank1_r1 */
"", /* bank1_r2 */
"", /* bank1_r3 */
"", /* bank1_r4 */
"", /* bank1_r5 */
"", /* bank1_r6 */
"", /* bank1_r7 */
"", /* bank2_r0 */
"", /* bank2_r1 */
"", /* bank2_r2 */
"", /* bank2_r3 */
"", /* bank2_r4 */
"", /* bank2_r5 */
"", /* bank2_r6 */
"", /* bank2_r7 */
"", /* bank3_r0 */
"", /* bank3_r1 */
"", /* bank3_r2 */
"", /* bank3_r3 */
"", /* bank3_r4 */
"", /* bank3_r5 */
"", /* bank3_r6 */
"", /* bank3_r7 */
"psw",
"es",
"cs",
"",
"", /* spl */
"", /* sph */
"pmc",
"mem",
"pc",
"sp",
"x",
"a",
"c",
"b",
"e",
"d",
"l",
"h",
"ax",
"bc",
"de",
"hl",
"bank0_r0",
"bank0_r1",
"bank0_r2",
"bank0_r3",
"bank0_r4",
"bank0_r5",
"bank0_r6",
"bank0_r7",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"bank0_rp0",
"bank0_rp1",
"bank0_rp2",
"bank0_rp3",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
/* The 16 register slots would be named
bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
want these to be user visible registers. */
"", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
};
return reg_names[regnr];
}
/* Implement the "register_reggroup_p" gdbarch method. */
static int
rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *group)
{
if (group == all_reggroup)
return 1;
/* All other registers are saved and restored. */
if (group == save_reggroup || group == restore_reggroup)
{
if ((regnum < RL78_NUM_REGS
&& regnum != RL78_SPL_REGNUM
&& regnum != RL78_SPH_REGNUM
&& regnum != RL78_RAW_PC_REGNUM)
|| regnum == RL78_SP_REGNUM
|| regnum == RL78_PC_REGNUM)
return 1;
else
return 0;
}
if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
|| regnum == RL78_ES_REGNUM
|| regnum == RL78_CS_REGNUM
|| regnum == RL78_SPL_REGNUM
|| regnum == RL78_SPH_REGNUM
|| regnum == RL78_PMC_REGNUM
|| regnum == RL78_MEM_REGNUM
|| regnum == RL78_RAW_PC_REGNUM
|| (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
return group == system_reggroup;
return group == general_reggroup;
}
/* Strip bits to form an instruction address. (When fetching a
32-bit address from the stack, the high eight bits are garbage.
This function strips off those unused bits.) */
static CORE_ADDR
rl78_make_instruction_address (CORE_ADDR addr)
{
return addr & 0xffffff;
}
/* Set / clear bits necessary to make a data address. */
static CORE_ADDR
rl78_make_data_address (CORE_ADDR addr)
{
return (addr & 0xffff) | 0xf0000;
}
/* Implement the "pseudo_register_read" gdbarch method. */
static enum register_status
rl78_pseudo_register_read (struct gdbarch *gdbarch,
struct regcache *regcache,
int reg, gdb_byte *buffer)
{
enum register_status status;
if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
{
int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
+ (reg - RL78_BANK0_R0_REGNUM);
status = regcache_raw_read (regcache, raw_regnum, buffer);
}
else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
{
int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
+ RL78_RAW_BANK0_R0_REGNUM;
status = regcache_raw_read (regcache, raw_regnum, buffer);
if (status == REG_VALID)
status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
}
else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
{
int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
+ RL78_RAW_BANK0_R0_REGNUM;
status = regcache_raw_read (regcache, raw_regnum, buffer);
if (status == REG_VALID)
status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
}
else if (reg == RL78_SP_REGNUM)
{
status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
if (status == REG_VALID)
status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
}
else if (reg == RL78_PC_REGNUM)
{
gdb_byte rawbuf[4];
status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
memcpy (buffer, rawbuf, 3);
}
else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
{
ULONGEST psw;
status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
if (status == REG_VALID)
{
/* RSB0 is at bit 3; RSBS1 is at bit 5. */
int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
+ (reg - RL78_X_REGNUM);
status = regcache_raw_read (regcache, raw_regnum, buffer);
}
}
else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
{
ULONGEST psw;
status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
if (status == REG_VALID)
{
/* RSB0 is at bit 3; RSBS1 is at bit 5. */
int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
+ 2 * (reg - RL78_AX_REGNUM);
status = regcache_raw_read (regcache, raw_regnum, buffer);
if (status == REG_VALID)
status = regcache_raw_read (regcache, raw_regnum + 1,
buffer + 1);
}
}
else
gdb_assert_not_reached ("invalid pseudo register number");
return status;
}
/* Implement the "pseudo_register_write" gdbarch method. */
static void
rl78_pseudo_register_write (struct gdbarch *gdbarch,
struct regcache *regcache,
int reg, const gdb_byte *buffer)
{
if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
{
int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
+ (reg - RL78_BANK0_R0_REGNUM);
regcache_raw_write (regcache, raw_regnum, buffer);
}
else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
{
int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
+ RL78_RAW_BANK0_R0_REGNUM;
regcache_raw_write (regcache, raw_regnum, buffer);
regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
}
else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
{
int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
+ RL78_RAW_BANK0_R0_REGNUM;
regcache_raw_write (regcache, raw_regnum, buffer);
regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
}
else if (reg == RL78_SP_REGNUM)
{
regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
}
else if (reg == RL78_PC_REGNUM)
{
gdb_byte rawbuf[4];
memcpy (rawbuf, buffer, 3);
rawbuf[3] = 0;
regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
}
else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
{
ULONGEST psw;
int bank;
int raw_regnum;
regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
/* RSB0 is at bit 3; RSBS1 is at bit 5. */
raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
+ (reg - RL78_X_REGNUM);
regcache_raw_write (regcache, raw_regnum, buffer);
}
else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
{
ULONGEST psw;
int bank, raw_regnum;
regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
/* RSB0 is at bit 3; RSBS1 is at bit 5. */
raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
+ 2 * (reg - RL78_AX_REGNUM);
regcache_raw_write (regcache, raw_regnum, buffer);
regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
}
else
gdb_assert_not_reached ("invalid pseudo register number");
}
/* Implement the "breakpoint_from_pc" gdbarch method. */
static const gdb_byte *
rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
int *lenptr)
{
/* The documented BRK instruction is actually a two byte sequence,
{0x61, 0xcc}, but instructions may be as short as one byte.
Correspondence with Renesas revealed that the one byte sequence
0xff is used when a one byte breakpoint instruction is required. */
static gdb_byte breakpoint[] = { 0xff };
*lenptr = sizeof breakpoint;
return breakpoint;
}
/* Define a "handle" struct for fetching the next opcode. */
struct rl78_get_opcode_byte_handle
{
CORE_ADDR pc;
};
static int
opc_reg_to_gdb_regnum (int opcreg)
{
switch (opcreg)
{
case RL78_Reg_X:
return RL78_X_REGNUM;
case RL78_Reg_A:
return RL78_A_REGNUM;
case RL78_Reg_C:
return RL78_C_REGNUM;
case RL78_Reg_B:
return RL78_B_REGNUM;
case RL78_Reg_E:
return RL78_E_REGNUM;
case RL78_Reg_D:
return RL78_D_REGNUM;
case RL78_Reg_L:
return RL78_L_REGNUM;
case RL78_Reg_H:
return RL78_H_REGNUM;
case RL78_Reg_AX:
return RL78_AX_REGNUM;
case RL78_Reg_BC:
return RL78_BC_REGNUM;
case RL78_Reg_DE:
return RL78_DE_REGNUM;
case RL78_Reg_HL:
return RL78_HL_REGNUM;
case RL78_Reg_SP:
return RL78_SP_REGNUM;
case RL78_Reg_PSW:
return RL78_PSW_REGNUM;
case RL78_Reg_CS:
return RL78_CS_REGNUM;
case RL78_Reg_ES:
return RL78_ES_REGNUM;
case RL78_Reg_PMC:
return RL78_PMC_REGNUM;
case RL78_Reg_MEM:
return RL78_MEM_REGNUM;
default:
internal_error (__FILE__, __LINE__,
_("Undefined mapping for opc reg %d"),
opcreg);
}
/* Not reached. */
return 0;
}
/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
the memory address of the next byte to fetch. If successful,
the address in the handle is updated and the byte fetched is
returned as the value of the function. If not successful, -1
is returned. */
static int
rl78_get_opcode_byte (void *handle)
{
struct rl78_get_opcode_byte_handle *opcdata = handle;
int status;
gdb_byte byte;
status = target_read_memory (opcdata->pc, &byte, 1);
if (status == 0)
{
opcdata->pc += 1;
return byte;
}
else
return -1;
}
/* Function for finding saved registers in a 'struct pv_area'; this
function is passed to pv_area_scan.
If VALUE is a saved register, ADDR says it was saved at a constant
offset from the frame base, and SIZE indicates that the whole
register was saved, record its offset. */
static void
check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
pv_t value)
{
struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
if (value.kind == pvk_register
&& value.k == 0
&& pv_is_register (addr, RL78_SP_REGNUM)
&& size == register_size (target_gdbarch (), value.reg))
result->reg_offset[value.reg] = addr.k;
}
/* Analyze a prologue starting at START_PC, going no further than
LIMIT_PC. Fill in RESULT as appropriate. */
static void
rl78_analyze_prologue (CORE_ADDR start_pc,
CORE_ADDR limit_pc, struct rl78_prologue *result)
{
CORE_ADDR pc, next_pc;
int rn;
pv_t reg[RL78_NUM_TOTAL_REGS];
struct pv_area *stack;
struct cleanup *back_to;
CORE_ADDR after_last_frame_setup_insn = start_pc;
int bank = 0;
memset (result, 0, sizeof (*result));
for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
{
reg[rn] = pv_register (rn, 0);
result->reg_offset[rn] = 1;
}
stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
back_to = make_cleanup_free_pv_area (stack);
/* The call instruction has saved the return address on the stack. */
reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
pc = start_pc;
while (pc < limit_pc)
{
int bytes_read;
struct rl78_get_opcode_byte_handle opcode_handle;
RL78_Opcode_Decoded opc;
opcode_handle.pc = pc;
bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
&opcode_handle, RL78_ISA_DEFAULT);
next_pc = pc + bytes_read;
if (opc.id == RLO_sel)
{
bank = opc.op[1].addend;
}
else if (opc.id == RLO_mov
&& opc.op[0].type == RL78_Operand_PreDec
&& opc.op[0].reg == RL78_Reg_SP
&& opc.op[1].type == RL78_Operand_Register)
{
int rsrc = (bank * RL78_REGS_PER_BANK)
+ 2 * (opc.op[1].reg - RL78_Reg_AX);
reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
after_last_frame_setup_insn = next_pc;
}
else if (opc.id == RLO_sub
&& opc.op[0].type == RL78_Operand_Register
&& opc.op[0].reg == RL78_Reg_SP
&& opc.op[1].type == RL78_Operand_Immediate)
{
int addend = opc.op[1].addend;
reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
-addend);
after_last_frame_setup_insn = next_pc;
}
else if (opc.id == RLO_mov
&& opc.size == RL78_Word
&& opc.op[0].type == RL78_Operand_Register
&& opc.op[1].type == RL78_Operand_Indirect
&& opc.op[1].addend == RL78_SP_ADDR)
{
reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
= reg[RL78_SP_REGNUM];
}
else if (opc.id == RLO_sub
&& opc.size == RL78_Word
&& opc.op[0].type == RL78_Operand_Register
&& opc.op[1].type == RL78_Operand_Immediate)
{
int addend = opc.op[1].addend;
int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
reg[regnum] = pv_add_constant (reg[regnum], -addend);
}
else if (opc.id == RLO_mov
&& opc.size == RL78_Word
&& opc.op[0].type == RL78_Operand_Indirect
&& opc.op[0].addend == RL78_SP_ADDR
&& opc.op[1].type == RL78_Operand_Register)
{
reg[RL78_SP_REGNUM]
= reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
after_last_frame_setup_insn = next_pc;
}
else
{
/* Terminate the prologue scan. */
break;
}
pc = next_pc;
}
/* Is the frame size (offset, really) a known constant? */
if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
result->frame_size = reg[RL78_SP_REGNUM].k;