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mips-tdep.c
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/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
Copyright (C) 1988-2015 Free Software Foundation, Inc.
Contributed by Alessandro Forin([email protected]) at CMU
and by Per Bothner([email protected]) at U.Wisconsin.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "inferior.h"
#include "symtab.h"
#include "value.h"
#include "gdbcmd.h"
#include "language.h"
#include "gdbcore.h"
#include "symfile.h"
#include "objfiles.h"
#include "gdbtypes.h"
#include "target.h"
#include "arch-utils.h"
#include "regcache.h"
#include "osabi.h"
#include "mips-tdep.h"
#include "block.h"
#include "reggroups.h"
#include "opcode/mips.h"
#include "elf/mips.h"
#include "elf-bfd.h"
#include "symcat.h"
#include "sim-regno.h"
#include "dis-asm.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "infcall.h"
#include "floatformat.h"
#include "remote.h"
#include "target-descriptions.h"
#include "dwarf2-frame.h"
#include "user-regs.h"
#include "valprint.h"
#include "ax.h"
static const struct objfile_data *mips_pdr_data;
static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch,
ULONGEST inst);
static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32);
static int mips16_instruction_has_delay_slot (unsigned short inst,
int mustbe32);
static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
CORE_ADDR addr);
static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
CORE_ADDR addr, int mustbe32);
static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch,
CORE_ADDR addr, int mustbe32);
static void mips_print_float_info (struct gdbarch *, struct ui_file *,
struct frame_info *, const char *);
/* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
#define ST0_FR (1 << 26)
/* The sizes of floating point registers. */
enum
{
MIPS_FPU_SINGLE_REGSIZE = 4,
MIPS_FPU_DOUBLE_REGSIZE = 8
};
enum
{
MIPS32_REGSIZE = 4,
MIPS64_REGSIZE = 8
};
static const char *mips_abi_string;
static const char *const mips_abi_strings[] = {
"auto",
"n32",
"o32",
"n64",
"o64",
"eabi32",
"eabi64",
NULL
};
/* For backwards compatibility we default to MIPS16. This flag is
overridden as soon as unambiguous ELF file flags tell us the
compressed ISA encoding used. */
static const char mips_compression_mips16[] = "mips16";
static const char mips_compression_micromips[] = "micromips";
static const char *const mips_compression_strings[] =
{
mips_compression_mips16,
mips_compression_micromips,
NULL
};
static const char *mips_compression_string = mips_compression_mips16;
/* The standard register names, and all the valid aliases for them. */
struct register_alias
{
const char *name;
int regnum;
};
/* Aliases for o32 and most other ABIs. */
const struct register_alias mips_o32_aliases[] = {
{ "ta0", 12 },
{ "ta1", 13 },
{ "ta2", 14 },
{ "ta3", 15 }
};
/* Aliases for n32 and n64. */
const struct register_alias mips_n32_n64_aliases[] = {
{ "ta0", 8 },
{ "ta1", 9 },
{ "ta2", 10 },
{ "ta3", 11 }
};
/* Aliases for ABI-independent registers. */
const struct register_alias mips_register_aliases[] = {
/* The architecture manuals specify these ABI-independent names for
the GPRs. */
#define R(n) { "r" #n, n }
R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
#undef R
/* k0 and k1 are sometimes called these instead (for "kernel
temp"). */
{ "kt0", 26 },
{ "kt1", 27 },
/* This is the traditional GDB name for the CP0 status register. */
{ "sr", MIPS_PS_REGNUM },
/* This is the traditional GDB name for the CP0 BadVAddr register. */
{ "bad", MIPS_EMBED_BADVADDR_REGNUM },
/* This is the traditional GDB name for the FCSR. */
{ "fsr", MIPS_EMBED_FP0_REGNUM + 32 }
};
const struct register_alias mips_numeric_register_aliases[] = {
#define R(n) { #n, n }
R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
#undef R
};
#ifndef MIPS_DEFAULT_FPU_TYPE
#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
#endif
static int mips_fpu_type_auto = 1;
static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
static unsigned int mips_debug = 0;
/* Properties (for struct target_desc) describing the g/G packet
layout. */
#define PROPERTY_GP32 "internal: transfers-32bit-registers"
#define PROPERTY_GP64 "internal: transfers-64bit-registers"
struct target_desc *mips_tdesc_gp32;
struct target_desc *mips_tdesc_gp64;
const struct mips_regnum *
mips_regnum (struct gdbarch *gdbarch)
{
return gdbarch_tdep (gdbarch)->regnum;
}
static int
mips_fpa0_regnum (struct gdbarch *gdbarch)
{
return mips_regnum (gdbarch)->fp0 + 12;
}
/* Return 1 if REGNUM refers to a floating-point general register, raw
or cooked. Otherwise return 0. */
static int
mips_float_register_p (struct gdbarch *gdbarch, int regnum)
{
int rawnum = regnum % gdbarch_num_regs (gdbarch);
return (rawnum >= mips_regnum (gdbarch)->fp0
&& rawnum < mips_regnum (gdbarch)->fp0 + 32);
}
#define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
== MIPS_ABI_EABI32 \
|| gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
#define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
(gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
#define MIPS_LAST_ARG_REGNUM(gdbarch) \
(gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
#define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
/* Return the MIPS ABI associated with GDBARCH. */
enum mips_abi
mips_abi (struct gdbarch *gdbarch)
{
return gdbarch_tdep (gdbarch)->mips_abi;
}
int
mips_isa_regsize (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* If we know how big the registers are, use that size. */
if (tdep->register_size_valid_p)
return tdep->register_size;
/* Fall back to the previous behavior. */
return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
/ gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
}
/* Return the currently configured (or set) saved register size. */
unsigned int
mips_abi_regsize (struct gdbarch *gdbarch)
{
switch (mips_abi (gdbarch))
{
case MIPS_ABI_EABI32:
case MIPS_ABI_O32:
return 4;
case MIPS_ABI_N32:
case MIPS_ABI_N64:
case MIPS_ABI_O64:
case MIPS_ABI_EABI64:
return 8;
case MIPS_ABI_UNKNOWN:
case MIPS_ABI_LAST:
default:
internal_error (__FILE__, __LINE__, _("bad switch"));
}
}
/* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
are some functions to handle addresses associated with compressed
code including but not limited to testing, setting, or clearing
bit 0 of such addresses. */
/* Return one iff compressed code is the MIPS16 instruction set. */
static int
is_mips16_isa (struct gdbarch *gdbarch)
{
return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16;
}
/* Return one iff compressed code is the microMIPS instruction set. */
static int
is_micromips_isa (struct gdbarch *gdbarch)
{
return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS;
}
/* Return one iff ADDR denotes compressed code. */
static int
is_compact_addr (CORE_ADDR addr)
{
return ((addr) & 1);
}
/* Return one iff ADDR denotes standard ISA code. */
static int
is_mips_addr (CORE_ADDR addr)
{
return !is_compact_addr (addr);
}
/* Return one iff ADDR denotes MIPS16 code. */
static int
is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
{
return is_compact_addr (addr) && is_mips16_isa (gdbarch);
}
/* Return one iff ADDR denotes microMIPS code. */
static int
is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr)
{
return is_compact_addr (addr) && is_micromips_isa (gdbarch);
}
/* Strip the ISA (compression) bit off from ADDR. */
static CORE_ADDR
unmake_compact_addr (CORE_ADDR addr)
{
return ((addr) & ~(CORE_ADDR) 1);
}
/* Add the ISA (compression) bit to ADDR. */
static CORE_ADDR
make_compact_addr (CORE_ADDR addr)
{
return ((addr) | (CORE_ADDR) 1);
}
/* Extern version of unmake_compact_addr; we use a separate function
so that unmake_compact_addr can be inlined throughout this file. */
CORE_ADDR
mips_unmake_compact_addr (CORE_ADDR addr)
{
return unmake_compact_addr (addr);
}
/* Functions for setting and testing a bit in a minimal symbol that
marks it as MIPS16 or microMIPS function. The MSB of the minimal
symbol's "info" field is used for this purpose.
gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
"special", i.e. refers to a MIPS16 or microMIPS function, and sets
one of the "special" bits in a minimal symbol to mark it accordingly.
The test checks an ELF-private flag that is valid for true function
symbols only; for synthetic symbols such as for PLT stubs that have
no ELF-private part at all the MIPS BFD backend arranges for this
information to be carried in the asymbol's udata field instead.
msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
in a minimal symbol. */
static void
mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
{
elf_symbol_type *elfsym = (elf_symbol_type *) sym;
unsigned char st_other;
if ((sym->flags & BSF_SYNTHETIC) == 0)
st_other = elfsym->internal_elf_sym.st_other;
else if ((sym->flags & BSF_FUNCTION) != 0)
st_other = sym->udata.i;
else
return;
if (ELF_ST_IS_MICROMIPS (st_other))
{
MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1;
SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
}
else if (ELF_ST_IS_MIPS16 (st_other))
{
MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1;
SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
}
}
/* Return one iff MSYM refers to standard ISA code. */
static int
msymbol_is_mips (struct minimal_symbol *msym)
{
return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym)
| MSYMBOL_TARGET_FLAG_MICROMIPS (msym));
}
/* Return one iff MSYM refers to MIPS16 code. */
static int
msymbol_is_mips16 (struct minimal_symbol *msym)
{
return MSYMBOL_TARGET_FLAG_MIPS16 (msym);
}
/* Return one iff MSYM refers to microMIPS code. */
static int
msymbol_is_micromips (struct minimal_symbol *msym)
{
return MSYMBOL_TARGET_FLAG_MICROMIPS (msym);
}
/* Set the ISA bit in the main symbol too, complementing the corresponding
minimal symbol setting and reflecting the run-time value of the symbol.
The need for comes from the ISA bit having been cleared as code in
`_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
`st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
of symbols referring to compressed code different in GDB to the values
used by actual code. That in turn makes them evaluate incorrectly in
expressions, producing results different to what the same expressions
yield when compiled into the program being debugged. */
static void
mips_make_symbol_special (struct symbol *sym, struct objfile *objfile)
{
if (SYMBOL_CLASS (sym) == LOC_BLOCK)
{
/* We are in symbol reading so it is OK to cast away constness. */
struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym);
CORE_ADDR compact_block_start;
struct bound_minimal_symbol msym;
compact_block_start = BLOCK_START (block) | 1;
msym = lookup_minimal_symbol_by_pc (compact_block_start);
if (msym.minsym && !msymbol_is_mips (msym.minsym))
{
BLOCK_START (block) = compact_block_start;
}
}
}
/* XFER a value from the big/little/left end of the register.
Depending on the size of the value it might occupy the entire
register or just part of it. Make an allowance for this, aligning
things accordingly. */
static void
mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache,
int reg_num, int length,
enum bfd_endian endian, gdb_byte *in,
const gdb_byte *out, int buf_offset)
{
int reg_offset = 0;
gdb_assert (reg_num >= gdbarch_num_regs (gdbarch));
/* Need to transfer the left or right part of the register, based on
the targets byte order. */
switch (endian)
{
case BFD_ENDIAN_BIG:
reg_offset = register_size (gdbarch, reg_num) - length;
break;
case BFD_ENDIAN_LITTLE:
reg_offset = 0;
break;
case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
reg_offset = 0;
break;
default:
internal_error (__FILE__, __LINE__, _("bad switch"));
}
if (mips_debug)
fprintf_unfiltered (gdb_stderr,
"xfer $%d, reg offset %d, buf offset %d, length %d, ",
reg_num, reg_offset, buf_offset, length);
if (mips_debug && out != NULL)
{
int i;
fprintf_unfiltered (gdb_stdlog, "out ");
for (i = 0; i < length; i++)
fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
}
if (in != NULL)
regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
in + buf_offset);
if (out != NULL)
regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
out + buf_offset);
if (mips_debug && in != NULL)
{
int i;
fprintf_unfiltered (gdb_stdlog, "in ");
for (i = 0; i < length; i++)
fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
}
if (mips_debug)
fprintf_unfiltered (gdb_stdlog, "\n");
}
/* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
compatiblity mode. A return value of 1 means that we have
physical 64-bit registers, but should treat them as 32-bit registers. */
static int
mips2_fp_compat (struct frame_info *frame)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
/* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
meaningful. */
if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4)
return 0;
#if 0
/* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
in all the places we deal with FP registers. PR gdb/413. */
/* Otherwise check the FR bit in the status register - it controls
the FP compatiblity mode. If it is clear we are in compatibility
mode. */
if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0)
return 1;
#endif
return 0;
}
#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
/* The list of available "set mips " and "show mips " commands. */
static struct cmd_list_element *setmipscmdlist = NULL;
static struct cmd_list_element *showmipscmdlist = NULL;
/* Integer registers 0 thru 31 are handled explicitly by
mips_register_name(). Processor specific registers 32 and above
are listed in the following tables. */
enum
{ NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
/* Generic MIPS. */
static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
"sr", "lo", "hi", "bad", "cause", "pc",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"fsr", "fir",
};
/* Names of IDT R3041 registers. */
static const char *mips_r3041_reg_names[] = {
"sr", "lo", "hi", "bad", "cause", "pc",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"fsr", "fir", "", /*"fp" */ "",
"", "", "bus", "ccfg", "", "", "", "",
"", "", "port", "cmp", "", "", "epc", "prid",
};
/* Names of tx39 registers. */
static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
"sr", "lo", "hi", "bad", "cause", "pc",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "config", "cache", "debug", "depc", "epc",
};
/* Names of IRIX registers. */
static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"pc", "cause", "bad", "hi", "lo", "fsr", "fir"
};
/* Names of registers with Linux kernels. */
static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
"sr", "lo", "hi", "bad", "cause", "pc",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"fsr", "fir"
};
/* Return the name of the register corresponding to REGNO. */
static const char *
mips_register_name (struct gdbarch *gdbarch, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* GPR names for all ABIs other than n32/n64. */
static char *mips_gpr_names[] = {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
};
/* GPR names for n32 and n64 ABIs. */
static char *mips_n32_n64_gpr_names[] = {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
enum mips_abi abi = mips_abi (gdbarch);
/* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
but then don't make the raw register names visible. This (upper)
range of user visible register numbers are the pseudo-registers.
This approach was adopted accommodate the following scenario:
It is possible to debug a 64-bit device using a 32-bit
programming model. In such instances, the raw registers are
configured to be 64-bits wide, while the pseudo registers are
configured to be 32-bits wide. The registers that the user
sees - the pseudo registers - match the users expectations
given the programming model being used. */
int rawnum = regno % gdbarch_num_regs (gdbarch);
if (regno < gdbarch_num_regs (gdbarch))
return "";
/* The MIPS integer registers are always mapped from 0 to 31. The
names of the registers (which reflects the conventions regarding
register use) vary depending on the ABI. */
if (0 <= rawnum && rawnum < 32)
{
if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
return mips_n32_n64_gpr_names[rawnum];
else
return mips_gpr_names[rawnum];
}
else if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
return tdesc_register_name (gdbarch, rawnum);
else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch))
{
gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
if (tdep->mips_processor_reg_names[rawnum - 32])
return tdep->mips_processor_reg_names[rawnum - 32];
return "";
}
else
internal_error (__FILE__, __LINE__,
_("mips_register_name: bad register number %d"), rawnum);
}
/* Return the groups that a MIPS register can be categorised into. */
static int
mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *reggroup)
{
int vector_p;
int float_p;
int raw_p;
int rawnum = regnum % gdbarch_num_regs (gdbarch);
int pseudo = regnum / gdbarch_num_regs (gdbarch);
if (reggroup == all_reggroup)
return pseudo;
vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
/* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
(gdbarch), as not all architectures are multi-arch. */
raw_p = rawnum < gdbarch_num_regs (gdbarch);
if (gdbarch_register_name (gdbarch, regnum) == NULL
|| gdbarch_register_name (gdbarch, regnum)[0] == '\0')
return 0;
if (reggroup == float_reggroup)
return float_p && pseudo;
if (reggroup == vector_reggroup)
return vector_p && pseudo;
if (reggroup == general_reggroup)
return (!vector_p && !float_p) && pseudo;
/* Save the pseudo registers. Need to make certain that any code
extracting register values from a saved register cache also uses
pseudo registers. */
if (reggroup == save_reggroup)
return raw_p && pseudo;
/* Restore the same pseudo register. */
if (reggroup == restore_reggroup)
return raw_p && pseudo;
return 0;
}
/* Return the groups that a MIPS register can be categorised into.
This version is only used if we have a target description which
describes real registers (and their groups). */
static int
mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *reggroup)
{
int rawnum = regnum % gdbarch_num_regs (gdbarch);
int pseudo = regnum / gdbarch_num_regs (gdbarch);
int ret;
/* Only save, restore, and display the pseudo registers. Need to
make certain that any code extracting register values from a
saved register cache also uses pseudo registers.
Note: saving and restoring the pseudo registers is slightly
strange; if we have 64 bits, we should save and restore all
64 bits. But this is hard and has little benefit. */
if (!pseudo)
return 0;
ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup);
if (ret != -1)
return ret;
return mips_register_reggroup_p (gdbarch, regnum, reggroup);
}
/* Map the symbol table registers which live in the range [1 *
gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
registers. Take care of alignment and size problems. */
static enum register_status
mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
int cookednum, gdb_byte *buf)
{
int rawnum = cookednum % gdbarch_num_regs (gdbarch);
gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
&& cookednum < 2 * gdbarch_num_regs (gdbarch));
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
return regcache_raw_read (regcache, rawnum, buf);
else if (register_size (gdbarch, rawnum) >
register_size (gdbarch, cookednum))
{
if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
return regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
else
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
LONGEST regval;
enum register_status status;
status = regcache_raw_read_signed (regcache, rawnum, ®val);
if (status == REG_VALID)
store_signed_integer (buf, 4, byte_order, regval);
return status;
}
}
else
internal_error (__FILE__, __LINE__, _("bad register size"));
}
static void
mips_pseudo_register_write (struct gdbarch *gdbarch,
struct regcache *regcache, int cookednum,
const gdb_byte *buf)
{
int rawnum = cookednum % gdbarch_num_regs (gdbarch);
gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
&& cookednum < 2 * gdbarch_num_regs (gdbarch));
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
regcache_raw_write (regcache, rawnum, buf);
else if (register_size (gdbarch, rawnum) >
register_size (gdbarch, cookednum))
{
if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
else
{
/* Sign extend the shortened version of the register prior
to placing it in the raw register. This is required for
some mips64 parts in order to avoid unpredictable behavior. */
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
LONGEST regval = extract_signed_integer (buf, 4, byte_order);
regcache_raw_write_signed (regcache, rawnum, regval);
}
}
else
internal_error (__FILE__, __LINE__, _("bad register size"));
}
static int
mips_ax_pseudo_register_collect (struct gdbarch *gdbarch,
struct agent_expr *ax, int reg)
{
int rawnum = reg % gdbarch_num_regs (gdbarch);
gdb_assert (reg >= gdbarch_num_regs (gdbarch)
&& reg < 2 * gdbarch_num_regs (gdbarch));
ax_reg_mask (ax, rawnum);
return 0;
}
static int
mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
struct agent_expr *ax, int reg)
{
int rawnum = reg % gdbarch_num_regs (gdbarch);
gdb_assert (reg >= gdbarch_num_regs (gdbarch)
&& reg < 2 * gdbarch_num_regs (gdbarch));
if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg))
{
ax_reg (ax, rawnum);
if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg))
{
if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
|| gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG)
{
ax_const_l (ax, 32);
ax_simple (ax, aop_lsh);
}
ax_const_l (ax, 32);
ax_simple (ax, aop_rsh_signed);
}
}
else
internal_error (__FILE__, __LINE__, _("bad register size"));
return 0;
}
/* Table to translate 3-bit register field to actual register number. */
static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
/* Heuristic_proc_start may hunt through the text section for a long
time across a 2400 baud serial line. Allows the user to limit this
search. */
static int heuristic_fence_post = 0;
/* Number of bytes of storage in the actual machine representation for
register N. NOTE: This defines the pseudo register type so need to
rebuild the architecture vector. */
static int mips64_transfers_32bit_regs_p = 0;
static void
set_mips64_transfers_32bit_regs (char *args, int from_tty,
struct cmd_list_element *c)
{
struct gdbarch_info info;
gdbarch_info_init (&info);
/* FIXME: cagney/2003-11-15: Should be setting a field in "info"
instead of relying on globals. Doing that would let generic code
handle the search for this specific architecture. */
if (!gdbarch_update_p (info))
{
mips64_transfers_32bit_regs_p = 0;
error (_("32-bit compatibility mode not supported"));
}
}
/* Convert to/from a register and the corresponding memory value. */
/* This predicate tests for the case of an 8 byte floating point
value that is being transferred to or from a pair of floating point
registers each of which are (or are considered to be) only 4 bytes
wide. */
static int
mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum,
struct type *type)
{
return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
&& register_size (gdbarch, regnum) == 4
&& mips_float_register_p (gdbarch, regnum)
&& TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
}
/* This predicate tests for the case of a value of less than 8
bytes in width that is being transfered to or from an 8 byte
general purpose register. */
static int
mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum,
struct type *type)
{
int num_regs = gdbarch_num_regs (gdbarch);
return (register_size (gdbarch, regnum) == 8
&& regnum % num_regs > 0 && regnum % num_regs < 32
&& TYPE_LENGTH (type) < 8);
}
static int
mips_convert_register_p (struct gdbarch *gdbarch,
int regnum, struct type *type)
{
return (mips_convert_register_float_case_p (gdbarch, regnum, type)
|| mips_convert_register_gpreg_case_p (gdbarch, regnum, type));
}
static int
mips_register_to_value (struct frame_info *frame, int regnum,
struct type *type, gdb_byte *to,
int *optimizedp, int *unavailablep)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
if (mips_convert_register_float_case_p (gdbarch, regnum, type))
{
get_frame_register (frame, regnum + 0, to + 4);
get_frame_register (frame, regnum + 1, to + 0);
if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4,
optimizedp, unavailablep))
return 0;
if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0,
optimizedp, unavailablep))
return 0;
*optimizedp = *unavailablep = 0;
return 1;
}
else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
{
int len = TYPE_LENGTH (type);
CORE_ADDR offset;
offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0;
if (!get_frame_register_bytes (frame, regnum, offset, len, to,
optimizedp, unavailablep))
return 0;
*optimizedp = *unavailablep = 0;
return 1;
}
else
{
internal_error (__FILE__, __LINE__,
_("mips_register_to_value: unrecognized case"));
}
}
static void
mips_value_to_register (struct frame_info *frame, int regnum,
struct type *type, const gdb_byte *from)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
if (mips_convert_register_float_case_p (gdbarch, regnum, type))
{
put_frame_register (frame, regnum + 0, from + 4);
put_frame_register (frame, regnum + 1, from + 0);
}
else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
{
gdb_byte fill[8];
int len = TYPE_LENGTH (type);
/* Sign extend values, irrespective of type, that are stored to
a 64-bit general purpose register. (32-bit unsigned values
are stored as signed quantities within a 64-bit register.
When performing an operation, in compiled code, that combines
a 32-bit unsigned value with a signed 64-bit value, a type
conversion is first performed that zeroes out the high 32 bits.) */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
if (from[0] & 0x80)
store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1);
else
store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0);
put_frame_register_bytes (frame, regnum, 0, 8 - len, fill);
put_frame_register_bytes (frame, regnum, 8 - len, len, from);
}
else
{
if (from[len-1] & 0x80)
store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1);
else
store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0);
put_frame_register_bytes (frame, regnum, 0, len, from);
put_frame_register_bytes (frame, regnum, len, 8 - len, fill);
}
}
else
{
internal_error (__FILE__, __LINE__,
_("mips_value_to_register: unrecognized case"));
}
}