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cris-tdep.c
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/* Target dependent code for CRIS, for GDB, the GNU debugger.
Copyright (C) 2001-2015 Free Software Foundation, Inc.
Contributed by Axis Communications AB.
Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "dwarf2-frame.h"
#include "symtab.h"
#include "inferior.h"
#include "gdbtypes.h"
#include "gdbcore.h"
#include "gdbcmd.h"
#include "target.h"
#include "value.h"
#include "opcode/cris.h"
#include "osabi.h"
#include "arch-utils.h"
#include "regcache.h"
#include "objfiles.h"
#include "solib.h" /* Support for shared libraries. */
#include "solib-svr4.h"
#include "dis-asm.h"
#include "cris-tdep.h"
enum cris_num_regs
{
/* There are no floating point registers. Used in gdbserver low-linux.c. */
NUM_FREGS = 0,
/* There are 16 general registers. */
NUM_GENREGS = 16,
/* There are 16 special registers. */
NUM_SPECREGS = 16,
/* CRISv32 has a pseudo PC register, not noted here. */
/* CRISv32 has 16 support registers. */
NUM_SUPPREGS = 16
};
/* Register numbers of various important registers.
CRIS_FP_REGNUM Contains address of executing stack frame.
STR_REGNUM Contains the address of structure return values.
RET_REGNUM Contains the return value when shorter than or equal to 32 bits
ARG1_REGNUM Contains the first parameter to a function.
ARG2_REGNUM Contains the second parameter to a function.
ARG3_REGNUM Contains the third parameter to a function.
ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack.
gdbarch_sp_regnum Contains address of top of stack.
gdbarch_pc_regnum Contains address of next instruction.
SRP_REGNUM Subroutine return pointer register.
BRP_REGNUM Breakpoint return pointer register. */
enum cris_regnums
{
/* Enums with respect to the general registers, valid for all
CRIS versions. The frame pointer is always in R8. */
CRIS_FP_REGNUM = 8,
/* ABI related registers. */
STR_REGNUM = 9,
RET_REGNUM = 10,
ARG1_REGNUM = 10,
ARG2_REGNUM = 11,
ARG3_REGNUM = 12,
ARG4_REGNUM = 13,
/* Registers which happen to be common. */
VR_REGNUM = 17,
MOF_REGNUM = 23,
SRP_REGNUM = 27,
/* CRISv10 et al. specific registers. */
P0_REGNUM = 16,
P4_REGNUM = 20,
CCR_REGNUM = 21,
P8_REGNUM = 24,
IBR_REGNUM = 25,
IRP_REGNUM = 26,
BAR_REGNUM = 28,
DCCR_REGNUM = 29,
BRP_REGNUM = 30,
USP_REGNUM = 31,
/* CRISv32 specific registers. */
ACR_REGNUM = 15,
BZ_REGNUM = 16,
PID_REGNUM = 18,
SRS_REGNUM = 19,
WZ_REGNUM = 20,
EXS_REGNUM = 21,
EDA_REGNUM = 22,
DZ_REGNUM = 24,
EBP_REGNUM = 25,
ERP_REGNUM = 26,
NRP_REGNUM = 28,
CCS_REGNUM = 29,
CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */
SPC_REGNUM = 31,
CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */
S0_REGNUM = 33,
S1_REGNUM = 34,
S2_REGNUM = 35,
S3_REGNUM = 36,
S4_REGNUM = 37,
S5_REGNUM = 38,
S6_REGNUM = 39,
S7_REGNUM = 40,
S8_REGNUM = 41,
S9_REGNUM = 42,
S10_REGNUM = 43,
S11_REGNUM = 44,
S12_REGNUM = 45,
S13_REGNUM = 46,
S14_REGNUM = 47,
S15_REGNUM = 48,
};
extern const struct cris_spec_reg cris_spec_regs[];
/* CRIS version, set via the user command 'set cris-version'. Affects
register names and sizes. */
static unsigned int usr_cmd_cris_version;
/* Indicates whether to trust the above variable. */
static int usr_cmd_cris_version_valid = 0;
static const char cris_mode_normal[] = "normal";
static const char cris_mode_guru[] = "guru";
static const char *const cris_modes[] = {
cris_mode_normal,
cris_mode_guru,
0
};
/* CRIS mode, set via the user command 'set cris-mode'. Affects
type of break instruction among other things. */
static const char *usr_cmd_cris_mode = cris_mode_normal;
/* Whether to make use of Dwarf-2 CFI (default on). */
static int usr_cmd_cris_dwarf2_cfi = 1;
/* Sigtramp identification code copied from i386-linux-tdep.c. */
#define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */
#define SIGTRAMP_OFFSET0 0
#define SIGTRAMP_INSN1 0xe93d /* break 13 */
#define SIGTRAMP_OFFSET1 4
static const unsigned short sigtramp_code[] =
{
SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */
SIGTRAMP_INSN1 /* break 13 */
};
#define SIGTRAMP_LEN (sizeof sigtramp_code)
/* Note: same length as normal sigtramp code. */
static const unsigned short rt_sigtramp_code[] =
{
SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */
SIGTRAMP_INSN1 /* break 13 */
};
/* If PC is in a sigtramp routine, return the address of the start of
the routine. Otherwise, return 0. */
static CORE_ADDR
cris_sigtramp_start (struct frame_info *this_frame)
{
CORE_ADDR pc = get_frame_pc (this_frame);
gdb_byte buf[SIGTRAMP_LEN];
if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
return 0;
if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
{
if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
return 0;
pc -= SIGTRAMP_OFFSET1;
if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
return 0;
}
if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0)
return 0;
return pc;
}
/* If PC is in a RT sigtramp routine, return the address of the start of
the routine. Otherwise, return 0. */
static CORE_ADDR
cris_rt_sigtramp_start (struct frame_info *this_frame)
{
CORE_ADDR pc = get_frame_pc (this_frame);
gdb_byte buf[SIGTRAMP_LEN];
if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
return 0;
if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0)
{
if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1)
return 0;
pc -= SIGTRAMP_OFFSET1;
if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN))
return 0;
}
if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0)
return 0;
return pc;
}
/* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine,
return the address of the associated sigcontext structure. */
static CORE_ADDR
cris_sigcontext_addr (struct frame_info *this_frame)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR pc;
CORE_ADDR sp;
gdb_byte buf[4];
get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
sp = extract_unsigned_integer (buf, 4, byte_order);
/* Look for normal sigtramp frame first. */
pc = cris_sigtramp_start (this_frame);
if (pc)
{
/* struct signal_frame (arch/cris/kernel/signal.c) contains
struct sigcontext as its first member, meaning the SP points to
it already. */
return sp;
}
pc = cris_rt_sigtramp_start (this_frame);
if (pc)
{
/* struct rt_signal_frame (arch/cris/kernel/signal.c) contains
a struct ucontext, which in turn contains a struct sigcontext.
Magic digging:
4 + 4 + 128 to struct ucontext, then
4 + 4 + 12 to struct sigcontext. */
return (sp + 156);
}
error (_("Couldn't recognize signal trampoline."));
return 0;
}
struct cris_unwind_cache
{
/* The previous frame's inner most stack address. Used as this
frame ID's stack_addr. */
CORE_ADDR prev_sp;
/* The frame's base, optionally used by the high-level debug info. */
CORE_ADDR base;
int size;
/* How far the SP and r8 (FP) have been offset from the start of
the stack frame (as defined by the previous frame's stack
pointer). */
LONGEST sp_offset;
LONGEST r8_offset;
int uses_frame;
/* From old frame_extra_info struct. */
CORE_ADDR return_pc;
int leaf_function;
/* Table indicating the location of each and every register. */
struct trad_frame_saved_reg *saved_regs;
};
static struct cris_unwind_cache *
cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame,
void **this_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
struct cris_unwind_cache *info;
CORE_ADDR addr;
gdb_byte buf[4];
int i;
if ((*this_cache))
return (*this_cache);
info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
(*this_cache) = info;
info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
/* Zero all fields. */
info->prev_sp = 0;
info->base = 0;
info->size = 0;
info->sp_offset = 0;
info->r8_offset = 0;
info->uses_frame = 0;
info->return_pc = 0;
info->leaf_function = 0;
get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf);
info->base = extract_unsigned_integer (buf, 4, byte_order);
addr = cris_sigcontext_addr (this_frame);
/* Layout of the sigcontext struct:
struct sigcontext {
struct pt_regs regs;
unsigned long oldmask;
unsigned long usp;
}; */
if (tdep->cris_version == 10)
{
/* R0 to R13 are stored in reverse order at offset (2 * 4) in
struct pt_regs. */
for (i = 0; i <= 13; i++)
info->saved_regs[i].addr = addr + ((15 - i) * 4);
info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
/* Note: IRP is off by 2 at this point. There's no point in correcting
it though since that will mean that the backtrace will show a PC
different from what is shown when stopped. */
info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
info->saved_regs[gdbarch_pc_regnum (gdbarch)]
= info->saved_regs[IRP_REGNUM];
info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4);
}
else
{
/* CRISv32. */
/* R0 to R13 are stored in order at offset (1 * 4) in
struct pt_regs. */
for (i = 0; i <= 13; i++)
info->saved_regs[i].addr = addr + ((i + 1) * 4);
info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
/* FIXME: If ERP is in a delay slot at this point then the PC will
be wrong at this point. This problem manifests itself in the
sigaltstack.exp test case, which occasionally generates FAILs when
the signal is received while in a delay slot.
This could be solved by a couple of read_memory_unsigned_integer and a
trad_frame_set_value. */
info->saved_regs[gdbarch_pc_regnum (gdbarch)]
= info->saved_regs[ERP_REGNUM];
info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr
= addr + (25 * 4);
}
return info;
}
static void
cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache,
struct frame_id *this_id)
{
struct cris_unwind_cache *cache =
cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
(*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame));
}
/* Forward declaration. */
static struct value *cris_frame_prev_register (struct frame_info *this_frame,
void **this_cache, int regnum);
static struct value *
cris_sigtramp_frame_prev_register (struct frame_info *this_frame,
void **this_cache, int regnum)
{
/* Make sure we've initialized the cache. */
cris_sigtramp_frame_unwind_cache (this_frame, this_cache);
return cris_frame_prev_register (this_frame, this_cache, regnum);
}
static int
cris_sigtramp_frame_sniffer (const struct frame_unwind *self,
struct frame_info *this_frame,
void **this_cache)
{
if (cris_sigtramp_start (this_frame)
|| cris_rt_sigtramp_start (this_frame))
return 1;
return 0;
}
static const struct frame_unwind cris_sigtramp_frame_unwind =
{
SIGTRAMP_FRAME,
default_frame_unwind_stop_reason,
cris_sigtramp_frame_this_id,
cris_sigtramp_frame_prev_register,
NULL,
cris_sigtramp_frame_sniffer
};
static int
crisv32_single_step_through_delay (struct gdbarch *gdbarch,
struct frame_info *this_frame)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
ULONGEST erp;
int ret = 0;
if (tdep->cris_mode == cris_mode_guru)
erp = get_frame_register_unsigned (this_frame, NRP_REGNUM);
else
erp = get_frame_register_unsigned (this_frame, ERP_REGNUM);
if (erp & 0x1)
{
/* In delay slot - check if there's a breakpoint at the preceding
instruction. */
if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1))
ret = 1;
}
return ret;
}
/* The instruction environment needed to find single-step breakpoints. */
typedef
struct instruction_environment
{
unsigned long reg[NUM_GENREGS];
unsigned long preg[NUM_SPECREGS];
unsigned long branch_break_address;
unsigned long delay_slot_pc;
unsigned long prefix_value;
int branch_found;
int prefix_found;
int invalid;
int slot_needed;
int delay_slot_pc_active;
int xflag_found;
int disable_interrupt;
int byte_order;
} inst_env_type;
/* Machine-dependencies in CRIS for opcodes. */
/* Instruction sizes. */
enum cris_instruction_sizes
{
INST_BYTE_SIZE = 0,
INST_WORD_SIZE = 1,
INST_DWORD_SIZE = 2
};
/* Addressing modes. */
enum cris_addressing_modes
{
REGISTER_MODE = 1,
INDIRECT_MODE = 2,
AUTOINC_MODE = 3
};
/* Prefix addressing modes. */
enum cris_prefix_addressing_modes
{
PREFIX_INDEX_MODE = 2,
PREFIX_ASSIGN_MODE = 3,
/* Handle immediate byte offset addressing mode prefix format. */
PREFIX_OFFSET_MODE = 2
};
/* Masks for opcodes. */
enum cris_opcode_masks
{
BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1,
SIGNED_EXTEND_BIT_MASK = 0x2,
SIGNED_BYTE_MASK = 0x80,
SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00,
SIGNED_WORD_MASK = 0x8000,
SIGNED_WORD_EXTEND_MASK = 0xFFFF0000,
SIGNED_DWORD_MASK = 0x80000000,
SIGNED_QUICK_VALUE_MASK = 0x20,
SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0
};
/* Functions for opcodes. The general form of the ETRAX 16-bit instruction:
Bit 15 - 12 Operand2
11 - 10 Mode
9 - 6 Opcode
5 - 4 Size
3 - 0 Operand1 */
static int
cris_get_operand2 (unsigned short insn)
{
return ((insn & 0xF000) >> 12);
}
static int
cris_get_mode (unsigned short insn)
{
return ((insn & 0x0C00) >> 10);
}
static int
cris_get_opcode (unsigned short insn)
{
return ((insn & 0x03C0) >> 6);
}
static int
cris_get_size (unsigned short insn)
{
return ((insn & 0x0030) >> 4);
}
static int
cris_get_operand1 (unsigned short insn)
{
return (insn & 0x000F);
}
/* Additional functions in order to handle opcodes. */
static int
cris_get_quick_value (unsigned short insn)
{
return (insn & 0x003F);
}
static int
cris_get_bdap_quick_offset (unsigned short insn)
{
return (insn & 0x00FF);
}
static int
cris_get_branch_short_offset (unsigned short insn)
{
return (insn & 0x00FF);
}
static int
cris_get_asr_shift_steps (unsigned long value)
{
return (value & 0x3F);
}
static int
cris_get_clear_size (unsigned short insn)
{
return ((insn) & 0xC000);
}
static int
cris_is_signed_extend_bit_on (unsigned short insn)
{
return (((insn) & 0x20) == 0x20);
}
static int
cris_is_xflag_bit_on (unsigned short insn)
{
return (((insn) & 0x1000) == 0x1000);
}
static void
cris_set_size_to_dword (unsigned short *insn)
{
*insn &= 0xFFCF;
*insn |= 0x20;
}
static signed char
cris_get_signed_offset (unsigned short insn)
{
return ((signed char) (insn & 0x00FF));
}
/* Calls an op function given the op-type, working on the insn and the
inst_env. */
static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short,
inst_env_type *);
static struct gdbarch *cris_gdbarch_init (struct gdbarch_info,
struct gdbarch_list *);
static void cris_dump_tdep (struct gdbarch *, struct ui_file *);
static void set_cris_version (char *ignore_args, int from_tty,
struct cmd_list_element *c);
static void set_cris_mode (char *ignore_args, int from_tty,
struct cmd_list_element *c);
static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty,
struct cmd_list_element *c);
static CORE_ADDR cris_scan_prologue (CORE_ADDR pc,
struct frame_info *this_frame,
struct cris_unwind_cache *info);
static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc,
struct frame_info *this_frame,
struct cris_unwind_cache *info);
static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch,
struct frame_info *next_frame);
static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch,
struct frame_info *next_frame);
/* When arguments must be pushed onto the stack, they go on in reverse
order. The below implements a FILO (stack) to do this.
Copied from d10v-tdep.c. */
struct stack_item
{
int len;
struct stack_item *prev;
void *data;
};
static struct stack_item *
push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len)
{
struct stack_item *si = XNEW (struct stack_item);
si->data = xmalloc (len);
si->len = len;
si->prev = prev;
memcpy (si->data, contents, len);
return si;
}
static struct stack_item *
pop_stack_item (struct stack_item *si)
{
struct stack_item *dead = si;
si = si->prev;
xfree (dead->data);
xfree (dead);
return si;
}
/* Put here the code to store, into fi->saved_regs, the addresses of
the saved registers of frame described by FRAME_INFO. This
includes special registers such as pc and fp saved in special ways
in the stack frame. sp is even more special: the address we return
for it IS the sp for the next frame. */
static struct cris_unwind_cache *
cris_frame_unwind_cache (struct frame_info *this_frame,
void **this_prologue_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
struct cris_unwind_cache *info;
if ((*this_prologue_cache))
return (*this_prologue_cache);
info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache);
(*this_prologue_cache) = info;
info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
/* Zero all fields. */
info->prev_sp = 0;
info->base = 0;
info->size = 0;
info->sp_offset = 0;
info->r8_offset = 0;
info->uses_frame = 0;
info->return_pc = 0;
info->leaf_function = 0;
/* Prologue analysis does the rest... */
if (tdep->cris_version == 32)
crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info);
else
cris_scan_prologue (get_frame_func (this_frame), this_frame, info);
return info;
}
/* Given a GDB frame, determine the address of the calling function's
frame. This will be used to create a new GDB frame struct. */
static void
cris_frame_this_id (struct frame_info *this_frame,
void **this_prologue_cache,
struct frame_id *this_id)
{
struct cris_unwind_cache *info
= cris_frame_unwind_cache (this_frame, this_prologue_cache);
CORE_ADDR base;
CORE_ADDR func;
struct frame_id id;
/* The FUNC is easy. */
func = get_frame_func (this_frame);
/* Hopefully the prologue analysis either correctly determined the
frame's base (which is the SP from the previous frame), or set
that base to "NULL". */
base = info->prev_sp;
if (base == 0)
return;
id = frame_id_build (base, func);
(*this_id) = id;
}
static struct value *
cris_frame_prev_register (struct frame_info *this_frame,
void **this_prologue_cache, int regnum)
{
struct cris_unwind_cache *info
= cris_frame_unwind_cache (this_frame, this_prologue_cache);
return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
}
/* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy
frame. The frame ID's base needs to match the TOS value saved by
save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */
static struct frame_id
cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
{
CORE_ADDR sp;
sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
return frame_id_build (sp, get_frame_pc (this_frame));
}
static CORE_ADDR
cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
{
/* Align to the size of an instruction (so that they can safely be
pushed onto the stack). */
return sp & ~3;
}
static CORE_ADDR
cris_push_dummy_code (struct gdbarch *gdbarch,
CORE_ADDR sp, CORE_ADDR funaddr,
struct value **args, int nargs,
struct type *value_type,
CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
struct regcache *regcache)
{
/* Allocate space sufficient for a breakpoint. */
sp = (sp - 4) & ~3;
/* Store the address of that breakpoint */
*bp_addr = sp;
/* CRIS always starts the call at the callee's entry point. */
*real_pc = funaddr;
return sp;
}
static CORE_ADDR
cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int stack_offset;
int argreg;
int argnum;
/* The function's arguments and memory allocated by gdb for the arguments to
point at reside in separate areas on the stack.
Both frame pointers grow toward higher addresses. */
CORE_ADDR fp_arg;
CORE_ADDR fp_mem;
struct stack_item *si = NULL;
/* Push the return address. */
regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr);
/* Are we returning a value using a structure return or a normal value
return? struct_addr is the address of the reserved space for the return
structure to be written on the stack. */
if (struct_return)
{
regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr);
}
/* Now load as many as possible of the first arguments into registers,
and push the rest onto the stack. */
argreg = ARG1_REGNUM;
stack_offset = 0;
for (argnum = 0; argnum < nargs; argnum++)
{
int len;
const gdb_byte *val;
int reg_demand;
int i;
len = TYPE_LENGTH (value_type (args[argnum]));
val = value_contents (args[argnum]);
/* How may registers worth of storage do we need for this argument? */
reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM))
{
/* Data passed by value. Fits in available register(s). */
for (i = 0; i < reg_demand; i++)
{
regcache_cooked_write (regcache, argreg, val);
argreg++;
val += 4;
}
}
else if (len <= (2 * 4) && argreg <= ARG4_REGNUM)
{
/* Data passed by value. Does not fit in available register(s).
Use the register(s) first, then the stack. */
for (i = 0; i < reg_demand; i++)
{
if (argreg <= ARG4_REGNUM)
{
regcache_cooked_write (regcache, argreg, val);
argreg++;
val += 4;
}
else
{
/* Push item for later so that pushed arguments
come in the right order. */
si = push_stack_item (si, val, 4);
val += 4;
}
}
}
else if (len > (2 * 4))
{
/* Data passed by reference. Push copy of data onto stack
and pass pointer to this copy as argument. */
sp = (sp - len) & ~3;
write_memory (sp, val, len);
if (argreg <= ARG4_REGNUM)
{
regcache_cooked_write_unsigned (regcache, argreg, sp);
argreg++;
}
else
{
gdb_byte buf[4];
store_unsigned_integer (buf, 4, byte_order, sp);
si = push_stack_item (si, buf, 4);
}
}
else
{
/* Data passed by value. No available registers. Put it on
the stack. */
si = push_stack_item (si, val, len);
}
}
while (si)
{
/* fp_arg must be word-aligned (i.e., don't += len) to match
the function prologue. */
sp = (sp - si->len) & ~3;
write_memory (sp, si->data, si->len);
si = pop_stack_item (si);
}
/* Finally, update the SP register. */
regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp);
return sp;
}
static const struct frame_unwind cris_frame_unwind =
{
NORMAL_FRAME,
default_frame_unwind_stop_reason,
cris_frame_this_id,
cris_frame_prev_register,
NULL,
default_frame_sniffer
};
static CORE_ADDR
cris_frame_base_address (struct frame_info *this_frame, void **this_cache)
{
struct cris_unwind_cache *info
= cris_frame_unwind_cache (this_frame, this_cache);
return info->base;
}
static const struct frame_base cris_frame_base =
{
&cris_frame_unwind,
cris_frame_base_address,
cris_frame_base_address,
cris_frame_base_address
};
/* Frames information. The definition of the struct frame_info is
CORE_ADDR frame
CORE_ADDR pc
enum frame_type type;
CORE_ADDR return_pc
int leaf_function
If the compilation option -fno-omit-frame-pointer is present the
variable frame will be set to the content of R8 which is the frame
pointer register.
The variable pc contains the address where execution is performed
in the present frame. The innermost frame contains the current content
of the register PC. All other frames contain the content of the
register PC in the next frame.
The variable `type' indicates the frame's type: normal, SIGTRAMP
(associated with a signal handler), dummy (associated with a dummy
frame).
The variable return_pc contains the address where execution should be
resumed when the present frame has finished, the return address.
The variable leaf_function is 1 if the return address is in the register
SRP, and 0 if it is on the stack.
Prologue instructions C-code.
The prologue may consist of (-fno-omit-frame-pointer)
1) 2)
push srp
push r8 push r8
move.d sp,r8 move.d sp,r8
subq X,sp subq X,sp
movem rY,[sp] movem rY,[sp]
move.S rZ,[r8-U] move.S rZ,[r8-U]
where 1 is a non-terminal function, and 2 is a leaf-function.
Note that this assumption is extremely brittle, and will break at the
slightest change in GCC's prologue.
If local variables are declared or register contents are saved on stack
the subq-instruction will be present with X as the number of bytes
needed for storage. The reshuffle with respect to r8 may be performed
with any size S (b, w, d) and any of the general registers Z={0..13}.
The offset U should be representable by a signed 8-bit value in all cases.