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aarch64-tdep.c
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/* Common target dependent code for GDB on AArch64 systems.
Copyright (C) 2009-2015 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "inferior.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "dis-asm.h"
#include "regcache.h"
#include "reggroups.h"
#include "doublest.h"
#include "value.h"
#include "arch-utils.h"
#include "osabi.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "objfiles.h"
#include "dwarf2-frame.h"
#include "gdbtypes.h"
#include "prologue-value.h"
#include "target-descriptions.h"
#include "user-regs.h"
#include "language.h"
#include "infcall.h"
#include "ax.h"
#include "ax-gdb.h"
#include "aarch64-tdep.h"
#include "elf-bfd.h"
#include "elf/aarch64.h"
#include "vec.h"
#include "record.h"
#include "record-full.h"
#include "features/aarch64.c"
/* Pseudo register base numbers. */
#define AARCH64_Q0_REGNUM 0
#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
/* The standard register names, and all the valid aliases for them. */
static const struct
{
const char *const name;
int regnum;
} aarch64_register_aliases[] =
{
/* 64-bit register names. */
{"fp", AARCH64_FP_REGNUM},
{"lr", AARCH64_LR_REGNUM},
{"sp", AARCH64_SP_REGNUM},
/* 32-bit register names. */
{"w0", AARCH64_X0_REGNUM + 0},
{"w1", AARCH64_X0_REGNUM + 1},
{"w2", AARCH64_X0_REGNUM + 2},
{"w3", AARCH64_X0_REGNUM + 3},
{"w4", AARCH64_X0_REGNUM + 4},
{"w5", AARCH64_X0_REGNUM + 5},
{"w6", AARCH64_X0_REGNUM + 6},
{"w7", AARCH64_X0_REGNUM + 7},
{"w8", AARCH64_X0_REGNUM + 8},
{"w9", AARCH64_X0_REGNUM + 9},
{"w10", AARCH64_X0_REGNUM + 10},
{"w11", AARCH64_X0_REGNUM + 11},
{"w12", AARCH64_X0_REGNUM + 12},
{"w13", AARCH64_X0_REGNUM + 13},
{"w14", AARCH64_X0_REGNUM + 14},
{"w15", AARCH64_X0_REGNUM + 15},
{"w16", AARCH64_X0_REGNUM + 16},
{"w17", AARCH64_X0_REGNUM + 17},
{"w18", AARCH64_X0_REGNUM + 18},
{"w19", AARCH64_X0_REGNUM + 19},
{"w20", AARCH64_X0_REGNUM + 20},
{"w21", AARCH64_X0_REGNUM + 21},
{"w22", AARCH64_X0_REGNUM + 22},
{"w23", AARCH64_X0_REGNUM + 23},
{"w24", AARCH64_X0_REGNUM + 24},
{"w25", AARCH64_X0_REGNUM + 25},
{"w26", AARCH64_X0_REGNUM + 26},
{"w27", AARCH64_X0_REGNUM + 27},
{"w28", AARCH64_X0_REGNUM + 28},
{"w29", AARCH64_X0_REGNUM + 29},
{"w30", AARCH64_X0_REGNUM + 30},
/* specials */
{"ip0", AARCH64_X0_REGNUM + 16},
{"ip1", AARCH64_X0_REGNUM + 17}
};
/* The required core 'R' registers. */
static const char *const aarch64_r_register_names[] =
{
/* These registers must appear in consecutive RAW register number
order and they must begin with AARCH64_X0_REGNUM! */
"x0", "x1", "x2", "x3",
"x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11",
"x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19",
"x20", "x21", "x22", "x23",
"x24", "x25", "x26", "x27",
"x28", "x29", "x30", "sp",
"pc", "cpsr"
};
/* The FP/SIMD 'V' registers. */
static const char *const aarch64_v_register_names[] =
{
/* These registers must appear in consecutive RAW register number
order and they must begin with AARCH64_V0_REGNUM! */
"v0", "v1", "v2", "v3",
"v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11",
"v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19",
"v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27",
"v28", "v29", "v30", "v31",
"fpsr",
"fpcr"
};
/* AArch64 prologue cache structure. */
struct aarch64_prologue_cache
{
/* The program counter at the start of the function. It is used to
identify this frame as a prologue frame. */
CORE_ADDR func;
/* The program counter at the time this frame was created; i.e. where
this function was called from. It is used to identify this frame as a
stub frame. */
CORE_ADDR prev_pc;
/* The stack pointer at the time this frame was created; i.e. the
caller's stack pointer when this function was called. It is used
to identify this frame. */
CORE_ADDR prev_sp;
/* Is the target available to read from? */
int available_p;
/* The frame base for this frame is just prev_sp - frame size.
FRAMESIZE is the distance from the frame pointer to the
initial stack pointer. */
int framesize;
/* The register used to hold the frame pointer for this frame. */
int framereg;
/* Saved register offsets. */
struct trad_frame_saved_reg *saved_regs;
};
/* Toggle this file's internal debugging dump. */
static int aarch64_debug;
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
{
fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
}
/* Extract a signed value from a bit field within an instruction
encoding.
INSN is the instruction opcode.
WIDTH specifies the width of the bit field to extract (in bits).
OFFSET specifies the least significant bit of the field where bits
are numbered zero counting from least to most significant. */
static int32_t
extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
{
unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
unsigned shift_r = sizeof (int32_t) * 8 - width;
return ((int32_t) insn << shift_l) >> shift_r;
}
/* Determine if specified bits within an instruction opcode matches a
specific pattern.
INSN is the instruction opcode.
MASK specifies the bits within the opcode that are to be tested
agsinst for a match with PATTERN. */
static int
decode_masked_match (uint32_t insn, uint32_t mask, uint32_t pattern)
{
return (insn & mask) == pattern;
}
/* Decode an opcode if it represents an immediate ADD or SUB instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
RD receives the 'rd' field from the decoded instruction.
RN receives the 'rn' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
int32_t *imm)
{
if ((insn & 0x9f000000) == 0x91000000)
{
unsigned shift;
unsigned op_is_sub;
*rd = (insn >> 0) & 0x1f;
*rn = (insn >> 5) & 0x1f;
*imm = (insn >> 10) & 0xfff;
shift = (insn >> 22) & 0x3;
op_is_sub = (insn >> 30) & 0x1;
switch (shift)
{
case 0:
break;
case 1:
*imm <<= 12;
break;
default:
/* UNDEFINED */
return 0;
}
if (op_is_sub)
*imm = -*imm;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x add x%u, x%u, #%d\n",
core_addr_to_string_nz (addr), insn, *rd, *rn,
*imm);
return 1;
}
return 0;
}
/* Decode an opcode if it represents an ADRP instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
RD receives the 'rd' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
{
if (decode_masked_match (insn, 0x9f000000, 0x90000000))
{
*rd = (insn >> 0) & 0x1f;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x adrp x%u, #?\n",
core_addr_to_string_nz (addr), insn, *rd);
return 1;
}
return 0;
}
/* Decode an opcode if it represents an branch immediate or branch
and link immediate instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
IS_BL receives the 'op' bit from the decoded instruction.
OFFSET receives the immediate offset from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
{
/* b 0001 01ii iiii iiii iiii iiii iiii iiii */
/* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
if (decode_masked_match (insn, 0x7c000000, 0x14000000))
{
*is_bl = (insn >> 31) & 0x1;
*offset = extract_signed_bitfield (insn, 26, 0) << 2;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x %s 0x%s\n",
core_addr_to_string_nz (addr), insn,
*is_bl ? "bl" : "b",
core_addr_to_string_nz (addr + *offset));
return 1;
}
return 0;
}
/* Decode an opcode if it represents a conditional branch instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
COND receives the branch condition field from the decoded
instruction.
OFFSET receives the immediate offset from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
{
/* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
if (decode_masked_match (insn, 0xff000010, 0x54000000))
{
*cond = (insn >> 0) & 0xf;
*offset = extract_signed_bitfield (insn, 19, 5) << 2;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x b<%u> 0x%s\n",
core_addr_to_string_nz (addr), insn, *cond,
core_addr_to_string_nz (addr + *offset));
return 1;
}
return 0;
}
/* Decode an opcode if it represents a branch via register instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
IS_BLR receives the 'op' bit from the decoded instruction.
RN receives the 'rn' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
{
/* 8 4 0 6 2 8 4 0 */
/* blr 110101100011111100000000000rrrrr */
/* br 110101100001111100000000000rrrrr */
if (decode_masked_match (insn, 0xffdffc1f, 0xd61f0000))
{
*is_blr = (insn >> 21) & 1;
*rn = (insn >> 5) & 0x1f;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x %s 0x%x\n",
core_addr_to_string_nz (addr), insn,
*is_blr ? "blr" : "br", *rn);
return 1;
}
return 0;
}
/* Decode an opcode if it represents a CBZ or CBNZ instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
IS64 receives the 'sf' field from the decoded instruction.
IS_CBNZ receives the 'op' field from the decoded instruction.
RN receives the 'rn' field from the decoded instruction.
OFFSET receives the 'imm19' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
unsigned *rn, int32_t *offset)
{
/* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
/* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
if (decode_masked_match (insn, 0x7e000000, 0x34000000))
{
*rn = (insn >> 0) & 0x1f;
*is64 = (insn >> 31) & 0x1;
*is_cbnz = (insn >> 24) & 0x1;
*offset = extract_signed_bitfield (insn, 19, 5) << 2;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x %s 0x%s\n",
core_addr_to_string_nz (addr), insn,
*is_cbnz ? "cbnz" : "cbz",
core_addr_to_string_nz (addr + *offset));
return 1;
}
return 0;
}
/* Decode an opcode if it represents a ERET instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_eret (CORE_ADDR addr, uint32_t insn)
{
/* eret 1101 0110 1001 1111 0000 0011 1110 0000 */
if (insn == 0xd69f03e0)
{
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog, "decode: 0x%s 0x%x eret\n",
core_addr_to_string_nz (addr), insn);
return 1;
}
return 0;
}
/* Decode an opcode if it represents a MOVZ instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
RD receives the 'rd' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
{
if (decode_masked_match (insn, 0xff800000, 0x52800000))
{
*rd = (insn >> 0) & 0x1f;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x movz x%u, #?\n",
core_addr_to_string_nz (addr), insn, *rd);
return 1;
}
return 0;
}
/* Decode an opcode if it represents a ORR (shifted register)
instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
RD receives the 'rd' field from the decoded instruction.
RN receives the 'rn' field from the decoded instruction.
RM receives the 'rm' field from the decoded instruction.
IMM receives the 'imm6' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_orr_shifted_register_x (CORE_ADDR addr,
uint32_t insn, unsigned *rd, unsigned *rn,
unsigned *rm, int32_t *imm)
{
if (decode_masked_match (insn, 0xff200000, 0xaa000000))
{
*rd = (insn >> 0) & 0x1f;
*rn = (insn >> 5) & 0x1f;
*rm = (insn >> 16) & 0x1f;
*imm = (insn >> 10) & 0x3f;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n",
core_addr_to_string_nz (addr), insn, *rd,
*rn, *rm, *imm);
return 1;
}
return 0;
}
/* Decode an opcode if it represents a RET instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
RN receives the 'rn' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
{
if (decode_masked_match (insn, 0xfffffc1f, 0xd65f0000))
{
*rn = (insn >> 5) & 0x1f;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x ret x%u\n",
core_addr_to_string_nz (addr), insn, *rn);
return 1;
}
return 0;
}
/* Decode an opcode if it represents the following instruction:
STP rt, rt2, [rn, #imm]
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
RT1 receives the 'rt' field from the decoded instruction.
RT2 receives the 'rt2' field from the decoded instruction.
RN receives the 'rn' field from the decoded instruction.
IMM receives the 'imm' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_stp_offset (CORE_ADDR addr,
uint32_t insn,
unsigned *rt1, unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9000000))
{
*rt1 = (insn >> 0) & 0x1f;
*rn = (insn >> 5) & 0x1f;
*rt2 = (insn >> 10) & 0x1f;
*imm = extract_signed_bitfield (insn, 7, 15);
*imm <<= 3;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n",
core_addr_to_string_nz (addr), insn,
*rt1, *rt2, *rn, *imm);
return 1;
}
return 0;
}
/* Decode an opcode if it represents the following instruction:
STP rt, rt2, [rn, #imm]!
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
RT1 receives the 'rt' field from the decoded instruction.
RT2 receives the 'rt2' field from the decoded instruction.
RN receives the 'rn' field from the decoded instruction.
IMM receives the 'imm' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_stp_offset_wb (CORE_ADDR addr,
uint32_t insn,
unsigned *rt1, unsigned *rt2, unsigned *rn,
int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9800000))
{
*rt1 = (insn >> 0) & 0x1f;
*rn = (insn >> 5) & 0x1f;
*rt2 = (insn >> 10) & 0x1f;
*imm = extract_signed_bitfield (insn, 7, 15);
*imm <<= 3;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n",
core_addr_to_string_nz (addr), insn,
*rt1, *rt2, *rn, *imm);
return 1;
}
return 0;
}
/* Decode an opcode if it represents the following instruction:
STUR rt, [rn, #imm]
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
IS64 receives size field from the decoded instruction.
RT receives the 'rt' field from the decoded instruction.
RN receives the 'rn' field from the decoded instruction.
IMM receives the 'imm' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xbfe00c00, 0xb8000000))
{
*is64 = (insn >> 30) & 1;
*rt = (insn >> 0) & 0x1f;
*rn = (insn >> 5) & 0x1f;
*imm = extract_signed_bitfield (insn, 9, 12);
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n",
core_addr_to_string_nz (addr), insn,
*is64 ? 'x' : 'w', *rt, *rn, *imm);
return 1;
}
return 0;
}
/* Decode an opcode if it represents a TBZ or TBNZ instruction.
ADDR specifies the address of the opcode.
INSN specifies the opcode to test.
IS_TBNZ receives the 'op' field from the decoded instruction.
BIT receives the bit position field from the decoded instruction.
RT receives 'rt' field from the decoded instruction.
IMM receives 'imm' field from the decoded instruction.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
unsigned *rt, int32_t *imm)
{
/* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
/* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
if (decode_masked_match (insn, 0x7e000000, 0x36000000))
{
*rt = (insn >> 0) & 0x1f;
*is_tbnz = (insn >> 24) & 0x1;
*bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
*imm = extract_signed_bitfield (insn, 14, 5) << 2;
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
core_addr_to_string_nz (addr), insn,
*is_tbnz ? "tbnz" : "tbz", *rt, *bit,
core_addr_to_string_nz (addr + *imm));
return 1;
}
return 0;
}
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
static CORE_ADDR
aarch64_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR start, CORE_ADDR limit,
struct aarch64_prologue_cache *cache)
{
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
int i;
pv_t regs[AARCH64_X_REGISTER_COUNT];
struct pv_area *stack;
struct cleanup *back_to;
for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
regs[i] = pv_register (i, 0);
stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
back_to = make_cleanup_free_pv_area (stack);
for (; start < limit; start += 4)
{
uint32_t insn;
unsigned rd;
unsigned rn;
unsigned rm;
unsigned rt;
unsigned rt1;
unsigned rt2;
int op_is_sub;
int32_t imm;
unsigned cond;
int is64;
int is_link;
int is_cbnz;
int is_tbnz;
unsigned bit;
int32_t offset;
insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
if (decode_add_sub_imm (start, insn, &rd, &rn, &imm))
regs[rd] = pv_add_constant (regs[rn], imm);
else if (decode_adrp (start, insn, &rd))
regs[rd] = pv_unknown ();
else if (decode_b (start, insn, &is_link, &offset))
{
/* Stop analysis on branch. */
break;
}
else if (decode_bcond (start, insn, &cond, &offset))
{
/* Stop analysis on branch. */
break;
}
else if (decode_br (start, insn, &is_link, &rn))
{
/* Stop analysis on branch. */
break;
}
else if (decode_cb (start, insn, &is64, &is_cbnz, &rn, &offset))
{
/* Stop analysis on branch. */
break;
}
else if (decode_eret (start, insn))
{
/* Stop analysis on branch. */
break;
}
else if (decode_movz (start, insn, &rd))
regs[rd] = pv_unknown ();
else
if (decode_orr_shifted_register_x (start, insn, &rd, &rn, &rm, &imm))
{
if (imm == 0 && rn == 31)
regs[rd] = regs[rm];
else
{
if (aarch64_debug)
fprintf_unfiltered
(gdb_stdlog,
"aarch64: prologue analysis gave up addr=0x%s "
"opcode=0x%x (orr x register)\n",
core_addr_to_string_nz (start),
insn);
break;
}
}
else if (decode_ret (start, insn, &rn))
{
/* Stop analysis on branch. */
break;
}
else if (decode_stur (start, insn, &is64, &rt, &rn, &offset))
{
pv_area_store (stack, pv_add_constant (regs[rn], offset),
is64 ? 8 : 4, regs[rt]);
}
else if (decode_stp_offset (start, insn, &rt1, &rt2, &rn, &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
further prologue analysis. */
if (pv_area_store_would_trash (stack,
pv_add_constant (regs[rn], imm)))
break;
if (pv_area_store_would_trash (stack,
pv_add_constant (regs[rn], imm + 8)))
break;
pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
regs[rt1]);
pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
regs[rt2]);
}
else if (decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn, &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
further prologue analysis. */
if (pv_area_store_would_trash (stack,
pv_add_constant (regs[rn], imm)))
break;
if (pv_area_store_would_trash (stack,
pv_add_constant (regs[rn], imm + 8)))
break;
pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
regs[rt1]);
pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
regs[rt2]);
regs[rn] = pv_add_constant (regs[rn], imm);
}
else if (decode_tb (start, insn, &is_tbnz, &bit, &rn, &offset))
{
/* Stop analysis on branch. */
break;
}
else
{
if (aarch64_debug)
fprintf_unfiltered (gdb_stdlog,
"aarch64: prologue analysis gave up addr=0x%s"
" opcode=0x%x\n",
core_addr_to_string_nz (start), insn);
break;
}
}
if (cache == NULL)
{
do_cleanups (back_to);
return start;
}
if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
{
/* Frame pointer is fp. Frame size is constant. */
cache->framereg = AARCH64_FP_REGNUM;
cache->framesize = -regs[AARCH64_FP_REGNUM].k;
}
else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
{
/* Try the stack pointer. */
cache->framesize = -regs[AARCH64_SP_REGNUM].k;
cache->framereg = AARCH64_SP_REGNUM;
}
else
{
/* We're just out of luck. We don't know where the frame is. */
cache->framereg = -1;
cache->framesize = 0;
}
for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
CORE_ADDR offset;
if (pv_area_find_reg (stack, gdbarch, i, &offset))
cache->saved_regs[i].addr = offset;
}
do_cleanups (back_to);
return start;
}
/* Implement the "skip_prologue" gdbarch method. */
static CORE_ADDR
aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
unsigned long inst;
CORE_ADDR skip_pc;
CORE_ADDR func_addr, limit_pc;
struct symtab_and_line sal;
/* See if we can determine the end of the prologue via the symbol
table. If so, then return either PC, or the PC after the
prologue, whichever is greater. */
if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
{
CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (gdbarch, func_addr);
if (post_prologue_pc != 0)
return max (pc, post_prologue_pc);
}
/* Can't determine prologue from the symbol table, need to examine
instructions. */
/* Find an upper limit on the function prologue using the debug
information. If the debug information could not be used to
provide that bound, then use an arbitrary large number as the
upper bound. */
limit_pc = skip_prologue_using_sal (gdbarch, pc);
if (limit_pc == 0)
limit_pc = pc + 128; /* Magic. */
/* Try disassembling prologue. */
return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
}
/* Scan the function prologue for THIS_FRAME and populate the prologue
cache CACHE. */
static void
aarch64_scan_prologue (struct frame_info *this_frame,
struct aarch64_prologue_cache *cache)
{
CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
CORE_ADDR prologue_start;
CORE_ADDR prologue_end;
CORE_ADDR prev_pc = get_frame_pc (this_frame);
struct gdbarch *gdbarch = get_frame_arch (this_frame);
cache->prev_pc = prev_pc;
/* Assume we do not find a frame. */
cache->framereg = -1;
cache->framesize = 0;
if (find_pc_partial_function (block_addr, NULL, &prologue_start,
&prologue_end))
{
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
if (sal.line == 0)
{
/* No line info so use the current PC. */
prologue_end = prev_pc;
}
else if (sal.end < prologue_end)
{
/* The next line begins after the function end. */
prologue_end = sal.end;
}
prologue_end = min (prologue_end, prev_pc);
aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
}
else
{
CORE_ADDR frame_loc;
LONGEST saved_fp;
LONGEST saved_lr;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
if (frame_loc == 0)
return;
cache->framereg = AARCH64_FP_REGNUM;
cache->framesize = 16;
cache->saved_regs[29].addr = 0;
cache->saved_regs[30].addr = 8;
}
}
/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
function may throw an exception if the inferior's registers or memory is
not available. */
static void
aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
struct aarch64_prologue_cache *cache)
{
CORE_ADDR unwound_fp;
int reg;
aarch64_scan_prologue (this_frame, cache);
if (cache->framereg == -1)
return;
unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
if (unwound_fp == 0)
return;
cache->prev_sp = unwound_fp + cache->framesize;
/* Calculate actual addresses of saved registers using offsets
determined by aarch64_analyze_prologue. */
for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
if (trad_frame_addr_p (cache->saved_regs, reg))
cache->saved_regs[reg].addr += cache->prev_sp;
cache->func = get_frame_func (this_frame);
cache->available_p = 1;
}
/* Allocate and fill in *THIS_CACHE with information about the prologue of
*THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
Return a pointer to the current aarch64_prologue_cache in
*THIS_CACHE. */
static struct aarch64_prologue_cache *
aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
{
struct aarch64_prologue_cache *cache;
if (*this_cache != NULL)
return *this_cache;
cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
*this_cache = cache;
TRY
{
aarch64_make_prologue_cache_1 (this_frame, cache);
}