add custom op GmmSwigluQuantWeightNZTensorList

Signed-off-by: QianChenxi <[email protected]>

[Kernel] add custom op DispatchGmmCombineDecode

Signed-off-by: wangqiankun13 <[email protected]>

Author: ChenxiQ

.github/workflows/release_whl.yml

@@ -95,6 +95,12 @@ jobs:
           --exclude libge_common_base.so \
           --exclude libc10.so \
           --exclude libc_sec.so \
+          --exclude libopapi.so \
+          --exclude libnnopbase.so \
+          --exclude libprofapi.so \
+          --exclude libgraph_base.so \
+          --exclude libgraph.so \
+          --exclude libexe_graph.so \
           --exclude "libascend*.so" \
           --exclude "libtorch*.so" \
           --exclude "liberror_manager.so"

.gitsubmodules

@@ -0,0 +1,4 @@
+[submodule "csrc/third_party/catlass"]
+	path = csrc/third_party/catlass
+	url = https://gitee.com/ascend/catlass.git
+	branch = catlass-v1-stable

.pre-commit-config.yaml

@@ -12,7 +12,7 @@ repos:
     - id: codespell
       args: [
         --toml, pyproject.toml,
-        '--skip', 'tests/e2e/multicard/test_torchair_graph_mode.py,csrc/mla_preprocess/**,tests/prompts/**,./benchmarks/sonnet.txt,*tests/lora/data/**,build/**,./vllm_ascend.egg-info/**,.github/**,typos.toml',
+        '--skip', 'tests/e2e/multicard/test_torchair_graph_mode.py,csrc/**,tests/prompts/**,./benchmarks/sonnet.txt,*tests/lora/data/**,build/**,./vllm_ascend.egg-info/**,.github/**,typos.toml',
         '-L', 'CANN,cann,NNAL,nnal,ASCEND,ascend,EnQue,CopyIn,ArchType,AND'
       ]
       additional_dependencies:
@@ -37,7 +37,7 @@ repos:
   - id: typos
     args: [
       "--force-exclude",
-      "--exclude", "csrc/mla_preprocess/**"
+      "--exclude", "csrc/**"
     ]
 - repo: https://github.com/PyCQA/isort
   rev: 6.0.1

CMakeLists.txt

@@ -81,6 +81,7 @@ set(
   ${TORCH_NPU_INCLUDE_DIRS}
   ${ASCEND_HOME_PATH}/include
   ${ASCEND_HOME_PATH}/aarch64-linux/include/experiment/platform
+  ${ASCEND_HOME_PATH}/x86_64-linux/include/experiment/platform
 )
 
 pybind11_add_module(vllm_ascend_C ${VLLM_ASCEND_SRC})