diff --git a/vtr_flow/benchmarks/verilog/koios/attention_layer.v b/vtr_flow/benchmarks/verilog/koios/attention_layer.v index f3fab46db4e..7a02ff61e2f 100644 --- a/vtr_flow/benchmarks/verilog/koios/attention_layer.v +++ b/vtr_flow/benchmarks/verilog/koios/attention_layer.v @@ -164,7 +164,7 @@ wordwise_bram_2 out_buffer34 ); //Softmax layer has a parallelism of 4 -softmax soft( +softmax softmax( .inp(data_to_softmax), .sub0_inp(data_to_softmax), .sub1_inp(data_to_softmax), diff --git a/vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v b/vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v index 6546e8d9a72..e6307c56e6f 100644 --- a/vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v +++ b/vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v @@ -18,6 +18,7 @@ // Abridged for VTR by: Daniel Rauch ////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns / 1 ps module dpram ( @@ -134,8 +135,6 @@ dual_port_ram u_dual_port_ram( endmodule -`timescale 1 ns / 1 ps - module td_fused_top_Block_entry_proc_proc505 ( ap_clk, ap_rst, diff --git a/vtr_flow/benchmarks/verilog/koios/dnnweaver.v b/vtr_flow/benchmarks/verilog/koios/dnnweaver.v index 34db583adba..0d8df011e58 100644 --- a/vtr_flow/benchmarks/verilog/koios/dnnweaver.v +++ b/vtr_flow/benchmarks/verilog/koios/dnnweaver.v @@ -156,12 +156,15 @@ module fifo // ****************************************************************** // FIFO Logic // ****************************************************************** + +/* initial begin if (INITIALIZE_FIFO == "yes") begin $readmemh(INIT, mem, 0, RAM_DEPTH-1); end end - +*/ + always @ (r_fifo_count) begin : FIFO_STATUS empty = (r_fifo_count == 0); @@ -1588,7 +1591,8 @@ module axi_master .s_write_ready ( rd_req_buf_wr_ready ), //output .s_write_data ( rd_req_buf_data_in ), //input .almost_full ( rd_req_buf_almost_full ), //output - .almost_empty ( rd_req_buf_almost_empty ) //output + .almost_empty ( rd_req_buf_almost_empty ), //output + .fifo_count ( ) //output ); //============================================================================== @@ -1622,7 +1626,8 @@ module axi_master .s_write_ready ( rx_req_id_buf_wr_ready ), //output .s_write_data ( rx_req_id_buf_data_in ), //input .almost_full ( rx_req_id_buf_almost_full ), //output - .almost_empty ( rx_req_id_buf_almost_empty ) //output + .almost_empty ( rx_req_id_buf_almost_empty ), //output + .fifo_count ( ) //output ); @@ -1799,7 +1804,8 @@ module axi_master .s_write_ready ( wr_req_buf_wr_ready ), //output .s_write_data ( wr_req_buf_data_in ), //input .almost_full ( wr_req_buf_almost_full ), //output - .almost_empty ( wr_req_buf_almost_empty ) //output + .almost_empty ( wr_req_buf_almost_empty ), //output + .fifo_count ( ) //output ); //============================================================================== @@ -1899,7 +1905,8 @@ module axi_master .s_write_ready ( wdata_req_buf_wr_ready ), //output .s_write_data ( wdata_req_buf_data_in ), //input .almost_full ( wdata_req_buf_almost_full ), //output - .almost_empty ( wdata_req_buf_almost_empty ) //output + .almost_empty ( wdata_req_buf_almost_empty ), //output + .fifo_count ( ) //output ); //============================================================================== diff --git a/vtr_flow/benchmarks/verilog/koios/tdarknet_like.large.v b/vtr_flow/benchmarks/verilog/koios/tdarknet_like.large.v index 2dbb4c41826..bc28af6ae7e 100644 --- a/vtr_flow/benchmarks/verilog/koios/tdarknet_like.large.v +++ b/vtr_flow/benchmarks/verilog/koios/tdarknet_like.large.v @@ -15,6 +15,8 @@ // Abridged for VTR by: Daniel Rauch ////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns / 1 ps + module td_fused_top_ap_hmul_3_max_dsp_16 ( input wire aclk, input wire aclken, @@ -116,8 +118,6 @@ FPAddSub u_FPAddSub_2 (.clk(), .rst(1'b0), .a(s_axis_a_tdata), .b(b_negative), . assign m_axis_result_tdata = {7'b0, result[15]}; endmodule -`timescale 1 ns / 1 ps - module td_fused_top_Block_entry_proc_proc491 ( ap_clk, ap_rst, @@ -63221,7 +63221,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -63366,7 +63366,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; integer i; @@ -63505,7 +63505,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; integer i; @@ -63648,7 +63648,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9, sr_10; integer i; @@ -63795,7 +63795,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -63936,7 +63936,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; integer i; @@ -64079,7 +64079,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -64224,7 +64224,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -64353,7 +64353,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -64482,7 +64482,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -64611,7 +64611,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -64740,7 +64740,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -64869,7 +64869,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -64998,7 +64998,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -65127,7 +65127,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -65256,7 +65256,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -65385,7 +65385,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -65514,7 +65514,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -65643,7 +65643,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -65772,7 +65772,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -65917,7 +65917,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9, sr_10; integer i; @@ -66064,7 +66064,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9, sr_10; integer i; @@ -66211,7 +66211,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9, sr_10; integer i; @@ -66358,7 +66358,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9, sr_10, sr_11; integer i; @@ -66507,7 +66507,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -66648,7 +66648,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; integer i; @@ -66791,7 +66791,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; integer i; @@ -66934,7 +66934,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -67063,7 +67063,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -67192,7 +67192,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -67337,7 +67337,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -67482,7 +67482,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -67611,7 +67611,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -67740,7 +67740,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; integer i; @@ -67879,7 +67879,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -68020,7 +68020,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -68161,7 +68161,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -68302,7 +68302,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; integer i; @@ -68445,7 +68445,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -68590,7 +68590,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -68719,7 +68719,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -68848,7 +68848,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -68977,7 +68977,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -69106,7 +69106,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; integer i; @@ -69245,7 +69245,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -69386,7 +69386,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; integer i; @@ -69529,7 +69529,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; integer i; @@ -69672,7 +69672,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9, sr_10; integer i; @@ -69819,7 +69819,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -69948,7 +69948,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -70077,7 +70077,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -70206,7 +70206,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; integer i; @@ -70345,7 +70345,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -70486,7 +70486,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -70627,7 +70627,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8; integer i; @@ -70770,7 +70770,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -70915,7 +70915,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -71044,7 +71044,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -71173,7 +71173,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -71302,7 +71302,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -71443,7 +71443,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -71584,7 +71584,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -71725,7 +71725,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -71870,7 +71870,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, sr_9; integer i; @@ -72015,7 +72015,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -72144,7 +72144,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; integer i; @@ -72283,7 +72283,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6; integer i; @@ -72422,7 +72422,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -72563,7 +72563,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -72704,7 +72704,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -72833,7 +72833,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7; integer i; @@ -74478,7 +74478,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -74607,7 +74607,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -74736,7 +74736,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -74865,7 +74865,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -74994,7 +74994,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -75123,7 +75123,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -75252,7 +75252,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -75381,7 +75381,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -75510,7 +75510,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -75639,7 +75639,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -75768,7 +75768,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i; @@ -75897,7 +75897,7 @@ input clk; input [DATA_WIDTH-1:0] data; input ce; input [ADDR_WIDTH-1:0] a; -output [DATA_WIDTH-1:0] q; +output reg [DATA_WIDTH-1:0] q; reg[DATA_WIDTH-1:0] sr_0, sr_1; integer i;