diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 2ecc7fbd41c..7f801c465b7 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -652,6 +652,11 @@ bool is_io_type(t_physical_tile_type_ptr type) { || is_output_type(type); } +bool is_io_type(t_logical_block_type_ptr type) { + auto physical_tile = pick_physical_type(type); + return is_io_type(physical_tile); +} + std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_physical_num, bool is_flat) { int max_ptc = get_tile_pin_max_ptc(type, is_flat); VTR_ASSERT(pin_physical_num < max_ptc); diff --git a/libs/libarchfpga/src/physical_types_util.h b/libs/libarchfpga/src/physical_types_util.h index a081683faeb..c3a6ea13c6e 100644 --- a/libs/libarchfpga/src/physical_types_util.h +++ b/libs/libarchfpga/src/physical_types_util.h @@ -127,6 +127,9 @@ bool is_output_type(t_physical_tile_type_ptr type); ///@brief Returns true if the given physical tile type can implement either a .input or .output block type bool is_io_type(t_physical_tile_type_ptr type); +///@brief Returns true if the given logical block type is an IO block +bool is_io_type(t_logical_block_type_ptr type); + /** * @brief Returns the corresponding physical pin based on the input parameters: * diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 9974de549a0..ab21fc92516 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -421,6 +421,13 @@ struct t_net_power { /** * @brief Stores a 3D bounding box in terms of the minimum and * maximum coordinates: x, y, layer + * + * @var xmin: The minimum x-coordinate of the bounding box + * @var xmax: The maximum x-coordinate of the bounding box + * @var ymin: The minimum y-coordinate of the bounding box + * @var ymax: The maximum y-coordinate of the bounding box + * @var layer_min: The minimum layer of the bounding box + * @var layer_max: The maximum layer of the bounding box */ struct t_bb { t_bb() = default; diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 3dc8650a3e2..3cdb5de6bd6 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -203,7 +203,8 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, * * @return true if the function can find any location near the centroid one, false otherwise. */ -static bool find_centroid_neighbor(t_pl_loc& centroid_loc, +static bool find_centroid_neighbor(ClusterBlockId block_id, + t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, int r_lim, @@ -212,7 +213,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, /** * @brief tries to place a macro at a centroid location of its placed connections. - * + * + * @param block_id The block to be placed. * @param pl_macro The macro to be placed. * @param pr The PartitionRegion of the macro - represents its floorplanning constraints, is the size of the whole chip if the macro is not * constrained. @@ -225,7 +227,8 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, * * @return true if the macro gets placed, false if not. */ -static bool try_centroid_placement(const t_pl_macro& pl_macro, +static bool try_centroid_placement(ClusterBlockId block_id, + const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, @@ -400,7 +403,8 @@ bool find_subtile_in_location(t_pl_loc& centroid, return false; } -static bool find_centroid_neighbor(t_pl_loc& centroid_loc, +static bool find_centroid_neighbor(ClusterBlockId block_id, + t_pl_loc& centroid_loc, t_logical_block_type_ptr block_type, bool search_for_empty, int rlim, @@ -425,6 +429,16 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc, int delta_cx = search_range.xmax - search_range.xmin; + bool search_range_adjusted = adjust_search_range(block_type, + block_id, + search_range, + delta_cx, + centroid_loc_layer_num); + + if (!search_range_adjusted) { + return false; + } + //Block has not been placed yet, so the "from" coords will be (-1, -1) int cx_from = OPEN; int cy_from = OPEN; @@ -832,7 +846,8 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat return best_loc; } -static bool try_centroid_placement(const t_pl_macro& pl_macro, +static bool try_centroid_placement(ClusterBlockId block_id, + const t_pl_macro& pl_macro, const PartitionRegion& pr, t_logical_block_type_ptr block_type, e_pad_loc_type pad_loc_type, @@ -889,7 +904,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro, //centroid suggestion was either occupied or does not match block type //try to find a near location that meet these requirements if (!found_legal_subtile) { - bool neighbor_legal_loc = find_centroid_neighbor(centroid_loc, block_type, false, rlim, blk_loc_registry, rng); + bool neighbor_legal_loc = find_centroid_neighbor(block_id, centroid_loc, block_type, false, rlim, blk_loc_registry, rng); if (!neighbor_legal_loc) { //no neighbor candidate found return false; } @@ -1300,7 +1315,7 @@ static bool place_macro(int macros_max_num_tries, if (!macro_placed) { VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tTry centroid placement\n"); - macro_placed = try_centroid_placement(pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); + macro_placed = try_centroid_placement(blk_id, pl_macro, pr, block_type, pad_loc_type, block_scores, blk_loc_registry, flat_placement_info, rng); } VTR_LOGV_DEBUG(g_vpr_ctx.placement().f_placer_debug, "\t\t\tMacro is placed: %d\n", macro_placed); // If macro is not placed yet, try to place the macro randomly for the max number of random tries diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index f3cc457d0bb..b77fd22430f 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -669,18 +669,13 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, rlim); int delta_cx = search_range.xmax - search_range.xmin; + bool adjust_search_range_res = adjust_search_range(type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; + } + t_physical_tile_loc to_compressed_loc; bool legal = false; - - if (is_cluster_constrained(b_from)) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } - } //TODO: For now, we only move the blocks on the same tile legal = find_compatible_compressed_loc_in_range(type, delta_cx, @@ -761,19 +756,13 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, to_layer_num, to_layer_num); - t_physical_tile_loc to_compressed_loc; - bool legal = false; - - if (is_cluster_constrained(b_from)) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } + bool adjust_search_range_res = adjust_search_range(blk_type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; } + t_physical_tile_loc to_compressed_loc; + bool legal = false; legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, from_compressed_locs[to_layer_num], @@ -850,20 +839,15 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, } delta_cx = search_range.xmax - search_range.xmin; + bool adjust_search_range_res = adjust_search_range(blk_type, b_from, search_range, delta_cx, to_layer_num); + if (!adjust_search_range_res) { + return false; + } + t_physical_tile_loc to_compressed_loc; bool legal = false; - if (is_cluster_constrained(b_from)) { - bool intersect = intersect_range_limit_with_floorplan_constraints(b_from, - search_range, - delta_cx, - to_layer_num); - if (!intersect) { - return false; - } - } - - //TODO: For now, we only move the blocks on the same tile + //TODO: For now, we only move the blocks on the same layer legal = find_compatible_compressed_loc_in_range(blk_type, delta_cx, from_compressed_loc[to_layer_num], @@ -961,7 +945,7 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, const int delta_cx, const t_physical_tile_loc& from_loc, - t_bb search_range, + const t_bb& search_range, t_physical_tile_loc& to_loc, bool is_median, int to_layer_num, @@ -1006,24 +990,8 @@ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, if (y_lower_iter == block_rows.end()) { continue; } - auto y_upper_iter = block_rows.upper_bound(search_range.ymax); - if (y_lower_iter->first > search_range.ymin) { - //No valid blocks at this x location which are within rlim_y - // - if (type->index != 1) - continue; - else { - //Fall back to allow the whole y range - y_lower_iter = block_rows.begin(); - y_upper_iter = block_rows.end(); - - search_range.ymin = y_lower_iter->first; - search_range.ymax = (y_upper_iter - 1)->first; - } - } - int y_range = std::distance(y_lower_iter, y_upper_iter); VTR_ASSERT(y_range >= 0); @@ -1202,6 +1170,37 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, return true; } +bool adjust_search_range(t_logical_block_type_ptr block_type, + ClusterBlockId block_id, + t_bb& search_range, + int& delta_cx, + int to_layer_num) { + + auto block_constrained = is_cluster_constrained(block_id); + + if (block_constrained) { + bool intersect = intersect_range_limit_with_floorplan_constraints(block_id, + search_range, + delta_cx, + to_layer_num); + if (!intersect) { + return false; + } + } + + if (is_io_type(block_type) && !block_constrained) { + /* We empirically found that for the IO blocks, + * Given their sparsity, we expand the y-axis search range + * to include all blocks in the column + */ + const t_compressed_block_grid& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; + search_range.ymin = 0; + search_range.ymax = compressed_block_grid.get_num_rows(to_layer_num) - 1; + } + + return true; +} + std::string e_move_result_to_string(e_move_result move_outcome) { switch (move_outcome) { case e_move_result::REJECTED: diff --git a/vpr/src/place/move_utils.h b/vpr/src/place/move_utils.h index 5552c36e8e9..69a7a5647e5 100644 --- a/vpr/src/place/move_utils.h +++ b/vpr/src/place/move_utils.h @@ -328,11 +328,12 @@ int find_empty_compatible_subtile(t_logical_block_type_ptr type, * is_median: true if this is called from find_to_loc_median * to_layer_num: the layer number of the new location (set by the caller) * search_for_empty: indicates that the returned location must be empty + * fixed_search_range: indicates that the search range is fixed and should not be adjusted */ bool find_compatible_compressed_loc_in_range(t_logical_block_type_ptr type, int delta_cx, const t_physical_tile_loc& from_loc, - t_bb search_range, + const t_bb& search_range, t_physical_tile_loc& to_loc, bool is_median, int to_layer_num, @@ -420,6 +421,27 @@ bool intersect_range_limit_with_floorplan_constraints(ClusterBlockId b_from, int& delta_cx, int layer_num); +/** + * @brief Adjust the search range based on the block type and constraints + * + * If the block is an IO block, we expand the search range to include all blocks in the column + * We found empirically that this is a good strategy for IO blocks given they are located in + * the periphery for most FPGA architectures + * + * @param block_type The type of the block to move + * @param block_id The block ID of the moving block + * @param search_range The search range to adjust + * @param delta_cx The delta x of the search range + * @param to_layer_num The layer that the block is moving to + * + * @return true if the search range was adjusted, false otherwise + */ +bool adjust_search_range(t_logical_block_type_ptr block_type, + ClusterBlockId block_id, + t_bb& search_range, + int& delta_cx, + int to_layer_num); + std::string e_move_result_to_string(e_move_result move_outcome); /** diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt index 594c4215910..ee9f959aaa6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 2.08 vpr 61.77 MiB -1 -1 0.12 16500 1 0.10 -1 -1 31836 -1 -1 2 6 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63252 6 1 13 14 2 8 9 4 4 16 clb auto 23.2 MiB 0.01 22 27 6 15 6 61.8 MiB 0.00 0.00 1.02737 -3.61973 -1.02737 0.545 0.01 3.6498e-05 2.6643e-05 0.000260655 0.000218319 -1 -1 -1 -1 20 22 8 107788 107788 10441.3 652.579 0.01 0.00250948 0.00220504 742 1670 -1 21 1 6 6 146 96 1.40641 0.545 -4.38899 -1.40641 0 0 13748.8 859.301 0.00 0.00 0.00 -1 -1 0.00 0.00176399 0.00169239 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 2.09 vpr 61.68 MiB -1 -1 0.15 16776 1 0.07 -1 -1 31648 -1 -1 2 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63160 3 -1 23 23 2 3 5 4 4 16 clb auto 23.2 MiB 0.01 3 12 2 3 7 61.7 MiB 0.00 0.00 0.620297 -7.93119 -0.620297 0.545 0.01 6.5504e-05 5.6164e-05 0.000543565 0.00049453 -1 -1 -1 -1 8 1 1 107788 107788 4888.88 305.555 0.01 0.00311117 0.00290556 622 902 -1 1 1 1 1 8 6 0.54641 0.545 -7.63564 -0.54641 0 0 5552.67 347.042 0.00 0.01 0.00 -1 -1 0.00 0.00221081 0.00210995 - k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 10 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 22 1 3 3 79 69 1.8363 1.8363 -2.38182 -1.8363 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 + k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 2.05 vpr 61.70 MiB -1 -1 0.10 16420 1 0.10 -1 -1 30004 -1 -1 1 3 0 0 success v8.0.0-11925-ga544f5fea-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2025-01-14T21:35:49 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/release/vtr-verilog-to-routing 63180 3 1 5 6 1 4 5 3 3 9 -1 auto 23.1 MiB 0.01 9 12 5 4 3 61.7 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 2.1504e-05 1.601e-05 0.000159881 0.000125763 -1 -1 -1 -1 20 5 1 53894 53894 4880.82 542.314 0.01 0.00174411 0.00161402 379 725 -1 5 1 3 3 79 69 0.8 0.8 -1.2 -0.8 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00154197 0.00149823 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt index 21dd6c7c148..04faf813cc3 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/iterative/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.3 vpr 255.23 MiB 0.1 37032 -1 -1 1 0.05 -1 -1 34904 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261360 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.1 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000265884 0.000243239 0.00748601 0.00452291 20 15 7 107788 107788 10441.3 652.579 0.66 0.0136031 0.00885329 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00736034 0.00605214 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.17 vpr 257.73 MiB 0.11 45924 -1 -1 1 0.05 -1 -1 34916 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 263920 3 1 23 24 2 8 6 4 4 16 clb auto 102.9 MiB 0.41 17 246.4 MiB 0.03 0 0.571 -8.10303 -0.571 0.557849 0.47 0.000537036 0.000469297 0.00334227 0.00240417 20 19 1 107788 107788 10441.3 652.579 0.66 0.0107944 0.00802791 742 1670 -1 27 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.27775 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471694 0.00381784 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.06 vpr 254.61 MiB 0.11 36040 -1 -1 1 0.01 -1 -1 32628 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260720 6 2 10 12 2 8 10 4 4 16 clb auto 100.6 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000492001 0.000225939 0.00246091 0.00127477 20 20 1 107788 107788 10441.3 652.579 0.64 0.00559049 0.00306652 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00247934 0.00153705 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.06 vpr 254.61 MiB 0.11 36040 -1 -1 1 0.01 -1 -1 32628 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260720 6 2 10 12 2 8 10 4 4 16 clb auto 100.6 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000492001 0.000225939 0.00246091 0.00127477 20 10 1 107788 107788 10441.3 652.579 0.64 0.00559049 0.00306652 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00247934 0.00153705 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt index 9ab3c9f38ba..13c480e3e16 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock_odin/func_multiclock/vanilla/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_mem32K_40nm.xml multiclock_output_and_latch.v common 12.42 vpr 255.39 MiB 0.11 37100 -1 -1 1 0.05 -1 -1 34836 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 261516 6 1 13 14 2 8 9 4 4 16 clb auto 100.9 MiB 0.11 13 244.2 MiB 0.04 0 0.875884 -3.21653 -0.875884 0.545 0.47 0.000271285 0.00024783 0.00755294 0.00457495 20 15 7 107788 107788 10441.3 652.579 0.66 0.0137643 0.00901687 742 1670 -1 15 14 32 32 476 268 0 0 476 268 32 32 0 0 45 42 0 0 51 45 0 0 32 32 0 0 205 79 0 0 111 38 0 0 32 0 0 0 0 0 32 0 0 1.31811 0.545 -4.12048 -1.31811 0 0 13748.8 859.301 0.01 0.04 0.18 -1 -1 0.01 0.00730106 0.00594924 k6_frac_N10_mem32K_40nm.xml multiclock_reader_writer.v common 13.23 vpr 258.31 MiB 0.12 45996 -1 -1 1 0.06 -1 -1 34908 -1 -1 2 3 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 264512 3 1 23 24 2 8 6 4 4 16 clb auto 103.2 MiB 0.41 17 246.6 MiB 0.03 0 0.865 -8.10303 -0.865 0.557849 0.47 0.00052053 0.00046898 0.00343969 0.00250359 20 19 1 107788 107788 10441.3 652.579 0.67 0.0108999 0.00814426 742 1670 -1 27 1 6 6 65 37 0 0 65 37 6 6 0 0 8 6 0 0 8 8 0 0 6 6 0 0 16 4 0 0 21 7 0 0 6 0 0 0 0 0 6 0 0 0.865 0.557849 -8.27775 -0.865 0 0 13748.8 859.301 0.01 0.03 0.17 -1 -1 0.01 0.00471607 0.00381108 -k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.08 vpr 254.57 MiB 0.11 35828 -1 -1 1 0 -1 -1 32584 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260676 6 2 10 12 2 8 10 4 4 16 clb auto 100.7 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000490217 0.000225774 0.00246486 0.00125809 20 20 1 107788 107788 10441.3 652.579 0.64 0.00562004 0.00308942 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00259444 0.00157979 +k6_frac_N10_mem32K_40nm.xml multiclock_separate_and_latch.v common 12.08 vpr 254.57 MiB 0.11 35828 -1 -1 1 0 -1 -1 32584 -1 -1 2 6 0 0 success v8.0.0-7653-g7c8f300-dirty release VTR_ASSERT_LEVEL=3 sanitizers GNU 9.4.0 on Linux-4.13.1-041301-generic x86_64 2023-04-21 14:13:39 agent-1 /home/mahmo494/RL_experiment/vtr-verilog-to-routing/vtr_flow/tasks 260676 6 2 10 12 2 8 10 4 4 16 clb auto 100.7 MiB 0.06 13 243.8 MiB 0.02 0 0.544641 -1.98049 -0.544641 nan 0.47 0.000490217 0.000225774 0.00246486 0.00125809 20 10 1 107788 107788 10441.3 652.579 0.64 0.00562004 0.00308942 742 1670 -1 15 2 7 7 97 57 0 0 97 57 7 7 0 0 12 9 0 0 12 12 0 0 7 7 0 0 35 12 0 0 24 10 0 0 7 0 0 0 0 0 7 0 0 0.640564 nan -2.29328 -0.640564 0 0 13748.8 859.301 0.01 0.02 0.18 -1 -1 0.01 0.00259444 0.00157979