From bfe351063fc8dd9739f6644b64d5e6c735ae0ef2 Mon Sep 17 00:00:00 2001
From: Xilai <xd44@cornell.edu>
Date: Mon, 24 Jul 2023 18:16:41 -0400
Subject: [PATCH] add top module and search path for parmys

---
 vtr_flow/misc/yosys/synthesis.tcl             |  8 +++----
 .../scripts/python_libs/vtr/parmys/parmys.py  | 23 +++++++++++++++++++
 vtr_flow/scripts/run_vtr_flow.py              | 19 ++++++++++++---
 3 files changed, 43 insertions(+), 7 deletions(-)

diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl
index 0c654a0dcf7..696d51df32f 100644
--- a/vtr_flow/misc/yosys/synthesis.tcl
+++ b/vtr_flow/misc/yosys/synthesis.tcl
@@ -20,10 +20,10 @@ if {$env(PARSER) == "surelog" } {
 	puts "Using Yosys read_systemverilog command"
 	plugin -i systemverilog
 	yosys -import
-	read_systemverilog -debug XXX
+	read_systemverilog -I"SEARCHPATH" -debug XXX
 } elseif {$env(PARSER) == "default" } {
 	puts "Using Yosys read_verilog command"
-	read_verilog -sv -nolatches XXX
+	read_verilog -I"SEARCHPATH" -sv -nolatches XXX
 } else {
 	error "Invalid PARSER"
 }
@@ -33,7 +33,7 @@ scc -select
 select -assert-none %
 select -clear
 
-hierarchy -check -auto-top -purge_lib
+hierarchy -check TOPMODULE -purge_lib
 
 opt_expr
 opt_clean
@@ -76,6 +76,6 @@ opt -fast -noff
 
 tee -o /dev/stdout stat
 
-hierarchy -check -auto-top -purge_lib
+hierarchy -check TOPMODULE -purge_lib
 
 write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ
diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py
index e3240e1c8d1..a1c2223463d 100644
--- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py
+++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py
@@ -52,6 +52,8 @@ def init_script_file(
     circuit_list,
     output_netlist,
     architecture_file_path,
+    include_dir='.',
+    top_module='-auto-top'
 ):
     """initializing the raw yosys script file"""
     # specify the input files type
@@ -68,6 +70,8 @@ def init_script_file(
             "TTT": str(vtr.paths.yosys_tcl_path),
             "ZZZ": output_netlist,
             "QQQ": architecture_file_path,
+            "SEARCHPATH": include_dir,
+            "TOPMODULE": top_module,
         },
     )
 
@@ -205,11 +209,30 @@ def run(
     # Create a list showing all (.v) and (.vh) files
     circuit_list = create_circuits_list(circuit_file, include_files)
 
+    # parse search directory
+    if ('searchpath' in parmys_args):
+        if (parmys_args['searchpath'] is not None) and (parmys_args['searchpath'] != ''):
+            include_dir = parmys_args['searchpath']
+        del parmys_args['searchpath']
+    else:
+        include_dir = '.'
+
+    # parse top module
+    # NOTE: the default value is '-auto-top'
+    if ('topmodule' in parmys_args):
+        if (parmys_args['topmodule'] is not None) and (parmys_args['topmodule'] != ''):
+            top_module = '-top ' + parmys_args['topmodule']
+        del parmys_args['topmodule']
+    else:
+        top_module = '-auto-top'
+
     init_script_file(
         yosys_script_full_path,
         circuit_list,
         output_netlist.name,
         architecture_file_path,
+        include_dir,
+        top_module
     )
 
     odin_base_config = str(vtr.paths.odin_cfg_path)
diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py
index 7a03918e80b..28960eaf3fd 100755
--- a/vtr_flow/scripts/run_vtr_flow.py
+++ b/vtr_flow/scripts/run_vtr_flow.py
@@ -10,7 +10,7 @@
 import socket
 from datetime import datetime
 from collections import OrderedDict
-
+import os
 # pylint: disable=wrong-import-position, import-error
 sys.path.insert(0, str(Path(__file__).resolve().parent / "python_libs"))
 import vtr
@@ -186,7 +186,7 @@ def vtr_command_argparser(prog=None):
 
     house_keeping.add_argument(
         "-temp_dir",
-        default=None,
+        default=os.getcwd() + "/temp",
         help="Directory to run the flow in (will be created if non-existant).",
     )
 
@@ -369,6 +369,18 @@ def vtr_command_argparser(prog=None):
         + "system-verilog]. The script used the Yosys conventional Verilog"
         + " parser if this argument is not specified.",
     )
+    parmys.add_argument(
+        "-top",
+        default=None,
+        dest="topmodule",
+        help="Specify the name of the module in the design that should be considered as top",
+    )
+    parmys.add_argument(
+        '-search',
+        default=os.getcwd(),
+        dest='searchpath',
+        help='search path for verilog files'
+    )
     #
     # VPR arguments
     #
@@ -725,7 +737,8 @@ def process_parmys_args(args):
     """
     parmys_args = OrderedDict()
     parmys_args["parser"] = args.parser
-
+    parmys_args["topmodule"] = args.topmodule
+    parmys_args['searchpath'] = args.searchpath
     return parmys_args