Skip to content

Commit 8ebdfa5

Browse files
committed
Merge branch 'release'
2 parents 3f90939 + 0cc9e8f commit 8ebdfa5

File tree

4 files changed

+30
-20
lines changed

4 files changed

+30
-20
lines changed

src/main/scala/examples/GCD.scala

Lines changed: 24 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -3,23 +3,33 @@ package examples
33

44
import chisel3._
55

6+
/**
7+
* Compute the GCD of 'a' and 'b' using Euclid's algorithm.
8+
* To start a computation, load the values into 'a' and 'b' and toggle 'load'
9+
* high.
10+
* The GCD will be returned in 'out' when 'valid' is high.
11+
*/
612
class GCD extends Module {
713
val io = IO(new Bundle {
8-
val a = Input(UInt(16.W))
9-
val b = Input(UInt(16.W))
10-
val e = Input(Bool())
11-
val z = Output(UInt(16.W))
12-
val v = Output(Bool())
14+
val a = Input(UInt(16.W))
15+
val b = Input(UInt(16.W))
16+
val load = Input(Bool())
17+
val out = Output(UInt(16.W))
18+
val valid = Output(Bool())
1319
})
20+
val x = Reg(UInt())
21+
val y = Reg(UInt())
1422

15-
val x = Reg(UInt())
16-
val y = Reg(UInt())
17-
when (x > y) {
18-
x := x - y
23+
when (io.load) {
24+
x := io.a; y := io.b
25+
} .otherwise {
26+
when (x > y) {
27+
x := x - y
28+
} .elsewhen (x <= y) {
29+
y := y - x
30+
}
1931
}
20-
.elsewhen (x <= y) { y := y - x }
2132

22-
when (io.e) { x := io.a; y := io.b }
23-
io.z := x
24-
io.v := y === 0.U
25-
}
33+
io.out := x
34+
io.valid := y === 0.U
35+
}

src/main/scala/examples/HiLoMultiplier.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ package examples
33

44
import chisel3._
55

6-
//A 4-bit adder with carry in and carry out
6+
//A 16*16-bit multiplier with separate high and low product outputs
77
class HiLoMultiplier() extends Module {
88
val io = IO(new Bundle {
99
val A = Input(UInt(16.W))

src/main/scala/solutions/VecShiftRegisterParam.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ class VecShiftRegisterParam(val n: Int, val w: Int) extends Module {
1515
val out = Output(UInt(w.W))
1616
})
1717

18-
val initValues = Seq.fill(n) { 0.U(8.W) }
18+
val initValues = Seq.fill(n) { 0.U(w.W) }
1919
val delays = RegInit(Vec(initValues))
2020

2121
for (i <- n-1 to 1 by -1) {

src/test/scala/examples/GCDTests.scala

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,18 +13,18 @@ class GCDTests(c: GCD) extends PeekPokeTester(c) {
1313
poke(c.io.a, inputs(i)._1)
1414
poke(c.io.b, inputs(i)._2)
1515

16-
poke(c.io.e, 1)
16+
poke(c.io.load, 1)
1717
step(1)
18-
poke(c.io.e, 0)
18+
poke(c.io.load, 0)
1919

2020
var ready = false
2121

2222
do {
23-
ready = peek(c.io.v) == 1
23+
ready = peek(c.io.valid) == 1
2424
step(1)
2525
} while (t < 100 && ! ready)
2626

27-
expect(c.io.z, outputs(i))
27+
expect(c.io.out, outputs(i))
2828
i += 1
2929
} while (t < 100 && i < 3)
3030

0 commit comments

Comments
 (0)