The register map is described in docs/interface.md (CTRL, STATUS, WINDOW, FIFO_LVL, SMA, VWAP) but nothing implements it yet. This is the gap between "passes sim" and "runs on a board".
Goal: a thin AXI4-Lite shim exposing those fields, plus a tiny host-side reader in host/ that opens the device and prints live SMA/VWAP.
Notes
host/fixed.py already does the Q16.16 and tick packing, reuse it.- A loopback test (host packs ticks, reads results back, compares to
sim/reference.py) would make this trustworthy.
Done when: you can stream ticks in and read SMA/VWAP back over the register block.
The register map is described in
docs/interface.md(CTRL, STATUS, WINDOW, FIFO_LVL, SMA, VWAP) but nothing implements it yet. This is the gap between "passes sim" and "runs on a board".Goal: a thin AXI4-Lite shim exposing those fields, plus a tiny host-side reader in
host/that opens the device and prints live SMA/VWAP.Notes
host/fixed.pyalready does the Q16.16 and tick packing, reuse it.sim/reference.py) would make this trustworthy.Done when: you can stream ticks in and read SMA/VWAP back over the register block.