rtl/tick_sync_fifo.v is single-clock today. The real host side (XDMA) runs in a different clock domain, so we need a proper asynchronous FIFO before wiring a DMA core in.
Goal: gray-coded read/write pointers with two-flop synchronizers, same ready/valid and full / empty / level interface so the top level does not change.
Notes
- Keep the backpressure behaviour: when full, upstream ready drops, we never drop a tick.
- A self-checking testbench that pushes from one clock and pops from another (a few clock-ratio cases) would be a great companion PR.
Done when: the FIFO is verified across two clocks and the existing make sim still passes.
rtl/tick_sync_fifo.vis single-clock today. The real host side (XDMA) runs in a different clock domain, so we need a proper asynchronous FIFO before wiring a DMA core in.Goal: gray-coded read/write pointers with two-flop synchronizers, same ready/valid and
full/empty/levelinterface so the top level does not change.Notes
Done when: the FIFO is verified across two clocks and the existing
make simstill passes.