From bc29ea7f6d5794fc7dfa286323ff7f2372f4cd09 Mon Sep 17 00:00:00 2001 From: Nick Peluso <10912027+nap32@users.noreply.github.com> Date: Wed, 19 Nov 2025 07:20:43 -0800 Subject: [PATCH 1/4] Introduce RISC-V support in goodasm The language support files are duplicated - galangriscv.{cpp|h} and galangriscv32.{cpp|h}. This is with the intention of follow-up work to add galangriscv64.{cpp|h}, which the RISCV spec identifies as a distinct base ISA. To suppport or streamline compressed instruction extension encoding, a new feature was added to goodasm.cpp for rejectWhenZero constraint matching. This makes it easier to differentiate between some compressed instructions against c.nop or each other. There may be ways to resolve and improve the bitmask / match() without this, but did not appear to impact performance. (An alternative path is to generalize rejectWhenZero so that you can support arbitrary constraint matching - this might help with other languages with funky edge-cases in the future.) A large number of test cases were added to riscv/tests - including an instruction generation python script that attempted to bruteforce every possible valid instruction. The general testing approach was reflexive - encode .asm to binary, decode that binary to .disasm. If .asm and .disasm match, it increases confidence of the correct encoding. Formatting need{s/ed} to be accounted for and the possibility of incorrect binary representations remain - more robust testing would include QEMU virtualization. Various AI coding assistants were used in combination with manual effort in an attempt to explore LLM capabilities; this contribution is "spec-driven development" by definition. There is a chance errors slipped through despite best efforts to manually audit and refine. --- CMakeLists.txt | 1 + galangriscv.cpp | 4543 +++++++++++++++++ galangriscv.h | 341 ++ galangriscv32.cpp | 4543 +++++++++++++++++ galangriscv32.h | 341 ++ gamnemonic.cpp | 27 + gamnemonic.h | 8 + goodasm.cpp | 2 + main.cpp | 12 + tests/riscv/a-extension/amoadd.w.asm | 516 ++ tests/riscv/a-extension/amoadd.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amoadd.w.disasm | 512 ++ tests/riscv/a-extension/amoadd_w.asm | 5 + tests/riscv/a-extension/amoadd_w.bin | Bin 0 -> 4 bytes tests/riscv/a-extension/amoadd_w.disasm | 1 + tests/riscv/a-extension/amoand.w.asm | 516 ++ tests/riscv/a-extension/amoand.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amoand.w.disasm | 512 ++ tests/riscv/a-extension/amoand_w.asm | 5 + tests/riscv/a-extension/amoand_w.bin | 1 + tests/riscv/a-extension/amoand_w.disasm | 1 + tests/riscv/a-extension/amomax.w.asm | 516 ++ tests/riscv/a-extension/amomax.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amomax.w.disasm | 512 ++ tests/riscv/a-extension/amomax_w.asm | 5 + tests/riscv/a-extension/amomax_w.bin | 1 + tests/riscv/a-extension/amomax_w.disasm | 1 + tests/riscv/a-extension/amomaxu.w.asm | 516 ++ tests/riscv/a-extension/amomaxu.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amomaxu.w.disasm | 512 ++ tests/riscv/a-extension/amomaxu_w.asm | 5 + tests/riscv/a-extension/amomaxu_w.bin | 1 + tests/riscv/a-extension/amomaxu_w.disasm | 1 + tests/riscv/a-extension/amomin.w.asm | 516 ++ tests/riscv/a-extension/amomin.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amomin.w.disasm | 512 ++ tests/riscv/a-extension/amomin_w.asm | 5 + tests/riscv/a-extension/amomin_w.bin | 1 + tests/riscv/a-extension/amomin_w.disasm | 1 + tests/riscv/a-extension/amominu.w.asm | 516 ++ tests/riscv/a-extension/amominu.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amominu.w.disasm | 512 ++ tests/riscv/a-extension/amominu_w.asm | 5 + tests/riscv/a-extension/amominu_w.bin | 1 + tests/riscv/a-extension/amominu_w.disasm | 1 + tests/riscv/a-extension/amoor.w.asm | 516 ++ tests/riscv/a-extension/amoor.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amoor.w.disasm | 512 ++ tests/riscv/a-extension/amoor_w.asm | 5 + tests/riscv/a-extension/amoor_w.bin | 1 + tests/riscv/a-extension/amoor_w.disasm | 1 + tests/riscv/a-extension/amoswap.w.asm | 516 ++ tests/riscv/a-extension/amoswap.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amoswap.w.disasm | 512 ++ tests/riscv/a-extension/amoswap_w.asm | 5 + tests/riscv/a-extension/amoswap_w.bin | 1 + tests/riscv/a-extension/amoswap_w.disasm | 1 + tests/riscv/a-extension/amoxor.w.asm | 516 ++ tests/riscv/a-extension/amoxor.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/amoxor.w.disasm | 512 ++ tests/riscv/a-extension/amoxor_w.asm | 5 + tests/riscv/a-extension/amoxor_w.bin | 1 + tests/riscv/a-extension/amoxor_w.disasm | 1 + tests/riscv/a-extension/lr.w.asm | 68 + tests/riscv/a-extension/lr.w.bin | Bin 0 -> 256 bytes tests/riscv/a-extension/lr.w.disasm | 64 + tests/riscv/a-extension/lr_w.asm | 5 + tests/riscv/a-extension/lr_w.bin | 1 + tests/riscv/a-extension/lr_w.disasm | 1 + tests/riscv/a-extension/sc.w.asm | 516 ++ tests/riscv/a-extension/sc.w.bin | Bin 0 -> 2048 bytes tests/riscv/a-extension/sc.w.disasm | 512 ++ tests/riscv/a-extension/sc_w.asm | 5 + tests/riscv/a-extension/sc_w.bin | 1 + tests/riscv/a-extension/sc_w.disasm | 1 + tests/riscv/c-extension/c.add.asm | 53 + tests/riscv/c-extension/c.add.bin | 1 + tests/riscv/c-extension/c.add.disasm | 49 + tests/riscv/c-extension/c.addi.asm | 95 + tests/riscv/c-extension/c.addi.bin | Bin 0 -> 182 bytes tests/riscv/c-extension/c.addi.disasm | 91 + tests/riscv/c-extension/c.addi16sp.asm | 14 + tests/riscv/c-extension/c.addi16sp.bin | 1 + tests/riscv/c-extension/c.addi16sp.disasm | 46 + tests/riscv/c-extension/c.addi4spn.asm | 84 + tests/riscv/c-extension/c.addi4spn.bin | Bin 0 -> 160 bytes tests/riscv/c-extension/c.addi4spn.disasm | 80 + tests/riscv/c-extension/c.and.asm | 68 + tests/riscv/c-extension/c.and.bin | 1 + tests/riscv/c-extension/c.and.disasm | 64 + tests/riscv/c-extension/c.andi.asm | 108 + tests/riscv/c-extension/c.andi.bin | 1 + tests/riscv/c-extension/c.andi.disasm | 104 + tests/riscv/c-extension/c.beqz.asm | 164 + tests/riscv/c-extension/c.beqz.bin | 1 + tests/riscv/c-extension/c.beqz.disasm | 80 + tests/riscv/c-extension/c.bnez.asm | 164 + tests/riscv/c-extension/c.bnez.bin | 1 + tests/riscv/c-extension/c.bnez.disasm | 80 + tests/riscv/c-extension/c.ebreak.asm | 5 + tests/riscv/c-extension/c.ebreak.bin | 1 + tests/riscv/c-extension/c.ebreak.disasm | 10 + tests/riscv/c-extension/c.j.asm | 24 + tests/riscv/c-extension/c.j.bin | 1 + tests/riscv/c-extension/c.j.disasm | 10 + tests/riscv/c-extension/c.jalr.asm | 11 + tests/riscv/c-extension/c.jalr.bin | 1 + tests/riscv/c-extension/c.jalr.disasm | 34 + tests/riscv/c-extension/c.jr.asm | 11 + tests/riscv/c-extension/c.jr.bin | 1 + tests/riscv/c-extension/c.jr.disasm | 7 + tests/riscv/c-extension/c.li.asm | 95 + tests/riscv/c-extension/c.li.bin | 1 + tests/riscv/c-extension/c.li.disasm | 91 + tests/riscv/c-extension/c.lui.asm | 62 + tests/riscv/c-extension/c.lui.bin | 1 + tests/riscv/c-extension/c.lui.disasm | 54 + tests/riscv/c-extension/c.lw.asm | 452 ++ tests/riscv/c-extension/c.lw.bin | Bin 0 -> 896 bytes tests/riscv/c-extension/c.lw.disasm | 448 ++ tests/riscv/c-extension/c.lwsp.asm | 60 + tests/riscv/c-extension/c.lwsp.bin | 3 + tests/riscv/c-extension/c.lwsp.disasm | 56 + tests/riscv/c-extension/c.mv.asm | 53 + tests/riscv/c-extension/c.mv.bin | 1 + tests/riscv/c-extension/c.mv.disasm | 49 + tests/riscv/c-extension/c.nop.asm | 5 + tests/riscv/c-extension/c.nop.bin | Bin 0 -> 2 bytes tests/riscv/c-extension/c.nop.disasm | 1 + tests/riscv/c-extension/c.or.asm | 68 + tests/riscv/c-extension/c.or.bin | 1 + tests/riscv/c-extension/c.or.disasm | 64 + tests/riscv/c-extension/c.slli.asm | 53 + tests/riscv/c-extension/c.slli.bin | Bin 0 -> 98 bytes tests/riscv/c-extension/c.slli.disasm | 49 + tests/riscv/c-extension/c.srai.asm | 60 + tests/riscv/c-extension/c.srai.bin | 1 + tests/riscv/c-extension/c.srai.disasm | 56 + tests/riscv/c-extension/c.srli.asm | 60 + tests/riscv/c-extension/c.srli.bin | 1 + tests/riscv/c-extension/c.srli.disasm | 56 + tests/riscv/c-extension/c.sub.asm | 68 + tests/riscv/c-extension/c.sub.bin | 1 + tests/riscv/c-extension/c.sub.disasm | 64 + tests/riscv/c-extension/c.sw.asm | 452 ++ tests/riscv/c-extension/c.sw.bin | Bin 0 -> 896 bytes tests/riscv/c-extension/c.sw.disasm | 448 ++ tests/riscv/c-extension/c.swsp.asm | 60 + tests/riscv/c-extension/c.swsp.bin | 1 + tests/riscv/c-extension/c.swsp.disasm | 56 + tests/riscv/c-extension/c.xor.asm | 68 + tests/riscv/c-extension/c.xor.bin | 1 + tests/riscv/c-extension/c.xor.disasm | 64 + tests/riscv/c-extension/c_add.asm | 53 + tests/riscv/c-extension/c_add.bin | 1 + tests/riscv/c-extension/c_add.disasm | 49 + tests/riscv/c-extension/c_addi.asm | 5 + tests/riscv/c-extension/c_addi.bin | 1 + tests/riscv/c-extension/c_addi.disasm | 1 + tests/riscv/c-extension/c_addi16sp.asm | 5 + tests/riscv/c-extension/c_addi16sp.bin | 1 + tests/riscv/c-extension/c_addi16sp.disasm | 10 + tests/riscv/c-extension/c_addi4spn.asm | 5 + tests/riscv/c-extension/c_addi4spn.bin | 1 + tests/riscv/c-extension/c_addi4spn.disasm | 1 + tests/riscv/c-extension/c_and.asm | 5 + tests/riscv/c-extension/c_and.bin | 1 + tests/riscv/c-extension/c_and.disasm | 1 + tests/riscv/c-extension/c_andi.asm | 5 + tests/riscv/c-extension/c_andi.bin | 1 + tests/riscv/c-extension/c_andi.disasm | 1 + tests/riscv/c-extension/c_andi_edge_cases.asm | 50 + tests/riscv/c-extension/c_andi_edge_cases.bin | 1 + .../c-extension/c_andi_edge_cases.disasm | 31 + tests/riscv/c-extension/c_beqz.asm | 6 + tests/riscv/c-extension/c_beqz.bin | 1 + tests/riscv/c-extension/c_beqz.disasm | 1 + tests/riscv/c-extension/c_beqz_edge_cases.asm | 56 + tests/riscv/c-extension/c_beqz_edge_cases.bin | 1 + .../c-extension/c_beqz_edge_cases.disasm | 29 + tests/riscv/c-extension/c_bnez.asm | 6 + tests/riscv/c-extension/c_bnez.bin | 1 + tests/riscv/c-extension/c_bnez.disasm | 1 + tests/riscv/c-extension/c_ebreak.asm | 5 + tests/riscv/c-extension/c_ebreak.bin | 1 + tests/riscv/c-extension/c_ebreak.disasm | 10 + tests/riscv/c-extension/c_j.asm | 6 + tests/riscv/c-extension/c_j.bin | 1 + tests/riscv/c-extension/c_j.disasm | 1 + tests/riscv/c-extension/c_jalr.asm | 5 + tests/riscv/c-extension/c_jalr.bin | 1 + tests/riscv/c-extension/c_jalr.disasm | 10 + tests/riscv/c-extension/c_jalr_edge_cases.asm | 28 + tests/riscv/c-extension/c_jalr_edge_cases.bin | 1 + .../c-extension/c_jalr_edge_cases.disasm | 74 + tests/riscv/c-extension/c_jr.asm | 5 + tests/riscv/c-extension/c_jr.bin | 1 + tests/riscv/c-extension/c_jr.disasm | 1 + tests/riscv/c-extension/c_li.asm | 5 + tests/riscv/c-extension/c_li.bin | 1 + tests/riscv/c-extension/c_li.disasm | 1 + tests/riscv/c-extension/c_lui.asm | 5 + tests/riscv/c-extension/c_lui.bin | 1 + tests/riscv/c-extension/c_lui.disasm | 1 + tests/riscv/c-extension/c_lui_edge_cases.asm | 51 + tests/riscv/c-extension/c_lui_edge_cases.bin | 1 + .../riscv/c-extension/c_lui_edge_cases.disasm | 34 + tests/riscv/c-extension/c_lw.asm | 5 + tests/riscv/c-extension/c_lw.bin | 1 + tests/riscv/c-extension/c_lw.disasm | 1 + tests/riscv/c-extension/c_lwsp.asm | 5 + tests/riscv/c-extension/c_lwsp.bin | 1 + tests/riscv/c-extension/c_lwsp.disasm | 1 + tests/riscv/c-extension/c_mv.asm | 5 + tests/riscv/c-extension/c_mv.bin | 1 + tests/riscv/c-extension/c_mv.disasm | 1 + tests/riscv/c-extension/c_mv_edge_cases.asm | 120 + tests/riscv/c-extension/c_mv_edge_cases.bin | 3 + .../riscv/c-extension/c_mv_edge_cases.disasm | 91 + tests/riscv/c-extension/c_nop.asm | 5 + tests/riscv/c-extension/c_nop.bin | Bin 0 -> 2 bytes tests/riscv/c-extension/c_nop.disasm | 1 + tests/riscv/c-extension/c_or.asm | 5 + tests/riscv/c-extension/c_or.bin | 1 + tests/riscv/c-extension/c_or.disasm | 1 + tests/riscv/c-extension/c_slli.asm | 5 + tests/riscv/c-extension/c_slli.bin | 1 + tests/riscv/c-extension/c_slli.disasm | 1 + tests/riscv/c-extension/c_srai.asm | 5 + tests/riscv/c-extension/c_srai.bin | 1 + tests/riscv/c-extension/c_srai.disasm | 1 + tests/riscv/c-extension/c_srli.asm | 5 + tests/riscv/c-extension/c_srli.bin | 1 + tests/riscv/c-extension/c_srli.disasm | 1 + tests/riscv/c-extension/c_sub.asm | 5 + tests/riscv/c-extension/c_sub.bin | 1 + tests/riscv/c-extension/c_sub.disasm | 1 + tests/riscv/c-extension/c_sw.asm | 5 + tests/riscv/c-extension/c_sw.bin | 1 + tests/riscv/c-extension/c_sw.disasm | 1 + tests/riscv/c-extension/c_swsp.asm | 47 + tests/riscv/c-extension/c_swsp.bin | 2 + tests/riscv/c-extension/c_swsp.disasm | 34 + tests/riscv/c-extension/c_xor.asm | 5 + tests/riscv/c-extension/c_xor.bin | 1 + tests/riscv/c-extension/c_xor.disasm | 1 + tests/riscv/c-extension/c_xor_a5.asm | 5 + tests/riscv/c-extension/c_xor_a5.bin | 1 + tests/riscv/c-extension/c_xor_a5.disasm | 1 + tests/riscv/c-extension/c_xor_all_regs.asm | 8 + tests/riscv/c-extension/c_xor_all_regs.bin | 1 + tests/riscv/c-extension/c_xor_all_regs.disasm | 4 + tests/riscv/c-extension/c_xor_mixed.asm | 8 + tests/riscv/c-extension/c_xor_mixed.bin | 1 + tests/riscv/c-extension/c_xor_mixed.disasm | 4 + tests/riscv/c-extension/c_xor_s0.asm | 5 + tests/riscv/c-extension/c_xor_s0.bin | 1 + tests/riscv/c-extension/c_xor_s0.disasm | 1 + tests/riscv/c-extension/c_xor_same_reg.asm | 5 + tests/riscv/c-extension/c_xor_same_reg.bin | 1 + tests/riscv/c-extension/c_xor_same_reg.disasm | 1 + tests/riscv/d-extension/fadd.d.asm | 516 ++ tests/riscv/d-extension/fadd.d.bin | Bin 0 -> 2048 bytes tests/riscv/d-extension/fadd.d.disasm | 512 ++ tests/riscv/d-extension/fadd_d.asm | 5 + tests/riscv/d-extension/fadd_d.bin | 1 + tests/riscv/d-extension/fadd_d.disasm | 1 + tests/riscv/d-extension/fclass.d.asm | 68 + tests/riscv/d-extension/fclass.d.bin | Bin 0 -> 256 bytes tests/riscv/d-extension/fclass.d.disasm | 64 + tests/riscv/d-extension/fclass_d.asm | 5 + tests/riscv/d-extension/fclass_d.bin | Bin 0 -> 4 bytes tests/riscv/d-extension/fclass_d.disasm | 1 + tests/riscv/d-extension/fcvt.d.s.asm | 68 + tests/riscv/d-extension/fcvt.d.s.bin | Bin 0 -> 256 bytes tests/riscv/d-extension/fcvt.d.s.disasm | 64 + tests/riscv/d-extension/fcvt.d.w.asm | 68 + tests/riscv/d-extension/fcvt.d.w.bin | Bin 0 -> 256 bytes tests/riscv/d-extension/fcvt.d.w.disasm | 64 + tests/riscv/d-extension/fcvt.d.wu.asm | 68 + tests/riscv/d-extension/fcvt.d.wu.bin | Bin 0 -> 256 bytes tests/riscv/d-extension/fcvt.d.wu.disasm | 64 + tests/riscv/d-extension/fcvt.s.d.asm | 68 + tests/riscv/d-extension/fcvt.s.d.bin | Bin 0 -> 256 bytes tests/riscv/d-extension/fcvt.s.d.disasm | 64 + tests/riscv/d-extension/fcvt.w.d.asm | 68 + tests/riscv/d-extension/fcvt.w.d.bin | Bin 0 -> 256 bytes tests/riscv/d-extension/fcvt.w.d.disasm | 64 + tests/riscv/d-extension/fcvt.wu.d.asm | 68 + tests/riscv/d-extension/fcvt.wu.d.bin | Bin 0 -> 256 bytes tests/riscv/d-extension/fcvt.wu.d.disasm | 64 + tests/riscv/d-extension/fcvt_d_s.asm | 5 + tests/riscv/d-extension/fcvt_d_s.bin | Bin 0 -> 4 bytes tests/riscv/d-extension/fcvt_d_s.disasm | 1 + tests/riscv/d-extension/fcvt_d_w.asm | 5 + tests/riscv/d-extension/fcvt_d_w.bin | 1 + tests/riscv/d-extension/fcvt_d_w.disasm | 1 + tests/riscv/d-extension/fcvt_d_wu.asm | 5 + tests/riscv/d-extension/fcvt_d_wu.bin | 1 + tests/riscv/d-extension/fcvt_d_wu.disasm | 1 + tests/riscv/d-extension/fcvt_s_d.asm | 5 + tests/riscv/d-extension/fcvt_s_d.bin | Bin 0 -> 4 bytes tests/riscv/d-extension/fcvt_s_d.disasm | 1 + tests/riscv/d-extension/fcvt_w_d.asm | 5 + tests/riscv/d-extension/fcvt_w_d.bin | Bin 0 -> 4 bytes tests/riscv/d-extension/fcvt_w_d.disasm | 1 + tests/riscv/d-extension/fcvt_wu_d.asm | 5 + tests/riscv/d-extension/fcvt_wu_d.bin | Bin 0 -> 4 bytes tests/riscv/d-extension/fcvt_wu_d.disasm | 1 + tests/riscv/d-extension/fdiv.d.asm | 516 ++ tests/riscv/d-extension/fdiv.d.bin | Bin 0 -> 2048 bytes tests/riscv/d-extension/fdiv.d.disasm | 512 ++ tests/riscv/d-extension/fdiv_d.asm | 5 + tests/riscv/d-extension/fdiv_d.bin | 1 + tests/riscv/d-extension/fdiv_d.disasm | 1 + tests/riscv/d-extension/feq.d.asm | 516 ++ tests/riscv/d-extension/feq.d.bin | Bin 0 -> 2048 bytes tests/riscv/d-extension/feq.d.disasm | 512 ++ tests/riscv/d-extension/feq_d.asm | 5 + tests/riscv/d-extension/feq_d.bin | 1 + tests/riscv/d-extension/feq_d.disasm | 1 + tests/riscv/d-extension/fld.asm | 1604 ++++++ tests/riscv/d-extension/fld.bin | Bin 0 -> 6400 bytes tests/riscv/d-extension/fld.disasm | 1600 ++++++ tests/riscv/d-extension/fle.d.asm | 516 ++ tests/riscv/d-extension/fle.d.bin | Bin 0 -> 2048 bytes tests/riscv/d-extension/fle.d.disasm | 512 ++ tests/riscv/d-extension/fle_d.asm | 5 + tests/riscv/d-extension/fle_d.bin | 1 + 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tests/riscv/d-extension/fmin.d.disasm | 512 ++ tests/riscv/d-extension/fmin_d.asm | 5 + tests/riscv/d-extension/fmin_d.bin | 1 + tests/riscv/d-extension/fmin_d.disasm | 1 + tests/riscv/d-extension/fmsub.d.asm | 4100 +++++++++++++++ tests/riscv/d-extension/fmsub.d.bin | Bin 0 -> 16384 bytes tests/riscv/d-extension/fmsub.d.disasm | 4096 +++++++++++++++ tests/riscv/d-extension/fmsub_d.asm | 5 + tests/riscv/d-extension/fmsub_d.bin | 1 + tests/riscv/d-extension/fmsub_d.disasm | 1 + tests/riscv/d-extension/fmul.d.asm | 516 ++ tests/riscv/d-extension/fmul.d.bin | Bin 0 -> 2048 bytes tests/riscv/d-extension/fmul.d.disasm | 512 ++ tests/riscv/d-extension/fmul_d.asm | 5 + tests/riscv/d-extension/fmul_d.bin | 1 + tests/riscv/d-extension/fmul_d.disasm | 1 + tests/riscv/d-extension/fnmadd.d.asm | 4100 +++++++++++++++ tests/riscv/d-extension/fnmadd.d.bin | Bin 0 -> 16384 bytes tests/riscv/d-extension/fnmadd.d.disasm | 4096 +++++++++++++++ tests/riscv/d-extension/fnmadd_d.asm | 5 + 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0000000..ca2e0ba --- /dev/null +++ b/galangriscv.cpp @@ -0,0 +1,4543 @@ +#include "goodasm.h" + +#include "galangriscv.h" + +#include "gamnemonic.h" + +#define mnem new GAMnemonic + +// https://riscv.org/specifications/ratified/ +// https://msyksphinz-self.github.io/riscv-isadoc/ +// Follow RISC-V Instruction Organization from the ISA Manual + +GALangRISCV::GALangRISCV() { + endian = LITTLE; + name = "riscv"; + maxbytes = 4; // Maximum instruction length (32-bit or 16-bit compressed) + + // Register names. + regnames.clear(); + regnames + <<"zero"<<"ra"<<"sp"<<"gp"<<"tp" + <<"t0"<<"t1"<<"t2" + <<"s0"<<"s1" + <<"a0"<<"a1"<<"a2"<<"a3"<<"a4"<<"a5"<<"a6"<<"a7" + <<"s2"<<"s3"<<"s4"<<"s5"<<"s6"<<"s7"<<"s8"<<"s9"<<"s10"<<"s11" + <<"t3"<<"t4"<<"t5"<<"t6" + // Floating point registers f0-f31 + <<"f0"<<"f1"<<"f2"<<"f3"<<"f4"<<"f5"<<"f6"<<"f7" + <<"f8"<<"f9"<<"f10"<<"f11"<<"f12"<<"f13"<<"f14"<<"f15" + <<"f16"<<"f17"<<"f18"<<"f19"<<"f20"<<"f21"<<"f22"<<"f23" + <<"f24"<<"f25"<<"f26"<<"f27"<<"f28"<<"f29"<<"f30"<<"f31"; + + threshold = 0.0; + + /* Integer Computational Instructions (RV32I Base) */ + + /* R-Type Instructions */ + + /* + * Example: ADD rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00000033 (funct7=0x00, funct3=000 + opcode=0x33) + */ + insert( + mnem("add", 4, + "\x33\x00\x00\x00", // pattern 32-bit LE: 0x00000033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Add: rd = rs1 + rs2") + ->example("add a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SUB rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x40000033 (funct7=0x20=bit30, funct3=000 + opcode=0x33) + */ + insert( + mnem("sub", 4, + "\x33\x00\x00\x40", // pattern 32-bit LE: 0x40000033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Subtract: rd = rs1 - rs2") + ->example("sub a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SLL rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00100033 (funct7=0x00, funct3=001 + opcode=0x33) + */ + insert( + mnem("sll", 4, + "\x33\x10\x00\x00", // pattern 32-bit LE: 0x00100033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Left Logical: rd = rs1 << rs2[4:0]") + ->example("sll a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SLT rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00200033 (funct7=0x00, funct3=010 + opcode=0x33) + */ + insert( + mnem("slt", 4, + "\x33\x20\x00\x00", // pattern 32-bit LE: 0x00200033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Set Less Than: rd = (rs1 < rs2) ? 1 : 0 (signed)") + ->example("slt a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SLTU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00300033 (funct7=0x00, funct3=011 + opcode=0x33) + */ + insert( + mnem("sltu", 4, + "\x33\x30\x00\x00", // pattern 32-bit LE: 0x00300033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Set Less Than Unsigned: rd = (rs1 < rs2) ? 1 : 0 (unsigned)") + ->example("sltu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: XOR rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00400033 (funct7=0x00, funct3=100 + opcode=0x33) + */ + insert( + mnem("xor", 4, + "\x33\x40\x00\x00", // pattern 32-bit LE: 0x00400033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Bitwise XOR: rd = rs1 ^ rs2") + ->example("xor a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SRL rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00500033 (funct7=0x00, funct3=101 + opcode=0x33) + */ + insert( + mnem("srl", 4, + "\x33\x50\x00\x00", // pattern 32-bit LE: 0x00500033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Right Logical: rd = rs1 >> rs2[4:0]") + ->example("srl a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SRA rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x40500033 (funct7=0x20=bit30, funct3=101 + opcode=0x33) + */ + insert( + mnem("sra", 4, + "\x33\x50\x00\x40", // pattern 32-bit LE: 0x40500033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Right Arithmetic: rd = rs1 >> rs2[4:0] (sign-extended)") + ->example("sra a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: OR rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00600033 (funct7=0x00, funct3=110 + opcode=0x33) + */ + insert( + mnem("or", 4, + "\x33\x60\x00\x00", // pattern 32-bit LE: 0x00600033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Bitwise OR: rd = rs1 | rs2") + ->example("or a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: AND rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00700033 (funct7=0x00, funct3=111 + opcode=0x33) + */ + insert( + mnem("and", 4, + "\x33\x70\x00\x00", // pattern 32-bit LE: 0x00700033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Bitwise AND: rd = rs1 & rs2") + ->example("and a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* I-Type Instructions */ + + /* + * Example: ADDI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000013 (funct3=000 + opcode=0x13) + */ + insert( + mnem("addi", 4, + "\x13\x00\x00\x00", // pattern 32-bit LE: 0x00000013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Add immediate: rd = rs1 + imm") + ->example("addi a0, a0, #1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: SLTI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002013 (funct3=010 + opcode=0x13) + */ + insert( + mnem("slti", 4, + "\x13\x20\x00\x00", // pattern 32-bit LE: 0x00002013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Set Less Than Immediate: rd = (rs1 < imm) ? 1 : 0 (signed)") + ->example("slti a0, a1, #10") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: SLTIU rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00003013 (funct3=011 + opcode=0x13) + */ + insert( + mnem("sltiu", 4, + "\x13\x30\x00\x00", // pattern 32-bit LE: 0x00003013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Set Less Than Immediate Unsigned: rd = (rs1 < imm) ? 1 : 0 (unsigned)") + ->example("sltiu a0, a1, #10") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: XORI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00004013 (funct3=100 + opcode=0x13) + */ + insert( + mnem("xori", 4, + "\x13\x40\x00\x00", // pattern 32-bit LE: 0x00004013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("XOR Immediate: rd = rs1 ^ imm") + ->example("xori a0, a1, #0xFF") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: ORI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00006013 (funct3=110 + opcode=0x13) + */ + insert( + mnem("ori", 4, + "\x13\x60\x00\x00", // pattern 32-bit LE: 0x00006013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("OR Immediate: rd = rs1 | imm") + ->example("ori a0, a1, #0xFF") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: ANDI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00007013 (funct3=111 + opcode=0x13) + */ + insert( + mnem("andi", 4, + "\x13\x70\x00\x00", // pattern 32-bit LE: 0x00007013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("AND Immediate: rd = rs1 & imm") + ->example("andi a0, a1, #0xFF") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* I-type Shift Immediate Instructions */ + + /* + * Example: SLLI rd, rs1, shamt5 + * + * Encoding: + * shamt[4:0] rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00100013 (funct7=0x00, funct3=001 + opcode=0x13) + * + * shamt[4:0] is in bits [24:20] + */ + insert( + mnem("slli", 4, + "\x13\x10\x00\x00", // pattern 32-bit LE: 0x00100013 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Left Logical Immediate: rd = rs1 << shamt") + ->example("slli a0, a1, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] + + /* + * Example: SRLI rd, rs1, shamt5 + * + * Encoding: + * shamt[4:0] rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00500013 (funct7=0x00, funct3=101 + opcode=0x13) + */ + insert( + mnem("srli", 4, + "\x13\x50\x00\x00", // pattern 32-bit LE: 0x00500013 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Right Logical Immediate: rd = rs1 >> shamt") + ->example("srli a0, a1, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] + + /* + * Example: SRAI rd, rs1, shamt5 + * + * Encoding: + * shamt[4:0] rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x40500013 (funct7=0x20, funct3=101 + opcode=0x13) + */ + insert( + mnem("srai", 4, + "\x13\x50\x00\x40", // pattern 32-bit LE: 0x40500013 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Right Arithmetic Immediate: rd = rs1 >> shamt (sign-extended)") + ->example("srai a0, a1, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] + + /* Control Transfer Instructions */ + + /* U-Type Control Transfer Instructions */ + + /* + * Example: LUI rd, imm20 + * + * Encoding: + * imm[31:12] rd opcode + * + * Mask : 0x0000007F (mask opcode) + * Value : 0x00000037 (opcode=0x37) + */ + insert( + mnem("lui", 4, + "\x37\x00\x00\x00", // pattern 32-bit LE: 0x00000037 + "\x7F\x00\x00\x00")) // mask: opcode only + ->help("Load Upper Immediate: rd = imm << 12") + ->example("lui a0, #0x12345000") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvUtypeImm20("\x00\xF0\xFF\xFF")); // imm[31:12] bits [31:12] + + /* + * Example: AUIPC rd, imm20 + * + * Encoding: + * imm[31:12] rd opcode + * + * Mask : 0x0000007F (mask opcode) + * Value : 0x00000017 (opcode=0x17) + */ + insert( + mnem("auipc", 4, + "\x17\x00\x00\x00", // pattern 32-bit LE: 0x00000017 + "\x7F\x00\x00\x00")) // mask: opcode only + ->help("Add Upper Immediate to PC: rd = PC + (imm << 12)") + ->example("auipc a0, #0x12345000") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvUtypeImm20("\x00\xF0\xFF\xFF")); // imm[31:12] bits [31:12] + + /* J-Type Control Transfer Instructions */ + + /* + * Example: JAL rd, imm21 + * + * Encoding: + * imm[20|10:1|11|19:12] rd opcode + * + * Mask : 0x0000007F (mask opcode) + * Value : 0x0000006F (opcode=0x6F) + */ + insert( + mnem("jal", 4, + "\x6F\x00\x00\x00", // pattern 32-bit LE: 0x0000006F + "\x7F\x00\x00\x00")) // mask: opcode only + ->help("Jump and Link: rd = PC + 4; PC += imm") + ->example("jal ra, #8") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvJtypeImm21("\x00\xF0\xFF\xFF")); // imm[20:1] in bits [31:12] + + /* I-Type Control Transfer Instructions */ + + /* + * Example: JALR rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000067 (funct3=000 + opcode=0x67) + */ + insert( + mnem("jalr", 4, + "\x67\x00\x00\x00", // pattern 32-bit LE: 0x00000067 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Jump and Link Register: rd = PC + 4; PC = (rs1 + imm) & ~1") + ->example("jalr ra, a1, #0") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] + + /* B-Type Control Transfer Instructions */ + + /* + * Example: BEQ rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000063 (funct3=000 + opcode=0x63) + */ + insert( + mnem("beq", 4, + "\x63\x00\x00\x00", // pattern 32-bit LE: 0x00000063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Equal: if (rs1 == rs2) PC += imm") + ->example("beq a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BNE rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00001063 (funct3=001 + opcode=0x63) + */ + insert( + mnem("bne", 4, + "\x63\x10\x00\x00", // pattern 32-bit LE: 0x00100063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Not Equal: if (rs1 != rs2) PC += imm") + ->example("bne a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BLT rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00004063 (funct3=100 + opcode=0x63) + */ + insert( + mnem("blt", 4, + "\x63\x40\x00\x00", // pattern 32-bit LE: 0x00004063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Less Than: if (rs1 < rs2) PC += imm (signed)") + ->example("blt a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BGE rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00005063 (funct3=101 + opcode=0x63) + */ + insert( + mnem("bge", 4, + "\x63\x50\x00\x00", // pattern 32-bit LE: 0x00005063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Greater or Equal: if (rs1 >= rs2) PC += imm (signed)") + ->example("bge a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BLTU rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00006063 (funct3=110 + opcode=0x63) + */ + insert( + mnem("bltu", 4, + "\x63\x60\x00\x00", // pattern 32-bit LE: 0x00006063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Less Than Unsigned: if (rs1 < rs2) PC += imm (unsigned)") + ->example("bltu a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BGEU rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00007063 (funct3=111 + opcode=0x63) + */ + insert( + mnem("bgeu", 4, + "\x63\x70\x00\x00", // pattern 32-bit LE: 0x00007063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Greater or Equal Unsigned: if (rs1 >= rs2) PC += imm (unsigned)") + ->example("bgeu a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* Load Instructions */ + + /* + * Example: LB rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000003 (funct3=000 + opcode=0x03) + */ + insert( + mnem("lb", 4, + "\x03\x00\x00\x00", // pattern 32-bit LE: 0x00000003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Byte (signed): rd = sign-extend(M[rs1 + imm][7:0])") + ->example("lb a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: LH rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00001003 (funct3=001 + opcode=0x03) + */ + insert( + mnem("lh", 4, + "\x03\x10\x00\x00", // pattern 32-bit LE: 0x00001003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Halfword (signed): rd = sign-extend(M[rs1 + imm][15:0])") + ->example("lh a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: LW rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002003 (funct3=010 + opcode=0x03) + */ + insert( + mnem("lw", 4, + "\x03\x20\x00\x00", // pattern 32-bit LE: 0x00002003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Word: rd = M[rs1 + imm][31:0]") + ->example("lw a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: LBU rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00004003 (funct3=100 + opcode=0x03) + */ + insert( + mnem("lbu", 4, + "\x03\x40\x00\x00", // pattern 32-bit LE: 0x00004003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Byte Unsigned: rd = zero-extend(M[rs1 + imm][7:0])") + ->example("lbu a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: LHU rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00005003 (funct3=101 + opcode=0x03) + */ + insert( + mnem("lhu", 4, + "\x03\x50\x00\x00", // pattern 32-bit LE: 0x00005003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Halfword Unsigned: rd = zero-extend(M[rs1 + imm][15:0])") + ->example("lhu a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* Store Instructions */ + + /* + * Example: SB rs2, imm(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000023 (funct3=000 + opcode=0x23) + */ + insert( + mnem("sb", 4, + "\x23\x00\x00\x00", // pattern 32-bit LE: 0x00000023 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Store Byte: M[rs1 + imm] = rs2[7:0]") + ->example("sb a1, (#4, a0)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: SH rs2, imm(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00001023 (funct3=001 + opcode=0x23) + */ + insert( + mnem("sh", 4, + "\x23\x10\x00\x00", // pattern 32-bit LE: 0x00001023 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Store Halfword: M[rs1 + imm] = rs2[15:0]") + ->example("sh a1, (#4, a0)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: SW rs2, imm(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002023 (funct3=010 + opcode=0x23) + */ + insert( + mnem("sw", 4, + "\x23\x20\x00\x00", // pattern 32-bit LE: 0x00002023 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Store Word: M[rs1 + imm] = rs2[31:0]") + ->example("sw a1, (#4, a0)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* System Instructions */ + + /* Memory Ordering Instructions (RV32I Base) */ + + /* + * Example: FENCE pred, succ + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x0000000F (funct3=000 + opcode=0x0F) + * + * pred[3:0] in imm[3:0] (bits [23:20]) + * succ[3:0] in imm[7:4] (bits [27:24]) + * rs1 and rd are typically zero but can be non-zero + */ + // Simple fence (no arguments) - defaults to fence iorw, iorw (full barrier) + // Encoding: 0x0FF0000F - pred=1111, succ=1111, rs1=x0, rd=x0 + insert( + mnem("fence", 4, + "\x0F\x00\xF0\x0F", // pattern 32-bit LE: 0x0FF0000F (fence iorw, iorw) + "\xFF\xFF\xFF\xFF")) // exact match - no variable bits + ->help("Memory Ordering Fence (full barrier): fence iorw, iorw") + ->example("fence"); + + // Fence with explicit pred/succ and registers + insert( + mnem("fence", 4, + "\x0F\x00\x00\x00", // pattern 32-bit LE: 0x0000000F + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Memory Ordering Fence: orders memory operations") + ->example("fence #0xFF, zero, zero") + ->insert(new GAParameterRiscvFencePredSucc("\x00\x00\xF0\x0F")) // pred/succ in imm[7:0] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] (typically zero) + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] (typically zero) + + /* + * Example: FENCE.I + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x0000100F (funct3=001 + opcode=0x0F) + * + * All fields except funct3 and opcode are zero + */ + insert( + mnem("fence.i", 4, + "\x0F\x10\x00\x00", // pattern 32-bit LE: 0x0000100F + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Instruction Fence: synchronizes instruction and data streams") + ->example("fence.i"); + + /* Environment Call and Breakpoints */ + + /* + * Example: ECALL + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000073 (funct3=000 + opcode=0x73) + * + * All fields except funct3 and opcode are zero + * Note: imm[0]=0, so no mask needed for byte 2 (unlike EBREAK) + */ + insert( + mnem("ecall", 4, + "\x73\x00\x00\x00", // pattern 32-bit LE: 0x00000073 + "\x7F\x70\x10\x00")) // mask: opcode + funct3 + imm[0] (bit 20 = byte 2 bit 4, must be 0) + ->help("Environment Call: makes a request to the execution environment") + ->example("ecall"); + + /* + * Example: EBREAK + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00100073 (funct3=000 + opcode=0x73 + imm[0]=1) + * + * imm[0]=1 (bit 20), all other fields except funct3 and opcode are zero + */ + insert( + mnem("ebreak", 4, + "\x73\x00\x10\x00", // pattern 32-bit LE: 0x00100073 (imm[0]=1 in bit 20) + "\x7F\x70\x10\x00")) // mask: opcode + funct3 + imm[0] (bit 20 = byte 2 bit 4) + ->help("Environment Break: causes a breakpoint exception") + ->example("ebreak"); + + /* M Extension Instructions */ + + /* + * Example: MUL rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02000033 (funct7=0x01, funct3=000 + opcode=0x33) + */ + insert( + mnem("mul", 4, + "\x33\x00\x00\x02", // pattern 32-bit LE: 0x02000033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Multiply: rd = (rs1 * rs2)[XLEN-1:0] (lower XLEN bits)") + ->example("mul a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: MULH rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02001033 (funct7=0x01, funct3=001 + opcode=0x33) + */ + insert( + mnem("mulh", 4, + "\x33\x10\x00\x02", // pattern 32-bit LE: 0x02001033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Multiply High (signed × signed): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") + ->example("mulh a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: MULHSU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02002033 (funct7=0x01, funct3=010 + opcode=0x33) + */ + insert( + mnem("mulhsu", 4, + "\x33\x20\x00\x02", // pattern 32-bit LE: 0x02002033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Multiply High (signed × unsigned): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") + ->example("mulhsu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: MULHU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02003033 (funct7=0x01, funct3=011 + opcode=0x33) + */ + insert( + mnem("mulhu", 4, + "\x33\x30\x00\x02", // pattern 32-bit LE: 0x02003033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Multiply High (unsigned × unsigned): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") + ->example("mulhu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: DIV rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02004033 (funct7=0x01, funct3=100 + opcode=0x33) + */ + insert( + mnem("div", 4, + "\x33\x40\x00\x02", // pattern 32-bit LE: 0x02004033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Divide (signed): rd = rs1 / rs2") + ->example("div a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: DIVU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02005033 (funct7=0x01, funct3=101 + opcode=0x33) + */ + insert( + mnem("divu", 4, + "\x33\x50\x00\x02", // pattern 32-bit LE: 0x02005033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Divide (unsigned): rd = rs1 / rs2") + ->example("divu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: REM rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02006033 (funct7=0x01, funct3=110 + opcode=0x33) + */ + insert( + mnem("rem", 4, + "\x33\x60\x00\x02", // pattern 32-bit LE: 0x02006033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Remainder (signed): rd = rs1 % rs2") + ->example("rem a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: REMU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02007033 (funct7=0x01, funct3=111 + opcode=0x33) + */ + insert( + mnem("remu", 4, + "\x33\x70\x00\x02", // pattern 32-bit LE: 0x02007033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Remainder (unsigned): rd = rs1 % rs2") + ->example("remu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* Atomic Memory Instructions Extension (RV32A) */ + + /* + * Example: LR.W rd, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode, rs2 must be 0) + * Value : 0x1000202F (funct5=00010, aq=0, rl=0, rs2=00000, funct3=010, opcode=0x2F) + * + * funct5[4:0] = 00010 (0x02) in bits [31:27] + * aq = 0 in bit [26] + * rl = 0 in bit [25] + * rs2 = 00000 (reserved, must be zero) in bits [24:20] + */ + insert( + mnem("lr.w", 4, + "\x2F\x20\x00\x10", // pattern 32-bit LE: 0x1000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 (aq/rl default to 0) + ->help("Load Reserved Word: rd = M[rs1]; reserve address") + ->example("lr.w a0, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: SC.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x1800202F (funct5=00011, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("sc.w", 4, + "\x2F\x20\x00\x18", // pattern 32-bit LE: 0x1800202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Store Conditional Word: if reserved, M[rs1] = rs2, rd = 0; else rd != 0") + ->example("sc.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOSWAP.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x0800202F (funct5=00001, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoswap.w", 4, + "\x2F\x20\x00\x08", // pattern 32-bit LE: 0x0800202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Swap Word: temp = M[rs1]; M[rs1] = rs2; rd = temp") + ->example("amoswap.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOADD.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x0000202F (funct5=00000, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoadd.w", 4, + "\x2F\x20\x00\x00", // pattern 32-bit LE: 0x0000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Add Word: temp = M[rs1]; M[rs1] = temp + rs2; rd = temp") + ->example("amoadd.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOXOR.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x2000202F (funct5=00100, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoxor.w", 4, + "\x2F\x20\x00\x20", // pattern 32-bit LE: 0x2000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory XOR Word: temp = M[rs1]; M[rs1] = temp ^ rs2; rd = temp") + ->example("amoxor.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOAND.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x6000202F (funct5=01100, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoand.w", 4, + "\x2F\x20\x00\x60", // pattern 32-bit LE: 0x6000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory AND Word: temp = M[rs1]; M[rs1] = temp & rs2; rd = temp") + ->example("amoand.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOOR.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x4000202F (funct5=01000, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoor.w", 4, + "\x2F\x20\x00\x40", // pattern 32-bit LE: 0x4000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory OR Word: temp = M[rs1]; M[rs1] = temp | rs2; rd = temp") + ->example("amoor.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOMIN.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x8000202F (funct5=10000, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amomin.w", 4, + "\x2F\x20\x00\x80", // pattern 32-bit LE: 0x8000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Minimum Word (signed): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp") + ->example("amomin.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOMAX.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0xA000202F (funct5=10100, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amomax.w", 4, + "\x2F\x20\x00\xA0", // pattern 32-bit LE: 0xA000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Maximum Word (signed): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp") + ->example("amomax.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOMINU.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0xC000202F (funct5=11000, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amominu.w", 4, + "\x2F\x20\x00\xC0", // pattern 32-bit LE: 0xC000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Minimum Word (unsigned): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp") + ->example("amominu.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOMAXU.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0xE000202F (funct5=11100, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amomaxu.w", 4, + "\x2F\x20\x00\xE0", // pattern 32-bit LE: 0xE000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Maximum Word (unsigned): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp") + ->example("amomaxu.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* ZICSR Instructions Extension */ + + /* + * Example: CSRRW rd, csr, rs1 + * + * Encoding: + * csr[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00001073 (funct3=001 + opcode=0x73) + * + * Atomic Read/Write CSR: rd = CSR; CSR = rs1 + */ + insert( + mnem("csrrw", 4, + "\x73\x10\x00\x00", // pattern 32-bit LE: 0x00001073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read/Write: rd = CSR; CSR = rs1") + ->example("csrrw a0, #0x300, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: CSRRS rd, csr, rs1 + * + * Encoding: + * csr[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002073 (funct3=010 + opcode=0x73) + * + * Atomic Read and Set Bits in CSR: rd = CSR; CSR = CSR | rs1 + */ + insert( + mnem("csrrs", 4, + "\x73\x20\x00\x00", // pattern 32-bit LE: 0x00002073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read and Set Bits: rd = CSR; CSR = CSR | rs1") + ->example("csrrs a0, #0x300, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: CSRRC rd, csr, rs1 + * + * Encoding: + * csr[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00003073 (funct3=011 + opcode=0x73) + * + * Atomic Read and Clear Bits in CSR: rd = CSR; CSR = CSR & ~rs1 + */ + insert( + mnem("csrrc", 4, + "\x73\x30\x00\x00", // pattern 32-bit LE: 0x00003073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read and Clear Bits: rd = CSR; CSR = CSR & ~rs1") + ->example("csrrc a0, #0x300, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: CSRRWI rd, csr, uimm5 + * + * Encoding: + * csr[11:0] uimm[4:0] funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00005073 (funct3=101 + opcode=0x73) + * + * Atomic Read/Write CSR Immediate: rd = CSR; CSR = uimm[4:0] + */ + insert( + mnem("csrrwi", 4, + "\x73\x50\x00\x00", // pattern 32-bit LE: 0x00005073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read/Write Immediate: rd = CSR; CSR = uimm[4:0]") + ->example("csrrwi a0, #0x300, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] + + /* + * Example: CSRRSI rd, csr, uimm5 + * + * Encoding: + * csr[11:0] uimm[4:0] funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00006073 (funct3=110 + opcode=0x73) + * + * Atomic Read and Set Bits in CSR Immediate: rd = CSR; CSR = CSR | uimm[4:0] + */ + insert( + mnem("csrrsi", 4, + "\x73\x60\x00\x00", // pattern 32-bit LE: 0x00006073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read and Set Bits Immediate: rd = CSR; CSR = CSR | uimm[4:0]") + ->example("csrrsi a0, #0x300, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] + + /* + * Example: CSRRCI rd, csr, uimm5 + * + * Encoding: + * csr[11:0] uimm[4:0] funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00007073 (funct3=111 + opcode=0x73) + * + * Atomic Read and Clear Bits in CSR Immediate: rd = CSR; CSR = CSR & ~uimm[4:0] + */ + insert( + mnem("csrrci", 4, + "\x73\x70\x00\x00", // pattern 32-bit LE: 0x00007073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read and Clear Bits Immediate: rd = CSR; CSR = CSR & ~uimm[4:0]") + ->example("csrrci a0, #0x300, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] + + /* F Extension Instructions */ + + /* + * Example: FLW rd, imm12(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002007 (funct3=010 + opcode=0x07) + */ + insert( + mnem("flw", 4, + "\x07\x20\x00\x00", // pattern 32-bit LE: 0x00002007 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Floating-Point Load Word: rd = M[rs1 + imm12]") + ->example("flw f0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0]: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FSW rs2, imm12(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002027 (funct3=010 + opcode=0x27) + */ + insert( + mnem("fsw", 4, + "\x27\x20\x00\x00", // pattern 32-bit LE: 0x00002027 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Floating-Point Store Word: M[rs1 + imm12] = rs2") + ->example("fsw f0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x00\x00\xF0\xFE")) // imm[11:0]: split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FMADD.S rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x00000043 (funct2=00, funct3=000 + opcode=0x43) + */ + insert( + mnem("fmadd.s", 4, + "\x43\x00\x00\x00", // pattern 32-bit LE: 0x00000043 + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Fused Multiply-Add: rd = rs1 * rs2 + rs3") + ->example("fmadd.s f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] + + /* + * Example: FMSUB.S rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x00000047 (funct2=00, funct3=000 + opcode=0x47) + */ + insert( + mnem("fmsub.s", 4, + "\x47\x00\x00\x00", // pattern 32-bit LE: 0x00000047 + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Fused Multiply-Subtract: rd = rs1 * rs2 - rs3") + ->example("fmsub.s f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] + + /* + * Example: FNMSUB.S rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x0000004B (funct2=00, funct3=000 + opcode=0x4B) + */ + insert( + mnem("fnmsub.s", 4, + "\x4B\x00\x00\x00", // pattern 32-bit LE: 0x0000004B + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Negative Fused Multiply-Subtract: rd = -(rs1 * rs2) + rs3") + ->example("fnmsub.s f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] + + /* + * Example: FNMADD.S rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x0000004F (funct2=00, funct3=000 + opcode=0x4F) + */ + insert( + mnem("fnmadd.s", 4, + "\x4F\x00\x00\x00", // pattern 32-bit LE: 0x0000004F + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Negative Fused Multiply-Add: rd = -(rs1 * rs2) - rs3") + ->example("fnmadd.s f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] + + /* + * Example: FADD.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00000053 (funct7=0x00, funct3=000 + opcode=0x53) + */ + insert( + mnem("fadd.s", 4, + "\x53\x00\x00\x00", // pattern 32-bit LE: 0x00000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Add: rd = rs1 + rs2") + ->example("fadd.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FSUB.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x08000053 (funct7=0x08, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsub.s", 4, + "\x53\x00\x00\x08", // pattern 32-bit LE: 0x08000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Subtract: rd = rs1 - rs2") + ->example("fsub.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FMUL.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x10000053 (funct7=0x10, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmul.s", 4, + "\x53\x00\x00\x10", // pattern 32-bit LE: 0x10000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Multiply: rd = rs1 * rs2") + ->example("fmul.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FDIV.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x18000053 (funct7=0x18, funct3=000 + opcode=0x53) + */ + insert( + mnem("fdiv.s", 4, + "\x53\x00\x00\x18", // pattern 32-bit LE: 0x18000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Divide: rd = rs1 / rs2") + ->example("fdiv.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FSQRT.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0x58000053 (funct7=0x2C, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsqrt.s", 4, + "\x53\x00\x00\x58", // pattern 32-bit LE: 0x58000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Square Root: rd = sqrt(rs1)") + ->example("fsqrt.s f0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FSGNJ.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x20000053 (funct7=0x20, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsgnj.s", 4, + "\x53\x00\x00\x20", // pattern 32-bit LE: 0x20000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection: rd = {rs2[31], rs1[30:0]}") + ->example("fsgnj.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FSGNJN.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x20001053 (funct7=0x20, funct3=001 + opcode=0x53) + */ + insert( + mnem("fsgnjn.s", 4, + "\x53\x10\x00\x20", // pattern 32-bit LE: 0x20001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection Negative: rd = {~rs2[31], rs1[30:0]}") + ->example("fsgnjn.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FSGNJX.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x20002053 (funct7=0x20, funct3=010 + opcode=0x53) + */ + insert( + mnem("fsgnjx.s", 4, + "\x53\x20\x00\x20", // pattern 32-bit LE: 0x20002053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection XOR: rd = {rs2[31]^rs1[31], rs1[30:0]}") + ->example("fsgnjx.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FMIN.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x28000053 (funct7=0x28, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmin.s", 4, + "\x53\x00\x00\x28", // pattern 32-bit LE: 0x28000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Minimum: rd = min(rs1, rs2)") + ->example("fmin.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FMAX.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x28001053 (funct7=0x28, funct3=001 + opcode=0x53) + */ + insert( + mnem("fmax.s", 4, + "\x53\x10\x00\x28", // pattern 32-bit LE: 0x28001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Maximum: rd = max(rs1, rs2)") + ->example("fmax.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FEQ.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA0002053 (funct7=0x50, funct3=010 + opcode=0x53) + */ + insert( + mnem("feq.s", 4, + "\x53\x20\x00\xA0", // pattern 32-bit LE: 0xA0002053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Equal Compare: rd = (rs1 == rs2) ? 1 : 0") + ->example("feq.s a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FLT.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA0001053 (funct7=0x50, funct3=001 + opcode=0x53) + */ + insert( + mnem("flt.s", 4, + "\x53\x10\x00\xA0", // pattern 32-bit LE: 0xA0001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Less Than Compare: rd = (rs1 < rs2) ? 1 : 0") + ->example("flt.s a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FLE.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA0000053 (funct7=0x50, funct3=000 + opcode=0x53) + */ + insert( + mnem("fle.s", 4, + "\x53\x00\x00\xA0", // pattern 32-bit LE: 0xA0000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Less Than or Equal Compare: rd = (rs1 <= rs2) ? 1 : 0") + ->example("fle.s a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FCVT.W.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xC0000053 (funct7=0x60, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.w.s", 4, + "\x53\x00\x00\xC0", // pattern 32-bit LE: 0xC0000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert to Word: rd = (int32_t)rs1") + ->example("fcvt.w.s a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.WU.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xC0001053 (funct7=0x60, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.wu.s", 4, + "\x53\x10\x00\xC0", // pattern 32-bit LE: 0xC0001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert to Word Unsigned: rd = (uint32_t)rs1") + ->example("fcvt.wu.s a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.S.W rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xD0000053 (funct7=0x68, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.s.w", 4, + "\x53\x00\x00\xD0", // pattern 32-bit LE: 0xD0000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert from Word: rd = (float)rs1") + ->example("fcvt.s.w f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.S.WU rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xD0001053 (funct7=0x68, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.s.wu", 4, + "\x53\x10\x00\xD0", // pattern 32-bit LE: 0xD0001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert from Word Unsigned: rd = (float)(uint32_t)rs1") + ->example("fcvt.s.wu f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FMV.X.W rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xE0000053 (funct7=0x70, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmv.x.w", 4, + "\x53\x00\x00\xE0", // pattern 32-bit LE: 0xE0000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Move to Integer: rd = rs1 (bitwise copy)") + ->example("fmv.x.w a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FMV.W.X rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xF0000053 (funct7=0x78, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmv.w.x", 4, + "\x53\x00\x00\xF0", // pattern 32-bit LE: 0xF0000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Move from Integer: rd = rs1 (bitwise copy)") + ->example("fmv.w.x f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCLASS.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xE0001053 (funct7=0x70, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fclass.s", 4, + "\x53\x10\x00\xE0", // pattern 32-bit LE: 0xE0001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Classify: rd = classification bits for rs1") + ->example("fclass.s a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* D Extension Instructions (Double-Precision Floating-Point) */ + + /* + * Example: FLD rd, imm12(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00003007 (funct3=011 + opcode=0x07) + */ + insert( + mnem("fld", 4, + "\x07\x30\x00\x00", // pattern 32-bit LE: 0x00003007 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Floating-Point Load Double: rd = M[rs1 + imm12]") + ->example("fld f0, (#8, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0]: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FSD rs2, imm12(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00003027 (funct3=011 + opcode=0x27) + */ + insert( + mnem("fsd", 4, + "\x27\x30\x00\x00", // pattern 32-bit LE: 0x00003027 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Floating-Point Store Double: M[rs1 + imm12] = rs2") + ->example("fsd f0, (#8, a1)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x00\x00\xF0\xFE")) // imm[11:0]: split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FMADD.D rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x04000043 (funct2=01, funct3=000 + opcode=0x43) + */ + insert( + mnem("fmadd.d", 4, + "\x43\x00\x00\x04", // pattern 32-bit LE: 0x04000043 + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Fused Multiply-Add Double: rd = rs1 * rs2 + rs3") + ->example("fmadd.d f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] + + /* + * Example: FMSUB.D rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x04000047 (funct2=01, funct3=000 + opcode=0x47) + */ + insert( + mnem("fmsub.d", 4, + "\x47\x00\x00\x04", // pattern 32-bit LE: 0x04000047 + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Fused Multiply-Subtract Double: rd = rs1 * rs2 - rs3") + ->example("fmsub.d f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] + + /* + * Example: FNMSUB.D rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x0400004B (funct2=01, funct3=000 + opcode=0x4B) + */ + insert( + mnem("fnmsub.d", 4, + "\x4B\x00\x00\x04", // pattern 32-bit LE: 0x0400004B + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Negative Fused Multiply-Subtract Double: rd = -(rs1 * rs2) + rs3") + ->example("fnmsub.d f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] + + /* + * Example: FNMADD.D rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x0400004F (funct2=01, funct3=000 + opcode=0x4F) + */ + insert( + mnem("fnmadd.d", 4, + "\x4F\x00\x00\x04", // pattern 32-bit LE: 0x0400004F + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Negative Fused Multiply-Add Double: rd = -(rs1 * rs2) - rs3") + ->example("fnmadd.d f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] + + /* + * Example: FADD.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02000053 (funct7=0x01, funct3=000 + opcode=0x53) + */ + insert( + mnem("fadd.d", 4, + "\x53\x00\x00\x02", // pattern 32-bit LE: 0x02000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Add Double: rd = rs1 + rs2") + ->example("fadd.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FSUB.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x0A000053 (funct7=0x05, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsub.d", 4, + "\x53\x00\x00\x0A", // pattern 32-bit LE: 0x0A000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Subtract Double: rd = rs1 - rs2") + ->example("fsub.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FMUL.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x12000053 (funct7=0x09, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmul.d", 4, + "\x53\x00\x00\x12", // pattern 32-bit LE: 0x12000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Multiply Double: rd = rs1 * rs2") + ->example("fmul.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FDIV.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x1A000053 (funct7=0x0D, funct3=000 + opcode=0x53) + */ + insert( + mnem("fdiv.d", 4, + "\x53\x00\x00\x1A", // pattern 32-bit LE: 0x1A000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Divide Double: rd = rs1 / rs2") + ->example("fdiv.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FSQRT.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0x5A000053 (funct7=0x2D, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsqrt.d", 4, + "\x53\x00\x00\x5A", // pattern 32-bit LE: 0x5A000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Square Root Double: rd = sqrt(rs1)") + ->example("fsqrt.d f0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FSGNJ.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x22000053 (funct7=0x11, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsgnj.d", 4, + "\x53\x00\x00\x22", // pattern 32-bit LE: 0x22000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection Double: rd = {rs2[63], rs1[62:0]}") + ->example("fsgnj.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FSGNJN.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x22001053 (funct7=0x11, funct3=001 + opcode=0x53) + */ + insert( + mnem("fsgnjn.d", 4, + "\x53\x10\x00\x22", // pattern 32-bit LE: 0x22001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection Negative Double: rd = {~rs2[63], rs1[62:0]}") + ->example("fsgnjn.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FSGNJX.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x22002053 (funct7=0x11, funct3=010 + opcode=0x53) + */ + insert( + mnem("fsgnjx.d", 4, + "\x53\x20\x00\x22", // pattern 32-bit LE: 0x22002053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection XOR Double: rd = {rs2[63]^rs1[63], rs1[62:0]}") + ->example("fsgnjx.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FMIN.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x2A000053 (funct7=0x15, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmin.d", 4, + "\x53\x00\x00\x2A", // pattern 32-bit LE: 0x2A000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Minimum Double: rd = min(rs1, rs2)") + ->example("fmin.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FMAX.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x2A001053 (funct7=0x15, funct3=001 + opcode=0x53) + */ + insert( + mnem("fmax.d", 4, + "\x53\x10\x00\x2A", // pattern 32-bit LE: 0x2A001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Maximum Double: rd = max(rs1, rs2)") + ->example("fmax.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FCVT.S.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0x40000053 (funct7=0x20, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.s.d", 4, + "\x53\x00\x00\x40", // pattern 32-bit LE: 0x40000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert Single from Double: rd = (float)rs1") + ->example("fcvt.s.d f0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.D.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0x42000053 (funct7=0x21, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.d.s", 4, + "\x53\x00\x00\x42", // pattern 32-bit LE: 0x42000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert Double from Single: rd = (double)rs1") + ->example("fcvt.d.s f0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FEQ.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA2002053 (funct7=0x51, funct3=010 + opcode=0x53) + */ + insert( + mnem("feq.d", 4, + "\x53\x20\x00\xA2", // pattern 32-bit LE: 0xA2002053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Equal Compare Double: rd = (rs1 == rs2) ? 1 : 0") + ->example("feq.d a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FLT.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA2001053 (funct7=0x51, funct3=001 + opcode=0x53) + */ + insert( + mnem("flt.d", 4, + "\x53\x10\x00\xA2", // pattern 32-bit LE: 0xA2001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Less Than Compare Double: rd = (rs1 < rs2) ? 1 : 0") + ->example("flt.d a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FLE.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA2000053 (funct7=0x51, funct3=000 + opcode=0x53) + */ + insert( + mnem("fle.d", 4, + "\x53\x00\x00\xA2", // pattern 32-bit LE: 0xA2000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Less Than or Equal Compare Double: rd = (rs1 <= rs2) ? 1 : 0") + ->example("fle.d a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FCVT.W.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xC2000053 (funct7=0x61, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.w.d", 4, + "\x53\x00\x00\xC2", // pattern 32-bit LE: 0xC2000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert to Word from Double: rd = (int32_t)rs1") + ->example("fcvt.w.d a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.WU.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xC2001053 (funct7=0x61, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.wu.d", 4, + "\x53\x10\x00\xC2", // pattern 32-bit LE: 0xC2001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert to Word Unsigned from Double: rd = (uint32_t)rs1") + ->example("fcvt.wu.d a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.D.W rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xD2000053 (funct7=0x69, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.d.w", 4, + "\x53\x00\x00\xD2", // pattern 32-bit LE: 0xD2000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert from Word to Double: rd = (double)rs1") + ->example("fcvt.d.w f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.D.WU rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xD2001053 (funct7=0x69, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.d.wu", 4, + "\x53\x10\x00\xD2", // pattern 32-bit LE: 0xD2001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert from Word Unsigned to Double: rd = (double)(uint32_t)rs1") + ->example("fcvt.d.wu f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCLASS.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xE2001053 (funct7=0x71, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fclass.d", 4, + "\x53\x10\x00\xE2", // pattern 32-bit LE: 0xE2001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Classify Double: rd = classification bits for rs1") + ->example("fclass.d a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* C-Extension - Compressed Instructions (16-bit) */ + + // Quadrant 0 (opcode [1:0] = 00) + + /* + * C.ADDI4SPN - Add Immediate to Stack Pointer (4-byte aligned) + * Format: CIW + * Encoding: 000|imm[9:2]|rd'[4:2]|00 + * Opcode: 0x00 (bits [1:0] = 00, bits [15:13] = 000) + */ + insert( + mnem("c.addi4spn", 2, + "\x00\x00", // pattern 16-bit LE: bits [1:0]=00, [15:13]=000 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Add Immediate to SP: rd' = sp + (uimm << 2)") + ->example("c.addi4spn a0, #16") + ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rd': bits [4:2] in byte 0 + ->insert(new GAParameterRiscvCIWimm9("\xE0\x1F")); // imm[9:2]: bits [7:5] in byte 0, bits [4:0] in byte 1 = instruction bits [12:5] + + /* + * C.LW - Compressed Load Word + * Format: CL + * Encoding: 010|imm[5|4:3|8:6]|rs1'[2:0]|imm[2|6]|rd'[2:0]|00 + * Opcode: 0x4000 (bits [1:0] = 00, bits [15:13] = 010) + */ + insert( + mnem("c.lw", 2, + "\x00\x40", // pattern 16-bit LE: bits [1:0]=00, [15:13]=010 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Load Word: rd' = M[rs1' + (uimm << 2)][31:0]") + ->example("c.lw a0, (#4, a1)") + ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rd': bits [4:2] in byte 0 + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvCLimm5("\x60\x1C")) // imm[6:2]: imm[6] in bit 5, imm[2] in bit 6, imm[5:3] in bits [12:10] + ->insert(new GAParameterRiscvCompReg("\x80\x03")); // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + + /* + * C.SW - Compressed Store Word + * Format: CS + * Encoding: 110|imm[5|4:3|8:6]|rs1'[2:0]|imm[2|6]|rs2'[2:0]|00 + * Opcode: 0xC000 (bits [1:0] = 00, bits [15:13] = 110) + */ + insert( + mnem("c.sw", 2, + "\x00\xC0", // pattern 16-bit LE: bits [1:0]=00, [15:13]=110 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Store Word: M[rs1' + (uimm << 2)] = rs2'[31:0]") + ->example("c.sw a0, (#4, a1)") + ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rs2': bits [4:2] in byte 0 + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvCSimm5("\x60\x1C")) // imm[6:2]: imm[6] in bit 5, imm[2] in bit 6, imm[5:3] in bits [12:10] + ->insert(new GAParameterRiscvCompReg("\x80\x03")); // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + + // Quadrant 1 (opcode [1:0] = 01) + + /* + * C.NOP - Compressed No Operation / C.ADDI + * Format: CI + * Encoding: 000|imm[5:0]|rd[4:0]|01 + * Opcode: 0x0001 (bits [1:0] = 01, bits [15:13] = 000, rd=0 for NOP) + * Note: Inserted before c.addi so it's checked first (more specific pattern with rd=0) + */ + insert( + mnem("c.nop", 2, + "\x01\x00", // pattern 16-bit LE: bits [1:0]=01, [15:13]=000, rd=0 + "\x83\xEF")) // mask: opcode + rd (byte0: bits [7] and [1:0]=0x83, byte1: bits [15:13] and [11:8]=0xEF) + ->help("Compressed No Operation") + ->example("c.nop"); + + /* + * C.ADDI - Compressed Add Immediate + * Format: CI + * Encoding: 000|imm[5:0]|rd[4:0]|01 + * Opcode: 0x0001 (bits [1:0] = 01, bits [15:13] = 000, rd != 0) + * Note: Uses rejectWhenZero to check rd != 0, eliminating collision with c.nop + */ + insert( + mnem("c.addi", 2, + "\x01\x00", // pattern 16-bit LE: bits [1:0]=01, [15:13]=000 + "\x03\xE0")) // mask: opcode bits only + ->rejectWhenZero("\x80\x0F") // rd (bits [11:7]) must be non-zero + ->help("Compressed Add Immediate: rd = rd + imm") + ->example("c.addi a0, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.LI - Compressed Load Immediate + * Format: CI + * Encoding: 010|imm[5:0]|rd[4:0]|01 + * Opcode: 0x4001 (bits [1:0] = 01, bits [15:13] = 010) + */ + insert( + mnem("c.li", 2, + "\x01\x40", // pattern 16-bit LE: bits [1:0]=01, [15:13]=010 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Load Immediate: rd = imm (rd != 0, rd != 2)") + ->example("c.li a0, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.ADDI16SP - Compressed Add Immediate to SP (16-byte aligned) + * Format: CI + * Encoding: 011|imm[9|4|6|8:7|5]|01010|01 + * Opcode: 0x6101 (bits [1:0] = 01, bits [15:13] = 011, rd = 2 (sp)) + * Note: Pattern includes rd=2 (bits [11:7]=00010) to distinguish from c.lui + * rd[4:1]=0001 in bits [11:8], rd[0]=0 in bit [7] + * Inserted before c.lui so it's checked first (more specific pattern) + */ + insert( + mnem("c.addi16sp", 2, + "\x01\x61", // pattern 16-bit LE: bits [1:0]=01, [15:13]=011, rd=2 (bits [11:8]=0001, bit [7]=0) + "\x83\xEF")) // mask: opcode + rd (byte0: bits [7] and [1:0]=0x83, byte1: bits [15:13] and [11:8]=0xEF) + ->help("Compressed Add Immediate to SP: sp = sp + (imm << 4)") + ->example("c.addi16sp #-32") + ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[9|4|6|8:7|5]: split encoding (special format) - same mask as CI but different encoding logic + + /* + * C.LUI - Compressed Load Upper Immediate + * Format: CI + * Encoding: 011|imm[17:12]|rd[4:0]|01 + * Opcode: 0x6001 (bits [1:0] = 01, bits [15:13] = 011, rd != 0, rd != 2) + * Note: Inserted after c.addi16sp so c.addi16sp (more specific) is checked first + */ + insert( + mnem("c.lui", 2, + "\x01\x60", // pattern 16-bit LE: bits [1:0]=01, [15:13]=011 (rd != 0 and != 2 is checked in parameter decode to distinguish from c.addi16sp) + "\x03\xE0")) // mask: opcode only (rd != 0 and != 2 is checked in parameter decode to distinguish from c.addi16sp) + ->help("Compressed Load Upper Immediate: rd = (imm << 12)") + ->example("c.lui a0, #0x10000") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 (must be != 0 and != 2) + ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[17:12]: encoded in imm[5:0] position - same mask as CI but represents imm[17:12] + + /* + * C.SRAI - Compressed Shift Right Arithmetic Immediate + * Format: CB + * Encoding: 100|imm[5:0]|rd'[2:0]|01 + * Opcode: 0x8401 (bits [1:0] = 01, bits [15:13] = 100, bits [11:10] = 01) + * Note: C.SRAI is in quadrant 01, distinct from C.MV which is in quadrant 10 + */ + { + auto m = mnem("c.srai", 2, + "\x01\x84", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=01 (only fixed opcode bits) + "\x03\xEC"); // mask: bits [1:0] + [15:13] + [11:10] = 0x03 in byte 0, 0xEC in byte 1 (exclude bit [6] and [12] - they're data!) + m->help("Compressed Shift Right Arithmetic Immediate: rd' = rd' >> uimm (arithmetic)"); + m->example("c.srai a0, #3"); + m->insert(new GAParameterRiscvCompReg("\x80\x03")); // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + m->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 + insert(m); + } + + // Quadrant 2 (opcode [1:0] = 10) + + /* + * C.EBREAK - Compressed Environment Break + * Format: CR + * Encoding: 100|00000|00000|10 + * Opcode: 0x9002 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 001, rd=0, rs1=0) + * Note: Inserted first to ensure it's checked first (has most specific mask 0xFFFF) + */ + insert( + mnem("c.ebreak", 2, + "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=001, rd=0, rs1=0 + "\xFF\xFF")) // mask: all bits (0xFFFF) - c.ebreak is an exact encoding with rd=0, rs2=0 + // Removed priority - full mask 0xFFFF ensures c.ebreak matches only its exact encoding 0x9002 + ->help("Compressed Environment Break"); + + /* + * C.ANDI - Compressed AND Immediate + * Format: CB + * Encoding: 100|imm[5]|10|rd'[2:0]|imm[4:0]|01 + * Opcode: 0x8801 (bits [1:0] = 01, bits [15:13] = 100, bits [11:10] = 10) + * Note: bits [12] and [6:2] are part of immediate data, so they are NOT in the mask + */ + // Using standard mnemonic - c.andi is in quadrant 01 (bits[1:0]=01), + // distinct from c.jr/c.jalr which are in quadrant 10 (bits[1:0]=10) + // The mask already distinguishes them by checking bits[1:0] and bits[11:10]=10 + insert( + mnem("c.andi", 2, + "\x01\x88", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=10 + "\x03\xEC")) // mask: bits [1:0] in byte 0, bits [15:13] + [11:10] in byte 1 + ->help("Compressed AND Immediate: rd' = rd' & imm") + ->example("c.andi a0, #7") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCBimm6Andi("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.SRLI - Compressed Shift Right Logical Immediate + * Format: CB + * Encoding: 100|imm[5]|00|rd'[2:0]|imm[4:0]|01 + * Opcode: bits [1:0] = 01 (quadrant 1), bits [15:13] = 100, bits [11:10] = 00 + * Note: bit [12] is imm[5], bits [6:2] are imm[4:0] (parameters) + * Pattern: 0x8001 (bits [1:0]=01, [15:13]=100, [11:10]=00) + */ + // Using standard mnemonic - c.srli is in quadrant 01 (bits[1:0]=01), + // distinct from c.jr/c.jalr/c.mv which are in quadrant 10 (bits[1:0]=10) + // The mask checks bits[11:10]=00 to distinguish from c.srai (01) and c.andi (10) + insert( + mnem("c.srli", 2, + "\x01\x80", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=00 + "\x03\xEC")) // mask: bits [1:0] in byte 0, bits [15:13] + [11:10] in byte 1 + ->help("Compressed Shift Right Logical Immediate: rd' = rd' >> uimm") + ->example("c.srli a0, #3") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.JR - Compressed Jump Register + * Format: CR + * Encoding: 100|rs1[4:0]|00000|10 + * Opcode: bits [15:13] = 100, bits [12:10] = 000, bits [6:2] = 00000 (rd=0), bits [1:0] = 10 + * Note: [11:10] are part of rs1 register field, not opcode bits, so mask doesn't check them + * Note: rs1 must be non-zero (rs1=0 with rd=0 is reserved) + */ + insert( + mnem("c.jr", 2, + "\x02\x80", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12]=0 (funct4), [6:2]=00000 (rs2=0) + "\x7F\xF0")) // mask: bits [1:0] + [6:2] in byte 0 (0x7F), bits [15:12] in byte 1 (0xF0) + ->rejectWhenZero("\x80\x0F") // rs1 (bits [11:7]) must be non-zero + ->help("Compressed Jump Register: pc = rs1") + ->example("c.jr a0") + ->insert(new GAParameterRiscvReg("\x80\x0F")); // rs1: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + + /* + * C.JALR - Compressed Jump and Link Register + * Format: CR + * Encoding: 1001|rs1[4:0]|00000|10 + * Opcode: bits [15:12] = 1001 (funct4), bits [6:2] = 00000 (rs2=0), bits [1:0] = 10 + * Note: rd is implicitly ra (x1), rs1 must be non-zero (rs1=0 with rs2=0 is c.ebreak) + */ + insert( + mnem("c.jalr", 2, + "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1001 (funct4), [6:2]=00000 (rs2=0) + "\x7F\xF0")) // mask: bits [6:0] in byte 0 (check rs2=0, op=10), bits [15:12] in byte 1 (check funct4) + ->rejectWhenZero("\x80\x0F") // rs1 (bits [11:7]) must be non-zero + ->help("Compressed Jump and Link Register: ra = pc + 2; pc = rs1") + ->example("c.jalr a0") + ->insert(new GAParameterRiscvReg("\x80\x0F")); // rs1: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + + /* + * C.SUB - Compressed Subtract + * Format: CA + * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|00|10 + * Opcode: 0x8C02 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 00) + */ + insert( + mnem("c.sub", 2, + "\x02\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=00 + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + // Removed priority - mask correctly checks [6:5]=00 to distinguish from other CA format instructions + ->help("Compressed Subtract: rd' = rd' - rs2'") + ->example("c.sub a0, a1") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 + + /* + * C.XOR - Compressed XOR + * Format: CA + * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|01|10 + * Opcode: 0x8C22 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 01) + */ + insert( + mnem("c.xor", 2, + "\x22\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=01 + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + // Removed priority - mask correctly checks [6:5]=01 to distinguish from other CA format instructions + ->help("Compressed XOR: rd' = rd' ^ rs2'") + ->example("c.xor a0, a1") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 + + /* + * C.OR - Compressed OR + * Format: CA + * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|10|10 + * Opcode: 0x8C42 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 10) + */ + insert( + mnem("c.or", 2, + "\x42\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=10 + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + // Removed priority - mask correctly checks [6:5]=10 to distinguish from other CA format instructions + ->help("Compressed OR: rd' = rd' | rs2'") + ->example("c.or a0, a1") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 + + /* + * C.AND - Compressed AND + * Format: CA + * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|11|10 + * Opcode: 0x8C62 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 11) + */ + insert( + mnem("c.and", 2, + "\x62\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=11 + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + // Removed priority - mask correctly checks [6:5]=11 to distinguish from other CA format instructions + ->help("Compressed AND: rd' = rd' & rs2'") + ->example("c.and a0, a1") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 + + /* + * C.J - Compressed Jump + * Format: CJ + * Encoding: 101|imm[11|4|9:8|10|6|7|3:1|5]|01 + * Opcode: 0xA001 (bits [1:0] = 01, bits [15:13] = 101) + */ + insert( + mnem("c.j", 2, + "\x01\xA0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=101 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Jump: pc = pc + imm") + ->example("c.j #8") + ->insert(new GAParameterRiscvCJimm12("\xFC\x1F")); // imm[11:1]: split encoding - bits [7:2] from byte 0, bits [12:8] from byte 1 + + /* + * C.BEQZ - Compressed Branch if Equal to Zero + * Format: CB + * Encoding: 110|imm[8|4:3|7:6|2:1|5]|rs1'[2:0]|01 + * Opcode: 0xC001 (bits [1:0] = 01, bits [15:13] = 110) + * Note: bits [9:7] contain rs1' (compressed register), not regular rs2 + * Note: Distinguished from c.swsp by op field: c.beqz has [1:0]=01, c.swsp has [1:0]=10 + */ + insert( + mnem("c.beqz", 2, + "\x01\xC0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=110 + "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 + ->help("Compressed Branch if Equal to Zero: if (rs1' == 0) pc = pc + imm") + ->example("c.beqz a0, #8") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCBimm9("\x7C\x1C")); // imm[8:1]: split encoding - bits [6:2] from byte 0, bits [12] and [11:10] from byte 1 + + /* + * C.BNEZ - Compressed Branch if Not Equal to Zero + * Format: CB + * Encoding: 111|imm[8|4:3|7:6|2:1|5]|rs1'[2:0]|01 + * Opcode: 0xE001 (bits [1:0] = 01, bits [15:13] = 111) + */ + insert( + mnem("c.bnez", 2, + "\x01\xE0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=111 + "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 + ->help("Compressed Branch if Not Equal to Zero: if (rs1' != 0) pc = pc + imm") + ->example("c.bnez a0, #8") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCBimm9("\x7C\x1C")); // imm[8:1]: split encoding - bits [6:2] from byte 0, bits [12] and [11:10] from byte 1 + + // Quadrant 2 special instructions (rd != 0) + + /* + * C.SLLI - Compressed Shift Left Logical Immediate + * Format: CI + * Encoding: 000|imm[5:0]|rd[4:0]|10 + * Opcode: 0x0002 (bits [1:0] = 10, bits [15:13] = 000, rd != 0) + */ + insert( + mnem("c.slli", 2, + "\x02\x00", // pattern 16-bit LE: bits [1:0]=10, [15:13]=000 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Shift Left Logical Immediate: rd = rd << uimm") + ->example("c.slli a0, #3") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.LWSP - Compressed Load Word from Stack Pointer + * Format: CI + * Encoding: 010|imm[7:2]|rd[4:0]|10 + * Opcode: 0x4002 (bits [1:0] = 10, bits [15:13] = 010, rd != 0) + */ + insert( + mnem("c.lwsp", 2, + "\x02\x40", // pattern 16-bit LE: bits [1:0]=10, [15:13]=010 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Load Word from SP: rd = M[sp + (uimm << 2)][31:0]") + ->example("c.lwsp a0, #4") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvCIimm7("\x7C\x10")); // imm[7:2]: imm[5] in bit [12], imm[4:2] in bits [6:4], imm[7:6] in bits [3:2] + + /* + * C.MV - Compressed Move + * Format: CR + * Encoding: 1000|rs2[4:0]|rd[4:0]|10 + * Opcode: funct4 = 1000, so bits [15:12] = 1000, bits [1:0] = 10 + * Note: bit [12] = 0 distinguishes from c.add (funct4 = 1001, bit [12] = 1) + * Note: C.MV is in quadrant 10, distinct from C.SRAI which is in quadrant 01 + * Note: both rd != 0 and rs2 != 0 required (rs2=0 would be c.jr, rd=0 invalid) + */ + insert( + mnem("c.mv", 2, + "\x02\x80", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1000 (funct4) + "\x03\xF0")) // mask: bits [1:0] + [15:12] = 0x03 in byte 0, 0xF0 in byte 1 + ->rejectWhenZero("\x80\x0F") // rd (bits [11:7]) must be non-zero + ->rejectWhenZero("\x7C\x00") // rs2 (bits [6:2]) must be non-zero + ->help("Compressed Move: rd = rs2") + ->example("c.mv a0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvReg("\x7C\x00")); // rs2: bits [6:2] - bits [6:2] in byte 0 + + /* + * C.ADD - Compressed Add + * Format: CR + * Encoding: 100|rs2[4:0]/rs1[4:0]|rd[4:0]|10 + * Opcode: 0x9002 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 000, rd != 0, rd != 1) + */ + insert( + mnem("c.add", 2, + "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1001 (funct4), rd=0 (template) + "\x03\xF0")) // mask: bits [1:0] + [15:12] = 0x03 in byte 0, 0xF0 in byte 1 (don't check rd or rs2) + // Removed priority - c.ebreak (inserted before this) has more specific mask (0x03FF) and will match first + ->help("Compressed Add: rd = rd + rs2") + ->example("c.add a0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvReg("\x7C\x00")); // rs2: bits [6:2] - bits [6:2] in byte 0 + + /* + * C.SWSP - Compressed Store Word to Stack Pointer + * Format: CSS + * Encoding: 110|imm[7:2]|rs2[4:0]|10 + * Opcode: 0xC002 (bits [1:0] = 10, bits [15:13] = 110) + * Note: bits [6:2] contain regular rs2 register, not compressed rs1' + * Note: Distinguished from c.beqz by op field: c.swsp has [1:0]=10, c.beqz has [1:0]=01 + */ + insert( + mnem("c.swsp", 2, + "\x02\xC0", // pattern 16-bit LE: bits [1:0]=10, [15:13]=110 + "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 + ->help("Compressed Store Word to SP: M[sp + (uimm << 2)] = rs2[31:0]") + ->example("c.swsp a0, #4") + ->insert(new GAParameterRiscvReg("\x7C\x00")) // rs2: bits [6:2] - bits [6:2] in byte 0 + ->insert(new GAParameterRiscvCSSimm7("\x80\x1F")); // imm[7:2]: bits [12:7] - bit [7] from byte 0, bits [12:8] from byte 1 +} + +/* RISC-V Parameter Types */ + +// RISC-V Reg Parameter + +GAParameterRiscvReg::GAParameterRiscvReg(const char* mask){ + setMask(mask); +} + +int GAParameterRiscvReg::match(GAParserOperand *op, int len){ + if(op->prefix!=this->prefix) + return 0; + + // Check if it is a valid RISC-V register name. + QString name = op->value; + if(name == "zero" || name == "ra" || name == "sp" || name == "gp" || name == "tp" || + name == "t0" || name == "t1" || name == "t2" || + name == "s0" || name == "s1" || + name == "a0" || name == "a1" || name == "a2" || name == "a3" || + name == "a4" || name == "a5" || name == "a6" || name == "a7" || + name == "s2" || name == "s3" || name == "s4" || name == "s5" || + name == "s6" || name == "s7" || name == "s8" || name == "s9" || + name == "s10" || name == "s11" || + name == "t3" || name == "t4" || name == "t5" || name == "t6" || + // Floating point registers f0-f31 + name == "f0" || name == "f1" || name == "f2" || name == "f3" || + name == "f4" || name == "f5" || name == "f6" || name == "f7" || + name == "f8" || name == "f9" || name == "f10" || name == "f11" || + name == "f12" || name == "f13" || name == "f14" || name == "f15" || + name == "f16" || name == "f17" || name == "f18" || name == "f19" || + name == "f20" || name == "f21" || name == "f22" || name == "f23" || + name == "f24" || name == "f25" || name == "f26" || name == "f27" || + name == "f28" || name == "f29" || name == "f30" || name == "f31") { + return 1; + } + return 0; +} + +QString GAParameterRiscvReg::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t regnum = rawdecode(lang, adr, bytes, inslen); + // Clamp register number to valid range (0-31 for both integer and floating point) + if(regnum > 31) { + return QString::asprintf("r%llu", (unsigned long long) regnum); + } + + // Check if this is a C-Extension instruction (16-bit, mask "\x80\x0F" for bits [11:7]) + // For 16-bit instructions, mask is 2 bytes; for 32-bit, it's 4 bytes + bool isCExtension = (inslen == 2 && (unsigned char)mask[0] == 0x80 && (unsigned char)mask[1] == 0x0F); + + // Determine which register field this is by checking the mask + // For 32-bit instructions: + // RD: bits [11:7] - mask "\x80\x0F\x00\x00" + // RS1: bits [19:15] - mask "\x00\x80\x0F\x00" + // RS2: bits [24:20] - mask "\x00\x00\xF0\x01" or "\x00\x00\xF0\x1F" + // RS3: bits [31:27] - mask "\x00\x00\x00\xF8" + // For 16-bit C-Extension: + // RD/RS1/RS2: bits [11:7] - mask "\x80\x0F" + bool isRD = false; + bool isRS1 = false; + bool isRS2 = false; + bool isRS3 = false; + + if(isCExtension) { + // For C-Extension, bits [11:7] can be RD, RS1, or RS2 depending on instruction + // We can't determine from mask alone, so assume it's RD (most common) + isRD = true; + } else { + isRD = ((unsigned char)mask[0] == 0x80 && (unsigned char)mask[1] == 0x0F && (unsigned char)mask[2] == 0x00 && (unsigned char)mask[3] == 0x00); + isRS1 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x80 && (unsigned char)mask[2] == 0x0F && (unsigned char)mask[3] == 0x00); + isRS2 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x00 && ((unsigned char)mask[2] == 0xF0) && ((unsigned char)mask[3] == 0x01 || (unsigned char)mask[3] == 0x1F)); + isRS3 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x00 && (unsigned char)mask[2] == 0x00 && (unsigned char)mask[3] == 0xF8); + } + + // Check instruction encoding to determine register type for F extension instructions + bool useFPReg = false; + if(inslen >= 4) { + uint8_t opcode = bytes[0] & 0x7F; // Opcode is in bits [6:0] of first byte + + if(opcode == 0x07 || opcode == 0x27) { + // FLW, FSW: rd/rs2 are FP, rs1 is integer (base address) + useFPReg = (isRD || isRS2); + } else if(opcode == 0x43 || opcode == 0x47 || opcode == 0x4B || opcode == 0x4F) { + // FMADD/FMSUB/FNMSUB/FNMADD: all registers are FP + useFPReg = true; + } else if(opcode == 0x53) { + // F extension arithmetic/comparison/conversion instructions + // Extract funct7 from byte 3 (bits [31:25] = byte 3 bits [7:1]) + // funct7 is 7 bits, so we shift right by 1 and mask with 0x7F + uint8_t funct7 = (bytes[3] >> 1) & 0x7F; + uint8_t funct3 = (bytes[1] >> 4) & 0x07; // funct3 is in bits [14:12] = byte 1 bits [6:4] + + if(funct7 == 0x60) { // fcvt.w.s, fcvt.wu.s + useFPReg = isRS1; // rs1 is FP, rd is integer + } else if(funct7 == 0x68) { // fcvt.s.w, fcvt.s.wu + useFPReg = isRD; // rd is FP, rs1 is integer + } else if(funct7 == 0x70) { // fmv.x.w, fclass.s + useFPReg = isRS1; // rs1 is FP, rd is integer + } else if(funct7 == 0x78) { // fmv.w.x + useFPReg = isRD; // rd is FP, rs1 is integer + } else if(funct7 == 0x50) { // feq.s, flt.s, fle.s + useFPReg = (isRS1 || isRS2); // rs1 and rs2 are FP, rd is integer + } else if(funct7 == 0x51) { // feq.d, flt.d, fle.d + useFPReg = (isRS1 || isRS2); // rs1 and rs2 are FP, rd is integer + } else if(funct7 == 0x61) { // fcvt.w.d, fcvt.wu.d + useFPReg = isRS1; // rs1 is FP, rd is integer + } else if(funct7 == 0x69) { // fcvt.d.w, fcvt.d.wu + useFPReg = isRD; // rd is FP, rs1 is integer + } else if(funct7 == 0x71) { // fclass.d + useFPReg = isRS1; // rs1 is FP, rd is integer + } else { + // All other F/D extension instructions: all registers are FP + useFPReg = true; + } + } + } + + // Use the determined register type + if(useFPReg && regnum + 32 < lang->regnames.size()) { + QString fpname = lang->regnames[regnum + 32]; + if(fpname.startsWith("f")) { + return fpname; + } + } + + // Prefer integer registers for non-FP or when useFPReg is false + if(regnum < 32 && regnum < lang->regnames.size()) { + QString intname = lang->regnames[regnum]; + // If it's not a floating point register name, use it + if(!intname.startsWith("f")) { + return intname; + } + } + + // Fallback to floating point register if integer register wasn't found + if(regnum + 32 < lang->regnames.size()) { + QString fpname = lang->regnames[regnum + 32]; + if(fpname.startsWith("f")) { + return fpname; + } + } + + // Final fallback + if(regnum < lang->regnames.size()) { + return lang->regnames[regnum]; + } + return QString::asprintf("r%llu", (unsigned long long) regnum); +} + +void GAParameterRiscvReg::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int regnum = lang->regnames.indexOf(op.value); + if(regnum == -1) { + op.goodasm->error("Unknown RISC-V register: " + op.value); + return; + } + // Floating point registers f0-f31 are at indices 32-63, but encode as 0-31 + if(regnum >= 32 && regnum < 64) { + regnum -= 32; + } + rawencode(lang, adr, bytes, op, inslen, regnum); +} + +// RISC-V Imm12 (imm[11:0]) parameter + +GAParameterRiscvImm12::GAParameterRiscvImm12(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvImm12::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); //False on a match, int64 handles negative prefix. + + // must fit signed 12-bit immediate + if (val < -2048 || val > 2047) { + op->goodasm->error("RISC-V imm12 is out of range (-2048 to 2047)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvImm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + int32_t val = (raw & 0x800) ? (raw | ~0xFFF) : (raw & 0xFFF); + // Format as hex if value is >= 0x10 or negative, otherwise decimal + if (val < 0 || (uint32_t)val >= 0x10) { + return prefix + QString::asprintf("0x%x", (uint32_t)val); + } + return prefix + QString::number(val); +} + +void GAParameterRiscvImm12::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -2048 || val > 2047) { + op.goodasm->error("RISC-V imm12 is out of range (-2048 to 2047)."); + return; + } + + rawencode(lang,adr,bytes,op,inslen,val); +} + +// RISC-V U-type Imm20 (imm[31:12]) parameter + +GAParameterRiscvUtypeImm20::GAParameterRiscvUtypeImm20(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvUtypeImm20::match(GAParserOperand *op, int len){ + // Try parsing as unsigned first, then signed if that fails + uint64_t val=op->uint64(false); // False on a match + + // If uint64 parsing failed, try int64 (for negative values, though U-type shouldn't have them) + if (val == (uint64_t)-1) { + int64_t sval = op->int64(false); + if (sval == -1) { + return 0; // Parsing failed, let other parameter types try + } + // If negative, reject (U-type immediates are unsigned) + if (sval < 0) { + return 0; + } + val = (uint64_t)sval; + } + + // U-type immediate: the value is the result value (what should be in rd) + // Must be <= 0xFFFFF000 and a multiple of 0x1000 (lower 12 bits must be zero) + + // Check if value is out of range + if (val > 0xFFFFF000) { + op->goodasm->error("RISC-V U-type instruction imm20 is out of range (0 to 0xFFFFF000, must be multiple of 0x1000)"); + return 0; + } + + // Check if value is a multiple of 0x1000 + if ((val & 0xFFF) != 0) { + op->goodasm->error("RISC-V U-type instruction imm20 must be a multiple of 0x1000 (lower 12 bits must be zero)"); + return 0; + } + + return 1; // valid value +} + +QString GAParameterRiscvUtypeImm20::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode extracts bits [31:12] which is the immediate field + // lui sets rd = imm[31:12] << 12, so we need to left-shift to show the result value + uint32_t imm_field = raw & 0xFFFFF; + uint64_t result = ((uint64_t)imm_field) << 12; + return prefix + QString::asprintf("0x%llx", (unsigned long long)result); +} + +void GAParameterRiscvUtypeImm20::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + uint32_t imm_field; + + // lui/auipc: rd = imm[31:12] << 12 + // The immediate value provided is the result value (what should be in rd) + // Extract the immediate field: imm[31:12] = val >> 12 + + // Check if value is out of range (max 32-bit value with lower 12 bits zero) + if (val > 0xFFFFF000) { + op.goodasm->error("RISC-V U-type imm20 is out of range (0 to 0xFFFFF000, must be multiple of 0x1000)."); + return; + } + + // Check if value is a multiple of 0x1000 (lower 12 bits must be zero) + if ((val & 0xFFF) != 0) { + op.goodasm->error("RISC-V U-type imm20 must be a multiple of 0x1000 (lower 12 bits must be zero)."); + return; + } + + // Right-shift by 12 to get the immediate field value that goes in bits [31:12] + imm_field = (val >> 12) & 0xFFFFF; + + rawencode(lang,adr,bytes,op,inslen,imm_field); +} + +// RISC-V B-type Imm13 (imm[12:1]) parameter +// Encoding: imm[12] in bit [31], imm[11] in bit [7], imm[10:5] in bits [30:25], imm[4:1] in bits [11:8] +// Mask: "\x80\x8F\xF0\xBF" - combined from: imm[12] (0x80 in byte 3), imm[11] (0x80 in byte 1), imm[10:5] (0xF0 in byte 2, 0x3F in byte 3), imm[4:1] (0x0F in byte 1) + +GAParameterRiscvBtypeImm13::GAParameterRiscvBtypeImm13(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvBtypeImm13::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); // False on a match + + // must fit signed 13-bit immediate, and must be even (imm[0] = 0) + if (val < -4096 || val > 4094) { + op->goodasm->error("RISC-V B-type imm13 is out of range (-4096 to 4094)"); + return 0; + } + if ((val & 1) != 0) { + op->goodasm->error("RISC-V B-type imm13 must be even (target address must be 2-byte aligned)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvBtypeImm13::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode packs bits in mask order: bit7(imm[11]), bits8-11(imm[4:1]), bits25-30(imm[10:5]), bit31(imm[12]) + int32_t imm11 = raw & 1; + int32_t imm4_1 = (raw >> 1) & 0xF; + int32_t imm10_5 = (raw >> 5) & 0x3F; + int32_t imm12 = (raw >> 11) & 1; + int32_t imm = (imm12 << 12) | (imm11 << 11) | (imm10_5 << 5) | (imm4_1 << 1); + // Sign extend from 13 bits + if (imm & 0x1000) { + imm |= ~0x1FFF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvBtypeImm13::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -4096 || val > 4094) { + op.goodasm->error("RISC-V B-type imm13 is out of range (-4096 to 4094)."); + return; + } + if ((val & 1) != 0) { + op.goodasm->error("RISC-V B-type imm13 must be even (target address must be 2-byte aligned)."); + return; + } + + // Pack imm[12:1] in mask order: imm[11], imm[4:1], imm[10:5], imm[12] + uint32_t imm = val & 0x1FFE; + uint32_t raw = ((imm >> 11) & 1) | + ((imm >> 1) & 0xF) << 1 | + ((imm >> 5) & 0x3F) << 5 | + ((imm >> 12) & 1) << 11; + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V J-type Imm21 (imm[20:1]) parameter +// Encoding: imm[20] in bit [31], imm[19:12] in bits [19:12], imm[11] in bit [20], imm[10:1] in bits [30:21] +// Mask: "\x00\xFF\x10\xFF" - combined from: imm[20] (0x80 in byte 3), imm[19:12] (0xFF in byte 1), imm[11] (0x10 in byte 2), imm[10:1] (0x7F in byte 3) + +GAParameterRiscvJtypeImm21::GAParameterRiscvJtypeImm21(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvJtypeImm21::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); // False on a match + + // must fit signed 21-bit immediate, and must be even (imm[0] = 0) + if (val < -1048576 || val > 1048574) { + op->goodasm->error("RISC-V J-type imm21 is out of range (-1048576 to 1048574)"); + return 0; + } + if ((val & 1) != 0) { + op->goodasm->error("RISC-V J-type imm21 must be even (target address must be 2-byte aligned)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvJtypeImm21::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Reconstruct imm[20:1] from mask-ordered bits + // Mask "\x00\xF0\xFF\xFF" extracts bits in this order: + // raw[3:0] = inst[15:12] = imm[19:16] + // raw[7:4] = inst[19:16] = imm[15:12] + // raw[8] = inst[20] = imm[11] + // raw[11:9] = inst[23:21] = imm[10:8] + // raw[18:12] = inst[30:24] = imm[7:1] + // raw[19] = inst[31] = imm[20] + int32_t imm20 = (raw >> 19) & 1; + int32_t imm19_16 = raw & 0xF; + int32_t imm15_12 = (raw >> 4) & 0xF; + int32_t imm11 = (raw >> 8) & 1; + int32_t imm10_8 = (raw >> 9) & 0x7; + int32_t imm7_1 = (raw >> 12) & 0x7F; + int32_t imm = (imm20 << 20) | (imm19_16 << 16) | (imm15_12 << 12) | (imm11 << 11) | (imm10_8 << 8) | (imm7_1 << 1); + // Sign extend from 21 bits + if (imm & 0x100000) { + imm |= ~0x1FFFFF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvJtypeImm21::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -1048576 || val > 1048574) { + op.goodasm->error("RISC-V J-type imm21 is out of range (-1048576 to 1048574)."); + return; + } + if ((val & 1) != 0) { + op.goodasm->error("RISC-V J-type imm21 must be even (target address must be 2-byte aligned)."); + return; + } + + // Pack imm[20:1] into mask order + // raw[3:0] = imm[19:16] + // raw[7:4] = imm[15:12] + // raw[8] = imm[11] + // raw[11:9] = imm[10:8] + // raw[18:12] = imm[7:1] + // raw[19] = imm[20] + uint32_t imm = val & 0x1FFFFE; // imm[20:1], clear imm[0] + uint32_t raw = (((imm >> 20) & 1) << 19) | // imm[20] -> raw[19] + (((imm >> 1) & 0x7F) << 12) | // imm[7:1] -> raw[18:12] + (((imm >> 8) & 0x7) << 9) | // imm[10:8] -> raw[11:9] + (((imm >> 11) & 1) << 8) | // imm[11] -> raw[8] + (((imm >> 12) & 0xF) << 4) | // imm[15:12] -> raw[7:4] + ((imm >> 16) & 0xF); // imm[19:16] -> raw[3:0] + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V S-type Imm12 (imm[11:0]) parameter +// Encoding: imm[11:5] in bits [31:25], imm[4:0] in bits [11:7] +// Mask: "\x80\x0F\x00\xFE" - imm[4:0] in bits [11:7] (byte 0 bit 7 + byte 1 bits 0-3), imm[11:5] in bits [31:25] (byte 3 bits 1-7) + +GAParameterRiscvStypeImm12::GAParameterRiscvStypeImm12(const char* mask){ + setMask(mask); + prefix = "#"; + isSigned = true; // 12-bit signed immediate +} + +int GAParameterRiscvStypeImm12::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); // False on a match + + // must fit signed 12-bit immediate + if (val < -2048 || val > 2047) { + op->goodasm->error("RISC-V S-type imm12 is out of range (-2048 to 2047)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvStypeImm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode already extracts and packs imm[11:0] from the split encoding via the mask + int32_t imm = raw & 0xFFF; + // Sign extend from 12 bits + if (imm & 0x800) { + imm |= ~0xFFF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvStypeImm12::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -2048 || val > 2047) { + op.goodasm->error("RISC-V S-type imm12 is out of range (-2048 to 2047)."); + return; + } + + // rawencode expects the immediate value directly (in mask bit order, not instruction bit positions) + // The mask will distribute the bits to the correct instruction positions + uint32_t imm = val & 0xFFF; // imm[11:0] - mask to 12 bits + rawencode(lang, adr, bytes, op, inslen, imm); +} + +// RISC-V FENCE pred/succ parameter +// Encoding: pred[3:0] in imm[3:0] (bits [23:20], byte 2 bits [7:4]) +// succ[3:0] in imm[7:4] (bits [27:24], byte 3 bits [3:0]) +// Mask: "\x00\x00\xF0\x0F" - pred in byte 2 bits [7:4], succ in byte 3 bits [3:0] + +GAParameterRiscvFencePredSucc::GAParameterRiscvFencePredSucc(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvFencePredSucc::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit 8-bit value (0-255) where lower 4 bits are pred and upper 4 bits are succ + if (val < 0 || val > 255) { + op->goodasm->error("RISC-V FENCE pred/succ is out of range (0 to 255)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvFencePredSucc::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + // Extract pred[3:0] from imm[3:0] (bits [23:20], byte 2 bits [7:4]) + // Extract succ[3:0] from imm[7:4] (bits [27:24], byte 3 bits [3:0]) + // For little-endian: byte 2 is bytes[2], byte 3 is bytes[3] + uint32_t pred = (bytes[2] >> 4) & 0x0F; // byte 2 bits [7:4] -> pred[3:0] + uint32_t succ = bytes[3] & 0x0F; // byte 3 bits [3:0] -> succ[3:0] + uint32_t val = (succ << 4) | pred; + return QString::asprintf("#0x%02X", val); +} + +void GAParameterRiscvFencePredSucc::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 255) { + op.goodasm->error("RISC-V FENCE pred/succ is out of range (0 to 255)."); + return; + } + + // Split into pred[3:0] and succ[3:0] + uint32_t pred = val & 0x0F; // lower 4 bits + uint32_t succ = (val >> 4) & 0x0F; // upper 4 bits + + // Encode directly into bytes: pred in byte 2 bits [7:4], succ in byte 3 bits [3:0] + // For little-endian: byte 2 is bytes[2], byte 3 is bytes[3] + bytes[2] = (bytes[2] & 0x0F) | (pred << 4); // Set byte 2 bits [7:4] to pred + bytes[3] = (bytes[3] & 0xF0) | succ; // Set byte 3 bits [3:0] to succ +} + +// RISC-V Shamt5 (shamt[4:0]) parameter +// Encoding: shamt[4:0] in bits [24:20] +// Mask: "\x00\x00\xF0\x01" - bits [24:20] in bytes 2-3 (byte 2 bits 7-4, byte 3 bit 0) + +GAParameterRiscvShamt5::GAParameterRiscvShamt5(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvShamt5::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit 5-bit shift amount (0 to 31) + if (val < 0 || val > 31) { + op->goodasm->error("RISC-V shamt5 is out of range (0 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvShamt5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode already extracts bits [24:20] into the value, so just return it + uint32_t shamt = raw & 0x1F; // Mask to 5 bits just to be safe + return prefix + QString::number(shamt); +} + +void GAParameterRiscvShamt5::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < 0 || val > 31) { + op.goodasm->error("RISC-V shamt5 is out of range (0 to 31)."); + return; + } + + // Encode shamt[4:0] into bits [24:20] + rawencode(lang,adr,bytes,op,inslen,val); +} + +// RISC-V CSR12 (csr[11:0]) parameter +// Encoding: csr[11:0] in bits [31:20] +// Mask: "\x00\x00\xF0\xFF" - bits [31:20] in bytes 2-3 + +GAParameterRiscvCsr12::GAParameterRiscvCsr12(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCsr12::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 12-bit CSR address (0 to 4095) + if (val < 0 || val > 4095) { + op->goodasm->error("RISC-V CSR12 is out of range (0 to 4095)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCsr12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode already extracts bits [31:20] into the lower bits + uint32_t csr = raw & 0xFFF; + return QString::asprintf("#0x%03X", csr); +} + +void GAParameterRiscvCsr12::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 4095) { + op.goodasm->error("RISC-V CSR12 is out of range (0 to 4095)."); + return; + } + + // Encode csr[11:0] into bits [31:20] + rawencode(lang,adr,bytes,op,inslen,val); +} + +// RISC-V Uimm5 (uimm[4:0]) parameter +// Encoding: uimm[4:0] in bits [19:15] +// Mask: "\x00\x80\x0F\x00" - bits [19:15] in byte 1-2 + +GAParameterRiscvUimm5::GAParameterRiscvUimm5(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvUimm5::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit 5-bit unsigned immediate (0 to 31) + if (val < 0 || val > 31) { + op->goodasm->error("RISC-V uimm5 is out of range (0 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvUimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode already extracts bits [19:15] into the lower bits + uint32_t uimm = raw & 0x1F; + return prefix + QString::number(uimm); +} + +void GAParameterRiscvUimm5::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 31) { + op.goodasm->error("RISC-V uimm5 is out of range (0 to 31)."); + return; + } + + // Encode uimm[4:0] into bits [19:15] + rawencode(lang,adr,bytes,op,inslen,val); +} + +// C Extension parameter types for compressed 16-bit instructions + +// RISC-V Compressed Register (rd'/rs1'/rs2') parameter +// Encoding: 3-bit field for registers x8-x15 (encoded as 0-7) +// rd' in bits [4:2] (CIW format) or bits [9:7] (most formats) +// rs1' in bits [9:7] +// rs2' in bits [4:2] +// Mask depends on specific format + +GAParameterRiscvCompReg::GAParameterRiscvCompReg(const char* mask){ + setMask(mask); +} + +int GAParameterRiscvCompReg::match(GAParserOperand *op, int len){ + if(op->prefix!=this->prefix) + return 0; + + // Check if it is a valid RISC-V register name. + QString name = op->value; + // Compressed registers are x8-x15 (s0-s1, a0-a7) + if(name == "s0" || name == "s1" || + name == "a0" || name == "a1" || name == "a2" || name == "a3" || + name == "a4" || name == "a5" || name == "a6" || name == "a7") { + return 1; + } + return 0; +} + +QString GAParameterRiscvCompReg::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t regnum = rawdecode(lang, adr, bytes, inslen); + // Compressed register encoding: 0-7 maps to x8-x15 + if(regnum > 7) { + return QString::asprintf("r%llu", (unsigned long long)(regnum + 8)); + } + // Map 0-7 to x8-x15 (s0, s1, a0-a7) + int regnames_idx = 8 + regnum; // x8 = s0, x9 = s1, x10 = a0, etc. + if(regnames_idx < lang->regnames.size()) { + return lang->regnames[regnames_idx]; + } + return QString::asprintf("r%llu", (unsigned long long)(regnum + 8)); +} + +void GAParameterRiscvCompReg::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int regnum = lang->regnames.indexOf(op.value); + if(regnum == -1) { + op.goodasm->error("Unknown RISC-V register: " + op.value); + return; + } + // Compressed registers must be x8-x15 + if(regnum < 8 || regnum > 15) { + op.goodasm->error("RISC-V compressed register must be x8-x15 (s0, s1, a0-a7): " + op.value); + return; + } + // Map x8-x15 (8-15) to compressed encoding (0-7) + int compressed = regnum - 8; + rawencode(lang, adr, bytes, op, inslen, compressed); +} + +// RISC-V CI Format Immediate (imm[5:0]) parameter +// Encoding: imm[5] in bit [12], imm[4:0] in bits [6:2] +// Mask depends on specific instruction + +GAParameterRiscvCIimm6::GAParameterRiscvCIimm6(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIimm6::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); // False on a match + + // Standard CI format: must fit signed 6-bit immediate (-32 to 31) + if (val >= -32 && val <= 31) { + return 1; // valid for standard CI + } + + // c.lui: accepts values 0-63 (imm[17:12]) or shifted values (imm << 12) + // where imm[17:12] is in range 0-63 + // This means values that are multiples of 0x1000 in range 0x0 to 0x3F000 + if (val >= 0) { + if (val <= 63) { + return 1; // valid for c.lui (direct imm[17:12]) + } + // Check if it's a valid shifted value for c.lui + if ((val & 0xFFF) == 0) { // Must be multiple of 0x1000 + uint32_t imm_upper = (val >> 12) & 0x3F; + if (imm_upper >= 1 && imm_upper <= 63) { // c.lui cannot be 0 (reserved for c.addi16sp) + return 1; // valid for c.lui (shifted value) + } + } + } + + // c.addi16sp: accepts multiples of 16 in range -512 to 496 + if ((val & 0xF) == 0) { // Must be multiple of 16 + if (val >= -512 && val <= 496) { + return 1; // valid for c.addi16sp + } + } + + // Value doesn't fit any CI format + op->goodasm->error("RISC-V CI imm6 is out of range (-32 to 31 for standard CI, 0-63 or multiples of 0x1000 up to 0x3F000 for c.lui, or multiples of 16 in -512 to 496 for c.addi16sp)"); + return 0; +} + +QString GAParameterRiscvCIimm6::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + + // Check if this is c.addi16sp (rd=2, bits [1:0]=01, [15:13]=011) or c.lui (bits [1:0]=01, [15:13]=011, rd!=0,2) + // rd is the definitive distinguisher - c.addi16sp has rd=2, c.lui has rd != 0 and rd != 2 + bool is_addi16sp = false; + bool is_lui = false; + if(inslen >= 2) { + uint8_t byte0 = bytes[0]; + uint8_t byte1 = bytes[1]; + uint8_t opcode_low = byte0 & 0x03; // bits [1:0] + uint8_t opcode_high = (byte1 >> 5) & 0x07; // bits [15:13] + + // Extract rd from bits [11:7]: + // bit [7] is in byte0 bit 7 + // bits [11:8] are in byte1 bits [3:0] + // So rd = (bits [11:8] << 1) | bit [7] + uint8_t rd_high = (byte1 & 0x0F); // bits [11:8] + uint8_t rd_low = (byte0 >> 7) & 0x01; // bit [7] + uint8_t rd = (rd_high << 1) | rd_low; + + if(opcode_low == 0x01 && opcode_high == 0x03) { // bits [1:0]=01, [15:13]=011 + if(rd == 2) { + is_addi16sp = true; // rd=2 definitively indicates c.addi16sp + } else if(rd != 0 && rd != 2) { + is_lui = true; // rd != 0,2 definitively indicates c.lui + } + // rd == 0 is invalid for both c.addi16sp and c.lui (reserved) + } + } + + if(is_addi16sp) { + // c.addi16sp: nzimm[9:4] encoded in bits [12|6|5:2] + // According to RISC-V spec and rawencode order: + // rawencode processes mask 0x7C10 in order: + // val[0]->bit[2] (nzimm[6]) + // val[1]->bit[3] (nzimm[7]) + // val[2]->bit[4] (nzimm[8]) + // val[3]->bit[5] (nzimm[9]) + // val[4]->bit[6] (nzimm[4]) + // val[5]->bit[12] (nzimm[5]) + // So rawdecode extracts in the same order: + // raw[0] = nzimm[6] + // raw[1] = nzimm[7] + // raw[2] = nzimm[8] + // raw[3] = nzimm[9] + // raw[4] = nzimm[4] + // raw[5] = nzimm[5] + // The instruction does: sp = sp + sext(nzimm[9:4] << 4) + if(inslen >= 2) { + // Extract individual bits from raw value (already decoded by rawdecode) + uint32_t nzimm6 = (raw >> 0) & 1; // raw[0] = nzimm[6] + uint32_t nzimm7 = (raw >> 1) & 1; // raw[1] = nzimm[7] + uint32_t nzimm8 = (raw >> 2) & 1; // raw[2] = nzimm[8] + uint32_t nzimm9 = (raw >> 3) & 1; // raw[3] = nzimm[9] + uint32_t nzimm4 = (raw >> 4) & 1; // raw[4] = nzimm[4] + uint32_t nzimm5 = (raw >> 5) & 1; // raw[5] = nzimm[5] + // Reconstruct nzimm[9:4] (6 bits): nzimm[9] is MSB, nzimm[4] is LSB + uint32_t nzimm_6bit = (nzimm9 << 5) | (nzimm8 << 4) | (nzimm7 << 3) | (nzimm6 << 2) | (nzimm5 << 1) | nzimm4; + // Sign extend from 6 bits (nzimm[9] is the sign bit) + // Convert to signed 6-bit value: if bit 5 is set, it's negative + int32_t signed_nzimm_6bit; + if(nzimm_6bit & 0x20) { // Check bit 5 (nzimm[9] when in position) - negative + signed_nzimm_6bit = (int32_t)(nzimm_6bit | 0xFFFFFFC0); // Sign extend to 32 bits + } else { + signed_nzimm_6bit = (int32_t)nzimm_6bit; // Positive, no sign extension needed + } + // The instruction does: sp = sp + sext(nzimm[9:4] << 4) + int32_t result = signed_nzimm_6bit << 4; + return prefix + QString::number(result); + } + return prefix + QString::number(0); + } else if(is_lui) { + // c.lui: imm[17:12] in bits [12|6:2] (same positions as CI format) + // The instruction does: rd = imm << 12 + // Extract directly from bytes + if(inslen >= 2) { + uint8_t byte0 = bytes[0]; + uint8_t byte1 = bytes[1]; + uint32_t imm17 = (byte1 >> 4) & 1; // bit [12] = byte1 bit 4 + uint32_t imm16_12 = (byte0 >> 2) & 0x1F; // bits [6:2] = byte0 bits 6:2 + uint32_t imm_upper = (imm17 << 5) | imm16_12; // imm[17:12] + // Return the full shifted value (imm << 12) for display + uint32_t imm_full = imm_upper << 12; + return prefix + QString::asprintf("0x%x", imm_full); + } + return QString::number(0); + } + + // Standard CI format: rawdecode packs bits in mask order + // Mask 0x7C10: bits [6:2] -> raw[4:0], bit [12] -> raw[5] + uint32_t imm4_0 = raw & 0x1F; // raw[4:0] = imm[4:0] + uint32_t imm5 = (raw >> 5) & 1; // raw[5] = imm[5] + int32_t imm = (imm5 << 5) | imm4_0; + // Sign extend from 6 bits + if (imm & 0x20) { + imm |= ~0x3F; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIimm6::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + // Check if this might be c.addi16sp (value is multiple of 16, range -512 to 496) + // or c.lui (value represents upper 6 bits, typically 0-63 but represents imm << 12) + // We detect by checking opcode, rd value, and value constraints + bool is_addi16sp = false; + bool is_lui = false; + if(inslen >= 2 && bytes.length() >= 2) { + uint8_t byte0 = bytes[0]; + uint8_t byte1 = bytes[1]; + uint8_t opcode_low = byte0 & 0x03; + uint8_t opcode_high = (byte1 >> 5) & 0x07; + + if(opcode_low == 0x01 && opcode_high == 0x03) { + // Extract rd from bits [11:7]: + // bit [7] is in byte0 bit 7 + // bits [11:8] are in byte1 bits [3:0] + // So rd = (bits [11:8] << 1) | bit [7] + uint8_t rd_high = (byte1 & 0x0F); // bits [11:8] + uint8_t rd_low = (byte0 >> 7) & 0x01; // bit [7] + uint8_t rd = (rd_high << 1) | rd_low; + + // Check value constraints + bool val_is_multiple_of_16 = ((val & 0xF) == 0) && (val >= -512) && (val <= 496); + bool val_is_lui_range = (val >= 0 && val <= 63) || ((val & 0xFFF) == 0 && (val >> 12) >= 1 && (val >> 12) <= 63); + + // Check value constraints first - if value can only be one instruction, use that + if(val_is_lui_range && !val_is_multiple_of_16) { + // Value only matches c.lui range + is_lui = true; + } else if(val_is_multiple_of_16 && !val_is_lui_range) { + // Value only matches c.addi16sp range + is_addi16sp = true; + } else { + // Value matches both or neither - use rd as definitive distinguisher + if(rd == 2) { + is_addi16sp = true; // rd=2 definitively indicates c.addi16sp + } else if(rd != 0 && rd != 2) { + is_lui = true; // rd != 0,2 definitively indicates c.lui + } else { + // rd is 0 or not yet set - value matches both ranges + // If value is a multiple of 0x1000 (c.lui format), prefer c.lui + if((val & 0xFFF) == 0 && (val >> 12) >= 1 && (val >> 12) <= 63) { + is_lui = true; + } else if(val_is_multiple_of_16) { + // Value is multiple of 16 but not 0x1000 - prefer c.addi16sp + is_addi16sp = true; + } + // If neither matches, neither will be set and standard CI encoding will be used + } + } + } + } + + if(is_addi16sp) { + // c.addi16sp: encode imm[9|4|6|8:7|5] where imm is the actual value (not shifted) + // The instruction does: sp = sp + (imm << 4), so we need to divide by 16 + // Also ensure rd=2 (sp) is set in the instruction + if((val & 0xF) != 0) { + op.goodasm->error("RISC-V c.addi16sp immediate must be a multiple of 16."); + return; + } + if(val < -512 || val > 496) { + op.goodasm->error("RISC-V c.addi16sp immediate is out of range (-512 to 496)."); + return; + } + // Set rd=2 (sp) in the instruction: rd bits [11:7] = 2 = 00010 + // bit [7] is in byte0 bit 7, bits [11:8] are in byte1 bits [3:0] + if(inslen >= 2 && bytes.length() >= 2) { + bytes[0] = (bytes[0] & ~0x80) | (0 << 7); // bit [7] = 0 (from rd bit 0) + bytes[1] = (bytes[1] & ~0x0F) | (1 << 0); // bits [11:8] = 0001 (from rd bits [4:1]) + } + int32_t imm_shifted = (int32_t)(val >> 4); // Divide by 16 (signed) + // Convert to 6-bit two's complement for encoding + // Mask to 6 bits - this automatically handles two's complement for negative values + uint32_t nzimm_6bit = (uint32_t)(imm_shifted & 0x3F); // Get lower 6 bits (handles negative correctly) + // Now extract the individual bits for the scrambled encoding + // According to RISC-V spec: + // nzimm[5] goes to bit [12] + // nzimm[4] goes to bit [6] + // nzimm[9:6] go to bits [5:2] + uint32_t nzimm9 = (nzimm_6bit >> 5) & 1; // nzimm[9] -> bit [5] + uint32_t nzimm8 = (nzimm_6bit >> 4) & 1; // nzimm[8] -> bit [4] + uint32_t nzimm7 = (nzimm_6bit >> 3) & 1; // nzimm[7] -> bit [3] + uint32_t nzimm6 = (nzimm_6bit >> 2) & 1; // nzimm[6] -> bit [2] + uint32_t nzimm5 = (nzimm_6bit >> 1) & 1; // nzimm[5] -> bit [12] + uint32_t nzimm4 = (nzimm_6bit >> 0) & 1; // nzimm[4] -> bit [6] + // Encode according to c.addi16sp format + // rawencode processes mask 0x7C10 (little-endian) in this order: + // Byte 0: bits [6:2] = 0x7C, processes j=2,3,4,5,6 in order + // Byte 1: bit [12] = 0x10, processes j=4 in byte1 + // So the order is: val[0]->bit[2], val[1]->bit[3], val[2]->bit[4], val[3]->bit[5], val[4]->bit[6], val[5]->bit[12] + // Which means: nzimm[6]->bit[2], nzimm[7]->bit[3], nzimm[8]->bit[4], nzimm[9]->bit[5], nzimm[4]->bit[6], nzimm[5]->bit[12] + uint32_t raw = (nzimm6 << 0) | // val[0] -> bit [2] (nzimm[6]) + (nzimm7 << 1) | // val[1] -> bit [3] (nzimm[7]) + (nzimm8 << 2) | // val[2] -> bit [4] (nzimm[8]) + (nzimm9 << 3) | // val[3] -> bit [5] (nzimm[9]) + (nzimm4 << 4) | // val[4] -> bit [6] (nzimm[4]) + (nzimm5 << 5); // val[5] -> bit [12] (nzimm[5]) + rawencode(lang,adr,bytes,op,inslen,raw); + } else if(is_lui) { + // c.lui: encode imm[17:12] where the value represents the upper 6 bits + // The instruction does: rd = imm << 12 + // If val is already the shifted value (like 0x10000), extract upper bits + // Otherwise, if val is 0-63, treat it as imm[17:12] directly + uint32_t imm_upper; + if(val >= 0 && val <= 63) { + imm_upper = val; // Direct value 0-63 + } else { + imm_upper = (val >> 12) & 0x3F; // Extract upper 6 bits from shifted value + } + if(imm_upper == 0) { + op.goodasm->error("RISC-V c.lui immediate cannot be 0 (reserved for c.addi16sp)."); + return; + } + // Note: imm_upper == 1 is technically reserved per spec, but some implementations allow it + // rawencode processes mask 0x7C10 in order: val[0]->bit[2], val[1]->bit[3], val[2]->bit[4], val[3]->bit[5], val[4]->bit[6], val[5]->bit[12] + // For c.lui: imm[17:12] maps to bits [12|6:2] + // So: imm[12]->bit[2], imm[13]->bit[3], imm[14]->bit[4], imm[15]->bit[5], imm[16]->bit[6], imm[17]->bit[12] + uint32_t imm12 = (imm_upper >> 0) & 1; + uint32_t imm13 = (imm_upper >> 1) & 1; + uint32_t imm14 = (imm_upper >> 2) & 1; + uint32_t imm15 = (imm_upper >> 3) & 1; + uint32_t imm16 = (imm_upper >> 4) & 1; + uint32_t imm17 = (imm_upper >> 5) & 1; + uint32_t raw = (imm12 << 0) | // val[0] -> bit [2] + (imm13 << 1) | // val[1] -> bit [3] + (imm14 << 2) | // val[2] -> bit [4] + (imm15 << 3) | // val[3] -> bit [5] + (imm16 << 4) | // val[4] -> bit [6] + (imm17 << 5); // val[5] -> bit [12] + rawencode(lang,adr,bytes,op,inslen,raw); + } else { + // Standard CI format + if (val < -32 || val > 31) { + op.goodasm->error("RISC-V CI imm6 is out of range (-32 to 31)."); + return; + } + + // rawencode packs bits in mask order: raw[4:0]->inst[6:2], raw[5]->inst[12] + // This matches imm[4:0] and imm[5] directly + uint32_t raw = val & 0x3F; // imm[5:0] directly + + rawencode(lang,adr,bytes,op,inslen,raw); + } +} + +// RISC-V CI Format Immediate Unsigned (uimm[5:0]) parameter +// Encoding: Same as CI format but unsigned (0-31) +// Used in C.SLLI, C.SRLI, C.SRAI + +GAParameterRiscvCIUimm6::GAParameterRiscvCIUimm6(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIUimm6::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 6-bit immediate (0 to 31) + if (val < 0 || val > 31) { + op->goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCIUimm6::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode extracts bits in order: [12] (byte 1 bit 4), then [6:2] (byte 0 bits [6:2]) + // So the result has: [12] at bit 5, [6] at bit 4, [5] at bit 3, [4] at bit 2, [3] at bit 1, [2] at bit 0 + // This gives us: imm[5]|imm[4]|imm[3]|imm[2]|imm[1]|imm[0] + uint32_t imm5 = (raw >> 5) & 1; // imm[5] from bit [12] (at position 5 in raw) + uint32_t imm4 = (raw >> 4) & 1; // imm[4] from bit [6] (at position 4 in raw) + uint32_t imm3_0 = raw & 0xF; // imm[3:0] from bits [5:2] (at positions [3:0] in raw) + uint32_t imm = (imm5 << 5) | (imm4 << 4) | imm3_0; + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIUimm6::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 31) { + op.goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)."); + return; + } + + // Encode uimm[5] into bit [12] and uimm[4:0] into bits [6:2] + // rawencode expects the value in the same order as rawdecode extracts it: + // - imm[5] at bit position 5 (encodes to [12]) + // - imm[4] at bit position 4 (encodes to [6]) + // - imm[3:0] at bit positions [3:0] (encodes to [5:2]) + uint32_t imm = val & 0x3F; // uimm[5:0] + uint32_t raw = ((imm >> 5) & 1) << 5 | // uimm[5] -> position 5 (encodes to bit [12]) + ((imm >> 4) & 1) << 4 | // uimm[4] -> position 4 (encodes to bit [6]) + ((imm >> 0) & 0xF); // uimm[3:0] -> positions [3:0] (encodes to bits [5:2]) + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CI Format Immediate Unsigned (uimm[5:0]) parameter for C.SRAI +// Encoding: Same as CIUimm6 but bit [6] is part of opcode (must be 1) +// Used in C.SRAI only (C.SLLI and C.SRLI use GAParameterRiscvCIUimm6) + +GAParameterRiscvCIUimm6Srai::GAParameterRiscvCIUimm6Srai(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIUimm6Srai::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 6-bit immediate (0 to 31) + if (val < 0 || val > 31) { + op->goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCIUimm6Srai::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + // Use the same logic as GAParameterRiscvCIUimm6 - the encoding is the same + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode extracts bits in order: [12] (byte 1 bit 4), then [6:2] (byte 0 bits [6:2]) + // So the result has: [12] at bit 5, [6] at bit 4, [5] at bit 3, [4] at bit 2, [3] at bit 1, [2] at bit 0 + uint32_t imm5 = (raw >> 5) & 1; // imm[5] from bit [12] (at position 5 in raw) + uint32_t imm4 = (raw >> 4) & 1; // imm[4] from bit [6] (at position 4 in raw) + uint32_t imm3_0 = raw & 0xF; // imm[3:0] from bits [5:2] (at positions [3:0] in raw) + uint32_t imm = (imm5 << 5) | (imm4 << 4) | imm3_0; + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIUimm6Srai::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 31) { + op.goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)."); + return; + } + + // Encode uimm[5] into bit [12] and uimm[4:0] into bits [6:2] + // rawencode expects the value in the same order as rawdecode extracts it: + // - imm[5] at bit position 5 (encodes to [12]) + // - imm[4] at bit position 4 (encodes to [6]) + // - imm[3:0] at bit positions [3:0] (encodes to [5:2]) + uint32_t imm = val & 0x3F; // uimm[5:0] + uint32_t raw = ((imm >> 5) & 1) << 5 | // uimm[5] -> position 5 (encodes to bit [12]) + ((imm >> 4) & 1) << 4 | // uimm[4] -> position 4 (encodes to bit [6]) + ((imm >> 0) & 0xF); // uimm[3:0] -> positions [3:0] (encodes to bits [5:2]) + + // Clear bits [6:5] first since they're part of the opcode pattern but also encode imm[4:3] + // The mask 0x7C covers bits [6:2], so we need to clear bits [6:5] before encoding + bytes[0] &= ~0x60; // Clear bits [6:5] in byte 0 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CI Format Immediate (imm[7:2]) parameter for c.lwsp +// Encoding: imm[5] in bit [12], imm[4:2] in bits [6:4], imm[7:6] in bits [3:2] +// Used in C.LWSP + +GAParameterRiscvCIimm7::GAParameterRiscvCIimm7(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIimm7::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 8-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0, 4, 8, 12, ..., 252 (must be multiple of 4, 0-252) + if (val < 0 || val > 252 || (val & 3) != 0) { + op->goodasm->error("RISC-V CI imm7 is out of range (0 to 252, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCIimm7::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask "\x7C\x10" captures instruction bits [6:4], [3:2], [12] + // rawdecode packs bits sequentially by mask position: + // raw bit 0 = instruction bit 2 = imm[6] + // raw bit 1 = instruction bit 3 = imm[7] + // raw bit 2 = instruction bit 4 = imm[2] + // raw bit 3 = instruction bit 5 = imm[3] + // raw bit 4 = instruction bit 6 = imm[4] + // raw bit 5 = instruction bit 12 = imm[5] + uint32_t imm6 = (raw >> 0) & 1; + uint32_t imm7 = (raw >> 1) & 1; + uint32_t imm2 = (raw >> 2) & 1; + uint32_t imm3 = (raw >> 3) & 1; + uint32_t imm4 = (raw >> 4) & 1; + uint32_t imm5 = (raw >> 5) & 1; + uint32_t imm = (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIimm7::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 252 || (val & 3) != 0) { + op.goodasm->error("RISC-V CI imm7 is out of range (0 to 252, must be multiple of 4)."); + return; + } + + // Encode imm[7:2] into sequential raw bits (matching mask bit order) + // raw bit 0 = imm[6] + // raw bit 1 = imm[7] + // raw bit 2 = imm[2] + // raw bit 3 = imm[3] + // raw bit 4 = imm[4] + // raw bit 5 = imm[5] + uint32_t imm = val; + uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 + ((imm >> 7) & 1) << 1 | // imm[7] -> raw bit 1 + ((imm >> 2) & 1) << 2 | // imm[2] -> raw bit 2 + ((imm >> 3) & 1) << 3 | // imm[3] -> raw bit 3 + ((imm >> 4) & 1) << 4 | // imm[4] -> raw bit 4 + ((imm >> 5) & 1) << 5; // imm[5] -> raw bit 5 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CIW Format Immediate (imm[9:2]) parameter +// Encoding: imm[9:2] in bits [10:7|12:11|5|6] (split across instruction) +// Used in C.ADDI4SPN + +GAParameterRiscvCIWimm9::GAParameterRiscvCIWimm9(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIWimm9::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 9-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0 to 1020 (must be multiple of 4) + if (val < 0 || val > 1020 || (val & 3) != 0) { + op->goodasm->error("RISC-V CIW imm9 is out of range (0 to 1020, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCIWimm9::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Extract imm[9:2] from split encoding + // Mask "\xE0\x1F" captures instruction bits [12:5] + // rawdecode packs bits sequentially: + // raw bit 0 = instruction bit 5 = nzuimm[3] + // raw bit 1 = instruction bit 6 = nzuimm[2] + // raw bit 2 = instruction bit 7 = nzuimm[6] + // raw bit 3 = instruction bit 8 = nzuimm[7] + // raw bit 4 = instruction bit 9 = nzuimm[8] + // raw bit 5 = instruction bit 10 = nzuimm[9] + // raw bit 6 = instruction bit 11 = nzuimm[4] + // raw bit 7 = instruction bit 12 = nzuimm[5] + uint32_t imm3 = (raw >> 0) & 1; // raw bit 0 + uint32_t imm2 = (raw >> 1) & 1; // raw bit 1 + uint32_t imm6 = (raw >> 2) & 1; // raw bit 2 + uint32_t imm7 = (raw >> 3) & 1; // raw bit 3 + uint32_t imm8 = (raw >> 4) & 1; // raw bit 4 + uint32_t imm9 = (raw >> 5) & 1; // raw bit 5 + uint32_t imm4 = (raw >> 6) & 1; // raw bit 6 + uint32_t imm5 = (raw >> 7) & 1; // raw bit 7 + uint32_t imm = (imm9 << 9) | (imm8 << 8) | (imm7 << 7) | (imm6 << 6) | + (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIWimm9::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 1020 || (val & 3) != 0) { + op.goodasm->error("RISC-V CIW imm9 is out of range (0 to 1020, must be multiple of 4)."); + return; + } + + // Encode imm[9:2] into sequential raw bits (matching mask bit order) + // raw bit 0 = nzuimm[3] + // raw bit 1 = nzuimm[2] + // raw bit 2 = nzuimm[6] + // raw bit 3 = nzuimm[7] + // raw bit 4 = nzuimm[8] + // raw bit 5 = nzuimm[9] + // raw bit 6 = nzuimm[4] + // raw bit 7 = nzuimm[5] + uint32_t imm = val; + uint32_t raw = ((imm >> 3) & 1) << 0 | // nzuimm[3] -> raw bit 0 + ((imm >> 2) & 1) << 1 | // nzuimm[2] -> raw bit 1 + ((imm >> 6) & 1) << 2 | // nzuimm[6] -> raw bit 2 + ((imm >> 7) & 1) << 3 | // nzuimm[7] -> raw bit 3 + ((imm >> 8) & 1) << 4 | // nzuimm[8] -> raw bit 4 + ((imm >> 9) & 1) << 5 | // nzuimm[9] -> raw bit 5 + ((imm >> 4) & 1) << 6 | // nzuimm[4] -> raw bit 6 + ((imm >> 5) & 1) << 7; // nzuimm[5] -> raw bit 7 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CL Format Immediate (imm[5:2]) parameter +// Encoding: imm[5] in bit [12], imm[4:2] in bits [6:5|2] +// Used in C.LW + +GAParameterRiscvCLimm5::GAParameterRiscvCLimm5(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCLimm5::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 4-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0, 4, 8, 12, ..., 124 (must be multiple of 4, 0-124) + if (val < 0 || val > 124 || (val & 3) != 0) { + op->goodasm->error("RISC-V CL imm5 is out of range (0 to 124, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCLimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask "\x60\x1C" captures instruction bits [6:5], [12:10] + // rawdecode packs bits sequentially by mask position: + // raw bit 0 = instruction bit 5 = imm[6] + // raw bit 1 = instruction bit 6 = imm[2] + // raw bit 2 = instruction bit 10 = imm[3] + // raw bit 3 = instruction bit 11 = imm[4] + // raw bit 4 = instruction bit 12 = imm[5] + uint32_t imm6 = (raw >> 0) & 1; + uint32_t imm2 = (raw >> 1) & 1; + uint32_t imm3 = (raw >> 2) & 1; + uint32_t imm4 = (raw >> 3) & 1; + uint32_t imm5 = (raw >> 4) & 1; + uint32_t imm = (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); + return prefix + QString::number(imm); +} + +void GAParameterRiscvCLimm5::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 124 || (val & 3) != 0) { + op.goodasm->error("RISC-V CL imm5 is out of range (0 to 124, must be multiple of 4)."); + return; + } + + // Encode imm[6:2] into sequential raw bits (matching mask bit order) + // raw bit 0 = imm[6] + // raw bit 1 = imm[2] + // raw bit 2 = imm[3] + // raw bit 3 = imm[4] + // raw bit 4 = imm[5] + uint32_t imm = val; + uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 + ((imm >> 2) & 1) << 1 | // imm[2] -> raw bit 1 + ((imm >> 3) & 1) << 2 | // imm[3] -> raw bit 2 + ((imm >> 4) & 1) << 3 | // imm[4] -> raw bit 3 + ((imm >> 5) & 1) << 4; // imm[5] -> raw bit 4 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CS Format Immediate (imm[5:2]) parameter +// Encoding: Same as CL format +// Used in C.SW + +GAParameterRiscvCSimm5::GAParameterRiscvCSimm5(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCSimm5::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 4-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0, 4, 8, 12, ..., 124 (must be multiple of 4, 0-124) + if (val < 0 || val > 124 || (val & 3) != 0) { + op->goodasm->error("RISC-V CS imm5 is out of range (0 to 124, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCSimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask "\x60\x1C" captures instruction bits [6:5], [12:10] + // rawdecode packs bits sequentially by mask position: + // raw bit 0 = instruction bit 5 = imm[6] + // raw bit 1 = instruction bit 6 = imm[2] + // raw bit 2 = instruction bit 10 = imm[3] + // raw bit 3 = instruction bit 11 = imm[4] + // raw bit 4 = instruction bit 12 = imm[5] + uint32_t imm6 = (raw >> 0) & 1; + uint32_t imm2 = (raw >> 1) & 1; + uint32_t imm3 = (raw >> 2) & 1; + uint32_t imm4 = (raw >> 3) & 1; + uint32_t imm5 = (raw >> 4) & 1; + uint32_t imm = (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); + return prefix + QString::number(imm); +} + +void GAParameterRiscvCSimm5::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 124 || (val & 3) != 0) { + op.goodasm->error("RISC-V CS imm5 is out of range (0 to 124, must be multiple of 4)."); + return; + } + + // Encode imm[6:2] into sequential raw bits (matching mask bit order) + // raw bit 0 = imm[6] + // raw bit 1 = imm[2] + // raw bit 2 = imm[3] + // raw bit 3 = imm[4] + // raw bit 4 = imm[5] + uint32_t imm = val; + uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 + ((imm >> 2) & 1) << 1 | // imm[2] -> raw bit 1 + ((imm >> 3) & 1) << 2 | // imm[3] -> raw bit 2 + ((imm >> 4) & 1) << 3 | // imm[4] -> raw bit 3 + ((imm >> 5) & 1) << 4; // imm[5] -> raw bit 4 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CSS Format Immediate (imm[7:2]) parameter +// Encoding: imm[7:2] in bits [12:7] +// Used in C.SWSP + +GAParameterRiscvCSSimm7::GAParameterRiscvCSSimm7(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCSSimm7::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 6-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0, 4, 8, 12, ..., 252 (must be multiple of 4, 0-252) + if (val < 0 || val > 252 || (val & 3) != 0) { + op->goodasm->error("RISC-V CSS imm7 is out of range (0 to 252, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCSSimm7::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode with mask 0x80 0x1F extracts bits [12:7] in the order: + // Byte 1 (last): bits [12:8] (mask 0x1F = bits [4:0] of byte 1) + // Byte 0 (first): bit 7 (mask 0x80 = bit 7 of byte 0) + // rawdecode processes bits from highest byte to lowest, highest bit to lowest bit: + // Byte 1, bit 4 (bit 12) → raw bit 5 (MSB of imm[7:2]) + // Byte 1, bit 3 (bit 11) → raw bit 4 + // Byte 1, bit 2 (bit 10) → raw bit 3 + // Byte 1, bit 1 (bit 9) → raw bit 2 + // Byte 1, bit 0 (bit 8) → raw bit 1 + // Byte 0, bit 7 (bit 7) → raw bit 0 (LSB of imm[7:2]) + // So raw already contains imm[7:2] in the correct order! + uint32_t imm = raw << 2; // Shift left by 2 (imm[1:0] are always 0) + return prefix + QString::number(imm); +} + +void GAParameterRiscvCSSimm7::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 252 || (val & 3) != 0) { + op.goodasm->error("RISC-V CSS imm7 is out of range (0 to 252, must be multiple of 4)."); + return; + } + + // Encode imm[7:2] into bits [12:7] + // rawencode processes bits from lowest bit to highest, placing them into mask positions + // in order (highest byte first, highest bit first): + // raw bit 0 → Byte 0, bit 7 (bit 7) - LSB + // raw bit 1 → Byte 1, bit 0 (bit 8) + // raw bit 2 → Byte 1, bit 1 (bit 9) + // raw bit 3 → Byte 1, bit 2 (bit 10) + // raw bit 4 → Byte 1, bit 3 (bit 11) + // raw bit 5 → Byte 1, bit 4 (bit 12) - MSB + // So raw should be imm[7:2] directly (no rearrangement needed) + uint32_t imm = (val >> 2) & 0x3F; // imm[7:2] + rawencode(lang,adr,bytes,op,inslen,imm); +} + +// RISC-V CB Format Immediate (imm[8|4:3|7:6|2:1|5]) parameter +// Encoding: Split across instruction bits +// Used in C.BEQZ, C.BNEZ + +GAParameterRiscvCBimm9::GAParameterRiscvCBimm9(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCBimm9::match(GAParserOperand *op, int len){ + // Accept any label or integer - range check will happen in encode with PC-relative calculation + // This allows labels to be matched and resolved during encoding + return 1; // valid +} + +QString GAParameterRiscvCBimm9::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask 0x7C1C: inst[6:2] -> raw[4:0], inst[12:10] -> raw[7:5] + // CB format immediate mapping in instruction bits: + // inst[2]=imm[5], inst[3]=imm[1], inst[4]=imm[2], inst[5]=imm[6] + // inst[6]=imm[7], inst[10]=imm[3], inst[11]=imm[4], inst[12]=imm[8] + // So in raw: + // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[6] + // raw[4]=imm[7], raw[5]=imm[3], raw[6]=imm[4], raw[7]=imm[8] + int32_t imm1 = (raw >> 1) & 1; + int32_t imm2 = (raw >> 2) & 1; + int32_t imm3 = (raw >> 5) & 1; + int32_t imm4 = (raw >> 6) & 1; + int32_t imm5 = raw & 1; + int32_t imm6 = (raw >> 3) & 1; + int32_t imm7 = (raw >> 4) & 1; + int32_t imm8 = (raw >> 7) & 1; + int32_t imm = (imm8 << 8) | (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | + (imm4 << 4) | (imm3 << 3) | (imm2 << 2) | (imm1 << 1); + // Sign extend from 9 bits + if (imm & 0x100) { + imm |= ~0x1FF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvCBimm9::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + // PC-relative addressing: calculate offset from current address + int64_t target = op.int64(true); + int64_t val = target - adr; // PC-relative offset + + // Range check: -256 to 254 bytes (signed 9-bit, even addresses only) + if (val < -256 || val > 254) { + op.goodasm->error("RISC-V CB imm9 is out of range (-256 to 254 bytes from PC)."); + return; + } + if ((val & 1) != 0) { + op.goodasm->error("RISC-V CB imm9 must be even (target address must be 2-byte aligned)."); + return; + } + + // Pack into raw in mask order: + // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[6] + // raw[4]=imm[7], raw[5]=imm[3], raw[6]=imm[4], raw[7]=imm[8] + uint32_t imm = val & 0x1FE; // imm[8:1], clear imm[0] + uint32_t raw = (((imm >> 5) & 1) << 0) | // imm[5] -> raw[0] + (((imm >> 1) & 1) << 1) | // imm[1] -> raw[1] + (((imm >> 2) & 1) << 2) | // imm[2] -> raw[2] + (((imm >> 6) & 1) << 3) | // imm[6] -> raw[3] + (((imm >> 7) & 1) << 4) | // imm[7] -> raw[4] + (((imm >> 3) & 1) << 5) | // imm[3] -> raw[5] + (((imm >> 4) & 1) << 6) | // imm[4] -> raw[6] + (((imm >> 8) & 1) << 7); // imm[8] -> raw[7] + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CJ Format Immediate (imm[11|4|9:8|10|6|7|3:1|5]) parameter +// Encoding: Split across instruction bits +// Used in C.J + +GAParameterRiscvCJimm12::GAParameterRiscvCJimm12(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCJimm12::match(GAParserOperand *op, int len){ + // Accept any label or integer - range check will happen in encode with PC-relative calculation + // This allows labels to be matched and resolved during encoding + return 1; // valid +} + +QString GAParameterRiscvCJimm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask 0xFC1F: inst[7:2] -> raw[5:0], inst[12:8] -> raw[10:6] + // CJ format immediate mapping in instruction bits: + // inst[2]=imm[5], inst[3]=imm[1], inst[4]=imm[2], inst[5]=imm[3] + // inst[6]=imm[7], inst[7]=imm[6], inst[8]=imm[10], inst[9]=imm[9] + // inst[10]=imm[8], inst[11]=imm[4], inst[12]=imm[11] + // So in raw: + // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[3] + // raw[4]=imm[7], raw[5]=imm[6], raw[6]=imm[10], raw[7]=imm[9] + // raw[8]=imm[8], raw[9]=imm[4], raw[10]=imm[11] + int32_t imm1 = (raw >> 1) & 1; + int32_t imm2 = (raw >> 2) & 1; + int32_t imm3 = (raw >> 3) & 1; + int32_t imm4 = (raw >> 9) & 1; + int32_t imm5 = raw & 1; + int32_t imm6 = (raw >> 5) & 1; + int32_t imm7 = (raw >> 4) & 1; + int32_t imm8 = (raw >> 8) & 1; + int32_t imm9 = (raw >> 7) & 1; + int32_t imm10 = (raw >> 6) & 1; + int32_t imm11 = (raw >> 10) & 1; + int32_t imm = (imm11 << 11) | (imm10 << 10) | (imm9 << 9) | (imm8 << 8) | + (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | + (imm3 << 3) | (imm2 << 2) | (imm1 << 1); + // Sign extend from 12 bits + if (imm & 0x800) { + imm |= ~0xFFF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvCJimm12::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + // PC-relative addressing: calculate offset from current address + int64_t target = op.int64(true); + int64_t val = target - adr; // PC-relative offset + + // Range check: -2048 to 2046 bytes (signed 12-bit, even addresses only) + if (val < -2048 || val > 2046) { + op.goodasm->error("RISC-V CJ imm12 is out of range (-2048 to 2046 bytes from PC)."); + return; + } + if ((val & 1) != 0) { + op.goodasm->error("RISC-V CJ imm12 must be even (target address must be 2-byte aligned)."); + return; + } + + // Pack into raw in mask order: + // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[3] + // raw[4]=imm[7], raw[5]=imm[6], raw[6]=imm[10], raw[7]=imm[9] + // raw[8]=imm[8], raw[9]=imm[4], raw[10]=imm[11] + uint32_t imm = val & 0xFFE; // imm[11:1], clear imm[0] + uint32_t raw = (((imm >> 5) & 1) << 0) | // imm[5] -> raw[0] + (((imm >> 1) & 1) << 1) | // imm[1] -> raw[1] + (((imm >> 2) & 1) << 2) | // imm[2] -> raw[2] + (((imm >> 3) & 1) << 3) | // imm[3] -> raw[3] + (((imm >> 7) & 1) << 4) | // imm[7] -> raw[4] + (((imm >> 6) & 1) << 5) | // imm[6] -> raw[5] + (((imm >> 10) & 1) << 6) | // imm[10] -> raw[6] + (((imm >> 9) & 1) << 7) | // imm[9] -> raw[7] + (((imm >> 8) & 1) << 8) | // imm[8] -> raw[8] + (((imm >> 4) & 1) << 9) | // imm[4] -> raw[9] + (((imm >> 11) & 1) << 10); // imm[11] -> raw[10] + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CB Format Immediate for C.ANDI (imm[5:0]) parameter +// Encoding: Standard CB format: imm[5] in bit [12], imm[4:0] in bits [6:2] +// - imm[5] in bit [12] +// - imm[4:0] in bits [6:2] +// Note: bits [6:5] are part of the immediate encoding, not the opcode pattern +// Range: -32 to 31 (6-bit signed) + +GAParameterRiscvCBimm6Andi::GAParameterRiscvCBimm6Andi(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCBimm6Andi::match(GAParserOperand *op, int len){ + int64_t val = op->int64(false); // False on a match + + // must fit signed 6-bit immediate (-32 to 31) + if (val < -32 || val > 31) { + op->goodasm->error("RISC-V CB imm6 (c.andi) is out of range (-32 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCBimm6Andi::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + + // rawdecode extracts bits according to mask 0x7C10: + // - bits [6:2] from byte 0 → bits 0-4 of raw = imm[4:0] + // - bit [12] from byte 1 → bit 5 of raw = imm[5] + // So raw already has: imm[4:0] in bits 0-4, imm[5] in bit 5 + uint32_t imm5 = (raw >> 5) & 1; // bit 5 of raw = imm[5] + uint32_t imm4_0 = raw & 0x1F; // bits 0-4 of raw = imm[4:0] + + // Reconstruct imm[5:0] = imm[5] << 5 | imm[4:0] + uint32_t imm = (imm5 << 5) | imm4_0; + + // Sign extend from 6 bits + if (imm & 0x20) { + imm |= ~0x3F; + } + int32_t signed_imm = (int32_t)imm; + return prefix + QString::number(signed_imm); +} + +void GAParameterRiscvCBimm6Andi::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -32 || val > 31) { + op.goodasm->error("RISC-V CB imm6 (c.andi) is out of range (-32 to 31)."); + return; + } + + // Convert to 6-bit signed value + int32_t imm_signed = val & 0x3F; + if (imm_signed & 0x20) { + imm_signed |= ~0x3F; // Sign extend + } + + // Extract imm[5] and imm[4:0] as unsigned for encoding + // Mask 0x7C10 encodes: imm[4:0] in bits [6:2], imm[5] in bit [12] + // rawencode processes mask bits in order: first bits [6:2] (5 bits), then bit [12] (1 bit) + // So the raw value should have: imm[4:0] in bits 0-4, imm[5] in bit 5 + uint32_t imm = (uint32_t)(imm_signed & 0x3F); // Get 6-bit value as unsigned + uint32_t imm5 = (imm >> 5) & 1; + uint32_t imm4_0 = imm & 0x1F; + + // rawencode processes mask 0x7C10 in order: + // - Byte 0 bits [6:2] (5 bits) = imm[4:0] + // - Byte 1 bit [12] (1 bit) = imm[5] + // So raw value: imm[4:0] in lower 5 bits, imm[5] in bit 5 + uint32_t raw = imm4_0 | (imm5 << 5); + + rawencode(lang,adr,bytes,op,inslen,raw); +} diff --git a/galangriscv.h b/galangriscv.h new file mode 100644 index 0000000..e0cb4ea --- /dev/null +++ b/galangriscv.h @@ -0,0 +1,341 @@ +#include "galanguage.h" +#include "gaparameter.h" +#include "gamnemonic.h" + +class GALangRISCV : public GALanguage +{ +public: + GALangRISCV(); +}; + +class GAParameterRiscvReg : public GAParameter { + public: + GAParameterRiscvReg(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + + +class GAParameterRiscvImm12 : public GAParameter { +public: + GAParameterRiscvImm12(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvUtypeImm20 : public GAParameter { +public: + GAParameterRiscvUtypeImm20(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvBtypeImm13 : public GAParameter { +public: + GAParameterRiscvBtypeImm13(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvJtypeImm21 : public GAParameter { +public: + GAParameterRiscvJtypeImm21(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvStypeImm12 : public GAParameter { +public: + GAParameterRiscvStypeImm12(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvFencePredSucc : public GAParameter { +public: + GAParameterRiscvFencePredSucc(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvShamt5 : public GAParameter { +public: + GAParameterRiscvShamt5(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCsr12 : public GAParameter { +public: + GAParameterRiscvCsr12(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvUimm5 : public GAParameter { +public: + GAParameterRiscvUimm5(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +// C Extension parameter types for compressed 16-bit instructions + +class GAParameterRiscvCompReg : public GAParameter { +public: + GAParameterRiscvCompReg(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIimm6 : public GAParameter { +public: + GAParameterRiscvCIimm6(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIUimm6 : public GAParameter { +public: + GAParameterRiscvCIUimm6(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIUimm6Srai : public GAParameter { +public: + GAParameterRiscvCIUimm6Srai(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIimm7 : public GAParameter { +public: + GAParameterRiscvCIimm7(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIWimm9 : public GAParameter { +public: + GAParameterRiscvCIWimm9(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCLimm5 : public GAParameter { +public: + GAParameterRiscvCLimm5(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCSimm5 : public GAParameter { +public: + GAParameterRiscvCSimm5(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCSSimm7 : public GAParameter { +public: + GAParameterRiscvCSSimm7(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCBimm9 : public GAParameter { +public: + GAParameterRiscvCBimm9(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCJimm12 : public GAParameter { +public: + GAParameterRiscvCJimm12(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCBimm6Andi : public GAParameter { +public: + GAParameterRiscvCBimm6Andi(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; \ No newline at end of file diff --git a/galangriscv32.cpp b/galangriscv32.cpp new file mode 100644 index 0000000..9a66824 --- /dev/null +++ b/galangriscv32.cpp @@ -0,0 +1,4543 @@ +#include "goodasm.h" + +#include "galangriscv32.h" + +#include "gamnemonic.h" + +#define mnem new GAMnemonic + +// https://riscv.org/specifications/ratified/ +// https://msyksphinz-self.github.io/riscv-isadoc/ +// Follow RISC-V Instruction Organization from the ISA Manual + +GALangRISCV::GALangRISCV() { + endian = LITTLE; + name = "riscv32"; + maxbytes = 4; // Maximum instruction length (32-bit or 16-bit compressed) + + // Register names. + regnames.clear(); + regnames + <<"zero"<<"ra"<<"sp"<<"gp"<<"tp" + <<"t0"<<"t1"<<"t2" + <<"s0"<<"s1" + <<"a0"<<"a1"<<"a2"<<"a3"<<"a4"<<"a5"<<"a6"<<"a7" + <<"s2"<<"s3"<<"s4"<<"s5"<<"s6"<<"s7"<<"s8"<<"s9"<<"s10"<<"s11" + <<"t3"<<"t4"<<"t5"<<"t6" + // Floating point registers f0-f31 + <<"f0"<<"f1"<<"f2"<<"f3"<<"f4"<<"f5"<<"f6"<<"f7" + <<"f8"<<"f9"<<"f10"<<"f11"<<"f12"<<"f13"<<"f14"<<"f15" + <<"f16"<<"f17"<<"f18"<<"f19"<<"f20"<<"f21"<<"f22"<<"f23" + <<"f24"<<"f25"<<"f26"<<"f27"<<"f28"<<"f29"<<"f30"<<"f31"; + + threshold = 0.0; + + /* Integer Computational Instructions (RV32I Base) */ + + /* R-Type Instructions */ + + /* + * Example: ADD rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00000033 (funct7=0x00, funct3=000 + opcode=0x33) + */ + insert( + mnem("add", 4, + "\x33\x00\x00\x00", // pattern 32-bit LE: 0x00000033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Add: rd = rs1 + rs2") + ->example("add a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SUB rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x40000033 (funct7=0x20=bit30, funct3=000 + opcode=0x33) + */ + insert( + mnem("sub", 4, + "\x33\x00\x00\x40", // pattern 32-bit LE: 0x40000033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Subtract: rd = rs1 - rs2") + ->example("sub a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SLL rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00100033 (funct7=0x00, funct3=001 + opcode=0x33) + */ + insert( + mnem("sll", 4, + "\x33\x10\x00\x00", // pattern 32-bit LE: 0x00100033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Left Logical: rd = rs1 << rs2[4:0]") + ->example("sll a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SLT rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00200033 (funct7=0x00, funct3=010 + opcode=0x33) + */ + insert( + mnem("slt", 4, + "\x33\x20\x00\x00", // pattern 32-bit LE: 0x00200033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Set Less Than: rd = (rs1 < rs2) ? 1 : 0 (signed)") + ->example("slt a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SLTU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00300033 (funct7=0x00, funct3=011 + opcode=0x33) + */ + insert( + mnem("sltu", 4, + "\x33\x30\x00\x00", // pattern 32-bit LE: 0x00300033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Set Less Than Unsigned: rd = (rs1 < rs2) ? 1 : 0 (unsigned)") + ->example("sltu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: XOR rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00400033 (funct7=0x00, funct3=100 + opcode=0x33) + */ + insert( + mnem("xor", 4, + "\x33\x40\x00\x00", // pattern 32-bit LE: 0x00400033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Bitwise XOR: rd = rs1 ^ rs2") + ->example("xor a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SRL rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00500033 (funct7=0x00, funct3=101 + opcode=0x33) + */ + insert( + mnem("srl", 4, + "\x33\x50\x00\x00", // pattern 32-bit LE: 0x00500033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Right Logical: rd = rs1 >> rs2[4:0]") + ->example("srl a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: SRA rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x40500033 (funct7=0x20=bit30, funct3=101 + opcode=0x33) + */ + insert( + mnem("sra", 4, + "\x33\x50\x00\x40", // pattern 32-bit LE: 0x40500033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Right Arithmetic: rd = rs1 >> rs2[4:0] (sign-extended)") + ->example("sra a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: OR rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00600033 (funct7=0x00, funct3=110 + opcode=0x33) + */ + insert( + mnem("or", 4, + "\x33\x60\x00\x00", // pattern 32-bit LE: 0x00600033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Bitwise OR: rd = rs1 | rs2") + ->example("or a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* + * Example: AND rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00700033 (funct7=0x00, funct3=111 + opcode=0x33) + */ + insert( + mnem("and", 4, + "\x33\x70\x00\x00", // pattern 32-bit LE: 0x00700033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Bitwise AND: rd = rs1 & rs2") + ->example("and a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 + + /* I-Type Instructions */ + + /* + * Example: ADDI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000013 (funct3=000 + opcode=0x13) + */ + insert( + mnem("addi", 4, + "\x13\x00\x00\x00", // pattern 32-bit LE: 0x00000013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Add immediate: rd = rs1 + imm") + ->example("addi a0, a0, #1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: SLTI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002013 (funct3=010 + opcode=0x13) + */ + insert( + mnem("slti", 4, + "\x13\x20\x00\x00", // pattern 32-bit LE: 0x00002013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Set Less Than Immediate: rd = (rs1 < imm) ? 1 : 0 (signed)") + ->example("slti a0, a1, #10") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: SLTIU rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00003013 (funct3=011 + opcode=0x13) + */ + insert( + mnem("sltiu", 4, + "\x13\x30\x00\x00", // pattern 32-bit LE: 0x00003013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Set Less Than Immediate Unsigned: rd = (rs1 < imm) ? 1 : 0 (unsigned)") + ->example("sltiu a0, a1, #10") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: XORI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00004013 (funct3=100 + opcode=0x13) + */ + insert( + mnem("xori", 4, + "\x13\x40\x00\x00", // pattern 32-bit LE: 0x00004013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("XOR Immediate: rd = rs1 ^ imm") + ->example("xori a0, a1, #0xFF") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: ORI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00006013 (funct3=110 + opcode=0x13) + */ + insert( + mnem("ori", 4, + "\x13\x60\x00\x00", // pattern 32-bit LE: 0x00006013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("OR Immediate: rd = rs1 | imm") + ->example("ori a0, a1, #0xFF") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* + * Example: ANDI rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00007013 (funct3=111 + opcode=0x13) + */ + insert( + mnem("andi", 4, + "\x13\x70\x00\x00", // pattern 32-bit LE: 0x00007013 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("AND Immediate: rd = rs1 & imm") + ->example("andi a0, a1, #0xFF") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 + + /* I-type Shift Immediate Instructions */ + + /* + * Example: SLLI rd, rs1, shamt5 + * + * Encoding: + * shamt[4:0] rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00100013 (funct7=0x00, funct3=001 + opcode=0x13) + * + * shamt[4:0] is in bits [24:20] + */ + insert( + mnem("slli", 4, + "\x13\x10\x00\x00", // pattern 32-bit LE: 0x00100013 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Left Logical Immediate: rd = rs1 << shamt") + ->example("slli a0, a1, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] + + /* + * Example: SRLI rd, rs1, shamt5 + * + * Encoding: + * shamt[4:0] rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00500013 (funct7=0x00, funct3=101 + opcode=0x13) + */ + insert( + mnem("srli", 4, + "\x13\x50\x00\x00", // pattern 32-bit LE: 0x00500013 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Right Logical Immediate: rd = rs1 >> shamt") + ->example("srli a0, a1, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] + + /* + * Example: SRAI rd, rs1, shamt5 + * + * Encoding: + * shamt[4:0] rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x40500013 (funct7=0x20, funct3=101 + opcode=0x13) + */ + insert( + mnem("srai", 4, + "\x13\x50\x00\x40", // pattern 32-bit LE: 0x40500013 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Shift Right Arithmetic Immediate: rd = rs1 >> shamt (sign-extended)") + ->example("srai a0, a1, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] + + /* Control Transfer Instructions */ + + /* U-Type Control Transfer Instructions */ + + /* + * Example: LUI rd, imm20 + * + * Encoding: + * imm[31:12] rd opcode + * + * Mask : 0x0000007F (mask opcode) + * Value : 0x00000037 (opcode=0x37) + */ + insert( + mnem("lui", 4, + "\x37\x00\x00\x00", // pattern 32-bit LE: 0x00000037 + "\x7F\x00\x00\x00")) // mask: opcode only + ->help("Load Upper Immediate: rd = imm << 12") + ->example("lui a0, #0x12345000") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvUtypeImm20("\x00\xF0\xFF\xFF")); // imm[31:12] bits [31:12] + + /* + * Example: AUIPC rd, imm20 + * + * Encoding: + * imm[31:12] rd opcode + * + * Mask : 0x0000007F (mask opcode) + * Value : 0x00000017 (opcode=0x17) + */ + insert( + mnem("auipc", 4, + "\x17\x00\x00\x00", // pattern 32-bit LE: 0x00000017 + "\x7F\x00\x00\x00")) // mask: opcode only + ->help("Add Upper Immediate to PC: rd = PC + (imm << 12)") + ->example("auipc a0, #0x12345000") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvUtypeImm20("\x00\xF0\xFF\xFF")); // imm[31:12] bits [31:12] + + /* J-Type Control Transfer Instructions */ + + /* + * Example: JAL rd, imm21 + * + * Encoding: + * imm[20|10:1|11|19:12] rd opcode + * + * Mask : 0x0000007F (mask opcode) + * Value : 0x0000006F (opcode=0x6F) + */ + insert( + mnem("jal", 4, + "\x6F\x00\x00\x00", // pattern 32-bit LE: 0x0000006F + "\x7F\x00\x00\x00")) // mask: opcode only + ->help("Jump and Link: rd = PC + 4; PC += imm") + ->example("jal ra, #8") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvJtypeImm21("\x00\xF0\xFF\xFF")); // imm[20:1] in bits [31:12] + + /* I-Type Control Transfer Instructions */ + + /* + * Example: JALR rd, rs1, imm12 + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000067 (funct3=000 + opcode=0x67) + */ + insert( + mnem("jalr", 4, + "\x67\x00\x00\x00", // pattern 32-bit LE: 0x00000067 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Jump and Link Register: rd = PC + 4; PC = (rs1 + imm) & ~1") + ->example("jalr ra, a1, #0") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] + + /* B-Type Control Transfer Instructions */ + + /* + * Example: BEQ rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000063 (funct3=000 + opcode=0x63) + */ + insert( + mnem("beq", 4, + "\x63\x00\x00\x00", // pattern 32-bit LE: 0x00000063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Equal: if (rs1 == rs2) PC += imm") + ->example("beq a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BNE rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00001063 (funct3=001 + opcode=0x63) + */ + insert( + mnem("bne", 4, + "\x63\x10\x00\x00", // pattern 32-bit LE: 0x00100063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Not Equal: if (rs1 != rs2) PC += imm") + ->example("bne a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BLT rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00004063 (funct3=100 + opcode=0x63) + */ + insert( + mnem("blt", 4, + "\x63\x40\x00\x00", // pattern 32-bit LE: 0x00004063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Less Than: if (rs1 < rs2) PC += imm (signed)") + ->example("blt a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BGE rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00005063 (funct3=101 + opcode=0x63) + */ + insert( + mnem("bge", 4, + "\x63\x50\x00\x00", // pattern 32-bit LE: 0x00005063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Greater or Equal: if (rs1 >= rs2) PC += imm (signed)") + ->example("bge a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BLTU rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00006063 (funct3=110 + opcode=0x63) + */ + insert( + mnem("bltu", 4, + "\x63\x60\x00\x00", // pattern 32-bit LE: 0x00006063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Less Than Unsigned: if (rs1 < rs2) PC += imm (unsigned)") + ->example("bltu a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* + * Example: BGEU rs1, rs2, imm13 + * + * Encoding: + * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00007063 (funct3=111 + opcode=0x63) + */ + insert( + mnem("bgeu", 4, + "\x63\x70\x00\x00", // pattern 32-bit LE: 0x00007063 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Branch if Greater or Equal Unsigned: if (rs1 >= rs2) PC += imm (unsigned)") + ->example("bgeu a0, a1, #8") + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding + + /* Load Instructions */ + + /* + * Example: LB rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000003 (funct3=000 + opcode=0x03) + */ + insert( + mnem("lb", 4, + "\x03\x00\x00\x00", // pattern 32-bit LE: 0x00000003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Byte (signed): rd = sign-extend(M[rs1 + imm][7:0])") + ->example("lb a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: LH rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00001003 (funct3=001 + opcode=0x03) + */ + insert( + mnem("lh", 4, + "\x03\x10\x00\x00", // pattern 32-bit LE: 0x00001003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Halfword (signed): rd = sign-extend(M[rs1 + imm][15:0])") + ->example("lh a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: LW rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002003 (funct3=010 + opcode=0x03) + */ + insert( + mnem("lw", 4, + "\x03\x20\x00\x00", // pattern 32-bit LE: 0x00002003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Word: rd = M[rs1 + imm][31:0]") + ->example("lw a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: LBU rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00004003 (funct3=100 + opcode=0x03) + */ + insert( + mnem("lbu", 4, + "\x03\x40\x00\x00", // pattern 32-bit LE: 0x00004003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Byte Unsigned: rd = zero-extend(M[rs1 + imm][7:0])") + ->example("lbu a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: LHU rd, imm(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00005003 (funct3=101 + opcode=0x03) + */ + insert( + mnem("lhu", 4, + "\x03\x50\x00\x00", // pattern 32-bit LE: 0x00005003 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Load Halfword Unsigned: rd = zero-extend(M[rs1 + imm][15:0])") + ->example("lhu a0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* Store Instructions */ + + /* + * Example: SB rs2, imm(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000023 (funct3=000 + opcode=0x23) + */ + insert( + mnem("sb", 4, + "\x23\x00\x00\x00", // pattern 32-bit LE: 0x00000023 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Store Byte: M[rs1 + imm] = rs2[7:0]") + ->example("sb a1, (#4, a0)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: SH rs2, imm(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00001023 (funct3=001 + opcode=0x23) + */ + insert( + mnem("sh", 4, + "\x23\x10\x00\x00", // pattern 32-bit LE: 0x00001023 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Store Halfword: M[rs1 + imm] = rs2[15:0]") + ->example("sh a1, (#4, a0)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: SW rs2, imm(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002023 (funct3=010 + opcode=0x23) + */ + insert( + mnem("sw", 4, + "\x23\x20\x00\x00", // pattern 32-bit LE: 0x00002023 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Store Word: M[rs1 + imm] = rs2[31:0]") + ->example("sw a1, (#4, a0)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* System Instructions */ + + /* Memory Ordering Instructions (RV32I Base) */ + + /* + * Example: FENCE pred, succ + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x0000000F (funct3=000 + opcode=0x0F) + * + * pred[3:0] in imm[3:0] (bits [23:20]) + * succ[3:0] in imm[7:4] (bits [27:24]) + * rs1 and rd are typically zero but can be non-zero + */ + // Simple fence (no arguments) - defaults to fence iorw, iorw (full barrier) + // Encoding: 0x0FF0000F - pred=1111, succ=1111, rs1=x0, rd=x0 + insert( + mnem("fence", 4, + "\x0F\x00\xF0\x0F", // pattern 32-bit LE: 0x0FF0000F (fence iorw, iorw) + "\xFF\xFF\xFF\xFF")) // exact match - no variable bits + ->help("Memory Ordering Fence (full barrier): fence iorw, iorw") + ->example("fence"); + + // Fence with explicit pred/succ and registers + insert( + mnem("fence", 4, + "\x0F\x00\x00\x00", // pattern 32-bit LE: 0x0000000F + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Memory Ordering Fence: orders memory operations") + ->example("fence #0xFF, zero, zero") + ->insert(new GAParameterRiscvFencePredSucc("\x00\x00\xF0\x0F")) // pred/succ in imm[7:0] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] (typically zero) + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] (typically zero) + + /* + * Example: FENCE.I + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x0000100F (funct3=001 + opcode=0x0F) + * + * All fields except funct3 and opcode are zero + */ + insert( + mnem("fence.i", 4, + "\x0F\x10\x00\x00", // pattern 32-bit LE: 0x0000100F + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Instruction Fence: synchronizes instruction and data streams") + ->example("fence.i"); + + /* Environment Call and Breakpoints */ + + /* + * Example: ECALL + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00000073 (funct3=000 + opcode=0x73) + * + * All fields except funct3 and opcode are zero + * Note: imm[0]=0, so no mask needed for byte 2 (unlike EBREAK) + */ + insert( + mnem("ecall", 4, + "\x73\x00\x00\x00", // pattern 32-bit LE: 0x00000073 + "\x7F\x70\x10\x00")) // mask: opcode + funct3 + imm[0] (bit 20 = byte 2 bit 4, must be 0) + ->help("Environment Call: makes a request to the execution environment") + ->example("ecall"); + + /* + * Example: EBREAK + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00100073 (funct3=000 + opcode=0x73 + imm[0]=1) + * + * imm[0]=1 (bit 20), all other fields except funct3 and opcode are zero + */ + insert( + mnem("ebreak", 4, + "\x73\x00\x10\x00", // pattern 32-bit LE: 0x00100073 (imm[0]=1 in bit 20) + "\x7F\x70\x10\x00")) // mask: opcode + funct3 + imm[0] (bit 20 = byte 2 bit 4) + ->help("Environment Break: causes a breakpoint exception") + ->example("ebreak"); + + /* M Extension Instructions */ + + /* + * Example: MUL rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02000033 (funct7=0x01, funct3=000 + opcode=0x33) + */ + insert( + mnem("mul", 4, + "\x33\x00\x00\x02", // pattern 32-bit LE: 0x02000033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Multiply: rd = (rs1 * rs2)[XLEN-1:0] (lower XLEN bits)") + ->example("mul a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: MULH rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02001033 (funct7=0x01, funct3=001 + opcode=0x33) + */ + insert( + mnem("mulh", 4, + "\x33\x10\x00\x02", // pattern 32-bit LE: 0x02001033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Multiply High (signed × signed): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") + ->example("mulh a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: MULHSU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02002033 (funct7=0x01, funct3=010 + opcode=0x33) + */ + insert( + mnem("mulhsu", 4, + "\x33\x20\x00\x02", // pattern 32-bit LE: 0x02002033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Multiply High (signed × unsigned): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") + ->example("mulhsu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: MULHU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02003033 (funct7=0x01, funct3=011 + opcode=0x33) + */ + insert( + mnem("mulhu", 4, + "\x33\x30\x00\x02", // pattern 32-bit LE: 0x02003033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Multiply High (unsigned × unsigned): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") + ->example("mulhu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: DIV rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02004033 (funct7=0x01, funct3=100 + opcode=0x33) + */ + insert( + mnem("div", 4, + "\x33\x40\x00\x02", // pattern 32-bit LE: 0x02004033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Divide (signed): rd = rs1 / rs2") + ->example("div a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: DIVU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02005033 (funct7=0x01, funct3=101 + opcode=0x33) + */ + insert( + mnem("divu", 4, + "\x33\x50\x00\x02", // pattern 32-bit LE: 0x02005033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Divide (unsigned): rd = rs1 / rs2") + ->example("divu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: REM rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02006033 (funct7=0x01, funct3=110 + opcode=0x33) + */ + insert( + mnem("rem", 4, + "\x33\x60\x00\x02", // pattern 32-bit LE: 0x02006033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Remainder (signed): rd = rs1 % rs2") + ->example("rem a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* + * Example: REMU rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02007033 (funct7=0x01, funct3=111 + opcode=0x33) + */ + insert( + mnem("remu", 4, + "\x33\x70\x00\x02", // pattern 32-bit LE: 0x02007033 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Remainder (unsigned): rd = rs1 % rs2") + ->example("remu a0, a1, a2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) + + /* Atomic Memory Instructions Extension (RV32A) */ + + /* + * Example: LR.W rd, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode, rs2 must be 0) + * Value : 0x1000202F (funct5=00010, aq=0, rl=0, rs2=00000, funct3=010, opcode=0x2F) + * + * funct5[4:0] = 00010 (0x02) in bits [31:27] + * aq = 0 in bit [26] + * rl = 0 in bit [25] + * rs2 = 00000 (reserved, must be zero) in bits [24:20] + */ + insert( + mnem("lr.w", 4, + "\x2F\x20\x00\x10", // pattern 32-bit LE: 0x1000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 (aq/rl default to 0) + ->help("Load Reserved Word: rd = M[rs1]; reserve address") + ->example("lr.w a0, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: SC.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x1800202F (funct5=00011, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("sc.w", 4, + "\x2F\x20\x00\x18", // pattern 32-bit LE: 0x1800202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Store Conditional Word: if reserved, M[rs1] = rs2, rd = 0; else rd != 0") + ->example("sc.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOSWAP.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x0800202F (funct5=00001, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoswap.w", 4, + "\x2F\x20\x00\x08", // pattern 32-bit LE: 0x0800202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Swap Word: temp = M[rs1]; M[rs1] = rs2; rd = temp") + ->example("amoswap.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOADD.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x0000202F (funct5=00000, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoadd.w", 4, + "\x2F\x20\x00\x00", // pattern 32-bit LE: 0x0000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Add Word: temp = M[rs1]; M[rs1] = temp + rs2; rd = temp") + ->example("amoadd.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOXOR.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x2000202F (funct5=00100, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoxor.w", 4, + "\x2F\x20\x00\x20", // pattern 32-bit LE: 0x2000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory XOR Word: temp = M[rs1]; M[rs1] = temp ^ rs2; rd = temp") + ->example("amoxor.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOAND.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x6000202F (funct5=01100, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoand.w", 4, + "\x2F\x20\x00\x60", // pattern 32-bit LE: 0x6000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory AND Word: temp = M[rs1]; M[rs1] = temp & rs2; rd = temp") + ->example("amoand.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOOR.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x4000202F (funct5=01000, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amoor.w", 4, + "\x2F\x20\x00\x40", // pattern 32-bit LE: 0x4000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory OR Word: temp = M[rs1]; M[rs1] = temp | rs2; rd = temp") + ->example("amoor.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOMIN.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0x8000202F (funct5=10000, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amomin.w", 4, + "\x2F\x20\x00\x80", // pattern 32-bit LE: 0x8000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Minimum Word (signed): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp") + ->example("amomin.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOMAX.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0xA000202F (funct5=10100, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amomax.w", 4, + "\x2F\x20\x00\xA0", // pattern 32-bit LE: 0xA000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Maximum Word (signed): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp") + ->example("amomax.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOMINU.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0xC000202F (funct5=11000, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amominu.w", 4, + "\x2F\x20\x00\xC0", // pattern 32-bit LE: 0xC000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Minimum Word (unsigned): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp") + ->example("amominu.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: AMOMAXU.W rd, rs2, (rs1) + * + * Encoding: + * funct5 aq rl rs2 rs1 funct3 rd opcode + * + * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) + * Value : 0xE000202F (funct5=11100, aq=0, rl=0, funct3=010, opcode=0x2F) + */ + insert( + mnem("amomaxu.w", 4, + "\x2F\x20\x00\xE0", // pattern 32-bit LE: 0xE000202F + "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 + ->help("Atomic Memory Maximum Word (unsigned): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp") + ->example("amomaxu.w a0, a2, (a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* ZICSR Instructions Extension */ + + /* + * Example: CSRRW rd, csr, rs1 + * + * Encoding: + * csr[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00001073 (funct3=001 + opcode=0x73) + * + * Atomic Read/Write CSR: rd = CSR; CSR = rs1 + */ + insert( + mnem("csrrw", 4, + "\x73\x10\x00\x00", // pattern 32-bit LE: 0x00001073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read/Write: rd = CSR; CSR = rs1") + ->example("csrrw a0, #0x300, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: CSRRS rd, csr, rs1 + * + * Encoding: + * csr[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002073 (funct3=010 + opcode=0x73) + * + * Atomic Read and Set Bits in CSR: rd = CSR; CSR = CSR | rs1 + */ + insert( + mnem("csrrs", 4, + "\x73\x20\x00\x00", // pattern 32-bit LE: 0x00002073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read and Set Bits: rd = CSR; CSR = CSR | rs1") + ->example("csrrs a0, #0x300, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: CSRRC rd, csr, rs1 + * + * Encoding: + * csr[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00003073 (funct3=011 + opcode=0x73) + * + * Atomic Read and Clear Bits in CSR: rd = CSR; CSR = CSR & ~rs1 + */ + insert( + mnem("csrrc", 4, + "\x73\x30\x00\x00", // pattern 32-bit LE: 0x00003073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read and Clear Bits: rd = CSR; CSR = CSR & ~rs1") + ->example("csrrc a0, #0x300, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: CSRRWI rd, csr, uimm5 + * + * Encoding: + * csr[11:0] uimm[4:0] funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00005073 (funct3=101 + opcode=0x73) + * + * Atomic Read/Write CSR Immediate: rd = CSR; CSR = uimm[4:0] + */ + insert( + mnem("csrrwi", 4, + "\x73\x50\x00\x00", // pattern 32-bit LE: 0x00005073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read/Write Immediate: rd = CSR; CSR = uimm[4:0]") + ->example("csrrwi a0, #0x300, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] + + /* + * Example: CSRRSI rd, csr, uimm5 + * + * Encoding: + * csr[11:0] uimm[4:0] funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00006073 (funct3=110 + opcode=0x73) + * + * Atomic Read and Set Bits in CSR Immediate: rd = CSR; CSR = CSR | uimm[4:0] + */ + insert( + mnem("csrrsi", 4, + "\x73\x60\x00\x00", // pattern 32-bit LE: 0x00006073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read and Set Bits Immediate: rd = CSR; CSR = CSR | uimm[4:0]") + ->example("csrrsi a0, #0x300, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] + + /* + * Example: CSRRCI rd, csr, uimm5 + * + * Encoding: + * csr[11:0] uimm[4:0] funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00007073 (funct3=111 + opcode=0x73) + * + * Atomic Read and Clear Bits in CSR Immediate: rd = CSR; CSR = CSR & ~uimm[4:0] + */ + insert( + mnem("csrrci", 4, + "\x73\x70\x00\x00", // pattern 32-bit LE: 0x00007073 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("CSR Read and Clear Bits Immediate: rd = CSR; CSR = CSR & ~uimm[4:0]") + ->example("csrrci a0, #0x300, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] + ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] + + /* F Extension Instructions */ + + /* + * Example: FLW rd, imm12(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002007 (funct3=010 + opcode=0x07) + */ + insert( + mnem("flw", 4, + "\x07\x20\x00\x00", // pattern 32-bit LE: 0x00002007 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Floating-Point Load Word: rd = M[rs1 + imm12]") + ->example("flw f0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0]: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FSW rs2, imm12(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00002027 (funct3=010 + opcode=0x27) + */ + insert( + mnem("fsw", 4, + "\x27\x20\x00\x00", // pattern 32-bit LE: 0x00002027 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Floating-Point Store Word: M[rs1 + imm12] = rs2") + ->example("fsw f0, (#4, a1)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x00\x00\xF0\xFE")) // imm[11:0]: split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FMADD.S rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x00000043 (funct2=00, funct3=000 + opcode=0x43) + */ + insert( + mnem("fmadd.s", 4, + "\x43\x00\x00\x00", // pattern 32-bit LE: 0x00000043 + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Fused Multiply-Add: rd = rs1 * rs2 + rs3") + ->example("fmadd.s f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] + + /* + * Example: FMSUB.S rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x00000047 (funct2=00, funct3=000 + opcode=0x47) + */ + insert( + mnem("fmsub.s", 4, + "\x47\x00\x00\x00", // pattern 32-bit LE: 0x00000047 + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Fused Multiply-Subtract: rd = rs1 * rs2 - rs3") + ->example("fmsub.s f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] + + /* + * Example: FNMSUB.S rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x0000004B (funct2=00, funct3=000 + opcode=0x4B) + */ + insert( + mnem("fnmsub.s", 4, + "\x4B\x00\x00\x00", // pattern 32-bit LE: 0x0000004B + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Negative Fused Multiply-Subtract: rd = -(rs1 * rs2) + rs3") + ->example("fnmsub.s f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] + + /* + * Example: FNMADD.S rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x0000004F (funct2=00, funct3=000 + opcode=0x4F) + */ + insert( + mnem("fnmadd.s", 4, + "\x4F\x00\x00\x00", // pattern 32-bit LE: 0x0000004F + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Negative Fused Multiply-Add: rd = -(rs1 * rs2) - rs3") + ->example("fnmadd.s f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] + + /* + * Example: FADD.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x00000053 (funct7=0x00, funct3=000 + opcode=0x53) + */ + insert( + mnem("fadd.s", 4, + "\x53\x00\x00\x00", // pattern 32-bit LE: 0x00000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Add: rd = rs1 + rs2") + ->example("fadd.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FSUB.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x08000053 (funct7=0x08, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsub.s", 4, + "\x53\x00\x00\x08", // pattern 32-bit LE: 0x08000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Subtract: rd = rs1 - rs2") + ->example("fsub.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FMUL.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x10000053 (funct7=0x10, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmul.s", 4, + "\x53\x00\x00\x10", // pattern 32-bit LE: 0x10000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Multiply: rd = rs1 * rs2") + ->example("fmul.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FDIV.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x18000053 (funct7=0x18, funct3=000 + opcode=0x53) + */ + insert( + mnem("fdiv.s", 4, + "\x53\x00\x00\x18", // pattern 32-bit LE: 0x18000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Divide: rd = rs1 / rs2") + ->example("fdiv.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FSQRT.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0x58000053 (funct7=0x2C, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsqrt.s", 4, + "\x53\x00\x00\x58", // pattern 32-bit LE: 0x58000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Square Root: rd = sqrt(rs1)") + ->example("fsqrt.s f0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FSGNJ.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x20000053 (funct7=0x20, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsgnj.s", 4, + "\x53\x00\x00\x20", // pattern 32-bit LE: 0x20000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection: rd = {rs2[31], rs1[30:0]}") + ->example("fsgnj.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FSGNJN.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x20001053 (funct7=0x20, funct3=001 + opcode=0x53) + */ + insert( + mnem("fsgnjn.s", 4, + "\x53\x10\x00\x20", // pattern 32-bit LE: 0x20001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection Negative: rd = {~rs2[31], rs1[30:0]}") + ->example("fsgnjn.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FSGNJX.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x20002053 (funct7=0x20, funct3=010 + opcode=0x53) + */ + insert( + mnem("fsgnjx.s", 4, + "\x53\x20\x00\x20", // pattern 32-bit LE: 0x20002053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection XOR: rd = {rs2[31]^rs1[31], rs1[30:0]}") + ->example("fsgnjx.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FMIN.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x28000053 (funct7=0x28, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmin.s", 4, + "\x53\x00\x00\x28", // pattern 32-bit LE: 0x28000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Minimum: rd = min(rs1, rs2)") + ->example("fmin.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FMAX.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x28001053 (funct7=0x28, funct3=001 + opcode=0x53) + */ + insert( + mnem("fmax.s", 4, + "\x53\x10\x00\x28", // pattern 32-bit LE: 0x28001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Maximum: rd = max(rs1, rs2)") + ->example("fmax.s f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FEQ.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA0002053 (funct7=0x50, funct3=010 + opcode=0x53) + */ + insert( + mnem("feq.s", 4, + "\x53\x20\x00\xA0", // pattern 32-bit LE: 0xA0002053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Equal Compare: rd = (rs1 == rs2) ? 1 : 0") + ->example("feq.s a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FLT.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA0001053 (funct7=0x50, funct3=001 + opcode=0x53) + */ + insert( + mnem("flt.s", 4, + "\x53\x10\x00\xA0", // pattern 32-bit LE: 0xA0001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Less Than Compare: rd = (rs1 < rs2) ? 1 : 0") + ->example("flt.s a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FLE.S rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA0000053 (funct7=0x50, funct3=000 + opcode=0x53) + */ + insert( + mnem("fle.s", 4, + "\x53\x00\x00\xA0", // pattern 32-bit LE: 0xA0000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Less Than or Equal Compare: rd = (rs1 <= rs2) ? 1 : 0") + ->example("fle.s a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + + /* + * Example: FCVT.W.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xC0000053 (funct7=0x60, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.w.s", 4, + "\x53\x00\x00\xC0", // pattern 32-bit LE: 0xC0000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert to Word: rd = (int32_t)rs1") + ->example("fcvt.w.s a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.WU.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xC0001053 (funct7=0x60, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.wu.s", 4, + "\x53\x10\x00\xC0", // pattern 32-bit LE: 0xC0001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert to Word Unsigned: rd = (uint32_t)rs1") + ->example("fcvt.wu.s a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.S.W rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xD0000053 (funct7=0x68, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.s.w", 4, + "\x53\x00\x00\xD0", // pattern 32-bit LE: 0xD0000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert from Word: rd = (float)rs1") + ->example("fcvt.s.w f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.S.WU rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xD0001053 (funct7=0x68, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.s.wu", 4, + "\x53\x10\x00\xD0", // pattern 32-bit LE: 0xD0001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert from Word Unsigned: rd = (float)(uint32_t)rs1") + ->example("fcvt.s.wu f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FMV.X.W rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xE0000053 (funct7=0x70, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmv.x.w", 4, + "\x53\x00\x00\xE0", // pattern 32-bit LE: 0xE0000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Move to Integer: rd = rs1 (bitwise copy)") + ->example("fmv.x.w a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FMV.W.X rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xF0000053 (funct7=0x78, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmv.w.x", 4, + "\x53\x00\x00\xF0", // pattern 32-bit LE: 0xF0000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Move from Integer: rd = rs1 (bitwise copy)") + ->example("fmv.w.x f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCLASS.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xE0001053 (funct7=0x70, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fclass.s", 4, + "\x53\x10\x00\xE0", // pattern 32-bit LE: 0xE0001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Classify: rd = classification bits for rs1") + ->example("fclass.s a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* D Extension Instructions (Double-Precision Floating-Point) */ + + /* + * Example: FLD rd, imm12(rs1) + * + * Encoding: + * imm[11:0] rs1 funct3 rd opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00003007 (funct3=011 + opcode=0x07) + */ + insert( + mnem("fld", 4, + "\x07\x30\x00\x00", // pattern 32-bit LE: 0x00003007 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Floating-Point Load Double: rd = M[rs1 + imm12]") + ->example("fld f0, (#8, a1)") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0]: bits [31:20] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FSD rs2, imm12(rs1) + * + * Encoding: + * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode + * + * Mask : 0x0000707F (mask funct3 + opcode) + * Value : 0x00003027 (funct3=011 + opcode=0x27) + */ + insert( + mnem("fsd", 4, + "\x27\x30\x00\x00", // pattern 32-bit LE: 0x00003027 + "\x7F\x70\x00\x00")) // mask: opcode + funct3 + ->help("Floating-Point Store Double: M[rs1 + imm12] = rs2") + ->example("fsd f0, (#8, a1)") + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] + ->group('(') // (rs1) group + ->insert(new GAParameterRiscvStypeImm12("\x00\x00\xF0\xFE")) // imm[11:0]: split encoding + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FMADD.D rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x04000043 (funct2=01, funct3=000 + opcode=0x43) + */ + insert( + mnem("fmadd.d", 4, + "\x43\x00\x00\x04", // pattern 32-bit LE: 0x04000043 + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Fused Multiply-Add Double: rd = rs1 * rs2 + rs3") + ->example("fmadd.d f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] + + /* + * Example: FMSUB.D rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x04000047 (funct2=01, funct3=000 + opcode=0x47) + */ + insert( + mnem("fmsub.d", 4, + "\x47\x00\x00\x04", // pattern 32-bit LE: 0x04000047 + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Fused Multiply-Subtract Double: rd = rs1 * rs2 - rs3") + ->example("fmsub.d f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] + + /* + * Example: FNMSUB.D rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x0400004B (funct2=01, funct3=000 + opcode=0x4B) + */ + insert( + mnem("fnmsub.d", 4, + "\x4B\x00\x00\x04", // pattern 32-bit LE: 0x0400004B + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Negative Fused Multiply-Subtract Double: rd = -(rs1 * rs2) + rs3") + ->example("fnmsub.d f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] + + /* + * Example: FNMADD.D rd, rs1, rs2, rs3 + * + * Encoding: + * rs3 funct2 rs2 rs1 funct3 rd opcode + * + * Mask : 0x6000707F (mask funct2 + funct3 + opcode) + * Value : 0x0400004F (funct2=01, funct3=000 + opcode=0x4F) + */ + insert( + mnem("fnmadd.d", 4, + "\x4F\x00\x00\x04", // pattern 32-bit LE: 0x0400004F + "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 + ->help("Floating-Point Negative Fused Multiply-Add Double: rd = -(rs1 * rs2) - rs3") + ->example("fnmadd.d f0, f1, f2, f3") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] + ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] + + /* + * Example: FADD.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x02000053 (funct7=0x01, funct3=000 + opcode=0x53) + */ + insert( + mnem("fadd.d", 4, + "\x53\x00\x00\x02", // pattern 32-bit LE: 0x02000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Add Double: rd = rs1 + rs2") + ->example("fadd.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FSUB.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x0A000053 (funct7=0x05, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsub.d", 4, + "\x53\x00\x00\x0A", // pattern 32-bit LE: 0x0A000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Subtract Double: rd = rs1 - rs2") + ->example("fsub.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FMUL.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x12000053 (funct7=0x09, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmul.d", 4, + "\x53\x00\x00\x12", // pattern 32-bit LE: 0x12000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Multiply Double: rd = rs1 * rs2") + ->example("fmul.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FDIV.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x1A000053 (funct7=0x0D, funct3=000 + opcode=0x53) + */ + insert( + mnem("fdiv.d", 4, + "\x53\x00\x00\x1A", // pattern 32-bit LE: 0x1A000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Divide Double: rd = rs1 / rs2") + ->example("fdiv.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FSQRT.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0x5A000053 (funct7=0x2D, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsqrt.d", 4, + "\x53\x00\x00\x5A", // pattern 32-bit LE: 0x5A000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Square Root Double: rd = sqrt(rs1)") + ->example("fsqrt.d f0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FSGNJ.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x22000053 (funct7=0x11, funct3=000 + opcode=0x53) + */ + insert( + mnem("fsgnj.d", 4, + "\x53\x00\x00\x22", // pattern 32-bit LE: 0x22000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection Double: rd = {rs2[63], rs1[62:0]}") + ->example("fsgnj.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FSGNJN.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x22001053 (funct7=0x11, funct3=001 + opcode=0x53) + */ + insert( + mnem("fsgnjn.d", 4, + "\x53\x10\x00\x22", // pattern 32-bit LE: 0x22001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection Negative Double: rd = {~rs2[63], rs1[62:0]}") + ->example("fsgnjn.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FSGNJX.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x22002053 (funct7=0x11, funct3=010 + opcode=0x53) + */ + insert( + mnem("fsgnjx.d", 4, + "\x53\x20\x00\x22", // pattern 32-bit LE: 0x22002053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Sign Injection XOR Double: rd = {rs2[63]^rs1[63], rs1[62:0]}") + ->example("fsgnjx.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FMIN.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x2A000053 (funct7=0x15, funct3=000 + opcode=0x53) + */ + insert( + mnem("fmin.d", 4, + "\x53\x00\x00\x2A", // pattern 32-bit LE: 0x2A000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Minimum Double: rd = min(rs1, rs2)") + ->example("fmin.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FMAX.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0x2A001053 (funct7=0x15, funct3=001 + opcode=0x53) + */ + insert( + mnem("fmax.d", 4, + "\x53\x10\x00\x2A", // pattern 32-bit LE: 0x2A001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Maximum Double: rd = max(rs1, rs2)") + ->example("fmax.d f0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FCVT.S.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0x40000053 (funct7=0x20, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.s.d", 4, + "\x53\x00\x00\x40", // pattern 32-bit LE: 0x40000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert Single from Double: rd = (float)rs1") + ->example("fcvt.s.d f0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.D.S rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0x42000053 (funct7=0x21, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.d.s", 4, + "\x53\x00\x00\x42", // pattern 32-bit LE: 0x42000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert Double from Single: rd = (double)rs1") + ->example("fcvt.d.s f0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FEQ.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA2002053 (funct7=0x51, funct3=010 + opcode=0x53) + */ + insert( + mnem("feq.d", 4, + "\x53\x20\x00\xA2", // pattern 32-bit LE: 0xA2002053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Equal Compare Double: rd = (rs1 == rs2) ? 1 : 0") + ->example("feq.d a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FLT.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA2001053 (funct7=0x51, funct3=001 + opcode=0x53) + */ + insert( + mnem("flt.d", 4, + "\x53\x10\x00\xA2", // pattern 32-bit LE: 0xA2001053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Less Than Compare Double: rd = (rs1 < rs2) ? 1 : 0") + ->example("flt.d a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FLE.D rd, rs1, rs2 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) + * Value : 0xA2000053 (funct7=0x51, funct3=000 + opcode=0x53) + */ + insert( + mnem("fle.d", 4, + "\x53\x00\x00\xA2", // pattern 32-bit LE: 0xA2000053 + "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 + ->help("Floating-Point Less Than or Equal Compare Double: rd = (rs1 <= rs2) ? 1 : 0") + ->example("fle.d a0, f1, f2") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] + ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + + /* + * Example: FCVT.W.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xC2000053 (funct7=0x61, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.w.d", 4, + "\x53\x00\x00\xC2", // pattern 32-bit LE: 0xC2000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert to Word from Double: rd = (int32_t)rs1") + ->example("fcvt.w.d a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.WU.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xC2001053 (funct7=0x61, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.wu.d", 4, + "\x53\x10\x00\xC2", // pattern 32-bit LE: 0xC2001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert to Word Unsigned from Double: rd = (uint32_t)rs1") + ->example("fcvt.wu.d a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.D.W rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xD2000053 (funct7=0x69, rs2=0, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.d.w", 4, + "\x53\x00\x00\xD2", // pattern 32-bit LE: 0xD2000053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert from Word to Double: rd = (double)rs1") + ->example("fcvt.d.w f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCVT.D.WU rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xD2001053 (funct7=0x69, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fcvt.d.wu", 4, + "\x53\x10\x00\xD2", // pattern 32-bit LE: 0xD2001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Convert from Word Unsigned to Double: rd = (double)(uint32_t)rs1") + ->example("fcvt.d.wu f0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* + * Example: FCLASS.D rd, rs1 + * + * Encoding: + * funct7 rs2 rs1 funct3 rd opcode + * + * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) + * Value : 0xE2001053 (funct7=0x71, rs2=1, funct3=000 + opcode=0x53) + */ + insert( + mnem("fclass.d", 4, + "\x53\x10\x00\xE2", // pattern 32-bit LE: 0xE2001053 + "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + ->help("Floating-Point Classify Double: rd = classification bits for rs1") + ->example("fclass.d a0, f1") + ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + + /* C-Extension - Compressed Instructions (16-bit) */ + + // Quadrant 0 (opcode [1:0] = 00) + + /* + * C.ADDI4SPN - Add Immediate to Stack Pointer (4-byte aligned) + * Format: CIW + * Encoding: 000|imm[9:2]|rd'[4:2]|00 + * Opcode: 0x00 (bits [1:0] = 00, bits [15:13] = 000) + */ + insert( + mnem("c.addi4spn", 2, + "\x00\x00", // pattern 16-bit LE: bits [1:0]=00, [15:13]=000 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Add Immediate to SP: rd' = sp + (uimm << 2)") + ->example("c.addi4spn a0, #16") + ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rd': bits [4:2] in byte 0 + ->insert(new GAParameterRiscvCIWimm9("\xE0\x1F")); // imm[9:2]: bits [7:5] in byte 0, bits [4:0] in byte 1 = instruction bits [12:5] + + /* + * C.LW - Compressed Load Word + * Format: CL + * Encoding: 010|imm[5|4:3|8:6]|rs1'[2:0]|imm[2|6]|rd'[2:0]|00 + * Opcode: 0x4000 (bits [1:0] = 00, bits [15:13] = 010) + */ + insert( + mnem("c.lw", 2, + "\x00\x40", // pattern 16-bit LE: bits [1:0]=00, [15:13]=010 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Load Word: rd' = M[rs1' + (uimm << 2)][31:0]") + ->example("c.lw a0, (#4, a1)") + ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rd': bits [4:2] in byte 0 + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvCLimm5("\x60\x1C")) // imm[6:2]: imm[6] in bit 5, imm[2] in bit 6, imm[5:3] in bits [12:10] + ->insert(new GAParameterRiscvCompReg("\x80\x03")); // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + + /* + * C.SW - Compressed Store Word + * Format: CS + * Encoding: 110|imm[5|4:3|8:6]|rs1'[2:0]|imm[2|6]|rs2'[2:0]|00 + * Opcode: 0xC000 (bits [1:0] = 00, bits [15:13] = 110) + */ + insert( + mnem("c.sw", 2, + "\x00\xC0", // pattern 16-bit LE: bits [1:0]=00, [15:13]=110 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Store Word: M[rs1' + (uimm << 2)] = rs2'[31:0]") + ->example("c.sw a0, (#4, a1)") + ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rs2': bits [4:2] in byte 0 + ->group('(') // imm(rs1) group + ->insert(new GAParameterRiscvCSimm5("\x60\x1C")) // imm[6:2]: imm[6] in bit 5, imm[2] in bit 6, imm[5:3] in bits [12:10] + ->insert(new GAParameterRiscvCompReg("\x80\x03")); // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + + // Quadrant 1 (opcode [1:0] = 01) + + /* + * C.NOP - Compressed No Operation / C.ADDI + * Format: CI + * Encoding: 000|imm[5:0]|rd[4:0]|01 + * Opcode: 0x0001 (bits [1:0] = 01, bits [15:13] = 000, rd=0 for NOP) + * Note: Inserted before c.addi so it's checked first (more specific pattern with rd=0) + */ + insert( + mnem("c.nop", 2, + "\x01\x00", // pattern 16-bit LE: bits [1:0]=01, [15:13]=000, rd=0 + "\x83\xEF")) // mask: opcode + rd (byte0: bits [7] and [1:0]=0x83, byte1: bits [15:13] and [11:8]=0xEF) + ->help("Compressed No Operation") + ->example("c.nop"); + + /* + * C.ADDI - Compressed Add Immediate + * Format: CI + * Encoding: 000|imm[5:0]|rd[4:0]|01 + * Opcode: 0x0001 (bits [1:0] = 01, bits [15:13] = 000, rd != 0) + * Note: Uses rejectWhenZero to check rd != 0, eliminating collision with c.nop + */ + insert( + mnem("c.addi", 2, + "\x01\x00", // pattern 16-bit LE: bits [1:0]=01, [15:13]=000 + "\x03\xE0")) // mask: opcode bits only + ->rejectWhenZero("\x80\x0F") // rd (bits [11:7]) must be non-zero + ->help("Compressed Add Immediate: rd = rd + imm") + ->example("c.addi a0, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.LI - Compressed Load Immediate + * Format: CI + * Encoding: 010|imm[5:0]|rd[4:0]|01 + * Opcode: 0x4001 (bits [1:0] = 01, bits [15:13] = 010) + */ + insert( + mnem("c.li", 2, + "\x01\x40", // pattern 16-bit LE: bits [1:0]=01, [15:13]=010 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Load Immediate: rd = imm (rd != 0, rd != 2)") + ->example("c.li a0, #5") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.ADDI16SP - Compressed Add Immediate to SP (16-byte aligned) + * Format: CI + * Encoding: 011|imm[9|4|6|8:7|5]|01010|01 + * Opcode: 0x6101 (bits [1:0] = 01, bits [15:13] = 011, rd = 2 (sp)) + * Note: Pattern includes rd=2 (bits [11:7]=00010) to distinguish from c.lui + * rd[4:1]=0001 in bits [11:8], rd[0]=0 in bit [7] + * Inserted before c.lui so it's checked first (more specific pattern) + */ + insert( + mnem("c.addi16sp", 2, + "\x01\x61", // pattern 16-bit LE: bits [1:0]=01, [15:13]=011, rd=2 (bits [11:8]=0001, bit [7]=0) + "\x83\xEF")) // mask: opcode + rd (byte0: bits [7] and [1:0]=0x83, byte1: bits [15:13] and [11:8]=0xEF) + ->help("Compressed Add Immediate to SP: sp = sp + (imm << 4)") + ->example("c.addi16sp #-32") + ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[9|4|6|8:7|5]: split encoding (special format) - same mask as CI but different encoding logic + + /* + * C.LUI - Compressed Load Upper Immediate + * Format: CI + * Encoding: 011|imm[17:12]|rd[4:0]|01 + * Opcode: 0x6001 (bits [1:0] = 01, bits [15:13] = 011, rd != 0, rd != 2) + * Note: Inserted after c.addi16sp so c.addi16sp (more specific) is checked first + */ + insert( + mnem("c.lui", 2, + "\x01\x60", // pattern 16-bit LE: bits [1:0]=01, [15:13]=011 (rd != 0 and != 2 is checked in parameter decode to distinguish from c.addi16sp) + "\x03\xE0")) // mask: opcode only (rd != 0 and != 2 is checked in parameter decode to distinguish from c.addi16sp) + ->help("Compressed Load Upper Immediate: rd = (imm << 12)") + ->example("c.lui a0, #0x10000") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 (must be != 0 and != 2) + ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[17:12]: encoded in imm[5:0] position - same mask as CI but represents imm[17:12] + + /* + * C.SRAI - Compressed Shift Right Arithmetic Immediate + * Format: CB + * Encoding: 100|imm[5:0]|rd'[2:0]|01 + * Opcode: 0x8401 (bits [1:0] = 01, bits [15:13] = 100, bits [11:10] = 01) + * Note: C.SRAI is in quadrant 01, distinct from C.MV which is in quadrant 10 + */ + { + auto m = mnem("c.srai", 2, + "\x01\x84", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=01 (only fixed opcode bits) + "\x03\xEC"); // mask: bits [1:0] + [15:13] + [11:10] = 0x03 in byte 0, 0xEC in byte 1 (exclude bit [6] and [12] - they're data!) + m->help("Compressed Shift Right Arithmetic Immediate: rd' = rd' >> uimm (arithmetic)"); + m->example("c.srai a0, #3"); + m->insert(new GAParameterRiscvCompReg("\x80\x03")); // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + m->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 + insert(m); + } + + // Quadrant 2 (opcode [1:0] = 10) + + /* + * C.EBREAK - Compressed Environment Break + * Format: CR + * Encoding: 100|00000|00000|10 + * Opcode: 0x9002 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 001, rd=0, rs1=0) + * Note: Inserted first to ensure it's checked first (has most specific mask 0xFFFF) + */ + insert( + mnem("c.ebreak", 2, + "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=001, rd=0, rs1=0 + "\xFF\xFF")) // mask: all bits (0xFFFF) - c.ebreak is an exact encoding with rd=0, rs2=0 + // Removed priority - full mask 0xFFFF ensures c.ebreak matches only its exact encoding 0x9002 + ->help("Compressed Environment Break"); + + /* + * C.ANDI - Compressed AND Immediate + * Format: CB + * Encoding: 100|imm[5]|10|rd'[2:0]|imm[4:0]|01 + * Opcode: 0x8801 (bits [1:0] = 01, bits [15:13] = 100, bits [11:10] = 10) + * Note: bits [12] and [6:2] are part of immediate data, so they are NOT in the mask + */ + // Using standard mnemonic - c.andi is in quadrant 01 (bits[1:0]=01), + // distinct from c.jr/c.jalr which are in quadrant 10 (bits[1:0]=10) + // The mask already distinguishes them by checking bits[1:0] and bits[11:10]=10 + insert( + mnem("c.andi", 2, + "\x01\x88", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=10 + "\x03\xEC")) // mask: bits [1:0] in byte 0, bits [15:13] + [11:10] in byte 1 + ->help("Compressed AND Immediate: rd' = rd' & imm") + ->example("c.andi a0, #7") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCBimm6Andi("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.SRLI - Compressed Shift Right Logical Immediate + * Format: CB + * Encoding: 100|imm[5]|00|rd'[2:0]|imm[4:0]|01 + * Opcode: bits [1:0] = 01 (quadrant 1), bits [15:13] = 100, bits [11:10] = 00 + * Note: bit [12] is imm[5], bits [6:2] are imm[4:0] (parameters) + * Pattern: 0x8001 (bits [1:0]=01, [15:13]=100, [11:10]=00) + */ + // Using standard mnemonic - c.srli is in quadrant 01 (bits[1:0]=01), + // distinct from c.jr/c.jalr/c.mv which are in quadrant 10 (bits[1:0]=10) + // The mask checks bits[11:10]=00 to distinguish from c.srai (01) and c.andi (10) + insert( + mnem("c.srli", 2, + "\x01\x80", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=00 + "\x03\xEC")) // mask: bits [1:0] in byte 0, bits [15:13] + [11:10] in byte 1 + ->help("Compressed Shift Right Logical Immediate: rd' = rd' >> uimm") + ->example("c.srli a0, #3") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.JR - Compressed Jump Register + * Format: CR + * Encoding: 100|rs1[4:0]|00000|10 + * Opcode: bits [15:13] = 100, bits [12:10] = 000, bits [6:2] = 00000 (rd=0), bits [1:0] = 10 + * Note: [11:10] are part of rs1 register field, not opcode bits, so mask doesn't check them + * Note: rs1 must be non-zero (rs1=0 with rd=0 is reserved) + */ + insert( + mnem("c.jr", 2, + "\x02\x80", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12]=0 (funct4), [6:2]=00000 (rs2=0) + "\x7F\xF0")) // mask: bits [1:0] + [6:2] in byte 0 (0x7F), bits [15:12] in byte 1 (0xF0) + ->rejectWhenZero("\x80\x0F") // rs1 (bits [11:7]) must be non-zero + ->help("Compressed Jump Register: pc = rs1") + ->example("c.jr a0") + ->insert(new GAParameterRiscvReg("\x80\x0F")); // rs1: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + + /* + * C.JALR - Compressed Jump and Link Register + * Format: CR + * Encoding: 1001|rs1[4:0]|00000|10 + * Opcode: bits [15:12] = 1001 (funct4), bits [6:2] = 00000 (rs2=0), bits [1:0] = 10 + * Note: rd is implicitly ra (x1), rs1 must be non-zero (rs1=0 with rs2=0 is c.ebreak) + */ + insert( + mnem("c.jalr", 2, + "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1001 (funct4), [6:2]=00000 (rs2=0) + "\x7F\xF0")) // mask: bits [6:0] in byte 0 (check rs2=0, op=10), bits [15:12] in byte 1 (check funct4) + ->rejectWhenZero("\x80\x0F") // rs1 (bits [11:7]) must be non-zero + ->help("Compressed Jump and Link Register: ra = pc + 2; pc = rs1") + ->example("c.jalr a0") + ->insert(new GAParameterRiscvReg("\x80\x0F")); // rs1: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + + /* + * C.SUB - Compressed Subtract + * Format: CA + * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|00|10 + * Opcode: 0x8C02 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 00) + */ + insert( + mnem("c.sub", 2, + "\x02\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=00 + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + // Removed priority - mask correctly checks [6:5]=00 to distinguish from other CA format instructions + ->help("Compressed Subtract: rd' = rd' - rs2'") + ->example("c.sub a0, a1") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 + + /* + * C.XOR - Compressed XOR + * Format: CA + * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|01|10 + * Opcode: 0x8C22 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 01) + */ + insert( + mnem("c.xor", 2, + "\x22\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=01 + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + // Removed priority - mask correctly checks [6:5]=01 to distinguish from other CA format instructions + ->help("Compressed XOR: rd' = rd' ^ rs2'") + ->example("c.xor a0, a1") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 + + /* + * C.OR - Compressed OR + * Format: CA + * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|10|10 + * Opcode: 0x8C42 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 10) + */ + insert( + mnem("c.or", 2, + "\x42\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=10 + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + // Removed priority - mask correctly checks [6:5]=10 to distinguish from other CA format instructions + ->help("Compressed OR: rd' = rd' | rs2'") + ->example("c.or a0, a1") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 + + /* + * C.AND - Compressed AND + * Format: CA + * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|11|10 + * Opcode: 0x8C62 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 11) + */ + insert( + mnem("c.and", 2, + "\x62\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=11 + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + // Removed priority - mask correctly checks [6:5]=11 to distinguish from other CA format instructions + ->help("Compressed AND: rd' = rd' & rs2'") + ->example("c.and a0, a1") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 + + /* + * C.J - Compressed Jump + * Format: CJ + * Encoding: 101|imm[11|4|9:8|10|6|7|3:1|5]|01 + * Opcode: 0xA001 (bits [1:0] = 01, bits [15:13] = 101) + */ + insert( + mnem("c.j", 2, + "\x01\xA0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=101 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Jump: pc = pc + imm") + ->example("c.j #8") + ->insert(new GAParameterRiscvCJimm12("\xFC\x1F")); // imm[11:1]: split encoding - bits [7:2] from byte 0, bits [12:8] from byte 1 + + /* + * C.BEQZ - Compressed Branch if Equal to Zero + * Format: CB + * Encoding: 110|imm[8|4:3|7:6|2:1|5]|rs1'[2:0]|01 + * Opcode: 0xC001 (bits [1:0] = 01, bits [15:13] = 110) + * Note: bits [9:7] contain rs1' (compressed register), not regular rs2 + * Note: Distinguished from c.swsp by op field: c.beqz has [1:0]=01, c.swsp has [1:0]=10 + */ + insert( + mnem("c.beqz", 2, + "\x01\xC0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=110 + "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 + ->help("Compressed Branch if Equal to Zero: if (rs1' == 0) pc = pc + imm") + ->example("c.beqz a0, #8") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCBimm9("\x7C\x1C")); // imm[8:1]: split encoding - bits [6:2] from byte 0, bits [12] and [11:10] from byte 1 + + /* + * C.BNEZ - Compressed Branch if Not Equal to Zero + * Format: CB + * Encoding: 111|imm[8|4:3|7:6|2:1|5]|rs1'[2:0]|01 + * Opcode: 0xE001 (bits [1:0] = 01, bits [15:13] = 111) + */ + insert( + mnem("c.bnez", 2, + "\x01\xE0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=111 + "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 + ->help("Compressed Branch if Not Equal to Zero: if (rs1' != 0) pc = pc + imm") + ->example("c.bnez a0, #8") + ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 + ->insert(new GAParameterRiscvCBimm9("\x7C\x1C")); // imm[8:1]: split encoding - bits [6:2] from byte 0, bits [12] and [11:10] from byte 1 + + // Quadrant 2 special instructions (rd != 0) + + /* + * C.SLLI - Compressed Shift Left Logical Immediate + * Format: CI + * Encoding: 000|imm[5:0]|rd[4:0]|10 + * Opcode: 0x0002 (bits [1:0] = 10, bits [15:13] = 000, rd != 0) + */ + insert( + mnem("c.slli", 2, + "\x02\x00", // pattern 16-bit LE: bits [1:0]=10, [15:13]=000 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Shift Left Logical Immediate: rd = rd << uimm") + ->example("c.slli a0, #3") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 + + /* + * C.LWSP - Compressed Load Word from Stack Pointer + * Format: CI + * Encoding: 010|imm[7:2]|rd[4:0]|10 + * Opcode: 0x4002 (bits [1:0] = 10, bits [15:13] = 010, rd != 0) + */ + insert( + mnem("c.lwsp", 2, + "\x02\x40", // pattern 16-bit LE: bits [1:0]=10, [15:13]=010 + "\x03\xE0")) // mask: opcode bits + ->help("Compressed Load Word from SP: rd = M[sp + (uimm << 2)][31:0]") + ->example("c.lwsp a0, #4") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvCIimm7("\x7C\x10")); // imm[7:2]: imm[5] in bit [12], imm[4:2] in bits [6:4], imm[7:6] in bits [3:2] + + /* + * C.MV - Compressed Move + * Format: CR + * Encoding: 1000|rs2[4:0]|rd[4:0]|10 + * Opcode: funct4 = 1000, so bits [15:12] = 1000, bits [1:0] = 10 + * Note: bit [12] = 0 distinguishes from c.add (funct4 = 1001, bit [12] = 1) + * Note: C.MV is in quadrant 10, distinct from C.SRAI which is in quadrant 01 + * Note: both rd != 0 and rs2 != 0 required (rs2=0 would be c.jr, rd=0 invalid) + */ + insert( + mnem("c.mv", 2, + "\x02\x80", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1000 (funct4) + "\x03\xF0")) // mask: bits [1:0] + [15:12] = 0x03 in byte 0, 0xF0 in byte 1 + ->rejectWhenZero("\x80\x0F") // rd (bits [11:7]) must be non-zero + ->rejectWhenZero("\x7C\x00") // rs2 (bits [6:2]) must be non-zero + ->help("Compressed Move: rd = rs2") + ->example("c.mv a0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvReg("\x7C\x00")); // rs2: bits [6:2] - bits [6:2] in byte 0 + + /* + * C.ADD - Compressed Add + * Format: CR + * Encoding: 100|rs2[4:0]/rs1[4:0]|rd[4:0]|10 + * Opcode: 0x9002 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 000, rd != 0, rd != 1) + */ + insert( + mnem("c.add", 2, + "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1001 (funct4), rd=0 (template) + "\x03\xF0")) // mask: bits [1:0] + [15:12] = 0x03 in byte 0, 0xF0 in byte 1 (don't check rd or rs2) + // Removed priority - c.ebreak (inserted before this) has more specific mask (0x03FF) and will match first + ->help("Compressed Add: rd = rd + rs2") + ->example("c.add a0, a1") + ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 + ->insert(new GAParameterRiscvReg("\x7C\x00")); // rs2: bits [6:2] - bits [6:2] in byte 0 + + /* + * C.SWSP - Compressed Store Word to Stack Pointer + * Format: CSS + * Encoding: 110|imm[7:2]|rs2[4:0]|10 + * Opcode: 0xC002 (bits [1:0] = 10, bits [15:13] = 110) + * Note: bits [6:2] contain regular rs2 register, not compressed rs1' + * Note: Distinguished from c.beqz by op field: c.swsp has [1:0]=10, c.beqz has [1:0]=01 + */ + insert( + mnem("c.swsp", 2, + "\x02\xC0", // pattern 16-bit LE: bits [1:0]=10, [15:13]=110 + "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 + ->help("Compressed Store Word to SP: M[sp + (uimm << 2)] = rs2[31:0]") + ->example("c.swsp a0, #4") + ->insert(new GAParameterRiscvReg("\x7C\x00")) // rs2: bits [6:2] - bits [6:2] in byte 0 + ->insert(new GAParameterRiscvCSSimm7("\x80\x1F")); // imm[7:2]: bits [12:7] - bit [7] from byte 0, bits [12:8] from byte 1 +} + +/* RISC-V Parameter Types */ + +// RISC-V Reg Parameter + +GAParameterRiscvReg::GAParameterRiscvReg(const char* mask){ + setMask(mask); +} + +int GAParameterRiscvReg::match(GAParserOperand *op, int len){ + if(op->prefix!=this->prefix) + return 0; + + // Check if it is a valid RISC-V register name. + QString name = op->value; + if(name == "zero" || name == "ra" || name == "sp" || name == "gp" || name == "tp" || + name == "t0" || name == "t1" || name == "t2" || + name == "s0" || name == "s1" || + name == "a0" || name == "a1" || name == "a2" || name == "a3" || + name == "a4" || name == "a5" || name == "a6" || name == "a7" || + name == "s2" || name == "s3" || name == "s4" || name == "s5" || + name == "s6" || name == "s7" || name == "s8" || name == "s9" || + name == "s10" || name == "s11" || + name == "t3" || name == "t4" || name == "t5" || name == "t6" || + // Floating point registers f0-f31 + name == "f0" || name == "f1" || name == "f2" || name == "f3" || + name == "f4" || name == "f5" || name == "f6" || name == "f7" || + name == "f8" || name == "f9" || name == "f10" || name == "f11" || + name == "f12" || name == "f13" || name == "f14" || name == "f15" || + name == "f16" || name == "f17" || name == "f18" || name == "f19" || + name == "f20" || name == "f21" || name == "f22" || name == "f23" || + name == "f24" || name == "f25" || name == "f26" || name == "f27" || + name == "f28" || name == "f29" || name == "f30" || name == "f31") { + return 1; + } + return 0; +} + +QString GAParameterRiscvReg::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t regnum = rawdecode(lang, adr, bytes, inslen); + // Clamp register number to valid range (0-31 for both integer and floating point) + if(regnum > 31) { + return QString::asprintf("r%llu", (unsigned long long) regnum); + } + + // Check if this is a C-Extension instruction (16-bit, mask "\x80\x0F" for bits [11:7]) + // For 16-bit instructions, mask is 2 bytes; for 32-bit, it's 4 bytes + bool isCExtension = (inslen == 2 && (unsigned char)mask[0] == 0x80 && (unsigned char)mask[1] == 0x0F); + + // Determine which register field this is by checking the mask + // For 32-bit instructions: + // RD: bits [11:7] - mask "\x80\x0F\x00\x00" + // RS1: bits [19:15] - mask "\x00\x80\x0F\x00" + // RS2: bits [24:20] - mask "\x00\x00\xF0\x01" or "\x00\x00\xF0\x1F" + // RS3: bits [31:27] - mask "\x00\x00\x00\xF8" + // For 16-bit C-Extension: + // RD/RS1/RS2: bits [11:7] - mask "\x80\x0F" + bool isRD = false; + bool isRS1 = false; + bool isRS2 = false; + bool isRS3 = false; + + if(isCExtension) { + // For C-Extension, bits [11:7] can be RD, RS1, or RS2 depending on instruction + // We can't determine from mask alone, so assume it's RD (most common) + isRD = true; + } else { + isRD = ((unsigned char)mask[0] == 0x80 && (unsigned char)mask[1] == 0x0F && (unsigned char)mask[2] == 0x00 && (unsigned char)mask[3] == 0x00); + isRS1 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x80 && (unsigned char)mask[2] == 0x0F && (unsigned char)mask[3] == 0x00); + isRS2 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x00 && ((unsigned char)mask[2] == 0xF0) && ((unsigned char)mask[3] == 0x01 || (unsigned char)mask[3] == 0x1F)); + isRS3 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x00 && (unsigned char)mask[2] == 0x00 && (unsigned char)mask[3] == 0xF8); + } + + // Check instruction encoding to determine register type for F extension instructions + bool useFPReg = false; + if(inslen >= 4) { + uint8_t opcode = bytes[0] & 0x7F; // Opcode is in bits [6:0] of first byte + + if(opcode == 0x07 || opcode == 0x27) { + // FLW, FSW: rd/rs2 are FP, rs1 is integer (base address) + useFPReg = (isRD || isRS2); + } else if(opcode == 0x43 || opcode == 0x47 || opcode == 0x4B || opcode == 0x4F) { + // FMADD/FMSUB/FNMSUB/FNMADD: all registers are FP + useFPReg = true; + } else if(opcode == 0x53) { + // F extension arithmetic/comparison/conversion instructions + // Extract funct7 from byte 3 (bits [31:25] = byte 3 bits [7:1]) + // funct7 is 7 bits, so we shift right by 1 and mask with 0x7F + uint8_t funct7 = (bytes[3] >> 1) & 0x7F; + uint8_t funct3 = (bytes[1] >> 4) & 0x07; // funct3 is in bits [14:12] = byte 1 bits [6:4] + + if(funct7 == 0x60) { // fcvt.w.s, fcvt.wu.s + useFPReg = isRS1; // rs1 is FP, rd is integer + } else if(funct7 == 0x68) { // fcvt.s.w, fcvt.s.wu + useFPReg = isRD; // rd is FP, rs1 is integer + } else if(funct7 == 0x70) { // fmv.x.w, fclass.s + useFPReg = isRS1; // rs1 is FP, rd is integer + } else if(funct7 == 0x78) { // fmv.w.x + useFPReg = isRD; // rd is FP, rs1 is integer + } else if(funct7 == 0x50) { // feq.s, flt.s, fle.s + useFPReg = (isRS1 || isRS2); // rs1 and rs2 are FP, rd is integer + } else if(funct7 == 0x51) { // feq.d, flt.d, fle.d + useFPReg = (isRS1 || isRS2); // rs1 and rs2 are FP, rd is integer + } else if(funct7 == 0x61) { // fcvt.w.d, fcvt.wu.d + useFPReg = isRS1; // rs1 is FP, rd is integer + } else if(funct7 == 0x69) { // fcvt.d.w, fcvt.d.wu + useFPReg = isRD; // rd is FP, rs1 is integer + } else if(funct7 == 0x71) { // fclass.d + useFPReg = isRS1; // rs1 is FP, rd is integer + } else { + // All other F/D extension instructions: all registers are FP + useFPReg = true; + } + } + } + + // Use the determined register type + if(useFPReg && regnum + 32 < lang->regnames.size()) { + QString fpname = lang->regnames[regnum + 32]; + if(fpname.startsWith("f")) { + return fpname; + } + } + + // Prefer integer registers for non-FP or when useFPReg is false + if(regnum < 32 && regnum < lang->regnames.size()) { + QString intname = lang->regnames[regnum]; + // If it's not a floating point register name, use it + if(!intname.startsWith("f")) { + return intname; + } + } + + // Fallback to floating point register if integer register wasn't found + if(regnum + 32 < lang->regnames.size()) { + QString fpname = lang->regnames[regnum + 32]; + if(fpname.startsWith("f")) { + return fpname; + } + } + + // Final fallback + if(regnum < lang->regnames.size()) { + return lang->regnames[regnum]; + } + return QString::asprintf("r%llu", (unsigned long long) regnum); +} + +void GAParameterRiscvReg::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int regnum = lang->regnames.indexOf(op.value); + if(regnum == -1) { + op.goodasm->error("Unknown RISC-V register: " + op.value); + return; + } + // Floating point registers f0-f31 are at indices 32-63, but encode as 0-31 + if(regnum >= 32 && regnum < 64) { + regnum -= 32; + } + rawencode(lang, adr, bytes, op, inslen, regnum); +} + +// RISC-V Imm12 (imm[11:0]) parameter + +GAParameterRiscvImm12::GAParameterRiscvImm12(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvImm12::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); //False on a match, int64 handles negative prefix. + + // must fit signed 12-bit immediate + if (val < -2048 || val > 2047) { + op->goodasm->error("RISC-V imm12 is out of range (-2048 to 2047)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvImm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + int32_t val = (raw & 0x800) ? (raw | ~0xFFF) : (raw & 0xFFF); + // Format as hex if value is >= 0x10 or negative, otherwise decimal + if (val < 0 || (uint32_t)val >= 0x10) { + return prefix + QString::asprintf("0x%x", (uint32_t)val); + } + return prefix + QString::number(val); +} + +void GAParameterRiscvImm12::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -2048 || val > 2047) { + op.goodasm->error("RISC-V imm12 is out of range (-2048 to 2047)."); + return; + } + + rawencode(lang,adr,bytes,op,inslen,val); +} + +// RISC-V U-type Imm20 (imm[31:12]) parameter + +GAParameterRiscvUtypeImm20::GAParameterRiscvUtypeImm20(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvUtypeImm20::match(GAParserOperand *op, int len){ + // Try parsing as unsigned first, then signed if that fails + uint64_t val=op->uint64(false); // False on a match + + // If uint64 parsing failed, try int64 (for negative values, though U-type shouldn't have them) + if (val == (uint64_t)-1) { + int64_t sval = op->int64(false); + if (sval == -1) { + return 0; // Parsing failed, let other parameter types try + } + // If negative, reject (U-type immediates are unsigned) + if (sval < 0) { + return 0; + } + val = (uint64_t)sval; + } + + // U-type immediate: the value is the result value (what should be in rd) + // Must be <= 0xFFFFF000 and a multiple of 0x1000 (lower 12 bits must be zero) + + // Check if value is out of range + if (val > 0xFFFFF000) { + op->goodasm->error("RISC-V U-type instruction imm20 is out of range (0 to 0xFFFFF000, must be multiple of 0x1000)"); + return 0; + } + + // Check if value is a multiple of 0x1000 + if ((val & 0xFFF) != 0) { + op->goodasm->error("RISC-V U-type instruction imm20 must be a multiple of 0x1000 (lower 12 bits must be zero)"); + return 0; + } + + return 1; // valid value +} + +QString GAParameterRiscvUtypeImm20::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode extracts bits [31:12] which is the immediate field + // lui sets rd = imm[31:12] << 12, so we need to left-shift to show the result value + uint32_t imm_field = raw & 0xFFFFF; + uint64_t result = ((uint64_t)imm_field) << 12; + return prefix + QString::asprintf("0x%llx", (unsigned long long)result); +} + +void GAParameterRiscvUtypeImm20::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + uint32_t imm_field; + + // lui/auipc: rd = imm[31:12] << 12 + // The immediate value provided is the result value (what should be in rd) + // Extract the immediate field: imm[31:12] = val >> 12 + + // Check if value is out of range (max 32-bit value with lower 12 bits zero) + if (val > 0xFFFFF000) { + op.goodasm->error("RISC-V U-type imm20 is out of range (0 to 0xFFFFF000, must be multiple of 0x1000)."); + return; + } + + // Check if value is a multiple of 0x1000 (lower 12 bits must be zero) + if ((val & 0xFFF) != 0) { + op.goodasm->error("RISC-V U-type imm20 must be a multiple of 0x1000 (lower 12 bits must be zero)."); + return; + } + + // Right-shift by 12 to get the immediate field value that goes in bits [31:12] + imm_field = (val >> 12) & 0xFFFFF; + + rawencode(lang,adr,bytes,op,inslen,imm_field); +} + +// RISC-V B-type Imm13 (imm[12:1]) parameter +// Encoding: imm[12] in bit [31], imm[11] in bit [7], imm[10:5] in bits [30:25], imm[4:1] in bits [11:8] +// Mask: "\x80\x8F\xF0\xBF" - combined from: imm[12] (0x80 in byte 3), imm[11] (0x80 in byte 1), imm[10:5] (0xF0 in byte 2, 0x3F in byte 3), imm[4:1] (0x0F in byte 1) + +GAParameterRiscvBtypeImm13::GAParameterRiscvBtypeImm13(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvBtypeImm13::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); // False on a match + + // must fit signed 13-bit immediate, and must be even (imm[0] = 0) + if (val < -4096 || val > 4094) { + op->goodasm->error("RISC-V B-type imm13 is out of range (-4096 to 4094)"); + return 0; + } + if ((val & 1) != 0) { + op->goodasm->error("RISC-V B-type imm13 must be even (target address must be 2-byte aligned)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvBtypeImm13::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode packs bits in mask order: bit7(imm[11]), bits8-11(imm[4:1]), bits25-30(imm[10:5]), bit31(imm[12]) + int32_t imm11 = raw & 1; + int32_t imm4_1 = (raw >> 1) & 0xF; + int32_t imm10_5 = (raw >> 5) & 0x3F; + int32_t imm12 = (raw >> 11) & 1; + int32_t imm = (imm12 << 12) | (imm11 << 11) | (imm10_5 << 5) | (imm4_1 << 1); + // Sign extend from 13 bits + if (imm & 0x1000) { + imm |= ~0x1FFF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvBtypeImm13::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -4096 || val > 4094) { + op.goodasm->error("RISC-V B-type imm13 is out of range (-4096 to 4094)."); + return; + } + if ((val & 1) != 0) { + op.goodasm->error("RISC-V B-type imm13 must be even (target address must be 2-byte aligned)."); + return; + } + + // Pack imm[12:1] in mask order: imm[11], imm[4:1], imm[10:5], imm[12] + uint32_t imm = val & 0x1FFE; + uint32_t raw = ((imm >> 11) & 1) | + ((imm >> 1) & 0xF) << 1 | + ((imm >> 5) & 0x3F) << 5 | + ((imm >> 12) & 1) << 11; + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V J-type Imm21 (imm[20:1]) parameter +// Encoding: imm[20] in bit [31], imm[19:12] in bits [19:12], imm[11] in bit [20], imm[10:1] in bits [30:21] +// Mask: "\x00\xFF\x10\xFF" - combined from: imm[20] (0x80 in byte 3), imm[19:12] (0xFF in byte 1), imm[11] (0x10 in byte 2), imm[10:1] (0x7F in byte 3) + +GAParameterRiscvJtypeImm21::GAParameterRiscvJtypeImm21(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvJtypeImm21::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); // False on a match + + // must fit signed 21-bit immediate, and must be even (imm[0] = 0) + if (val < -1048576 || val > 1048574) { + op->goodasm->error("RISC-V J-type imm21 is out of range (-1048576 to 1048574)"); + return 0; + } + if ((val & 1) != 0) { + op->goodasm->error("RISC-V J-type imm21 must be even (target address must be 2-byte aligned)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvJtypeImm21::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Reconstruct imm[20:1] from mask-ordered bits + // Mask "\x00\xF0\xFF\xFF" extracts bits in this order: + // raw[3:0] = inst[15:12] = imm[19:16] + // raw[7:4] = inst[19:16] = imm[15:12] + // raw[8] = inst[20] = imm[11] + // raw[11:9] = inst[23:21] = imm[10:8] + // raw[18:12] = inst[30:24] = imm[7:1] + // raw[19] = inst[31] = imm[20] + int32_t imm20 = (raw >> 19) & 1; + int32_t imm19_16 = raw & 0xF; + int32_t imm15_12 = (raw >> 4) & 0xF; + int32_t imm11 = (raw >> 8) & 1; + int32_t imm10_8 = (raw >> 9) & 0x7; + int32_t imm7_1 = (raw >> 12) & 0x7F; + int32_t imm = (imm20 << 20) | (imm19_16 << 16) | (imm15_12 << 12) | (imm11 << 11) | (imm10_8 << 8) | (imm7_1 << 1); + // Sign extend from 21 bits + if (imm & 0x100000) { + imm |= ~0x1FFFFF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvJtypeImm21::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -1048576 || val > 1048574) { + op.goodasm->error("RISC-V J-type imm21 is out of range (-1048576 to 1048574)."); + return; + } + if ((val & 1) != 0) { + op.goodasm->error("RISC-V J-type imm21 must be even (target address must be 2-byte aligned)."); + return; + } + + // Pack imm[20:1] into mask order + // raw[3:0] = imm[19:16] + // raw[7:4] = imm[15:12] + // raw[8] = imm[11] + // raw[11:9] = imm[10:8] + // raw[18:12] = imm[7:1] + // raw[19] = imm[20] + uint32_t imm = val & 0x1FFFFE; // imm[20:1], clear imm[0] + uint32_t raw = (((imm >> 20) & 1) << 19) | // imm[20] -> raw[19] + (((imm >> 1) & 0x7F) << 12) | // imm[7:1] -> raw[18:12] + (((imm >> 8) & 0x7) << 9) | // imm[10:8] -> raw[11:9] + (((imm >> 11) & 1) << 8) | // imm[11] -> raw[8] + (((imm >> 12) & 0xF) << 4) | // imm[15:12] -> raw[7:4] + ((imm >> 16) & 0xF); // imm[19:16] -> raw[3:0] + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V S-type Imm12 (imm[11:0]) parameter +// Encoding: imm[11:5] in bits [31:25], imm[4:0] in bits [11:7] +// Mask: "\x80\x0F\x00\xFE" - imm[4:0] in bits [11:7] (byte 0 bit 7 + byte 1 bits 0-3), imm[11:5] in bits [31:25] (byte 3 bits 1-7) + +GAParameterRiscvStypeImm12::GAParameterRiscvStypeImm12(const char* mask){ + setMask(mask); + prefix = "#"; + isSigned = true; // 12-bit signed immediate +} + +int GAParameterRiscvStypeImm12::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); // False on a match + + // must fit signed 12-bit immediate + if (val < -2048 || val > 2047) { + op->goodasm->error("RISC-V S-type imm12 is out of range (-2048 to 2047)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvStypeImm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode already extracts and packs imm[11:0] from the split encoding via the mask + int32_t imm = raw & 0xFFF; + // Sign extend from 12 bits + if (imm & 0x800) { + imm |= ~0xFFF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvStypeImm12::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -2048 || val > 2047) { + op.goodasm->error("RISC-V S-type imm12 is out of range (-2048 to 2047)."); + return; + } + + // rawencode expects the immediate value directly (in mask bit order, not instruction bit positions) + // The mask will distribute the bits to the correct instruction positions + uint32_t imm = val & 0xFFF; // imm[11:0] - mask to 12 bits + rawencode(lang, adr, bytes, op, inslen, imm); +} + +// RISC-V FENCE pred/succ parameter +// Encoding: pred[3:0] in imm[3:0] (bits [23:20], byte 2 bits [7:4]) +// succ[3:0] in imm[7:4] (bits [27:24], byte 3 bits [3:0]) +// Mask: "\x00\x00\xF0\x0F" - pred in byte 2 bits [7:4], succ in byte 3 bits [3:0] + +GAParameterRiscvFencePredSucc::GAParameterRiscvFencePredSucc(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvFencePredSucc::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit 8-bit value (0-255) where lower 4 bits are pred and upper 4 bits are succ + if (val < 0 || val > 255) { + op->goodasm->error("RISC-V FENCE pred/succ is out of range (0 to 255)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvFencePredSucc::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + // Extract pred[3:0] from imm[3:0] (bits [23:20], byte 2 bits [7:4]) + // Extract succ[3:0] from imm[7:4] (bits [27:24], byte 3 bits [3:0]) + // For little-endian: byte 2 is bytes[2], byte 3 is bytes[3] + uint32_t pred = (bytes[2] >> 4) & 0x0F; // byte 2 bits [7:4] -> pred[3:0] + uint32_t succ = bytes[3] & 0x0F; // byte 3 bits [3:0] -> succ[3:0] + uint32_t val = (succ << 4) | pred; + return QString::asprintf("#0x%02X", val); +} + +void GAParameterRiscvFencePredSucc::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 255) { + op.goodasm->error("RISC-V FENCE pred/succ is out of range (0 to 255)."); + return; + } + + // Split into pred[3:0] and succ[3:0] + uint32_t pred = val & 0x0F; // lower 4 bits + uint32_t succ = (val >> 4) & 0x0F; // upper 4 bits + + // Encode directly into bytes: pred in byte 2 bits [7:4], succ in byte 3 bits [3:0] + // For little-endian: byte 2 is bytes[2], byte 3 is bytes[3] + bytes[2] = (bytes[2] & 0x0F) | (pred << 4); // Set byte 2 bits [7:4] to pred + bytes[3] = (bytes[3] & 0xF0) | succ; // Set byte 3 bits [3:0] to succ +} + +// RISC-V Shamt5 (shamt[4:0]) parameter +// Encoding: shamt[4:0] in bits [24:20] +// Mask: "\x00\x00\xF0\x01" - bits [24:20] in bytes 2-3 (byte 2 bits 7-4, byte 3 bit 0) + +GAParameterRiscvShamt5::GAParameterRiscvShamt5(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvShamt5::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit 5-bit shift amount (0 to 31) + if (val < 0 || val > 31) { + op->goodasm->error("RISC-V shamt5 is out of range (0 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvShamt5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode already extracts bits [24:20] into the value, so just return it + uint32_t shamt = raw & 0x1F; // Mask to 5 bits just to be safe + return prefix + QString::number(shamt); +} + +void GAParameterRiscvShamt5::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < 0 || val > 31) { + op.goodasm->error("RISC-V shamt5 is out of range (0 to 31)."); + return; + } + + // Encode shamt[4:0] into bits [24:20] + rawencode(lang,adr,bytes,op,inslen,val); +} + +// RISC-V CSR12 (csr[11:0]) parameter +// Encoding: csr[11:0] in bits [31:20] +// Mask: "\x00\x00\xF0\xFF" - bits [31:20] in bytes 2-3 + +GAParameterRiscvCsr12::GAParameterRiscvCsr12(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCsr12::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 12-bit CSR address (0 to 4095) + if (val < 0 || val > 4095) { + op->goodasm->error("RISC-V CSR12 is out of range (0 to 4095)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCsr12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode already extracts bits [31:20] into the lower bits + uint32_t csr = raw & 0xFFF; + return QString::asprintf("#0x%03X", csr); +} + +void GAParameterRiscvCsr12::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 4095) { + op.goodasm->error("RISC-V CSR12 is out of range (0 to 4095)."); + return; + } + + // Encode csr[11:0] into bits [31:20] + rawencode(lang,adr,bytes,op,inslen,val); +} + +// RISC-V Uimm5 (uimm[4:0]) parameter +// Encoding: uimm[4:0] in bits [19:15] +// Mask: "\x00\x80\x0F\x00" - bits [19:15] in byte 1-2 + +GAParameterRiscvUimm5::GAParameterRiscvUimm5(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvUimm5::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit 5-bit unsigned immediate (0 to 31) + if (val < 0 || val > 31) { + op->goodasm->error("RISC-V uimm5 is out of range (0 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvUimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode already extracts bits [19:15] into the lower bits + uint32_t uimm = raw & 0x1F; + return prefix + QString::number(uimm); +} + +void GAParameterRiscvUimm5::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 31) { + op.goodasm->error("RISC-V uimm5 is out of range (0 to 31)."); + return; + } + + // Encode uimm[4:0] into bits [19:15] + rawencode(lang,adr,bytes,op,inslen,val); +} + +// C Extension parameter types for compressed 16-bit instructions + +// RISC-V Compressed Register (rd'/rs1'/rs2') parameter +// Encoding: 3-bit field for registers x8-x15 (encoded as 0-7) +// rd' in bits [4:2] (CIW format) or bits [9:7] (most formats) +// rs1' in bits [9:7] +// rs2' in bits [4:2] +// Mask depends on specific format + +GAParameterRiscvCompReg::GAParameterRiscvCompReg(const char* mask){ + setMask(mask); +} + +int GAParameterRiscvCompReg::match(GAParserOperand *op, int len){ + if(op->prefix!=this->prefix) + return 0; + + // Check if it is a valid RISC-V register name. + QString name = op->value; + // Compressed registers are x8-x15 (s0-s1, a0-a7) + if(name == "s0" || name == "s1" || + name == "a0" || name == "a1" || name == "a2" || name == "a3" || + name == "a4" || name == "a5" || name == "a6" || name == "a7") { + return 1; + } + return 0; +} + +QString GAParameterRiscvCompReg::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t regnum = rawdecode(lang, adr, bytes, inslen); + // Compressed register encoding: 0-7 maps to x8-x15 + if(regnum > 7) { + return QString::asprintf("r%llu", (unsigned long long)(regnum + 8)); + } + // Map 0-7 to x8-x15 (s0, s1, a0-a7) + int regnames_idx = 8 + regnum; // x8 = s0, x9 = s1, x10 = a0, etc. + if(regnames_idx < lang->regnames.size()) { + return lang->regnames[regnames_idx]; + } + return QString::asprintf("r%llu", (unsigned long long)(regnum + 8)); +} + +void GAParameterRiscvCompReg::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int regnum = lang->regnames.indexOf(op.value); + if(regnum == -1) { + op.goodasm->error("Unknown RISC-V register: " + op.value); + return; + } + // Compressed registers must be x8-x15 + if(regnum < 8 || regnum > 15) { + op.goodasm->error("RISC-V compressed register must be x8-x15 (s0, s1, a0-a7): " + op.value); + return; + } + // Map x8-x15 (8-15) to compressed encoding (0-7) + int compressed = regnum - 8; + rawencode(lang, adr, bytes, op, inslen, compressed); +} + +// RISC-V CI Format Immediate (imm[5:0]) parameter +// Encoding: imm[5] in bit [12], imm[4:0] in bits [6:2] +// Mask depends on specific instruction + +GAParameterRiscvCIimm6::GAParameterRiscvCIimm6(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIimm6::match(GAParserOperand *op, int len){ + int64_t val=op->int64(false); // False on a match + + // Standard CI format: must fit signed 6-bit immediate (-32 to 31) + if (val >= -32 && val <= 31) { + return 1; // valid for standard CI + } + + // c.lui: accepts values 0-63 (imm[17:12]) or shifted values (imm << 12) + // where imm[17:12] is in range 0-63 + // This means values that are multiples of 0x1000 in range 0x0 to 0x3F000 + if (val >= 0) { + if (val <= 63) { + return 1; // valid for c.lui (direct imm[17:12]) + } + // Check if it's a valid shifted value for c.lui + if ((val & 0xFFF) == 0) { // Must be multiple of 0x1000 + uint32_t imm_upper = (val >> 12) & 0x3F; + if (imm_upper >= 1 && imm_upper <= 63) { // c.lui cannot be 0 (reserved for c.addi16sp) + return 1; // valid for c.lui (shifted value) + } + } + } + + // c.addi16sp: accepts multiples of 16 in range -512 to 496 + if ((val & 0xF) == 0) { // Must be multiple of 16 + if (val >= -512 && val <= 496) { + return 1; // valid for c.addi16sp + } + } + + // Value doesn't fit any CI format + op->goodasm->error("RISC-V CI imm6 is out of range (-32 to 31 for standard CI, 0-63 or multiples of 0x1000 up to 0x3F000 for c.lui, or multiples of 16 in -512 to 496 for c.addi16sp)"); + return 0; +} + +QString GAParameterRiscvCIimm6::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + + // Check if this is c.addi16sp (rd=2, bits [1:0]=01, [15:13]=011) or c.lui (bits [1:0]=01, [15:13]=011, rd!=0,2) + // rd is the definitive distinguisher - c.addi16sp has rd=2, c.lui has rd != 0 and rd != 2 + bool is_addi16sp = false; + bool is_lui = false; + if(inslen >= 2) { + uint8_t byte0 = bytes[0]; + uint8_t byte1 = bytes[1]; + uint8_t opcode_low = byte0 & 0x03; // bits [1:0] + uint8_t opcode_high = (byte1 >> 5) & 0x07; // bits [15:13] + + // Extract rd from bits [11:7]: + // bit [7] is in byte0 bit 7 + // bits [11:8] are in byte1 bits [3:0] + // So rd = (bits [11:8] << 1) | bit [7] + uint8_t rd_high = (byte1 & 0x0F); // bits [11:8] + uint8_t rd_low = (byte0 >> 7) & 0x01; // bit [7] + uint8_t rd = (rd_high << 1) | rd_low; + + if(opcode_low == 0x01 && opcode_high == 0x03) { // bits [1:0]=01, [15:13]=011 + if(rd == 2) { + is_addi16sp = true; // rd=2 definitively indicates c.addi16sp + } else if(rd != 0 && rd != 2) { + is_lui = true; // rd != 0,2 definitively indicates c.lui + } + // rd == 0 is invalid for both c.addi16sp and c.lui (reserved) + } + } + + if(is_addi16sp) { + // c.addi16sp: nzimm[9:4] encoded in bits [12|6|5:2] + // According to RISC-V spec and rawencode order: + // rawencode processes mask 0x7C10 in order: + // val[0]->bit[2] (nzimm[6]) + // val[1]->bit[3] (nzimm[7]) + // val[2]->bit[4] (nzimm[8]) + // val[3]->bit[5] (nzimm[9]) + // val[4]->bit[6] (nzimm[4]) + // val[5]->bit[12] (nzimm[5]) + // So rawdecode extracts in the same order: + // raw[0] = nzimm[6] + // raw[1] = nzimm[7] + // raw[2] = nzimm[8] + // raw[3] = nzimm[9] + // raw[4] = nzimm[4] + // raw[5] = nzimm[5] + // The instruction does: sp = sp + sext(nzimm[9:4] << 4) + if(inslen >= 2) { + // Extract individual bits from raw value (already decoded by rawdecode) + uint32_t nzimm6 = (raw >> 0) & 1; // raw[0] = nzimm[6] + uint32_t nzimm7 = (raw >> 1) & 1; // raw[1] = nzimm[7] + uint32_t nzimm8 = (raw >> 2) & 1; // raw[2] = nzimm[8] + uint32_t nzimm9 = (raw >> 3) & 1; // raw[3] = nzimm[9] + uint32_t nzimm4 = (raw >> 4) & 1; // raw[4] = nzimm[4] + uint32_t nzimm5 = (raw >> 5) & 1; // raw[5] = nzimm[5] + // Reconstruct nzimm[9:4] (6 bits): nzimm[9] is MSB, nzimm[4] is LSB + uint32_t nzimm_6bit = (nzimm9 << 5) | (nzimm8 << 4) | (nzimm7 << 3) | (nzimm6 << 2) | (nzimm5 << 1) | nzimm4; + // Sign extend from 6 bits (nzimm[9] is the sign bit) + // Convert to signed 6-bit value: if bit 5 is set, it's negative + int32_t signed_nzimm_6bit; + if(nzimm_6bit & 0x20) { // Check bit 5 (nzimm[9] when in position) - negative + signed_nzimm_6bit = (int32_t)(nzimm_6bit | 0xFFFFFFC0); // Sign extend to 32 bits + } else { + signed_nzimm_6bit = (int32_t)nzimm_6bit; // Positive, no sign extension needed + } + // The instruction does: sp = sp + sext(nzimm[9:4] << 4) + int32_t result = signed_nzimm_6bit << 4; + return prefix + QString::number(result); + } + return prefix + QString::number(0); + } else if(is_lui) { + // c.lui: imm[17:12] in bits [12|6:2] (same positions as CI format) + // The instruction does: rd = imm << 12 + // Extract directly from bytes + if(inslen >= 2) { + uint8_t byte0 = bytes[0]; + uint8_t byte1 = bytes[1]; + uint32_t imm17 = (byte1 >> 4) & 1; // bit [12] = byte1 bit 4 + uint32_t imm16_12 = (byte0 >> 2) & 0x1F; // bits [6:2] = byte0 bits 6:2 + uint32_t imm_upper = (imm17 << 5) | imm16_12; // imm[17:12] + // Return the full shifted value (imm << 12) for display + uint32_t imm_full = imm_upper << 12; + return prefix + QString::asprintf("0x%x", imm_full); + } + return QString::number(0); + } + + // Standard CI format: rawdecode packs bits in mask order + // Mask 0x7C10: bits [6:2] -> raw[4:0], bit [12] -> raw[5] + uint32_t imm4_0 = raw & 0x1F; // raw[4:0] = imm[4:0] + uint32_t imm5 = (raw >> 5) & 1; // raw[5] = imm[5] + int32_t imm = (imm5 << 5) | imm4_0; + // Sign extend from 6 bits + if (imm & 0x20) { + imm |= ~0x3F; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIimm6::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + // Check if this might be c.addi16sp (value is multiple of 16, range -512 to 496) + // or c.lui (value represents upper 6 bits, typically 0-63 but represents imm << 12) + // We detect by checking opcode, rd value, and value constraints + bool is_addi16sp = false; + bool is_lui = false; + if(inslen >= 2 && bytes.length() >= 2) { + uint8_t byte0 = bytes[0]; + uint8_t byte1 = bytes[1]; + uint8_t opcode_low = byte0 & 0x03; + uint8_t opcode_high = (byte1 >> 5) & 0x07; + + if(opcode_low == 0x01 && opcode_high == 0x03) { + // Extract rd from bits [11:7]: + // bit [7] is in byte0 bit 7 + // bits [11:8] are in byte1 bits [3:0] + // So rd = (bits [11:8] << 1) | bit [7] + uint8_t rd_high = (byte1 & 0x0F); // bits [11:8] + uint8_t rd_low = (byte0 >> 7) & 0x01; // bit [7] + uint8_t rd = (rd_high << 1) | rd_low; + + // Check value constraints + bool val_is_multiple_of_16 = ((val & 0xF) == 0) && (val >= -512) && (val <= 496); + bool val_is_lui_range = (val >= 0 && val <= 63) || ((val & 0xFFF) == 0 && (val >> 12) >= 1 && (val >> 12) <= 63); + + // Check value constraints first - if value can only be one instruction, use that + if(val_is_lui_range && !val_is_multiple_of_16) { + // Value only matches c.lui range + is_lui = true; + } else if(val_is_multiple_of_16 && !val_is_lui_range) { + // Value only matches c.addi16sp range + is_addi16sp = true; + } else { + // Value matches both or neither - use rd as definitive distinguisher + if(rd == 2) { + is_addi16sp = true; // rd=2 definitively indicates c.addi16sp + } else if(rd != 0 && rd != 2) { + is_lui = true; // rd != 0,2 definitively indicates c.lui + } else { + // rd is 0 or not yet set - value matches both ranges + // If value is a multiple of 0x1000 (c.lui format), prefer c.lui + if((val & 0xFFF) == 0 && (val >> 12) >= 1 && (val >> 12) <= 63) { + is_lui = true; + } else if(val_is_multiple_of_16) { + // Value is multiple of 16 but not 0x1000 - prefer c.addi16sp + is_addi16sp = true; + } + // If neither matches, neither will be set and standard CI encoding will be used + } + } + } + } + + if(is_addi16sp) { + // c.addi16sp: encode imm[9|4|6|8:7|5] where imm is the actual value (not shifted) + // The instruction does: sp = sp + (imm << 4), so we need to divide by 16 + // Also ensure rd=2 (sp) is set in the instruction + if((val & 0xF) != 0) { + op.goodasm->error("RISC-V c.addi16sp immediate must be a multiple of 16."); + return; + } + if(val < -512 || val > 496) { + op.goodasm->error("RISC-V c.addi16sp immediate is out of range (-512 to 496)."); + return; + } + // Set rd=2 (sp) in the instruction: rd bits [11:7] = 2 = 00010 + // bit [7] is in byte0 bit 7, bits [11:8] are in byte1 bits [3:0] + if(inslen >= 2 && bytes.length() >= 2) { + bytes[0] = (bytes[0] & ~0x80) | (0 << 7); // bit [7] = 0 (from rd bit 0) + bytes[1] = (bytes[1] & ~0x0F) | (1 << 0); // bits [11:8] = 0001 (from rd bits [4:1]) + } + int32_t imm_shifted = (int32_t)(val >> 4); // Divide by 16 (signed) + // Convert to 6-bit two's complement for encoding + // Mask to 6 bits - this automatically handles two's complement for negative values + uint32_t nzimm_6bit = (uint32_t)(imm_shifted & 0x3F); // Get lower 6 bits (handles negative correctly) + // Now extract the individual bits for the scrambled encoding + // According to RISC-V spec: + // nzimm[5] goes to bit [12] + // nzimm[4] goes to bit [6] + // nzimm[9:6] go to bits [5:2] + uint32_t nzimm9 = (nzimm_6bit >> 5) & 1; // nzimm[9] -> bit [5] + uint32_t nzimm8 = (nzimm_6bit >> 4) & 1; // nzimm[8] -> bit [4] + uint32_t nzimm7 = (nzimm_6bit >> 3) & 1; // nzimm[7] -> bit [3] + uint32_t nzimm6 = (nzimm_6bit >> 2) & 1; // nzimm[6] -> bit [2] + uint32_t nzimm5 = (nzimm_6bit >> 1) & 1; // nzimm[5] -> bit [12] + uint32_t nzimm4 = (nzimm_6bit >> 0) & 1; // nzimm[4] -> bit [6] + // Encode according to c.addi16sp format + // rawencode processes mask 0x7C10 (little-endian) in this order: + // Byte 0: bits [6:2] = 0x7C, processes j=2,3,4,5,6 in order + // Byte 1: bit [12] = 0x10, processes j=4 in byte1 + // So the order is: val[0]->bit[2], val[1]->bit[3], val[2]->bit[4], val[3]->bit[5], val[4]->bit[6], val[5]->bit[12] + // Which means: nzimm[6]->bit[2], nzimm[7]->bit[3], nzimm[8]->bit[4], nzimm[9]->bit[5], nzimm[4]->bit[6], nzimm[5]->bit[12] + uint32_t raw = (nzimm6 << 0) | // val[0] -> bit [2] (nzimm[6]) + (nzimm7 << 1) | // val[1] -> bit [3] (nzimm[7]) + (nzimm8 << 2) | // val[2] -> bit [4] (nzimm[8]) + (nzimm9 << 3) | // val[3] -> bit [5] (nzimm[9]) + (nzimm4 << 4) | // val[4] -> bit [6] (nzimm[4]) + (nzimm5 << 5); // val[5] -> bit [12] (nzimm[5]) + rawencode(lang,adr,bytes,op,inslen,raw); + } else if(is_lui) { + // c.lui: encode imm[17:12] where the value represents the upper 6 bits + // The instruction does: rd = imm << 12 + // If val is already the shifted value (like 0x10000), extract upper bits + // Otherwise, if val is 0-63, treat it as imm[17:12] directly + uint32_t imm_upper; + if(val >= 0 && val <= 63) { + imm_upper = val; // Direct value 0-63 + } else { + imm_upper = (val >> 12) & 0x3F; // Extract upper 6 bits from shifted value + } + if(imm_upper == 0) { + op.goodasm->error("RISC-V c.lui immediate cannot be 0 (reserved for c.addi16sp)."); + return; + } + // Note: imm_upper == 1 is technically reserved per spec, but some implementations allow it + // rawencode processes mask 0x7C10 in order: val[0]->bit[2], val[1]->bit[3], val[2]->bit[4], val[3]->bit[5], val[4]->bit[6], val[5]->bit[12] + // For c.lui: imm[17:12] maps to bits [12|6:2] + // So: imm[12]->bit[2], imm[13]->bit[3], imm[14]->bit[4], imm[15]->bit[5], imm[16]->bit[6], imm[17]->bit[12] + uint32_t imm12 = (imm_upper >> 0) & 1; + uint32_t imm13 = (imm_upper >> 1) & 1; + uint32_t imm14 = (imm_upper >> 2) & 1; + uint32_t imm15 = (imm_upper >> 3) & 1; + uint32_t imm16 = (imm_upper >> 4) & 1; + uint32_t imm17 = (imm_upper >> 5) & 1; + uint32_t raw = (imm12 << 0) | // val[0] -> bit [2] + (imm13 << 1) | // val[1] -> bit [3] + (imm14 << 2) | // val[2] -> bit [4] + (imm15 << 3) | // val[3] -> bit [5] + (imm16 << 4) | // val[4] -> bit [6] + (imm17 << 5); // val[5] -> bit [12] + rawencode(lang,adr,bytes,op,inslen,raw); + } else { + // Standard CI format + if (val < -32 || val > 31) { + op.goodasm->error("RISC-V CI imm6 is out of range (-32 to 31)."); + return; + } + + // rawencode packs bits in mask order: raw[4:0]->inst[6:2], raw[5]->inst[12] + // This matches imm[4:0] and imm[5] directly + uint32_t raw = val & 0x3F; // imm[5:0] directly + + rawencode(lang,adr,bytes,op,inslen,raw); + } +} + +// RISC-V CI Format Immediate Unsigned (uimm[5:0]) parameter +// Encoding: Same as CI format but unsigned (0-31) +// Used in C.SLLI, C.SRLI, C.SRAI + +GAParameterRiscvCIUimm6::GAParameterRiscvCIUimm6(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIUimm6::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 6-bit immediate (0 to 31) + if (val < 0 || val > 31) { + op->goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCIUimm6::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode extracts bits in order: [12] (byte 1 bit 4), then [6:2] (byte 0 bits [6:2]) + // So the result has: [12] at bit 5, [6] at bit 4, [5] at bit 3, [4] at bit 2, [3] at bit 1, [2] at bit 0 + // This gives us: imm[5]|imm[4]|imm[3]|imm[2]|imm[1]|imm[0] + uint32_t imm5 = (raw >> 5) & 1; // imm[5] from bit [12] (at position 5 in raw) + uint32_t imm4 = (raw >> 4) & 1; // imm[4] from bit [6] (at position 4 in raw) + uint32_t imm3_0 = raw & 0xF; // imm[3:0] from bits [5:2] (at positions [3:0] in raw) + uint32_t imm = (imm5 << 5) | (imm4 << 4) | imm3_0; + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIUimm6::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 31) { + op.goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)."); + return; + } + + // Encode uimm[5] into bit [12] and uimm[4:0] into bits [6:2] + // rawencode expects the value in the same order as rawdecode extracts it: + // - imm[5] at bit position 5 (encodes to [12]) + // - imm[4] at bit position 4 (encodes to [6]) + // - imm[3:0] at bit positions [3:0] (encodes to [5:2]) + uint32_t imm = val & 0x3F; // uimm[5:0] + uint32_t raw = ((imm >> 5) & 1) << 5 | // uimm[5] -> position 5 (encodes to bit [12]) + ((imm >> 4) & 1) << 4 | // uimm[4] -> position 4 (encodes to bit [6]) + ((imm >> 0) & 0xF); // uimm[3:0] -> positions [3:0] (encodes to bits [5:2]) + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CI Format Immediate Unsigned (uimm[5:0]) parameter for C.SRAI +// Encoding: Same as CIUimm6 but bit [6] is part of opcode (must be 1) +// Used in C.SRAI only (C.SLLI and C.SRLI use GAParameterRiscvCIUimm6) + +GAParameterRiscvCIUimm6Srai::GAParameterRiscvCIUimm6Srai(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIUimm6Srai::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 6-bit immediate (0 to 31) + if (val < 0 || val > 31) { + op->goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCIUimm6Srai::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + // Use the same logic as GAParameterRiscvCIUimm6 - the encoding is the same + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode extracts bits in order: [12] (byte 1 bit 4), then [6:2] (byte 0 bits [6:2]) + // So the result has: [12] at bit 5, [6] at bit 4, [5] at bit 3, [4] at bit 2, [3] at bit 1, [2] at bit 0 + uint32_t imm5 = (raw >> 5) & 1; // imm[5] from bit [12] (at position 5 in raw) + uint32_t imm4 = (raw >> 4) & 1; // imm[4] from bit [6] (at position 4 in raw) + uint32_t imm3_0 = raw & 0xF; // imm[3:0] from bits [5:2] (at positions [3:0] in raw) + uint32_t imm = (imm5 << 5) | (imm4 << 4) | imm3_0; + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIUimm6Srai::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 31) { + op.goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)."); + return; + } + + // Encode uimm[5] into bit [12] and uimm[4:0] into bits [6:2] + // rawencode expects the value in the same order as rawdecode extracts it: + // - imm[5] at bit position 5 (encodes to [12]) + // - imm[4] at bit position 4 (encodes to [6]) + // - imm[3:0] at bit positions [3:0] (encodes to [5:2]) + uint32_t imm = val & 0x3F; // uimm[5:0] + uint32_t raw = ((imm >> 5) & 1) << 5 | // uimm[5] -> position 5 (encodes to bit [12]) + ((imm >> 4) & 1) << 4 | // uimm[4] -> position 4 (encodes to bit [6]) + ((imm >> 0) & 0xF); // uimm[3:0] -> positions [3:0] (encodes to bits [5:2]) + + // Clear bits [6:5] first since they're part of the opcode pattern but also encode imm[4:3] + // The mask 0x7C covers bits [6:2], so we need to clear bits [6:5] before encoding + bytes[0] &= ~0x60; // Clear bits [6:5] in byte 0 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CI Format Immediate (imm[7:2]) parameter for c.lwsp +// Encoding: imm[5] in bit [12], imm[4:2] in bits [6:4], imm[7:6] in bits [3:2] +// Used in C.LWSP + +GAParameterRiscvCIimm7::GAParameterRiscvCIimm7(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIimm7::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 8-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0, 4, 8, 12, ..., 252 (must be multiple of 4, 0-252) + if (val < 0 || val > 252 || (val & 3) != 0) { + op->goodasm->error("RISC-V CI imm7 is out of range (0 to 252, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCIimm7::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask "\x7C\x10" captures instruction bits [6:4], [3:2], [12] + // rawdecode packs bits sequentially by mask position: + // raw bit 0 = instruction bit 2 = imm[6] + // raw bit 1 = instruction bit 3 = imm[7] + // raw bit 2 = instruction bit 4 = imm[2] + // raw bit 3 = instruction bit 5 = imm[3] + // raw bit 4 = instruction bit 6 = imm[4] + // raw bit 5 = instruction bit 12 = imm[5] + uint32_t imm6 = (raw >> 0) & 1; + uint32_t imm7 = (raw >> 1) & 1; + uint32_t imm2 = (raw >> 2) & 1; + uint32_t imm3 = (raw >> 3) & 1; + uint32_t imm4 = (raw >> 4) & 1; + uint32_t imm5 = (raw >> 5) & 1; + uint32_t imm = (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIimm7::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 252 || (val & 3) != 0) { + op.goodasm->error("RISC-V CI imm7 is out of range (0 to 252, must be multiple of 4)."); + return; + } + + // Encode imm[7:2] into sequential raw bits (matching mask bit order) + // raw bit 0 = imm[6] + // raw bit 1 = imm[7] + // raw bit 2 = imm[2] + // raw bit 3 = imm[3] + // raw bit 4 = imm[4] + // raw bit 5 = imm[5] + uint32_t imm = val; + uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 + ((imm >> 7) & 1) << 1 | // imm[7] -> raw bit 1 + ((imm >> 2) & 1) << 2 | // imm[2] -> raw bit 2 + ((imm >> 3) & 1) << 3 | // imm[3] -> raw bit 3 + ((imm >> 4) & 1) << 4 | // imm[4] -> raw bit 4 + ((imm >> 5) & 1) << 5; // imm[5] -> raw bit 5 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CIW Format Immediate (imm[9:2]) parameter +// Encoding: imm[9:2] in bits [10:7|12:11|5|6] (split across instruction) +// Used in C.ADDI4SPN + +GAParameterRiscvCIWimm9::GAParameterRiscvCIWimm9(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCIWimm9::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 9-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0 to 1020 (must be multiple of 4) + if (val < 0 || val > 1020 || (val & 3) != 0) { + op->goodasm->error("RISC-V CIW imm9 is out of range (0 to 1020, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCIWimm9::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Extract imm[9:2] from split encoding + // Mask "\xE0\x1F" captures instruction bits [12:5] + // rawdecode packs bits sequentially: + // raw bit 0 = instruction bit 5 = nzuimm[3] + // raw bit 1 = instruction bit 6 = nzuimm[2] + // raw bit 2 = instruction bit 7 = nzuimm[6] + // raw bit 3 = instruction bit 8 = nzuimm[7] + // raw bit 4 = instruction bit 9 = nzuimm[8] + // raw bit 5 = instruction bit 10 = nzuimm[9] + // raw bit 6 = instruction bit 11 = nzuimm[4] + // raw bit 7 = instruction bit 12 = nzuimm[5] + uint32_t imm3 = (raw >> 0) & 1; // raw bit 0 + uint32_t imm2 = (raw >> 1) & 1; // raw bit 1 + uint32_t imm6 = (raw >> 2) & 1; // raw bit 2 + uint32_t imm7 = (raw >> 3) & 1; // raw bit 3 + uint32_t imm8 = (raw >> 4) & 1; // raw bit 4 + uint32_t imm9 = (raw >> 5) & 1; // raw bit 5 + uint32_t imm4 = (raw >> 6) & 1; // raw bit 6 + uint32_t imm5 = (raw >> 7) & 1; // raw bit 7 + uint32_t imm = (imm9 << 9) | (imm8 << 8) | (imm7 << 7) | (imm6 << 6) | + (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); + return prefix + QString::number(imm); +} + +void GAParameterRiscvCIWimm9::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 1020 || (val & 3) != 0) { + op.goodasm->error("RISC-V CIW imm9 is out of range (0 to 1020, must be multiple of 4)."); + return; + } + + // Encode imm[9:2] into sequential raw bits (matching mask bit order) + // raw bit 0 = nzuimm[3] + // raw bit 1 = nzuimm[2] + // raw bit 2 = nzuimm[6] + // raw bit 3 = nzuimm[7] + // raw bit 4 = nzuimm[8] + // raw bit 5 = nzuimm[9] + // raw bit 6 = nzuimm[4] + // raw bit 7 = nzuimm[5] + uint32_t imm = val; + uint32_t raw = ((imm >> 3) & 1) << 0 | // nzuimm[3] -> raw bit 0 + ((imm >> 2) & 1) << 1 | // nzuimm[2] -> raw bit 1 + ((imm >> 6) & 1) << 2 | // nzuimm[6] -> raw bit 2 + ((imm >> 7) & 1) << 3 | // nzuimm[7] -> raw bit 3 + ((imm >> 8) & 1) << 4 | // nzuimm[8] -> raw bit 4 + ((imm >> 9) & 1) << 5 | // nzuimm[9] -> raw bit 5 + ((imm >> 4) & 1) << 6 | // nzuimm[4] -> raw bit 6 + ((imm >> 5) & 1) << 7; // nzuimm[5] -> raw bit 7 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CL Format Immediate (imm[5:2]) parameter +// Encoding: imm[5] in bit [12], imm[4:2] in bits [6:5|2] +// Used in C.LW + +GAParameterRiscvCLimm5::GAParameterRiscvCLimm5(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCLimm5::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 4-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0, 4, 8, 12, ..., 124 (must be multiple of 4, 0-124) + if (val < 0 || val > 124 || (val & 3) != 0) { + op->goodasm->error("RISC-V CL imm5 is out of range (0 to 124, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCLimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask "\x60\x1C" captures instruction bits [6:5], [12:10] + // rawdecode packs bits sequentially by mask position: + // raw bit 0 = instruction bit 5 = imm[6] + // raw bit 1 = instruction bit 6 = imm[2] + // raw bit 2 = instruction bit 10 = imm[3] + // raw bit 3 = instruction bit 11 = imm[4] + // raw bit 4 = instruction bit 12 = imm[5] + uint32_t imm6 = (raw >> 0) & 1; + uint32_t imm2 = (raw >> 1) & 1; + uint32_t imm3 = (raw >> 2) & 1; + uint32_t imm4 = (raw >> 3) & 1; + uint32_t imm5 = (raw >> 4) & 1; + uint32_t imm = (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); + return prefix + QString::number(imm); +} + +void GAParameterRiscvCLimm5::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 124 || (val & 3) != 0) { + op.goodasm->error("RISC-V CL imm5 is out of range (0 to 124, must be multiple of 4)."); + return; + } + + // Encode imm[6:2] into sequential raw bits (matching mask bit order) + // raw bit 0 = imm[6] + // raw bit 1 = imm[2] + // raw bit 2 = imm[3] + // raw bit 3 = imm[4] + // raw bit 4 = imm[5] + uint32_t imm = val; + uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 + ((imm >> 2) & 1) << 1 | // imm[2] -> raw bit 1 + ((imm >> 3) & 1) << 2 | // imm[3] -> raw bit 2 + ((imm >> 4) & 1) << 3 | // imm[4] -> raw bit 3 + ((imm >> 5) & 1) << 4; // imm[5] -> raw bit 4 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CS Format Immediate (imm[5:2]) parameter +// Encoding: Same as CL format +// Used in C.SW + +GAParameterRiscvCSimm5::GAParameterRiscvCSimm5(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCSimm5::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 4-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0, 4, 8, 12, ..., 124 (must be multiple of 4, 0-124) + if (val < 0 || val > 124 || (val & 3) != 0) { + op->goodasm->error("RISC-V CS imm5 is out of range (0 to 124, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCSimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask "\x60\x1C" captures instruction bits [6:5], [12:10] + // rawdecode packs bits sequentially by mask position: + // raw bit 0 = instruction bit 5 = imm[6] + // raw bit 1 = instruction bit 6 = imm[2] + // raw bit 2 = instruction bit 10 = imm[3] + // raw bit 3 = instruction bit 11 = imm[4] + // raw bit 4 = instruction bit 12 = imm[5] + uint32_t imm6 = (raw >> 0) & 1; + uint32_t imm2 = (raw >> 1) & 1; + uint32_t imm3 = (raw >> 2) & 1; + uint32_t imm4 = (raw >> 3) & 1; + uint32_t imm5 = (raw >> 4) & 1; + uint32_t imm = (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); + return prefix + QString::number(imm); +} + +void GAParameterRiscvCSimm5::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 124 || (val & 3) != 0) { + op.goodasm->error("RISC-V CS imm5 is out of range (0 to 124, must be multiple of 4)."); + return; + } + + // Encode imm[6:2] into sequential raw bits (matching mask bit order) + // raw bit 0 = imm[6] + // raw bit 1 = imm[2] + // raw bit 2 = imm[3] + // raw bit 3 = imm[4] + // raw bit 4 = imm[5] + uint32_t imm = val; + uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 + ((imm >> 2) & 1) << 1 | // imm[2] -> raw bit 1 + ((imm >> 3) & 1) << 2 | // imm[3] -> raw bit 2 + ((imm >> 4) & 1) << 3 | // imm[4] -> raw bit 3 + ((imm >> 5) & 1) << 4; // imm[5] -> raw bit 4 + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CSS Format Immediate (imm[7:2]) parameter +// Encoding: imm[7:2] in bits [12:7] +// Used in C.SWSP + +GAParameterRiscvCSSimm7::GAParameterRiscvCSSimm7(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCSSimm7::match(GAParserOperand *op, int len){ + int64_t val=op->uint64(false); // False on a match + + // must fit unsigned 6-bit immediate, 4-byte aligned (imm[1:0] = 0) + // Range: 0, 4, 8, 12, ..., 252 (must be multiple of 4, 0-252) + if (val < 0 || val > 252 || (val & 3) != 0) { + op->goodasm->error("RISC-V CSS imm7 is out of range (0 to 252, must be multiple of 4)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCSSimm7::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // rawdecode with mask 0x80 0x1F extracts bits [12:7] in the order: + // Byte 1 (last): bits [12:8] (mask 0x1F = bits [4:0] of byte 1) + // Byte 0 (first): bit 7 (mask 0x80 = bit 7 of byte 0) + // rawdecode processes bits from highest byte to lowest, highest bit to lowest bit: + // Byte 1, bit 4 (bit 12) → raw bit 5 (MSB of imm[7:2]) + // Byte 1, bit 3 (bit 11) → raw bit 4 + // Byte 1, bit 2 (bit 10) → raw bit 3 + // Byte 1, bit 1 (bit 9) → raw bit 2 + // Byte 1, bit 0 (bit 8) → raw bit 1 + // Byte 0, bit 7 (bit 7) → raw bit 0 (LSB of imm[7:2]) + // So raw already contains imm[7:2] in the correct order! + uint32_t imm = raw << 2; // Shift left by 2 (imm[1:0] are always 0) + return prefix + QString::number(imm); +} + +void GAParameterRiscvCSSimm7::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.uint64(true); + + if (val < 0 || val > 252 || (val & 3) != 0) { + op.goodasm->error("RISC-V CSS imm7 is out of range (0 to 252, must be multiple of 4)."); + return; + } + + // Encode imm[7:2] into bits [12:7] + // rawencode processes bits from lowest bit to highest, placing them into mask positions + // in order (highest byte first, highest bit first): + // raw bit 0 → Byte 0, bit 7 (bit 7) - LSB + // raw bit 1 → Byte 1, bit 0 (bit 8) + // raw bit 2 → Byte 1, bit 1 (bit 9) + // raw bit 3 → Byte 1, bit 2 (bit 10) + // raw bit 4 → Byte 1, bit 3 (bit 11) + // raw bit 5 → Byte 1, bit 4 (bit 12) - MSB + // So raw should be imm[7:2] directly (no rearrangement needed) + uint32_t imm = (val >> 2) & 0x3F; // imm[7:2] + rawencode(lang,adr,bytes,op,inslen,imm); +} + +// RISC-V CB Format Immediate (imm[8|4:3|7:6|2:1|5]) parameter +// Encoding: Split across instruction bits +// Used in C.BEQZ, C.BNEZ + +GAParameterRiscvCBimm9::GAParameterRiscvCBimm9(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCBimm9::match(GAParserOperand *op, int len){ + // Accept any label or integer - range check will happen in encode with PC-relative calculation + // This allows labels to be matched and resolved during encoding + return 1; // valid +} + +QString GAParameterRiscvCBimm9::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask 0x7C1C: inst[6:2] -> raw[4:0], inst[12:10] -> raw[7:5] + // CB format immediate mapping in instruction bits: + // inst[2]=imm[5], inst[3]=imm[1], inst[4]=imm[2], inst[5]=imm[6] + // inst[6]=imm[7], inst[10]=imm[3], inst[11]=imm[4], inst[12]=imm[8] + // So in raw: + // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[6] + // raw[4]=imm[7], raw[5]=imm[3], raw[6]=imm[4], raw[7]=imm[8] + int32_t imm1 = (raw >> 1) & 1; + int32_t imm2 = (raw >> 2) & 1; + int32_t imm3 = (raw >> 5) & 1; + int32_t imm4 = (raw >> 6) & 1; + int32_t imm5 = raw & 1; + int32_t imm6 = (raw >> 3) & 1; + int32_t imm7 = (raw >> 4) & 1; + int32_t imm8 = (raw >> 7) & 1; + int32_t imm = (imm8 << 8) | (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | + (imm4 << 4) | (imm3 << 3) | (imm2 << 2) | (imm1 << 1); + // Sign extend from 9 bits + if (imm & 0x100) { + imm |= ~0x1FF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvCBimm9::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + // PC-relative addressing: calculate offset from current address + int64_t target = op.int64(true); + int64_t val = target - adr; // PC-relative offset + + // Range check: -256 to 254 bytes (signed 9-bit, even addresses only) + if (val < -256 || val > 254) { + op.goodasm->error("RISC-V CB imm9 is out of range (-256 to 254 bytes from PC)."); + return; + } + if ((val & 1) != 0) { + op.goodasm->error("RISC-V CB imm9 must be even (target address must be 2-byte aligned)."); + return; + } + + // Pack into raw in mask order: + // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[6] + // raw[4]=imm[7], raw[5]=imm[3], raw[6]=imm[4], raw[7]=imm[8] + uint32_t imm = val & 0x1FE; // imm[8:1], clear imm[0] + uint32_t raw = (((imm >> 5) & 1) << 0) | // imm[5] -> raw[0] + (((imm >> 1) & 1) << 1) | // imm[1] -> raw[1] + (((imm >> 2) & 1) << 2) | // imm[2] -> raw[2] + (((imm >> 6) & 1) << 3) | // imm[6] -> raw[3] + (((imm >> 7) & 1) << 4) | // imm[7] -> raw[4] + (((imm >> 3) & 1) << 5) | // imm[3] -> raw[5] + (((imm >> 4) & 1) << 6) | // imm[4] -> raw[6] + (((imm >> 8) & 1) << 7); // imm[8] -> raw[7] + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CJ Format Immediate (imm[11|4|9:8|10|6|7|3:1|5]) parameter +// Encoding: Split across instruction bits +// Used in C.J + +GAParameterRiscvCJimm12::GAParameterRiscvCJimm12(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCJimm12::match(GAParserOperand *op, int len){ + // Accept any label or integer - range check will happen in encode with PC-relative calculation + // This allows labels to be matched and resolved during encoding + return 1; // valid +} + +QString GAParameterRiscvCJimm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + // Mask 0xFC1F: inst[7:2] -> raw[5:0], inst[12:8] -> raw[10:6] + // CJ format immediate mapping in instruction bits: + // inst[2]=imm[5], inst[3]=imm[1], inst[4]=imm[2], inst[5]=imm[3] + // inst[6]=imm[7], inst[7]=imm[6], inst[8]=imm[10], inst[9]=imm[9] + // inst[10]=imm[8], inst[11]=imm[4], inst[12]=imm[11] + // So in raw: + // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[3] + // raw[4]=imm[7], raw[5]=imm[6], raw[6]=imm[10], raw[7]=imm[9] + // raw[8]=imm[8], raw[9]=imm[4], raw[10]=imm[11] + int32_t imm1 = (raw >> 1) & 1; + int32_t imm2 = (raw >> 2) & 1; + int32_t imm3 = (raw >> 3) & 1; + int32_t imm4 = (raw >> 9) & 1; + int32_t imm5 = raw & 1; + int32_t imm6 = (raw >> 5) & 1; + int32_t imm7 = (raw >> 4) & 1; + int32_t imm8 = (raw >> 8) & 1; + int32_t imm9 = (raw >> 7) & 1; + int32_t imm10 = (raw >> 6) & 1; + int32_t imm11 = (raw >> 10) & 1; + int32_t imm = (imm11 << 11) | (imm10 << 10) | (imm9 << 9) | (imm8 << 8) | + (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | + (imm3 << 3) | (imm2 << 2) | (imm1 << 1); + // Sign extend from 12 bits + if (imm & 0x800) { + imm |= ~0xFFF; + } + return prefix + QString::number(imm); +} + +void GAParameterRiscvCJimm12::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + // PC-relative addressing: calculate offset from current address + int64_t target = op.int64(true); + int64_t val = target - adr; // PC-relative offset + + // Range check: -2048 to 2046 bytes (signed 12-bit, even addresses only) + if (val < -2048 || val > 2046) { + op.goodasm->error("RISC-V CJ imm12 is out of range (-2048 to 2046 bytes from PC)."); + return; + } + if ((val & 1) != 0) { + op.goodasm->error("RISC-V CJ imm12 must be even (target address must be 2-byte aligned)."); + return; + } + + // Pack into raw in mask order: + // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[3] + // raw[4]=imm[7], raw[5]=imm[6], raw[6]=imm[10], raw[7]=imm[9] + // raw[8]=imm[8], raw[9]=imm[4], raw[10]=imm[11] + uint32_t imm = val & 0xFFE; // imm[11:1], clear imm[0] + uint32_t raw = (((imm >> 5) & 1) << 0) | // imm[5] -> raw[0] + (((imm >> 1) & 1) << 1) | // imm[1] -> raw[1] + (((imm >> 2) & 1) << 2) | // imm[2] -> raw[2] + (((imm >> 3) & 1) << 3) | // imm[3] -> raw[3] + (((imm >> 7) & 1) << 4) | // imm[7] -> raw[4] + (((imm >> 6) & 1) << 5) | // imm[6] -> raw[5] + (((imm >> 10) & 1) << 6) | // imm[10] -> raw[6] + (((imm >> 9) & 1) << 7) | // imm[9] -> raw[7] + (((imm >> 8) & 1) << 8) | // imm[8] -> raw[8] + (((imm >> 4) & 1) << 9) | // imm[4] -> raw[9] + (((imm >> 11) & 1) << 10); // imm[11] -> raw[10] + + rawencode(lang,adr,bytes,op,inslen,raw); +} + +// RISC-V CB Format Immediate for C.ANDI (imm[5:0]) parameter +// Encoding: Standard CB format: imm[5] in bit [12], imm[4:0] in bits [6:2] +// - imm[5] in bit [12] +// - imm[4:0] in bits [6:2] +// Note: bits [6:5] are part of the immediate encoding, not the opcode pattern +// Range: -32 to 31 (6-bit signed) + +GAParameterRiscvCBimm6Andi::GAParameterRiscvCBimm6Andi(const char* mask){ + setMask(mask); + prefix = "#"; +} + +int GAParameterRiscvCBimm6Andi::match(GAParserOperand *op, int len){ + int64_t val = op->int64(false); // False on a match + + // must fit signed 6-bit immediate (-32 to 31) + if (val < -32 || val > 31) { + op->goodasm->error("RISC-V CB imm6 (c.andi) is out of range (-32 to 31)"); + return 0; + } + + return 1; // valid +} + +QString GAParameterRiscvCBimm6Andi::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ + uint64_t raw = rawdecode(lang,adr,bytes,inslen); + + // rawdecode extracts bits according to mask 0x7C10: + // - bits [6:2] from byte 0 → bits 0-4 of raw = imm[4:0] + // - bit [12] from byte 1 → bit 5 of raw = imm[5] + // So raw already has: imm[4:0] in bits 0-4, imm[5] in bit 5 + uint32_t imm5 = (raw >> 5) & 1; // bit 5 of raw = imm[5] + uint32_t imm4_0 = raw & 0x1F; // bits 0-4 of raw = imm[4:0] + + // Reconstruct imm[5:0] = imm[5] << 5 | imm[4:0] + uint32_t imm = (imm5 << 5) | imm4_0; + + // Sign extend from 6 bits + if (imm & 0x20) { + imm |= ~0x3F; + } + int32_t signed_imm = (int32_t)imm; + return prefix + QString::number(signed_imm); +} + +void GAParameterRiscvCBimm6Andi::encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ){ + int64_t val = op.int64(true); + + if (val < -32 || val > 31) { + op.goodasm->error("RISC-V CB imm6 (c.andi) is out of range (-32 to 31)."); + return; + } + + // Convert to 6-bit signed value + int32_t imm_signed = val & 0x3F; + if (imm_signed & 0x20) { + imm_signed |= ~0x3F; // Sign extend + } + + // Extract imm[5] and imm[4:0] as unsigned for encoding + // Mask 0x7C10 encodes: imm[4:0] in bits [6:2], imm[5] in bit [12] + // rawencode processes mask bits in order: first bits [6:2] (5 bits), then bit [12] (1 bit) + // So the raw value should have: imm[4:0] in bits 0-4, imm[5] in bit 5 + uint32_t imm = (uint32_t)(imm_signed & 0x3F); // Get 6-bit value as unsigned + uint32_t imm5 = (imm >> 5) & 1; + uint32_t imm4_0 = imm & 0x1F; + + // rawencode processes mask 0x7C10 in order: + // - Byte 0 bits [6:2] (5 bits) = imm[4:0] + // - Byte 1 bit [12] (1 bit) = imm[5] + // So raw value: imm[4:0] in lower 5 bits, imm[5] in bit 5 + uint32_t raw = imm4_0 | (imm5 << 5); + + rawencode(lang,adr,bytes,op,inslen,raw); +} diff --git a/galangriscv32.h b/galangriscv32.h new file mode 100644 index 0000000..e0cb4ea --- /dev/null +++ b/galangriscv32.h @@ -0,0 +1,341 @@ +#include "galanguage.h" +#include "gaparameter.h" +#include "gamnemonic.h" + +class GALangRISCV : public GALanguage +{ +public: + GALangRISCV(); +}; + +class GAParameterRiscvReg : public GAParameter { + public: + GAParameterRiscvReg(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + + +class GAParameterRiscvImm12 : public GAParameter { +public: + GAParameterRiscvImm12(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvUtypeImm20 : public GAParameter { +public: + GAParameterRiscvUtypeImm20(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvBtypeImm13 : public GAParameter { +public: + GAParameterRiscvBtypeImm13(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvJtypeImm21 : public GAParameter { +public: + GAParameterRiscvJtypeImm21(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvStypeImm12 : public GAParameter { +public: + GAParameterRiscvStypeImm12(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvFencePredSucc : public GAParameter { +public: + GAParameterRiscvFencePredSucc(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvShamt5 : public GAParameter { +public: + GAParameterRiscvShamt5(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCsr12 : public GAParameter { +public: + GAParameterRiscvCsr12(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvUimm5 : public GAParameter { +public: + GAParameterRiscvUimm5(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +// C Extension parameter types for compressed 16-bit instructions + +class GAParameterRiscvCompReg : public GAParameter { +public: + GAParameterRiscvCompReg(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIimm6 : public GAParameter { +public: + GAParameterRiscvCIimm6(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIUimm6 : public GAParameter { +public: + GAParameterRiscvCIUimm6(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIUimm6Srai : public GAParameter { +public: + GAParameterRiscvCIUimm6Srai(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIimm7 : public GAParameter { +public: + GAParameterRiscvCIimm7(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCIWimm9 : public GAParameter { +public: + GAParameterRiscvCIWimm9(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCLimm5 : public GAParameter { +public: + GAParameterRiscvCLimm5(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCSimm5 : public GAParameter { +public: + GAParameterRiscvCSimm5(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCSSimm7 : public GAParameter { +public: + GAParameterRiscvCSSimm7(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCBimm9 : public GAParameter { +public: + GAParameterRiscvCBimm9(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCJimm12 : public GAParameter { +public: + GAParameterRiscvCJimm12(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; + +class GAParameterRiscvCBimm6Andi : public GAParameter { +public: + GAParameterRiscvCBimm6Andi(const char* mask); + int match(GAParserOperand *op, int len) override; + + QString decode(GALanguage *lang, uint64_t adr, + const char *bytes, int inslen) override; + + void encode(GALanguage *lang, + uint64_t adr, QByteArray &bytes, + GAParserOperand op, + int inslen + ) override; +}; \ No newline at end of file diff --git a/gamnemonic.cpp b/gamnemonic.cpp index 7f2eb1d..11b47f3 100644 --- a/gamnemonic.cpp +++ b/gamnemonic.cpp @@ -63,6 +63,10 @@ int GAMnemonic::match(GAInstruction &ins, uint64_t adr, uint32_t &len, return 0; //No match. } + //Check reject-when-zero constraints (e.g., RISC-V c.addi requires rd != 0). + if(!passesRejectConstraints(bytes)) + return 0; + //Here we have a match, but we need to form a valid instructions. ins.verb=name; ins.type=GAInstruction::MNEMONIC; @@ -171,3 +175,26 @@ GAMnemonic* GAMnemonic::prioritize(int priority){ this->priority=priority; return this; } + +//Reject match if specified field is zero (for instruction disambiguation). +GAMnemonic* GAMnemonic::rejectWhenZero(const char* mask){ + QByteArray m; + for(uint32_t i = 0; i < length; i++) + m.append(mask[i]); + rejectZeroMasks.append(m); + return this; +} + +//Helper to check reject-when-zero constraints. +bool GAMnemonic::passesRejectConstraints(const char* bytes){ + for(const auto& rzMask : rejectZeroMasks) { + bool fieldIsZero = true; + for(uint32_t i = 0; i < length && fieldIsZero; i++) { + if(bytes[i] & rzMask[i]) + fieldIsZero = false; + } + if(fieldIsZero) + return false; // Reject: field must be non-zero + } + return true; +} diff --git a/gamnemonic.h b/gamnemonic.h index dfc26ce..b9424c6 100644 --- a/gamnemonic.h +++ b/gamnemonic.h @@ -3,6 +3,8 @@ #include #include +#include +#include #include "gaparameter.h" #include "gaparser.h" @@ -41,6 +43,10 @@ class GAMnemonic : public GAParameterGroup GAMnemonic* prioritize(int priority=1); int priority=0; + //Reject match if specified field is zero (for instruction disambiguation). + GAMnemonic* rejectWhenZero(const char* mask); + QList rejectZeroMasks; + //Short help string for the cheat sheet. GAMnemonic* help(QString help); @@ -75,6 +81,8 @@ class GAMnemonic : public GAParameterGroup void config(QString mnemonic, uint32_t length, const char *opcode, const char *opcodemask, const char *invertmask); + //Helper to check reject-when-zero constraints. + bool passesRejectConstraints(const char* bytes); }; #endif // GAMNEMONIC_H diff --git a/goodasm.cpp b/goodasm.cpp index 49d5c6c..e176b3a 100644 --- a/goodasm.cpp +++ b/goodasm.cpp @@ -31,6 +31,7 @@ #include "galangarm7tdmi.h" #include "galangtms320c28x.h" #include "galangti80.h" +#include "galangriscv32.h" //Listings #include "galistingdefault.h" @@ -78,6 +79,7 @@ bool GoodASM::setLanguage(QString language){ languages.append(new GALangARM7TDMI()); languages.append(new GALangTMS320C28x()); languages.append(new GALangTI80()); + languages.append(new GALangRISCV()); } //Does our language match? diff --git a/main.cpp b/main.cpp index 9f76d7c..5c3e9d4 100644 --- a/main.cpp +++ b/main.cpp @@ -254,6 +254,14 @@ int main(int argc, char *argv[]){ "TI 80 (broken)" ); parser.addOption(langTI80); + QCommandLineOption langRISCV(QStringList()<<"riscv", + "RISCV (alpha)" + ); + parser.addOption(langRISCV); + QCommandLineOption langRISCV32(QStringList()<<"riscv32", + "RISCV32 (alpha)" + ); + parser.addOption(langRISCV32); @@ -304,6 +312,10 @@ int main(int argc, char *argv[]){ language="tms320c28x"; else if(parser.isSet(langTI80)) language="ti80"; + else if(parser.isSet(langRISCV)) + language="riscv32"; + else if(parser.isSet(langRISCV32)) + language="riscv32"; //We allocate this dynamically to test that we free properly. GoodASM *goodasm=new GoodASM(language); diff --git a/tests/riscv/a-extension/amoadd.w.asm b/tests/riscv/a-extension/amoadd.w.asm new file mode 100644 index 0000000..6c8dc31 --- /dev/null +++ b/tests/riscv/a-extension/amoadd.w.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +amoadd.w zero, zero, (zero) +amoadd.w zero, zero, (ra) +amoadd.w zero, zero, (t0) +amoadd.w zero, zero, (a0) +amoadd.w zero, zero, (a5) +amoadd.w zero, zero, (s4) +amoadd.w zero, zero, (s9) +amoadd.w zero, zero, (t6) +amoadd.w zero, ra, (zero) +amoadd.w zero, ra, (ra) +amoadd.w zero, ra, (t0) +amoadd.w zero, ra, (a0) +amoadd.w zero, ra, (a5) +amoadd.w zero, ra, (s4) +amoadd.w zero, ra, (s9) +amoadd.w zero, ra, (t6) +amoadd.w zero, t0, (zero) +amoadd.w zero, t0, (ra) +amoadd.w zero, t0, (t0) +amoadd.w zero, t0, (a0) +amoadd.w zero, t0, (a5) +amoadd.w zero, t0, (s4) +amoadd.w zero, t0, (s9) +amoadd.w zero, t0, (t6) +amoadd.w zero, a0, (zero) +amoadd.w zero, a0, (ra) +amoadd.w zero, a0, (t0) +amoadd.w zero, a0, (a0) +amoadd.w zero, a0, (a5) +amoadd.w zero, a0, (s4) +amoadd.w zero, a0, (s9) +amoadd.w zero, a0, (t6) +amoadd.w zero, a5, (zero) +amoadd.w zero, a5, (ra) +amoadd.w zero, a5, (t0) +amoadd.w zero, a5, (a0) +amoadd.w zero, a5, (a5) +amoadd.w zero, a5, (s4) +amoadd.w zero, a5, (s9) +amoadd.w zero, a5, (t6) +amoadd.w zero, s4, (zero) +amoadd.w zero, s4, (ra) +amoadd.w zero, s4, (t0) +amoadd.w zero, s4, (a0) +amoadd.w zero, s4, (a5) +amoadd.w zero, s4, (s4) +amoadd.w zero, s4, (s9) +amoadd.w zero, s4, (t6) +amoadd.w zero, s9, (zero) +amoadd.w zero, s9, (ra) +amoadd.w zero, s9, (t0) +amoadd.w zero, s9, (a0) +amoadd.w zero, s9, (a5) +amoadd.w zero, s9, (s4) +amoadd.w zero, s9, (s9) +amoadd.w zero, s9, (t6) +amoadd.w zero, t6, (zero) +amoadd.w zero, t6, (ra) +amoadd.w zero, t6, (t0) +amoadd.w zero, t6, (a0) +amoadd.w zero, t6, (a5) +amoadd.w zero, t6, (s4) +amoadd.w zero, t6, (s9) +amoadd.w zero, t6, (t6) +amoadd.w ra, zero, (zero) +amoadd.w ra, zero, (ra) +amoadd.w ra, zero, (t0) +amoadd.w ra, zero, (a0) +amoadd.w ra, zero, (a5) +amoadd.w ra, zero, (s4) +amoadd.w ra, zero, (s9) +amoadd.w ra, zero, (t6) +amoadd.w ra, ra, (zero) +amoadd.w ra, ra, (ra) +amoadd.w ra, ra, (t0) +amoadd.w ra, ra, (a0) +amoadd.w ra, ra, (a5) +amoadd.w ra, ra, (s4) +amoadd.w ra, ra, (s9) +amoadd.w ra, ra, (t6) +amoadd.w ra, t0, (zero) +amoadd.w ra, t0, (ra) +amoadd.w ra, t0, (t0) +amoadd.w ra, t0, (a0) +amoadd.w ra, t0, (a5) +amoadd.w ra, t0, (s4) +amoadd.w ra, t0, (s9) +amoadd.w ra, t0, (t6) +amoadd.w ra, a0, (zero) +amoadd.w ra, a0, (ra) +amoadd.w ra, a0, (t0) +amoadd.w ra, a0, (a0) +amoadd.w ra, a0, (a5) +amoadd.w ra, a0, (s4) +amoadd.w ra, a0, (s9) +amoadd.w ra, a0, (t6) +amoadd.w ra, a5, (zero) +amoadd.w ra, a5, (ra) +amoadd.w ra, a5, (t0) +amoadd.w ra, a5, (a0) +amoadd.w ra, a5, (a5) +amoadd.w ra, a5, (s4) +amoadd.w ra, a5, (s9) +amoadd.w ra, a5, (t6) +amoadd.w ra, s4, (zero) +amoadd.w ra, s4, (ra) +amoadd.w ra, s4, (t0) +amoadd.w ra, s4, (a0) +amoadd.w ra, s4, (a5) +amoadd.w ra, s4, (s4) +amoadd.w ra, s4, (s9) +amoadd.w ra, s4, (t6) +amoadd.w ra, s9, (zero) +amoadd.w ra, s9, (ra) +amoadd.w ra, s9, (t0) +amoadd.w ra, s9, (a0) +amoadd.w ra, s9, (a5) +amoadd.w ra, s9, (s4) +amoadd.w ra, s9, (s9) +amoadd.w ra, s9, (t6) +amoadd.w ra, t6, (zero) +amoadd.w ra, t6, (ra) +amoadd.w ra, t6, (t0) +amoadd.w ra, t6, (a0) +amoadd.w ra, t6, (a5) +amoadd.w ra, t6, (s4) +amoadd.w ra, t6, (s9) +amoadd.w ra, t6, (t6) +amoadd.w t0, zero, (zero) +amoadd.w t0, zero, (ra) +amoadd.w t0, zero, (t0) +amoadd.w t0, zero, (a0) +amoadd.w t0, zero, (a5) +amoadd.w t0, zero, (s4) +amoadd.w t0, zero, (s9) +amoadd.w t0, zero, (t6) +amoadd.w t0, ra, (zero) +amoadd.w t0, ra, (ra) +amoadd.w t0, ra, (t0) +amoadd.w t0, ra, (a0) +amoadd.w t0, ra, (a5) +amoadd.w t0, ra, (s4) +amoadd.w t0, ra, (s9) +amoadd.w t0, ra, (t6) +amoadd.w t0, t0, (zero) +amoadd.w t0, t0, (ra) +amoadd.w t0, t0, (t0) +amoadd.w t0, t0, (a0) +amoadd.w t0, t0, (a5) +amoadd.w t0, t0, (s4) +amoadd.w t0, t0, (s9) +amoadd.w t0, t0, (t6) +amoadd.w t0, a0, (zero) +amoadd.w t0, a0, (ra) +amoadd.w t0, a0, (t0) +amoadd.w t0, a0, (a0) +amoadd.w t0, a0, (a5) +amoadd.w t0, a0, (s4) +amoadd.w t0, a0, (s9) +amoadd.w t0, a0, (t6) +amoadd.w t0, a5, (zero) +amoadd.w t0, a5, (ra) +amoadd.w t0, a5, (t0) +amoadd.w t0, a5, (a0) +amoadd.w t0, a5, (a5) +amoadd.w t0, a5, (s4) +amoadd.w t0, a5, (s9) +amoadd.w t0, a5, (t6) +amoadd.w t0, s4, (zero) +amoadd.w t0, s4, (ra) +amoadd.w t0, s4, (t0) +amoadd.w t0, s4, (a0) +amoadd.w t0, s4, (a5) +amoadd.w t0, s4, (s4) +amoadd.w t0, s4, (s9) +amoadd.w t0, s4, (t6) +amoadd.w t0, s9, (zero) +amoadd.w t0, s9, (ra) +amoadd.w t0, s9, (t0) +amoadd.w t0, s9, (a0) +amoadd.w t0, s9, (a5) +amoadd.w t0, s9, (s4) +amoadd.w t0, s9, (s9) +amoadd.w t0, s9, (t6) +amoadd.w t0, t6, (zero) +amoadd.w t0, t6, (ra) +amoadd.w t0, t6, (t0) +amoadd.w t0, t6, (a0) +amoadd.w t0, t6, (a5) +amoadd.w t0, t6, (s4) +amoadd.w t0, t6, (s9) +amoadd.w t0, t6, (t6) +amoadd.w a0, zero, (zero) +amoadd.w a0, zero, (ra) +amoadd.w a0, zero, (t0) +amoadd.w a0, zero, (a0) +amoadd.w a0, zero, (a5) +amoadd.w a0, zero, (s4) +amoadd.w a0, zero, (s9) +amoadd.w a0, zero, (t6) +amoadd.w a0, ra, (zero) +amoadd.w a0, ra, (ra) +amoadd.w a0, ra, (t0) +amoadd.w a0, ra, (a0) +amoadd.w a0, ra, (a5) +amoadd.w a0, ra, (s4) +amoadd.w a0, ra, (s9) +amoadd.w a0, ra, (t6) +amoadd.w a0, t0, (zero) +amoadd.w a0, t0, (ra) +amoadd.w a0, t0, (t0) +amoadd.w a0, t0, (a0) +amoadd.w a0, t0, (a5) +amoadd.w a0, t0, (s4) +amoadd.w a0, t0, (s9) +amoadd.w a0, t0, (t6) +amoadd.w a0, a0, (zero) +amoadd.w a0, a0, (ra) +amoadd.w a0, a0, (t0) +amoadd.w a0, a0, (a0) +amoadd.w a0, a0, (a5) +amoadd.w a0, a0, (s4) +amoadd.w a0, a0, (s9) +amoadd.w a0, a0, (t6) +amoadd.w a0, a5, (zero) +amoadd.w a0, a5, (ra) +amoadd.w a0, a5, (t0) +amoadd.w a0, a5, (a0) +amoadd.w a0, a5, (a5) +amoadd.w a0, a5, (s4) +amoadd.w a0, a5, (s9) +amoadd.w a0, a5, (t6) +amoadd.w a0, s4, (zero) +amoadd.w a0, s4, (ra) +amoadd.w a0, s4, (t0) +amoadd.w a0, s4, (a0) +amoadd.w a0, s4, (a5) +amoadd.w a0, s4, (s4) +amoadd.w a0, s4, (s9) +amoadd.w a0, s4, (t6) +amoadd.w a0, s9, (zero) +amoadd.w a0, s9, (ra) +amoadd.w a0, s9, (t0) +amoadd.w a0, s9, (a0) +amoadd.w a0, s9, (a5) +amoadd.w a0, s9, (s4) +amoadd.w a0, s9, (s9) +amoadd.w a0, s9, (t6) +amoadd.w a0, t6, (zero) +amoadd.w a0, t6, (ra) +amoadd.w a0, t6, (t0) +amoadd.w a0, t6, (a0) +amoadd.w a0, t6, (a5) +amoadd.w a0, t6, (s4) +amoadd.w a0, t6, (s9) +amoadd.w a0, t6, (t6) +amoadd.w a5, zero, (zero) +amoadd.w a5, zero, (ra) +amoadd.w a5, zero, (t0) +amoadd.w a5, zero, (a0) +amoadd.w a5, zero, (a5) +amoadd.w a5, zero, (s4) +amoadd.w a5, zero, (s9) +amoadd.w a5, zero, (t6) +amoadd.w a5, ra, (zero) +amoadd.w a5, ra, (ra) +amoadd.w a5, ra, (t0) +amoadd.w a5, ra, (a0) +amoadd.w a5, ra, (a5) +amoadd.w a5, ra, (s4) +amoadd.w a5, ra, (s9) +amoadd.w a5, ra, (t6) +amoadd.w a5, t0, (zero) +amoadd.w a5, t0, (ra) +amoadd.w a5, t0, (t0) +amoadd.w a5, t0, (a0) +amoadd.w a5, t0, (a5) +amoadd.w a5, t0, (s4) +amoadd.w a5, t0, (s9) +amoadd.w a5, t0, (t6) +amoadd.w a5, a0, (zero) +amoadd.w a5, a0, (ra) +amoadd.w a5, a0, (t0) +amoadd.w a5, a0, (a0) +amoadd.w a5, a0, (a5) +amoadd.w a5, a0, (s4) +amoadd.w a5, a0, (s9) +amoadd.w a5, a0, (t6) +amoadd.w a5, a5, (zero) +amoadd.w a5, a5, (ra) +amoadd.w a5, a5, (t0) +amoadd.w a5, a5, (a0) +amoadd.w a5, a5, (a5) +amoadd.w a5, a5, (s4) +amoadd.w a5, a5, (s9) +amoadd.w a5, a5, (t6) +amoadd.w a5, s4, (zero) +amoadd.w a5, s4, (ra) +amoadd.w a5, s4, (t0) +amoadd.w a5, s4, (a0) +amoadd.w a5, s4, (a5) +amoadd.w a5, s4, (s4) +amoadd.w a5, s4, (s9) +amoadd.w a5, s4, (t6) +amoadd.w a5, s9, (zero) +amoadd.w a5, s9, (ra) +amoadd.w a5, s9, (t0) +amoadd.w a5, s9, (a0) +amoadd.w a5, s9, (a5) +amoadd.w a5, s9, (s4) +amoadd.w a5, s9, (s9) +amoadd.w a5, s9, (t6) +amoadd.w a5, t6, (zero) +amoadd.w a5, t6, (ra) +amoadd.w a5, t6, (t0) +amoadd.w a5, t6, (a0) +amoadd.w a5, t6, (a5) +amoadd.w a5, t6, (s4) +amoadd.w a5, t6, (s9) +amoadd.w a5, t6, (t6) +amoadd.w s4, zero, (zero) +amoadd.w s4, zero, (ra) +amoadd.w s4, zero, (t0) +amoadd.w s4, zero, (a0) +amoadd.w s4, zero, (a5) +amoadd.w s4, zero, (s4) +amoadd.w s4, zero, (s9) +amoadd.w s4, zero, (t6) +amoadd.w s4, ra, (zero) +amoadd.w s4, ra, (ra) +amoadd.w s4, ra, (t0) +amoadd.w s4, ra, (a0) +amoadd.w s4, ra, (a5) +amoadd.w s4, ra, (s4) +amoadd.w s4, ra, (s9) +amoadd.w s4, ra, (t6) +amoadd.w s4, t0, (zero) +amoadd.w s4, t0, (ra) +amoadd.w s4, t0, (t0) +amoadd.w s4, t0, (a0) +amoadd.w s4, t0, (a5) +amoadd.w s4, t0, (s4) +amoadd.w s4, t0, (s9) +amoadd.w s4, t0, (t6) +amoadd.w s4, a0, (zero) +amoadd.w s4, a0, (ra) +amoadd.w s4, a0, (t0) +amoadd.w s4, a0, (a0) +amoadd.w s4, a0, (a5) +amoadd.w s4, a0, (s4) +amoadd.w s4, a0, (s9) +amoadd.w s4, a0, (t6) +amoadd.w s4, a5, (zero) +amoadd.w s4, a5, (ra) +amoadd.w s4, a5, (t0) +amoadd.w s4, a5, (a0) +amoadd.w s4, a5, (a5) +amoadd.w s4, a5, (s4) +amoadd.w s4, a5, (s9) +amoadd.w s4, a5, (t6) +amoadd.w s4, s4, (zero) +amoadd.w s4, s4, (ra) +amoadd.w s4, s4, (t0) +amoadd.w s4, s4, (a0) +amoadd.w s4, s4, (a5) +amoadd.w s4, s4, (s4) +amoadd.w s4, s4, (s9) +amoadd.w s4, s4, (t6) +amoadd.w s4, s9, (zero) +amoadd.w s4, s9, (ra) +amoadd.w s4, s9, (t0) +amoadd.w s4, s9, (a0) +amoadd.w s4, s9, (a5) +amoadd.w s4, s9, (s4) +amoadd.w s4, s9, (s9) +amoadd.w s4, s9, (t6) +amoadd.w s4, t6, (zero) +amoadd.w s4, t6, (ra) +amoadd.w s4, t6, (t0) +amoadd.w s4, t6, (a0) +amoadd.w s4, t6, (a5) +amoadd.w s4, t6, (s4) +amoadd.w s4, t6, (s9) +amoadd.w s4, t6, (t6) +amoadd.w s9, zero, (zero) +amoadd.w s9, zero, (ra) +amoadd.w s9, zero, (t0) +amoadd.w s9, zero, (a0) +amoadd.w s9, zero, (a5) +amoadd.w s9, zero, (s4) +amoadd.w s9, zero, (s9) +amoadd.w s9, zero, (t6) +amoadd.w s9, ra, (zero) +amoadd.w s9, ra, (ra) +amoadd.w s9, ra, (t0) +amoadd.w s9, ra, (a0) +amoadd.w s9, ra, (a5) +amoadd.w s9, ra, (s4) +amoadd.w s9, ra, (s9) +amoadd.w s9, ra, (t6) +amoadd.w s9, t0, (zero) +amoadd.w s9, t0, (ra) +amoadd.w s9, t0, (t0) +amoadd.w s9, t0, (a0) +amoadd.w s9, t0, (a5) +amoadd.w s9, t0, (s4) +amoadd.w s9, t0, (s9) +amoadd.w s9, t0, (t6) +amoadd.w s9, a0, (zero) +amoadd.w s9, a0, (ra) +amoadd.w s9, a0, (t0) +amoadd.w s9, a0, (a0) +amoadd.w s9, a0, (a5) +amoadd.w s9, a0, (s4) +amoadd.w s9, a0, (s9) +amoadd.w s9, a0, (t6) +amoadd.w s9, a5, (zero) +amoadd.w s9, a5, (ra) +amoadd.w s9, a5, (t0) +amoadd.w s9, a5, (a0) +amoadd.w s9, a5, (a5) +amoadd.w s9, a5, (s4) +amoadd.w s9, a5, (s9) +amoadd.w s9, a5, (t6) +amoadd.w s9, s4, (zero) +amoadd.w s9, s4, (ra) +amoadd.w s9, s4, (t0) +amoadd.w s9, s4, (a0) +amoadd.w s9, s4, (a5) +amoadd.w s9, s4, (s4) +amoadd.w s9, s4, (s9) +amoadd.w s9, s4, (t6) +amoadd.w s9, s9, (zero) +amoadd.w s9, s9, (ra) +amoadd.w s9, s9, (t0) +amoadd.w s9, s9, (a0) +amoadd.w s9, s9, (a5) +amoadd.w s9, s9, (s4) +amoadd.w s9, s9, (s9) +amoadd.w s9, s9, (t6) +amoadd.w s9, t6, (zero) +amoadd.w s9, t6, (ra) +amoadd.w s9, t6, (t0) +amoadd.w s9, t6, (a0) +amoadd.w s9, t6, (a5) +amoadd.w s9, t6, (s4) +amoadd.w s9, t6, (s9) +amoadd.w s9, t6, (t6) +amoadd.w t6, zero, (zero) +amoadd.w t6, zero, (ra) +amoadd.w t6, zero, (t0) +amoadd.w t6, zero, (a0) +amoadd.w t6, zero, (a5) +amoadd.w t6, zero, (s4) +amoadd.w t6, zero, (s9) +amoadd.w t6, zero, (t6) +amoadd.w t6, ra, (zero) +amoadd.w t6, ra, (ra) +amoadd.w t6, ra, (t0) +amoadd.w t6, ra, (a0) +amoadd.w t6, ra, (a5) +amoadd.w t6, ra, (s4) +amoadd.w t6, ra, (s9) +amoadd.w t6, ra, (t6) +amoadd.w t6, t0, (zero) +amoadd.w t6, t0, (ra) +amoadd.w t6, t0, (t0) +amoadd.w t6, t0, (a0) +amoadd.w t6, t0, (a5) +amoadd.w t6, t0, (s4) +amoadd.w t6, t0, (s9) +amoadd.w t6, t0, (t6) +amoadd.w t6, a0, (zero) +amoadd.w t6, a0, (ra) +amoadd.w t6, a0, (t0) +amoadd.w t6, a0, (a0) +amoadd.w t6, a0, (a5) +amoadd.w t6, a0, (s4) +amoadd.w t6, a0, (s9) +amoadd.w t6, a0, (t6) +amoadd.w t6, a5, (zero) +amoadd.w t6, a5, (ra) +amoadd.w t6, a5, (t0) +amoadd.w t6, a5, (a0) +amoadd.w t6, a5, (a5) +amoadd.w t6, a5, (s4) +amoadd.w t6, a5, (s9) +amoadd.w t6, a5, (t6) +amoadd.w t6, s4, (zero) +amoadd.w t6, s4, (ra) +amoadd.w t6, s4, (t0) +amoadd.w t6, s4, (a0) +amoadd.w t6, s4, (a5) +amoadd.w t6, s4, (s4) +amoadd.w t6, s4, (s9) +amoadd.w t6, s4, (t6) +amoadd.w t6, s9, (zero) +amoadd.w t6, s9, (ra) +amoadd.w t6, s9, (t0) +amoadd.w t6, s9, (a0) +amoadd.w t6, s9, (a5) +amoadd.w t6, s9, (s4) +amoadd.w t6, s9, (s9) +amoadd.w t6, s9, (t6) +amoadd.w t6, t6, (zero) +amoadd.w t6, t6, (ra) +amoadd.w t6, t6, (t0) +amoadd.w t6, t6, (a0) +amoadd.w t6, t6, (a5) +amoadd.w t6, t6, (s4) +amoadd.w t6, t6, (s9) +amoadd.w t6, t6, (t6) + diff --git a/tests/riscv/a-extension/amoadd.w.bin b/tests/riscv/a-extension/amoadd.w.bin new file mode 100644 index 0000000000000000000000000000000000000000..8f7b81f837465f4ee328f9e579c08fe77d04457f GIT binary patch literal 2048 zcmWmEVTWB;7>40YsS+Vah!7!Tvu(D``U_F2ROt~SM95!?Ql(1AVp%MU_pcqp7{)NY z-VcxG{j|4x-_JSa`q{H`llkFUx&BfAq@U{-^3r|MnOE-D`i*|8-^qLTS!X`FKk3i< zi~cI#+&4N?-A#8r^ptR4bmrE5r|Nx!N1_I_!s;Yf5pF?bq4=} zzv5r;SNs+Kg1u(&FZe6|1%Jg~@h=yh!N1_I_!s;Yf5pFGuNnLc{)&IWU-4J`3-+49 zzu>R<7yK1}#lK*$8TcY zX8+Cp*R#&p|7!ou{#W~N_TTJ(wf&Z{|JDAR{jc`l?7!LndeIsCU+ury|7!ou{+s=; zw%;=LzuJGZ|JDAR{WtqxZNFvgf3^Q+|Ev8s`)~HY+J4K}|7!ou{#W~N_TTv5xbGSM zH~u^S8~>gE&i{7O8U8o^JO3O1o&V1NcGemGH~u^S8~>gE&i}@J&+xzT-}&G8@BDZE zw~Nm3zwzJs-}vwRcm6l-dxrmw|IYu$f9JpRzj5C){BQhs{x|+R|DFGh`<~%{@B9z`2mkv;XZYXwAN=q95B>-LJNF~Q|IYv5f9HSjKltCd9~u64{s;d%|AYU* z|IYo$@W1mv_}}>-{15&Q?q`Poga66@!T;oc@_(FkhW~^A$^XIspV literal 0 HcmV?d00001 diff --git a/tests/riscv/a-extension/amoadd.w.disasm b/tests/riscv/a-extension/amoadd.w.disasm new file mode 100644 index 0000000..6f9dae6 --- /dev/null +++ b/tests/riscv/a-extension/amoadd.w.disasm @@ -0,0 +1,512 @@ +amoadd.w zero, zero, (zero) +amoadd.w zero, zero, (ra) +amoadd.w zero, zero, (t0) +amoadd.w zero, zero, (a0) +amoadd.w zero, zero, (a5) +amoadd.w zero, zero, (s4) +amoadd.w zero, zero, (s9) +amoadd.w zero, zero, (t6) +amoadd.w zero, ra, (zero) +amoadd.w zero, ra, (ra) +amoadd.w zero, ra, (t0) +amoadd.w zero, ra, (a0) +amoadd.w zero, ra, (a5) +amoadd.w zero, ra, (s4) +amoadd.w zero, ra, (s9) +amoadd.w zero, ra, (t6) +amoadd.w zero, t0, (zero) +amoadd.w zero, t0, (ra) +amoadd.w zero, t0, (t0) +amoadd.w zero, t0, (a0) +amoadd.w zero, t0, (a5) +amoadd.w zero, t0, (s4) +amoadd.w zero, t0, (s9) +amoadd.w zero, t0, (t6) +amoadd.w zero, a0, (zero) +amoadd.w zero, a0, (ra) +amoadd.w zero, a0, (t0) +amoadd.w zero, a0, (a0) +amoadd.w zero, a0, (a5) +amoadd.w zero, a0, (s4) +amoadd.w zero, a0, (s9) +amoadd.w zero, a0, (t6) +amoadd.w zero, a5, (zero) +amoadd.w zero, a5, (ra) +amoadd.w zero, a5, (t0) +amoadd.w zero, a5, (a0) +amoadd.w zero, a5, (a5) +amoadd.w zero, a5, (s4) +amoadd.w zero, a5, (s9) +amoadd.w zero, a5, (t6) +amoadd.w zero, s4, (zero) +amoadd.w zero, s4, (ra) +amoadd.w zero, s4, (t0) +amoadd.w zero, s4, (a0) +amoadd.w zero, s4, (a5) +amoadd.w zero, s4, (s4) +amoadd.w zero, s4, (s9) +amoadd.w zero, s4, (t6) +amoadd.w zero, s9, (zero) +amoadd.w zero, s9, (ra) +amoadd.w zero, s9, (t0) +amoadd.w zero, s9, (a0) +amoadd.w zero, s9, (a5) +amoadd.w zero, s9, (s4) +amoadd.w zero, s9, (s9) +amoadd.w zero, s9, (t6) +amoadd.w zero, t6, (zero) +amoadd.w zero, t6, (ra) +amoadd.w zero, t6, (t0) +amoadd.w zero, t6, (a0) +amoadd.w zero, t6, (a5) +amoadd.w zero, t6, (s4) +amoadd.w zero, t6, (s9) +amoadd.w zero, t6, (t6) +amoadd.w ra, zero, (zero) +amoadd.w ra, zero, (ra) +amoadd.w ra, zero, (t0) +amoadd.w ra, zero, (a0) +amoadd.w ra, zero, (a5) +amoadd.w ra, zero, (s4) +amoadd.w ra, zero, (s9) +amoadd.w ra, zero, (t6) +amoadd.w ra, ra, (zero) +amoadd.w ra, ra, (ra) +amoadd.w ra, ra, (t0) +amoadd.w ra, ra, (a0) +amoadd.w ra, ra, (a5) +amoadd.w ra, ra, (s4) +amoadd.w ra, ra, (s9) +amoadd.w ra, ra, (t6) +amoadd.w ra, t0, (zero) +amoadd.w ra, t0, (ra) +amoadd.w ra, t0, (t0) +amoadd.w ra, t0, (a0) +amoadd.w ra, t0, (a5) +amoadd.w ra, t0, (s4) +amoadd.w ra, t0, (s9) +amoadd.w ra, t0, (t6) +amoadd.w ra, a0, (zero) +amoadd.w ra, a0, (ra) +amoadd.w ra, a0, (t0) +amoadd.w ra, a0, (a0) +amoadd.w ra, a0, (a5) +amoadd.w ra, a0, (s4) +amoadd.w ra, a0, (s9) +amoadd.w ra, a0, (t6) +amoadd.w ra, a5, (zero) +amoadd.w ra, a5, (ra) +amoadd.w ra, a5, (t0) +amoadd.w ra, a5, (a0) +amoadd.w ra, a5, (a5) +amoadd.w ra, a5, (s4) +amoadd.w ra, a5, (s9) +amoadd.w ra, a5, (t6) +amoadd.w ra, s4, (zero) +amoadd.w ra, s4, (ra) +amoadd.w ra, s4, (t0) +amoadd.w ra, s4, (a0) +amoadd.w ra, s4, (a5) +amoadd.w ra, s4, (s4) +amoadd.w ra, s4, (s9) +amoadd.w ra, s4, (t6) +amoadd.w ra, s9, (zero) +amoadd.w ra, s9, (ra) +amoadd.w ra, s9, (t0) +amoadd.w ra, s9, (a0) +amoadd.w ra, s9, (a5) +amoadd.w ra, s9, (s4) +amoadd.w ra, s9, (s9) +amoadd.w ra, s9, (t6) +amoadd.w ra, t6, (zero) +amoadd.w ra, t6, (ra) +amoadd.w ra, t6, (t0) +amoadd.w ra, t6, (a0) +amoadd.w ra, t6, (a5) +amoadd.w ra, t6, (s4) +amoadd.w ra, t6, (s9) +amoadd.w ra, t6, (t6) +amoadd.w t0, zero, (zero) +amoadd.w t0, zero, (ra) +amoadd.w t0, zero, (t0) +amoadd.w t0, zero, (a0) +amoadd.w t0, zero, (a5) +amoadd.w t0, zero, (s4) +amoadd.w t0, zero, (s9) +amoadd.w t0, zero, (t6) +amoadd.w t0, ra, (zero) +amoadd.w t0, ra, (ra) +amoadd.w t0, ra, (t0) +amoadd.w t0, ra, (a0) +amoadd.w t0, ra, (a5) +amoadd.w t0, ra, (s4) +amoadd.w t0, ra, (s9) +amoadd.w t0, ra, (t6) +amoadd.w t0, t0, (zero) +amoadd.w t0, t0, (ra) +amoadd.w t0, t0, (t0) +amoadd.w t0, t0, (a0) +amoadd.w t0, t0, (a5) +amoadd.w t0, t0, (s4) +amoadd.w t0, t0, (s9) +amoadd.w t0, t0, (t6) +amoadd.w t0, a0, (zero) +amoadd.w t0, a0, (ra) +amoadd.w t0, a0, (t0) +amoadd.w t0, a0, (a0) +amoadd.w t0, a0, (a5) +amoadd.w t0, a0, (s4) +amoadd.w t0, a0, (s9) +amoadd.w t0, a0, (t6) +amoadd.w t0, a5, (zero) +amoadd.w t0, a5, (ra) +amoadd.w t0, a5, (t0) +amoadd.w t0, a5, (a0) +amoadd.w t0, a5, (a5) +amoadd.w t0, a5, (s4) +amoadd.w t0, a5, (s9) +amoadd.w t0, a5, (t6) +amoadd.w t0, s4, (zero) +amoadd.w t0, s4, (ra) +amoadd.w t0, s4, (t0) +amoadd.w t0, s4, (a0) +amoadd.w t0, s4, (a5) +amoadd.w t0, s4, (s4) +amoadd.w t0, s4, (s9) +amoadd.w t0, s4, (t6) +amoadd.w t0, s9, (zero) +amoadd.w t0, s9, (ra) +amoadd.w t0, s9, (t0) +amoadd.w t0, s9, (a0) +amoadd.w t0, s9, (a5) +amoadd.w t0, s9, (s4) +amoadd.w t0, s9, (s9) +amoadd.w t0, s9, (t6) +amoadd.w t0, t6, (zero) +amoadd.w t0, t6, (ra) +amoadd.w t0, t6, (t0) +amoadd.w t0, t6, (a0) +amoadd.w t0, t6, (a5) +amoadd.w t0, t6, (s4) +amoadd.w t0, t6, (s9) +amoadd.w t0, t6, (t6) +amoadd.w a0, zero, (zero) +amoadd.w a0, zero, (ra) +amoadd.w a0, zero, (t0) +amoadd.w a0, zero, (a0) +amoadd.w a0, zero, (a5) +amoadd.w a0, zero, (s4) +amoadd.w a0, zero, (s9) +amoadd.w a0, zero, (t6) +amoadd.w a0, ra, (zero) +amoadd.w a0, ra, (ra) +amoadd.w a0, ra, (t0) +amoadd.w a0, ra, (a0) +amoadd.w a0, ra, (a5) +amoadd.w a0, ra, (s4) +amoadd.w a0, ra, (s9) +amoadd.w a0, ra, (t6) +amoadd.w a0, t0, (zero) +amoadd.w a0, t0, (ra) +amoadd.w a0, t0, (t0) +amoadd.w a0, t0, (a0) +amoadd.w a0, t0, (a5) +amoadd.w a0, t0, (s4) +amoadd.w a0, t0, (s9) +amoadd.w a0, t0, (t6) +amoadd.w a0, a0, (zero) +amoadd.w a0, a0, (ra) +amoadd.w a0, a0, (t0) +amoadd.w a0, a0, (a0) +amoadd.w a0, a0, (a5) +amoadd.w a0, a0, (s4) +amoadd.w a0, a0, (s9) +amoadd.w a0, a0, (t6) +amoadd.w a0, a5, (zero) +amoadd.w a0, a5, (ra) +amoadd.w a0, a5, (t0) +amoadd.w a0, a5, (a0) +amoadd.w a0, a5, (a5) +amoadd.w a0, a5, (s4) +amoadd.w a0, a5, (s9) +amoadd.w a0, a5, (t6) +amoadd.w a0, s4, (zero) +amoadd.w a0, s4, (ra) +amoadd.w a0, s4, (t0) +amoadd.w a0, s4, (a0) +amoadd.w a0, s4, (a5) +amoadd.w a0, s4, (s4) +amoadd.w a0, s4, (s9) +amoadd.w a0, s4, (t6) +amoadd.w a0, s9, (zero) +amoadd.w a0, s9, (ra) +amoadd.w a0, s9, (t0) +amoadd.w a0, s9, (a0) +amoadd.w a0, s9, (a5) +amoadd.w a0, s9, (s4) +amoadd.w a0, s9, (s9) +amoadd.w a0, s9, (t6) +amoadd.w a0, t6, (zero) +amoadd.w a0, t6, (ra) +amoadd.w a0, t6, (t0) +amoadd.w a0, t6, (a0) +amoadd.w a0, t6, (a5) +amoadd.w a0, t6, (s4) +amoadd.w a0, t6, (s9) +amoadd.w a0, t6, (t6) +amoadd.w a5, zero, (zero) +amoadd.w a5, zero, (ra) +amoadd.w a5, zero, (t0) +amoadd.w a5, zero, (a0) +amoadd.w a5, zero, (a5) +amoadd.w a5, zero, (s4) +amoadd.w a5, zero, (s9) +amoadd.w a5, zero, (t6) +amoadd.w a5, ra, (zero) +amoadd.w a5, ra, (ra) +amoadd.w a5, ra, (t0) +amoadd.w a5, ra, (a0) +amoadd.w a5, ra, (a5) +amoadd.w a5, ra, (s4) +amoadd.w a5, ra, (s9) +amoadd.w a5, ra, (t6) +amoadd.w a5, t0, (zero) +amoadd.w a5, t0, (ra) +amoadd.w a5, t0, (t0) +amoadd.w a5, t0, (a0) +amoadd.w a5, t0, (a5) +amoadd.w a5, t0, (s4) +amoadd.w a5, t0, (s9) +amoadd.w a5, t0, (t6) +amoadd.w a5, a0, (zero) +amoadd.w a5, a0, (ra) +amoadd.w a5, a0, (t0) +amoadd.w a5, a0, (a0) +amoadd.w a5, a0, (a5) +amoadd.w a5, a0, (s4) +amoadd.w a5, a0, (s9) +amoadd.w a5, a0, (t6) +amoadd.w a5, a5, (zero) +amoadd.w a5, a5, (ra) +amoadd.w a5, a5, (t0) +amoadd.w a5, a5, (a0) +amoadd.w a5, a5, (a5) +amoadd.w a5, a5, (s4) +amoadd.w a5, a5, (s9) +amoadd.w a5, a5, (t6) +amoadd.w a5, s4, (zero) +amoadd.w a5, s4, (ra) +amoadd.w a5, s4, (t0) +amoadd.w a5, s4, (a0) +amoadd.w a5, s4, (a5) +amoadd.w a5, s4, (s4) +amoadd.w a5, s4, (s9) +amoadd.w a5, s4, (t6) +amoadd.w a5, s9, (zero) +amoadd.w a5, s9, (ra) +amoadd.w a5, s9, (t0) +amoadd.w a5, s9, (a0) +amoadd.w a5, s9, (a5) +amoadd.w a5, s9, (s4) +amoadd.w a5, s9, (s9) +amoadd.w a5, s9, (t6) +amoadd.w a5, t6, (zero) +amoadd.w a5, t6, (ra) +amoadd.w a5, t6, (t0) +amoadd.w a5, t6, (a0) +amoadd.w a5, t6, (a5) +amoadd.w a5, t6, (s4) +amoadd.w a5, t6, (s9) +amoadd.w a5, t6, (t6) +amoadd.w s4, zero, (zero) +amoadd.w s4, zero, (ra) +amoadd.w s4, zero, (t0) +amoadd.w s4, zero, (a0) +amoadd.w s4, zero, (a5) +amoadd.w s4, zero, (s4) +amoadd.w s4, zero, (s9) +amoadd.w s4, zero, (t6) +amoadd.w s4, ra, (zero) +amoadd.w s4, ra, (ra) +amoadd.w s4, ra, (t0) +amoadd.w s4, ra, (a0) +amoadd.w s4, ra, (a5) +amoadd.w s4, ra, (s4) +amoadd.w s4, ra, (s9) +amoadd.w s4, ra, (t6) +amoadd.w s4, t0, (zero) +amoadd.w s4, t0, (ra) +amoadd.w s4, t0, (t0) +amoadd.w s4, t0, (a0) +amoadd.w s4, t0, (a5) +amoadd.w s4, t0, (s4) +amoadd.w s4, t0, (s9) +amoadd.w s4, t0, (t6) +amoadd.w s4, a0, (zero) +amoadd.w s4, a0, (ra) +amoadd.w s4, a0, (t0) +amoadd.w s4, a0, (a0) +amoadd.w s4, a0, (a5) +amoadd.w s4, a0, (s4) +amoadd.w s4, a0, (s9) +amoadd.w s4, a0, (t6) +amoadd.w s4, a5, (zero) +amoadd.w s4, a5, (ra) +amoadd.w s4, a5, (t0) +amoadd.w s4, a5, (a0) +amoadd.w s4, a5, (a5) +amoadd.w s4, a5, (s4) +amoadd.w s4, a5, (s9) +amoadd.w s4, a5, (t6) +amoadd.w s4, s4, (zero) +amoadd.w s4, s4, (ra) +amoadd.w s4, s4, (t0) +amoadd.w s4, s4, (a0) +amoadd.w s4, s4, (a5) +amoadd.w s4, s4, (s4) +amoadd.w s4, s4, (s9) +amoadd.w s4, s4, (t6) +amoadd.w s4, s9, (zero) +amoadd.w s4, s9, (ra) +amoadd.w s4, s9, (t0) +amoadd.w s4, s9, (a0) +amoadd.w s4, s9, (a5) +amoadd.w s4, s9, (s4) +amoadd.w s4, s9, (s9) +amoadd.w s4, s9, (t6) +amoadd.w s4, t6, (zero) +amoadd.w s4, t6, (ra) +amoadd.w s4, t6, (t0) +amoadd.w s4, t6, (a0) +amoadd.w s4, t6, (a5) +amoadd.w s4, t6, (s4) +amoadd.w s4, t6, (s9) +amoadd.w s4, t6, (t6) +amoadd.w s9, zero, (zero) +amoadd.w s9, zero, (ra) +amoadd.w s9, zero, (t0) +amoadd.w s9, zero, (a0) +amoadd.w s9, zero, (a5) +amoadd.w s9, zero, (s4) +amoadd.w s9, zero, (s9) +amoadd.w s9, zero, (t6) +amoadd.w s9, ra, (zero) +amoadd.w s9, ra, (ra) +amoadd.w s9, ra, (t0) +amoadd.w s9, ra, (a0) +amoadd.w s9, ra, (a5) +amoadd.w s9, ra, (s4) +amoadd.w s9, ra, (s9) +amoadd.w s9, ra, (t6) +amoadd.w s9, t0, (zero) +amoadd.w s9, t0, (ra) +amoadd.w s9, t0, (t0) +amoadd.w s9, t0, (a0) +amoadd.w s9, t0, (a5) +amoadd.w s9, t0, (s4) +amoadd.w s9, t0, (s9) +amoadd.w s9, t0, (t6) +amoadd.w s9, a0, (zero) +amoadd.w s9, a0, (ra) +amoadd.w s9, a0, (t0) +amoadd.w s9, a0, (a0) +amoadd.w s9, a0, (a5) +amoadd.w s9, a0, (s4) +amoadd.w s9, a0, (s9) +amoadd.w s9, a0, (t6) +amoadd.w s9, a5, (zero) +amoadd.w s9, a5, (ra) +amoadd.w s9, a5, (t0) +amoadd.w s9, a5, (a0) +amoadd.w s9, a5, (a5) +amoadd.w s9, a5, (s4) +amoadd.w s9, a5, (s9) +amoadd.w s9, a5, (t6) +amoadd.w s9, s4, (zero) +amoadd.w s9, s4, (ra) +amoadd.w s9, s4, (t0) +amoadd.w s9, s4, (a0) +amoadd.w s9, s4, (a5) +amoadd.w s9, s4, (s4) +amoadd.w s9, s4, (s9) +amoadd.w s9, s4, (t6) +amoadd.w s9, s9, (zero) +amoadd.w s9, s9, (ra) +amoadd.w s9, s9, (t0) +amoadd.w s9, s9, (a0) +amoadd.w s9, s9, (a5) +amoadd.w s9, s9, (s4) +amoadd.w s9, s9, (s9) +amoadd.w s9, s9, (t6) +amoadd.w s9, t6, (zero) +amoadd.w s9, t6, (ra) +amoadd.w s9, t6, (t0) +amoadd.w s9, t6, (a0) +amoadd.w s9, t6, (a5) +amoadd.w s9, t6, (s4) +amoadd.w s9, t6, (s9) +amoadd.w s9, t6, (t6) +amoadd.w t6, zero, (zero) +amoadd.w t6, zero, (ra) +amoadd.w t6, zero, (t0) +amoadd.w t6, zero, (a0) +amoadd.w t6, zero, (a5) +amoadd.w t6, zero, (s4) +amoadd.w t6, zero, (s9) +amoadd.w t6, zero, (t6) +amoadd.w t6, ra, (zero) +amoadd.w t6, ra, (ra) +amoadd.w t6, ra, (t0) +amoadd.w t6, ra, (a0) +amoadd.w t6, ra, (a5) +amoadd.w t6, ra, (s4) +amoadd.w t6, ra, (s9) +amoadd.w t6, ra, (t6) +amoadd.w t6, t0, (zero) +amoadd.w t6, t0, (ra) +amoadd.w t6, t0, (t0) +amoadd.w t6, t0, (a0) +amoadd.w t6, t0, (a5) +amoadd.w t6, t0, (s4) +amoadd.w t6, t0, (s9) +amoadd.w t6, t0, (t6) +amoadd.w t6, a0, (zero) +amoadd.w t6, a0, (ra) +amoadd.w t6, a0, (t0) +amoadd.w t6, a0, (a0) +amoadd.w t6, a0, (a5) +amoadd.w t6, a0, (s4) +amoadd.w t6, a0, (s9) +amoadd.w t6, a0, (t6) +amoadd.w t6, a5, (zero) +amoadd.w t6, a5, (ra) +amoadd.w t6, a5, (t0) +amoadd.w t6, a5, (a0) +amoadd.w t6, a5, (a5) +amoadd.w t6, a5, (s4) +amoadd.w t6, a5, (s9) +amoadd.w t6, a5, (t6) +amoadd.w t6, s4, (zero) +amoadd.w t6, s4, (ra) +amoadd.w t6, s4, (t0) +amoadd.w t6, s4, (a0) +amoadd.w t6, s4, (a5) +amoadd.w t6, s4, (s4) +amoadd.w t6, s4, (s9) +amoadd.w t6, s4, (t6) +amoadd.w t6, s9, (zero) +amoadd.w t6, s9, (ra) +amoadd.w t6, s9, (t0) +amoadd.w t6, s9, (a0) +amoadd.w t6, s9, (a5) +amoadd.w t6, s9, (s4) +amoadd.w t6, s9, (s9) +amoadd.w t6, s9, (t6) +amoadd.w t6, t6, (zero) +amoadd.w t6, t6, (ra) +amoadd.w t6, t6, (t0) +amoadd.w t6, t6, (a0) +amoadd.w t6, t6, (a5) +amoadd.w t6, t6, (s4) +amoadd.w t6, t6, (s9) +amoadd.w t6, t6, (t6) diff --git a/tests/riscv/a-extension/amoadd_w.asm b/tests/riscv/a-extension/amoadd_w.asm new file mode 100644 index 0000000..9047cba --- /dev/null +++ b/tests/riscv/a-extension/amoadd_w.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +amoadd.w a0, a2, (a1) + diff --git a/tests/riscv/a-extension/amoadd_w.bin b/tests/riscv/a-extension/amoadd_w.bin new file mode 100644 index 0000000000000000000000000000000000000000..084aba89448521e273d1e8b79f3669f823ad45f6 GIT binary patch literal 4 LcmdO2dXxbG1UUhk literal 0 HcmV?d00001 diff --git a/tests/riscv/a-extension/amoadd_w.disasm b/tests/riscv/a-extension/amoadd_w.disasm new file mode 100644 index 0000000..5aa086d --- /dev/null +++ b/tests/riscv/a-extension/amoadd_w.disasm @@ -0,0 +1 @@ +amoadd.w a0, a2, (a1) diff --git a/tests/riscv/a-extension/amoand.w.asm b/tests/riscv/a-extension/amoand.w.asm new file mode 100644 index 0000000..23d18e4 --- /dev/null +++ b/tests/riscv/a-extension/amoand.w.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +amoand.w zero, zero, (zero) +amoand.w zero, zero, (ra) +amoand.w zero, zero, (t0) +amoand.w zero, zero, (a0) +amoand.w zero, zero, (a5) +amoand.w zero, zero, (s4) +amoand.w zero, zero, (s9) +amoand.w zero, zero, (t6) +amoand.w zero, ra, (zero) +amoand.w zero, ra, (ra) +amoand.w zero, ra, (t0) +amoand.w zero, ra, (a0) +amoand.w zero, ra, (a5) +amoand.w zero, ra, (s4) +amoand.w zero, ra, (s9) +amoand.w zero, ra, (t6) +amoand.w zero, t0, (zero) +amoand.w zero, t0, (ra) +amoand.w zero, t0, (t0) +amoand.w zero, t0, (a0) +amoand.w zero, t0, (a5) +amoand.w zero, t0, (s4) +amoand.w zero, t0, (s9) +amoand.w zero, t0, (t6) +amoand.w zero, a0, (zero) +amoand.w zero, a0, (ra) +amoand.w zero, a0, (t0) +amoand.w zero, a0, (a0) +amoand.w zero, a0, (a5) +amoand.w zero, a0, (s4) +amoand.w zero, a0, (s9) +amoand.w zero, a0, (t6) +amoand.w zero, a5, (zero) +amoand.w zero, a5, (ra) +amoand.w zero, a5, (t0) +amoand.w zero, a5, (a0) +amoand.w zero, a5, (a5) +amoand.w zero, a5, (s4) +amoand.w zero, a5, (s9) +amoand.w zero, a5, (t6) +amoand.w zero, s4, (zero) +amoand.w zero, s4, (ra) +amoand.w zero, s4, (t0) +amoand.w zero, s4, (a0) +amoand.w zero, s4, (a5) +amoand.w zero, s4, (s4) +amoand.w zero, s4, (s9) +amoand.w zero, s4, (t6) +amoand.w zero, s9, (zero) +amoand.w zero, s9, (ra) +amoand.w zero, s9, (t0) +amoand.w zero, s9, (a0) +amoand.w zero, s9, (a5) +amoand.w zero, s9, (s4) +amoand.w zero, s9, (s9) +amoand.w zero, s9, (t6) +amoand.w zero, t6, (zero) +amoand.w zero, t6, (ra) +amoand.w zero, t6, (t0) +amoand.w zero, t6, (a0) +amoand.w zero, t6, (a5) +amoand.w zero, t6, (s4) +amoand.w zero, t6, (s9) +amoand.w zero, t6, (t6) +amoand.w ra, zero, (zero) +amoand.w ra, zero, (ra) +amoand.w ra, zero, (t0) +amoand.w ra, zero, (a0) +amoand.w ra, zero, (a5) +amoand.w ra, zero, (s4) +amoand.w ra, zero, (s9) +amoand.w ra, zero, (t6) +amoand.w ra, ra, (zero) +amoand.w ra, ra, (ra) +amoand.w ra, ra, (t0) +amoand.w ra, ra, (a0) +amoand.w ra, ra, (a5) +amoand.w ra, ra, (s4) +amoand.w ra, ra, (s9) +amoand.w ra, ra, (t6) +amoand.w ra, t0, (zero) +amoand.w ra, t0, (ra) +amoand.w ra, t0, (t0) +amoand.w ra, t0, (a0) +amoand.w ra, t0, (a5) +amoand.w ra, t0, (s4) +amoand.w ra, t0, (s9) +amoand.w ra, t0, (t6) +amoand.w ra, a0, (zero) +amoand.w ra, a0, (ra) +amoand.w ra, a0, (t0) +amoand.w ra, a0, (a0) +amoand.w ra, a0, (a5) +amoand.w ra, a0, (s4) +amoand.w ra, a0, (s9) +amoand.w ra, a0, (t6) +amoand.w ra, a5, (zero) +amoand.w ra, a5, (ra) +amoand.w ra, a5, (t0) +amoand.w ra, a5, (a0) +amoand.w ra, a5, (a5) +amoand.w ra, a5, (s4) +amoand.w ra, a5, (s9) +amoand.w ra, a5, (t6) +amoand.w ra, s4, (zero) +amoand.w ra, s4, (ra) +amoand.w ra, s4, (t0) +amoand.w ra, s4, (a0) +amoand.w ra, s4, (a5) +amoand.w ra, s4, (s4) +amoand.w ra, s4, (s9) +amoand.w ra, s4, (t6) +amoand.w ra, s9, (zero) +amoand.w ra, s9, (ra) +amoand.w ra, s9, (t0) +amoand.w ra, s9, (a0) +amoand.w ra, s9, (a5) +amoand.w ra, s9, (s4) +amoand.w ra, s9, (s9) +amoand.w ra, s9, (t6) +amoand.w ra, t6, (zero) +amoand.w ra, t6, (ra) +amoand.w ra, t6, (t0) +amoand.w ra, t6, (a0) +amoand.w ra, t6, (a5) +amoand.w ra, t6, (s4) +amoand.w ra, t6, (s9) +amoand.w ra, t6, (t6) +amoand.w t0, zero, (zero) +amoand.w t0, zero, (ra) +amoand.w t0, zero, (t0) +amoand.w t0, zero, (a0) +amoand.w t0, zero, (a5) +amoand.w t0, zero, (s4) +amoand.w t0, zero, (s9) +amoand.w t0, zero, (t6) +amoand.w t0, ra, (zero) +amoand.w t0, ra, (ra) +amoand.w t0, ra, (t0) +amoand.w t0, ra, (a0) +amoand.w t0, ra, (a5) +amoand.w t0, ra, (s4) +amoand.w t0, ra, (s9) +amoand.w t0, ra, (t6) +amoand.w t0, t0, (zero) +amoand.w t0, t0, (ra) +amoand.w t0, t0, (t0) +amoand.w t0, t0, (a0) +amoand.w t0, t0, (a5) +amoand.w t0, t0, (s4) +amoand.w t0, t0, (s9) +amoand.w t0, t0, (t6) +amoand.w t0, a0, (zero) +amoand.w t0, a0, (ra) +amoand.w t0, a0, (t0) +amoand.w t0, a0, (a0) +amoand.w t0, a0, (a5) +amoand.w t0, a0, (s4) +amoand.w t0, a0, (s9) +amoand.w t0, a0, (t6) +amoand.w t0, a5, (zero) +amoand.w t0, a5, (ra) +amoand.w t0, a5, (t0) +amoand.w t0, a5, (a0) +amoand.w t0, a5, (a5) +amoand.w t0, a5, (s4) +amoand.w t0, a5, (s9) +amoand.w t0, a5, (t6) +amoand.w t0, s4, (zero) +amoand.w t0, s4, (ra) +amoand.w t0, s4, (t0) +amoand.w t0, s4, (a0) +amoand.w t0, s4, (a5) +amoand.w t0, s4, (s4) +amoand.w t0, s4, (s9) +amoand.w t0, s4, (t6) +amoand.w t0, s9, (zero) +amoand.w t0, s9, (ra) +amoand.w t0, s9, (t0) +amoand.w t0, s9, (a0) +amoand.w t0, s9, (a5) +amoand.w t0, s9, (s4) +amoand.w t0, s9, (s9) +amoand.w t0, s9, (t6) +amoand.w t0, t6, (zero) +amoand.w t0, t6, (ra) +amoand.w t0, t6, (t0) +amoand.w t0, t6, (a0) +amoand.w t0, t6, (a5) +amoand.w t0, t6, (s4) +amoand.w t0, t6, (s9) +amoand.w t0, t6, (t6) +amoand.w a0, zero, (zero) +amoand.w a0, zero, (ra) +amoand.w a0, zero, (t0) +amoand.w a0, zero, (a0) +amoand.w a0, zero, (a5) +amoand.w a0, zero, (s4) +amoand.w a0, zero, (s9) +amoand.w a0, zero, (t6) +amoand.w a0, ra, (zero) +amoand.w a0, ra, (ra) +amoand.w a0, ra, (t0) +amoand.w a0, ra, (a0) +amoand.w a0, ra, (a5) +amoand.w a0, ra, (s4) +amoand.w a0, ra, (s9) +amoand.w a0, ra, (t6) +amoand.w a0, t0, (zero) +amoand.w a0, t0, (ra) +amoand.w a0, t0, (t0) +amoand.w a0, t0, (a0) +amoand.w a0, t0, (a5) +amoand.w a0, t0, (s4) +amoand.w a0, t0, (s9) +amoand.w a0, t0, (t6) +amoand.w a0, a0, (zero) +amoand.w a0, a0, (ra) +amoand.w a0, a0, (t0) +amoand.w a0, a0, (a0) +amoand.w a0, a0, (a5) +amoand.w a0, a0, (s4) +amoand.w a0, a0, (s9) +amoand.w a0, a0, (t6) +amoand.w a0, a5, (zero) +amoand.w a0, a5, (ra) +amoand.w a0, a5, (t0) +amoand.w a0, a5, (a0) +amoand.w a0, a5, (a5) +amoand.w a0, a5, (s4) +amoand.w a0, a5, (s9) +amoand.w a0, a5, (t6) +amoand.w a0, s4, (zero) +amoand.w a0, s4, (ra) +amoand.w a0, s4, (t0) +amoand.w a0, s4, (a0) +amoand.w a0, s4, (a5) +amoand.w a0, s4, (s4) +amoand.w a0, s4, (s9) +amoand.w a0, s4, (t6) +amoand.w a0, s9, (zero) +amoand.w a0, s9, (ra) +amoand.w a0, s9, (t0) +amoand.w a0, s9, (a0) +amoand.w a0, s9, (a5) +amoand.w a0, s9, (s4) +amoand.w a0, s9, (s9) +amoand.w a0, s9, (t6) +amoand.w a0, t6, (zero) +amoand.w a0, t6, (ra) +amoand.w a0, t6, (t0) +amoand.w a0, t6, (a0) +amoand.w a0, t6, (a5) +amoand.w a0, t6, (s4) +amoand.w a0, t6, (s9) +amoand.w a0, t6, (t6) +amoand.w a5, zero, (zero) +amoand.w a5, zero, (ra) +amoand.w a5, zero, (t0) +amoand.w a5, zero, (a0) +amoand.w a5, zero, (a5) +amoand.w a5, zero, (s4) +amoand.w a5, zero, (s9) +amoand.w a5, zero, (t6) +amoand.w a5, ra, (zero) +amoand.w a5, ra, (ra) +amoand.w a5, ra, (t0) +amoand.w a5, ra, (a0) +amoand.w a5, ra, (a5) +amoand.w a5, ra, (s4) +amoand.w a5, ra, (s9) +amoand.w a5, ra, (t6) +amoand.w a5, t0, (zero) +amoand.w a5, t0, (ra) +amoand.w a5, t0, (t0) +amoand.w a5, t0, (a0) +amoand.w a5, t0, (a5) +amoand.w a5, t0, (s4) +amoand.w a5, t0, (s9) +amoand.w a5, t0, (t6) +amoand.w a5, a0, (zero) +amoand.w a5, a0, (ra) +amoand.w a5, a0, (t0) +amoand.w a5, a0, (a0) +amoand.w a5, a0, (a5) +amoand.w a5, a0, (s4) +amoand.w a5, a0, (s9) +amoand.w a5, a0, (t6) +amoand.w a5, a5, (zero) +amoand.w a5, a5, (ra) +amoand.w a5, a5, (t0) +amoand.w a5, a5, (a0) +amoand.w a5, a5, (a5) +amoand.w a5, a5, (s4) +amoand.w a5, a5, (s9) +amoand.w a5, a5, (t6) +amoand.w a5, s4, (zero) +amoand.w a5, s4, (ra) +amoand.w a5, s4, (t0) +amoand.w a5, s4, (a0) +amoand.w a5, s4, (a5) +amoand.w a5, s4, (s4) +amoand.w a5, s4, (s9) +amoand.w a5, s4, (t6) +amoand.w a5, s9, (zero) +amoand.w a5, s9, (ra) +amoand.w a5, s9, (t0) +amoand.w a5, s9, (a0) +amoand.w a5, s9, (a5) +amoand.w a5, s9, (s4) +amoand.w a5, s9, (s9) +amoand.w a5, s9, (t6) +amoand.w a5, t6, (zero) +amoand.w a5, t6, (ra) +amoand.w a5, t6, (t0) +amoand.w a5, t6, (a0) +amoand.w a5, t6, (a5) +amoand.w a5, t6, (s4) +amoand.w a5, t6, (s9) +amoand.w a5, t6, (t6) +amoand.w s4, zero, (zero) +amoand.w s4, zero, (ra) +amoand.w s4, zero, (t0) +amoand.w s4, zero, (a0) +amoand.w s4, zero, (a5) +amoand.w s4, zero, (s4) +amoand.w s4, zero, (s9) +amoand.w s4, zero, (t6) +amoand.w s4, ra, (zero) +amoand.w s4, ra, (ra) +amoand.w s4, ra, (t0) +amoand.w s4, ra, (a0) +amoand.w s4, ra, (a5) +amoand.w s4, ra, (s4) +amoand.w s4, ra, (s9) +amoand.w s4, ra, (t6) +amoand.w s4, t0, (zero) +amoand.w s4, t0, (ra) +amoand.w s4, t0, (t0) +amoand.w s4, t0, (a0) +amoand.w s4, t0, (a5) +amoand.w s4, t0, (s4) +amoand.w s4, t0, (s9) +amoand.w s4, t0, (t6) +amoand.w s4, a0, (zero) +amoand.w s4, a0, (ra) +amoand.w s4, a0, (t0) +amoand.w s4, a0, (a0) +amoand.w s4, a0, (a5) +amoand.w s4, a0, (s4) +amoand.w s4, a0, (s9) +amoand.w s4, a0, (t6) +amoand.w s4, a5, (zero) +amoand.w s4, a5, (ra) +amoand.w s4, a5, (t0) +amoand.w s4, a5, (a0) +amoand.w s4, a5, (a5) +amoand.w s4, a5, (s4) +amoand.w s4, a5, (s9) +amoand.w s4, a5, (t6) +amoand.w s4, s4, (zero) +amoand.w s4, s4, (ra) +amoand.w s4, s4, (t0) +amoand.w s4, s4, (a0) +amoand.w s4, s4, (a5) +amoand.w s4, s4, (s4) +amoand.w s4, s4, (s9) +amoand.w s4, s4, (t6) +amoand.w s4, s9, (zero) +amoand.w s4, s9, (ra) +amoand.w s4, s9, (t0) +amoand.w s4, s9, (a0) +amoand.w s4, s9, (a5) +amoand.w s4, s9, (s4) +amoand.w s4, s9, (s9) +amoand.w s4, s9, (t6) +amoand.w s4, t6, (zero) +amoand.w s4, t6, (ra) +amoand.w s4, t6, (t0) +amoand.w s4, t6, (a0) +amoand.w s4, t6, (a5) +amoand.w s4, t6, (s4) +amoand.w s4, t6, (s9) +amoand.w s4, t6, (t6) +amoand.w s9, zero, (zero) +amoand.w s9, zero, (ra) +amoand.w s9, zero, (t0) +amoand.w s9, zero, (a0) +amoand.w s9, zero, (a5) +amoand.w s9, zero, (s4) +amoand.w s9, zero, (s9) +amoand.w s9, zero, (t6) +amoand.w s9, ra, (zero) +amoand.w s9, ra, (ra) +amoand.w s9, ra, (t0) +amoand.w s9, ra, (a0) +amoand.w s9, ra, (a5) +amoand.w s9, ra, (s4) +amoand.w s9, ra, (s9) +amoand.w s9, ra, (t6) +amoand.w s9, t0, (zero) +amoand.w s9, t0, (ra) +amoand.w s9, t0, (t0) +amoand.w s9, t0, (a0) +amoand.w s9, t0, (a5) +amoand.w s9, t0, (s4) +amoand.w s9, t0, (s9) +amoand.w s9, t0, (t6) +amoand.w s9, a0, (zero) +amoand.w s9, a0, (ra) +amoand.w s9, a0, (t0) +amoand.w s9, a0, (a0) +amoand.w s9, a0, (a5) +amoand.w s9, a0, (s4) +amoand.w s9, a0, (s9) +amoand.w s9, a0, (t6) +amoand.w s9, a5, (zero) +amoand.w s9, a5, (ra) +amoand.w s9, a5, (t0) +amoand.w s9, a5, (a0) +amoand.w s9, a5, (a5) +amoand.w s9, a5, (s4) +amoand.w s9, a5, (s9) +amoand.w s9, a5, (t6) +amoand.w s9, s4, (zero) +amoand.w s9, s4, (ra) +amoand.w s9, s4, (t0) +amoand.w s9, s4, (a0) +amoand.w s9, s4, (a5) +amoand.w s9, s4, (s4) +amoand.w s9, s4, (s9) +amoand.w s9, s4, (t6) +amoand.w s9, s9, (zero) +amoand.w s9, s9, (ra) +amoand.w s9, s9, (t0) +amoand.w s9, s9, (a0) +amoand.w s9, s9, (a5) +amoand.w s9, s9, (s4) +amoand.w s9, s9, (s9) +amoand.w s9, s9, (t6) +amoand.w s9, t6, (zero) +amoand.w s9, t6, (ra) +amoand.w s9, t6, (t0) +amoand.w s9, t6, (a0) +amoand.w s9, t6, (a5) +amoand.w s9, t6, (s4) +amoand.w s9, t6, (s9) +amoand.w s9, t6, (t6) +amoand.w t6, zero, (zero) +amoand.w t6, zero, (ra) +amoand.w t6, zero, (t0) +amoand.w t6, zero, (a0) +amoand.w t6, zero, (a5) +amoand.w t6, zero, (s4) +amoand.w t6, zero, (s9) +amoand.w t6, zero, (t6) +amoand.w t6, ra, (zero) +amoand.w t6, ra, (ra) +amoand.w t6, ra, (t0) +amoand.w t6, ra, (a0) +amoand.w t6, ra, (a5) +amoand.w t6, ra, (s4) +amoand.w t6, ra, (s9) +amoand.w t6, ra, (t6) +amoand.w t6, t0, (zero) +amoand.w t6, t0, (ra) +amoand.w t6, t0, (t0) +amoand.w t6, t0, (a0) +amoand.w t6, t0, (a5) +amoand.w t6, t0, (s4) +amoand.w t6, t0, (s9) +amoand.w t6, t0, (t6) +amoand.w t6, a0, (zero) +amoand.w t6, a0, (ra) +amoand.w t6, a0, (t0) +amoand.w t6, a0, (a0) +amoand.w t6, a0, (a5) +amoand.w t6, a0, (s4) +amoand.w t6, a0, (s9) +amoand.w t6, a0, (t6) +amoand.w t6, a5, (zero) +amoand.w t6, a5, (ra) +amoand.w t6, a5, (t0) +amoand.w t6, a5, (a0) +amoand.w t6, a5, (a5) +amoand.w t6, a5, (s4) +amoand.w t6, a5, (s9) +amoand.w t6, a5, (t6) +amoand.w t6, s4, (zero) +amoand.w t6, s4, (ra) +amoand.w t6, s4, (t0) +amoand.w t6, s4, (a0) +amoand.w t6, s4, (a5) +amoand.w t6, s4, (s4) +amoand.w t6, s4, (s9) +amoand.w t6, s4, (t6) +amoand.w t6, s9, (zero) +amoand.w t6, s9, (ra) +amoand.w t6, s9, (t0) +amoand.w t6, s9, (a0) +amoand.w t6, s9, (a5) +amoand.w t6, s9, (s4) +amoand.w t6, s9, (s9) +amoand.w t6, s9, (t6) +amoand.w t6, t6, (zero) +amoand.w t6, t6, (ra) +amoand.w t6, t6, (t0) +amoand.w t6, t6, (a0) +amoand.w t6, t6, (a5) +amoand.w t6, t6, (s4) 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literal 0 HcmV?d00001 diff --git a/tests/riscv/a-extension/amomaxu.w.disasm b/tests/riscv/a-extension/amomaxu.w.disasm new file mode 100644 index 0000000..4eb2732 --- /dev/null +++ b/tests/riscv/a-extension/amomaxu.w.disasm @@ -0,0 +1,512 @@ +amomaxu.w zero, zero, (zero) +amomaxu.w zero, zero, (ra) +amomaxu.w zero, zero, (t0) +amomaxu.w zero, zero, (a0) +amomaxu.w zero, zero, (a5) +amomaxu.w zero, zero, (s4) +amomaxu.w zero, zero, (s9) +amomaxu.w zero, zero, (t6) +amomaxu.w zero, ra, (zero) +amomaxu.w zero, ra, (ra) +amomaxu.w zero, ra, (t0) +amomaxu.w zero, ra, (a0) +amomaxu.w zero, ra, (a5) +amomaxu.w zero, ra, (s4) +amomaxu.w zero, ra, (s9) +amomaxu.w zero, ra, (t6) +amomaxu.w zero, t0, (zero) +amomaxu.w zero, t0, (ra) +amomaxu.w zero, t0, (t0) +amomaxu.w zero, t0, (a0) +amomaxu.w zero, t0, (a5) +amomaxu.w zero, t0, (s4) +amomaxu.w zero, t0, (s9) +amomaxu.w zero, t0, (t6) +amomaxu.w zero, a0, (zero) +amomaxu.w zero, a0, (ra) +amomaxu.w zero, a0, (t0) +amomaxu.w zero, a0, (a0) +amomaxu.w zero, a0, (a5) +amomaxu.w zero, a0, (s4) +amomaxu.w zero, a0, (s9) +amomaxu.w zero, a0, (t6) +amomaxu.w zero, a5, (zero) +amomaxu.w zero, a5, (ra) +amomaxu.w zero, a5, (t0) +amomaxu.w zero, a5, (a0) +amomaxu.w zero, a5, (a5) +amomaxu.w zero, a5, (s4) +amomaxu.w zero, a5, (s9) +amomaxu.w zero, a5, (t6) +amomaxu.w zero, s4, (zero) +amomaxu.w zero, s4, (ra) +amomaxu.w zero, s4, (t0) +amomaxu.w zero, s4, (a0) +amomaxu.w zero, s4, (a5) +amomaxu.w zero, s4, (s4) +amomaxu.w zero, s4, (s9) +amomaxu.w zero, s4, (t6) +amomaxu.w zero, s9, (zero) +amomaxu.w zero, s9, (ra) +amomaxu.w zero, s9, (t0) +amomaxu.w zero, s9, (a0) +amomaxu.w zero, s9, (a5) +amomaxu.w zero, s9, (s4) +amomaxu.w zero, s9, (s9) +amomaxu.w zero, s9, (t6) +amomaxu.w zero, t6, (zero) +amomaxu.w zero, t6, (ra) +amomaxu.w zero, t6, (t0) +amomaxu.w zero, t6, (a0) +amomaxu.w zero, t6, (a5) +amomaxu.w zero, t6, (s4) +amomaxu.w zero, t6, (s9) +amomaxu.w zero, t6, (t6) +amomaxu.w ra, zero, (zero) +amomaxu.w ra, zero, (ra) +amomaxu.w ra, zero, (t0) +amomaxu.w ra, zero, (a0) +amomaxu.w ra, zero, (a5) +amomaxu.w ra, zero, (s4) +amomaxu.w ra, zero, (s9) +amomaxu.w ra, zero, (t6) +amomaxu.w ra, ra, (zero) +amomaxu.w ra, ra, (ra) +amomaxu.w ra, ra, (t0) +amomaxu.w ra, ra, (a0) +amomaxu.w ra, ra, (a5) +amomaxu.w ra, ra, (s4) +amomaxu.w ra, ra, (s9) +amomaxu.w ra, ra, (t6) +amomaxu.w ra, t0, (zero) +amomaxu.w ra, t0, (ra) +amomaxu.w ra, t0, (t0) +amomaxu.w ra, t0, (a0) +amomaxu.w ra, t0, (a5) +amomaxu.w ra, t0, (s4) +amomaxu.w ra, t0, (s9) +amomaxu.w ra, t0, (t6) +amomaxu.w ra, a0, (zero) +amomaxu.w ra, a0, (ra) +amomaxu.w ra, a0, (t0) +amomaxu.w ra, a0, (a0) +amomaxu.w ra, a0, (a5) +amomaxu.w ra, a0, (s4) +amomaxu.w ra, a0, (s9) +amomaxu.w ra, a0, (t6) +amomaxu.w ra, a5, (zero) +amomaxu.w ra, a5, (ra) +amomaxu.w ra, a5, (t0) +amomaxu.w ra, a5, (a0) +amomaxu.w ra, a5, (a5) +amomaxu.w ra, a5, (s4) +amomaxu.w ra, a5, (s9) +amomaxu.w ra, a5, (t6) +amomaxu.w ra, s4, (zero) +amomaxu.w ra, s4, (ra) +amomaxu.w ra, s4, (t0) +amomaxu.w ra, s4, (a0) +amomaxu.w ra, s4, (a5) +amomaxu.w ra, s4, (s4) +amomaxu.w ra, s4, (s9) +amomaxu.w ra, s4, (t6) +amomaxu.w ra, s9, (zero) +amomaxu.w ra, s9, (ra) +amomaxu.w ra, s9, (t0) +amomaxu.w ra, s9, (a0) +amomaxu.w ra, s9, (a5) +amomaxu.w ra, s9, (s4) +amomaxu.w ra, s9, (s9) +amomaxu.w ra, s9, (t6) +amomaxu.w ra, t6, (zero) +amomaxu.w ra, t6, (ra) +amomaxu.w ra, t6, (t0) +amomaxu.w ra, t6, (a0) +amomaxu.w ra, t6, (a5) +amomaxu.w ra, t6, (s4) +amomaxu.w ra, t6, (s9) +amomaxu.w ra, t6, (t6) +amomaxu.w t0, zero, (zero) +amomaxu.w t0, zero, (ra) +amomaxu.w t0, zero, (t0) +amomaxu.w t0, zero, (a0) +amomaxu.w t0, zero, (a5) +amomaxu.w t0, zero, (s4) +amomaxu.w t0, zero, (s9) +amomaxu.w t0, zero, (t6) +amomaxu.w t0, ra, (zero) +amomaxu.w t0, ra, (ra) +amomaxu.w t0, ra, (t0) +amomaxu.w t0, ra, (a0) +amomaxu.w t0, ra, (a5) +amomaxu.w t0, ra, (s4) +amomaxu.w t0, ra, (s9) +amomaxu.w t0, ra, (t6) +amomaxu.w t0, t0, (zero) +amomaxu.w t0, t0, (ra) +amomaxu.w t0, t0, (t0) +amomaxu.w t0, t0, (a0) +amomaxu.w t0, t0, (a5) +amomaxu.w t0, t0, (s4) +amomaxu.w t0, t0, (s9) +amomaxu.w t0, t0, (t6) +amomaxu.w t0, a0, (zero) +amomaxu.w t0, a0, (ra) +amomaxu.w t0, a0, (t0) +amomaxu.w t0, a0, (a0) +amomaxu.w t0, a0, (a5) +amomaxu.w t0, a0, (s4) +amomaxu.w t0, a0, (s9) +amomaxu.w t0, a0, (t6) +amomaxu.w t0, a5, (zero) +amomaxu.w t0, a5, (ra) +amomaxu.w t0, a5, (t0) +amomaxu.w t0, a5, (a0) +amomaxu.w t0, a5, (a5) +amomaxu.w t0, a5, (s4) +amomaxu.w t0, a5, (s9) +amomaxu.w t0, a5, (t6) +amomaxu.w t0, s4, (zero) +amomaxu.w t0, s4, (ra) +amomaxu.w t0, s4, (t0) +amomaxu.w t0, s4, (a0) +amomaxu.w t0, s4, (a5) +amomaxu.w t0, s4, (s4) +amomaxu.w t0, s4, (s9) +amomaxu.w t0, s4, (t6) +amomaxu.w t0, s9, (zero) +amomaxu.w t0, s9, (ra) +amomaxu.w t0, s9, (t0) +amomaxu.w t0, s9, (a0) +amomaxu.w t0, s9, (a5) +amomaxu.w t0, s9, (s4) +amomaxu.w t0, s9, (s9) +amomaxu.w t0, s9, (t6) +amomaxu.w t0, t6, (zero) +amomaxu.w t0, t6, (ra) +amomaxu.w t0, t6, (t0) +amomaxu.w t0, t6, (a0) +amomaxu.w t0, t6, (a5) +amomaxu.w t0, t6, (s4) +amomaxu.w t0, t6, (s9) +amomaxu.w t0, t6, (t6) +amomaxu.w a0, zero, (zero) +amomaxu.w a0, zero, (ra) +amomaxu.w a0, zero, (t0) +amomaxu.w a0, zero, (a0) +amomaxu.w a0, zero, (a5) +amomaxu.w a0, zero, (s4) +amomaxu.w a0, zero, (s9) +amomaxu.w a0, zero, (t6) +amomaxu.w a0, ra, (zero) +amomaxu.w a0, ra, (ra) +amomaxu.w a0, ra, (t0) +amomaxu.w a0, ra, (a0) +amomaxu.w a0, ra, (a5) +amomaxu.w a0, ra, (s4) +amomaxu.w a0, ra, (s9) +amomaxu.w a0, ra, (t6) +amomaxu.w a0, t0, (zero) +amomaxu.w a0, t0, (ra) +amomaxu.w a0, t0, (t0) +amomaxu.w a0, t0, (a0) +amomaxu.w a0, t0, (a5) +amomaxu.w a0, t0, (s4) +amomaxu.w a0, t0, (s9) +amomaxu.w a0, t0, (t6) +amomaxu.w a0, a0, (zero) +amomaxu.w a0, a0, (ra) +amomaxu.w a0, a0, (t0) +amomaxu.w a0, a0, (a0) +amomaxu.w a0, a0, (a5) +amomaxu.w a0, a0, (s4) +amomaxu.w a0, a0, (s9) +amomaxu.w a0, a0, (t6) +amomaxu.w a0, a5, (zero) +amomaxu.w a0, a5, (ra) +amomaxu.w a0, a5, (t0) +amomaxu.w a0, a5, (a0) +amomaxu.w a0, a5, (a5) +amomaxu.w a0, a5, (s4) +amomaxu.w a0, a5, (s9) +amomaxu.w a0, a5, (t6) +amomaxu.w a0, s4, (zero) +amomaxu.w a0, s4, (ra) +amomaxu.w a0, s4, (t0) +amomaxu.w a0, s4, (a0) +amomaxu.w a0, s4, (a5) +amomaxu.w a0, s4, (s4) +amomaxu.w a0, s4, (s9) +amomaxu.w a0, s4, (t6) +amomaxu.w a0, s9, (zero) +amomaxu.w a0, s9, (ra) +amomaxu.w a0, s9, (t0) +amomaxu.w a0, s9, (a0) +amomaxu.w a0, s9, (a5) +amomaxu.w a0, s9, (s4) +amomaxu.w a0, s9, (s9) +amomaxu.w a0, s9, (t6) +amomaxu.w a0, t6, (zero) +amomaxu.w a0, t6, (ra) +amomaxu.w a0, t6, (t0) +amomaxu.w a0, t6, (a0) +amomaxu.w a0, t6, (a5) +amomaxu.w a0, t6, (s4) +amomaxu.w a0, t6, (s9) +amomaxu.w a0, t6, (t6) +amomaxu.w a5, zero, (zero) +amomaxu.w a5, zero, (ra) +amomaxu.w a5, zero, (t0) +amomaxu.w a5, zero, (a0) +amomaxu.w a5, zero, (a5) +amomaxu.w a5, zero, (s4) +amomaxu.w a5, zero, (s9) +amomaxu.w a5, zero, (t6) +amomaxu.w a5, ra, (zero) +amomaxu.w a5, ra, (ra) +amomaxu.w a5, ra, (t0) +amomaxu.w a5, ra, (a0) +amomaxu.w a5, ra, (a5) +amomaxu.w a5, ra, (s4) +amomaxu.w a5, ra, (s9) +amomaxu.w a5, ra, (t6) +amomaxu.w a5, t0, (zero) +amomaxu.w a5, t0, (ra) +amomaxu.w a5, t0, (t0) +amomaxu.w a5, t0, (a0) +amomaxu.w a5, t0, (a5) +amomaxu.w a5, t0, (s4) +amomaxu.w a5, t0, (s9) +amomaxu.w a5, t0, (t6) +amomaxu.w a5, a0, (zero) +amomaxu.w a5, a0, (ra) +amomaxu.w a5, a0, (t0) +amomaxu.w a5, a0, (a0) +amomaxu.w a5, a0, (a5) +amomaxu.w a5, a0, (s4) +amomaxu.w a5, a0, (s9) +amomaxu.w a5, a0, (t6) +amomaxu.w a5, a5, (zero) +amomaxu.w a5, a5, (ra) +amomaxu.w a5, a5, (t0) +amomaxu.w a5, a5, (a0) +amomaxu.w a5, a5, (a5) +amomaxu.w a5, a5, (s4) +amomaxu.w a5, a5, (s9) +amomaxu.w a5, a5, (t6) +amomaxu.w a5, s4, (zero) +amomaxu.w a5, s4, (ra) +amomaxu.w a5, s4, (t0) +amomaxu.w a5, s4, (a0) +amomaxu.w a5, s4, (a5) +amomaxu.w a5, s4, (s4) +amomaxu.w a5, s4, (s9) +amomaxu.w a5, s4, (t6) +amomaxu.w a5, s9, (zero) +amomaxu.w a5, s9, (ra) +amomaxu.w a5, s9, (t0) +amomaxu.w a5, s9, (a0) +amomaxu.w a5, s9, (a5) +amomaxu.w a5, s9, (s4) +amomaxu.w a5, s9, (s9) +amomaxu.w a5, s9, (t6) +amomaxu.w a5, t6, (zero) +amomaxu.w a5, t6, (ra) +amomaxu.w a5, t6, (t0) +amomaxu.w a5, t6, (a0) +amomaxu.w a5, t6, (a5) +amomaxu.w a5, t6, (s4) +amomaxu.w a5, t6, (s9) +amomaxu.w a5, t6, (t6) +amomaxu.w s4, zero, (zero) +amomaxu.w s4, zero, (ra) +amomaxu.w s4, zero, (t0) +amomaxu.w s4, zero, (a0) +amomaxu.w s4, zero, (a5) +amomaxu.w s4, zero, (s4) +amomaxu.w s4, zero, (s9) +amomaxu.w s4, zero, (t6) +amomaxu.w s4, ra, (zero) +amomaxu.w s4, ra, (ra) +amomaxu.w s4, ra, (t0) +amomaxu.w s4, ra, (a0) +amomaxu.w s4, ra, (a5) +amomaxu.w s4, ra, (s4) +amomaxu.w s4, ra, (s9) +amomaxu.w s4, ra, (t6) +amomaxu.w s4, t0, (zero) +amomaxu.w s4, t0, (ra) +amomaxu.w s4, t0, (t0) +amomaxu.w s4, t0, (a0) +amomaxu.w s4, t0, (a5) +amomaxu.w s4, t0, (s4) +amomaxu.w s4, t0, (s9) +amomaxu.w s4, t0, (t6) +amomaxu.w s4, a0, (zero) +amomaxu.w s4, a0, (ra) +amomaxu.w s4, a0, (t0) +amomaxu.w s4, a0, (a0) +amomaxu.w s4, a0, (a5) +amomaxu.w s4, a0, (s4) +amomaxu.w s4, a0, (s9) +amomaxu.w s4, a0, (t6) +amomaxu.w s4, a5, (zero) +amomaxu.w s4, a5, (ra) +amomaxu.w s4, a5, (t0) +amomaxu.w s4, a5, (a0) +amomaxu.w s4, a5, (a5) +amomaxu.w s4, a5, (s4) +amomaxu.w s4, a5, (s9) +amomaxu.w s4, a5, (t6) +amomaxu.w s4, s4, (zero) +amomaxu.w s4, s4, (ra) +amomaxu.w s4, s4, (t0) +amomaxu.w s4, s4, (a0) +amomaxu.w s4, s4, (a5) +amomaxu.w s4, s4, (s4) +amomaxu.w s4, s4, (s9) +amomaxu.w s4, s4, (t6) +amomaxu.w s4, s9, (zero) +amomaxu.w s4, s9, (ra) +amomaxu.w s4, s9, (t0) +amomaxu.w s4, s9, (a0) +amomaxu.w s4, s9, (a5) +amomaxu.w s4, s9, (s4) +amomaxu.w s4, s9, (s9) +amomaxu.w s4, s9, (t6) +amomaxu.w s4, t6, (zero) +amomaxu.w s4, t6, (ra) +amomaxu.w s4, t6, (t0) +amomaxu.w s4, t6, (a0) +amomaxu.w s4, t6, (a5) +amomaxu.w s4, t6, (s4) +amomaxu.w s4, t6, (s9) +amomaxu.w s4, t6, (t6) +amomaxu.w s9, zero, (zero) +amomaxu.w s9, zero, (ra) +amomaxu.w s9, zero, (t0) +amomaxu.w s9, zero, (a0) +amomaxu.w s9, zero, (a5) +amomaxu.w s9, zero, (s4) +amomaxu.w s9, zero, (s9) +amomaxu.w s9, zero, (t6) +amomaxu.w s9, ra, (zero) +amomaxu.w s9, ra, (ra) +amomaxu.w s9, ra, (t0) +amomaxu.w s9, ra, (a0) +amomaxu.w s9, ra, (a5) +amomaxu.w s9, ra, (s4) +amomaxu.w s9, ra, (s9) +amomaxu.w s9, ra, (t6) +amomaxu.w s9, t0, (zero) +amomaxu.w s9, t0, (ra) +amomaxu.w s9, t0, (t0) +amomaxu.w s9, t0, (a0) +amomaxu.w s9, t0, (a5) +amomaxu.w s9, t0, (s4) +amomaxu.w s9, t0, (s9) +amomaxu.w s9, t0, (t6) +amomaxu.w s9, a0, (zero) +amomaxu.w s9, a0, (ra) +amomaxu.w s9, a0, (t0) +amomaxu.w s9, a0, (a0) +amomaxu.w s9, a0, (a5) +amomaxu.w s9, a0, (s4) +amomaxu.w s9, a0, (s9) +amomaxu.w s9, a0, (t6) +amomaxu.w s9, a5, (zero) +amomaxu.w s9, a5, (ra) +amomaxu.w s9, a5, (t0) +amomaxu.w s9, a5, (a0) +amomaxu.w s9, a5, (a5) +amomaxu.w s9, a5, (s4) +amomaxu.w s9, a5, (s9) +amomaxu.w s9, a5, (t6) +amomaxu.w s9, s4, (zero) +amomaxu.w s9, s4, (ra) +amomaxu.w s9, s4, (t0) +amomaxu.w s9, s4, (a0) +amomaxu.w s9, s4, (a5) +amomaxu.w s9, s4, (s4) +amomaxu.w s9, s4, (s9) +amomaxu.w s9, s4, (t6) +amomaxu.w s9, s9, (zero) +amomaxu.w s9, s9, (ra) +amomaxu.w s9, s9, (t0) +amomaxu.w s9, s9, (a0) +amomaxu.w s9, s9, (a5) +amomaxu.w s9, s9, (s4) +amomaxu.w s9, s9, (s9) +amomaxu.w s9, s9, (t6) +amomaxu.w s9, t6, (zero) +amomaxu.w s9, t6, (ra) +amomaxu.w s9, t6, (t0) +amomaxu.w s9, t6, (a0) +amomaxu.w s9, t6, (a5) +amomaxu.w s9, t6, (s4) +amomaxu.w s9, t6, (s9) +amomaxu.w s9, t6, (t6) +amomaxu.w t6, zero, (zero) +amomaxu.w t6, zero, (ra) +amomaxu.w t6, zero, (t0) +amomaxu.w t6, zero, (a0) +amomaxu.w t6, zero, (a5) +amomaxu.w t6, zero, (s4) +amomaxu.w t6, zero, (s9) +amomaxu.w t6, zero, (t6) +amomaxu.w t6, ra, (zero) +amomaxu.w t6, ra, (ra) +amomaxu.w t6, ra, (t0) +amomaxu.w t6, ra, (a0) +amomaxu.w t6, ra, (a5) +amomaxu.w t6, ra, (s4) +amomaxu.w t6, ra, (s9) +amomaxu.w t6, ra, (t6) +amomaxu.w t6, t0, (zero) +amomaxu.w t6, t0, (ra) +amomaxu.w t6, t0, (t0) +amomaxu.w t6, t0, (a0) +amomaxu.w t6, t0, (a5) +amomaxu.w t6, t0, (s4) +amomaxu.w t6, t0, (s9) +amomaxu.w t6, t0, (t6) +amomaxu.w t6, a0, (zero) +amomaxu.w t6, a0, (ra) +amomaxu.w t6, a0, (t0) +amomaxu.w t6, a0, (a0) +amomaxu.w t6, a0, (a5) +amomaxu.w t6, a0, (s4) +amomaxu.w t6, a0, (s9) +amomaxu.w t6, a0, (t6) +amomaxu.w t6, a5, (zero) +amomaxu.w t6, a5, (ra) +amomaxu.w t6, a5, (t0) +amomaxu.w t6, a5, (a0) +amomaxu.w t6, a5, (a5) +amomaxu.w t6, a5, (s4) +amomaxu.w t6, a5, (s9) +amomaxu.w t6, a5, (t6) +amomaxu.w t6, s4, (zero) +amomaxu.w t6, s4, (ra) +amomaxu.w t6, s4, (t0) +amomaxu.w t6, s4, (a0) +amomaxu.w t6, s4, (a5) +amomaxu.w t6, s4, (s4) +amomaxu.w t6, s4, (s9) +amomaxu.w t6, s4, (t6) +amomaxu.w t6, s9, (zero) +amomaxu.w t6, s9, (ra) +amomaxu.w t6, s9, (t0) +amomaxu.w t6, s9, (a0) +amomaxu.w t6, s9, (a5) +amomaxu.w t6, s9, (s4) +amomaxu.w t6, s9, (s9) +amomaxu.w t6, s9, (t6) +amomaxu.w t6, t6, (zero) +amomaxu.w t6, t6, (ra) +amomaxu.w t6, t6, (t0) +amomaxu.w t6, t6, (a0) +amomaxu.w t6, t6, (a5) +amomaxu.w t6, t6, (s4) +amomaxu.w t6, t6, (s9) +amomaxu.w t6, t6, (t6) diff --git a/tests/riscv/a-extension/amomaxu_w.asm b/tests/riscv/a-extension/amomaxu_w.asm new file mode 100644 index 0000000..fcd8fd4 --- /dev/null +++ b/tests/riscv/a-extension/amomaxu_w.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +amomaxu.w a0, a2, (a1) + diff --git a/tests/riscv/a-extension/amomaxu_w.bin b/tests/riscv/a-extension/amomaxu_w.bin new file mode 100644 index 0000000..a6f174f --- /dev/null +++ b/tests/riscv/a-extension/amomaxu_w.bin @@ -0,0 +1 @@ +/ \ No newline at end of file diff --git a/tests/riscv/a-extension/amomaxu_w.disasm b/tests/riscv/a-extension/amomaxu_w.disasm new file mode 100644 index 0000000..c19cd65 --- /dev/null +++ b/tests/riscv/a-extension/amomaxu_w.disasm @@ -0,0 +1 @@ +amomaxu.w a0, a2, (a1) diff --git a/tests/riscv/a-extension/amomin.w.asm b/tests/riscv/a-extension/amomin.w.asm new file mode 100644 index 0000000..ae23e34 --- /dev/null +++ b/tests/riscv/a-extension/amomin.w.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +amomin.w zero, zero, (zero) +amomin.w zero, zero, (ra) +amomin.w zero, zero, (t0) +amomin.w zero, zero, (a0) +amomin.w zero, zero, (a5) +amomin.w zero, zero, (s4) +amomin.w zero, zero, (s9) +amomin.w zero, zero, (t6) +amomin.w zero, ra, (zero) +amomin.w zero, ra, (ra) +amomin.w zero, ra, (t0) +amomin.w zero, ra, (a0) +amomin.w zero, ra, (a5) +amomin.w zero, ra, (s4) +amomin.w zero, ra, (s9) +amomin.w zero, ra, (t6) +amomin.w zero, t0, (zero) +amomin.w zero, t0, (ra) +amomin.w zero, t0, (t0) +amomin.w zero, t0, (a0) +amomin.w zero, t0, (a5) +amomin.w zero, t0, (s4) +amomin.w zero, t0, (s9) +amomin.w zero, t0, (t6) +amomin.w zero, a0, (zero) +amomin.w zero, a0, (ra) +amomin.w zero, a0, (t0) +amomin.w zero, a0, (a0) +amomin.w zero, a0, (a5) +amomin.w zero, a0, (s4) +amomin.w zero, a0, (s9) +amomin.w zero, a0, (t6) +amomin.w zero, a5, (zero) +amomin.w zero, a5, (ra) +amomin.w zero, a5, (t0) +amomin.w zero, a5, (a0) +amomin.w zero, a5, (a5) +amomin.w zero, a5, (s4) +amomin.w zero, a5, (s9) +amomin.w zero, a5, (t6) +amomin.w zero, s4, (zero) +amomin.w zero, s4, (ra) +amomin.w zero, s4, (t0) +amomin.w zero, s4, (a0) +amomin.w zero, s4, (a5) +amomin.w zero, s4, (s4) +amomin.w zero, s4, (s9) +amomin.w zero, s4, (t6) +amomin.w zero, s9, (zero) +amomin.w zero, s9, (ra) +amomin.w zero, s9, (t0) +amomin.w zero, s9, (a0) +amomin.w zero, s9, (a5) +amomin.w zero, s9, (s4) +amomin.w zero, s9, (s9) +amomin.w zero, s9, (t6) +amomin.w zero, t6, (zero) +amomin.w zero, t6, (ra) +amomin.w zero, t6, (t0) +amomin.w zero, t6, (a0) +amomin.w zero, t6, (a5) +amomin.w zero, t6, (s4) +amomin.w zero, t6, (s9) +amomin.w zero, t6, (t6) +amomin.w ra, zero, (zero) +amomin.w ra, zero, (ra) +amomin.w ra, zero, (t0) +amomin.w ra, zero, (a0) +amomin.w ra, zero, (a5) +amomin.w ra, zero, (s4) +amomin.w ra, zero, (s9) +amomin.w ra, zero, (t6) +amomin.w ra, ra, (zero) +amomin.w ra, ra, (ra) +amomin.w ra, ra, (t0) +amomin.w ra, ra, (a0) +amomin.w ra, ra, (a5) +amomin.w ra, ra, (s4) +amomin.w ra, ra, (s9) +amomin.w ra, ra, (t6) +amomin.w ra, t0, (zero) +amomin.w ra, t0, (ra) +amomin.w ra, t0, (t0) +amomin.w ra, t0, (a0) +amomin.w ra, t0, (a5) +amomin.w ra, t0, (s4) +amomin.w ra, t0, (s9) +amomin.w ra, t0, (t6) +amomin.w ra, a0, (zero) +amomin.w ra, a0, (ra) +amomin.w ra, a0, (t0) +amomin.w ra, a0, (a0) +amomin.w ra, a0, (a5) +amomin.w ra, a0, (s4) +amomin.w ra, a0, (s9) +amomin.w ra, a0, (t6) +amomin.w ra, a5, (zero) +amomin.w ra, a5, (ra) +amomin.w ra, a5, (t0) +amomin.w ra, a5, (a0) +amomin.w ra, a5, (a5) +amomin.w ra, a5, (s4) +amomin.w ra, a5, (s9) +amomin.w ra, a5, (t6) +amomin.w ra, s4, (zero) +amomin.w ra, s4, (ra) +amomin.w ra, s4, (t0) +amomin.w ra, s4, (a0) +amomin.w ra, s4, (a5) +amomin.w ra, s4, (s4) +amomin.w ra, s4, (s9) +amomin.w ra, s4, (t6) +amomin.w ra, s9, (zero) +amomin.w ra, s9, (ra) +amomin.w ra, s9, (t0) +amomin.w ra, s9, (a0) +amomin.w ra, s9, (a5) +amomin.w ra, s9, (s4) +amomin.w ra, s9, (s9) +amomin.w ra, s9, (t6) +amomin.w ra, t6, (zero) +amomin.w ra, t6, (ra) +amomin.w ra, t6, (t0) +amomin.w ra, t6, (a0) +amomin.w ra, t6, (a5) +amomin.w ra, t6, (s4) +amomin.w ra, t6, (s9) +amomin.w ra, t6, (t6) +amomin.w t0, zero, (zero) +amomin.w t0, zero, (ra) +amomin.w t0, zero, (t0) +amomin.w t0, zero, (a0) +amomin.w t0, zero, (a5) +amomin.w t0, zero, (s4) +amomin.w t0, zero, (s9) +amomin.w t0, zero, (t6) +amomin.w t0, ra, (zero) +amomin.w t0, ra, (ra) +amomin.w t0, ra, (t0) +amomin.w t0, ra, (a0) +amomin.w t0, ra, (a5) +amomin.w t0, ra, (s4) +amomin.w t0, ra, (s9) +amomin.w t0, ra, (t6) +amomin.w t0, t0, (zero) +amomin.w t0, t0, (ra) +amomin.w t0, t0, (t0) +amomin.w t0, t0, (a0) +amomin.w t0, t0, (a5) +amomin.w t0, t0, (s4) +amomin.w t0, t0, (s9) +amomin.w t0, t0, (t6) +amomin.w t0, a0, (zero) +amomin.w t0, a0, (ra) +amomin.w t0, a0, (t0) +amomin.w t0, a0, (a0) +amomin.w t0, a0, (a5) +amomin.w t0, a0, (s4) +amomin.w t0, a0, (s9) +amomin.w t0, a0, (t6) +amomin.w t0, a5, (zero) +amomin.w t0, a5, (ra) +amomin.w t0, a5, (t0) +amomin.w t0, a5, (a0) +amomin.w t0, a5, (a5) +amomin.w t0, a5, (s4) +amomin.w t0, a5, (s9) +amomin.w t0, a5, (t6) +amomin.w t0, s4, (zero) +amomin.w t0, s4, (ra) +amomin.w t0, s4, (t0) +amomin.w t0, s4, (a0) +amomin.w t0, s4, (a5) +amomin.w t0, s4, (s4) +amomin.w t0, s4, (s9) +amomin.w t0, s4, (t6) +amomin.w t0, s9, (zero) +amomin.w t0, s9, (ra) +amomin.w t0, s9, (t0) +amomin.w t0, s9, (a0) +amomin.w t0, s9, (a5) +amomin.w t0, s9, (s4) +amomin.w t0, s9, (s9) +amomin.w t0, s9, (t6) +amomin.w t0, t6, (zero) +amomin.w t0, t6, (ra) +amomin.w t0, t6, (t0) +amomin.w t0, t6, (a0) +amomin.w t0, t6, (a5) +amomin.w t0, t6, (s4) +amomin.w t0, t6, (s9) +amomin.w t0, t6, (t6) +amomin.w a0, zero, (zero) +amomin.w a0, zero, (ra) +amomin.w a0, zero, (t0) +amomin.w a0, zero, (a0) +amomin.w a0, zero, (a5) +amomin.w a0, zero, (s4) +amomin.w a0, zero, (s9) +amomin.w a0, zero, (t6) +amomin.w a0, ra, (zero) +amomin.w a0, ra, (ra) +amomin.w a0, ra, (t0) +amomin.w a0, ra, (a0) +amomin.w a0, ra, (a5) +amomin.w a0, ra, (s4) +amomin.w a0, ra, (s9) +amomin.w a0, ra, (t6) +amomin.w a0, t0, (zero) +amomin.w a0, t0, (ra) +amomin.w a0, t0, (t0) +amomin.w a0, t0, (a0) +amomin.w a0, t0, (a5) +amomin.w a0, t0, (s4) +amomin.w a0, t0, (s9) +amomin.w a0, t0, (t6) +amomin.w a0, a0, (zero) +amomin.w a0, a0, (ra) +amomin.w a0, a0, (t0) +amomin.w a0, a0, (a0) +amomin.w a0, a0, (a5) +amomin.w a0, a0, (s4) +amomin.w a0, a0, (s9) +amomin.w a0, a0, (t6) +amomin.w a0, a5, (zero) +amomin.w a0, a5, (ra) +amomin.w a0, a5, (t0) +amomin.w a0, a5, (a0) +amomin.w a0, a5, (a5) +amomin.w a0, a5, (s4) +amomin.w a0, a5, (s9) +amomin.w a0, a5, (t6) +amomin.w a0, s4, (zero) +amomin.w a0, s4, (ra) +amomin.w a0, s4, (t0) +amomin.w a0, s4, (a0) +amomin.w a0, s4, (a5) +amomin.w a0, s4, (s4) +amomin.w a0, s4, (s9) +amomin.w a0, s4, (t6) +amomin.w a0, s9, (zero) +amomin.w a0, s9, (ra) +amomin.w a0, s9, (t0) +amomin.w a0, s9, (a0) +amomin.w a0, s9, (a5) +amomin.w a0, s9, (s4) +amomin.w a0, s9, (s9) +amomin.w a0, s9, (t6) +amomin.w a0, t6, (zero) +amomin.w a0, t6, (ra) +amomin.w a0, t6, (t0) +amomin.w a0, t6, (a0) +amomin.w a0, t6, (a5) +amomin.w a0, t6, (s4) +amomin.w a0, t6, (s9) +amomin.w a0, t6, (t6) +amomin.w a5, zero, (zero) +amomin.w a5, zero, (ra) +amomin.w a5, zero, (t0) +amomin.w a5, zero, (a0) +amomin.w a5, zero, (a5) +amomin.w a5, zero, (s4) +amomin.w a5, zero, (s9) +amomin.w a5, zero, (t6) +amomin.w a5, ra, (zero) +amomin.w a5, ra, (ra) +amomin.w a5, ra, (t0) +amomin.w a5, ra, (a0) +amomin.w a5, ra, (a5) +amomin.w a5, ra, (s4) +amomin.w a5, ra, (s9) +amomin.w a5, ra, (t6) +amomin.w a5, t0, (zero) +amomin.w a5, t0, (ra) +amomin.w a5, t0, (t0) +amomin.w a5, t0, (a0) +amomin.w a5, t0, (a5) +amomin.w a5, t0, (s4) +amomin.w a5, t0, (s9) +amomin.w a5, t0, (t6) +amomin.w a5, a0, (zero) +amomin.w a5, a0, (ra) +amomin.w a5, a0, (t0) +amomin.w a5, a0, (a0) +amomin.w a5, a0, (a5) +amomin.w a5, a0, (s4) +amomin.w a5, a0, (s9) +amomin.w a5, a0, (t6) +amomin.w a5, a5, (zero) +amomin.w a5, a5, (ra) +amomin.w a5, a5, (t0) +amomin.w a5, a5, (a0) +amomin.w a5, a5, (a5) +amomin.w a5, a5, (s4) +amomin.w a5, a5, (s9) +amomin.w a5, a5, (t6) +amomin.w a5, s4, (zero) +amomin.w a5, s4, (ra) +amomin.w a5, s4, (t0) +amomin.w a5, s4, (a0) +amomin.w a5, s4, (a5) +amomin.w a5, s4, (s4) +amomin.w a5, s4, (s9) +amomin.w a5, s4, (t6) +amomin.w a5, s9, (zero) +amomin.w a5, s9, (ra) +amomin.w a5, s9, (t0) +amomin.w a5, s9, (a0) +amomin.w a5, s9, (a5) +amomin.w a5, s9, (s4) +amomin.w a5, s9, (s9) +amomin.w a5, s9, (t6) +amomin.w a5, t6, (zero) +amomin.w a5, t6, (ra) +amomin.w a5, t6, (t0) +amomin.w a5, t6, (a0) +amomin.w a5, t6, (a5) +amomin.w a5, t6, (s4) +amomin.w a5, t6, (s9) +amomin.w a5, t6, (t6) +amomin.w s4, zero, (zero) +amomin.w s4, zero, (ra) +amomin.w s4, zero, (t0) +amomin.w s4, zero, (a0) +amomin.w s4, zero, (a5) +amomin.w s4, zero, (s4) +amomin.w s4, zero, (s9) +amomin.w s4, zero, (t6) +amomin.w s4, ra, (zero) +amomin.w s4, ra, (ra) +amomin.w s4, ra, (t0) +amomin.w s4, ra, (a0) +amomin.w s4, ra, (a5) +amomin.w s4, ra, (s4) +amomin.w s4, ra, (s9) +amomin.w s4, ra, (t6) +amomin.w s4, t0, (zero) +amomin.w s4, t0, (ra) +amomin.w s4, t0, (t0) +amomin.w s4, t0, (a0) +amomin.w s4, t0, (a5) +amomin.w s4, t0, (s4) +amomin.w s4, t0, (s9) +amomin.w s4, t0, (t6) +amomin.w s4, a0, (zero) +amomin.w s4, a0, (ra) +amomin.w s4, a0, (t0) +amomin.w s4, a0, (a0) +amomin.w s4, a0, (a5) +amomin.w s4, a0, (s4) +amomin.w s4, a0, (s9) +amomin.w s4, a0, (t6) +amomin.w s4, a5, (zero) +amomin.w s4, a5, (ra) +amomin.w s4, a5, (t0) +amomin.w s4, a5, (a0) +amomin.w s4, a5, (a5) +amomin.w s4, a5, (s4) +amomin.w s4, a5, (s9) +amomin.w s4, a5, (t6) +amomin.w s4, s4, (zero) +amomin.w s4, s4, (ra) +amomin.w s4, s4, (t0) +amomin.w s4, s4, (a0) +amomin.w s4, s4, (a5) +amomin.w s4, s4, (s4) +amomin.w s4, s4, (s9) +amomin.w s4, s4, (t6) +amomin.w s4, s9, (zero) +amomin.w s4, s9, (ra) +amomin.w s4, s9, (t0) +amomin.w s4, s9, (a0) +amomin.w s4, s9, (a5) +amomin.w s4, s9, (s4) +amomin.w s4, s9, (s9) +amomin.w s4, s9, (t6) +amomin.w s4, t6, (zero) +amomin.w s4, t6, (ra) +amomin.w s4, t6, (t0) +amomin.w s4, t6, (a0) +amomin.w s4, t6, (a5) +amomin.w s4, t6, (s4) +amomin.w s4, t6, (s9) +amomin.w s4, t6, (t6) +amomin.w s9, zero, (zero) +amomin.w s9, zero, (ra) +amomin.w s9, zero, (t0) +amomin.w s9, zero, (a0) +amomin.w s9, zero, (a5) +amomin.w s9, zero, (s4) +amomin.w s9, zero, (s9) +amomin.w s9, zero, (t6) +amomin.w s9, ra, (zero) +amomin.w s9, ra, (ra) +amomin.w s9, ra, (t0) +amomin.w s9, ra, (a0) +amomin.w s9, ra, (a5) +amomin.w s9, ra, (s4) +amomin.w s9, ra, (s9) +amomin.w s9, ra, (t6) +amomin.w s9, t0, (zero) +amomin.w s9, t0, (ra) +amomin.w s9, t0, (t0) +amomin.w s9, t0, (a0) +amomin.w s9, t0, (a5) +amomin.w s9, t0, (s4) +amomin.w s9, t0, (s9) +amomin.w s9, t0, (t6) +amomin.w s9, a0, (zero) +amomin.w s9, a0, (ra) +amomin.w s9, a0, (t0) +amomin.w s9, a0, (a0) +amomin.w s9, a0, (a5) +amomin.w s9, a0, (s4) +amomin.w s9, a0, (s9) +amomin.w s9, a0, (t6) +amomin.w s9, a5, (zero) +amomin.w s9, a5, (ra) +amomin.w s9, a5, (t0) +amomin.w s9, a5, (a0) +amomin.w s9, a5, (a5) +amomin.w s9, a5, (s4) +amomin.w s9, a5, (s9) +amomin.w s9, a5, (t6) +amomin.w s9, s4, (zero) +amomin.w s9, s4, (ra) +amomin.w s9, s4, (t0) +amomin.w s9, s4, (a0) +amomin.w s9, s4, (a5) +amomin.w s9, s4, (s4) +amomin.w s9, s4, (s9) +amomin.w s9, s4, (t6) +amomin.w s9, s9, (zero) +amomin.w s9, s9, (ra) +amomin.w s9, s9, (t0) +amomin.w s9, s9, (a0) +amomin.w s9, s9, (a5) +amomin.w s9, s9, (s4) +amomin.w s9, s9, (s9) +amomin.w s9, s9, (t6) +amomin.w s9, t6, (zero) +amomin.w s9, t6, (ra) +amomin.w s9, t6, (t0) +amomin.w s9, t6, (a0) +amomin.w s9, t6, (a5) +amomin.w s9, t6, (s4) +amomin.w s9, t6, (s9) +amomin.w s9, t6, (t6) +amomin.w t6, zero, (zero) +amomin.w t6, zero, (ra) +amomin.w t6, zero, (t0) +amomin.w t6, zero, (a0) +amomin.w t6, zero, (a5) +amomin.w t6, zero, (s4) +amomin.w t6, zero, (s9) +amomin.w t6, zero, (t6) +amomin.w t6, ra, (zero) +amomin.w t6, ra, (ra) +amomin.w t6, ra, (t0) +amomin.w t6, ra, (a0) +amomin.w t6, ra, (a5) +amomin.w t6, ra, (s4) +amomin.w t6, ra, (s9) +amomin.w t6, ra, (t6) +amomin.w t6, t0, (zero) +amomin.w t6, t0, (ra) +amomin.w t6, t0, (t0) +amomin.w t6, t0, (a0) +amomin.w t6, t0, (a5) +amomin.w t6, t0, (s4) +amomin.w t6, t0, (s9) +amomin.w t6, t0, (t6) +amomin.w t6, a0, (zero) +amomin.w t6, a0, (ra) +amomin.w t6, a0, (t0) +amomin.w t6, a0, (a0) +amomin.w t6, a0, (a5) +amomin.w t6, a0, (s4) +amomin.w t6, a0, (s9) +amomin.w t6, a0, (t6) +amomin.w t6, a5, (zero) +amomin.w t6, a5, (ra) +amomin.w t6, a5, (t0) +amomin.w t6, a5, (a0) +amomin.w t6, a5, (a5) +amomin.w t6, a5, (s4) +amomin.w t6, a5, (s9) +amomin.w t6, a5, (t6) +amomin.w t6, s4, (zero) +amomin.w t6, s4, (ra) +amomin.w t6, s4, (t0) +amomin.w t6, s4, (a0) +amomin.w t6, s4, (a5) +amomin.w t6, s4, (s4) +amomin.w t6, s4, (s9) +amomin.w t6, s4, (t6) +amomin.w t6, s9, (zero) +amomin.w t6, s9, (ra) +amomin.w t6, s9, (t0) +amomin.w t6, s9, (a0) +amomin.w t6, s9, (a5) +amomin.w t6, s9, (s4) +amomin.w t6, s9, (s9) +amomin.w t6, s9, (t6) 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+amoor.w zero, zero, (s4) +amoor.w zero, zero, (s9) +amoor.w zero, zero, (t6) +amoor.w zero, ra, (zero) +amoor.w zero, ra, (ra) +amoor.w zero, ra, (t0) +amoor.w zero, ra, (a0) +amoor.w zero, ra, (a5) +amoor.w zero, ra, (s4) +amoor.w zero, ra, (s9) +amoor.w zero, ra, (t6) +amoor.w zero, t0, (zero) +amoor.w zero, t0, (ra) +amoor.w zero, t0, (t0) +amoor.w zero, t0, (a0) +amoor.w zero, t0, (a5) +amoor.w zero, t0, (s4) +amoor.w zero, t0, (s9) +amoor.w zero, t0, (t6) +amoor.w zero, a0, (zero) +amoor.w zero, a0, (ra) +amoor.w zero, a0, (t0) +amoor.w zero, a0, (a0) +amoor.w zero, a0, (a5) +amoor.w zero, a0, (s4) +amoor.w zero, a0, (s9) +amoor.w zero, a0, (t6) +amoor.w zero, a5, (zero) +amoor.w zero, a5, (ra) +amoor.w zero, a5, (t0) +amoor.w zero, a5, (a0) +amoor.w zero, a5, (a5) +amoor.w zero, a5, (s4) +amoor.w zero, a5, (s9) +amoor.w zero, a5, (t6) +amoor.w zero, s4, (zero) +amoor.w zero, s4, (ra) +amoor.w zero, s4, (t0) +amoor.w zero, s4, (a0) +amoor.w zero, s4, (a5) +amoor.w zero, s4, (s4) +amoor.w zero, s4, (s9) +amoor.w zero, s4, (t6) +amoor.w zero, s9, (zero) +amoor.w zero, s9, (ra) +amoor.w zero, s9, (t0) +amoor.w zero, s9, (a0) +amoor.w zero, s9, (a5) +amoor.w zero, s9, (s4) +amoor.w zero, s9, (s9) +amoor.w zero, s9, (t6) +amoor.w zero, t6, (zero) +amoor.w zero, t6, (ra) +amoor.w zero, t6, (t0) +amoor.w zero, t6, (a0) +amoor.w zero, t6, (a5) +amoor.w zero, t6, (s4) +amoor.w zero, t6, (s9) +amoor.w zero, t6, (t6) +amoor.w ra, zero, (zero) +amoor.w ra, zero, (ra) +amoor.w ra, zero, (t0) +amoor.w ra, zero, (a0) +amoor.w ra, zero, (a5) +amoor.w ra, zero, (s4) +amoor.w ra, zero, (s9) +amoor.w ra, zero, (t6) +amoor.w ra, ra, (zero) +amoor.w ra, ra, (ra) +amoor.w ra, ra, (t0) +amoor.w ra, ra, (a0) +amoor.w ra, ra, (a5) +amoor.w ra, ra, (s4) +amoor.w ra, ra, (s9) +amoor.w ra, ra, (t6) +amoor.w ra, t0, (zero) +amoor.w ra, t0, (ra) +amoor.w ra, t0, (t0) +amoor.w ra, t0, (a0) +amoor.w ra, t0, (a5) +amoor.w ra, t0, (s4) +amoor.w ra, t0, (s9) +amoor.w ra, t0, (t6) +amoor.w ra, a0, (zero) +amoor.w ra, a0, (ra) +amoor.w ra, a0, (t0) +amoor.w ra, a0, (a0) +amoor.w ra, a0, (a5) +amoor.w ra, a0, (s4) +amoor.w ra, a0, (s9) +amoor.w ra, a0, (t6) +amoor.w ra, a5, (zero) +amoor.w ra, a5, (ra) +amoor.w ra, a5, (t0) +amoor.w ra, a5, (a0) +amoor.w ra, a5, (a5) +amoor.w ra, a5, (s4) +amoor.w ra, a5, (s9) +amoor.w ra, a5, (t6) +amoor.w ra, s4, (zero) +amoor.w ra, s4, (ra) +amoor.w ra, s4, (t0) +amoor.w ra, s4, (a0) +amoor.w ra, s4, (a5) +amoor.w ra, s4, (s4) +amoor.w ra, s4, (s9) +amoor.w ra, s4, (t6) +amoor.w ra, s9, (zero) +amoor.w ra, s9, (ra) +amoor.w ra, s9, (t0) +amoor.w ra, s9, (a0) +amoor.w ra, s9, (a5) +amoor.w ra, s9, (s4) +amoor.w ra, s9, (s9) +amoor.w ra, s9, (t6) +amoor.w ra, t6, (zero) +amoor.w ra, t6, (ra) +amoor.w ra, t6, (t0) +amoor.w ra, t6, (a0) +amoor.w ra, t6, (a5) +amoor.w ra, t6, (s4) +amoor.w ra, t6, (s9) +amoor.w ra, t6, (t6) +amoor.w t0, zero, (zero) +amoor.w t0, zero, (ra) +amoor.w t0, zero, (t0) +amoor.w t0, zero, (a0) +amoor.w t0, zero, (a5) +amoor.w t0, zero, (s4) +amoor.w t0, zero, (s9) +amoor.w t0, zero, (t6) +amoor.w t0, ra, (zero) +amoor.w t0, ra, (ra) +amoor.w t0, ra, (t0) +amoor.w t0, ra, (a0) +amoor.w t0, ra, (a5) +amoor.w t0, ra, (s4) +amoor.w t0, ra, (s9) +amoor.w t0, ra, (t6) +amoor.w t0, t0, (zero) +amoor.w t0, t0, (ra) +amoor.w t0, t0, (t0) +amoor.w t0, t0, (a0) +amoor.w t0, t0, (a5) +amoor.w t0, t0, (s4) +amoor.w t0, t0, (s9) +amoor.w t0, t0, (t6) +amoor.w t0, a0, (zero) +amoor.w t0, a0, (ra) +amoor.w t0, a0, (t0) +amoor.w t0, a0, (a0) +amoor.w t0, a0, (a5) +amoor.w t0, a0, (s4) +amoor.w t0, a0, (s9) +amoor.w t0, a0, (t6) +amoor.w t0, a5, (zero) +amoor.w t0, a5, (ra) +amoor.w t0, a5, (t0) +amoor.w t0, a5, (a0) +amoor.w t0, a5, (a5) +amoor.w t0, a5, (s4) +amoor.w t0, a5, (s9) +amoor.w t0, a5, (t6) +amoor.w t0, s4, (zero) +amoor.w t0, s4, (ra) +amoor.w t0, s4, (t0) +amoor.w t0, s4, (a0) +amoor.w t0, s4, (a5) +amoor.w t0, s4, (s4) +amoor.w t0, s4, (s9) +amoor.w t0, s4, (t6) +amoor.w t0, s9, (zero) +amoor.w t0, s9, (ra) +amoor.w t0, s9, (t0) +amoor.w t0, s9, (a0) +amoor.w t0, s9, (a5) +amoor.w t0, s9, (s4) +amoor.w t0, s9, (s9) +amoor.w t0, s9, (t6) +amoor.w t0, t6, (zero) +amoor.w t0, t6, (ra) +amoor.w t0, t6, (t0) +amoor.w t0, t6, (a0) +amoor.w t0, t6, (a5) +amoor.w t0, t6, (s4) +amoor.w t0, t6, (s9) +amoor.w t0, t6, (t6) +amoor.w a0, zero, (zero) +amoor.w a0, zero, (ra) +amoor.w a0, zero, (t0) +amoor.w a0, zero, (a0) +amoor.w a0, zero, (a5) +amoor.w a0, zero, (s4) +amoor.w a0, zero, (s9) +amoor.w a0, zero, (t6) +amoor.w a0, ra, (zero) +amoor.w a0, ra, (ra) +amoor.w a0, ra, (t0) +amoor.w a0, ra, (a0) +amoor.w a0, ra, (a5) +amoor.w a0, ra, (s4) +amoor.w a0, ra, (s9) +amoor.w a0, ra, (t6) +amoor.w a0, t0, (zero) +amoor.w a0, t0, (ra) +amoor.w a0, t0, (t0) +amoor.w a0, t0, (a0) +amoor.w a0, t0, (a5) +amoor.w a0, t0, (s4) +amoor.w a0, t0, (s9) +amoor.w a0, t0, (t6) +amoor.w a0, a0, (zero) +amoor.w a0, a0, (ra) +amoor.w a0, a0, (t0) +amoor.w a0, a0, (a0) +amoor.w a0, a0, (a5) +amoor.w a0, a0, (s4) +amoor.w a0, a0, (s9) +amoor.w a0, a0, (t6) +amoor.w a0, a5, (zero) +amoor.w a0, a5, (ra) +amoor.w a0, a5, (t0) +amoor.w a0, a5, (a0) +amoor.w a0, a5, (a5) +amoor.w a0, a5, (s4) +amoor.w a0, a5, (s9) +amoor.w a0, a5, (t6) +amoor.w a0, s4, (zero) +amoor.w a0, s4, (ra) +amoor.w a0, s4, (t0) +amoor.w a0, s4, (a0) +amoor.w a0, s4, (a5) +amoor.w a0, s4, (s4) +amoor.w a0, s4, (s9) +amoor.w a0, s4, (t6) +amoor.w a0, s9, (zero) +amoor.w a0, s9, (ra) +amoor.w a0, s9, (t0) +amoor.w a0, s9, (a0) +amoor.w a0, s9, (a5) +amoor.w a0, s9, (s4) +amoor.w a0, s9, (s9) +amoor.w a0, s9, (t6) +amoor.w a0, t6, (zero) +amoor.w a0, t6, (ra) +amoor.w a0, t6, (t0) +amoor.w a0, t6, (a0) +amoor.w a0, t6, (a5) +amoor.w a0, t6, (s4) +amoor.w a0, t6, (s9) +amoor.w a0, t6, (t6) +amoor.w a5, zero, (zero) +amoor.w a5, zero, (ra) +amoor.w a5, zero, (t0) +amoor.w a5, zero, (a0) +amoor.w a5, zero, (a5) +amoor.w a5, zero, (s4) +amoor.w a5, zero, (s9) +amoor.w a5, zero, (t6) +amoor.w a5, ra, (zero) +amoor.w a5, ra, (ra) +amoor.w a5, ra, (t0) +amoor.w a5, ra, (a0) +amoor.w a5, ra, (a5) +amoor.w a5, ra, (s4) +amoor.w a5, ra, (s9) +amoor.w a5, ra, (t6) +amoor.w a5, t0, (zero) +amoor.w a5, t0, (ra) +amoor.w a5, t0, (t0) +amoor.w a5, t0, (a0) +amoor.w a5, t0, (a5) +amoor.w a5, t0, (s4) +amoor.w a5, t0, (s9) +amoor.w a5, t0, (t6) +amoor.w a5, a0, (zero) +amoor.w a5, a0, (ra) +amoor.w a5, a0, (t0) +amoor.w a5, a0, (a0) +amoor.w a5, a0, (a5) +amoor.w a5, a0, (s4) +amoor.w a5, a0, (s9) +amoor.w a5, a0, (t6) +amoor.w a5, a5, (zero) +amoor.w a5, a5, (ra) +amoor.w a5, a5, (t0) +amoor.w a5, a5, (a0) +amoor.w a5, a5, (a5) +amoor.w a5, a5, (s4) +amoor.w a5, a5, (s9) +amoor.w a5, a5, (t6) +amoor.w a5, s4, (zero) +amoor.w a5, s4, (ra) +amoor.w a5, s4, (t0) +amoor.w a5, s4, (a0) +amoor.w a5, s4, (a5) +amoor.w a5, s4, (s4) +amoor.w a5, s4, (s9) +amoor.w a5, s4, (t6) +amoor.w a5, s9, (zero) +amoor.w a5, s9, (ra) +amoor.w a5, s9, (t0) +amoor.w a5, s9, (a0) +amoor.w a5, s9, (a5) +amoor.w a5, s9, (s4) +amoor.w a5, s9, (s9) +amoor.w a5, s9, (t6) +amoor.w a5, t6, (zero) +amoor.w a5, t6, (ra) +amoor.w a5, t6, (t0) +amoor.w a5, t6, (a0) +amoor.w a5, t6, (a5) +amoor.w a5, t6, (s4) +amoor.w a5, t6, (s9) +amoor.w a5, t6, (t6) +amoor.w s4, zero, (zero) +amoor.w s4, zero, (ra) +amoor.w s4, zero, (t0) +amoor.w s4, zero, (a0) +amoor.w s4, zero, (a5) +amoor.w s4, zero, (s4) +amoor.w s4, zero, (s9) +amoor.w s4, zero, (t6) +amoor.w s4, ra, (zero) +amoor.w s4, ra, (ra) +amoor.w s4, ra, (t0) +amoor.w s4, ra, (a0) +amoor.w s4, ra, (a5) +amoor.w s4, ra, (s4) +amoor.w s4, ra, (s9) +amoor.w s4, ra, (t6) +amoor.w s4, t0, (zero) +amoor.w s4, t0, (ra) +amoor.w s4, t0, (t0) +amoor.w s4, t0, (a0) +amoor.w s4, t0, (a5) +amoor.w s4, t0, (s4) +amoor.w s4, t0, (s9) +amoor.w s4, t0, (t6) +amoor.w s4, a0, (zero) +amoor.w s4, a0, (ra) +amoor.w s4, a0, (t0) +amoor.w s4, a0, (a0) +amoor.w s4, a0, (a5) +amoor.w s4, a0, (s4) +amoor.w s4, a0, (s9) +amoor.w s4, a0, (t6) +amoor.w s4, a5, (zero) +amoor.w s4, a5, (ra) +amoor.w s4, a5, (t0) +amoor.w s4, a5, (a0) +amoor.w s4, a5, (a5) +amoor.w s4, a5, (s4) +amoor.w s4, a5, (s9) +amoor.w s4, a5, (t6) +amoor.w s4, s4, (zero) +amoor.w s4, s4, (ra) +amoor.w s4, s4, (t0) +amoor.w s4, s4, (a0) +amoor.w s4, s4, (a5) +amoor.w s4, s4, (s4) +amoor.w s4, s4, (s9) +amoor.w s4, s4, (t6) +amoor.w s4, s9, (zero) +amoor.w s4, s9, (ra) +amoor.w s4, s9, (t0) +amoor.w s4, s9, (a0) +amoor.w s4, s9, (a5) +amoor.w s4, s9, (s4) +amoor.w s4, s9, (s9) +amoor.w s4, s9, (t6) +amoor.w s4, t6, (zero) +amoor.w s4, t6, (ra) +amoor.w s4, t6, (t0) +amoor.w s4, t6, (a0) +amoor.w s4, t6, (a5) +amoor.w s4, t6, (s4) +amoor.w s4, t6, (s9) +amoor.w s4, t6, (t6) +amoor.w s9, zero, (zero) +amoor.w s9, zero, (ra) +amoor.w s9, zero, (t0) +amoor.w s9, zero, (a0) +amoor.w s9, zero, (a5) +amoor.w s9, zero, (s4) +amoor.w s9, zero, (s9) +amoor.w s9, zero, (t6) +amoor.w s9, ra, (zero) +amoor.w s9, ra, (ra) +amoor.w s9, ra, (t0) +amoor.w s9, ra, (a0) +amoor.w s9, ra, (a5) +amoor.w s9, ra, (s4) +amoor.w s9, ra, (s9) +amoor.w s9, ra, (t6) +amoor.w s9, t0, (zero) +amoor.w s9, t0, (ra) +amoor.w s9, t0, (t0) +amoor.w s9, t0, (a0) +amoor.w s9, t0, (a5) +amoor.w s9, t0, (s4) +amoor.w s9, t0, (s9) +amoor.w s9, t0, (t6) +amoor.w s9, a0, (zero) +amoor.w s9, a0, (ra) +amoor.w s9, a0, (t0) +amoor.w s9, a0, (a0) +amoor.w s9, a0, (a5) +amoor.w s9, a0, (s4) +amoor.w s9, a0, (s9) +amoor.w s9, a0, (t6) +amoor.w s9, a5, (zero) +amoor.w s9, a5, (ra) +amoor.w s9, a5, (t0) +amoor.w s9, a5, (a0) +amoor.w s9, a5, (a5) +amoor.w s9, a5, (s4) +amoor.w s9, a5, (s9) +amoor.w s9, a5, (t6) +amoor.w s9, s4, (zero) +amoor.w s9, s4, (ra) +amoor.w s9, s4, (t0) +amoor.w s9, s4, (a0) +amoor.w s9, s4, (a5) +amoor.w s9, s4, (s4) +amoor.w s9, s4, (s9) +amoor.w s9, s4, (t6) +amoor.w s9, s9, (zero) +amoor.w s9, s9, (ra) +amoor.w s9, s9, (t0) +amoor.w s9, s9, (a0) +amoor.w s9, s9, (a5) +amoor.w s9, s9, (s4) +amoor.w s9, s9, (s9) +amoor.w s9, s9, (t6) +amoor.w s9, t6, (zero) +amoor.w s9, t6, (ra) +amoor.w s9, t6, (t0) +amoor.w s9, t6, (a0) +amoor.w s9, t6, (a5) +amoor.w s9, t6, (s4) +amoor.w s9, t6, (s9) +amoor.w s9, t6, (t6) +amoor.w t6, zero, (zero) +amoor.w t6, zero, (ra) +amoor.w t6, zero, (t0) +amoor.w t6, zero, (a0) +amoor.w t6, zero, (a5) +amoor.w t6, zero, (s4) +amoor.w t6, zero, (s9) +amoor.w t6, zero, (t6) +amoor.w t6, ra, (zero) +amoor.w t6, ra, (ra) +amoor.w t6, ra, (t0) +amoor.w t6, ra, (a0) +amoor.w t6, ra, (a5) +amoor.w t6, ra, (s4) +amoor.w t6, ra, (s9) +amoor.w t6, ra, (t6) +amoor.w t6, t0, (zero) +amoor.w t6, t0, (ra) +amoor.w t6, t0, (t0) +amoor.w t6, t0, (a0) +amoor.w t6, t0, (a5) +amoor.w t6, t0, (s4) +amoor.w t6, t0, (s9) +amoor.w t6, t0, (t6) +amoor.w t6, a0, (zero) +amoor.w t6, a0, (ra) +amoor.w t6, a0, (t0) +amoor.w t6, a0, (a0) +amoor.w t6, a0, (a5) +amoor.w t6, a0, (s4) +amoor.w t6, a0, (s9) +amoor.w t6, a0, (t6) +amoor.w t6, a5, (zero) +amoor.w t6, a5, (ra) +amoor.w t6, a5, (t0) +amoor.w t6, a5, (a0) +amoor.w t6, a5, (a5) +amoor.w t6, a5, (s4) +amoor.w t6, a5, (s9) +amoor.w t6, a5, (t6) +amoor.w t6, s4, (zero) +amoor.w t6, s4, (ra) +amoor.w t6, s4, (t0) +amoor.w t6, s4, (a0) +amoor.w t6, s4, (a5) +amoor.w t6, s4, (s4) +amoor.w t6, s4, (s9) +amoor.w t6, s4, (t6) +amoor.w t6, s9, (zero) +amoor.w t6, s9, (ra) +amoor.w t6, s9, (t0) +amoor.w t6, s9, (a0) +amoor.w t6, s9, (a5) +amoor.w t6, s9, (s4) +amoor.w t6, s9, (s9) +amoor.w t6, s9, (t6) +amoor.w t6, t6, (zero) +amoor.w t6, t6, (ra) +amoor.w t6, t6, (t0) +amoor.w t6, t6, (a0) +amoor.w t6, t6, (a5) +amoor.w t6, t6, (s4) +amoor.w t6, t6, (s9) +amoor.w t6, t6, (t6) diff --git a/tests/riscv/a-extension/amoor_w.asm b/tests/riscv/a-extension/amoor_w.asm new file mode 100644 index 0000000..81a8dcc --- /dev/null +++ b/tests/riscv/a-extension/amoor_w.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +amoor.w a0, a2, (a1) + diff --git a/tests/riscv/a-extension/amoor_w.bin b/tests/riscv/a-extension/amoor_w.bin new file mode 100644 index 0000000..c8cf065 --- /dev/null +++ b/tests/riscv/a-extension/amoor_w.bin @@ -0,0 +1 @@ +/@ \ No newline at end of file diff --git a/tests/riscv/a-extension/amoor_w.disasm b/tests/riscv/a-extension/amoor_w.disasm new file mode 100644 index 0000000..7273639 --- /dev/null +++ b/tests/riscv/a-extension/amoor_w.disasm @@ -0,0 +1 @@ +amoor.w a0, a2, (a1) diff --git a/tests/riscv/a-extension/amoswap.w.asm b/tests/riscv/a-extension/amoswap.w.asm new file mode 100644 index 0000000..e4f090b --- /dev/null +++ b/tests/riscv/a-extension/amoswap.w.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +amoswap.w zero, zero, (zero) +amoswap.w zero, zero, (ra) +amoswap.w zero, zero, (t0) +amoswap.w zero, zero, (a0) +amoswap.w zero, zero, (a5) +amoswap.w zero, zero, (s4) +amoswap.w zero, zero, (s9) +amoswap.w zero, zero, (t6) +amoswap.w zero, ra, (zero) +amoswap.w zero, ra, (ra) +amoswap.w zero, ra, (t0) +amoswap.w zero, ra, (a0) +amoswap.w zero, ra, (a5) +amoswap.w zero, ra, (s4) +amoswap.w zero, ra, (s9) +amoswap.w zero, ra, (t6) +amoswap.w zero, t0, (zero) +amoswap.w zero, t0, (ra) +amoswap.w zero, t0, (t0) +amoswap.w zero, t0, (a0) +amoswap.w zero, t0, (a5) +amoswap.w zero, t0, (s4) +amoswap.w zero, t0, (s9) +amoswap.w zero, t0, (t6) +amoswap.w zero, a0, (zero) +amoswap.w zero, a0, (ra) +amoswap.w zero, a0, (t0) +amoswap.w zero, a0, (a0) +amoswap.w zero, a0, (a5) +amoswap.w zero, a0, (s4) +amoswap.w zero, a0, (s9) +amoswap.w zero, a0, (t6) +amoswap.w zero, a5, (zero) +amoswap.w zero, a5, (ra) +amoswap.w zero, a5, (t0) +amoswap.w zero, a5, (a0) +amoswap.w zero, a5, (a5) +amoswap.w zero, a5, (s4) +amoswap.w zero, a5, (s9) +amoswap.w zero, a5, (t6) +amoswap.w zero, s4, (zero) +amoswap.w zero, s4, (ra) +amoswap.w zero, s4, (t0) +amoswap.w zero, s4, (a0) +amoswap.w zero, s4, (a5) +amoswap.w zero, s4, (s4) +amoswap.w zero, s4, (s9) +amoswap.w zero, s4, (t6) +amoswap.w zero, s9, (zero) +amoswap.w zero, s9, (ra) +amoswap.w zero, s9, (t0) +amoswap.w zero, s9, (a0) +amoswap.w zero, s9, (a5) +amoswap.w zero, s9, (s4) +amoswap.w zero, s9, (s9) +amoswap.w zero, s9, (t6) +amoswap.w zero, t6, (zero) +amoswap.w zero, t6, (ra) +amoswap.w zero, t6, (t0) +amoswap.w zero, t6, (a0) +amoswap.w zero, t6, (a5) +amoswap.w zero, t6, (s4) +amoswap.w zero, t6, (s9) +amoswap.w zero, t6, (t6) +amoswap.w ra, zero, (zero) +amoswap.w ra, zero, (ra) +amoswap.w ra, zero, (t0) +amoswap.w ra, zero, (a0) +amoswap.w ra, zero, (a5) +amoswap.w ra, zero, (s4) +amoswap.w ra, zero, (s9) +amoswap.w ra, zero, (t6) +amoswap.w ra, ra, (zero) +amoswap.w ra, ra, (ra) +amoswap.w ra, ra, (t0) +amoswap.w ra, ra, (a0) +amoswap.w ra, ra, (a5) +amoswap.w ra, ra, (s4) +amoswap.w ra, ra, (s9) +amoswap.w ra, ra, (t6) +amoswap.w ra, t0, (zero) +amoswap.w ra, t0, (ra) +amoswap.w ra, t0, (t0) +amoswap.w ra, t0, (a0) +amoswap.w ra, t0, (a5) +amoswap.w ra, t0, (s4) +amoswap.w ra, t0, (s9) +amoswap.w ra, t0, (t6) +amoswap.w ra, a0, (zero) +amoswap.w ra, a0, (ra) +amoswap.w ra, a0, (t0) +amoswap.w ra, a0, (a0) +amoswap.w ra, a0, (a5) +amoswap.w ra, a0, (s4) +amoswap.w ra, a0, (s9) +amoswap.w ra, a0, (t6) +amoswap.w ra, a5, (zero) +amoswap.w ra, a5, (ra) +amoswap.w ra, a5, (t0) +amoswap.w ra, a5, (a0) +amoswap.w ra, a5, (a5) +amoswap.w ra, a5, (s4) +amoswap.w ra, a5, (s9) +amoswap.w ra, a5, (t6) +amoswap.w ra, s4, (zero) +amoswap.w ra, s4, (ra) +amoswap.w ra, s4, (t0) +amoswap.w ra, s4, (a0) +amoswap.w ra, s4, (a5) +amoswap.w ra, s4, (s4) +amoswap.w ra, s4, (s9) +amoswap.w ra, s4, (t6) +amoswap.w ra, s9, (zero) +amoswap.w ra, s9, (ra) +amoswap.w ra, s9, (t0) +amoswap.w ra, s9, (a0) +amoswap.w ra, s9, (a5) +amoswap.w ra, s9, (s4) +amoswap.w ra, s9, (s9) +amoswap.w ra, s9, (t6) +amoswap.w ra, t6, (zero) +amoswap.w ra, t6, (ra) +amoswap.w ra, t6, (t0) +amoswap.w ra, t6, (a0) +amoswap.w ra, t6, (a5) +amoswap.w ra, t6, (s4) +amoswap.w ra, t6, (s9) +amoswap.w ra, t6, (t6) +amoswap.w t0, zero, (zero) +amoswap.w t0, zero, (ra) +amoswap.w t0, zero, (t0) +amoswap.w t0, zero, (a0) +amoswap.w t0, zero, (a5) +amoswap.w t0, zero, (s4) +amoswap.w t0, zero, (s9) +amoswap.w t0, zero, (t6) +amoswap.w t0, ra, (zero) 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(zero) +amoxor.w t0, t6, (ra) +amoxor.w t0, t6, (t0) +amoxor.w t0, t6, (a0) +amoxor.w t0, t6, (a5) +amoxor.w t0, t6, (s4) +amoxor.w t0, t6, (s9) +amoxor.w t0, t6, (t6) +amoxor.w a0, zero, (zero) +amoxor.w a0, zero, (ra) +amoxor.w a0, zero, (t0) +amoxor.w a0, zero, (a0) +amoxor.w a0, zero, (a5) +amoxor.w a0, zero, (s4) +amoxor.w a0, zero, (s9) +amoxor.w a0, zero, (t6) +amoxor.w a0, ra, (zero) +amoxor.w a0, ra, (ra) +amoxor.w a0, ra, (t0) +amoxor.w a0, ra, (a0) +amoxor.w a0, ra, (a5) +amoxor.w a0, ra, (s4) +amoxor.w a0, ra, (s9) +amoxor.w a0, ra, (t6) +amoxor.w a0, t0, (zero) +amoxor.w a0, t0, (ra) +amoxor.w a0, t0, (t0) +amoxor.w a0, t0, (a0) +amoxor.w a0, t0, (a5) +amoxor.w a0, t0, (s4) +amoxor.w a0, t0, (s9) +amoxor.w a0, t0, (t6) +amoxor.w a0, a0, (zero) +amoxor.w a0, a0, (ra) +amoxor.w a0, a0, (t0) +amoxor.w a0, a0, (a0) +amoxor.w a0, a0, (a5) +amoxor.w a0, a0, (s4) +amoxor.w a0, a0, (s9) +amoxor.w a0, a0, (t6) +amoxor.w a0, a5, (zero) +amoxor.w a0, a5, (ra) +amoxor.w a0, a5, (t0) +amoxor.w a0, a5, (a0) +amoxor.w a0, a5, (a5) +amoxor.w a0, a5, (s4) +amoxor.w a0, a5, (s9) +amoxor.w a0, a5, (t6) +amoxor.w a0, s4, (zero) +amoxor.w a0, s4, (ra) +amoxor.w a0, s4, (t0) +amoxor.w a0, s4, (a0) +amoxor.w a0, s4, (a5) +amoxor.w a0, s4, (s4) +amoxor.w a0, s4, (s9) +amoxor.w a0, s4, (t6) +amoxor.w a0, s9, (zero) +amoxor.w a0, s9, (ra) +amoxor.w a0, s9, (t0) +amoxor.w a0, s9, (a0) +amoxor.w a0, s9, (a5) +amoxor.w a0, s9, (s4) +amoxor.w a0, s9, (s9) +amoxor.w a0, s9, (t6) +amoxor.w a0, t6, (zero) +amoxor.w a0, t6, (ra) +amoxor.w a0, t6, (t0) +amoxor.w a0, t6, (a0) +amoxor.w a0, t6, (a5) +amoxor.w a0, t6, (s4) +amoxor.w a0, t6, (s9) +amoxor.w a0, t6, (t6) +amoxor.w a5, zero, (zero) +amoxor.w a5, zero, (ra) +amoxor.w a5, zero, (t0) +amoxor.w a5, zero, (a0) +amoxor.w a5, zero, (a5) +amoxor.w a5, zero, (s4) +amoxor.w a5, zero, (s9) +amoxor.w a5, zero, (t6) +amoxor.w a5, ra, (zero) +amoxor.w a5, ra, (ra) +amoxor.w a5, ra, (t0) +amoxor.w a5, ra, (a0) +amoxor.w a5, ra, (a5) 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+amoxor.w a5, t6, (zero) +amoxor.w a5, t6, (ra) +amoxor.w a5, t6, (t0) +amoxor.w a5, t6, (a0) +amoxor.w a5, t6, (a5) +amoxor.w a5, t6, (s4) +amoxor.w a5, t6, (s9) +amoxor.w a5, t6, (t6) +amoxor.w s4, zero, (zero) +amoxor.w s4, zero, (ra) +amoxor.w s4, zero, (t0) +amoxor.w s4, zero, (a0) +amoxor.w s4, zero, (a5) +amoxor.w s4, zero, (s4) +amoxor.w s4, zero, (s9) +amoxor.w s4, zero, (t6) +amoxor.w s4, ra, (zero) +amoxor.w s4, ra, (ra) +amoxor.w s4, ra, (t0) +amoxor.w s4, ra, (a0) +amoxor.w s4, ra, (a5) +amoxor.w s4, ra, (s4) +amoxor.w s4, ra, (s9) +amoxor.w s4, ra, (t6) +amoxor.w s4, t0, (zero) +amoxor.w s4, t0, (ra) +amoxor.w s4, t0, (t0) +amoxor.w s4, t0, (a0) +amoxor.w s4, t0, (a5) +amoxor.w s4, t0, (s4) +amoxor.w s4, t0, (s9) +amoxor.w s4, t0, (t6) +amoxor.w s4, a0, (zero) +amoxor.w s4, a0, (ra) +amoxor.w s4, a0, (t0) +amoxor.w s4, a0, (a0) +amoxor.w s4, a0, (a5) +amoxor.w s4, a0, (s4) +amoxor.w s4, a0, (s9) +amoxor.w s4, a0, (t6) +amoxor.w s4, a5, (zero) +amoxor.w s4, a5, (ra) +amoxor.w s4, a5, (t0) +amoxor.w s4, a5, (a0) +amoxor.w s4, a5, (a5) +amoxor.w s4, a5, (s4) +amoxor.w s4, a5, (s9) +amoxor.w s4, a5, (t6) +amoxor.w s4, s4, (zero) +amoxor.w s4, s4, (ra) +amoxor.w s4, s4, (t0) +amoxor.w s4, s4, (a0) +amoxor.w s4, s4, (a5) +amoxor.w s4, s4, (s4) +amoxor.w s4, s4, (s9) +amoxor.w s4, s4, (t6) +amoxor.w s4, s9, (zero) +amoxor.w s4, s9, (ra) +amoxor.w s4, s9, (t0) +amoxor.w s4, s9, (a0) +amoxor.w s4, s9, (a5) +amoxor.w s4, s9, (s4) +amoxor.w s4, s9, (s9) +amoxor.w s4, s9, (t6) +amoxor.w s4, t6, (zero) +amoxor.w s4, t6, (ra) +amoxor.w s4, t6, (t0) +amoxor.w s4, t6, (a0) +amoxor.w s4, t6, (a5) +amoxor.w s4, t6, (s4) +amoxor.w s4, t6, (s9) +amoxor.w s4, t6, (t6) +amoxor.w s9, zero, (zero) +amoxor.w s9, zero, (ra) +amoxor.w s9, zero, (t0) +amoxor.w s9, zero, (a0) +amoxor.w s9, zero, (a5) +amoxor.w s9, zero, (s4) +amoxor.w s9, zero, (s9) +amoxor.w s9, zero, (t6) +amoxor.w s9, ra, (zero) +amoxor.w s9, ra, (ra) +amoxor.w s9, ra, (t0) +amoxor.w s9, ra, (a0) +amoxor.w s9, ra, (a5) +amoxor.w s9, ra, (s4) +amoxor.w s9, ra, (s9) +amoxor.w s9, ra, (t6) +amoxor.w s9, t0, (zero) +amoxor.w s9, t0, (ra) +amoxor.w s9, t0, (t0) +amoxor.w s9, t0, (a0) +amoxor.w s9, t0, (a5) +amoxor.w s9, t0, (s4) +amoxor.w s9, t0, (s9) +amoxor.w s9, t0, (t6) +amoxor.w s9, a0, (zero) +amoxor.w s9, a0, (ra) +amoxor.w s9, a0, (t0) +amoxor.w s9, a0, (a0) +amoxor.w s9, a0, (a5) +amoxor.w s9, a0, (s4) +amoxor.w s9, a0, (s9) +amoxor.w s9, a0, (t6) +amoxor.w s9, a5, (zero) +amoxor.w s9, a5, (ra) +amoxor.w s9, a5, (t0) +amoxor.w s9, a5, (a0) +amoxor.w s9, a5, (a5) +amoxor.w s9, a5, (s4) +amoxor.w s9, a5, (s9) +amoxor.w s9, a5, (t6) +amoxor.w s9, s4, (zero) +amoxor.w s9, s4, (ra) +amoxor.w s9, s4, (t0) +amoxor.w s9, s4, (a0) +amoxor.w s9, s4, (a5) +amoxor.w s9, s4, (s4) +amoxor.w s9, s4, (s9) +amoxor.w s9, s4, (t6) +amoxor.w s9, s9, (zero) +amoxor.w s9, s9, (ra) +amoxor.w s9, s9, (t0) +amoxor.w s9, s9, (a0) +amoxor.w s9, s9, (a5) +amoxor.w s9, s9, (s4) +amoxor.w s9, s9, (s9) +amoxor.w s9, s9, (t6) +amoxor.w s9, t6, (zero) +amoxor.w s9, t6, (ra) +amoxor.w s9, t6, (t0) +amoxor.w s9, t6, (a0) +amoxor.w s9, t6, (a5) +amoxor.w s9, t6, (s4) +amoxor.w s9, t6, (s9) +amoxor.w s9, t6, (t6) +amoxor.w t6, zero, (zero) +amoxor.w t6, zero, (ra) +amoxor.w t6, zero, (t0) +amoxor.w t6, zero, (a0) +amoxor.w t6, zero, (a5) +amoxor.w t6, zero, (s4) +amoxor.w t6, zero, (s9) +amoxor.w t6, zero, (t6) +amoxor.w t6, ra, (zero) +amoxor.w t6, ra, (ra) +amoxor.w t6, ra, (t0) +amoxor.w t6, ra, (a0) +amoxor.w t6, ra, (a5) +amoxor.w t6, ra, (s4) +amoxor.w t6, ra, (s9) +amoxor.w t6, ra, (t6) +amoxor.w t6, t0, (zero) +amoxor.w t6, t0, (ra) +amoxor.w t6, t0, (t0) +amoxor.w t6, t0, (a0) +amoxor.w t6, t0, (a5) +amoxor.w t6, t0, (s4) +amoxor.w t6, t0, (s9) +amoxor.w t6, t0, (t6) +amoxor.w t6, a0, (zero) +amoxor.w t6, a0, (ra) +amoxor.w t6, a0, (t0) +amoxor.w t6, a0, (a0) +amoxor.w t6, a0, (a5) +amoxor.w t6, a0, (s4) +amoxor.w t6, a0, (s9) +amoxor.w t6, a0, (t6) +amoxor.w t6, a5, (zero) +amoxor.w t6, a5, (ra) +amoxor.w t6, a5, (t0) +amoxor.w t6, a5, (a0) +amoxor.w t6, a5, (a5) +amoxor.w t6, a5, (s4) +amoxor.w t6, a5, (s9) +amoxor.w t6, a5, (t6) +amoxor.w t6, s4, (zero) +amoxor.w t6, s4, (ra) +amoxor.w t6, s4, (t0) +amoxor.w t6, s4, (a0) +amoxor.w t6, s4, (a5) +amoxor.w t6, s4, (s4) +amoxor.w t6, s4, (s9) +amoxor.w t6, s4, (t6) +amoxor.w t6, s9, (zero) +amoxor.w t6, s9, (ra) +amoxor.w t6, s9, (t0) +amoxor.w t6, s9, (a0) +amoxor.w t6, s9, (a5) +amoxor.w t6, s9, (s4) +amoxor.w t6, s9, (s9) +amoxor.w t6, s9, (t6) +amoxor.w t6, t6, (zero) +amoxor.w t6, t6, (ra) +amoxor.w t6, t6, (t0) +amoxor.w t6, t6, (a0) +amoxor.w t6, t6, (a5) +amoxor.w t6, t6, (s4) +amoxor.w t6, t6, (s9) +amoxor.w t6, t6, (t6) diff --git a/tests/riscv/a-extension/amoxor_w.asm b/tests/riscv/a-extension/amoxor_w.asm new file mode 100644 index 0000000..1ff3ab9 --- /dev/null +++ b/tests/riscv/a-extension/amoxor_w.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +amoxor.w a0, a2, (a1) + diff --git a/tests/riscv/a-extension/amoxor_w.bin b/tests/riscv/a-extension/amoxor_w.bin new file mode 100644 index 0000000..1dd2646 --- /dev/null +++ b/tests/riscv/a-extension/amoxor_w.bin @@ -0,0 +1 @@ +/ \ No newline at end of file diff --git a/tests/riscv/a-extension/amoxor_w.disasm b/tests/riscv/a-extension/amoxor_w.disasm new file mode 100644 index 0000000..abcee64 --- /dev/null +++ b/tests/riscv/a-extension/amoxor_w.disasm @@ -0,0 +1 @@ +amoxor.w a0, a2, (a1) diff --git a/tests/riscv/a-extension/lr.w.asm b/tests/riscv/a-extension/lr.w.asm new file mode 100644 index 0000000..cccf377 --- /dev/null +++ b/tests/riscv/a-extension/lr.w.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +lr.w zero, (zero) +lr.w zero, (ra) +lr.w zero, (t0) +lr.w zero, (a0) +lr.w zero, (a5) +lr.w zero, (s4) +lr.w zero, (s9) +lr.w zero, (t6) +lr.w ra, (zero) +lr.w ra, (ra) +lr.w ra, (t0) +lr.w ra, (a0) +lr.w ra, (a5) +lr.w ra, (s4) +lr.w ra, (s9) +lr.w ra, (t6) +lr.w t0, (zero) +lr.w t0, (ra) +lr.w t0, (t0) +lr.w t0, (a0) +lr.w t0, (a5) +lr.w t0, (s4) +lr.w t0, (s9) +lr.w t0, (t6) +lr.w a0, (zero) +lr.w a0, (ra) +lr.w a0, (t0) +lr.w a0, (a0) +lr.w a0, (a5) +lr.w a0, (s4) +lr.w a0, (s9) +lr.w a0, (t6) +lr.w a5, (zero) +lr.w a5, (ra) +lr.w a5, (t0) +lr.w a5, (a0) +lr.w a5, (a5) +lr.w a5, (s4) +lr.w a5, (s9) +lr.w a5, (t6) +lr.w s4, (zero) +lr.w s4, (ra) +lr.w s4, (t0) +lr.w s4, (a0) +lr.w s4, (a5) +lr.w s4, (s4) +lr.w s4, (s9) +lr.w s4, (t6) +lr.w s9, (zero) +lr.w s9, (ra) +lr.w s9, (t0) +lr.w s9, (a0) +lr.w s9, (a5) +lr.w s9, (s4) +lr.w s9, (s9) +lr.w s9, (t6) +lr.w t6, (zero) +lr.w t6, (ra) +lr.w t6, (t0) +lr.w t6, (a0) +lr.w t6, (a5) +lr.w t6, (s4) +lr.w t6, (s9) +lr.w t6, (t6) + diff --git a/tests/riscv/a-extension/lr.w.bin b/tests/riscv/a-extension/lr.w.bin new file mode 100644 index 0000000000000000000000000000000000000000..3a1d5d3c21adb940c82d69b7404137a547d53257 GIT binary patch literal 256 zcmWm6(FVgn5QfnzRjOnkAwq-*`^vSfWrcagp1JtV#pg_2AEo|s&r;Wy`*uI>*On4` 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No newline at end of file diff --git a/tests/riscv/c-extension/c.add.disasm b/tests/riscv/c-extension/c.add.disasm new file mode 100644 index 0000000..7c0efb5 --- /dev/null +++ b/tests/riscv/c-extension/c.add.disasm @@ -0,0 +1,49 @@ +c.add ra, ra +c.add ra, t0 +c.add ra, a0 +c.add ra, a5 +c.add ra, s4 +c.add ra, s9 +c.add ra, t6 +c.add t0, ra +c.add t0, t0 +c.add t0, a0 +c.add t0, a5 +c.add t0, s4 +c.add t0, s9 +c.add t0, t6 +c.add a0, ra +c.add a0, t0 +c.add a0, a0 +c.add a0, a5 +c.add a0, s4 +c.add a0, s9 +c.add a0, t6 +c.add a5, ra +c.add a5, t0 +c.add a5, a0 +c.add a5, a5 +c.add a5, s4 +c.add a5, s9 +c.add a5, t6 +c.add s4, ra +c.add s4, t0 +c.add s4, a0 +c.add s4, a5 +c.add s4, s4 +c.add s4, s9 +c.add s4, t6 +c.add s9, ra +c.add s9, t0 +c.add s9, a0 +c.add s9, a5 +c.add s9, s4 +c.add s9, s9 +c.add s9, t6 +c.add t6, ra +c.add t6, t0 +c.add t6, a0 +c.add t6, a5 +c.add t6, s4 +c.add t6, s9 +c.add t6, t6 diff --git a/tests/riscv/c-extension/c.addi.asm b/tests/riscv/c-extension/c.addi.asm new file mode 100644 index 0000000..5d470c1 --- /dev/null +++ b/tests/riscv/c-extension/c.addi.asm @@ -0,0 +1,95 @@ +.lang riscv32 +.org 0x0 + +c.addi ra, #-32 +c.addi ra, #-16 +c.addi ra, #-8 +c.addi ra, #-4 +c.addi ra, #-2 +c.addi ra, #-1 +c.addi ra, #0 +c.addi ra, #1 +c.addi ra, #2 +c.addi ra, #4 +c.addi ra, #8 +c.addi ra, #16 +c.addi ra, #31 +c.addi t0, #-32 +c.addi t0, #-16 +c.addi t0, #-8 +c.addi t0, #-4 +c.addi t0, #-2 +c.addi t0, #-1 +c.addi t0, #0 +c.addi t0, #1 +c.addi t0, #2 +c.addi t0, #4 +c.addi t0, #8 +c.addi t0, #16 +c.addi t0, #31 +c.addi a0, #-32 +c.addi a0, #-16 +c.addi a0, #-8 +c.addi a0, #-4 +c.addi a0, #-2 +c.addi a0, #-1 +c.addi a0, #0 +c.addi a0, #1 +c.addi a0, #2 +c.addi a0, #4 +c.addi a0, #8 +c.addi a0, #16 +c.addi a0, #31 +c.addi a5, #-32 +c.addi a5, #-16 +c.addi a5, #-8 +c.addi a5, #-4 +c.addi a5, #-2 +c.addi a5, #-1 +c.addi a5, #0 +c.addi a5, #1 +c.addi a5, #2 +c.addi a5, #4 +c.addi a5, #8 +c.addi a5, #16 +c.addi a5, #31 +c.addi s4, #-32 +c.addi s4, #-16 +c.addi s4, #-8 +c.addi s4, #-4 +c.addi s4, #-2 +c.addi s4, #-1 +c.addi s4, #0 +c.addi s4, #1 +c.addi s4, #2 +c.addi s4, #4 +c.addi s4, #8 +c.addi s4, #16 +c.addi s4, #31 +c.addi s9, #-32 +c.addi s9, #-16 +c.addi s9, #-8 +c.addi s9, #-4 +c.addi s9, #-2 +c.addi s9, #-1 +c.addi s9, #0 +c.addi s9, #1 +c.addi s9, #2 +c.addi s9, #4 +c.addi s9, #8 +c.addi s9, #16 +c.addi s9, #31 +c.addi t6, #-32 +c.addi t6, #-16 +c.addi t6, #-8 +c.addi t6, #-4 +c.addi t6, #-2 +c.addi t6, #-1 +c.addi t6, #0 +c.addi t6, #1 +c.addi t6, #2 +c.addi t6, #4 +c.addi t6, #8 +c.addi t6, #16 +c.addi t6, #31 + diff --git a/tests/riscv/c-extension/c.addi.bin b/tests/riscv/c-extension/c.addi.bin new file mode 100644 index 0000000000000000000000000000000000000000..387a72bde50474cbfd15eda38150027c3b4956da GIT binary patch literal 182 zcmV~$u?Ykr5CA|=SmZ^}6GRX}u9Pd~OZf1D3pOw?v;<4pQY^vHVBu%bk(+M0?bxBH zqKPhsAi)AX`RSM6o;}Jco9uE(k}QvKhi~|WC%oYRfDfE-!3{59q&VY>J90!-Ra0FJ zMT*st?(|K+^rSZ(8uUk>`qH<4HD<~)ue>v7G}ScI%`jxxV4*V0D!Xt&TWz!54ojBp EAL{2i_W%F@ literal 0 HcmV?d00001 diff --git a/tests/riscv/c-extension/c.addi.disasm b/tests/riscv/c-extension/c.addi.disasm new file mode 100644 index 0000000..b1159b8 --- /dev/null +++ b/tests/riscv/c-extension/c.addi.disasm @@ -0,0 +1,91 @@ +c.addi ra, #-32 +c.addi ra, #-16 +c.addi ra, #-8 +c.addi ra, #-4 +c.addi ra, #-2 +c.addi ra, #-1 +c.addi ra, #0 +c.addi ra, #1 +c.addi ra, #2 +c.addi ra, #4 +c.addi ra, #8 +c.addi ra, #16 +c.addi ra, #31 +c.addi t0, #-32 +c.addi t0, #-16 +c.addi t0, #-8 +c.addi t0, #-4 +c.addi t0, #-2 +c.addi t0, #-1 +c.addi t0, #0 +c.addi t0, #1 +c.addi t0, #2 +c.addi t0, #4 +c.addi t0, #8 +c.addi t0, #16 +c.addi t0, #31 +c.addi a0, #-32 +c.addi a0, #-16 +c.addi a0, #-8 +c.addi a0, #-4 +c.addi a0, #-2 +c.addi a0, #-1 +c.addi a0, #0 +c.addi a0, #1 +c.addi a0, #2 +c.addi a0, #4 +c.addi a0, #8 +c.addi a0, #16 +c.addi a0, #31 +c.addi a5, #-32 +c.addi a5, #-16 +c.addi a5, #-8 +c.addi a5, #-4 +c.addi a5, #-2 +c.addi a5, #-1 +c.addi a5, #0 +c.addi a5, #1 +c.addi a5, #2 +c.addi a5, #4 +c.addi a5, #8 +c.addi a5, #16 +c.addi a5, #31 +c.addi s4, #-32 +c.addi s4, #-16 +c.addi s4, #-8 +c.addi s4, #-4 +c.addi s4, #-2 +c.addi s4, #-1 +c.addi s4, #0 +c.addi s4, #1 +c.addi s4, #2 +c.addi s4, #4 +c.addi s4, #8 +c.addi s4, #16 +c.addi s4, #31 +c.addi s9, #-32 +c.addi s9, #-16 +c.addi s9, #-8 +c.addi s9, #-4 +c.addi s9, #-2 +c.addi s9, #-1 +c.addi s9, #0 +c.addi s9, #1 +c.addi s9, #2 +c.addi s9, #4 +c.addi s9, #8 +c.addi s9, #16 +c.addi s9, #31 +c.addi t6, #-32 +c.addi t6, #-16 +c.addi t6, #-8 +c.addi t6, #-4 +c.addi t6, #-2 +c.addi t6, #-1 +c.addi t6, #0 +c.addi t6, #1 +c.addi t6, #2 +c.addi t6, #4 +c.addi t6, #8 +c.addi t6, #16 +c.addi t6, #31 diff --git a/tests/riscv/c-extension/c.addi16sp.asm b/tests/riscv/c-extension/c.addi16sp.asm new file mode 100644 index 0000000..e230fa5 --- /dev/null +++ b/tests/riscv/c-extension/c.addi16sp.asm @@ -0,0 +1,14 @@ +.lang riscv32 +.org 0x0 + +c.addi16sp #-512 +c.addi16sp #-256 +c.addi16sp #-128 +c.addi16sp #-64 +c.addi16sp #-32 +c.addi16sp #32 +c.addi16sp #64 +c.addi16sp #128 +c.addi16sp #256 +c.addi16sp #496 + diff --git a/tests/riscv/c-extension/c.addi16sp.bin b/tests/riscv/c-extension/c.addi16sp.bin new file mode 100644 index 0000000..15037a7 --- /dev/null +++ b/tests/riscv/c-extension/c.addi16sp.bin @@ -0,0 +1 @@ +!a1a9a=a=qqa aa]q \ No newline at end of file diff --git a/tests/riscv/c-extension/c.addi16sp.disasm b/tests/riscv/c-extension/c.addi16sp.disasm new file mode 100644 index 0000000..51bb5f0 --- /dev/null +++ b/tests/riscv/c-extension/c.addi16sp.disasm @@ -0,0 +1,46 @@ +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +c.addi16sp #-512 +c.addi16sp #-256 +c.addi16sp #-128 +c.addi16sp #-64 +c.addi16sp #-32 +c.addi16sp #32 +c.addi16sp #64 +c.addi16sp #128 +c.addi16sp #256 +c.addi16sp #496 diff --git a/tests/riscv/c-extension/c.addi4spn.asm b/tests/riscv/c-extension/c.addi4spn.asm new file mode 100644 index 0000000..3a4f179 --- /dev/null +++ b/tests/riscv/c-extension/c.addi4spn.asm @@ -0,0 +1,84 @@ +.lang riscv32 +.org 0x0 + +c.addi4spn s0, #0 +c.addi4spn s0, #4 +c.addi4spn s0, #8 +c.addi4spn s0, #16 +c.addi4spn s0, #32 +c.addi4spn s0, #64 +c.addi4spn s0, #128 +c.addi4spn s0, #256 +c.addi4spn s0, #512 +c.addi4spn s0, #1020 +c.addi4spn s1, #0 +c.addi4spn s1, #4 +c.addi4spn s1, #8 +c.addi4spn s1, #16 +c.addi4spn s1, #32 +c.addi4spn s1, #64 +c.addi4spn s1, #128 +c.addi4spn s1, #256 +c.addi4spn s1, #512 +c.addi4spn s1, #1020 +c.addi4spn a0, #0 +c.addi4spn a0, #4 +c.addi4spn a0, #8 +c.addi4spn a0, #16 +c.addi4spn a0, #32 +c.addi4spn a0, #64 +c.addi4spn a0, #128 +c.addi4spn a0, #256 +c.addi4spn a0, #512 +c.addi4spn a0, #1020 +c.addi4spn a1, #0 +c.addi4spn a1, #4 +c.addi4spn a1, #8 +c.addi4spn a1, #16 +c.addi4spn a1, #32 +c.addi4spn a1, #64 +c.addi4spn a1, #128 +c.addi4spn a1, #256 +c.addi4spn a1, #512 +c.addi4spn a1, #1020 +c.addi4spn a2, #0 +c.addi4spn a2, #4 +c.addi4spn a2, #8 +c.addi4spn a2, #16 +c.addi4spn a2, #32 +c.addi4spn a2, #64 +c.addi4spn a2, #128 +c.addi4spn a2, #256 +c.addi4spn a2, #512 +c.addi4spn a2, #1020 +c.addi4spn a3, #0 +c.addi4spn a3, #4 +c.addi4spn a3, #8 +c.addi4spn a3, #16 +c.addi4spn a3, #32 +c.addi4spn a3, #64 +c.addi4spn a3, #128 +c.addi4spn a3, #256 +c.addi4spn a3, #512 +c.addi4spn a3, #1020 +c.addi4spn a4, #0 +c.addi4spn a4, #4 +c.addi4spn a4, #8 +c.addi4spn a4, #16 +c.addi4spn a4, #32 +c.addi4spn a4, #64 +c.addi4spn a4, #128 +c.addi4spn a4, #256 +c.addi4spn a4, #512 +c.addi4spn a4, #1020 +c.addi4spn a5, #0 +c.addi4spn a5, #4 +c.addi4spn a5, #8 +c.addi4spn a5, #16 +c.addi4spn a5, #32 +c.addi4spn a5, #64 +c.addi4spn a5, #128 +c.addi4spn a5, #256 +c.addi4spn a5, #512 +c.addi4spn a5, #1020 + diff --git a/tests/riscv/c-extension/c.addi4spn.bin b/tests/riscv/c-extension/c.addi4spn.bin new file mode 100644 index 0000000000000000000000000000000000000000..c070c48216e5296010f2e8d37fb82fc9be3684d5 GIT binary patch literal 160 zcmV~$k=6o05P;Ed<_ruh3@j|{IrBph1VIo4K@bGN4?zzT1VIo4K@S%MK@bE%(7iC{ z51iP6px7;q1p~}2_L!KO-P2hz#NFe7i>uos3oAwxFL9(u(PGaG){F^{I1v&W_R7jX k6ROuZQ>ALPcQ!UmY2M;Olcvo++1WCqdygw!x_0~K53oxVQ2+n{ literal 0 HcmV?d00001 diff --git a/tests/riscv/c-extension/c.addi4spn.disasm b/tests/riscv/c-extension/c.addi4spn.disasm new file mode 100644 index 0000000..0487e72 --- /dev/null +++ b/tests/riscv/c-extension/c.addi4spn.disasm @@ -0,0 +1,80 @@ +c.addi4spn s0, #0 +c.addi4spn s0, #4 +c.addi4spn s0, #8 +c.addi4spn s0, #16 +c.addi4spn s0, #32 +c.addi4spn s0, #64 +c.addi4spn s0, #128 +c.addi4spn s0, #256 +c.addi4spn s0, #512 +c.addi4spn s0, #1020 +c.addi4spn s1, #0 +c.addi4spn s1, #4 +c.addi4spn s1, #8 +c.addi4spn s1, #16 +c.addi4spn s1, #32 +c.addi4spn s1, #64 +c.addi4spn s1, #128 +c.addi4spn s1, #256 +c.addi4spn s1, #512 +c.addi4spn s1, #1020 +c.addi4spn a0, #0 +c.addi4spn a0, #4 +c.addi4spn a0, #8 +c.addi4spn a0, #16 +c.addi4spn a0, #32 +c.addi4spn a0, #64 +c.addi4spn a0, #128 +c.addi4spn a0, #256 +c.addi4spn a0, #512 +c.addi4spn a0, #1020 +c.addi4spn a1, #0 +c.addi4spn a1, #4 +c.addi4spn a1, #8 +c.addi4spn a1, #16 +c.addi4spn a1, #32 +c.addi4spn a1, #64 +c.addi4spn a1, #128 +c.addi4spn a1, #256 +c.addi4spn a1, #512 +c.addi4spn a1, #1020 +c.addi4spn a2, #0 +c.addi4spn a2, #4 +c.addi4spn a2, #8 +c.addi4spn a2, #16 +c.addi4spn a2, #32 +c.addi4spn a2, #64 +c.addi4spn a2, #128 +c.addi4spn a2, #256 +c.addi4spn a2, #512 +c.addi4spn a2, #1020 +c.addi4spn a3, #0 +c.addi4spn a3, #4 +c.addi4spn a3, #8 +c.addi4spn a3, #16 +c.addi4spn a3, #32 +c.addi4spn a3, #64 +c.addi4spn a3, #128 +c.addi4spn a3, #256 +c.addi4spn a3, #512 +c.addi4spn a3, #1020 +c.addi4spn a4, #0 +c.addi4spn a4, #4 +c.addi4spn a4, #8 +c.addi4spn a4, #16 +c.addi4spn a4, #32 +c.addi4spn a4, #64 +c.addi4spn a4, #128 +c.addi4spn a4, #256 +c.addi4spn a4, #512 +c.addi4spn a4, #1020 +c.addi4spn a5, #0 +c.addi4spn a5, #4 +c.addi4spn a5, #8 +c.addi4spn a5, #16 +c.addi4spn a5, #32 +c.addi4spn a5, #64 +c.addi4spn a5, #128 +c.addi4spn a5, #256 +c.addi4spn a5, #512 +c.addi4spn a5, #1020 diff --git a/tests/riscv/c-extension/c.and.asm b/tests/riscv/c-extension/c.and.asm new file mode 100644 index 0000000..d306066 --- /dev/null +++ b/tests/riscv/c-extension/c.and.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +c.and s0, s0 +c.and s0, s1 +c.and s0, a0 +c.and s0, a1 +c.and s0, a2 +c.and s0, a3 +c.and s0, a4 +c.and s0, a5 +c.and s1, s0 +c.and s1, s1 +c.and s1, a0 +c.and s1, a1 +c.and s1, a2 +c.and s1, a3 +c.and s1, a4 +c.and s1, a5 +c.and a0, s0 +c.and a0, s1 +c.and a0, a0 +c.and a0, a1 +c.and a0, a2 +c.and a0, a3 +c.and a0, a4 +c.and a0, a5 +c.and a1, s0 +c.and a1, s1 +c.and a1, a0 +c.and a1, a1 +c.and a1, a2 +c.and a1, a3 +c.and a1, a4 +c.and a1, a5 +c.and a2, s0 +c.and a2, s1 +c.and a2, a0 +c.and a2, a1 +c.and a2, a2 +c.and a2, a3 +c.and a2, a4 +c.and a2, a5 +c.and a3, s0 +c.and a3, s1 +c.and a3, a0 +c.and a3, a1 +c.and a3, a2 +c.and a3, a3 +c.and a3, a4 +c.and a3, a5 +c.and a4, s0 +c.and a4, s1 +c.and a4, a0 +c.and a4, a1 +c.and a4, a2 +c.and a4, a3 +c.and a4, a4 +c.and a4, a5 +c.and a5, s0 +c.and a5, s1 +c.and a5, a0 +c.and a5, a1 +c.and a5, a2 +c.and a5, a3 +c.and a5, a4 +c.and a5, a5 + diff --git a/tests/riscv/c-extension/c.and.bin b/tests/riscv/c-extension/c.and.bin new file mode 100644 index 0000000..ac31941 --- /dev/null +++ b/tests/riscv/c-extension/c.and.bin @@ -0,0 +1 @@ +aeimquy}aeimquy}aeimquy}aeimquy} \ No newline at end of file diff --git a/tests/riscv/c-extension/c.and.disasm b/tests/riscv/c-extension/c.and.disasm new file mode 100644 index 0000000..ef33fec --- /dev/null +++ b/tests/riscv/c-extension/c.and.disasm @@ -0,0 +1,64 @@ +c.and s0, s0 +c.and s0, s1 +c.and s0, a0 +c.and s0, a1 +c.and s0, a2 +c.and s0, a3 +c.and s0, a4 +c.and s0, a5 +c.and s1, s0 +c.and s1, s1 +c.and s1, a0 +c.and s1, a1 +c.and s1, a2 +c.and s1, a3 +c.and s1, a4 +c.and s1, a5 +c.and a0, s0 +c.and a0, s1 +c.and a0, a0 +c.and a0, a1 +c.and a0, a2 +c.and a0, a3 +c.and a0, a4 +c.and a0, a5 +c.and a1, s0 +c.and a1, s1 +c.and a1, a0 +c.and a1, a1 +c.and a1, a2 +c.and a1, a3 +c.and a1, a4 +c.and a1, a5 +c.and a2, s0 +c.and a2, s1 +c.and a2, a0 +c.and a2, a1 +c.and a2, a2 +c.and a2, a3 +c.and a2, a4 +c.and a2, a5 +c.and a3, s0 +c.and a3, s1 +c.and a3, a0 +c.and a3, a1 +c.and a3, a2 +c.and a3, a3 +c.and a3, a4 +c.and a3, a5 +c.and a4, s0 +c.and a4, s1 +c.and a4, a0 +c.and a4, a1 +c.and a4, a2 +c.and a4, a3 +c.and a4, a4 +c.and a4, a5 +c.and a5, s0 +c.and a5, s1 +c.and a5, a0 +c.and a5, a1 +c.and a5, a2 +c.and a5, a3 +c.and a5, a4 +c.and a5, a5 diff --git a/tests/riscv/c-extension/c.andi.asm b/tests/riscv/c-extension/c.andi.asm new file mode 100644 index 0000000..c6fa27b --- /dev/null +++ b/tests/riscv/c-extension/c.andi.asm @@ -0,0 +1,108 @@ +.lang riscv32 +.org 0x0 + +c.andi s0, #-32 +c.andi s0, #-16 +c.andi s0, #-8 +c.andi s0, #-4 +c.andi s0, #-2 +c.andi s0, #-1 +c.andi s0, #0 +c.andi s0, #1 +c.andi s0, #2 +c.andi s0, #4 +c.andi s0, #8 +c.andi s0, #16 +c.andi s0, #31 +c.andi s1, #-32 +c.andi s1, #-16 +c.andi s1, #-8 +c.andi s1, #-4 +c.andi s1, #-2 +c.andi s1, #-1 +c.andi s1, #0 +c.andi s1, #1 +c.andi s1, #2 +c.andi s1, #4 +c.andi s1, #8 +c.andi s1, #16 +c.andi s1, #31 +c.andi a0, #-32 +c.andi a0, #-16 +c.andi a0, #-8 +c.andi a0, #-4 +c.andi a0, #-2 +c.andi a0, #-1 +c.andi a0, #0 +c.andi a0, #1 +c.andi a0, #2 +c.andi a0, #4 +c.andi a0, #8 +c.andi a0, #16 +c.andi a0, #31 +c.andi a1, #-32 +c.andi a1, #-16 +c.andi a1, #-8 +c.andi a1, #-4 +c.andi a1, #-2 +c.andi a1, #-1 +c.andi a1, #0 +c.andi a1, #1 +c.andi a1, #2 +c.andi a1, #4 +c.andi a1, #8 +c.andi a1, #16 +c.andi a1, #31 +c.andi a2, #-32 +c.andi a2, #-16 +c.andi a2, #-8 +c.andi a2, #-4 +c.andi a2, #-2 +c.andi a2, #-1 +c.andi a2, #0 +c.andi a2, #1 +c.andi a2, #2 +c.andi a2, #4 +c.andi a2, #8 +c.andi a2, #16 +c.andi a2, #31 +c.andi a3, #-32 +c.andi a3, #-16 +c.andi a3, #-8 +c.andi a3, #-4 +c.andi a3, #-2 +c.andi a3, #-1 +c.andi a3, #0 +c.andi a3, #1 +c.andi a3, #2 +c.andi a3, #4 +c.andi a3, #8 +c.andi a3, #16 +c.andi a3, #31 +c.andi a4, #-32 +c.andi a4, #-16 +c.andi a4, #-8 +c.andi a4, #-4 +c.andi a4, #-2 +c.andi a4, #-1 +c.andi a4, #0 +c.andi a4, #1 +c.andi a4, #2 +c.andi a4, #4 +c.andi a4, #8 +c.andi a4, #16 +c.andi a4, #31 +c.andi a5, #-32 +c.andi a5, #-16 +c.andi a5, #-8 +c.andi a5, #-4 +c.andi a5, #-2 +c.andi a5, #-1 +c.andi a5, #0 +c.andi a5, #1 +c.andi a5, #2 +c.andi a5, #4 +c.andi a5, #8 +c.andi a5, #16 +c.andi a5, #31 + diff --git a/tests/riscv/c-extension/c.andi.bin b/tests/riscv/c-extension/c.andi.bin new file mode 100644 index 0000000..3fd36ea --- /dev/null +++ b/tests/riscv/c-extension/c.andi.bin @@ -0,0 +1 @@ +Aaqy} !A}Aaqy} !A}Aaqy} !A}Aaqy} !A} \ No newline at end of file diff --git a/tests/riscv/c-extension/c.andi.disasm b/tests/riscv/c-extension/c.andi.disasm new file mode 100644 index 0000000..b4f5049 --- /dev/null +++ b/tests/riscv/c-extension/c.andi.disasm @@ -0,0 +1,104 @@ +c.andi s0, #-32 +c.andi s0, #-16 +c.andi s0, #-8 +c.andi s0, #-4 +c.andi s0, #-2 +c.andi s0, #-1 +c.andi s0, #0 +c.andi s0, #1 +c.andi s0, #2 +c.andi s0, #4 +c.andi s0, #8 +c.andi s0, #16 +c.andi s0, #31 +c.andi s1, #-32 +c.andi s1, #-16 +c.andi s1, #-8 +c.andi s1, #-4 +c.andi s1, #-2 +c.andi s1, #-1 +c.andi s1, #0 +c.andi s1, #1 +c.andi s1, #2 +c.andi s1, #4 +c.andi s1, #8 +c.andi s1, #16 +c.andi s1, #31 +c.andi a0, #-32 +c.andi a0, #-16 +c.andi a0, #-8 +c.andi a0, #-4 +c.andi a0, #-2 +c.andi a0, #-1 +c.andi a0, #0 +c.andi a0, #1 +c.andi a0, #2 +c.andi a0, #4 +c.andi a0, #8 +c.andi a0, #16 +c.andi a0, #31 +c.andi a1, #-32 +c.andi a1, #-16 +c.andi a1, #-8 +c.andi a1, #-4 +c.andi a1, #-2 +c.andi a1, #-1 +c.andi a1, #0 +c.andi a1, #1 +c.andi a1, #2 +c.andi a1, #4 +c.andi a1, #8 +c.andi a1, #16 +c.andi a1, #31 +c.andi a2, #-32 +c.andi a2, #-16 +c.andi a2, #-8 +c.andi a2, #-4 +c.andi a2, #-2 +c.andi a2, #-1 +c.andi a2, #0 +c.andi a2, #1 +c.andi a2, #2 +c.andi a2, #4 +c.andi a2, #8 +c.andi a2, #16 +c.andi a2, #31 +c.andi a3, #-32 +c.andi a3, #-16 +c.andi a3, #-8 +c.andi a3, #-4 +c.andi a3, #-2 +c.andi a3, #-1 +c.andi a3, #0 +c.andi a3, #1 +c.andi a3, #2 +c.andi a3, #4 +c.andi a3, #8 +c.andi a3, #16 +c.andi a3, #31 +c.andi a4, #-32 +c.andi a4, #-16 +c.andi a4, #-8 +c.andi a4, #-4 +c.andi a4, #-2 +c.andi a4, #-1 +c.andi a4, #0 +c.andi a4, #1 +c.andi a4, #2 +c.andi a4, #4 +c.andi a4, #8 +c.andi a4, #16 +c.andi a4, #31 +c.andi a5, #-32 +c.andi a5, #-16 +c.andi a5, #-8 +c.andi a5, #-4 +c.andi a5, #-2 +c.andi a5, #-1 +c.andi a5, #0 +c.andi a5, #1 +c.andi a5, #2 +c.andi a5, #4 +c.andi a5, #8 +c.andi a5, #16 +c.andi a5, #31 diff --git a/tests/riscv/c-extension/c.beqz.asm b/tests/riscv/c-extension/c.beqz.asm new file mode 100644 index 0000000..07144a0 --- /dev/null +++ b/tests/riscv/c-extension/c.beqz.asm @@ -0,0 +1,164 @@ +.lang riscv32 +.org 0x0 + +c.beqz s0, label_0 +label_0: +c.beqz s0, label_1 +label_1: +c.beqz s0, label_2 +label_2: +c.beqz s0, label_3 +label_3: +c.beqz s0, label_4 +label_4: +c.beqz s0, label_5 +label_5: +c.beqz s0, label_6 +label_6: +c.beqz s0, label_7 +label_7: +c.beqz s0, label_8 +label_8: +c.beqz s0, label_9 +label_9: +c.beqz s1, label_0 +label_0: +c.beqz s1, label_1 +label_1: +c.beqz s1, label_2 +label_2: +c.beqz s1, label_3 +label_3: +c.beqz s1, label_4 +label_4: +c.beqz s1, label_5 +label_5: +c.beqz s1, label_6 +label_6: +c.beqz s1, label_7 +label_7: +c.beqz s1, label_8 +label_8: +c.beqz s1, label_9 +label_9: +c.beqz a0, label_0 +label_0: +c.beqz a0, label_1 +label_1: +c.beqz a0, label_2 +label_2: +c.beqz a0, label_3 +label_3: +c.beqz a0, label_4 +label_4: +c.beqz a0, label_5 +label_5: +c.beqz a0, label_6 +label_6: +c.beqz a0, label_7 +label_7: +c.beqz a0, label_8 +label_8: +c.beqz a0, label_9 +label_9: +c.beqz a1, label_0 +label_0: +c.beqz a1, label_1 +label_1: +c.beqz a1, label_2 +label_2: +c.beqz a1, label_3 +label_3: +c.beqz a1, label_4 +label_4: +c.beqz a1, label_5 +label_5: +c.beqz a1, label_6 +label_6: +c.beqz a1, label_7 +label_7: +c.beqz a1, label_8 +label_8: +c.beqz a1, label_9 +label_9: +c.beqz a2, label_0 +label_0: +c.beqz a2, label_1 +label_1: +c.beqz a2, label_2 +label_2: +c.beqz a2, label_3 +label_3: +c.beqz a2, label_4 +label_4: +c.beqz a2, label_5 +label_5: +c.beqz a2, label_6 +label_6: +c.beqz a2, label_7 +label_7: +c.beqz a2, label_8 +label_8: +c.beqz a2, label_9 +label_9: +c.beqz a3, label_0 +label_0: +c.beqz a3, label_1 +label_1: +c.beqz a3, label_2 +label_2: +c.beqz a3, label_3 +label_3: +c.beqz a3, label_4 +label_4: +c.beqz a3, label_5 +label_5: +c.beqz a3, label_6 +label_6: +c.beqz a3, label_7 +label_7: +c.beqz a3, label_8 +label_8: +c.beqz a3, label_9 +label_9: +c.beqz a4, label_0 +label_0: +c.beqz a4, label_1 +label_1: +c.beqz a4, label_2 +label_2: +c.beqz a4, label_3 +label_3: +c.beqz a4, label_4 +label_4: +c.beqz a4, label_5 +label_5: +c.beqz a4, label_6 +label_6: +c.beqz a4, label_7 +label_7: +c.beqz a4, label_8 +label_8: +c.beqz a4, label_9 +label_9: +c.beqz a5, label_0 +label_0: +c.beqz a5, label_1 +label_1: +c.beqz a5, label_2 +label_2: +c.beqz a5, label_3 +label_3: +c.beqz a5, label_4 +label_4: +c.beqz a5, label_5 +label_5: +c.beqz a5, label_6 +label_6: +c.beqz a5, label_7 +label_7: +c.beqz a5, label_8 +label_8: +c.beqz a5, label_9 +label_9: + diff --git a/tests/riscv/c-extension/c.beqz.bin b/tests/riscv/c-extension/c.beqz.bin new file mode 100644 index 0000000..d34ca12 --- /dev/null +++ b/tests/riscv/c-extension/c.beqz.bin @@ -0,0 +1 @@ +YYYYYYYYYY}}}}}}}}}}}}}}}}}}}}}}}}}}}}}} \ No newline at end of file diff --git a/tests/riscv/c-extension/c.beqz.disasm b/tests/riscv/c-extension/c.beqz.disasm new file mode 100644 index 0000000..2ac95a0 --- /dev/null +++ b/tests/riscv/c-extension/c.beqz.disasm @@ -0,0 +1,80 @@ +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s0, #142 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz s1, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a0, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a1, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a2, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a3, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a4, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 +c.beqz a5, #-18 diff --git a/tests/riscv/c-extension/c.bnez.asm b/tests/riscv/c-extension/c.bnez.asm new file mode 100644 index 0000000..d6425ac --- /dev/null +++ b/tests/riscv/c-extension/c.bnez.asm @@ -0,0 +1,164 @@ +.lang riscv32 +.org 0x0 + +c.bnez s0, label_0 +label_0: +c.bnez s0, label_1 +label_1: +c.bnez s0, label_2 +label_2: +c.bnez s0, label_3 +label_3: +c.bnez s0, label_4 +label_4: +c.bnez s0, label_5 +label_5: +c.bnez s0, label_6 +label_6: +c.bnez s0, label_7 +label_7: +c.bnez s0, label_8 +label_8: +c.bnez s0, label_9 +label_9: +c.bnez s1, label_0 +label_0: +c.bnez s1, label_1 +label_1: +c.bnez s1, label_2 +label_2: +c.bnez s1, label_3 +label_3: +c.bnez s1, label_4 +label_4: +c.bnez s1, label_5 +label_5: +c.bnez s1, label_6 +label_6: +c.bnez s1, label_7 +label_7: +c.bnez s1, label_8 +label_8: +c.bnez s1, label_9 +label_9: +c.bnez a0, label_0 +label_0: +c.bnez a0, label_1 +label_1: +c.bnez a0, label_2 +label_2: +c.bnez a0, label_3 +label_3: +c.bnez a0, label_4 +label_4: +c.bnez a0, label_5 +label_5: +c.bnez a0, label_6 +label_6: +c.bnez a0, label_7 +label_7: +c.bnez a0, label_8 +label_8: +c.bnez a0, label_9 +label_9: +c.bnez a1, label_0 +label_0: +c.bnez a1, label_1 +label_1: +c.bnez a1, label_2 +label_2: +c.bnez a1, label_3 +label_3: +c.bnez a1, label_4 +label_4: +c.bnez a1, label_5 +label_5: +c.bnez a1, label_6 +label_6: +c.bnez a1, label_7 +label_7: +c.bnez a1, label_8 +label_8: +c.bnez a1, label_9 +label_9: +c.bnez a2, label_0 +label_0: +c.bnez a2, label_1 +label_1: +c.bnez a2, label_2 +label_2: +c.bnez a2, label_3 +label_3: +c.bnez a2, label_4 +label_4: +c.bnez a2, label_5 +label_5: +c.bnez a2, label_6 +label_6: +c.bnez a2, label_7 +label_7: +c.bnez a2, label_8 +label_8: +c.bnez a2, label_9 +label_9: +c.bnez a3, label_0 +label_0: +c.bnez a3, label_1 +label_1: +c.bnez a3, label_2 +label_2: +c.bnez a3, label_3 +label_3: +c.bnez a3, label_4 +label_4: +c.bnez a3, label_5 +label_5: +c.bnez a3, label_6 +label_6: +c.bnez a3, label_7 +label_7: +c.bnez a3, label_8 +label_8: +c.bnez a3, label_9 +label_9: +c.bnez a4, label_0 +label_0: +c.bnez a4, label_1 +label_1: +c.bnez a4, label_2 +label_2: +c.bnez a4, label_3 +label_3: +c.bnez a4, label_4 +label_4: +c.bnez a4, label_5 +label_5: +c.bnez a4, label_6 +label_6: +c.bnez a4, label_7 +label_7: +c.bnez a4, label_8 +label_8: +c.bnez a4, label_9 +label_9: +c.bnez a5, label_0 +label_0: +c.bnez a5, label_1 +label_1: +c.bnez a5, label_2 +label_2: +c.bnez a5, label_3 +label_3: +c.bnez a5, label_4 +label_4: +c.bnez a5, label_5 +label_5: +c.bnez a5, label_6 +label_6: +c.bnez a5, label_7 +label_7: +c.bnez a5, label_8 +label_8: +c.bnez a5, label_9 +label_9: + diff --git a/tests/riscv/c-extension/c.bnez.bin b/tests/riscv/c-extension/c.bnez.bin new file mode 100644 index 0000000..9236dd7 --- /dev/null +++ b/tests/riscv/c-extension/c.bnez.bin @@ -0,0 +1 @@ +YYYYYYYYYY}}}}}}}}}}}}}}}}}}}}}}}}}}}}}} \ No newline at end of file diff --git a/tests/riscv/c-extension/c.bnez.disasm b/tests/riscv/c-extension/c.bnez.disasm new file mode 100644 index 0000000..d2dd1c6 --- /dev/null +++ b/tests/riscv/c-extension/c.bnez.disasm @@ -0,0 +1,80 @@ +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s0, #142 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez s1, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a0, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a1, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a2, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a3, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a4, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 +c.bnez a5, #-18 diff --git a/tests/riscv/c-extension/c.ebreak.asm b/tests/riscv/c-extension/c.ebreak.asm new file mode 100644 index 0000000..a3706a5 --- /dev/null +++ b/tests/riscv/c-extension/c.ebreak.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.ebreak + diff --git a/tests/riscv/c-extension/c.ebreak.bin b/tests/riscv/c-extension/c.ebreak.bin new file mode 100644 index 0000000..c0dc987 --- /dev/null +++ b/tests/riscv/c-extension/c.ebreak.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c.ebreak.disasm b/tests/riscv/c-extension/c.ebreak.disasm new file mode 100644 index 0000000..d1cda2d --- /dev/null +++ b/tests/riscv/c-extension/c.ebreak.disasm @@ -0,0 +1,10 @@ +Colliding matches: "c.ebreak c.add " +1: "c.ebreak" +2: "c.add a0, a1" +Colliding matches: "c.ebreak c.add " +1: "c.ebreak" +2: "c.add a0, a1" +Colliding matches: "c.ebreak c.add " +1: "c.ebreak" +2: "c.add a0, a1" +c.ebreak diff --git a/tests/riscv/c-extension/c.j.asm b/tests/riscv/c-extension/c.j.asm new file mode 100644 index 0000000..4ff1529 --- /dev/null +++ b/tests/riscv/c-extension/c.j.asm @@ -0,0 +1,24 @@ +.lang riscv32 +.org 0x0 + +c.j label_0 +label_0: +c.j label_1 +label_1: +c.j label_2 +label_2: +c.j label_3 +label_3: +c.j label_4 +label_4: +c.j label_5 +label_5: +c.j label_6 +label_6: +c.j label_7 +label_7: +c.j label_8 +label_8: +c.j label_9 +label_9: + diff --git a/tests/riscv/c-extension/c.j.bin b/tests/riscv/c-extension/c.j.bin new file mode 100644 index 0000000..10b6239 --- /dev/null +++ b/tests/riscv/c-extension/c.j.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c.j.disasm b/tests/riscv/c-extension/c.j.disasm new file mode 100644 index 0000000..b3b9399 --- /dev/null +++ b/tests/riscv/c-extension/c.j.disasm @@ -0,0 +1,10 @@ +c.j #2 +c.j #2 +c.j #2 +c.j #2 +c.j #2 +c.j #2 +c.j #2 +c.j #2 +c.j #2 +c.j #2 diff --git a/tests/riscv/c-extension/c.jalr.asm b/tests/riscv/c-extension/c.jalr.asm new file mode 100644 index 0000000..01d4edc --- /dev/null +++ b/tests/riscv/c-extension/c.jalr.asm @@ -0,0 +1,11 @@ +.lang riscv32 +.org 0x0 + +c.jalr ra +c.jalr t0 +c.jalr a0 +c.jalr a5 +c.jalr s4 +c.jalr s9 +c.jalr t6 + diff --git a/tests/riscv/c-extension/c.jalr.bin b/tests/riscv/c-extension/c.jalr.bin new file mode 100644 index 0000000..f92e1c2 --- /dev/null +++ b/tests/riscv/c-extension/c.jalr.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c.jalr.disasm b/tests/riscv/c-extension/c.jalr.disasm new file mode 100644 index 0000000..024cc30 --- /dev/null +++ b/tests/riscv/c-extension/c.jalr.disasm @@ -0,0 +1,34 @@ +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +c.jalr ra +c.jalr t0 +c.jalr a0 +c.jalr a5 +c.jalr s4 +c.jalr s9 +c.jalr t6 diff --git a/tests/riscv/c-extension/c.jr.asm b/tests/riscv/c-extension/c.jr.asm new file mode 100644 index 0000000..e7585cd --- /dev/null +++ b/tests/riscv/c-extension/c.jr.asm @@ -0,0 +1,11 @@ +.lang riscv32 +.org 0x0 + +c.jr ra +c.jr t0 +c.jr a0 +c.jr a5 +c.jr s4 +c.jr s9 +c.jr t6 + diff --git a/tests/riscv/c-extension/c.jr.bin b/tests/riscv/c-extension/c.jr.bin new file mode 100644 index 0000000..ecaeec5 --- /dev/null +++ b/tests/riscv/c-extension/c.jr.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c.jr.disasm b/tests/riscv/c-extension/c.jr.disasm new file mode 100644 index 0000000..9bd5bae --- /dev/null +++ b/tests/riscv/c-extension/c.jr.disasm @@ -0,0 +1,7 @@ +c.jr ra +c.jr t0 +c.jr a0 +c.jr a5 +c.jr s4 +c.jr s9 +c.jr t6 diff --git a/tests/riscv/c-extension/c.li.asm b/tests/riscv/c-extension/c.li.asm new file mode 100644 index 0000000..99e4ddf --- /dev/null +++ b/tests/riscv/c-extension/c.li.asm @@ -0,0 +1,95 @@ +.lang riscv32 +.org 0x0 + +c.li ra, #-32 +c.li ra, #-16 +c.li ra, #-8 +c.li ra, #-4 +c.li ra, #-2 +c.li ra, #-1 +c.li ra, #0 +c.li ra, #1 +c.li ra, #2 +c.li ra, #4 +c.li ra, #8 +c.li ra, #16 +c.li ra, #31 +c.li t0, #-32 +c.li t0, #-16 +c.li t0, #-8 +c.li t0, #-4 +c.li t0, #-2 +c.li t0, #-1 +c.li t0, #0 +c.li t0, #1 +c.li t0, #2 +c.li t0, #4 +c.li t0, #8 +c.li t0, #16 +c.li t0, #31 +c.li a0, #-32 +c.li a0, #-16 +c.li a0, #-8 +c.li a0, #-4 +c.li a0, #-2 +c.li a0, #-1 +c.li a0, #0 +c.li a0, #1 +c.li a0, #2 +c.li a0, #4 +c.li a0, #8 +c.li a0, #16 +c.li a0, #31 +c.li a5, #-32 +c.li a5, #-16 +c.li a5, #-8 +c.li a5, #-4 +c.li a5, #-2 +c.li a5, #-1 +c.li a5, #0 +c.li a5, #1 +c.li a5, #2 +c.li a5, #4 +c.li a5, #8 +c.li a5, #16 +c.li a5, #31 +c.li s4, #-32 +c.li s4, #-16 +c.li s4, #-8 +c.li s4, #-4 +c.li s4, #-2 +c.li s4, #-1 +c.li s4, #0 +c.li s4, #1 +c.li s4, #2 +c.li s4, #4 +c.li s4, #8 +c.li s4, #16 +c.li s4, #31 +c.li s9, #-32 +c.li s9, #-16 +c.li s9, #-8 +c.li s9, #-4 +c.li s9, #-2 +c.li s9, #-1 +c.li s9, #0 +c.li s9, #1 +c.li s9, #2 +c.li s9, #4 +c.li s9, #8 +c.li s9, #16 +c.li s9, #31 +c.li t6, #-32 +c.li t6, #-16 +c.li t6, #-8 +c.li t6, #-4 +c.li t6, #-2 +c.li t6, #-1 +c.li t6, #0 +c.li t6, #1 +c.li t6, #2 +c.li t6, #4 +c.li t6, #8 +c.li t6, #16 +c.li t6, #31 + diff --git a/tests/riscv/c-extension/c.li.bin b/tests/riscv/c-extension/c.li.bin new file mode 100644 index 0000000..c9e0da3 --- /dev/null +++ b/tests/riscv/c-extension/c.li.bin @@ -0,0 +1 @@ +PPPPPP@@@@@@@RRRRRRBBBBBBBUAUaUqUyU}UEE EE!EAE}EWWWWWWGGGGGGGZAZaZqZyZ}ZJJ JJ!JAJ}J\\\\\\LLLLLLL______OOOOOOO \ No newline at end of file diff --git a/tests/riscv/c-extension/c.li.disasm b/tests/riscv/c-extension/c.li.disasm new file mode 100644 index 0000000..196df9c --- /dev/null +++ b/tests/riscv/c-extension/c.li.disasm @@ -0,0 +1,91 @@ +c.li ra, #-32 +c.li ra, #-16 +c.li ra, #-8 +c.li ra, #-4 +c.li ra, #-2 +c.li ra, #-1 +c.li ra, #0 +c.li ra, #1 +c.li ra, #2 +c.li ra, #4 +c.li ra, #8 +c.li ra, #16 +c.li ra, #31 +c.li t0, #-32 +c.li t0, #-16 +c.li t0, #-8 +c.li t0, #-4 +c.li t0, #-2 +c.li t0, #-1 +c.li t0, #0 +c.li t0, #1 +c.li t0, #2 +c.li t0, #4 +c.li t0, #8 +c.li t0, #16 +c.li t0, #31 +c.li a0, #-32 +c.li a0, #-16 +c.li a0, #-8 +c.li a0, #-4 +c.li a0, #-2 +c.li a0, #-1 +c.li a0, #0 +c.li a0, #1 +c.li a0, #2 +c.li a0, #4 +c.li a0, #8 +c.li a0, #16 +c.li a0, #31 +c.li a5, #-32 +c.li a5, #-16 +c.li a5, #-8 +c.li a5, #-4 +c.li a5, #-2 +c.li a5, #-1 +c.li a5, #0 +c.li a5, #1 +c.li a5, #2 +c.li a5, #4 +c.li a5, #8 +c.li a5, #16 +c.li a5, #31 +c.li s4, #-32 +c.li s4, #-16 +c.li s4, #-8 +c.li s4, #-4 +c.li s4, #-2 +c.li s4, #-1 +c.li s4, #0 +c.li s4, #1 +c.li s4, #2 +c.li s4, #4 +c.li s4, #8 +c.li s4, #16 +c.li s4, #31 +c.li s9, #-32 +c.li s9, #-16 +c.li s9, #-8 +c.li s9, #-4 +c.li s9, #-2 +c.li s9, #-1 +c.li s9, #0 +c.li s9, #1 +c.li s9, #2 +c.li s9, #4 +c.li s9, #8 +c.li s9, #16 +c.li s9, #31 +c.li t6, #-32 +c.li t6, #-16 +c.li t6, #-8 +c.li t6, #-4 +c.li t6, #-2 +c.li t6, #-1 +c.li t6, #0 +c.li t6, #1 +c.li t6, #2 +c.li t6, #4 +c.li t6, #8 +c.li t6, #16 +c.li t6, #31 diff --git a/tests/riscv/c-extension/c.lui.asm b/tests/riscv/c-extension/c.lui.asm new file mode 100644 index 0000000..39f0136 --- /dev/null +++ b/tests/riscv/c-extension/c.lui.asm @@ -0,0 +1,62 @@ +.lang riscv32 +.org 0x0 + +; c.lui uses 6-bit signed immediate nzimm[17:12] +; Valid positive range: 0x1000 to 0x1F000 (imm = 1 to 31) +; Valid negative range: 0xFFFE0000 to 0xFFFFF000 (imm = -32 to -1) + +c.lui gp, #0x1000 +c.lui gp, #0x2000 +c.lui gp, #0x4000 +c.lui gp, #0x8000 +c.lui gp, #0xf000 +c.lui gp, #0x1f000 +c.lui tp, #0x1000 +c.lui tp, #0x2000 +c.lui tp, #0x4000 +c.lui tp, #0x8000 +c.lui tp, #0xf000 +c.lui tp, #0x1f000 +c.lui t0, #0x1000 +c.lui t0, #0x2000 +c.lui t0, #0x4000 +c.lui t0, #0x8000 +c.lui t0, #0xf000 +c.lui t0, #0x1f000 +c.lui t1, #0x1000 +c.lui t1, #0x2000 +c.lui t1, #0x4000 +c.lui t1, #0x8000 +c.lui t1, #0xf000 +c.lui t1, #0x1f000 +c.lui t2, #0x1000 +c.lui t2, #0x2000 +c.lui t2, #0x4000 +c.lui t2, #0x8000 +c.lui t2, #0xf000 +c.lui t2, #0x1f000 +c.lui t3, #0x1000 +c.lui t3, #0x2000 +c.lui t3, #0x4000 +c.lui t3, #0x8000 +c.lui t3, #0xf000 +c.lui t3, #0x1f000 +c.lui t4, #0x1000 +c.lui t4, #0x2000 +c.lui t4, #0x4000 +c.lui t4, #0x8000 +c.lui t4, #0xf000 +c.lui t4, #0x1f000 +c.lui t5, #0x1000 +c.lui t5, #0x2000 +c.lui t5, #0x4000 +c.lui t5, #0x8000 +c.lui t5, #0xf000 +c.lui t5, #0x1f000 +c.lui t6, #0x1000 +c.lui t6, #0x2000 +c.lui t6, #0x4000 +c.lui t6, #0x8000 +c.lui t6, #0xf000 +c.lui t6, #0x1f000 + diff --git a/tests/riscv/c-extension/c.lui.bin b/tests/riscv/c-extension/c.lui.bin new file mode 100644 index 0000000..3f3a020 --- /dev/null +++ b/tests/riscv/c-extension/c.lui.bin @@ -0,0 +1 @@ +aaaaaab bb!b=b}bbbbbbbc cc!c=c}cccccccn nn!n=n}nnnnnnno oo!o=o}ooooooo \ No newline at end of file diff --git a/tests/riscv/c-extension/c.lui.disasm b/tests/riscv/c-extension/c.lui.disasm new file mode 100644 index 0000000..209ad86 --- /dev/null +++ b/tests/riscv/c-extension/c.lui.disasm @@ -0,0 +1,54 @@ +c.lui gp, #0x1000 +c.lui gp, #0x2000 +c.lui gp, #0x4000 +c.lui gp, #0x8000 +c.lui gp, #0xf000 +c.lui gp, #0x1f000 +c.lui tp, #0x1000 +c.lui tp, #0x2000 +c.lui tp, #0x4000 +c.lui tp, #0x8000 +c.lui tp, #0xf000 +c.lui tp, #0x1f000 +c.lui t0, #0x1000 +c.lui t0, #0x2000 +c.lui t0, #0x4000 +c.lui t0, #0x8000 +c.lui t0, #0xf000 +c.lui t0, #0x1f000 +c.lui t1, #0x1000 +c.lui t1, #0x2000 +c.lui t1, #0x4000 +c.lui t1, #0x8000 +c.lui t1, #0xf000 +c.lui t1, #0x1f000 +c.lui t2, #0x1000 +c.lui t2, #0x2000 +c.lui t2, #0x4000 +c.lui t2, #0x8000 +c.lui t2, #0xf000 +c.lui t2, #0x1f000 +c.lui t3, #0x1000 +c.lui t3, #0x2000 +c.lui t3, #0x4000 +c.lui t3, #0x8000 +c.lui t3, #0xf000 +c.lui t3, #0x1f000 +c.lui t4, #0x1000 +c.lui t4, #0x2000 +c.lui t4, #0x4000 +c.lui t4, #0x8000 +c.lui t4, #0xf000 +c.lui t4, #0x1f000 +c.lui t5, #0x1000 +c.lui t5, #0x2000 +c.lui t5, #0x4000 +c.lui t5, #0x8000 +c.lui t5, #0xf000 +c.lui t5, #0x1f000 +c.lui t6, #0x1000 +c.lui t6, #0x2000 +c.lui t6, #0x4000 +c.lui t6, #0x8000 +c.lui t6, #0xf000 +c.lui t6, #0x1f000 diff --git a/tests/riscv/c-extension/c.lw.asm b/tests/riscv/c-extension/c.lw.asm new file mode 100644 index 0000000..c7f7a96 --- /dev/null +++ b/tests/riscv/c-extension/c.lw.asm @@ -0,0 +1,452 @@ +.lang riscv32 +.org 0x0 + +c.lw s0, (#0, s0) +c.lw s0, (#4, s0) +c.lw s0, (#8, s0) +c.lw s0, (#16, s0) +c.lw s0, (#32, s0) +c.lw s0, (#64, s0) +c.lw s0, (#124, s0) +c.lw s0, (#0, s1) +c.lw s0, (#4, s1) +c.lw s0, (#8, s1) +c.lw s0, (#16, s1) +c.lw s0, (#32, s1) +c.lw s0, (#64, s1) +c.lw s0, (#124, s1) +c.lw s0, (#0, a0) +c.lw s0, (#4, a0) +c.lw s0, (#8, a0) +c.lw s0, (#16, a0) +c.lw s0, (#32, a0) +c.lw s0, (#64, a0) +c.lw s0, (#124, a0) +c.lw s0, (#0, a1) +c.lw s0, (#4, a1) +c.lw s0, (#8, a1) +c.lw s0, (#16, a1) +c.lw s0, (#32, a1) +c.lw s0, (#64, a1) +c.lw s0, (#124, a1) +c.lw s0, (#0, a2) +c.lw s0, (#4, a2) +c.lw s0, (#8, a2) +c.lw s0, (#16, a2) +c.lw s0, (#32, a2) +c.lw s0, (#64, a2) +c.lw s0, (#124, a2) +c.lw s0, (#0, a3) +c.lw s0, (#4, a3) +c.lw s0, (#8, a3) +c.lw s0, (#16, a3) +c.lw s0, (#32, a3) +c.lw s0, (#64, a3) +c.lw s0, (#124, a3) +c.lw s0, (#0, a4) +c.lw s0, (#4, a4) +c.lw s0, (#8, a4) +c.lw s0, (#16, a4) +c.lw s0, (#32, a4) +c.lw s0, (#64, a4) +c.lw s0, (#124, a4) +c.lw s0, (#0, a5) +c.lw s0, (#4, a5) +c.lw s0, (#8, a5) +c.lw s0, (#16, a5) +c.lw s0, (#32, a5) +c.lw s0, (#64, a5) +c.lw s0, (#124, a5) +c.lw s1, (#0, s0) +c.lw s1, (#4, s0) +c.lw s1, (#8, s0) +c.lw s1, (#16, s0) +c.lw s1, (#32, s0) +c.lw s1, (#64, s0) +c.lw s1, (#124, s0) +c.lw s1, (#0, s1) +c.lw s1, (#4, s1) +c.lw s1, (#8, s1) +c.lw s1, (#16, s1) +c.lw s1, (#32, s1) +c.lw s1, (#64, s1) +c.lw s1, (#124, s1) +c.lw s1, (#0, a0) +c.lw s1, (#4, a0) +c.lw s1, (#8, a0) +c.lw s1, (#16, a0) +c.lw s1, (#32, a0) +c.lw s1, (#64, a0) +c.lw s1, (#124, a0) +c.lw s1, (#0, a1) +c.lw s1, (#4, a1) +c.lw s1, (#8, a1) +c.lw s1, (#16, a1) +c.lw s1, (#32, a1) +c.lw s1, (#64, a1) +c.lw s1, (#124, a1) +c.lw s1, (#0, a2) +c.lw s1, (#4, a2) +c.lw s1, (#8, a2) +c.lw s1, (#16, a2) +c.lw s1, (#32, a2) +c.lw s1, (#64, a2) +c.lw s1, (#124, a2) +c.lw s1, (#0, a3) +c.lw s1, (#4, a3) +c.lw s1, (#8, a3) +c.lw s1, (#16, a3) +c.lw s1, (#32, a3) +c.lw s1, (#64, a3) +c.lw s1, (#124, a3) +c.lw s1, (#0, a4) +c.lw s1, (#4, a4) +c.lw s1, (#8, a4) +c.lw s1, (#16, a4) +c.lw s1, (#32, a4) +c.lw s1, (#64, a4) +c.lw s1, (#124, a4) +c.lw s1, (#0, a5) +c.lw s1, (#4, a5) +c.lw s1, (#8, a5) +c.lw s1, (#16, a5) +c.lw s1, (#32, a5) +c.lw s1, (#64, a5) +c.lw s1, (#124, a5) +c.lw a0, (#0, s0) +c.lw a0, (#4, s0) +c.lw a0, (#8, s0) +c.lw a0, (#16, s0) +c.lw a0, (#32, s0) +c.lw a0, (#64, s0) +c.lw a0, (#124, s0) +c.lw a0, (#0, s1) +c.lw a0, (#4, s1) +c.lw a0, (#8, s1) +c.lw a0, (#16, s1) +c.lw a0, (#32, s1) +c.lw a0, (#64, s1) +c.lw a0, (#124, s1) +c.lw a0, (#0, a0) +c.lw a0, (#4, a0) +c.lw a0, (#8, a0) +c.lw a0, (#16, a0) +c.lw a0, (#32, a0) +c.lw a0, (#64, a0) +c.lw a0, (#124, a0) +c.lw a0, (#0, a1) +c.lw a0, (#4, a1) +c.lw a0, (#8, a1) +c.lw a0, (#16, a1) +c.lw a0, (#32, a1) +c.lw a0, (#64, a1) +c.lw a0, (#124, a1) +c.lw a0, (#0, a2) +c.lw a0, (#4, a2) +c.lw a0, (#8, a2) +c.lw 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+c.lw a1, (#64, a1) +c.lw a1, (#124, a1) +c.lw a1, (#0, a2) +c.lw a1, (#4, a2) +c.lw a1, (#8, a2) +c.lw a1, (#16, a2) +c.lw a1, (#32, a2) +c.lw a1, (#64, a2) +c.lw a1, (#124, a2) +c.lw a1, (#0, a3) +c.lw a1, (#4, a3) +c.lw a1, (#8, a3) +c.lw a1, (#16, a3) +c.lw a1, (#32, a3) +c.lw a1, (#64, a3) +c.lw a1, (#124, a3) +c.lw a1, (#0, a4) +c.lw a1, (#4, a4) +c.lw a1, (#8, a4) +c.lw a1, (#16, a4) +c.lw a1, (#32, a4) +c.lw a1, (#64, a4) +c.lw a1, (#124, a4) +c.lw a1, (#0, a5) +c.lw a1, (#4, a5) +c.lw a1, (#8, a5) +c.lw a1, (#16, a5) +c.lw a1, (#32, a5) +c.lw a1, (#64, a5) +c.lw a1, (#124, a5) +c.lw a2, (#0, s0) +c.lw a2, (#4, s0) +c.lw a2, (#8, s0) +c.lw a2, (#16, s0) +c.lw a2, (#32, s0) +c.lw a2, (#64, s0) +c.lw a2, (#124, s0) +c.lw a2, (#0, s1) +c.lw a2, (#4, s1) +c.lw a2, (#8, s1) +c.lw a2, (#16, s1) +c.lw a2, (#32, s1) +c.lw a2, (#64, s1) +c.lw a2, (#124, s1) +c.lw a2, (#0, a0) +c.lw a2, (#4, a0) +c.lw a2, (#8, a0) +c.lw a2, (#16, a0) +c.lw a2, (#32, a0) +c.lw a2, (#64, a0) +c.lw a2, (#124, a0) +c.lw a2, (#0, a1) +c.lw a2, (#4, a1) +c.lw a2, (#8, a1) +c.lw a2, (#16, a1) +c.lw a2, (#32, a1) +c.lw a2, (#64, a1) +c.lw a2, (#124, a1) +c.lw a2, (#0, a2) +c.lw a2, (#4, a2) +c.lw a2, (#8, a2) +c.lw a2, (#16, a2) +c.lw a2, (#32, a2) +c.lw a2, (#64, a2) +c.lw a2, (#124, a2) +c.lw a2, (#0, a3) +c.lw a2, (#4, a3) +c.lw a2, (#8, a3) +c.lw a2, (#16, a3) +c.lw a2, (#32, a3) +c.lw a2, (#64, a3) +c.lw a2, (#124, a3) +c.lw a2, (#0, a4) +c.lw a2, (#4, a4) +c.lw a2, (#8, a4) +c.lw a2, (#16, a4) +c.lw a2, (#32, a4) +c.lw a2, (#64, a4) +c.lw a2, (#124, a4) +c.lw a2, (#0, a5) +c.lw a2, (#4, a5) +c.lw a2, (#8, a5) +c.lw a2, (#16, a5) +c.lw a2, (#32, a5) +c.lw a2, (#64, a5) +c.lw a2, (#124, a5) +c.lw a3, (#0, s0) +c.lw a3, (#4, s0) +c.lw a3, (#8, s0) +c.lw a3, (#16, s0) +c.lw a3, (#32, s0) +c.lw a3, (#64, s0) +c.lw a3, (#124, s0) +c.lw a3, (#0, s1) +c.lw a3, (#4, s1) +c.lw a3, (#8, s1) +c.lw a3, (#16, s1) +c.lw a3, (#32, s1) +c.lw a3, (#64, s1) +c.lw a3, (#124, s1) +c.lw a3, (#0, a0) +c.lw a3, (#4, a0) +c.lw a3, (#8, a0) +c.lw a3, (#16, a0) +c.lw a3, (#32, a0) +c.lw a3, (#64, a0) +c.lw a3, (#124, a0) +c.lw a3, (#0, a1) +c.lw a3, (#4, a1) +c.lw a3, (#8, a1) +c.lw a3, (#16, a1) +c.lw a3, (#32, a1) +c.lw a3, (#64, a1) +c.lw a3, (#124, a1) +c.lw a3, (#0, a2) +c.lw a3, (#4, a2) +c.lw a3, (#8, a2) +c.lw a3, (#16, a2) +c.lw a3, (#32, a2) +c.lw a3, (#64, a2) +c.lw a3, (#124, a2) +c.lw a3, (#0, a3) +c.lw a3, (#4, a3) +c.lw a3, (#8, a3) +c.lw a3, (#16, a3) +c.lw a3, (#32, a3) +c.lw a3, (#64, a3) +c.lw a3, (#124, a3) +c.lw a3, (#0, a4) +c.lw a3, (#4, a4) +c.lw a3, (#8, a4) +c.lw a3, (#16, a4) +c.lw a3, (#32, a4) +c.lw a3, (#64, a4) +c.lw a3, (#124, a4) +c.lw a3, (#0, a5) +c.lw a3, (#4, a5) +c.lw a3, (#8, a5) +c.lw a3, (#16, a5) +c.lw a3, (#32, a5) +c.lw a3, (#64, a5) +c.lw a3, (#124, a5) +c.lw a4, (#0, s0) +c.lw a4, (#4, s0) +c.lw a4, (#8, s0) +c.lw a4, (#16, s0) +c.lw a4, (#32, s0) +c.lw a4, (#64, s0) +c.lw a4, (#124, s0) +c.lw a4, (#0, s1) +c.lw a4, (#4, s1) +c.lw a4, (#8, s1) +c.lw a4, (#16, s1) +c.lw a4, (#32, s1) +c.lw a4, (#64, s1) +c.lw a4, (#124, s1) +c.lw a4, (#0, a0) +c.lw a4, (#4, a0) +c.lw a4, (#8, a0) +c.lw a4, (#16, a0) +c.lw a4, (#32, a0) +c.lw a4, (#64, a0) +c.lw a4, (#124, a0) +c.lw a4, (#0, a1) +c.lw a4, (#4, a1) +c.lw a4, (#8, a1) +c.lw a4, (#16, a1) +c.lw a4, (#32, a1) +c.lw a4, (#64, a1) +c.lw a4, (#124, a1) +c.lw a4, (#0, a2) +c.lw a4, (#4, a2) +c.lw a4, (#8, a2) +c.lw a4, (#16, a2) +c.lw a4, (#32, a2) +c.lw a4, (#64, a2) +c.lw a4, (#124, a2) +c.lw a4, (#0, a3) +c.lw a4, (#4, a3) +c.lw a4, (#8, a3) +c.lw a4, (#16, a3) +c.lw a4, (#32, a3) +c.lw a4, (#64, a3) +c.lw a4, (#124, a3) +c.lw a4, (#0, a4) +c.lw a4, (#4, a4) +c.lw a4, (#8, a4) +c.lw a4, (#16, a4) +c.lw a4, (#32, a4) +c.lw a4, (#64, a4) +c.lw a4, (#124, a4) +c.lw a4, (#0, a5) +c.lw a4, (#4, a5) +c.lw a4, (#8, a5) +c.lw a4, (#16, a5) +c.lw a4, (#32, a5) +c.lw a4, (#64, a5) +c.lw a4, (#124, a5) +c.lw a5, (#0, s0) +c.lw a5, (#4, s0) +c.lw a5, (#8, s0) +c.lw a5, (#16, s0) +c.lw a5, (#32, s0) +c.lw a5, (#64, s0) +c.lw a5, (#124, s0) +c.lw a5, (#0, s1) +c.lw a5, (#4, s1) +c.lw a5, (#8, s1) +c.lw a5, (#16, s1) +c.lw a5, (#32, s1) +c.lw a5, (#64, s1) +c.lw a5, (#124, s1) +c.lw a5, (#0, a0) +c.lw a5, (#4, a0) +c.lw a5, (#8, a0) +c.lw a5, (#16, a0) +c.lw a5, (#32, a0) +c.lw a5, (#64, a0) +c.lw a5, (#124, a0) +c.lw a5, (#0, a1) +c.lw a5, (#4, a1) +c.lw a5, (#8, a1) +c.lw a5, (#16, a1) +c.lw a5, (#32, a1) +c.lw a5, (#64, a1) +c.lw a5, (#124, a1) +c.lw a5, (#0, a2) +c.lw a5, (#4, a2) +c.lw a5, (#8, a2) +c.lw a5, (#16, a2) +c.lw a5, (#32, a2) +c.lw a5, (#64, a2) +c.lw a5, (#124, a2) +c.lw a5, (#0, a3) +c.lw a5, (#4, a3) +c.lw a5, (#8, a3) +c.lw a5, (#16, a3) +c.lw a5, (#32, a3) +c.lw a5, (#64, a3) +c.lw a5, (#124, a3) +c.lw a5, (#0, a4) +c.lw a5, (#4, a4) +c.lw a5, (#8, a4) +c.lw a5, (#16, a4) +c.lw a5, (#32, a4) +c.lw a5, (#64, a4) +c.lw a5, (#124, a4) +c.lw a5, (#0, a5) +c.lw a5, (#4, a5) +c.lw a5, (#8, a5) +c.lw a5, (#16, a5) +c.lw a5, (#32, a5) +c.lw a5, (#64, a5) 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b/tests/riscv/c-extension/c.lw.disasm @@ -0,0 +1,448 @@ +c.lw s0, (#0, s0) +c.lw s0, (#4, s0) +c.lw s0, (#8, s0) +c.lw s0, (#16, s0) +c.lw s0, (#32, s0) +c.lw s0, (#64, s0) +c.lw s0, (#124, s0) +c.lw s0, (#0, s1) +c.lw s0, (#4, s1) +c.lw s0, (#8, s1) +c.lw s0, (#16, s1) +c.lw s0, (#32, s1) +c.lw s0, (#64, s1) +c.lw s0, (#124, s1) +c.lw s0, (#0, a0) +c.lw s0, (#4, a0) +c.lw s0, (#8, a0) +c.lw s0, (#16, a0) +c.lw s0, (#32, a0) +c.lw s0, (#64, a0) +c.lw s0, (#124, a0) +c.lw s0, (#0, a1) +c.lw s0, (#4, a1) +c.lw s0, (#8, a1) +c.lw s0, (#16, a1) +c.lw s0, (#32, a1) +c.lw s0, (#64, a1) +c.lw s0, (#124, a1) +c.lw s0, (#0, a2) +c.lw s0, (#4, a2) +c.lw s0, (#8, a2) +c.lw s0, (#16, a2) +c.lw s0, (#32, a2) +c.lw s0, (#64, a2) +c.lw s0, (#124, a2) +c.lw s0, (#0, a3) +c.lw s0, (#4, a3) +c.lw s0, (#8, a3) +c.lw s0, (#16, a3) +c.lw s0, (#32, a3) +c.lw s0, (#64, a3) +c.lw s0, (#124, a3) +c.lw s0, (#0, a4) +c.lw s0, (#4, a4) +c.lw s0, (#8, a4) +c.lw s0, (#16, a4) +c.lw s0, (#32, a4) +c.lw s0, (#64, a4) +c.lw s0, (#124, a4) +c.lw s0, (#0, a5) +c.lw s0, (#4, a5) +c.lw s0, (#8, a5) +c.lw s0, (#16, a5) +c.lw s0, (#32, a5) +c.lw s0, (#64, a5) +c.lw s0, (#124, a5) +c.lw s1, (#0, s0) +c.lw s1, (#4, s0) +c.lw s1, (#8, s0) +c.lw s1, (#16, s0) +c.lw s1, (#32, s0) +c.lw s1, (#64, s0) +c.lw s1, (#124, s0) +c.lw s1, (#0, s1) +c.lw s1, (#4, s1) +c.lw s1, (#8, s1) +c.lw s1, (#16, s1) +c.lw s1, (#32, s1) +c.lw s1, (#64, s1) +c.lw s1, (#124, s1) +c.lw s1, (#0, a0) +c.lw s1, (#4, a0) +c.lw s1, (#8, a0) +c.lw s1, (#16, a0) +c.lw s1, (#32, a0) +c.lw s1, (#64, a0) +c.lw s1, (#124, a0) +c.lw s1, (#0, a1) +c.lw s1, (#4, a1) +c.lw s1, (#8, a1) +c.lw s1, (#16, a1) +c.lw s1, (#32, a1) +c.lw s1, (#64, a1) +c.lw s1, (#124, a1) +c.lw s1, (#0, a2) +c.lw s1, (#4, a2) +c.lw s1, (#8, a2) +c.lw s1, (#16, a2) +c.lw s1, (#32, a2) +c.lw s1, (#64, a2) +c.lw s1, (#124, a2) +c.lw s1, (#0, a3) +c.lw s1, (#4, a3) +c.lw s1, (#8, a3) +c.lw s1, (#16, a3) +c.lw s1, (#32, a3) +c.lw s1, (#64, a3) +c.lw s1, (#124, a3) +c.lw s1, (#0, a4) +c.lw s1, (#4, a4) +c.lw s1, (#8, a4) +c.lw s1, (#16, a4) +c.lw s1, (#32, a4) +c.lw s1, (#64, a4) +c.lw s1, (#124, a4) +c.lw s1, (#0, a5) +c.lw s1, (#4, a5) +c.lw s1, (#8, a5) +c.lw s1, (#16, a5) +c.lw s1, (#32, a5) +c.lw s1, (#64, a5) +c.lw s1, (#124, a5) +c.lw a0, (#0, s0) +c.lw a0, (#4, s0) +c.lw a0, (#8, s0) +c.lw a0, (#16, s0) +c.lw a0, (#32, s0) +c.lw a0, (#64, s0) +c.lw a0, (#124, s0) +c.lw a0, (#0, s1) +c.lw a0, (#4, s1) +c.lw a0, (#8, s1) +c.lw a0, (#16, s1) +c.lw a0, (#32, s1) +c.lw a0, (#64, s1) +c.lw a0, (#124, s1) +c.lw a0, (#0, a0) +c.lw a0, (#4, a0) +c.lw a0, (#8, a0) +c.lw a0, (#16, a0) +c.lw a0, (#32, a0) +c.lw a0, (#64, a0) +c.lw a0, (#124, a0) +c.lw a0, (#0, a1) +c.lw a0, (#4, a1) +c.lw a0, (#8, a1) +c.lw a0, (#16, a1) +c.lw a0, (#32, a1) +c.lw a0, (#64, a1) +c.lw a0, (#124, a1) +c.lw a0, (#0, a2) +c.lw a0, (#4, a2) +c.lw a0, (#8, a2) +c.lw a0, (#16, a2) +c.lw a0, (#32, a2) +c.lw a0, (#64, a2) +c.lw a0, (#124, a2) +c.lw a0, (#0, a3) +c.lw a0, (#4, a3) +c.lw a0, (#8, a3) +c.lw a0, (#16, a3) +c.lw a0, (#32, a3) +c.lw a0, (#64, a3) +c.lw a0, (#124, a3) +c.lw a0, (#0, a4) +c.lw a0, (#4, a4) +c.lw a0, (#8, a4) +c.lw a0, (#16, a4) +c.lw a0, (#32, a4) +c.lw a0, (#64, a4) +c.lw a0, (#124, a4) +c.lw a0, (#0, a5) +c.lw a0, (#4, a5) +c.lw a0, (#8, a5) +c.lw a0, (#16, a5) +c.lw a0, (#32, a5) +c.lw a0, (#64, a5) +c.lw a0, (#124, a5) +c.lw a1, (#0, s0) +c.lw a1, (#4, s0) +c.lw a1, (#8, s0) +c.lw a1, (#16, s0) +c.lw a1, (#32, s0) +c.lw a1, (#64, s0) +c.lw a1, (#124, s0) +c.lw a1, (#0, s1) +c.lw a1, (#4, s1) +c.lw a1, (#8, s1) +c.lw a1, (#16, s1) +c.lw a1, (#32, s1) +c.lw a1, (#64, s1) +c.lw a1, (#124, s1) +c.lw a1, (#0, a0) +c.lw a1, (#4, a0) +c.lw a1, (#8, a0) +c.lw a1, (#16, a0) +c.lw a1, (#32, a0) +c.lw a1, (#64, a0) +c.lw a1, (#124, a0) +c.lw a1, (#0, a1) +c.lw a1, (#4, a1) +c.lw a1, (#8, a1) +c.lw a1, (#16, a1) +c.lw a1, (#32, a1) +c.lw a1, (#64, a1) +c.lw a1, (#124, a1) +c.lw a1, (#0, a2) +c.lw a1, (#4, a2) +c.lw a1, (#8, a2) +c.lw a1, (#16, a2) +c.lw a1, (#32, a2) +c.lw a1, (#64, a2) +c.lw a1, (#124, a2) +c.lw a1, (#0, a3) +c.lw a1, (#4, a3) +c.lw a1, (#8, a3) +c.lw a1, (#16, a3) +c.lw a1, (#32, a3) +c.lw a1, (#64, a3) +c.lw a1, (#124, a3) +c.lw a1, (#0, a4) +c.lw a1, (#4, a4) +c.lw a1, (#8, a4) +c.lw a1, (#16, a4) +c.lw a1, (#32, a4) +c.lw a1, (#64, a4) +c.lw a1, (#124, a4) +c.lw a1, (#0, a5) +c.lw a1, (#4, a5) +c.lw a1, (#8, a5) +c.lw a1, (#16, a5) +c.lw a1, (#32, a5) +c.lw a1, (#64, a5) +c.lw a1, (#124, a5) +c.lw a2, (#0, s0) +c.lw a2, (#4, s0) +c.lw a2, (#8, s0) +c.lw a2, (#16, s0) +c.lw a2, (#32, s0) +c.lw a2, (#64, s0) +c.lw a2, (#124, s0) +c.lw a2, (#0, s1) +c.lw a2, (#4, s1) +c.lw a2, (#8, s1) +c.lw a2, (#16, s1) +c.lw a2, (#32, s1) +c.lw a2, (#64, s1) +c.lw a2, (#124, s1) +c.lw a2, (#0, a0) +c.lw a2, (#4, a0) +c.lw a2, (#8, a0) +c.lw a2, (#16, a0) +c.lw a2, (#32, a0) +c.lw a2, (#64, a0) +c.lw a2, (#124, a0) +c.lw a2, (#0, a1) +c.lw a2, (#4, a1) +c.lw a2, (#8, a1) +c.lw a2, (#16, a1) +c.lw a2, (#32, a1) +c.lw a2, (#64, a1) +c.lw a2, (#124, a1) +c.lw a2, (#0, a2) +c.lw a2, (#4, a2) +c.lw a2, (#8, a2) +c.lw a2, (#16, a2) +c.lw a2, (#32, a2) +c.lw a2, (#64, a2) +c.lw a2, (#124, a2) +c.lw a2, (#0, a3) +c.lw a2, (#4, a3) +c.lw a2, (#8, a3) +c.lw a2, (#16, a3) +c.lw a2, (#32, a3) +c.lw a2, (#64, a3) +c.lw a2, (#124, a3) +c.lw a2, (#0, a4) +c.lw a2, (#4, a4) +c.lw a2, (#8, a4) +c.lw a2, (#16, a4) +c.lw a2, (#32, a4) +c.lw a2, (#64, a4) +c.lw a2, (#124, a4) +c.lw a2, (#0, a5) +c.lw a2, (#4, a5) +c.lw a2, (#8, a5) +c.lw a2, (#16, a5) +c.lw a2, (#32, a5) +c.lw a2, (#64, a5) +c.lw a2, (#124, a5) +c.lw a3, (#0, s0) +c.lw a3, (#4, s0) +c.lw a3, (#8, s0) +c.lw a3, (#16, s0) +c.lw a3, (#32, s0) +c.lw a3, (#64, s0) +c.lw a3, (#124, s0) +c.lw a3, (#0, s1) +c.lw a3, (#4, s1) +c.lw a3, (#8, s1) +c.lw a3, (#16, s1) +c.lw a3, (#32, s1) +c.lw a3, (#64, s1) +c.lw a3, (#124, s1) +c.lw a3, (#0, a0) +c.lw a3, (#4, a0) +c.lw a3, (#8, a0) +c.lw a3, (#16, a0) +c.lw a3, (#32, a0) +c.lw a3, (#64, a0) +c.lw a3, (#124, a0) +c.lw a3, (#0, a1) +c.lw a3, (#4, a1) +c.lw a3, (#8, a1) +c.lw a3, (#16, a1) +c.lw a3, (#32, a1) +c.lw a3, (#64, a1) +c.lw a3, (#124, a1) +c.lw a3, (#0, a2) +c.lw a3, (#4, a2) +c.lw a3, (#8, a2) +c.lw a3, (#16, a2) +c.lw a3, (#32, a2) +c.lw a3, (#64, a2) +c.lw a3, (#124, a2) +c.lw a3, (#0, a3) +c.lw a3, (#4, a3) +c.lw a3, (#8, a3) +c.lw a3, (#16, a3) +c.lw a3, (#32, a3) +c.lw a3, (#64, a3) +c.lw a3, (#124, a3) +c.lw a3, (#0, a4) +c.lw a3, (#4, a4) +c.lw a3, (#8, a4) +c.lw a3, (#16, a4) +c.lw a3, (#32, a4) +c.lw a3, (#64, a4) +c.lw a3, (#124, a4) +c.lw a3, (#0, a5) +c.lw a3, (#4, a5) +c.lw a3, (#8, a5) +c.lw a3, (#16, a5) +c.lw a3, (#32, a5) +c.lw a3, (#64, a5) +c.lw a3, (#124, a5) +c.lw a4, (#0, s0) +c.lw a4, (#4, s0) +c.lw a4, (#8, s0) +c.lw a4, (#16, s0) +c.lw a4, (#32, s0) +c.lw a4, (#64, s0) +c.lw a4, (#124, s0) +c.lw a4, (#0, s1) +c.lw a4, (#4, s1) +c.lw a4, (#8, s1) +c.lw a4, (#16, s1) +c.lw a4, (#32, s1) +c.lw a4, (#64, s1) +c.lw a4, (#124, s1) +c.lw a4, (#0, a0) +c.lw a4, (#4, a0) +c.lw a4, (#8, a0) +c.lw a4, (#16, a0) +c.lw a4, (#32, a0) +c.lw a4, (#64, a0) +c.lw a4, (#124, a0) +c.lw a4, (#0, a1) +c.lw a4, (#4, a1) +c.lw a4, (#8, a1) +c.lw a4, (#16, a1) +c.lw a4, (#32, a1) +c.lw a4, (#64, a1) +c.lw a4, (#124, a1) +c.lw a4, (#0, a2) +c.lw a4, (#4, a2) +c.lw a4, (#8, a2) +c.lw a4, (#16, a2) +c.lw a4, (#32, a2) +c.lw a4, (#64, a2) +c.lw a4, (#124, a2) +c.lw a4, (#0, a3) +c.lw a4, (#4, a3) +c.lw a4, (#8, a3) +c.lw a4, (#16, a3) +c.lw a4, (#32, a3) +c.lw a4, (#64, a3) +c.lw a4, (#124, a3) +c.lw a4, (#0, a4) +c.lw a4, (#4, a4) +c.lw a4, (#8, a4) +c.lw a4, (#16, a4) +c.lw a4, (#32, a4) +c.lw a4, (#64, a4) +c.lw a4, (#124, a4) +c.lw a4, (#0, a5) +c.lw a4, (#4, a5) +c.lw a4, (#8, a5) +c.lw a4, (#16, a5) +c.lw a4, (#32, a5) +c.lw a4, (#64, a5) +c.lw a4, (#124, a5) +c.lw a5, (#0, s0) +c.lw a5, (#4, s0) +c.lw a5, (#8, s0) +c.lw a5, (#16, s0) +c.lw a5, (#32, s0) +c.lw a5, (#64, s0) +c.lw a5, (#124, s0) +c.lw a5, (#0, s1) +c.lw a5, (#4, s1) +c.lw a5, (#8, s1) +c.lw a5, (#16, s1) +c.lw a5, (#32, s1) +c.lw a5, (#64, s1) +c.lw a5, (#124, s1) +c.lw a5, (#0, a0) +c.lw a5, (#4, a0) +c.lw a5, (#8, a0) +c.lw a5, (#16, a0) +c.lw a5, (#32, a0) +c.lw a5, (#64, a0) +c.lw a5, (#124, a0) +c.lw a5, (#0, a1) +c.lw a5, (#4, a1) +c.lw a5, (#8, a1) +c.lw a5, (#16, a1) +c.lw a5, (#32, a1) +c.lw a5, (#64, a1) +c.lw a5, (#124, a1) +c.lw a5, (#0, a2) +c.lw a5, (#4, a2) +c.lw a5, (#8, a2) +c.lw a5, (#16, a2) +c.lw a5, (#32, a2) +c.lw a5, (#64, a2) +c.lw a5, (#124, a2) +c.lw a5, (#0, a3) +c.lw a5, (#4, a3) +c.lw a5, (#8, a3) +c.lw a5, (#16, a3) +c.lw a5, (#32, a3) +c.lw a5, (#64, a3) +c.lw a5, (#124, a3) +c.lw a5, (#0, a4) +c.lw a5, (#4, a4) +c.lw a5, (#8, a4) +c.lw a5, (#16, a4) +c.lw a5, (#32, a4) +c.lw a5, (#64, a4) +c.lw a5, (#124, a4) +c.lw a5, (#0, a5) +c.lw a5, (#4, a5) +c.lw a5, (#8, a5) +c.lw a5, (#16, a5) +c.lw a5, (#32, a5) +c.lw a5, (#64, a5) +c.lw a5, (#124, a5) diff --git a/tests/riscv/c-extension/c.lwsp.asm b/tests/riscv/c-extension/c.lwsp.asm new file mode 100644 index 0000000..864ec89 --- /dev/null +++ b/tests/riscv/c-extension/c.lwsp.asm @@ -0,0 +1,60 @@ +.lang riscv32 +.org 0x0 + +c.lwsp ra, #0 +c.lwsp ra, #4 +c.lwsp ra, #8 +c.lwsp ra, #16 +c.lwsp ra, #32 +c.lwsp ra, #64 +c.lwsp ra, #128 +c.lwsp ra, #252 +c.lwsp t0, #0 +c.lwsp t0, #4 +c.lwsp t0, #8 +c.lwsp t0, #16 +c.lwsp t0, #32 +c.lwsp t0, #64 +c.lwsp t0, #128 +c.lwsp t0, #252 +c.lwsp a0, #0 +c.lwsp a0, #4 +c.lwsp a0, #8 +c.lwsp a0, #16 +c.lwsp a0, #32 +c.lwsp a0, #64 +c.lwsp a0, #128 +c.lwsp a0, #252 +c.lwsp a5, #0 +c.lwsp a5, #4 +c.lwsp a5, #8 +c.lwsp a5, #16 +c.lwsp a5, #32 +c.lwsp a5, #64 +c.lwsp a5, #128 +c.lwsp a5, #252 +c.lwsp s4, #0 +c.lwsp s4, #4 +c.lwsp s4, #8 +c.lwsp s4, #16 +c.lwsp s4, #32 +c.lwsp s4, #64 +c.lwsp s4, #128 +c.lwsp s4, #252 +c.lwsp s9, #0 +c.lwsp s9, #4 +c.lwsp s9, #8 +c.lwsp s9, #16 +c.lwsp s9, #32 +c.lwsp s9, #64 +c.lwsp s9, #128 +c.lwsp s9, #252 +c.lwsp t6, #0 +c.lwsp t6, #4 +c.lwsp t6, #8 +c.lwsp t6, #16 +c.lwsp t6, #32 +c.lwsp t6, #64 +c.lwsp t6, #128 +c.lwsp t6, #252 + diff --git a/tests/riscv/c-extension/c.lwsp.bin b/tests/riscv/c-extension/c.lwsp.bin new file mode 100644 index 0000000..d2485ef --- /dev/null +++ b/tests/riscv/c-extension/c.lwsp.bin @@ -0,0 +1,3 @@ +@@@@P@@PBBBBRBBREE"EBEUE +E~UGGGGWGGWJJ"JBJZJ +J~ZLLLL\LL\OOOO_OO_ \ No newline at end of file diff --git a/tests/riscv/c-extension/c.lwsp.disasm b/tests/riscv/c-extension/c.lwsp.disasm new file mode 100644 index 0000000..b5d8309 --- /dev/null +++ b/tests/riscv/c-extension/c.lwsp.disasm @@ -0,0 +1,56 @@ +c.lwsp ra, #0 +c.lwsp ra, #4 +c.lwsp ra, #8 +c.lwsp ra, #16 +c.lwsp ra, #32 +c.lwsp ra, #64 +c.lwsp ra, #128 +c.lwsp ra, #252 +c.lwsp t0, #0 +c.lwsp t0, #4 +c.lwsp t0, #8 +c.lwsp t0, #16 +c.lwsp t0, #32 +c.lwsp t0, #64 +c.lwsp t0, #128 +c.lwsp t0, #252 +c.lwsp a0, #0 +c.lwsp a0, #4 +c.lwsp a0, #8 +c.lwsp a0, #16 +c.lwsp a0, #32 +c.lwsp a0, #64 +c.lwsp a0, #128 +c.lwsp a0, #252 +c.lwsp a5, #0 +c.lwsp a5, #4 +c.lwsp a5, #8 +c.lwsp a5, #16 +c.lwsp a5, #32 +c.lwsp a5, #64 +c.lwsp a5, #128 +c.lwsp a5, #252 +c.lwsp s4, #0 +c.lwsp s4, #4 +c.lwsp s4, #8 +c.lwsp s4, #16 +c.lwsp s4, #32 +c.lwsp s4, #64 +c.lwsp s4, #128 +c.lwsp s4, #252 +c.lwsp s9, #0 +c.lwsp s9, #4 +c.lwsp s9, #8 +c.lwsp s9, #16 +c.lwsp s9, #32 +c.lwsp s9, #64 +c.lwsp s9, #128 +c.lwsp s9, #252 +c.lwsp t6, #0 +c.lwsp t6, #4 +c.lwsp t6, #8 +c.lwsp t6, #16 +c.lwsp t6, #32 +c.lwsp t6, #64 +c.lwsp t6, #128 +c.lwsp t6, #252 diff --git a/tests/riscv/c-extension/c.mv.asm b/tests/riscv/c-extension/c.mv.asm new file mode 100644 index 0000000..5afdbb3 --- /dev/null +++ b/tests/riscv/c-extension/c.mv.asm @@ -0,0 +1,53 @@ +.lang riscv32 +.org 0x0 + +c.mv ra, ra +c.mv ra, t0 +c.mv ra, a0 +c.mv ra, a5 +c.mv ra, s4 +c.mv ra, s9 +c.mv ra, t6 +c.mv t0, ra +c.mv t0, t0 +c.mv t0, a0 +c.mv t0, a5 +c.mv t0, s4 +c.mv t0, s9 +c.mv t0, t6 +c.mv a0, ra +c.mv a0, t0 +c.mv a0, a0 +c.mv a0, a5 +c.mv a0, s4 +c.mv a0, s9 +c.mv a0, t6 +c.mv a5, ra +c.mv a5, t0 +c.mv a5, a0 +c.mv a5, a5 +c.mv a5, s4 +c.mv a5, s9 +c.mv a5, t6 +c.mv s4, ra +c.mv s4, t0 +c.mv s4, a0 +c.mv s4, a5 +c.mv s4, s4 +c.mv s4, s9 +c.mv s4, t6 +c.mv s9, ra +c.mv s9, t0 +c.mv s9, a0 +c.mv s9, a5 +c.mv s9, s4 +c.mv s9, s9 +c.mv s9, t6 +c.mv t6, ra +c.mv t6, t0 +c.mv t6, a0 +c.mv t6, a5 +c.mv t6, s4 +c.mv t6, s9 +c.mv t6, t6 + diff --git a/tests/riscv/c-extension/c.mv.bin b/tests/riscv/c-extension/c.mv.bin new file mode 100644 index 0000000..16f9f17 --- /dev/null +++ b/tests/riscv/c-extension/c.mv.bin @@ -0,0 +1 @@ +Ҁ҂*>Rf~҇*>Rf~Ҍҏ \ No newline at end of file diff --git a/tests/riscv/c-extension/c.mv.disasm b/tests/riscv/c-extension/c.mv.disasm new file mode 100644 index 0000000..4c60d4a --- /dev/null +++ b/tests/riscv/c-extension/c.mv.disasm @@ -0,0 +1,49 @@ +c.mv ra, ra +c.mv ra, t0 +c.mv ra, a0 +c.mv ra, a5 +c.mv ra, s4 +c.mv ra, s9 +c.mv ra, t6 +c.mv t0, ra +c.mv t0, t0 +c.mv t0, a0 +c.mv t0, a5 +c.mv t0, s4 +c.mv t0, s9 +c.mv t0, t6 +c.mv a0, ra +c.mv a0, t0 +c.mv a0, a0 +c.mv a0, a5 +c.mv a0, s4 +c.mv a0, s9 +c.mv a0, t6 +c.mv a5, ra +c.mv a5, t0 +c.mv a5, a0 +c.mv a5, a5 +c.mv a5, s4 +c.mv a5, s9 +c.mv a5, t6 +c.mv s4, ra +c.mv s4, t0 +c.mv s4, a0 +c.mv s4, a5 +c.mv s4, s4 +c.mv s4, s9 +c.mv s4, t6 +c.mv s9, ra +c.mv s9, t0 +c.mv s9, a0 +c.mv s9, a5 +c.mv s9, s4 +c.mv s9, s9 +c.mv s9, t6 +c.mv t6, ra +c.mv t6, t0 +c.mv t6, a0 +c.mv t6, a5 +c.mv t6, s4 +c.mv t6, s9 +c.mv t6, t6 diff --git a/tests/riscv/c-extension/c.nop.asm b/tests/riscv/c-extension/c.nop.asm new file mode 100644 index 0000000..e23624f --- /dev/null +++ b/tests/riscv/c-extension/c.nop.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.nop + diff --git a/tests/riscv/c-extension/c.nop.bin b/tests/riscv/c-extension/c.nop.bin new file mode 100644 index 0000000000000000000000000000000000000000..35a038769b15c0935bb3cd038f5cc1de7579f128 GIT binary patch literal 2 JcmZQ%0000400IC2 literal 0 HcmV?d00001 diff --git a/tests/riscv/c-extension/c.nop.disasm b/tests/riscv/c-extension/c.nop.disasm new file mode 100644 index 0000000..b324ca4 --- /dev/null +++ b/tests/riscv/c-extension/c.nop.disasm @@ -0,0 +1 @@ +c.nop diff --git a/tests/riscv/c-extension/c.or.asm b/tests/riscv/c-extension/c.or.asm new file mode 100644 index 0000000..f7f5bfd --- /dev/null +++ b/tests/riscv/c-extension/c.or.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +c.or s0, s0 +c.or s0, s1 +c.or s0, a0 +c.or s0, a1 +c.or s0, a2 +c.or s0, a3 +c.or s0, a4 +c.or s0, a5 +c.or s1, s0 +c.or s1, s1 +c.or s1, a0 +c.or s1, a1 +c.or s1, a2 +c.or s1, a3 +c.or s1, a4 +c.or s1, a5 +c.or a0, s0 +c.or a0, s1 +c.or a0, a0 +c.or a0, a1 +c.or a0, a2 +c.or a0, a3 +c.or a0, a4 +c.or a0, a5 +c.or a1, s0 +c.or a1, s1 +c.or a1, a0 +c.or a1, a1 +c.or a1, a2 +c.or a1, a3 +c.or a1, a4 +c.or a1, a5 +c.or a2, s0 +c.or a2, s1 +c.or a2, a0 +c.or a2, a1 +c.or a2, a2 +c.or a2, a3 +c.or a2, a4 +c.or a2, a5 +c.or a3, s0 +c.or a3, s1 +c.or a3, a0 +c.or a3, a1 +c.or a3, a2 +c.or a3, a3 +c.or a3, a4 +c.or a3, a5 +c.or a4, s0 +c.or a4, s1 +c.or a4, a0 +c.or a4, a1 +c.or a4, a2 +c.or a4, a3 +c.or a4, a4 +c.or a4, a5 +c.or a5, s0 +c.or a5, s1 +c.or a5, a0 +c.or a5, a1 +c.or a5, a2 +c.or a5, a3 +c.or a5, a4 +c.or a5, a5 + diff --git a/tests/riscv/c-extension/c.or.bin b/tests/riscv/c-extension/c.or.bin new file mode 100644 index 0000000..dbad590 --- /dev/null +++ b/tests/riscv/c-extension/c.or.bin @@ -0,0 +1 @@ +AEIMQUY]ŌɌ͌ьՌٌ݌AEIMQUY]ōɍ͍эՍٍݍAEIMQUY]ŎɎ͎юՎَݎAEIMQUY]ŏɏ͏яՏُݏ \ No newline at end of file diff --git a/tests/riscv/c-extension/c.or.disasm b/tests/riscv/c-extension/c.or.disasm new file mode 100644 index 0000000..3617c4d --- /dev/null +++ b/tests/riscv/c-extension/c.or.disasm @@ -0,0 +1,64 @@ +c.or s0, s0 +c.or s0, s1 +c.or s0, a0 +c.or s0, a1 +c.or s0, a2 +c.or s0, a3 +c.or s0, a4 +c.or s0, a5 +c.or s1, s0 +c.or s1, s1 +c.or s1, a0 +c.or s1, a1 +c.or s1, a2 +c.or s1, a3 +c.or s1, a4 +c.or s1, a5 +c.or a0, s0 +c.or a0, s1 +c.or a0, a0 +c.or a0, a1 +c.or a0, a2 +c.or a0, a3 +c.or a0, a4 +c.or a0, a5 +c.or a1, s0 +c.or a1, s1 +c.or a1, a0 +c.or a1, a1 +c.or a1, a2 +c.or a1, a3 +c.or a1, a4 +c.or a1, a5 +c.or a2, s0 +c.or a2, s1 +c.or a2, a0 +c.or a2, a1 +c.or a2, a2 +c.or a2, a3 +c.or a2, a4 +c.or a2, a5 +c.or a3, s0 +c.or a3, s1 +c.or a3, a0 +c.or a3, a1 +c.or a3, a2 +c.or a3, a3 +c.or a3, a4 +c.or a3, a5 +c.or a4, s0 +c.or a4, s1 +c.or a4, a0 +c.or a4, a1 +c.or a4, a2 +c.or a4, a3 +c.or a4, a4 +c.or a4, a5 +c.or a5, s0 +c.or a5, s1 +c.or a5, a0 +c.or a5, a1 +c.or a5, a2 +c.or a5, a3 +c.or a5, a4 +c.or a5, a5 diff --git a/tests/riscv/c-extension/c.slli.asm b/tests/riscv/c-extension/c.slli.asm new file mode 100644 index 0000000..f2977c1 --- /dev/null +++ b/tests/riscv/c-extension/c.slli.asm @@ -0,0 +1,53 @@ +.lang riscv32 +.org 0x0 + +c.slli ra, #0 +c.slli ra, #1 +c.slli ra, #2 +c.slli ra, #4 +c.slli ra, #8 +c.slli ra, #16 +c.slli ra, #31 +c.slli t0, #0 +c.slli t0, #1 +c.slli t0, #2 +c.slli t0, #4 +c.slli t0, #8 +c.slli t0, #16 +c.slli t0, #31 +c.slli a0, #0 +c.slli a0, #1 +c.slli a0, #2 +c.slli a0, #4 +c.slli a0, #8 +c.slli a0, #16 +c.slli a0, #31 +c.slli a5, #0 +c.slli a5, #1 +c.slli a5, #2 +c.slli a5, #4 +c.slli a5, #8 +c.slli a5, #16 +c.slli a5, #31 +c.slli s4, #0 +c.slli s4, #1 +c.slli s4, #2 +c.slli s4, #4 +c.slli s4, #8 +c.slli s4, #16 +c.slli s4, #31 +c.slli s9, #0 +c.slli s9, #1 +c.slli s9, #2 +c.slli s9, #4 +c.slli s9, #8 +c.slli s9, #16 +c.slli s9, #31 +c.slli t6, #0 +c.slli t6, #1 +c.slli t6, #2 +c.slli t6, #4 +c.slli t6, #8 +c.slli t6, #16 +c.slli t6, #31 + diff --git a/tests/riscv/c-extension/c.slli.bin b/tests/riscv/c-extension/c.slli.bin new file mode 100644 index 0000000000000000000000000000000000000000..2be5974eddc0ddeec420a7d71844abc2d9551402 GIT binary patch literal 98 zcmV~$u?fIH2mnA4j39!L5q^{(EQN)Ir6V|sgGufj0ul-u1{NFx6AK#$7m*$kdg;)m ikDP;(i<^g+Q63R_<;ay!Ttib!TSr&j!qUpx#@2q{BN`9@ literal 0 HcmV?d00001 diff --git a/tests/riscv/c-extension/c.slli.disasm b/tests/riscv/c-extension/c.slli.disasm new file mode 100644 index 0000000..e84cff2 --- /dev/null +++ b/tests/riscv/c-extension/c.slli.disasm @@ -0,0 +1,49 @@ +c.slli ra, #0 +c.slli ra, #1 +c.slli ra, #2 +c.slli ra, #4 +c.slli ra, #8 +c.slli ra, #16 +c.slli ra, #31 +c.slli t0, #0 +c.slli t0, #1 +c.slli t0, #2 +c.slli t0, #4 +c.slli t0, #8 +c.slli t0, #16 +c.slli t0, #31 +c.slli a0, #0 +c.slli a0, #1 +c.slli a0, #2 +c.slli a0, #4 +c.slli a0, #8 +c.slli a0, #16 +c.slli a0, #31 +c.slli a5, #0 +c.slli a5, #1 +c.slli a5, #2 +c.slli a5, #4 +c.slli a5, #8 +c.slli a5, #16 +c.slli a5, #31 +c.slli s4, #0 +c.slli s4, #1 +c.slli s4, #2 +c.slli s4, #4 +c.slli s4, #8 +c.slli s4, #16 +c.slli s4, #31 +c.slli s9, #0 +c.slli s9, #1 +c.slli s9, #2 +c.slli s9, #4 +c.slli s9, #8 +c.slli s9, #16 +c.slli s9, #31 +c.slli t6, #0 +c.slli t6, #1 +c.slli t6, #2 +c.slli t6, #4 +c.slli t6, #8 +c.slli t6, #16 +c.slli t6, #31 diff --git a/tests/riscv/c-extension/c.srai.asm b/tests/riscv/c-extension/c.srai.asm new file mode 100644 index 0000000..3e57784 --- /dev/null +++ b/tests/riscv/c-extension/c.srai.asm @@ -0,0 +1,60 @@ +.lang riscv32 +.org 0x0 + +c.srai s0, #0 +c.srai s0, #1 +c.srai s0, #2 +c.srai s0, #4 +c.srai s0, #8 +c.srai s0, #16 +c.srai s0, #31 +c.srai s1, #0 +c.srai s1, #1 +c.srai s1, #2 +c.srai s1, #4 +c.srai s1, #8 +c.srai s1, #16 +c.srai s1, #31 +c.srai a0, #0 +c.srai a0, #1 +c.srai a0, #2 +c.srai a0, #4 +c.srai a0, #8 +c.srai a0, #16 +c.srai a0, #31 +c.srai a1, #0 +c.srai a1, #1 +c.srai a1, #2 +c.srai a1, #4 +c.srai a1, #8 +c.srai a1, #16 +c.srai a1, #31 +c.srai a2, #0 +c.srai a2, #1 +c.srai a2, #2 +c.srai a2, #4 +c.srai a2, #8 +c.srai a2, #16 +c.srai a2, #31 +c.srai a3, #0 +c.srai a3, #1 +c.srai a3, #2 +c.srai a3, #4 +c.srai a3, #8 +c.srai a3, #16 +c.srai a3, #31 +c.srai a4, #0 +c.srai a4, #1 +c.srai a4, #2 +c.srai a4, #4 +c.srai a4, #8 +c.srai a4, #16 +c.srai a4, #31 +c.srai a5, #0 +c.srai a5, #1 +c.srai a5, #2 +c.srai a5, #4 +c.srai a5, #8 +c.srai a5, #16 +c.srai a5, #31 + diff --git a/tests/riscv/c-extension/c.srai.bin b/tests/riscv/c-extension/c.srai.bin new file mode 100644 index 0000000..05d4348 --- /dev/null +++ b/tests/riscv/c-extension/c.srai.bin @@ -0,0 +1 @@ + !A} !A} !A} !A} \ No newline at end of file diff --git a/tests/riscv/c-extension/c.srai.disasm b/tests/riscv/c-extension/c.srai.disasm new file mode 100644 index 0000000..56f203e --- /dev/null +++ b/tests/riscv/c-extension/c.srai.disasm @@ -0,0 +1,56 @@ +c.srai s0, #0 +c.srai s0, #1 +c.srai s0, #2 +c.srai s0, #4 +c.srai s0, #8 +c.srai s0, #16 +c.srai s0, #31 +c.srai s1, #0 +c.srai s1, #1 +c.srai s1, #2 +c.srai s1, #4 +c.srai s1, #8 +c.srai s1, #16 +c.srai s1, #31 +c.srai a0, #0 +c.srai a0, #1 +c.srai a0, #2 +c.srai a0, #4 +c.srai a0, #8 +c.srai a0, #16 +c.srai a0, #31 +c.srai a1, #0 +c.srai a1, #1 +c.srai a1, #2 +c.srai a1, #4 +c.srai a1, #8 +c.srai a1, #16 +c.srai a1, #31 +c.srai a2, #0 +c.srai a2, #1 +c.srai a2, #2 +c.srai a2, #4 +c.srai a2, #8 +c.srai a2, #16 +c.srai a2, #31 +c.srai a3, #0 +c.srai a3, #1 +c.srai a3, #2 +c.srai a3, #4 +c.srai a3, #8 +c.srai a3, #16 +c.srai a3, #31 +c.srai a4, #0 +c.srai a4, #1 +c.srai a4, #2 +c.srai a4, #4 +c.srai a4, #8 +c.srai a4, #16 +c.srai a4, #31 +c.srai a5, #0 +c.srai a5, #1 +c.srai a5, #2 +c.srai a5, #4 +c.srai a5, #8 +c.srai a5, #16 +c.srai a5, #31 diff --git a/tests/riscv/c-extension/c.srli.asm b/tests/riscv/c-extension/c.srli.asm new file mode 100644 index 0000000..3e78403 --- /dev/null +++ b/tests/riscv/c-extension/c.srli.asm @@ -0,0 +1,60 @@ +.lang riscv32 +.org 0x0 + +c.srli s0, #0 +c.srli s0, #1 +c.srli s0, #2 +c.srli s0, #4 +c.srli s0, #8 +c.srli s0, #16 +c.srli s0, #31 +c.srli s1, #0 +c.srli s1, #1 +c.srli s1, #2 +c.srli s1, #4 +c.srli s1, #8 +c.srli s1, #16 +c.srli s1, #31 +c.srli a0, #0 +c.srli a0, #1 +c.srli a0, #2 +c.srli a0, #4 +c.srli a0, #8 +c.srli a0, #16 +c.srli a0, #31 +c.srli a1, #0 +c.srli a1, #1 +c.srli a1, #2 +c.srli a1, #4 +c.srli a1, #8 +c.srli a1, #16 +c.srli a1, #31 +c.srli a2, #0 +c.srli a2, #1 +c.srli a2, #2 +c.srli a2, #4 +c.srli a2, #8 +c.srli a2, #16 +c.srli a2, #31 +c.srli a3, #0 +c.srli a3, #1 +c.srli a3, #2 +c.srli a3, #4 +c.srli a3, #8 +c.srli a3, #16 +c.srli a3, #31 +c.srli a4, #0 +c.srli a4, #1 +c.srli a4, #2 +c.srli a4, #4 +c.srli a4, #8 +c.srli a4, #16 +c.srli a4, #31 +c.srli a5, #0 +c.srli a5, #1 +c.srli a5, #2 +c.srli a5, #4 +c.srli a5, #8 +c.srli a5, #16 +c.srli a5, #31 + diff --git a/tests/riscv/c-extension/c.srli.bin b/tests/riscv/c-extension/c.srli.bin new file mode 100644 index 0000000..abadab6 --- /dev/null +++ b/tests/riscv/c-extension/c.srli.bin @@ -0,0 +1 @@ + !A} !A} !A} !A} \ No newline at end of file diff --git a/tests/riscv/c-extension/c.srli.disasm b/tests/riscv/c-extension/c.srli.disasm new file mode 100644 index 0000000..5b51d09 --- /dev/null +++ b/tests/riscv/c-extension/c.srli.disasm @@ -0,0 +1,56 @@ +c.srli s0, #0 +c.srli s0, #1 +c.srli s0, #2 +c.srli s0, #4 +c.srli s0, #8 +c.srli s0, #16 +c.srli s0, #31 +c.srli s1, #0 +c.srli s1, #1 +c.srli s1, #2 +c.srli s1, #4 +c.srli s1, #8 +c.srli s1, #16 +c.srli s1, #31 +c.srli a0, #0 +c.srli a0, #1 +c.srli a0, #2 +c.srli a0, #4 +c.srli a0, #8 +c.srli a0, #16 +c.srli a0, #31 +c.srli a1, #0 +c.srli a1, #1 +c.srli a1, #2 +c.srli a1, #4 +c.srli a1, #8 +c.srli a1, #16 +c.srli a1, #31 +c.srli a2, #0 +c.srli a2, #1 +c.srli a2, #2 +c.srli a2, #4 +c.srli a2, #8 +c.srli a2, #16 +c.srli a2, #31 +c.srli a3, #0 +c.srli a3, #1 +c.srli a3, #2 +c.srli a3, #4 +c.srli a3, #8 +c.srli a3, #16 +c.srli a3, #31 +c.srli a4, #0 +c.srli a4, #1 +c.srli a4, #2 +c.srli a4, #4 +c.srli a4, #8 +c.srli a4, #16 +c.srli a4, #31 +c.srli a5, #0 +c.srli a5, #1 +c.srli a5, #2 +c.srli a5, #4 +c.srli a5, #8 +c.srli a5, #16 +c.srli a5, #31 diff --git a/tests/riscv/c-extension/c.sub.asm b/tests/riscv/c-extension/c.sub.asm new file mode 100644 index 0000000..e533705 --- /dev/null +++ b/tests/riscv/c-extension/c.sub.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +c.sub s0, s0 +c.sub s0, s1 +c.sub s0, a0 +c.sub s0, a1 +c.sub s0, a2 +c.sub s0, a3 +c.sub s0, a4 +c.sub s0, a5 +c.sub s1, s0 +c.sub s1, s1 +c.sub s1, a0 +c.sub s1, a1 +c.sub s1, a2 +c.sub s1, a3 +c.sub s1, a4 +c.sub s1, a5 +c.sub a0, s0 +c.sub a0, s1 +c.sub a0, a0 +c.sub a0, a1 +c.sub a0, a2 +c.sub a0, a3 +c.sub a0, a4 +c.sub a0, a5 +c.sub a1, s0 +c.sub a1, s1 +c.sub a1, a0 +c.sub a1, a1 +c.sub a1, a2 +c.sub a1, a3 +c.sub a1, a4 +c.sub a1, a5 +c.sub a2, s0 +c.sub a2, s1 +c.sub a2, a0 +c.sub a2, a1 +c.sub a2, a2 +c.sub a2, a3 +c.sub a2, a4 +c.sub a2, a5 +c.sub a3, s0 +c.sub a3, s1 +c.sub a3, a0 +c.sub a3, a1 +c.sub a3, a2 +c.sub a3, a3 +c.sub a3, a4 +c.sub a3, a5 +c.sub a4, s0 +c.sub a4, s1 +c.sub a4, a0 +c.sub a4, a1 +c.sub a4, a2 +c.sub a4, a3 +c.sub a4, a4 +c.sub a4, a5 +c.sub a5, s0 +c.sub a5, s1 +c.sub a5, a0 +c.sub a5, a1 +c.sub a5, a2 +c.sub a5, a3 +c.sub a5, a4 +c.sub a5, a5 + diff --git a/tests/riscv/c-extension/c.sub.bin b/tests/riscv/c-extension/c.sub.bin new file mode 100644 index 0000000..b0e11c6 --- /dev/null +++ b/tests/riscv/c-extension/c.sub.bin @@ -0,0 +1 @@ +     \ No newline at end of file diff --git a/tests/riscv/c-extension/c.sub.disasm b/tests/riscv/c-extension/c.sub.disasm new file mode 100644 index 0000000..229be33 --- /dev/null +++ b/tests/riscv/c-extension/c.sub.disasm @@ -0,0 +1,64 @@ +c.sub s0, s0 +c.sub s0, s1 +c.sub s0, a0 +c.sub s0, a1 +c.sub s0, a2 +c.sub s0, a3 +c.sub s0, a4 +c.sub s0, a5 +c.sub s1, s0 +c.sub s1, s1 +c.sub s1, a0 +c.sub s1, a1 +c.sub s1, a2 +c.sub s1, a3 +c.sub s1, a4 +c.sub s1, a5 +c.sub a0, s0 +c.sub a0, s1 +c.sub a0, a0 +c.sub a0, a1 +c.sub a0, a2 +c.sub a0, a3 +c.sub a0, a4 +c.sub a0, a5 +c.sub a1, s0 +c.sub a1, s1 +c.sub a1, a0 +c.sub a1, a1 +c.sub a1, a2 +c.sub a1, a3 +c.sub a1, a4 +c.sub a1, a5 +c.sub a2, s0 +c.sub a2, s1 +c.sub a2, a0 +c.sub a2, a1 +c.sub a2, a2 +c.sub a2, a3 +c.sub a2, a4 +c.sub a2, a5 +c.sub a3, s0 +c.sub a3, s1 +c.sub a3, a0 +c.sub a3, a1 +c.sub a3, a2 +c.sub a3, a3 +c.sub a3, a4 +c.sub a3, a5 +c.sub a4, s0 +c.sub a4, s1 +c.sub a4, a0 +c.sub a4, a1 +c.sub a4, a2 +c.sub a4, a3 +c.sub a4, a4 +c.sub a4, a5 +c.sub a5, s0 +c.sub a5, s1 +c.sub a5, a0 +c.sub a5, a1 +c.sub a5, a2 +c.sub a5, a3 +c.sub a5, a4 +c.sub a5, a5 diff --git a/tests/riscv/c-extension/c.sw.asm b/tests/riscv/c-extension/c.sw.asm new file mode 100644 index 0000000..958b94d --- /dev/null +++ b/tests/riscv/c-extension/c.sw.asm @@ -0,0 +1,452 @@ +.lang riscv32 +.org 0x0 + +c.sw s0, (#0, s0) +c.sw s0, (#4, s0) +c.sw s0, (#8, s0) +c.sw s0, (#16, s0) +c.sw s0, (#32, s0) +c.sw s0, (#64, s0) +c.sw s0, (#124, s0) +c.sw s0, (#0, s1) +c.sw s0, (#4, s1) +c.sw s0, (#8, s1) +c.sw s0, (#16, s1) +c.sw s0, (#32, s1) +c.sw s0, (#64, s1) +c.sw s0, (#124, s1) +c.sw s0, (#0, a0) +c.sw s0, (#4, a0) +c.sw s0, (#8, a0) +c.sw s0, (#16, a0) +c.sw s0, (#32, a0) +c.sw s0, (#64, a0) +c.sw s0, (#124, a0) +c.sw s0, (#0, a1) +c.sw s0, (#4, a1) +c.sw s0, (#8, a1) +c.sw s0, (#16, a1) +c.sw s0, (#32, a1) +c.sw s0, (#64, a1) +c.sw s0, (#124, a1) +c.sw s0, (#0, a2) +c.sw s0, (#4, a2) +c.sw s0, (#8, a2) +c.sw s0, (#16, a2) +c.sw s0, (#32, a2) +c.sw s0, (#64, a2) +c.sw s0, (#124, a2) +c.sw s0, (#0, a3) +c.sw s0, (#4, a3) +c.sw s0, (#8, a3) +c.sw s0, (#16, a3) +c.sw s0, (#32, a3) +c.sw s0, (#64, a3) +c.sw s0, (#124, a3) +c.sw s0, (#0, a4) +c.sw s0, (#4, a4) +c.sw s0, (#8, a4) +c.sw s0, (#16, a4) +c.sw s0, (#32, a4) +c.sw s0, (#64, a4) +c.sw s0, (#124, a4) +c.sw s0, (#0, a5) +c.sw s0, (#4, a5) +c.sw s0, (#8, a5) +c.sw s0, (#16, a5) +c.sw s0, (#32, a5) +c.sw s0, (#64, a5) +c.sw s0, (#124, a5) +c.sw s1, (#0, s0) +c.sw s1, (#4, s0) +c.sw s1, (#8, s0) +c.sw s1, (#16, s0) +c.sw s1, (#32, s0) +c.sw s1, (#64, s0) +c.sw s1, (#124, s0) +c.sw s1, (#0, s1) +c.sw s1, (#4, s1) +c.sw s1, (#8, s1) +c.sw s1, (#16, s1) +c.sw s1, (#32, s1) +c.sw s1, (#64, s1) +c.sw s1, (#124, s1) +c.sw s1, (#0, a0) +c.sw s1, (#4, a0) +c.sw s1, (#8, a0) +c.sw s1, (#16, a0) +c.sw s1, (#32, a0) +c.sw s1, (#64, a0) +c.sw s1, (#124, a0) +c.sw s1, (#0, a1) +c.sw s1, (#4, a1) +c.sw s1, (#8, a1) +c.sw s1, (#16, a1) +c.sw s1, (#32, a1) +c.sw s1, (#64, a1) +c.sw s1, (#124, a1) +c.sw s1, (#0, a2) +c.sw s1, (#4, a2) +c.sw s1, (#8, a2) +c.sw s1, (#16, a2) +c.sw s1, (#32, a2) +c.sw s1, (#64, a2) +c.sw s1, (#124, a2) +c.sw s1, (#0, a3) +c.sw s1, (#4, a3) +c.sw s1, (#8, a3) +c.sw s1, (#16, a3) +c.sw s1, (#32, a3) +c.sw s1, (#64, a3) +c.sw s1, (#124, a3) +c.sw s1, (#0, a4) +c.sw s1, (#4, a4) +c.sw s1, (#8, a4) +c.sw s1, (#16, a4) +c.sw s1, (#32, a4) +c.sw s1, (#64, a4) +c.sw s1, (#124, a4) +c.sw s1, (#0, a5) +c.sw s1, (#4, a5) +c.sw s1, (#8, a5) +c.sw s1, (#16, a5) +c.sw s1, (#32, a5) +c.sw s1, (#64, a5) +c.sw s1, (#124, a5) +c.sw a0, (#0, s0) +c.sw a0, (#4, s0) +c.sw a0, (#8, s0) +c.sw a0, (#16, s0) +c.sw a0, (#32, s0) +c.sw a0, (#64, s0) +c.sw a0, (#124, s0) +c.sw a0, (#0, s1) +c.sw a0, (#4, s1) +c.sw a0, (#8, s1) +c.sw a0, (#16, s1) +c.sw a0, (#32, s1) +c.sw a0, (#64, s1) +c.sw a0, (#124, s1) +c.sw a0, (#0, a0) +c.sw a0, (#4, a0) +c.sw a0, (#8, a0) +c.sw a0, (#16, a0) +c.sw a0, (#32, a0) +c.sw a0, (#64, a0) +c.sw a0, (#124, a0) +c.sw a0, (#0, a1) +c.sw a0, (#4, a1) +c.sw a0, (#8, a1) +c.sw a0, (#16, a1) +c.sw a0, (#32, a1) +c.sw a0, (#64, a1) +c.sw a0, (#124, a1) +c.sw a0, (#0, a2) +c.sw a0, (#4, a2) +c.sw a0, (#8, a2) +c.sw a0, (#16, a2) +c.sw a0, (#32, a2) +c.sw a0, (#64, a2) +c.sw a0, (#124, a2) +c.sw a0, (#0, a3) +c.sw a0, (#4, a3) +c.sw a0, (#8, a3) +c.sw a0, (#16, a3) +c.sw a0, (#32, a3) +c.sw a0, (#64, a3) +c.sw a0, (#124, a3) +c.sw a0, (#0, a4) +c.sw a0, (#4, a4) +c.sw a0, (#8, a4) +c.sw a0, (#16, a4) +c.sw a0, (#32, a4) +c.sw a0, (#64, a4) +c.sw a0, (#124, a4) +c.sw a0, (#0, a5) +c.sw a0, (#4, a5) +c.sw a0, (#8, a5) +c.sw a0, (#16, a5) +c.sw a0, (#32, a5) +c.sw a0, (#64, a5) +c.sw a0, (#124, a5) +c.sw a1, (#0, s0) +c.sw a1, (#4, s0) +c.sw a1, (#8, s0) +c.sw a1, (#16, s0) +c.sw a1, (#32, s0) +c.sw a1, (#64, s0) +c.sw a1, (#124, s0) +c.sw a1, (#0, s1) +c.sw a1, (#4, s1) +c.sw a1, (#8, s1) +c.sw a1, (#16, s1) +c.sw a1, (#32, s1) +c.sw a1, (#64, s1) +c.sw a1, (#124, s1) +c.sw a1, (#0, a0) +c.sw a1, (#4, a0) +c.sw a1, (#8, a0) +c.sw a1, (#16, a0) +c.sw a1, (#32, a0) +c.sw a1, (#64, a0) +c.sw a1, (#124, a0) +c.sw a1, (#0, a1) +c.sw a1, (#4, a1) +c.sw a1, (#8, a1) +c.sw a1, (#16, a1) +c.sw a1, (#32, a1) +c.sw a1, (#64, a1) +c.sw a1, (#124, a1) +c.sw a1, (#0, a2) +c.sw a1, (#4, a2) +c.sw a1, (#8, a2) +c.sw a1, (#16, a2) +c.sw a1, (#32, a2) +c.sw a1, (#64, a2) +c.sw a1, (#124, a2) +c.sw a1, (#0, a3) +c.sw a1, (#4, a3) +c.sw a1, (#8, a3) +c.sw a1, (#16, a3) +c.sw a1, (#32, a3) +c.sw a1, (#64, a3) +c.sw a1, (#124, a3) +c.sw a1, (#0, a4) +c.sw a1, (#4, a4) +c.sw a1, (#8, a4) +c.sw a1, (#16, a4) +c.sw a1, (#32, a4) +c.sw a1, (#64, a4) +c.sw a1, (#124, a4) +c.sw a1, (#0, a5) +c.sw a1, (#4, a5) +c.sw a1, (#8, a5) +c.sw a1, (#16, a5) +c.sw a1, (#32, a5) +c.sw a1, (#64, a5) +c.sw a1, (#124, a5) +c.sw a2, (#0, s0) +c.sw a2, (#4, s0) +c.sw a2, (#8, s0) +c.sw a2, (#16, s0) +c.sw a2, (#32, s0) +c.sw a2, (#64, s0) +c.sw a2, (#124, s0) +c.sw a2, (#0, s1) +c.sw a2, (#4, s1) +c.sw a2, (#8, s1) +c.sw a2, (#16, s1) +c.sw a2, (#32, s1) +c.sw a2, (#64, s1) +c.sw a2, (#124, s1) +c.sw a2, (#0, a0) +c.sw a2, (#4, a0) +c.sw a2, (#8, a0) +c.sw a2, (#16, a0) +c.sw a2, (#32, a0) +c.sw a2, (#64, a0) +c.sw a2, (#124, a0) +c.sw a2, (#0, a1) +c.sw a2, (#4, a1) +c.sw a2, (#8, a1) +c.sw a2, (#16, a1) +c.sw a2, (#32, a1) +c.sw a2, (#64, a1) +c.sw a2, (#124, a1) +c.sw a2, (#0, a2) +c.sw a2, (#4, a2) +c.sw a2, (#8, a2) +c.sw a2, (#16, a2) +c.sw a2, (#32, a2) +c.sw a2, (#64, a2) +c.sw a2, (#124, a2) +c.sw a2, (#0, a3) +c.sw a2, (#4, a3) +c.sw a2, (#8, a3) +c.sw a2, (#16, a3) +c.sw a2, (#32, a3) +c.sw a2, (#64, a3) +c.sw a2, (#124, a3) +c.sw a2, (#0, a4) +c.sw a2, (#4, a4) +c.sw a2, (#8, a4) +c.sw a2, (#16, a4) +c.sw a2, (#32, a4) +c.sw a2, (#64, a4) +c.sw a2, (#124, a4) +c.sw a2, (#0, a5) +c.sw a2, (#4, a5) +c.sw a2, (#8, a5) +c.sw a2, (#16, a5) +c.sw a2, (#32, a5) +c.sw a2, (#64, a5) +c.sw a2, (#124, a5) +c.sw a3, (#0, s0) +c.sw a3, (#4, s0) +c.sw a3, (#8, s0) +c.sw a3, (#16, s0) +c.sw a3, (#32, s0) +c.sw a3, (#64, s0) +c.sw a3, (#124, s0) +c.sw a3, (#0, s1) +c.sw a3, (#4, s1) +c.sw a3, (#8, s1) +c.sw a3, (#16, s1) +c.sw a3, (#32, s1) +c.sw a3, (#64, s1) +c.sw a3, (#124, s1) +c.sw a3, (#0, a0) +c.sw a3, (#4, a0) +c.sw a3, (#8, a0) +c.sw a3, (#16, a0) +c.sw a3, (#32, a0) +c.sw a3, (#64, a0) +c.sw a3, (#124, a0) +c.sw a3, (#0, a1) +c.sw a3, (#4, a1) +c.sw a3, (#8, a1) +c.sw a3, (#16, a1) +c.sw a3, (#32, a1) +c.sw a3, (#64, a1) +c.sw a3, (#124, a1) +c.sw a3, (#0, a2) +c.sw a3, (#4, a2) +c.sw a3, (#8, a2) +c.sw a3, (#16, a2) +c.sw a3, (#32, a2) +c.sw a3, (#64, a2) +c.sw a3, (#124, a2) +c.sw a3, (#0, a3) +c.sw a3, (#4, a3) +c.sw a3, (#8, a3) +c.sw a3, (#16, a3) +c.sw a3, (#32, a3) +c.sw a3, (#64, a3) +c.sw a3, (#124, a3) +c.sw a3, (#0, a4) +c.sw a3, (#4, a4) +c.sw a3, (#8, a4) +c.sw a3, (#16, a4) +c.sw a3, (#32, a4) +c.sw a3, (#64, a4) +c.sw a3, (#124, a4) +c.sw a3, (#0, a5) +c.sw a3, (#4, a5) +c.sw a3, (#8, a5) +c.sw a3, (#16, a5) +c.sw a3, (#32, a5) +c.sw a3, (#64, a5) +c.sw a3, (#124, a5) +c.sw a4, (#0, s0) +c.sw a4, (#4, s0) +c.sw a4, (#8, s0) +c.sw a4, (#16, s0) +c.sw a4, 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(#0, a0) +c.sw a2, (#4, a0) +c.sw a2, (#8, a0) +c.sw a2, (#16, a0) +c.sw a2, (#32, a0) +c.sw a2, (#64, a0) +c.sw a2, (#124, a0) +c.sw a2, (#0, a1) +c.sw a2, (#4, a1) +c.sw a2, (#8, a1) +c.sw a2, (#16, a1) +c.sw a2, (#32, a1) +c.sw a2, (#64, a1) +c.sw a2, (#124, a1) +c.sw a2, (#0, a2) +c.sw a2, (#4, a2) +c.sw a2, (#8, a2) +c.sw a2, (#16, a2) +c.sw a2, (#32, a2) +c.sw a2, (#64, a2) +c.sw a2, (#124, a2) +c.sw a2, (#0, a3) +c.sw a2, (#4, a3) +c.sw a2, (#8, a3) +c.sw a2, (#16, a3) +c.sw a2, (#32, a3) +c.sw a2, (#64, a3) +c.sw a2, (#124, a3) +c.sw a2, (#0, a4) +c.sw a2, (#4, a4) +c.sw a2, (#8, a4) +c.sw a2, (#16, a4) +c.sw a2, (#32, a4) +c.sw a2, (#64, a4) +c.sw a2, (#124, a4) +c.sw a2, (#0, a5) +c.sw a2, (#4, a5) +c.sw a2, (#8, a5) +c.sw a2, (#16, a5) +c.sw a2, (#32, a5) +c.sw a2, (#64, a5) +c.sw a2, (#124, a5) +c.sw a3, (#0, s0) +c.sw a3, (#4, s0) +c.sw a3, (#8, s0) +c.sw a3, (#16, s0) +c.sw a3, (#32, s0) +c.sw a3, (#64, s0) +c.sw a3, (#124, s0) +c.sw a3, (#0, s1) +c.sw a3, (#4, s1) +c.sw a3, (#8, s1) +c.sw a3, (#16, s1) +c.sw a3, (#32, s1) +c.sw a3, (#64, s1) +c.sw a3, (#124, s1) +c.sw a3, (#0, a0) +c.sw a3, (#4, a0) +c.sw a3, (#8, a0) +c.sw a3, (#16, a0) +c.sw a3, (#32, a0) +c.sw a3, (#64, a0) +c.sw a3, (#124, a0) +c.sw a3, (#0, a1) +c.sw a3, (#4, a1) +c.sw a3, (#8, a1) +c.sw a3, (#16, a1) +c.sw a3, (#32, a1) +c.sw a3, (#64, a1) +c.sw a3, (#124, a1) +c.sw a3, (#0, a2) +c.sw a3, (#4, a2) +c.sw a3, (#8, a2) +c.sw a3, (#16, a2) +c.sw a3, (#32, a2) +c.sw a3, (#64, a2) +c.sw a3, (#124, a2) +c.sw a3, (#0, a3) +c.sw a3, (#4, a3) +c.sw a3, (#8, a3) +c.sw a3, (#16, a3) +c.sw a3, (#32, a3) +c.sw a3, (#64, a3) +c.sw a3, (#124, a3) +c.sw a3, (#0, a4) +c.sw a3, (#4, a4) +c.sw a3, (#8, a4) +c.sw a3, (#16, a4) +c.sw a3, (#32, a4) +c.sw a3, (#64, a4) +c.sw a3, (#124, a4) +c.sw a3, (#0, a5) +c.sw a3, (#4, a5) +c.sw a3, (#8, a5) +c.sw a3, (#16, a5) +c.sw a3, (#32, a5) +c.sw a3, (#64, a5) +c.sw a3, (#124, a5) +c.sw a4, (#0, s0) +c.sw a4, (#4, s0) +c.sw a4, (#8, s0) +c.sw a4, (#16, s0) +c.sw a4, (#32, s0) +c.sw a4, (#64, s0) +c.sw a4, (#124, s0) +c.sw a4, (#0, s1) +c.sw a4, (#4, s1) +c.sw a4, (#8, s1) +c.sw a4, (#16, s1) +c.sw a4, (#32, s1) +c.sw a4, (#64, s1) +c.sw a4, (#124, s1) +c.sw a4, (#0, a0) +c.sw a4, (#4, a0) +c.sw a4, (#8, a0) +c.sw a4, (#16, a0) +c.sw a4, (#32, a0) +c.sw a4, (#64, a0) +c.sw a4, (#124, a0) +c.sw a4, (#0, a1) +c.sw a4, (#4, a1) +c.sw a4, (#8, a1) +c.sw a4, (#16, a1) +c.sw a4, (#32, a1) +c.sw a4, (#64, a1) +c.sw a4, (#124, a1) +c.sw a4, (#0, a2) +c.sw a4, (#4, a2) +c.sw a4, (#8, a2) +c.sw a4, (#16, a2) +c.sw a4, (#32, a2) +c.sw a4, (#64, a2) +c.sw a4, (#124, a2) +c.sw a4, (#0, a3) +c.sw a4, (#4, a3) +c.sw a4, (#8, a3) +c.sw a4, (#16, a3) +c.sw a4, (#32, a3) +c.sw a4, (#64, a3) +c.sw a4, (#124, a3) +c.sw a4, (#0, a4) +c.sw a4, (#4, a4) +c.sw a4, (#8, a4) +c.sw a4, (#16, a4) +c.sw a4, (#32, a4) +c.sw a4, (#64, a4) +c.sw a4, (#124, a4) +c.sw a4, (#0, a5) +c.sw a4, (#4, a5) +c.sw a4, (#8, a5) +c.sw a4, (#16, a5) +c.sw a4, (#32, a5) +c.sw a4, (#64, a5) +c.sw a4, (#124, a5) +c.sw a5, (#0, s0) +c.sw a5, (#4, s0) +c.sw a5, (#8, s0) +c.sw a5, (#16, s0) +c.sw a5, (#32, s0) +c.sw a5, (#64, s0) +c.sw a5, (#124, s0) +c.sw a5, (#0, s1) +c.sw a5, (#4, s1) +c.sw a5, (#8, s1) +c.sw a5, (#16, s1) +c.sw a5, (#32, s1) +c.sw a5, (#64, s1) +c.sw a5, (#124, s1) +c.sw a5, (#0, a0) +c.sw a5, (#4, a0) +c.sw a5, (#8, a0) +c.sw a5, (#16, a0) +c.sw a5, (#32, a0) +c.sw a5, (#64, a0) +c.sw a5, (#124, a0) +c.sw a5, (#0, a1) +c.sw a5, (#4, a1) +c.sw a5, (#8, a1) +c.sw a5, (#16, a1) +c.sw a5, (#32, a1) +c.sw a5, (#64, a1) +c.sw a5, (#124, a1) +c.sw a5, (#0, a2) +c.sw a5, (#4, a2) +c.sw a5, (#8, a2) +c.sw a5, (#16, a2) +c.sw a5, (#32, a2) +c.sw a5, (#64, a2) +c.sw a5, (#124, a2) +c.sw a5, (#0, a3) +c.sw a5, (#4, a3) +c.sw a5, (#8, a3) +c.sw a5, (#16, a3) +c.sw a5, (#32, a3) +c.sw a5, (#64, a3) +c.sw a5, (#124, a3) +c.sw a5, (#0, a4) +c.sw a5, (#4, a4) +c.sw a5, (#8, a4) +c.sw a5, (#16, a4) +c.sw a5, (#32, a4) +c.sw a5, (#64, a4) +c.sw a5, (#124, a4) +c.sw a5, (#0, a5) +c.sw a5, (#4, a5) +c.sw a5, (#8, a5) +c.sw a5, (#16, a5) +c.sw a5, (#32, a5) +c.sw a5, (#64, a5) +c.sw a5, (#124, a5) diff --git a/tests/riscv/c-extension/c.swsp.asm b/tests/riscv/c-extension/c.swsp.asm new file mode 100644 index 0000000..3015f69 --- /dev/null +++ b/tests/riscv/c-extension/c.swsp.asm @@ -0,0 +1,60 @@ +.lang riscv32 +.org 0x0 + +c.swsp ra, #0 +c.swsp ra, #4 +c.swsp ra, #8 +c.swsp ra, #16 +c.swsp ra, #32 +c.swsp ra, #64 +c.swsp ra, #128 +c.swsp ra, #252 +c.swsp t0, #0 +c.swsp t0, #4 +c.swsp t0, #8 +c.swsp t0, #16 +c.swsp t0, #32 +c.swsp t0, #64 +c.swsp t0, #128 +c.swsp t0, #252 +c.swsp a0, #0 +c.swsp a0, #4 +c.swsp a0, #8 +c.swsp a0, #16 +c.swsp a0, #32 +c.swsp a0, #64 +c.swsp a0, #128 +c.swsp a0, #252 +c.swsp a5, #0 +c.swsp a5, #4 +c.swsp a5, #8 +c.swsp a5, #16 +c.swsp a5, #32 +c.swsp a5, #64 +c.swsp a5, #128 +c.swsp a5, #252 +c.swsp s4, #0 +c.swsp s4, #4 +c.swsp s4, #8 +c.swsp s4, #16 +c.swsp s4, #32 +c.swsp s4, #64 +c.swsp s4, #128 +c.swsp s4, #252 +c.swsp s9, #0 +c.swsp s9, #4 +c.swsp s9, #8 +c.swsp s9, #16 +c.swsp s9, #32 +c.swsp s9, #64 +c.swsp s9, #128 +c.swsp s9, #252 +c.swsp t6, #0 +c.swsp t6, #4 +c.swsp t6, #8 +c.swsp t6, #16 +c.swsp t6, #32 +c.swsp t6, #64 +c.swsp t6, #128 +c.swsp t6, #252 + diff --git a/tests/riscv/c-extension/c.swsp.bin b/tests/riscv/c-extension/c.swsp.bin new file mode 100644 index 0000000..a40eb56 --- /dev/null +++ b/tests/riscv/c-extension/c.swsp.bin @@ -0,0 +1 @@ +ІЖ******Ъ>>>>>>оRRRRRRffffff~~~~~~ \ No newline at end of file diff --git a/tests/riscv/c-extension/c.swsp.disasm b/tests/riscv/c-extension/c.swsp.disasm new file mode 100644 index 0000000..a7c6d09 --- /dev/null +++ b/tests/riscv/c-extension/c.swsp.disasm @@ -0,0 +1,56 @@ +c.swsp ra, #0 +c.swsp ra, #4 +c.swsp ra, #8 +c.swsp ra, #16 +c.swsp ra, #32 +c.swsp ra, #64 +c.swsp ra, #128 +c.swsp ra, #252 +c.swsp t0, #0 +c.swsp t0, #4 +c.swsp t0, #8 +c.swsp t0, #16 +c.swsp t0, #32 +c.swsp t0, #64 +c.swsp t0, #128 +c.swsp t0, #252 +c.swsp a0, #0 +c.swsp a0, #4 +c.swsp a0, #8 +c.swsp a0, #16 +c.swsp a0, #32 +c.swsp a0, #64 +c.swsp a0, #128 +c.swsp a0, #252 +c.swsp a5, #0 +c.swsp a5, #4 +c.swsp a5, #8 +c.swsp a5, #16 +c.swsp a5, #32 +c.swsp a5, #64 +c.swsp a5, #128 +c.swsp a5, #252 +c.swsp s4, #0 +c.swsp s4, #4 +c.swsp s4, #8 +c.swsp s4, #16 +c.swsp s4, #32 +c.swsp s4, #64 +c.swsp s4, #128 +c.swsp s4, #252 +c.swsp s9, #0 +c.swsp s9, #4 +c.swsp s9, #8 +c.swsp s9, #16 +c.swsp s9, #32 +c.swsp s9, #64 +c.swsp s9, #128 +c.swsp s9, #252 +c.swsp t6, #0 +c.swsp t6, #4 +c.swsp t6, #8 +c.swsp t6, #16 +c.swsp t6, #32 +c.swsp t6, #64 +c.swsp t6, #128 +c.swsp t6, #252 diff --git a/tests/riscv/c-extension/c.xor.asm b/tests/riscv/c-extension/c.xor.asm new file mode 100644 index 0000000..ad90b17 --- /dev/null +++ b/tests/riscv/c-extension/c.xor.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +c.xor s0, s0 +c.xor s0, s1 +c.xor s0, a0 +c.xor s0, a1 +c.xor s0, a2 +c.xor s0, a3 +c.xor s0, a4 +c.xor s0, a5 +c.xor s1, s0 +c.xor s1, s1 +c.xor s1, a0 +c.xor s1, a1 +c.xor s1, a2 +c.xor s1, a3 +c.xor s1, a4 +c.xor s1, a5 +c.xor a0, s0 +c.xor a0, s1 +c.xor a0, a0 +c.xor a0, a1 +c.xor a0, a2 +c.xor a0, a3 +c.xor a0, a4 +c.xor a0, a5 +c.xor a1, s0 +c.xor a1, s1 +c.xor a1, a0 +c.xor a1, a1 +c.xor a1, a2 +c.xor a1, a3 +c.xor a1, a4 +c.xor a1, a5 +c.xor a2, s0 +c.xor a2, s1 +c.xor a2, a0 +c.xor a2, a1 +c.xor a2, a2 +c.xor a2, a3 +c.xor a2, a4 +c.xor a2, a5 +c.xor a3, s0 +c.xor a3, s1 +c.xor a3, a0 +c.xor a3, a1 +c.xor a3, a2 +c.xor a3, a3 +c.xor a3, a4 +c.xor a3, a5 +c.xor a4, s0 +c.xor a4, s1 +c.xor a4, a0 +c.xor a4, a1 +c.xor a4, a2 +c.xor a4, a3 +c.xor a4, a4 +c.xor a4, a5 +c.xor a5, s0 +c.xor a5, s1 +c.xor a5, a0 +c.xor a5, a1 +c.xor a5, a2 +c.xor a5, a3 +c.xor a5, a4 +c.xor a5, a5 + diff --git a/tests/riscv/c-extension/c.xor.bin b/tests/riscv/c-extension/c.xor.bin new file mode 100644 index 0000000..f012091 --- /dev/null +++ b/tests/riscv/c-extension/c.xor.bin @@ -0,0 +1 @@ +!%)-159=!%)-159=!%)-159=!%)-159= \ No newline at end of file diff --git a/tests/riscv/c-extension/c.xor.disasm b/tests/riscv/c-extension/c.xor.disasm new file mode 100644 index 0000000..addc1e4 --- /dev/null +++ b/tests/riscv/c-extension/c.xor.disasm @@ -0,0 +1,64 @@ +c.xor s0, s0 +c.xor s0, s1 +c.xor s0, a0 +c.xor s0, a1 +c.xor s0, a2 +c.xor s0, a3 +c.xor s0, a4 +c.xor s0, a5 +c.xor s1, s0 +c.xor s1, s1 +c.xor s1, a0 +c.xor s1, a1 +c.xor s1, a2 +c.xor s1, a3 +c.xor s1, a4 +c.xor s1, a5 +c.xor a0, s0 +c.xor a0, s1 +c.xor a0, a0 +c.xor a0, a1 +c.xor a0, a2 +c.xor a0, a3 +c.xor a0, a4 +c.xor a0, a5 +c.xor a1, s0 +c.xor a1, s1 +c.xor a1, a0 +c.xor a1, a1 +c.xor a1, a2 +c.xor a1, a3 +c.xor a1, a4 +c.xor a1, a5 +c.xor a2, s0 +c.xor a2, s1 +c.xor a2, a0 +c.xor a2, a1 +c.xor a2, a2 +c.xor a2, a3 +c.xor a2, a4 +c.xor a2, a5 +c.xor a3, s0 +c.xor a3, s1 +c.xor a3, a0 +c.xor a3, a1 +c.xor a3, a2 +c.xor a3, a3 +c.xor a3, a4 +c.xor a3, a5 +c.xor a4, s0 +c.xor a4, s1 +c.xor a4, a0 +c.xor a4, a1 +c.xor a4, a2 +c.xor a4, a3 +c.xor a4, a4 +c.xor a4, a5 +c.xor a5, s0 +c.xor a5, s1 +c.xor a5, a0 +c.xor a5, a1 +c.xor a5, a2 +c.xor a5, a3 +c.xor a5, a4 +c.xor a5, a5 diff --git a/tests/riscv/c-extension/c_add.asm b/tests/riscv/c-extension/c_add.asm new file mode 100644 index 0000000..7956d0f --- /dev/null +++ b/tests/riscv/c-extension/c_add.asm @@ -0,0 +1,53 @@ +.lang riscv32 +.org 0x0 + +c.add ra, ra +c.add ra, t0 +c.add ra, a0 +c.add ra, a5 +c.add ra, s4 +c.add ra, s9 +c.add ra, t6 +c.add t0, ra +c.add t0, t0 +c.add t0, a0 +c.add t0, a5 +c.add t0, s4 +c.add t0, s9 +c.add t0, t6 +c.add a0, ra +c.add a0, t0 +c.add a0, a0 +c.add a0, a5 +c.add a0, s4 +c.add a0, s9 +c.add a0, t6 +c.add a5, ra +c.add a5, t0 +c.add a5, a0 +c.add a5, a5 +c.add a5, s4 +c.add a5, s9 +c.add a5, t6 +c.add s4, ra +c.add s4, t0 +c.add s4, a0 +c.add s4, a5 +c.add s4, s4 +c.add s4, s9 +c.add s4, t6 +c.add s9, ra +c.add s9, t0 +c.add s9, a0 +c.add s9, a5 +c.add s9, s4 +c.add s9, s9 +c.add s9, t6 +c.add t6, ra +c.add t6, t0 +c.add t6, a0 +c.add t6, a5 +c.add t6, s4 +c.add t6, s9 +c.add t6, t6 + diff --git a/tests/riscv/c-extension/c_add.bin b/tests/riscv/c-extension/c_add.bin new file mode 100644 index 0000000..857471a --- /dev/null +++ b/tests/riscv/c-extension/c_add.bin @@ -0,0 +1 @@ +ҐҒ*>Rf~җ*>Rf~Ҝҟ \ No newline at end of file diff --git a/tests/riscv/c-extension/c_add.disasm b/tests/riscv/c-extension/c_add.disasm new file mode 100644 index 0000000..7c0efb5 --- /dev/null +++ b/tests/riscv/c-extension/c_add.disasm @@ -0,0 +1,49 @@ +c.add ra, ra +c.add ra, t0 +c.add ra, a0 +c.add ra, a5 +c.add ra, s4 +c.add ra, s9 +c.add ra, t6 +c.add t0, ra +c.add t0, t0 +c.add t0, a0 +c.add t0, a5 +c.add t0, s4 +c.add t0, s9 +c.add t0, t6 +c.add a0, ra +c.add a0, t0 +c.add a0, a0 +c.add a0, a5 +c.add a0, s4 +c.add a0, s9 +c.add a0, t6 +c.add a5, ra +c.add a5, t0 +c.add a5, a0 +c.add a5, a5 +c.add a5, s4 +c.add a5, s9 +c.add a5, t6 +c.add s4, ra +c.add s4, t0 +c.add s4, a0 +c.add s4, a5 +c.add s4, s4 +c.add s4, s9 +c.add s4, t6 +c.add s9, ra +c.add s9, t0 +c.add s9, a0 +c.add s9, a5 +c.add s9, s4 +c.add s9, s9 +c.add s9, t6 +c.add t6, ra +c.add t6, t0 +c.add t6, a0 +c.add t6, a5 +c.add t6, s4 +c.add t6, s9 +c.add t6, t6 diff --git a/tests/riscv/c-extension/c_addi.asm b/tests/riscv/c-extension/c_addi.asm new file mode 100644 index 0000000..023d7ec --- /dev/null +++ b/tests/riscv/c-extension/c_addi.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.addi a0, #5 + diff --git a/tests/riscv/c-extension/c_addi.bin b/tests/riscv/c-extension/c_addi.bin new file mode 100644 index 0000000..42af1d5 --- /dev/null +++ b/tests/riscv/c-extension/c_addi.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_addi.disasm b/tests/riscv/c-extension/c_addi.disasm new file mode 100644 index 0000000..a76eef9 --- /dev/null +++ b/tests/riscv/c-extension/c_addi.disasm @@ -0,0 +1 @@ +c.addi a0, #5 diff --git a/tests/riscv/c-extension/c_addi16sp.asm b/tests/riscv/c-extension/c_addi16sp.asm new file mode 100644 index 0000000..a81bd9e --- /dev/null +++ b/tests/riscv/c-extension/c_addi16sp.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.addi16sp #-32 + diff --git a/tests/riscv/c-extension/c_addi16sp.bin b/tests/riscv/c-extension/c_addi16sp.bin new file mode 100644 index 0000000..478421b --- /dev/null +++ b/tests/riscv/c-extension/c_addi16sp.bin @@ -0,0 +1 @@ +=q \ No newline at end of file diff --git a/tests/riscv/c-extension/c_addi16sp.disasm b/tests/riscv/c-extension/c_addi16sp.disasm new file mode 100644 index 0000000..0942c5d --- /dev/null +++ b/tests/riscv/c-extension/c_addi16sp.disasm @@ -0,0 +1,10 @@ +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +Colliding matches: "c.addi16sp c.lui " +1: "c.addi16sp #-32" +2: "c.lui a0, #0x10000" +c.addi16sp #-32 diff --git a/tests/riscv/c-extension/c_addi4spn.asm b/tests/riscv/c-extension/c_addi4spn.asm new file mode 100644 index 0000000..828b22d --- /dev/null +++ b/tests/riscv/c-extension/c_addi4spn.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.addi4spn a0, #16 + diff --git a/tests/riscv/c-extension/c_addi4spn.bin b/tests/riscv/c-extension/c_addi4spn.bin new file mode 100644 index 0000000..9bf3397 --- /dev/null +++ b/tests/riscv/c-extension/c_addi4spn.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_addi4spn.disasm b/tests/riscv/c-extension/c_addi4spn.disasm new file mode 100644 index 0000000..f45b146 --- /dev/null +++ b/tests/riscv/c-extension/c_addi4spn.disasm @@ -0,0 +1 @@ +c.addi4spn a0, #16 diff --git a/tests/riscv/c-extension/c_and.asm b/tests/riscv/c-extension/c_and.asm new file mode 100644 index 0000000..8d73d05 --- /dev/null +++ b/tests/riscv/c-extension/c_and.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.and a0, a1 + diff --git a/tests/riscv/c-extension/c_and.bin b/tests/riscv/c-extension/c_and.bin new file mode 100644 index 0000000..bfc31db --- /dev/null +++ b/tests/riscv/c-extension/c_and.bin @@ -0,0 +1 @@ +m \ No newline at end of file diff --git a/tests/riscv/c-extension/c_and.disasm b/tests/riscv/c-extension/c_and.disasm new file mode 100644 index 0000000..6fdabef --- /dev/null +++ b/tests/riscv/c-extension/c_and.disasm @@ -0,0 +1 @@ +c.and a0, a1 diff --git a/tests/riscv/c-extension/c_andi.asm b/tests/riscv/c-extension/c_andi.asm new file mode 100644 index 0000000..83aacee --- /dev/null +++ b/tests/riscv/c-extension/c_andi.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.andi a0, #31 + diff --git a/tests/riscv/c-extension/c_andi.bin b/tests/riscv/c-extension/c_andi.bin new file mode 100644 index 0000000..fa267e3 --- /dev/null +++ b/tests/riscv/c-extension/c_andi.bin @@ -0,0 +1 @@ +} \ No newline at end of file diff --git a/tests/riscv/c-extension/c_andi.disasm b/tests/riscv/c-extension/c_andi.disasm new file mode 100644 index 0000000..2269ca9 --- /dev/null +++ b/tests/riscv/c-extension/c_andi.disasm @@ -0,0 +1 @@ +c.andi a0, #31 diff --git a/tests/riscv/c-extension/c_andi_edge_cases.asm b/tests/riscv/c-extension/c_andi_edge_cases.asm new file mode 100644 index 0000000..df17de1 --- /dev/null +++ b/tests/riscv/c-extension/c_andi_edge_cases.asm @@ -0,0 +1,50 @@ +.lang riscv32 +.org 0x0 + +; Edge cases for c.andi: signed 6-bit immediate range (-32 to 31) +; Testing minimum, maximum, zero, and various values + +; Minimum value +c.andi a0, #-32 + +; Maximum value +c.andi a1, #31 + +; Zero +c.andi a2, #0 + +; Negative edge cases +c.andi a3, #-1 +c.andi a4, #-16 +c.andi a5, #-8 +c.andi s0, #-4 +c.andi s1, #-2 + +; Positive edge cases +c.andi s0, #1 +c.andi s1, #2 +c.andi a0, #4 +c.andi a1, #8 +c.andi a2, #16 +c.andi a3, #15 +c.andi a4, #30 + +; Testing different compressed registers (x8-x15: s0, s1, a0-a5) +c.andi a0, #-32 +c.andi a1, #-32 +c.andi a2, #-32 +c.andi a3, #-32 +c.andi a4, #-32 +c.andi a5, #-32 +c.andi s0, #-32 +c.andi s1, #-32 + +c.andi a0, #31 +c.andi a1, #31 +c.andi a2, #31 +c.andi a3, #31 +c.andi a4, #31 +c.andi a5, #31 +c.andi s0, #31 +c.andi s1, #31 + diff --git a/tests/riscv/c-extension/c_andi_edge_cases.bin b/tests/riscv/c-extension/c_andi_edge_cases.bin new file mode 100644 index 0000000..4005df1 --- /dev/null +++ b/tests/riscv/c-extension/c_andi_edge_cases.bin @@ -0,0 +1 @@ +AqAy}}}} \ No newline at end of file diff --git a/tests/riscv/c-extension/c_andi_edge_cases.disasm b/tests/riscv/c-extension/c_andi_edge_cases.disasm new file mode 100644 index 0000000..110f8e0 --- /dev/null +++ b/tests/riscv/c-extension/c_andi_edge_cases.disasm @@ -0,0 +1,31 @@ +c.andi a0, #-32 +c.andi a1, #31 +c.andi a2, #0 +c.andi a3, #-1 +c.andi a4, #-16 +c.andi a5, #-8 +c.andi s0, #-4 +c.andi s1, #-2 +c.andi s0, #1 +c.andi s1, #2 +c.andi a0, #4 +c.andi a1, #8 +c.andi a2, #16 +c.andi a3, #15 +c.andi a4, #30 +c.andi a0, #-32 +c.andi a1, #-32 +c.andi a2, #-32 +c.andi a3, #-32 +c.andi a4, #-32 +c.andi a5, #-32 +c.andi s0, #-32 +c.andi s1, #-32 +c.andi a0, #31 +c.andi a1, #31 +c.andi a2, #31 +c.andi a3, #31 +c.andi a4, #31 +c.andi a5, #31 +c.andi s0, #31 +c.andi s1, #31 diff --git a/tests/riscv/c-extension/c_beqz.asm b/tests/riscv/c-extension/c_beqz.asm new file mode 100644 index 0000000..6e65357 --- /dev/null +++ b/tests/riscv/c-extension/c_beqz.asm @@ -0,0 +1,6 @@ +.lang riscv32 +.org 0x0 + +c.beqz a0, label +label: + diff --git a/tests/riscv/c-extension/c_beqz.bin b/tests/riscv/c-extension/c_beqz.bin new file mode 100644 index 0000000..55a3f9e --- /dev/null +++ b/tests/riscv/c-extension/c_beqz.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_beqz.disasm b/tests/riscv/c-extension/c_beqz.disasm new file mode 100644 index 0000000..11e5066 --- /dev/null +++ b/tests/riscv/c-extension/c_beqz.disasm @@ -0,0 +1 @@ +c.beqz a0, #2 diff --git a/tests/riscv/c-extension/c_beqz_edge_cases.asm b/tests/riscv/c-extension/c_beqz_edge_cases.asm new file mode 100644 index 0000000..9515bd0 --- /dev/null +++ b/tests/riscv/c-extension/c_beqz_edge_cases.asm @@ -0,0 +1,56 @@ +.lang riscv32 +.org 0x0 + +; Edge cases for c.beqz: testing different compressed registers and branch distances + +; Test all compressed registers (x8-x15: s0, s1, a0-a5) +c.beqz a0, label1 +c.beqz a1, label2 +c.beqz a2, label3 +c.beqz a3, label4 +c.beqz a4, label5 +c.beqz a5, label6 +c.beqz s0, label7 +c.beqz s1, label8 + +; Forward branches of different distances +label1: +c.beqz a0, label2 +label2: +c.beqz a1, label3 +label3: +c.beqz a2, label4 +label4: +c.beqz a3, label5 +label5: +c.beqz a4, label6 +label6: +c.beqz a5, label7 +label7: +c.beqz s0, label8 +label8: +c.beqz s1, label9 +label9: + +; Backward branches +c.beqz a0, label1 +c.beqz a1, label2 +c.beqz a2, label3 +c.beqz a3, label4 +c.beqz a4, label5 +c.beqz a5, label6 +c.beqz s0, label7 +c.beqz s1, label8 + +; Multiple branches to same label +c.beqz a0, common_label +c.beqz a1, common_label +c.beqz a2, common_label +common_label: + +; Nested branches +c.beqz a0, outer_label +outer_label: +c.beqz a1, inner_label +inner_label: + diff --git a/tests/riscv/c-extension/c_beqz_edge_cases.bin b/tests/riscv/c-extension/c_beqz_edge_cases.bin new file mode 100644 index 0000000..8e35681 --- /dev/null +++ b/tests/riscv/c-extension/c_beqz_edge_cases.bin @@ -0,0 +1 @@ +Ɂʁˁȁ ‰ É eeee \ No newline at end of file diff --git a/tests/riscv/c-extension/c_beqz_edge_cases.disasm b/tests/riscv/c-extension/c_beqz_edge_cases.disasm new file mode 100644 index 0000000..e2caf39 --- /dev/null +++ b/tests/riscv/c-extension/c_beqz_edge_cases.disasm @@ -0,0 +1,29 @@ +c.beqz a0, #16 +c.beqz a1, #16 +c.beqz a2, #16 +c.beqz a3, #16 +c.beqz a4, #16 +c.beqz a5, #16 +c.beqz s0, #16 +c.beqz s1, #16 +c.beqz a0, #2 +c.beqz a1, #2 +c.beqz a2, #2 +c.beqz a3, #2 +c.beqz a4, #2 +c.beqz a5, #2 +c.beqz s0, #2 +c.beqz s1, #2 +c.beqz a0, #-16 +c.beqz a1, #-16 +c.beqz a2, #-16 +c.beqz a3, #-16 +c.beqz a4, #-16 +c.beqz a5, #-16 +c.beqz s0, #-16 +c.beqz s1, #-16 +c.beqz a0, #6 +c.beqz a1, #4 +c.beqz a2, #2 +c.beqz a0, #2 +c.beqz a1, #2 diff --git a/tests/riscv/c-extension/c_bnez.asm b/tests/riscv/c-extension/c_bnez.asm new file mode 100644 index 0000000..5f6a712 --- /dev/null +++ b/tests/riscv/c-extension/c_bnez.asm @@ -0,0 +1,6 @@ +.lang riscv32 +.org 0x0 + +c.bnez a0, label +label: + diff --git a/tests/riscv/c-extension/c_bnez.bin b/tests/riscv/c-extension/c_bnez.bin new file mode 100644 index 0000000..db5df89 --- /dev/null +++ b/tests/riscv/c-extension/c_bnez.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_bnez.disasm b/tests/riscv/c-extension/c_bnez.disasm new file mode 100644 index 0000000..d7712d5 --- /dev/null +++ b/tests/riscv/c-extension/c_bnez.disasm @@ -0,0 +1 @@ +c.bnez a0, #2 diff --git a/tests/riscv/c-extension/c_ebreak.asm b/tests/riscv/c-extension/c_ebreak.asm new file mode 100644 index 0000000..a3706a5 --- /dev/null +++ b/tests/riscv/c-extension/c_ebreak.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.ebreak + diff --git a/tests/riscv/c-extension/c_ebreak.bin b/tests/riscv/c-extension/c_ebreak.bin new file mode 100644 index 0000000..c0dc987 --- /dev/null +++ b/tests/riscv/c-extension/c_ebreak.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_ebreak.disasm b/tests/riscv/c-extension/c_ebreak.disasm new file mode 100644 index 0000000..d1cda2d --- /dev/null +++ b/tests/riscv/c-extension/c_ebreak.disasm @@ -0,0 +1,10 @@ +Colliding matches: "c.ebreak c.add " +1: "c.ebreak" +2: "c.add a0, a1" +Colliding matches: "c.ebreak c.add " +1: "c.ebreak" +2: "c.add a0, a1" +Colliding matches: "c.ebreak c.add " +1: "c.ebreak" +2: "c.add a0, a1" +c.ebreak diff --git a/tests/riscv/c-extension/c_j.asm b/tests/riscv/c-extension/c_j.asm new file mode 100644 index 0000000..6975b26 --- /dev/null +++ b/tests/riscv/c-extension/c_j.asm @@ -0,0 +1,6 @@ +.lang riscv32 +.org 0x0 + +c.j label +label: + diff --git a/tests/riscv/c-extension/c_j.bin b/tests/riscv/c-extension/c_j.bin new file mode 100644 index 0000000..ee629f7 --- /dev/null +++ b/tests/riscv/c-extension/c_j.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_j.disasm b/tests/riscv/c-extension/c_j.disasm new file mode 100644 index 0000000..4c4576c --- /dev/null +++ b/tests/riscv/c-extension/c_j.disasm @@ -0,0 +1 @@ +c.j #2 diff --git a/tests/riscv/c-extension/c_jalr.asm b/tests/riscv/c-extension/c_jalr.asm new file mode 100644 index 0000000..42ba950 --- /dev/null +++ b/tests/riscv/c-extension/c_jalr.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.jalr a0 + diff --git a/tests/riscv/c-extension/c_jalr.bin b/tests/riscv/c-extension/c_jalr.bin new file mode 100644 index 0000000..a85fd75 --- /dev/null +++ b/tests/riscv/c-extension/c_jalr.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_jalr.disasm b/tests/riscv/c-extension/c_jalr.disasm new file mode 100644 index 0000000..1cd5a45 --- /dev/null +++ b/tests/riscv/c-extension/c_jalr.disasm @@ -0,0 +1,10 @@ +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +c.jalr a0 diff --git a/tests/riscv/c-extension/c_jalr_edge_cases.asm b/tests/riscv/c-extension/c_jalr_edge_cases.asm new file mode 100644 index 0000000..c851f0b --- /dev/null +++ b/tests/riscv/c-extension/c_jalr_edge_cases.asm @@ -0,0 +1,28 @@ +.lang riscv32 +.org 0x0 + +; Edge case tests for c.jalr +; c.jalr jumps to address in rs1 and stores return address in ra (x1) + +; Test various rs1 registers +c.jalr a0 +c.jalr a1 +c.jalr a2 +c.jalr a3 +c.jalr a4 +c.jalr a5 +c.jalr a6 +c.jalr a7 +c.jalr s0 +c.jalr s1 +c.jalr t0 +c.jalr t1 +c.jalr t2 +c.jalr ra +c.jalr sp +c.jalr gp +c.jalr tp + +; Note: c.jalr with rs1=zero (x0) is reserved and should encode as c.ebreak +; This is handled by the assembler/encoder, not by the instruction definition + diff --git a/tests/riscv/c-extension/c_jalr_edge_cases.bin b/tests/riscv/c-extension/c_jalr_edge_cases.bin new file mode 100644 index 0000000..2550c8d --- /dev/null +++ b/tests/riscv/c-extension/c_jalr_edge_cases.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_jalr_edge_cases.disasm b/tests/riscv/c-extension/c_jalr_edge_cases.disasm new file mode 100644 index 0000000..da8cda6 --- /dev/null +++ b/tests/riscv/c-extension/c_jalr_edge_cases.disasm @@ -0,0 +1,74 @@ +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +Colliding matches: "c.jalr c.add " +1: "c.jalr a0" +2: "c.add a0, a1" +c.jalr a0 +c.jalr a1 +c.jalr a2 +c.jalr a3 +c.jalr a4 +c.jalr a5 +c.jalr a6 +c.jalr a7 +c.jalr s0 +c.jalr s1 +c.jalr t0 +c.jalr t1 +c.jalr t2 +c.jalr ra +c.jalr sp +c.jalr gp +c.jalr tp diff --git a/tests/riscv/c-extension/c_jr.asm b/tests/riscv/c-extension/c_jr.asm new file mode 100644 index 0000000..696102a --- /dev/null +++ b/tests/riscv/c-extension/c_jr.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.jr a0 + diff --git a/tests/riscv/c-extension/c_jr.bin b/tests/riscv/c-extension/c_jr.bin new file mode 100644 index 0000000..f771dd7 --- /dev/null +++ b/tests/riscv/c-extension/c_jr.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_jr.disasm b/tests/riscv/c-extension/c_jr.disasm new file mode 100644 index 0000000..b549829 --- /dev/null +++ b/tests/riscv/c-extension/c_jr.disasm @@ -0,0 +1 @@ +c.jr a0 diff --git a/tests/riscv/c-extension/c_li.asm b/tests/riscv/c-extension/c_li.asm new file mode 100644 index 0000000..7c8333b --- /dev/null +++ b/tests/riscv/c-extension/c_li.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.li a0, #5 + diff --git a/tests/riscv/c-extension/c_li.bin b/tests/riscv/c-extension/c_li.bin new file mode 100644 index 0000000..ab77954 --- /dev/null +++ b/tests/riscv/c-extension/c_li.bin @@ -0,0 +1 @@ +E \ No newline at end of file diff --git a/tests/riscv/c-extension/c_li.disasm b/tests/riscv/c-extension/c_li.disasm new file mode 100644 index 0000000..6b82d56 --- /dev/null +++ b/tests/riscv/c-extension/c_li.disasm @@ -0,0 +1 @@ +c.li a0, #5 diff --git a/tests/riscv/c-extension/c_lui.asm b/tests/riscv/c-extension/c_lui.asm new file mode 100644 index 0000000..4bd924e --- /dev/null +++ b/tests/riscv/c-extension/c_lui.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.lui a0, #0x10000 + diff --git a/tests/riscv/c-extension/c_lui.bin b/tests/riscv/c-extension/c_lui.bin new file mode 100644 index 0000000..936f97f --- /dev/null +++ b/tests/riscv/c-extension/c_lui.bin @@ -0,0 +1 @@ +Ae \ No newline at end of file diff --git a/tests/riscv/c-extension/c_lui.disasm b/tests/riscv/c-extension/c_lui.disasm new file mode 100644 index 0000000..607d532 --- /dev/null +++ b/tests/riscv/c-extension/c_lui.disasm @@ -0,0 +1 @@ +c.lui a0, #0x10000 diff --git a/tests/riscv/c-extension/c_lui_edge_cases.asm b/tests/riscv/c-extension/c_lui_edge_cases.asm new file mode 100644 index 0000000..38dc4b9 --- /dev/null +++ b/tests/riscv/c-extension/c_lui_edge_cases.asm @@ -0,0 +1,51 @@ +.lang riscv32 +.org 0x0 + +; Edge case tests for c.lui instruction +; c.lui: rd = imm << 12, where imm[17:12] is in range 1-63 (imm[17:12]=0 is reserved for c.addi16sp) + +; Test minimum immediate value (imm[17:12] = 1, so imm = 0x1000) +c.lui a0, #0x1000 + +; Test various immediate values +c.lui a0, #0x2000 +c.lui a0, #0x3000 +c.lui a0, #0x4000 +c.lui a0, #0x5000 +c.lui a0, #0x6000 +c.lui a0, #0x7000 +c.lui a0, #0x8000 +c.lui a0, #0x9000 +c.lui a0, #0xA000 +c.lui a0, #0xB000 +c.lui a0, #0xC000 +c.lui a0, #0xD000 +c.lui a0, #0xE000 +c.lui a0, #0xF000 + +; Test maximum positive immediate value (imm[17:12] = 31, so imm = 0x1F000) +c.lui a0, #0x1F000 + +; Test with different registers (rd != 0 and rd != 2) +c.lui a1, #0x10000 +c.lui a2, #0x10000 +c.lui a3, #0x10000 +c.lui a4, #0x10000 +c.lui a5, #0x10000 +c.lui a6, #0x10000 +c.lui a7, #0x10000 +c.lui t0, #0x10000 +c.lui t1, #0x10000 +c.lui t2, #0x10000 +c.lui s0, #0x10000 +c.lui s1, #0x10000 + +; Test with various immediate values and different registers +; Note: c.lui uses 6-bit signed imm[17:12], so max positive is 0x1F000, not 0x20000+ +c.lui a0, #0x1F000 +c.lui a1, #0x1E000 +c.lui a2, #0x1D000 +c.lui a3, #0x1000 +c.lui a4, #0x2000 +c.lui a5, #0x1F000 + diff --git a/tests/riscv/c-extension/c_lui_edge_cases.bin b/tests/riscv/c-extension/c_lui_edge_cases.bin new file mode 100644 index 0000000..6aa817d --- /dev/null +++ b/tests/riscv/c-extension/c_lui_edge_cases.bin @@ -0,0 +1 @@ +e e eeeee!e%e)e-e1e5e9e=e}eeAffAggAhhbAccAdd}eeuff gg \ No newline at end of file diff --git a/tests/riscv/c-extension/c_lui_edge_cases.disasm b/tests/riscv/c-extension/c_lui_edge_cases.disasm new file mode 100644 index 0000000..8d92e8a --- /dev/null +++ b/tests/riscv/c-extension/c_lui_edge_cases.disasm @@ -0,0 +1,34 @@ +c.lui a0, #0x1000 +c.lui a0, #0x2000 +c.lui a0, #0x3000 +c.lui a0, #0x4000 +c.lui a0, #0x5000 +c.lui a0, #0x6000 +c.lui a0, #0x7000 +c.lui a0, #0x8000 +c.lui a0, #0x9000 +c.lui a0, #0xa000 +c.lui a0, #0xb000 +c.lui a0, #0xc000 +c.lui a0, #0xd000 +c.lui a0, #0xe000 +c.lui a0, #0xf000 +c.lui a0, #0x1f000 +c.lui a1, #0x10000 +c.lui a2, #0x10000 +c.lui a3, #0x10000 +c.lui a4, #0x10000 +c.lui a5, #0x10000 +c.lui a6, #0x10000 +c.lui a7, #0x10000 +c.lui t0, #0x10000 +c.lui t1, #0x10000 +c.lui t2, #0x10000 +c.lui s0, #0x10000 +c.lui s1, #0x10000 +c.lui a0, #0x1f000 +c.lui a1, #0x1e000 +c.lui a2, #0x1d000 +c.lui a3, #0x1000 +c.lui a4, #0x2000 +c.lui a5, #0x1f000 diff --git a/tests/riscv/c-extension/c_lw.asm b/tests/riscv/c-extension/c_lw.asm new file mode 100644 index 0000000..b8c5a4b --- /dev/null +++ b/tests/riscv/c-extension/c_lw.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.lw a0, (#4, a1) + diff --git a/tests/riscv/c-extension/c_lw.bin b/tests/riscv/c-extension/c_lw.bin new file mode 100644 index 0000000..0fda1ef --- /dev/null +++ b/tests/riscv/c-extension/c_lw.bin @@ -0,0 +1 @@ +A \ No newline at end of file diff --git a/tests/riscv/c-extension/c_lw.disasm b/tests/riscv/c-extension/c_lw.disasm new file mode 100644 index 0000000..acc6541 --- /dev/null +++ b/tests/riscv/c-extension/c_lw.disasm @@ -0,0 +1 @@ +c.lw a0, (#4, a1) diff --git a/tests/riscv/c-extension/c_lwsp.asm b/tests/riscv/c-extension/c_lwsp.asm new file mode 100644 index 0000000..28e64ac --- /dev/null +++ b/tests/riscv/c-extension/c_lwsp.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.lwsp a0, #4 + diff --git a/tests/riscv/c-extension/c_lwsp.bin b/tests/riscv/c-extension/c_lwsp.bin new file mode 100644 index 0000000..f838c12 --- /dev/null +++ b/tests/riscv/c-extension/c_lwsp.bin @@ -0,0 +1 @@ +E \ No newline at end of file diff --git a/tests/riscv/c-extension/c_lwsp.disasm b/tests/riscv/c-extension/c_lwsp.disasm new file mode 100644 index 0000000..40a4905 --- /dev/null +++ b/tests/riscv/c-extension/c_lwsp.disasm @@ -0,0 +1 @@ +c.lwsp a0, #4 diff --git a/tests/riscv/c-extension/c_mv.asm b/tests/riscv/c-extension/c_mv.asm new file mode 100644 index 0000000..e20164f --- /dev/null +++ b/tests/riscv/c-extension/c_mv.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.mv a0, a1 + diff --git a/tests/riscv/c-extension/c_mv.bin b/tests/riscv/c-extension/c_mv.bin new file mode 100644 index 0000000..856ac95 --- /dev/null +++ b/tests/riscv/c-extension/c_mv.bin @@ -0,0 +1 @@ +. \ No newline at end of file diff --git a/tests/riscv/c-extension/c_mv.disasm b/tests/riscv/c-extension/c_mv.disasm new file mode 100644 index 0000000..0f6703d --- /dev/null +++ b/tests/riscv/c-extension/c_mv.disasm @@ -0,0 +1 @@ +c.mv a0, a1 diff --git a/tests/riscv/c-extension/c_mv_edge_cases.asm b/tests/riscv/c-extension/c_mv_edge_cases.asm new file mode 100644 index 0000000..44020c8 --- /dev/null +++ b/tests/riscv/c-extension/c_mv_edge_cases.asm @@ -0,0 +1,120 @@ +.lang riscv32 +.org 0x0 + +; Edge cases for c.mv: Move register to register +; Testing all register combinations, including edge cases + +; Basic test - already in c_mv.asm +c.mv a0, a1 + +; Test all compressed register combinations (x8-x15: s0, s1, a0-a5) +; These are the only registers that c.mv can use (according to RISC-V spec, c.mv uses regular 5-bit register encoding) + +; Testing all destination registers with a1 as source +; Note: c.mv with rd=0 is reserved (use c.jr instead), so we skip zero +c.mv ra, a1 +c.mv sp, a1 +c.mv gp, a1 +c.mv tp, a1 +c.mv t0, a1 +c.mv t1, a1 +c.mv t2, a1 +c.mv s0, a1 +c.mv s1, a1 +c.mv a0, a1 +c.mv a1, a1 ; Move to itself (legal but effectively nop) +c.mv a2, a1 +c.mv a3, a1 +c.mv a4, a1 +c.mv a5, a1 + +; Testing all source registers with a0 as destination +; Note: c.mv with rs2=zero is invalid (reserved encoding - use c.jr instead) +c.mv a0, ra +c.mv a0, sp +c.mv a0, gp +c.mv a0, tp +c.mv a0, t0 +c.mv a0, t1 +c.mv a0, t2 +c.mv a0, s0 +c.mv a0, s1 +c.mv a0, a0 ; Move to itself (legal but effectively nop) +c.mv a0, a1 +c.mv a0, a2 +c.mv a0, a3 +c.mv a0, a4 +c.mv a0, a5 + +; Test all argument registers (a0-a7) combinations +c.mv a0, a1 +c.mv a0, a2 +c.mv a0, a3 +c.mv a0, a4 +c.mv a0, a5 +c.mv a1, a0 +c.mv a1, a2 +c.mv a1, a3 +c.mv a1, a4 +c.mv a1, a5 +c.mv a2, a0 +c.mv a2, a1 +c.mv a2, a3 +c.mv a2, a4 +c.mv a2, a5 +c.mv a3, a0 +c.mv a3, a1 +c.mv a3, a2 +c.mv a3, a4 +c.mv a3, a5 +c.mv a4, a0 +c.mv a4, a1 +c.mv a4, a2 +c.mv a4, a3 +c.mv a4, a5 +c.mv a5, a0 +c.mv a5, a1 +c.mv a5, a2 +c.mv a5, a3 +c.mv a5, a4 + +; Test saved registers (s0, s1) combinations +c.mv s0, s1 +c.mv s1, s0 +c.mv s0, a0 +c.mv s0, a1 +c.mv s1, a0 +c.mv s1, a1 +c.mv a0, s0 +c.mv a0, s1 +c.mv a1, s0 +c.mv a1, s1 + +; Test temporary registers (t0-t2) combinations +c.mv t0, t1 +c.mv t0, t2 +c.mv t1, t0 +c.mv t1, t2 +c.mv t2, t0 +c.mv t2, t1 +c.mv a0, t0 +c.mv a0, t1 +c.mv a0, t2 +c.mv t0, a0 +c.mv t1, a0 +c.mv t2, a0 + +; Test special registers as source +; Note: c.mv with rs2=zero is invalid (reserved encoding - use c.jr or c.add with zero instead) +c.mv a0, ra ; Move return address +c.mv a0, sp ; Move stack pointer +c.mv a0, gp ; Move global pointer +c.mv a0, tp ; Move thread pointer +; Note: c.mv with zero as destination (rd=0) is reserved - use c.jr instead +c.mv ra, a0 ; Move to return address +c.mv sp, a0 ; Move to stack pointer +c.mv gp, a0 ; Move to global pointer +c.mv tp, a0 ; Move to thread pointer + +; Note: According to RISC-V spec, c.mv with rd=0 is reserved and should be encoded as c.jr instead. +; Therefore, we don't test c.mv with zero as destination here - that's tested in c_jr.asm diff --git a/tests/riscv/c-extension/c_mv_edge_cases.bin b/tests/riscv/c-extension/c_mv_edge_cases.bin new file mode 100644 index 0000000..d733b0b --- /dev/null +++ b/tests/riscv/c-extension/c_mv_edge_cases.bin @@ -0,0 +1,3 @@ +........ +"&*.26:>.26:>*.6:>*.26>&*."&* +** \ No newline at end of file diff --git a/tests/riscv/c-extension/c_mv_edge_cases.disasm b/tests/riscv/c-extension/c_mv_edge_cases.disasm new file mode 100644 index 0000000..5d0781a --- /dev/null +++ b/tests/riscv/c-extension/c_mv_edge_cases.disasm @@ -0,0 +1,91 @@ +c.mv a0, a1 +c.mv ra, a1 +c.mv sp, a1 +c.mv gp, a1 +c.mv tp, a1 +c.mv t0, a1 +c.mv t1, a1 +c.mv t2, a1 +c.mv s0, a1 +c.mv s1, a1 +c.mv a0, a1 +c.mv a1, a1 +c.mv a2, a1 +c.mv a3, a1 +c.mv a4, a1 +c.mv a5, a1 +c.mv a0, ra +c.mv a0, sp +c.mv a0, gp +c.mv a0, tp +c.mv a0, t0 +c.mv a0, t1 +c.mv a0, t2 +c.mv a0, s0 +c.mv a0, s1 +c.mv a0, a0 +c.mv a0, a1 +c.mv a0, a2 +c.mv a0, a3 +c.mv a0, a4 +c.mv a0, a5 +c.mv a0, a1 +c.mv a0, a2 +c.mv a0, a3 +c.mv a0, a4 +c.mv a0, a5 +c.mv a1, a0 +c.mv a1, a2 +c.mv a1, a3 +c.mv a1, a4 +c.mv a1, a5 +c.mv a2, a0 +c.mv a2, a1 +c.mv a2, a3 +c.mv a2, a4 +c.mv a2, a5 +c.mv a3, a0 +c.mv a3, a1 +c.mv a3, a2 +c.mv a3, a4 +c.mv a3, a5 +c.mv a4, a0 +c.mv a4, a1 +c.mv a4, a2 +c.mv a4, a3 +c.mv a4, a5 +c.mv a5, a0 +c.mv a5, a1 +c.mv a5, a2 +c.mv a5, a3 +c.mv a5, a4 +c.mv s0, s1 +c.mv s1, s0 +c.mv s0, a0 +c.mv s0, a1 +c.mv s1, a0 +c.mv s1, a1 +c.mv a0, s0 +c.mv a0, s1 +c.mv a1, s0 +c.mv a1, s1 +c.mv t0, t1 +c.mv t0, t2 +c.mv t1, t0 +c.mv t1, t2 +c.mv t2, t0 +c.mv t2, t1 +c.mv a0, t0 +c.mv a0, t1 +c.mv a0, t2 +c.mv t0, a0 +c.mv t1, a0 +c.mv t2, a0 +c.mv a0, ra +c.mv a0, sp +c.mv a0, gp +c.mv a0, tp +c.mv ra, a0 +c.mv sp, a0 +c.mv gp, a0 +c.mv tp, a0 diff --git a/tests/riscv/c-extension/c_nop.asm b/tests/riscv/c-extension/c_nop.asm new file mode 100644 index 0000000..e23624f --- /dev/null +++ b/tests/riscv/c-extension/c_nop.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.nop + diff --git a/tests/riscv/c-extension/c_nop.bin b/tests/riscv/c-extension/c_nop.bin new file mode 100644 index 0000000000000000000000000000000000000000..35a038769b15c0935bb3cd038f5cc1de7579f128 GIT binary patch literal 2 JcmZQ%0000400IC2 literal 0 HcmV?d00001 diff --git a/tests/riscv/c-extension/c_nop.disasm b/tests/riscv/c-extension/c_nop.disasm new file mode 100644 index 0000000..b324ca4 --- /dev/null +++ b/tests/riscv/c-extension/c_nop.disasm @@ -0,0 +1 @@ +c.nop diff --git a/tests/riscv/c-extension/c_or.asm b/tests/riscv/c-extension/c_or.asm new file mode 100644 index 0000000..11a7739 --- /dev/null +++ b/tests/riscv/c-extension/c_or.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.or a0, a1 + diff --git a/tests/riscv/c-extension/c_or.bin b/tests/riscv/c-extension/c_or.bin new file mode 100644 index 0000000..3f434f7 --- /dev/null +++ b/tests/riscv/c-extension/c_or.bin @@ -0,0 +1 @@ +M \ No newline at end of file diff --git a/tests/riscv/c-extension/c_or.disasm b/tests/riscv/c-extension/c_or.disasm new file mode 100644 index 0000000..14bbeb9 --- /dev/null +++ b/tests/riscv/c-extension/c_or.disasm @@ -0,0 +1 @@ +c.or a0, a1 diff --git a/tests/riscv/c-extension/c_slli.asm b/tests/riscv/c-extension/c_slli.asm new file mode 100644 index 0000000..3b6ad03 --- /dev/null +++ b/tests/riscv/c-extension/c_slli.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.slli a0, #3 + diff --git a/tests/riscv/c-extension/c_slli.bin b/tests/riscv/c-extension/c_slli.bin new file mode 100644 index 0000000..d2fa5a1 --- /dev/null +++ b/tests/riscv/c-extension/c_slli.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_slli.disasm b/tests/riscv/c-extension/c_slli.disasm new file mode 100644 index 0000000..15d6e26 --- /dev/null +++ b/tests/riscv/c-extension/c_slli.disasm @@ -0,0 +1 @@ +c.slli a0, #3 diff --git a/tests/riscv/c-extension/c_srai.asm b/tests/riscv/c-extension/c_srai.asm new file mode 100644 index 0000000..a9c9031 --- /dev/null +++ b/tests/riscv/c-extension/c_srai.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.srai a0, #3 + diff --git a/tests/riscv/c-extension/c_srai.bin b/tests/riscv/c-extension/c_srai.bin new file mode 100644 index 0000000..44f452d --- /dev/null +++ b/tests/riscv/c-extension/c_srai.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_srai.disasm b/tests/riscv/c-extension/c_srai.disasm new file mode 100644 index 0000000..d19fcc0 --- /dev/null +++ b/tests/riscv/c-extension/c_srai.disasm @@ -0,0 +1 @@ +c.srai a0, #3 diff --git a/tests/riscv/c-extension/c_srli.asm b/tests/riscv/c-extension/c_srli.asm new file mode 100644 index 0000000..a2b77e0 --- /dev/null +++ b/tests/riscv/c-extension/c_srli.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.srli a0, #3 + diff --git a/tests/riscv/c-extension/c_srli.bin b/tests/riscv/c-extension/c_srli.bin new file mode 100644 index 0000000..da50c26 --- /dev/null +++ b/tests/riscv/c-extension/c_srli.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_srli.disasm b/tests/riscv/c-extension/c_srli.disasm new file mode 100644 index 0000000..4daa25b --- /dev/null +++ b/tests/riscv/c-extension/c_srli.disasm @@ -0,0 +1 @@ +c.srli a0, #3 diff --git a/tests/riscv/c-extension/c_sub.asm b/tests/riscv/c-extension/c_sub.asm new file mode 100644 index 0000000..0ee3d97 --- /dev/null +++ b/tests/riscv/c-extension/c_sub.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.sub a0, a1 + diff --git a/tests/riscv/c-extension/c_sub.bin b/tests/riscv/c-extension/c_sub.bin new file mode 100644 index 0000000..795689c --- /dev/null +++ b/tests/riscv/c-extension/c_sub.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_sub.disasm b/tests/riscv/c-extension/c_sub.disasm new file mode 100644 index 0000000..2459b1e --- /dev/null +++ b/tests/riscv/c-extension/c_sub.disasm @@ -0,0 +1 @@ +c.sub a0, a1 diff --git a/tests/riscv/c-extension/c_sw.asm b/tests/riscv/c-extension/c_sw.asm new file mode 100644 index 0000000..10d638b --- /dev/null +++ b/tests/riscv/c-extension/c_sw.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.sw a0, (#4, a1) + diff --git a/tests/riscv/c-extension/c_sw.bin b/tests/riscv/c-extension/c_sw.bin new file mode 100644 index 0000000..c60028a --- /dev/null +++ b/tests/riscv/c-extension/c_sw.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_sw.disasm b/tests/riscv/c-extension/c_sw.disasm new file mode 100644 index 0000000..a6c6b64 --- /dev/null +++ b/tests/riscv/c-extension/c_sw.disasm @@ -0,0 +1 @@ +c.sw a0, (#4, a1) diff --git a/tests/riscv/c-extension/c_swsp.asm b/tests/riscv/c-extension/c_swsp.asm new file mode 100644 index 0000000..5d0a3ca --- /dev/null +++ b/tests/riscv/c-extension/c_swsp.asm @@ -0,0 +1,47 @@ +.lang riscv32 +.org 0x0 + +; Basic test cases (from original failing tests - now FIXED) +c.swsp a0, #4 +c.swsp a2, #12 + +; Edge cases: minimum and maximum immediate values +c.swsp t6, #0 +c.swsp t1, #252 + +; Edge cases: various immediate values (must be multiples of 4) +c.swsp a1, #8 +c.swsp a3, #16 +c.swsp a4, #20 +c.swsp a5, #24 +c.swsp a6, #32 +c.swsp a7, #64 +c.swsp s0, #128 +c.swsp s1, #248 + +; Edge cases: different register types +c.swsp ra, #4 +c.swsp sp, #8 +c.swsp gp, #12 +c.swsp tp, #16 +c.swsp t0, #20 +c.swsp t2, #28 +c.swsp s2, #36 +c.swsp s3, #40 +c.swsp s4, #44 +c.swsp s5, #48 +c.swsp s6, #52 +c.swsp s7, #56 +c.swsp s8, #60 +c.swsp s9, #68 +c.swsp s10, #72 +c.swsp s11, #76 +c.swsp t3, #80 +c.swsp t4, #84 +c.swsp t5, #88 + +; Edge cases: boundary immediate values and zero register +c.swsp zero, #0 +c.swsp a0, #4 +c.swsp a1, #252 + diff --git a/tests/riscv/c-extension/c_swsp.bin b/tests/riscv/c-extension/c_swsp.bin new file mode 100644 index 0000000..fcf72ea --- /dev/null +++ b/tests/riscv/c-extension/c_swsp.bin @@ -0,0 +1,2 @@ +~.6º>BF"&߆ +–žNV^jrz \ No newline at end of file diff --git a/tests/riscv/c-extension/c_swsp.disasm b/tests/riscv/c-extension/c_swsp.disasm new file mode 100644 index 0000000..a5a2fcd --- /dev/null +++ b/tests/riscv/c-extension/c_swsp.disasm @@ -0,0 +1,34 @@ +c.swsp a0, #4 +c.swsp a2, #12 +c.swsp t6, #0 +c.swsp t1, #252 +c.swsp a1, #8 +c.swsp a3, #16 +c.swsp a4, #20 +c.swsp a5, #24 +c.swsp a6, #32 +c.swsp a7, #64 +c.swsp s0, #128 +c.swsp s1, #248 +c.swsp ra, #4 +c.swsp sp, #8 +c.swsp gp, #12 +c.swsp tp, #16 +c.swsp t0, #20 +c.swsp t2, #28 +c.swsp s2, #36 +c.swsp s3, #40 +c.swsp s4, #44 +c.swsp s5, #48 +c.swsp s6, #52 +c.swsp s7, #56 +c.swsp s8, #60 +c.swsp s9, #68 +c.swsp s10, #72 +c.swsp s11, #76 +c.swsp t3, #80 +c.swsp t4, #84 +c.swsp t5, #88 +c.swsp zero, #0 +c.swsp a0, #4 +c.swsp a1, #252 diff --git a/tests/riscv/c-extension/c_xor.asm b/tests/riscv/c-extension/c_xor.asm new file mode 100644 index 0000000..81070e6 --- /dev/null +++ b/tests/riscv/c-extension/c_xor.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.xor a0, a1 + diff --git a/tests/riscv/c-extension/c_xor.bin b/tests/riscv/c-extension/c_xor.bin new file mode 100644 index 0000000..a0fd56a --- /dev/null +++ b/tests/riscv/c-extension/c_xor.bin @@ -0,0 +1 @@ +- \ No newline at end of file diff --git a/tests/riscv/c-extension/c_xor.disasm b/tests/riscv/c-extension/c_xor.disasm new file mode 100644 index 0000000..5e40ccc --- /dev/null +++ b/tests/riscv/c-extension/c_xor.disasm @@ -0,0 +1 @@ +c.xor a0, a1 diff --git a/tests/riscv/c-extension/c_xor_a5.asm b/tests/riscv/c-extension/c_xor_a5.asm new file mode 100644 index 0000000..e6134d7 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_a5.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.xor a5, a4 + diff --git a/tests/riscv/c-extension/c_xor_a5.bin b/tests/riscv/c-extension/c_xor_a5.bin new file mode 100644 index 0000000..dd9d3f7 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_a5.bin @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/tests/riscv/c-extension/c_xor_a5.disasm b/tests/riscv/c-extension/c_xor_a5.disasm new file mode 100644 index 0000000..ca3db31 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_a5.disasm @@ -0,0 +1 @@ +c.xor a5, a4 diff --git a/tests/riscv/c-extension/c_xor_all_regs.asm b/tests/riscv/c-extension/c_xor_all_regs.asm new file mode 100644 index 0000000..5e54dc0 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_all_regs.asm @@ -0,0 +1,8 @@ +.lang riscv32 +.org 0x0 + +c.xor s0, s1 +c.xor a0, a1 +c.xor a2, a3 +c.xor a4, a5 + diff --git a/tests/riscv/c-extension/c_xor_all_regs.bin b/tests/riscv/c-extension/c_xor_all_regs.bin new file mode 100644 index 0000000..0a533ac --- /dev/null +++ b/tests/riscv/c-extension/c_xor_all_regs.bin @@ -0,0 +1 @@ +%-5= \ No newline at end of file diff --git a/tests/riscv/c-extension/c_xor_all_regs.disasm b/tests/riscv/c-extension/c_xor_all_regs.disasm new file mode 100644 index 0000000..c21233c --- /dev/null +++ b/tests/riscv/c-extension/c_xor_all_regs.disasm @@ -0,0 +1,4 @@ +c.xor s0, s1 +c.xor a0, a1 +c.xor a2, a3 +c.xor a4, a5 diff --git a/tests/riscv/c-extension/c_xor_mixed.asm b/tests/riscv/c-extension/c_xor_mixed.asm new file mode 100644 index 0000000..50a9c0e --- /dev/null +++ b/tests/riscv/c-extension/c_xor_mixed.asm @@ -0,0 +1,8 @@ +.lang riscv32 +.org 0x0 + +c.xor s1, a0 +c.xor a1, s0 +c.xor a2, a5 +c.xor a3, a0 + diff --git a/tests/riscv/c-extension/c_xor_mixed.bin b/tests/riscv/c-extension/c_xor_mixed.bin new file mode 100644 index 0000000..e3b0d43 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_mixed.bin @@ -0,0 +1 @@ += \ No newline at end of file diff --git a/tests/riscv/c-extension/c_xor_mixed.disasm b/tests/riscv/c-extension/c_xor_mixed.disasm new file mode 100644 index 0000000..05606b1 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_mixed.disasm @@ -0,0 +1,4 @@ +c.xor s1, a0 +c.xor a1, s0 +c.xor a2, a5 +c.xor a3, a0 diff --git a/tests/riscv/c-extension/c_xor_s0.asm b/tests/riscv/c-extension/c_xor_s0.asm new file mode 100644 index 0000000..6434cdf --- /dev/null +++ b/tests/riscv/c-extension/c_xor_s0.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.xor s0, a0 + diff --git a/tests/riscv/c-extension/c_xor_s0.bin b/tests/riscv/c-extension/c_xor_s0.bin new file mode 100644 index 0000000..323d643 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_s0.bin @@ -0,0 +1 @@ +) \ No newline at end of file diff --git a/tests/riscv/c-extension/c_xor_s0.disasm b/tests/riscv/c-extension/c_xor_s0.disasm new file mode 100644 index 0000000..0e21003 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_s0.disasm @@ -0,0 +1 @@ +c.xor s0, a0 diff --git a/tests/riscv/c-extension/c_xor_same_reg.asm b/tests/riscv/c-extension/c_xor_same_reg.asm new file mode 100644 index 0000000..cf29a0b --- /dev/null +++ b/tests/riscv/c-extension/c_xor_same_reg.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +c.xor a0, a0 + diff --git a/tests/riscv/c-extension/c_xor_same_reg.bin b/tests/riscv/c-extension/c_xor_same_reg.bin new file mode 100644 index 0000000..7fa1c50 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_same_reg.bin @@ -0,0 +1 @@ +) \ No newline at end of file diff --git a/tests/riscv/c-extension/c_xor_same_reg.disasm b/tests/riscv/c-extension/c_xor_same_reg.disasm new file mode 100644 index 0000000..8c11619 --- /dev/null +++ b/tests/riscv/c-extension/c_xor_same_reg.disasm @@ -0,0 +1 @@ +c.xor a0, a0 diff --git a/tests/riscv/d-extension/fadd.d.asm b/tests/riscv/d-extension/fadd.d.asm new file mode 100644 index 0000000..919099c --- /dev/null +++ b/tests/riscv/d-extension/fadd.d.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fadd.d f0, f0, f0 +fadd.d f0, f0, f1 +fadd.d f0, f0, f5 +fadd.d f0, f0, f10 +fadd.d f0, f0, f15 +fadd.d f0, f0, f20 +fadd.d f0, f0, f25 +fadd.d f0, f0, f31 +fadd.d f0, f1, f0 +fadd.d f0, f1, f1 +fadd.d f0, f1, f5 +fadd.d f0, f1, f10 +fadd.d f0, f1, f15 +fadd.d f0, f1, f20 +fadd.d f0, f1, f25 +fadd.d f0, f1, f31 +fadd.d f0, f5, f0 +fadd.d f0, f5, f1 +fadd.d f0, f5, f5 +fadd.d f0, f5, f10 +fadd.d f0, f5, f15 +fadd.d f0, f5, f20 +fadd.d f0, f5, f25 +fadd.d f0, f5, f31 +fadd.d f0, f10, f0 +fadd.d f0, f10, f1 +fadd.d f0, f10, f5 +fadd.d f0, f10, f10 +fadd.d f0, f10, f15 +fadd.d f0, f10, f20 +fadd.d f0, f10, f25 +fadd.d f0, f10, f31 +fadd.d f0, f15, f0 +fadd.d f0, f15, f1 +fadd.d f0, f15, f5 +fadd.d f0, f15, f10 +fadd.d f0, f15, f15 +fadd.d f0, f15, f20 +fadd.d f0, f15, f25 +fadd.d f0, f15, f31 +fadd.d f0, f20, f0 +fadd.d f0, f20, f1 +fadd.d f0, f20, f5 +fadd.d f0, f20, f10 +fadd.d f0, f20, f15 +fadd.d f0, f20, f20 +fadd.d f0, f20, f25 +fadd.d f0, f20, f31 +fadd.d f0, f25, f0 +fadd.d f0, f25, f1 +fadd.d f0, f25, f5 +fadd.d f0, f25, f10 +fadd.d f0, f25, f15 +fadd.d f0, f25, f20 +fadd.d f0, f25, f25 +fadd.d f0, f25, f31 +fadd.d f0, f31, f0 +fadd.d f0, f31, f1 +fadd.d f0, f31, f5 +fadd.d f0, f31, f10 +fadd.d f0, f31, f15 +fadd.d f0, f31, f20 +fadd.d f0, f31, f25 +fadd.d f0, f31, f31 +fadd.d f1, f0, f0 +fadd.d f1, f0, f1 +fadd.d f1, f0, f5 +fadd.d f1, f0, f10 +fadd.d f1, f0, f15 +fadd.d f1, f0, f20 +fadd.d f1, f0, f25 +fadd.d f1, f0, f31 +fadd.d f1, f1, f0 +fadd.d f1, f1, f1 +fadd.d f1, f1, f5 +fadd.d f1, f1, f10 +fadd.d f1, f1, f15 +fadd.d f1, f1, f20 +fadd.d f1, f1, f25 +fadd.d f1, f1, f31 +fadd.d f1, f5, f0 +fadd.d f1, f5, f1 +fadd.d f1, f5, f5 +fadd.d f1, f5, f10 +fadd.d f1, f5, f15 +fadd.d f1, f5, f20 +fadd.d f1, f5, f25 +fadd.d f1, f5, f31 +fadd.d f1, f10, f0 +fadd.d f1, f10, f1 +fadd.d f1, f10, f5 +fadd.d f1, f10, f10 +fadd.d f1, f10, f15 +fadd.d f1, f10, f20 +fadd.d f1, f10, f25 +fadd.d f1, f10, f31 +fadd.d f1, f15, f0 +fadd.d f1, f15, f1 +fadd.d f1, f15, f5 +fadd.d f1, f15, f10 +fadd.d f1, f15, f15 +fadd.d f1, f15, f20 +fadd.d f1, f15, f25 +fadd.d f1, f15, f31 +fadd.d f1, f20, f0 +fadd.d f1, f20, f1 +fadd.d f1, f20, f5 +fadd.d f1, f20, f10 +fadd.d f1, f20, f15 +fadd.d f1, f20, f20 +fadd.d f1, f20, f25 +fadd.d f1, f20, f31 +fadd.d f1, f25, f0 +fadd.d f1, f25, f1 +fadd.d f1, f25, f5 +fadd.d f1, f25, f10 +fadd.d f1, f25, f15 +fadd.d f1, f25, f20 +fadd.d f1, f25, f25 +fadd.d f1, f25, f31 +fadd.d f1, f31, f0 +fadd.d f1, f31, f1 +fadd.d f1, f31, f5 +fadd.d f1, f31, f10 +fadd.d f1, f31, f15 +fadd.d f1, f31, f20 +fadd.d f1, f31, f25 +fadd.d f1, f31, f31 +fadd.d f5, f0, f0 +fadd.d f5, f0, f1 +fadd.d f5, f0, f5 +fadd.d f5, f0, f10 +fadd.d f5, f0, f15 +fadd.d f5, f0, f20 +fadd.d f5, f0, f25 +fadd.d f5, f0, f31 +fadd.d f5, f1, f0 +fadd.d f5, f1, f1 +fadd.d f5, f1, f5 +fadd.d f5, f1, f10 +fadd.d f5, f1, f15 +fadd.d f5, f1, f20 +fadd.d f5, f1, f25 +fadd.d f5, f1, f31 +fadd.d f5, f5, f0 +fadd.d f5, f5, f1 +fadd.d f5, f5, f5 +fadd.d f5, f5, f10 +fadd.d f5, f5, f15 +fadd.d f5, f5, f20 +fadd.d f5, f5, f25 +fadd.d f5, f5, f31 +fadd.d f5, f10, f0 +fadd.d f5, f10, f1 +fadd.d f5, f10, f5 +fadd.d f5, f10, f10 +fadd.d f5, f10, f15 +fadd.d f5, f10, f20 +fadd.d f5, f10, f25 +fadd.d f5, f10, f31 +fadd.d f5, f15, f0 +fadd.d f5, f15, f1 +fadd.d f5, f15, f5 +fadd.d f5, f15, f10 +fadd.d f5, f15, f15 +fadd.d f5, f15, f20 +fadd.d f5, f15, f25 +fadd.d f5, f15, f31 +fadd.d f5, f20, f0 +fadd.d f5, f20, f1 +fadd.d f5, f20, f5 +fadd.d f5, f20, f10 +fadd.d f5, f20, f15 +fadd.d f5, f20, f20 +fadd.d f5, f20, f25 +fadd.d f5, f20, f31 +fadd.d f5, f25, f0 +fadd.d f5, f25, f1 +fadd.d f5, f25, f5 +fadd.d f5, f25, f10 +fadd.d f5, f25, f15 +fadd.d f5, f25, f20 +fadd.d f5, f25, f25 +fadd.d f5, f25, f31 +fadd.d f5, f31, f0 +fadd.d f5, f31, f1 +fadd.d f5, f31, f5 +fadd.d f5, f31, f10 +fadd.d f5, f31, f15 +fadd.d f5, f31, f20 +fadd.d f5, f31, f25 +fadd.d f5, f31, f31 +fadd.d f10, f0, f0 +fadd.d f10, f0, f1 +fadd.d f10, f0, f5 +fadd.d f10, f0, f10 +fadd.d f10, f0, f15 +fadd.d f10, f0, f20 +fadd.d f10, f0, f25 +fadd.d f10, f0, f31 +fadd.d f10, f1, f0 +fadd.d f10, f1, f1 +fadd.d f10, f1, f5 +fadd.d f10, f1, f10 +fadd.d f10, f1, f15 +fadd.d f10, f1, f20 +fadd.d f10, f1, f25 +fadd.d f10, f1, f31 +fadd.d f10, f5, f0 +fadd.d f10, f5, f1 +fadd.d f10, f5, f5 +fadd.d f10, f5, f10 +fadd.d f10, f5, f15 +fadd.d f10, f5, f20 +fadd.d f10, f5, f25 +fadd.d f10, f5, f31 +fadd.d f10, f10, f0 +fadd.d f10, f10, f1 +fadd.d f10, f10, f5 +fadd.d f10, f10, f10 +fadd.d f10, f10, f15 +fadd.d f10, f10, f20 +fadd.d f10, f10, f25 +fadd.d f10, f10, f31 +fadd.d f10, f15, f0 +fadd.d f10, f15, f1 +fadd.d f10, f15, f5 +fadd.d f10, f15, f10 +fadd.d f10, f15, f15 +fadd.d f10, f15, f20 +fadd.d f10, f15, f25 +fadd.d f10, f15, f31 +fadd.d f10, f20, f0 +fadd.d f10, f20, f1 +fadd.d f10, f20, f5 +fadd.d f10, f20, f10 +fadd.d f10, f20, f15 +fadd.d f10, f20, f20 +fadd.d f10, f20, f25 +fadd.d f10, f20, f31 +fadd.d f10, f25, f0 +fadd.d f10, f25, f1 +fadd.d f10, f25, f5 +fadd.d f10, f25, f10 +fadd.d f10, f25, f15 +fadd.d f10, f25, f20 +fadd.d f10, f25, f25 +fadd.d f10, f25, f31 +fadd.d f10, f31, f0 +fadd.d f10, f31, f1 +fadd.d f10, f31, f5 +fadd.d f10, f31, f10 +fadd.d f10, f31, f15 +fadd.d f10, f31, f20 +fadd.d f10, f31, f25 +fadd.d f10, f31, f31 +fadd.d f15, f0, f0 +fadd.d f15, f0, f1 +fadd.d f15, f0, f5 +fadd.d f15, f0, f10 +fadd.d f15, f0, f15 +fadd.d f15, f0, f20 +fadd.d f15, f0, f25 +fadd.d f15, f0, f31 +fadd.d f15, f1, f0 +fadd.d f15, f1, f1 +fadd.d f15, f1, f5 +fadd.d f15, f1, f10 +fadd.d f15, f1, f15 +fadd.d f15, f1, f20 +fadd.d f15, f1, f25 +fadd.d f15, f1, f31 +fadd.d f15, f5, f0 +fadd.d f15, f5, f1 +fadd.d f15, f5, f5 +fadd.d f15, f5, f10 +fadd.d f15, f5, f15 +fadd.d f15, f5, f20 +fadd.d f15, f5, f25 +fadd.d f15, f5, f31 +fadd.d f15, f10, f0 +fadd.d f15, f10, f1 +fadd.d f15, f10, f5 +fadd.d f15, f10, f10 +fadd.d f15, f10, f15 +fadd.d f15, f10, f20 +fadd.d f15, f10, f25 +fadd.d f15, f10, f31 +fadd.d f15, f15, f0 +fadd.d f15, f15, f1 +fadd.d f15, f15, f5 +fadd.d f15, f15, f10 +fadd.d f15, f15, f15 +fadd.d f15, f15, f20 +fadd.d f15, f15, f25 +fadd.d f15, f15, f31 +fadd.d f15, f20, f0 +fadd.d f15, f20, f1 +fadd.d f15, f20, f5 +fadd.d f15, f20, f10 +fadd.d f15, f20, f15 +fadd.d f15, f20, f20 +fadd.d f15, f20, f25 +fadd.d f15, f20, f31 +fadd.d f15, f25, f0 +fadd.d f15, f25, f1 +fadd.d f15, f25, f5 +fadd.d f15, f25, f10 +fadd.d f15, f25, f15 +fadd.d f15, f25, f20 +fadd.d f15, f25, f25 +fadd.d f15, f25, f31 +fadd.d f15, f31, f0 +fadd.d f15, f31, f1 +fadd.d f15, f31, f5 +fadd.d f15, f31, f10 +fadd.d f15, f31, f15 +fadd.d f15, f31, f20 +fadd.d f15, f31, f25 +fadd.d f15, f31, f31 +fadd.d f20, f0, f0 +fadd.d f20, f0, f1 +fadd.d f20, f0, f5 +fadd.d f20, f0, f10 +fadd.d f20, f0, f15 +fadd.d f20, f0, f20 +fadd.d f20, f0, f25 +fadd.d f20, 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f25, f25 +fadd.d f20, f25, f31 +fadd.d f20, f31, f0 +fadd.d f20, f31, f1 +fadd.d f20, f31, f5 +fadd.d f20, f31, f10 +fadd.d f20, f31, f15 +fadd.d f20, f31, f20 +fadd.d f20, f31, f25 +fadd.d f20, f31, f31 +fadd.d f25, f0, f0 +fadd.d f25, f0, f1 +fadd.d f25, f0, f5 +fadd.d f25, f0, f10 +fadd.d f25, f0, f15 +fadd.d f25, f0, f20 +fadd.d f25, f0, f25 +fadd.d f25, f0, f31 +fadd.d f25, f1, f0 +fadd.d f25, f1, f1 +fadd.d f25, f1, f5 +fadd.d f25, f1, f10 +fadd.d f25, f1, f15 +fadd.d f25, f1, f20 +fadd.d f25, f1, f25 +fadd.d f25, f1, f31 +fadd.d f25, f5, f0 +fadd.d f25, f5, f1 +fadd.d f25, f5, f5 +fadd.d f25, f5, f10 +fadd.d f25, f5, f15 +fadd.d f25, f5, f20 +fadd.d f25, f5, f25 +fadd.d f25, f5, f31 +fadd.d f25, f10, f0 +fadd.d f25, f10, f1 +fadd.d f25, f10, f5 +fadd.d f25, f10, f10 +fadd.d f25, f10, f15 +fadd.d f25, f10, f20 +fadd.d f25, f10, f25 +fadd.d f25, f10, f31 +fadd.d f25, f15, f0 +fadd.d f25, f15, f1 +fadd.d f25, f15, f5 +fadd.d f25, f15, f10 +fadd.d f25, f15, f15 +fadd.d f25, f15, f20 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+fadd.d f31, f5, f20 +fadd.d f31, f5, f25 +fadd.d f31, f5, f31 +fadd.d f31, f10, f0 +fadd.d f31, f10, f1 +fadd.d f31, f10, f5 +fadd.d f31, f10, f10 +fadd.d f31, f10, f15 +fadd.d f31, f10, f20 +fadd.d f31, f10, f25 +fadd.d f31, f10, f31 +fadd.d f31, f15, f0 +fadd.d f31, f15, f1 +fadd.d f31, f15, f5 +fadd.d f31, f15, f10 +fadd.d f31, f15, f15 +fadd.d f31, f15, f20 +fadd.d f31, f15, f25 +fadd.d f31, f15, f31 +fadd.d f31, f20, f0 +fadd.d f31, f20, f1 +fadd.d f31, f20, f5 +fadd.d f31, f20, f10 +fadd.d f31, f20, f15 +fadd.d f31, f20, f20 +fadd.d f31, f20, f25 +fadd.d f31, f20, f31 +fadd.d f31, f25, f0 +fadd.d f31, f25, f1 +fadd.d f31, f25, f5 +fadd.d f31, f25, f10 +fadd.d f31, f25, f15 +fadd.d f31, f25, f20 +fadd.d f31, f25, f25 +fadd.d f31, f25, f31 +fadd.d f31, f31, f0 +fadd.d f31, f31, f1 +fadd.d f31, f31, f5 +fadd.d f31, f31, f10 +fadd.d f31, f31, f15 +fadd.d f31, f31, f20 +fadd.d f31, f31, f25 +fadd.d f31, f31, f31 + diff --git a/tests/riscv/d-extension/fadd.d.bin b/tests/riscv/d-extension/fadd.d.bin new file mode 100644 index 0000000000000000000000000000000000000000..cc544a8285838429270ca36172d11e2a6af97d4a GIT binary patch literal 2048 zcmWmCafj7Q9LMoBYYbzUD-wyG$`y%3S1Xa|sT{)?#xPeT5?zr<^kB{t$+DKU?0ua- zKAiLYj300B&&AnUxH$Vu{*nLWkNkaparUqLIlnmQ5Bh`tpg-sj`h)&(>VyCHhS=$uGH;7w%u=R;vGx<-PotJ9+8;RqzLV0bjru@CAGUU%(ge zHGR`JebYC6(>HxP_4ph9hQHx&_#6I)zu^z~1O9+N;1Bo%{(wK=Z}=PjhQHx&_#6I) zzu^z~1O9+N;1Bo%{(wK=Z}=PjhQHx&_#6I)zu|BA8~%pB;cxgG{)WHZonJ)zj`khx zJKA@&?`YrAzN3A2eb;w=*LQu_cYQzg_TTNl+kdzJZvWl>yZv|jkM zyZv|j@AlvAzuSMe|8D=?{=5Bm{u956-^6d?H}RYJP5dT)hkodXe&~mO=!brsdj1Fh zga5(*;D7Kx_#gZy{uBR+|HOadKk=XVPy7%52mgcr!T;cY@IUw;{3res|B3&^f8sy! zpZHJw5B>-Lga5(*;D7Kx_#gZa{s;eq|H1#@fABx}AN*&2GryVN%x~s5^PBn2{7(JU zPyN(S{nStWJoWrf{wM#F|H=R4fAT;1&-`cpGyj?Y%zx%T^Pl;j{7?QT|C9g8|Kxx2 zKl#u6XZ|z)ng7gx=0EeF`Jenx{wM#F|H=R4fAT;1pZrh$C;yZG$^Ybk@;~`6{1$!- zzlGnzZ{fG_Tlii2rC<7`U;3qA`gQ90U;Hor7ypa@#sA`e@n85a{1^TU|Aqg;f8oFI zzxZGLFa8(*i~q&{;(zg9_%Hky{tN$w|H6Oazwp2KU;Hor7ypa@#sA`e@xS5~s-}lna}*m lmO1|93xD#3FZ{*UIsW1+fAN*C`mMD&{nnd)>rHRV_ye1)d~pB( literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fclass.d.disasm b/tests/riscv/d-extension/fclass.d.disasm new file mode 100644 index 0000000..90559c8 --- /dev/null +++ b/tests/riscv/d-extension/fclass.d.disasm @@ -0,0 +1,64 @@ +fclass.d zero, f0 +fclass.d zero, f1 +fclass.d zero, f5 +fclass.d zero, f10 +fclass.d zero, f15 +fclass.d zero, f20 +fclass.d zero, f25 +fclass.d zero, f31 +fclass.d ra, f0 +fclass.d ra, f1 +fclass.d ra, f5 +fclass.d ra, f10 +fclass.d ra, f15 +fclass.d ra, f20 +fclass.d ra, f25 +fclass.d ra, f31 +fclass.d t0, f0 +fclass.d t0, f1 +fclass.d t0, f5 +fclass.d t0, f10 +fclass.d t0, f15 +fclass.d t0, f20 +fclass.d t0, f25 +fclass.d t0, f31 +fclass.d a0, f0 +fclass.d a0, f1 +fclass.d a0, f5 +fclass.d a0, f10 +fclass.d a0, f15 +fclass.d a0, f20 +fclass.d a0, f25 +fclass.d a0, f31 +fclass.d a5, f0 +fclass.d a5, f1 +fclass.d a5, f5 +fclass.d a5, f10 +fclass.d a5, f15 +fclass.d a5, f20 +fclass.d a5, f25 +fclass.d a5, f31 +fclass.d s4, f0 +fclass.d s4, f1 +fclass.d s4, f5 +fclass.d s4, f10 +fclass.d s4, f15 +fclass.d s4, f20 +fclass.d s4, f25 +fclass.d s4, f31 +fclass.d s9, f0 +fclass.d s9, f1 +fclass.d s9, f5 +fclass.d s9, f10 +fclass.d s9, f15 +fclass.d s9, f20 +fclass.d s9, f25 +fclass.d s9, f31 +fclass.d t6, f0 +fclass.d t6, f1 +fclass.d t6, f5 +fclass.d t6, f10 +fclass.d t6, f15 +fclass.d t6, f20 +fclass.d t6, f25 +fclass.d t6, f31 diff --git a/tests/riscv/d-extension/fclass_d.asm b/tests/riscv/d-extension/fclass_d.asm new file mode 100644 index 0000000..b15bcb1 --- /dev/null +++ b/tests/riscv/d-extension/fclass_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fclass.d a0, f1 + diff --git a/tests/riscv/d-extension/fclass_d.bin b/tests/riscv/d-extension/fclass_d.bin new file mode 100644 index 0000000000000000000000000000000000000000..c91dc95fa841ea2d8698ae83971ce5835a29772e GIT binary patch literal 4 LcmWHZ%J2vP1MvaN literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fclass_d.disasm b/tests/riscv/d-extension/fclass_d.disasm new file mode 100644 index 0000000..665aa37 --- /dev/null +++ b/tests/riscv/d-extension/fclass_d.disasm @@ -0,0 +1 @@ +fclass.d a0, f1 diff --git a/tests/riscv/d-extension/fcvt.d.s.asm b/tests/riscv/d-extension/fcvt.d.s.asm new file mode 100644 index 0000000..a263c2f --- /dev/null +++ b/tests/riscv/d-extension/fcvt.d.s.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +fcvt.d.s f0, f0 +fcvt.d.s f0, f1 +fcvt.d.s f0, f5 +fcvt.d.s f0, f10 +fcvt.d.s f0, f15 +fcvt.d.s f0, f20 +fcvt.d.s f0, f25 +fcvt.d.s f0, f31 +fcvt.d.s f1, f0 +fcvt.d.s f1, f1 +fcvt.d.s f1, f5 +fcvt.d.s f1, f10 +fcvt.d.s f1, f15 +fcvt.d.s f1, f20 +fcvt.d.s f1, f25 +fcvt.d.s f1, f31 +fcvt.d.s f5, f0 +fcvt.d.s f5, f1 +fcvt.d.s f5, f5 +fcvt.d.s f5, f10 +fcvt.d.s f5, f15 +fcvt.d.s f5, f20 +fcvt.d.s f5, f25 +fcvt.d.s f5, f31 +fcvt.d.s f10, f0 +fcvt.d.s f10, f1 +fcvt.d.s f10, f5 +fcvt.d.s f10, f10 +fcvt.d.s f10, f15 +fcvt.d.s f10, f20 +fcvt.d.s f10, f25 +fcvt.d.s f10, f31 +fcvt.d.s f15, f0 +fcvt.d.s f15, f1 +fcvt.d.s f15, f5 +fcvt.d.s f15, f10 +fcvt.d.s f15, f15 +fcvt.d.s f15, f20 +fcvt.d.s f15, f25 +fcvt.d.s f15, f31 +fcvt.d.s f20, f0 +fcvt.d.s f20, f1 +fcvt.d.s f20, f5 +fcvt.d.s f20, f10 +fcvt.d.s f20, f15 +fcvt.d.s f20, f20 +fcvt.d.s f20, f25 +fcvt.d.s f20, f31 +fcvt.d.s f25, f0 +fcvt.d.s f25, f1 +fcvt.d.s f25, f5 +fcvt.d.s f25, f10 +fcvt.d.s f25, f15 +fcvt.d.s f25, f20 +fcvt.d.s f25, f25 +fcvt.d.s f25, f31 +fcvt.d.s f31, f0 +fcvt.d.s f31, f1 +fcvt.d.s f31, f5 +fcvt.d.s f31, f10 +fcvt.d.s f31, f15 +fcvt.d.s f31, f20 +fcvt.d.s f31, f25 +fcvt.d.s f31, f31 + diff --git a/tests/riscv/d-extension/fcvt.d.s.bin b/tests/riscv/d-extension/fcvt.d.s.bin new file mode 100644 index 0000000000000000000000000000000000000000..6dcad8131ff45e2e633f8da2e0ed084ba339b2c6 GIT binary patch literal 256 zcmWm6Q3gdJ6o%0w5{c&26wZXMNF>hSn$TT6{Px3V?e}@w`@0M6eWIJ(>=vu-=tn>L z(T{%gqo3P@*6;M7cRlD`@3p&W* b@R^-=eC8*g`N>bcXzNZd`qGQO^i}pBn{ae- literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fcvt.d.w.disasm b/tests/riscv/d-extension/fcvt.d.w.disasm new file mode 100644 index 0000000..68cabbc --- /dev/null +++ b/tests/riscv/d-extension/fcvt.d.w.disasm @@ -0,0 +1,64 @@ +fcvt.d.w f0, zero +fcvt.d.w f0, ra +fcvt.d.w f0, t0 +fcvt.d.w f0, a0 +fcvt.d.w f0, a5 +fcvt.d.w f0, s4 +fcvt.d.w f0, s9 +fcvt.d.w f0, t6 +fcvt.d.w f1, zero +fcvt.d.w f1, ra +fcvt.d.w f1, t0 +fcvt.d.w f1, a0 +fcvt.d.w f1, a5 +fcvt.d.w f1, s4 +fcvt.d.w f1, s9 +fcvt.d.w f1, t6 +fcvt.d.w f5, zero +fcvt.d.w f5, ra +fcvt.d.w f5, t0 +fcvt.d.w f5, a0 +fcvt.d.w f5, a5 +fcvt.d.w f5, s4 +fcvt.d.w f5, s9 +fcvt.d.w f5, t6 +fcvt.d.w f10, zero +fcvt.d.w f10, ra +fcvt.d.w f10, t0 +fcvt.d.w f10, a0 +fcvt.d.w f10, a5 +fcvt.d.w f10, s4 +fcvt.d.w f10, s9 +fcvt.d.w f10, t6 +fcvt.d.w f15, zero +fcvt.d.w f15, ra +fcvt.d.w f15, t0 +fcvt.d.w f15, a0 +fcvt.d.w f15, a5 +fcvt.d.w f15, s4 +fcvt.d.w f15, s9 +fcvt.d.w f15, t6 +fcvt.d.w f20, zero +fcvt.d.w f20, ra +fcvt.d.w f20, t0 +fcvt.d.w f20, a0 +fcvt.d.w f20, a5 +fcvt.d.w f20, s4 +fcvt.d.w f20, s9 +fcvt.d.w f20, t6 +fcvt.d.w f25, zero +fcvt.d.w f25, ra +fcvt.d.w f25, t0 +fcvt.d.w f25, a0 +fcvt.d.w f25, a5 +fcvt.d.w f25, s4 +fcvt.d.w f25, s9 +fcvt.d.w f25, t6 +fcvt.d.w f31, zero +fcvt.d.w f31, ra +fcvt.d.w f31, t0 +fcvt.d.w f31, a0 +fcvt.d.w f31, a5 +fcvt.d.w f31, s4 +fcvt.d.w f31, s9 +fcvt.d.w f31, t6 diff --git a/tests/riscv/d-extension/fcvt.d.wu.asm b/tests/riscv/d-extension/fcvt.d.wu.asm new file mode 100644 index 0000000..8dde20e --- /dev/null +++ b/tests/riscv/d-extension/fcvt.d.wu.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +fcvt.d.wu f0, zero +fcvt.d.wu f0, ra +fcvt.d.wu f0, t0 +fcvt.d.wu f0, a0 +fcvt.d.wu f0, a5 +fcvt.d.wu f0, s4 +fcvt.d.wu f0, s9 +fcvt.d.wu f0, t6 +fcvt.d.wu f1, zero +fcvt.d.wu f1, ra +fcvt.d.wu f1, t0 +fcvt.d.wu f1, a0 +fcvt.d.wu f1, a5 +fcvt.d.wu f1, s4 +fcvt.d.wu f1, s9 +fcvt.d.wu f1, t6 +fcvt.d.wu f5, zero +fcvt.d.wu f5, ra +fcvt.d.wu f5, t0 +fcvt.d.wu f5, a0 +fcvt.d.wu f5, a5 +fcvt.d.wu f5, s4 +fcvt.d.wu f5, s9 +fcvt.d.wu f5, t6 +fcvt.d.wu f10, zero +fcvt.d.wu f10, ra +fcvt.d.wu f10, t0 +fcvt.d.wu f10, a0 +fcvt.d.wu f10, a5 +fcvt.d.wu f10, s4 +fcvt.d.wu f10, s9 +fcvt.d.wu f10, t6 +fcvt.d.wu f15, zero +fcvt.d.wu f15, ra +fcvt.d.wu f15, t0 +fcvt.d.wu f15, a0 +fcvt.d.wu f15, a5 +fcvt.d.wu f15, s4 +fcvt.d.wu f15, s9 +fcvt.d.wu f15, t6 +fcvt.d.wu f20, zero +fcvt.d.wu f20, ra +fcvt.d.wu f20, t0 +fcvt.d.wu f20, a0 +fcvt.d.wu f20, a5 +fcvt.d.wu f20, s4 +fcvt.d.wu f20, s9 +fcvt.d.wu f20, t6 +fcvt.d.wu f25, zero +fcvt.d.wu f25, ra +fcvt.d.wu f25, t0 +fcvt.d.wu f25, a0 +fcvt.d.wu f25, a5 +fcvt.d.wu f25, s4 +fcvt.d.wu f25, s9 +fcvt.d.wu f25, t6 +fcvt.d.wu f31, zero +fcvt.d.wu f31, ra +fcvt.d.wu f31, t0 +fcvt.d.wu f31, a0 +fcvt.d.wu f31, a5 +fcvt.d.wu f31, s4 +fcvt.d.wu f31, s9 +fcvt.d.wu f31, t6 + diff --git a/tests/riscv/d-extension/fcvt.d.wu.bin b/tests/riscv/d-extension/fcvt.d.wu.bin new file mode 100644 index 0000000000000000000000000000000000000000..366908762a8ad1cc8d3b61d006efbbffd3c0092c GIT binary patch literal 256 zcmWm6Q3eAs6o%0%RjSMw#xRCiR5n&2LWJxo*-%d&e)r*XZde~Z{N|oLtS|TNe%!Au zedt3U`p}0y^r4U0H!aTTn;!K|k9u5s*!@m({_p-L|9AhB|A{}?JjWk=<_|venLpVw j$De%RPrmSlzt}p*Uwq{+zVcPSwKk{Uded*c>22wMpN@EO literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fcvt.d.wu.disasm b/tests/riscv/d-extension/fcvt.d.wu.disasm new file mode 100644 index 0000000..7362c3d --- /dev/null +++ b/tests/riscv/d-extension/fcvt.d.wu.disasm @@ -0,0 +1,64 @@ +fcvt.d.wu f0, zero +fcvt.d.wu f0, ra +fcvt.d.wu f0, t0 +fcvt.d.wu f0, a0 +fcvt.d.wu f0, a5 +fcvt.d.wu f0, s4 +fcvt.d.wu f0, s9 +fcvt.d.wu f0, t6 +fcvt.d.wu f1, zero +fcvt.d.wu f1, ra +fcvt.d.wu f1, t0 +fcvt.d.wu f1, a0 +fcvt.d.wu f1, a5 +fcvt.d.wu f1, s4 +fcvt.d.wu f1, s9 +fcvt.d.wu f1, t6 +fcvt.d.wu f5, zero +fcvt.d.wu f5, ra +fcvt.d.wu f5, t0 +fcvt.d.wu f5, a0 +fcvt.d.wu f5, a5 +fcvt.d.wu f5, s4 +fcvt.d.wu f5, s9 +fcvt.d.wu f5, t6 +fcvt.d.wu f10, zero +fcvt.d.wu f10, ra +fcvt.d.wu f10, t0 +fcvt.d.wu f10, a0 +fcvt.d.wu f10, a5 +fcvt.d.wu f10, s4 +fcvt.d.wu f10, s9 +fcvt.d.wu f10, t6 +fcvt.d.wu f15, zero +fcvt.d.wu f15, ra +fcvt.d.wu f15, t0 +fcvt.d.wu f15, a0 +fcvt.d.wu f15, a5 +fcvt.d.wu f15, s4 +fcvt.d.wu f15, s9 +fcvt.d.wu f15, t6 +fcvt.d.wu f20, zero +fcvt.d.wu f20, ra +fcvt.d.wu f20, t0 +fcvt.d.wu f20, a0 +fcvt.d.wu f20, a5 +fcvt.d.wu f20, s4 +fcvt.d.wu f20, s9 +fcvt.d.wu f20, t6 +fcvt.d.wu f25, zero +fcvt.d.wu f25, ra +fcvt.d.wu f25, t0 +fcvt.d.wu f25, a0 +fcvt.d.wu f25, a5 +fcvt.d.wu f25, s4 +fcvt.d.wu f25, s9 +fcvt.d.wu f25, t6 +fcvt.d.wu f31, zero +fcvt.d.wu f31, ra +fcvt.d.wu f31, t0 +fcvt.d.wu f31, a0 +fcvt.d.wu f31, a5 +fcvt.d.wu f31, s4 +fcvt.d.wu f31, s9 +fcvt.d.wu f31, t6 diff --git a/tests/riscv/d-extension/fcvt.s.d.asm b/tests/riscv/d-extension/fcvt.s.d.asm new file mode 100644 index 0000000..cf425c5 --- /dev/null +++ b/tests/riscv/d-extension/fcvt.s.d.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +fcvt.s.d f0, f0 +fcvt.s.d f0, f1 +fcvt.s.d f0, f5 +fcvt.s.d f0, f10 +fcvt.s.d f0, f15 +fcvt.s.d f0, f20 +fcvt.s.d f0, f25 +fcvt.s.d f0, f31 +fcvt.s.d f1, f0 +fcvt.s.d f1, f1 +fcvt.s.d f1, f5 +fcvt.s.d f1, f10 +fcvt.s.d f1, f15 +fcvt.s.d f1, f20 +fcvt.s.d f1, f25 +fcvt.s.d f1, f31 +fcvt.s.d f5, f0 +fcvt.s.d f5, f1 +fcvt.s.d f5, f5 +fcvt.s.d f5, f10 +fcvt.s.d f5, f15 +fcvt.s.d f5, f20 +fcvt.s.d f5, f25 +fcvt.s.d f5, f31 +fcvt.s.d f10, f0 +fcvt.s.d f10, f1 +fcvt.s.d f10, f5 +fcvt.s.d f10, f10 +fcvt.s.d f10, f15 +fcvt.s.d f10, f20 +fcvt.s.d f10, f25 +fcvt.s.d f10, f31 +fcvt.s.d f15, f0 +fcvt.s.d f15, f1 +fcvt.s.d f15, f5 +fcvt.s.d f15, f10 +fcvt.s.d f15, f15 +fcvt.s.d f15, f20 +fcvt.s.d f15, f25 +fcvt.s.d f15, f31 +fcvt.s.d f20, f0 +fcvt.s.d f20, f1 +fcvt.s.d f20, f5 +fcvt.s.d f20, f10 +fcvt.s.d f20, f15 +fcvt.s.d f20, f20 +fcvt.s.d f20, f25 +fcvt.s.d f20, f31 +fcvt.s.d f25, f0 +fcvt.s.d f25, f1 +fcvt.s.d f25, f5 +fcvt.s.d f25, f10 +fcvt.s.d f25, f15 +fcvt.s.d f25, f20 +fcvt.s.d f25, f25 +fcvt.s.d f25, f31 +fcvt.s.d f31, f0 +fcvt.s.d f31, f1 +fcvt.s.d f31, f5 +fcvt.s.d f31, f10 +fcvt.s.d f31, f15 +fcvt.s.d f31, f20 +fcvt.s.d f31, f25 +fcvt.s.d f31, f31 + diff --git a/tests/riscv/d-extension/fcvt.s.d.bin b/tests/riscv/d-extension/fcvt.s.d.bin new file mode 100644 index 0000000000000000000000000000000000000000..2332f157041a03f22f1e6745e391095613077ece GIT binary patch literal 256 zcmWm6Q3gdJ6o%0w5{ahN9L|KUNF>hSn$TT6{Px3V?e}@w`@0M6eWIJ(>=vu-=tn>L z(T{%gqo3P@*6;M7cRlD`@3pw(T{%g zqaXd~M?bd*t={QDuX@m{Ud#TX-|f!-=zsG+`rrI-{LA(`{^dLW@}2K|V#ghy_`xTB c@Pp6nyyG)J`OHs#>P1_3deN6&^rf$||DRHDaR2}S literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fcvt.w.d.disasm b/tests/riscv/d-extension/fcvt.w.d.disasm new file mode 100644 index 0000000..808d9e0 --- /dev/null +++ b/tests/riscv/d-extension/fcvt.w.d.disasm @@ -0,0 +1,64 @@ +fcvt.w.d zero, f0 +fcvt.w.d zero, f1 +fcvt.w.d zero, f5 +fcvt.w.d zero, f10 +fcvt.w.d zero, f15 +fcvt.w.d zero, f20 +fcvt.w.d zero, f25 +fcvt.w.d zero, f31 +fcvt.w.d ra, f0 +fcvt.w.d ra, f1 +fcvt.w.d ra, f5 +fcvt.w.d ra, f10 +fcvt.w.d ra, f15 +fcvt.w.d ra, f20 +fcvt.w.d ra, f25 +fcvt.w.d ra, f31 +fcvt.w.d t0, f0 +fcvt.w.d t0, f1 +fcvt.w.d t0, f5 +fcvt.w.d t0, f10 +fcvt.w.d t0, f15 +fcvt.w.d t0, f20 +fcvt.w.d t0, f25 +fcvt.w.d t0, f31 +fcvt.w.d a0, f0 +fcvt.w.d a0, f1 +fcvt.w.d a0, f5 +fcvt.w.d a0, f10 +fcvt.w.d a0, f15 +fcvt.w.d a0, f20 +fcvt.w.d a0, f25 +fcvt.w.d a0, f31 +fcvt.w.d a5, f0 +fcvt.w.d a5, f1 +fcvt.w.d a5, f5 +fcvt.w.d a5, f10 +fcvt.w.d a5, f15 +fcvt.w.d a5, f20 +fcvt.w.d a5, f25 +fcvt.w.d a5, f31 +fcvt.w.d s4, f0 +fcvt.w.d s4, f1 +fcvt.w.d s4, f5 +fcvt.w.d s4, f10 +fcvt.w.d s4, f15 +fcvt.w.d s4, f20 +fcvt.w.d s4, f25 +fcvt.w.d s4, f31 +fcvt.w.d s9, f0 +fcvt.w.d s9, f1 +fcvt.w.d s9, f5 +fcvt.w.d s9, f10 +fcvt.w.d s9, f15 +fcvt.w.d s9, f20 +fcvt.w.d s9, f25 +fcvt.w.d s9, f31 +fcvt.w.d t6, f0 +fcvt.w.d t6, f1 +fcvt.w.d t6, f5 +fcvt.w.d t6, f10 +fcvt.w.d t6, f15 +fcvt.w.d t6, f20 +fcvt.w.d t6, f25 +fcvt.w.d t6, f31 diff --git a/tests/riscv/d-extension/fcvt.wu.d.asm b/tests/riscv/d-extension/fcvt.wu.d.asm new file mode 100644 index 0000000..50eadde --- /dev/null +++ b/tests/riscv/d-extension/fcvt.wu.d.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +fcvt.wu.d zero, f0 +fcvt.wu.d zero, f1 +fcvt.wu.d zero, f5 +fcvt.wu.d zero, f10 +fcvt.wu.d zero, f15 +fcvt.wu.d zero, f20 +fcvt.wu.d zero, f25 +fcvt.wu.d zero, f31 +fcvt.wu.d ra, f0 +fcvt.wu.d ra, f1 +fcvt.wu.d ra, f5 +fcvt.wu.d ra, f10 +fcvt.wu.d ra, f15 +fcvt.wu.d ra, f20 +fcvt.wu.d ra, f25 +fcvt.wu.d ra, f31 +fcvt.wu.d t0, f0 +fcvt.wu.d t0, f1 +fcvt.wu.d t0, f5 +fcvt.wu.d t0, f10 +fcvt.wu.d t0, f15 +fcvt.wu.d t0, f20 +fcvt.wu.d t0, f25 +fcvt.wu.d t0, f31 +fcvt.wu.d a0, f0 +fcvt.wu.d a0, f1 +fcvt.wu.d a0, f5 +fcvt.wu.d a0, f10 +fcvt.wu.d a0, f15 +fcvt.wu.d a0, f20 +fcvt.wu.d a0, f25 +fcvt.wu.d a0, f31 +fcvt.wu.d a5, f0 +fcvt.wu.d a5, f1 +fcvt.wu.d a5, f5 +fcvt.wu.d a5, f10 +fcvt.wu.d a5, f15 +fcvt.wu.d a5, f20 +fcvt.wu.d a5, f25 +fcvt.wu.d a5, f31 +fcvt.wu.d s4, f0 +fcvt.wu.d s4, f1 +fcvt.wu.d s4, f5 +fcvt.wu.d s4, f10 +fcvt.wu.d s4, f15 +fcvt.wu.d s4, f20 +fcvt.wu.d s4, f25 +fcvt.wu.d s4, f31 +fcvt.wu.d s9, f0 +fcvt.wu.d s9, f1 +fcvt.wu.d s9, f5 +fcvt.wu.d s9, f10 +fcvt.wu.d s9, f15 +fcvt.wu.d s9, f20 +fcvt.wu.d s9, f25 +fcvt.wu.d s9, f31 +fcvt.wu.d t6, f0 +fcvt.wu.d t6, f1 +fcvt.wu.d t6, f5 +fcvt.wu.d t6, f10 +fcvt.wu.d t6, f15 +fcvt.wu.d t6, f20 +fcvt.wu.d t6, f25 +fcvt.wu.d t6, f31 + diff --git a/tests/riscv/d-extension/fcvt.wu.d.bin b/tests/riscv/d-extension/fcvt.wu.d.bin new file mode 100644 index 0000000000000000000000000000000000000000..e4dd60fb8624c0e9705325d4d0ac070923d5eed8 GIT binary patch literal 256 zcmWm6Q3eAs6o%0%RjSMw#xRCiR5n&2LWJxkTgZlb^6|uSmZ};PV zZRtZF`p}0y^q~)Z%)V)HPT%yXZ+g_@(!=g|n)846Kl#7=pZrh!!R9&s;4^>lna}*m lmO1|93xD#3FZ{*UIsW1+fAN*C`mMD&{nnd)>rHP<{{y3Nba4Ox literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fcvt.wu.d.disasm b/tests/riscv/d-extension/fcvt.wu.d.disasm new file mode 100644 index 0000000..cf6d855 --- /dev/null +++ b/tests/riscv/d-extension/fcvt.wu.d.disasm @@ -0,0 +1,64 @@ +fcvt.wu.d zero, f0 +fcvt.wu.d zero, f1 +fcvt.wu.d zero, f5 +fcvt.wu.d zero, f10 +fcvt.wu.d zero, f15 +fcvt.wu.d zero, f20 +fcvt.wu.d zero, f25 +fcvt.wu.d zero, f31 +fcvt.wu.d ra, f0 +fcvt.wu.d ra, f1 +fcvt.wu.d ra, f5 +fcvt.wu.d ra, f10 +fcvt.wu.d ra, f15 +fcvt.wu.d ra, f20 +fcvt.wu.d ra, f25 +fcvt.wu.d ra, f31 +fcvt.wu.d t0, f0 +fcvt.wu.d t0, f1 +fcvt.wu.d t0, f5 +fcvt.wu.d t0, f10 +fcvt.wu.d t0, f15 +fcvt.wu.d t0, f20 +fcvt.wu.d t0, f25 +fcvt.wu.d t0, f31 +fcvt.wu.d a0, f0 +fcvt.wu.d a0, f1 +fcvt.wu.d a0, f5 +fcvt.wu.d a0, f10 +fcvt.wu.d a0, f15 +fcvt.wu.d a0, f20 +fcvt.wu.d a0, f25 +fcvt.wu.d a0, f31 +fcvt.wu.d a5, f0 +fcvt.wu.d a5, f1 +fcvt.wu.d a5, f5 +fcvt.wu.d a5, f10 +fcvt.wu.d a5, f15 +fcvt.wu.d a5, f20 +fcvt.wu.d a5, f25 +fcvt.wu.d a5, f31 +fcvt.wu.d s4, f0 +fcvt.wu.d s4, f1 +fcvt.wu.d s4, f5 +fcvt.wu.d s4, f10 +fcvt.wu.d s4, f15 +fcvt.wu.d s4, f20 +fcvt.wu.d s4, f25 +fcvt.wu.d s4, f31 +fcvt.wu.d s9, f0 +fcvt.wu.d s9, f1 +fcvt.wu.d s9, f5 +fcvt.wu.d s9, f10 +fcvt.wu.d s9, f15 +fcvt.wu.d s9, f20 +fcvt.wu.d s9, f25 +fcvt.wu.d s9, f31 +fcvt.wu.d t6, f0 +fcvt.wu.d t6, f1 +fcvt.wu.d t6, f5 +fcvt.wu.d t6, f10 +fcvt.wu.d t6, f15 +fcvt.wu.d t6, f20 +fcvt.wu.d t6, f25 +fcvt.wu.d t6, f31 diff --git a/tests/riscv/d-extension/fcvt_d_s.asm b/tests/riscv/d-extension/fcvt_d_s.asm new file mode 100644 index 0000000..9259193 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_d_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.d.s f0, f1 + diff --git a/tests/riscv/d-extension/fcvt_d_s.bin b/tests/riscv/d-extension/fcvt_d_s.bin new file mode 100644 index 0000000000000000000000000000000000000000..057219dc3352902c8f0b0e0ddba4c0a2bb6dfb46 GIT binary patch literal 4 LcmWG;U~mEe0}=ri literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fcvt_d_s.disasm b/tests/riscv/d-extension/fcvt_d_s.disasm new file mode 100644 index 0000000..8fe9ab9 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_d_s.disasm @@ -0,0 +1 @@ +fcvt.d.s f0, f1 diff --git a/tests/riscv/d-extension/fcvt_d_w.asm b/tests/riscv/d-extension/fcvt_d_w.asm new file mode 100644 index 0000000..7e8eec6 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_d_w.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.d.w f0, a1 + diff --git a/tests/riscv/d-extension/fcvt_d_w.bin b/tests/riscv/d-extension/fcvt_d_w.bin new file mode 100644 index 0000000..a06e550 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_d_w.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/d-extension/fcvt_d_w.disasm b/tests/riscv/d-extension/fcvt_d_w.disasm new file mode 100644 index 0000000..7a76997 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_d_w.disasm @@ -0,0 +1 @@ +fcvt.d.w f0, a1 diff --git a/tests/riscv/d-extension/fcvt_d_wu.asm b/tests/riscv/d-extension/fcvt_d_wu.asm new file mode 100644 index 0000000..32715f4 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_d_wu.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.d.wu f0, a1 + diff --git a/tests/riscv/d-extension/fcvt_d_wu.bin b/tests/riscv/d-extension/fcvt_d_wu.bin new file mode 100644 index 0000000..d62ae73 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_d_wu.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/d-extension/fcvt_d_wu.disasm b/tests/riscv/d-extension/fcvt_d_wu.disasm new file mode 100644 index 0000000..6928e39 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_d_wu.disasm @@ -0,0 +1 @@ +fcvt.d.wu f0, a1 diff --git a/tests/riscv/d-extension/fcvt_s_d.asm b/tests/riscv/d-extension/fcvt_s_d.asm new file mode 100644 index 0000000..a6ce522 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_s_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.s.d f0, f1 + diff --git a/tests/riscv/d-extension/fcvt_s_d.bin b/tests/riscv/d-extension/fcvt_s_d.bin new file mode 100644 index 0000000000000000000000000000000000000000..d76fe4bcc634bc8bc8d22de04e49813f36647795 GIT binary patch literal 4 LcmWG;U~m8c0}ufe literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fcvt_s_d.disasm b/tests/riscv/d-extension/fcvt_s_d.disasm new file mode 100644 index 0000000..1ed357d --- /dev/null +++ b/tests/riscv/d-extension/fcvt_s_d.disasm @@ -0,0 +1 @@ +fcvt.s.d f0, f1 diff --git a/tests/riscv/d-extension/fcvt_w_d.asm b/tests/riscv/d-extension/fcvt_w_d.asm new file mode 100644 index 0000000..ca7128a --- /dev/null +++ b/tests/riscv/d-extension/fcvt_w_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.w.d a0, f1 + diff --git a/tests/riscv/d-extension/fcvt_w_d.bin b/tests/riscv/d-extension/fcvt_w_d.bin new file mode 100644 index 0000000000000000000000000000000000000000..416766f63fc565d10112212de2c23cfe4c52d8c3 GIT binary patch literal 4 LcmWG;WjF)?1EB$% literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fcvt_w_d.disasm b/tests/riscv/d-extension/fcvt_w_d.disasm new file mode 100644 index 0000000..2a40918 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_w_d.disasm @@ -0,0 +1 @@ +fcvt.w.d a0, f1 diff --git a/tests/riscv/d-extension/fcvt_wu_d.asm b/tests/riscv/d-extension/fcvt_wu_d.asm new file mode 100644 index 0000000..f964072 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_wu_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.wu.d a0, f1 + diff --git a/tests/riscv/d-extension/fcvt_wu_d.bin b/tests/riscv/d-extension/fcvt_wu_d.bin new file mode 100644 index 0000000000000000000000000000000000000000..793934545779518f7a9ad4712ea512a6d713a4f4 GIT binary patch literal 4 LcmWHZ%5Vq(1JMDi literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fcvt_wu_d.disasm b/tests/riscv/d-extension/fcvt_wu_d.disasm new file mode 100644 index 0000000..66fd187 --- /dev/null +++ b/tests/riscv/d-extension/fcvt_wu_d.disasm @@ -0,0 +1 @@ +fcvt.wu.d a0, f1 diff --git a/tests/riscv/d-extension/fdiv.d.asm b/tests/riscv/d-extension/fdiv.d.asm new file mode 100644 index 0000000..7644c80 --- /dev/null +++ b/tests/riscv/d-extension/fdiv.d.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fdiv.d f0, f0, f0 +fdiv.d f0, f0, f1 +fdiv.d f0, f0, f5 +fdiv.d f0, f0, f10 +fdiv.d f0, f0, f15 +fdiv.d f0, f0, f20 +fdiv.d f0, f0, f25 +fdiv.d f0, f0, f31 +fdiv.d f0, f1, f0 +fdiv.d f0, f1, f1 +fdiv.d f0, f1, f5 +fdiv.d f0, f1, f10 +fdiv.d f0, f1, f15 +fdiv.d f0, f1, f20 +fdiv.d f0, f1, f25 +fdiv.d f0, f1, f31 +fdiv.d f0, f5, f0 +fdiv.d f0, f5, f1 +fdiv.d f0, f5, f5 +fdiv.d f0, f5, f10 +fdiv.d f0, f5, f15 +fdiv.d f0, f5, f20 +fdiv.d f0, f5, f25 +fdiv.d f0, f5, f31 +fdiv.d f0, f10, f0 +fdiv.d f0, f10, f1 +fdiv.d f0, f10, f5 +fdiv.d f0, f10, f10 +fdiv.d f0, f10, f15 +fdiv.d f0, f10, f20 +fdiv.d f0, f10, f25 +fdiv.d f0, f10, f31 +fdiv.d f0, f15, f0 +fdiv.d f0, f15, f1 +fdiv.d f0, f15, f5 +fdiv.d f0, f15, f10 +fdiv.d f0, f15, f15 +fdiv.d f0, f15, f20 +fdiv.d f0, f15, f25 +fdiv.d f0, f15, f31 +fdiv.d f0, f20, f0 +fdiv.d f0, f20, f1 +fdiv.d f0, f20, f5 +fdiv.d f0, f20, f10 +fdiv.d f0, f20, f15 +fdiv.d f0, f20, f20 +fdiv.d f0, f20, f25 +fdiv.d f0, f20, f31 +fdiv.d f0, f25, f0 +fdiv.d f0, f25, f1 +fdiv.d f0, f25, f5 +fdiv.d f0, f25, f10 +fdiv.d f0, f25, f15 +fdiv.d f0, f25, f20 +fdiv.d f0, f25, f25 +fdiv.d f0, f25, f31 +fdiv.d f0, f31, f0 +fdiv.d f0, f31, f1 +fdiv.d f0, f31, f5 +fdiv.d f0, f31, f10 +fdiv.d f0, f31, f15 +fdiv.d f0, f31, f20 +fdiv.d f0, f31, f25 +fdiv.d f0, f31, f31 +fdiv.d f1, f0, f0 +fdiv.d f1, f0, f1 +fdiv.d f1, f0, f5 +fdiv.d f1, f0, f10 +fdiv.d f1, f0, f15 +fdiv.d f1, f0, f20 +fdiv.d f1, f0, f25 +fdiv.d f1, f0, f31 +fdiv.d f1, f1, f0 +fdiv.d f1, f1, f1 +fdiv.d f1, f1, f5 +fdiv.d f1, f1, f10 +fdiv.d f1, f1, f15 +fdiv.d f1, f1, f20 +fdiv.d f1, f1, f25 +fdiv.d f1, f1, f31 +fdiv.d f1, f5, f0 +fdiv.d f1, f5, f1 +fdiv.d f1, f5, f5 +fdiv.d f1, f5, f10 +fdiv.d f1, f5, f15 +fdiv.d f1, f5, f20 +fdiv.d f1, f5, f25 +fdiv.d f1, f5, f31 +fdiv.d f1, f10, f0 +fdiv.d f1, f10, f1 +fdiv.d f1, f10, f5 +fdiv.d f1, f10, f10 +fdiv.d f1, f10, f15 +fdiv.d f1, f10, f20 +fdiv.d f1, f10, f25 +fdiv.d f1, f10, f31 +fdiv.d f1, f15, f0 +fdiv.d f1, f15, f1 +fdiv.d f1, f15, f5 +fdiv.d f1, f15, f10 +fdiv.d f1, f15, f15 +fdiv.d f1, f15, f20 +fdiv.d f1, f15, f25 +fdiv.d f1, f15, f31 +fdiv.d f1, f20, f0 +fdiv.d f1, f20, f1 +fdiv.d f1, f20, f5 +fdiv.d f1, f20, f10 +fdiv.d f1, f20, f15 +fdiv.d f1, f20, f20 +fdiv.d f1, f20, f25 +fdiv.d f1, f20, f31 +fdiv.d f1, f25, f0 +fdiv.d f1, f25, f1 +fdiv.d f1, f25, f5 +fdiv.d f1, f25, f10 +fdiv.d f1, f25, f15 +fdiv.d f1, f25, f20 +fdiv.d f1, f25, f25 +fdiv.d f1, f25, f31 +fdiv.d f1, f31, f0 +fdiv.d f1, f31, f1 +fdiv.d f1, f31, f5 +fdiv.d f1, f31, f10 +fdiv.d f1, f31, f15 +fdiv.d f1, f31, f20 +fdiv.d f1, f31, f25 +fdiv.d f1, f31, f31 +fdiv.d f5, f0, f0 +fdiv.d f5, f0, f1 +fdiv.d f5, f0, f5 +fdiv.d f5, f0, f10 +fdiv.d f5, f0, f15 +fdiv.d f5, f0, f20 +fdiv.d f5, f0, f25 +fdiv.d f5, f0, f31 +fdiv.d f5, f1, f0 +fdiv.d f5, f1, f1 +fdiv.d f5, f1, f5 +fdiv.d f5, f1, f10 +fdiv.d f5, f1, f15 +fdiv.d f5, f1, f20 +fdiv.d f5, f1, f25 +fdiv.d f5, f1, f31 +fdiv.d f5, f5, f0 +fdiv.d f5, f5, f1 +fdiv.d f5, f5, f5 +fdiv.d f5, f5, f10 +fdiv.d f5, f5, f15 +fdiv.d f5, f5, f20 +fdiv.d f5, f5, f25 +fdiv.d f5, f5, f31 +fdiv.d f5, f10, f0 +fdiv.d f5, f10, f1 +fdiv.d f5, f10, f5 +fdiv.d f5, f10, f10 +fdiv.d f5, f10, f15 +fdiv.d f5, f10, f20 +fdiv.d f5, f10, f25 +fdiv.d f5, f10, f31 +fdiv.d f5, f15, f0 +fdiv.d f5, f15, f1 +fdiv.d f5, f15, f5 +fdiv.d f5, f15, f10 +fdiv.d f5, f15, f15 +fdiv.d f5, f15, f20 +fdiv.d f5, f15, f25 +fdiv.d f5, f15, f31 +fdiv.d f5, f20, f0 +fdiv.d f5, f20, f1 +fdiv.d f5, f20, f5 +fdiv.d f5, f20, f10 +fdiv.d f5, f20, f15 +fdiv.d f5, f20, f20 +fdiv.d f5, f20, f25 +fdiv.d f5, f20, f31 +fdiv.d f5, f25, f0 +fdiv.d f5, f25, f1 +fdiv.d f5, f25, f5 +fdiv.d f5, f25, f10 +fdiv.d f5, f25, f15 +fdiv.d f5, f25, f20 +fdiv.d f5, f25, f25 +fdiv.d f5, f25, f31 +fdiv.d f5, f31, f0 +fdiv.d f5, f31, f1 +fdiv.d f5, f31, f5 +fdiv.d f5, f31, f10 +fdiv.d f5, f31, f15 +fdiv.d f5, f31, f20 +fdiv.d f5, f31, f25 +fdiv.d f5, f31, f31 +fdiv.d f10, f0, f0 +fdiv.d f10, f0, f1 +fdiv.d f10, f0, f5 +fdiv.d f10, f0, f10 +fdiv.d f10, f0, f15 +fdiv.d f10, f0, f20 +fdiv.d f10, f0, f25 +fdiv.d f10, f0, f31 +fdiv.d f10, f1, f0 +fdiv.d f10, f1, f1 +fdiv.d f10, f1, f5 +fdiv.d f10, f1, f10 +fdiv.d f10, f1, f15 +fdiv.d f10, f1, f20 +fdiv.d f10, f1, f25 +fdiv.d f10, f1, f31 +fdiv.d f10, f5, f0 +fdiv.d f10, f5, f1 +fdiv.d f10, f5, f5 +fdiv.d f10, f5, f10 +fdiv.d f10, f5, f15 +fdiv.d f10, f5, f20 +fdiv.d f10, f5, f25 +fdiv.d f10, f5, f31 +fdiv.d f10, f10, f0 +fdiv.d f10, f10, f1 +fdiv.d f10, f10, f5 +fdiv.d f10, f10, f10 +fdiv.d f10, f10, f15 +fdiv.d f10, f10, f20 +fdiv.d f10, f10, f25 +fdiv.d f10, f10, f31 +fdiv.d f10, f15, f0 +fdiv.d f10, f15, f1 +fdiv.d f10, f15, f5 +fdiv.d f10, f15, f10 +fdiv.d f10, f15, f15 +fdiv.d f10, f15, f20 +fdiv.d f10, f15, f25 +fdiv.d f10, f15, f31 +fdiv.d f10, f20, f0 +fdiv.d f10, f20, f1 +fdiv.d f10, f20, f5 +fdiv.d f10, f20, f10 +fdiv.d f10, f20, f15 +fdiv.d f10, f20, f20 +fdiv.d f10, f20, f25 +fdiv.d f10, f20, f31 +fdiv.d f10, f25, f0 +fdiv.d f10, f25, f1 +fdiv.d f10, f25, f5 +fdiv.d f10, f25, f10 +fdiv.d f10, f25, f15 +fdiv.d f10, f25, f20 +fdiv.d f10, f25, f25 +fdiv.d f10, f25, f31 +fdiv.d f10, f31, f0 +fdiv.d f10, f31, f1 +fdiv.d f10, f31, f5 +fdiv.d f10, f31, f10 +fdiv.d f10, f31, f15 +fdiv.d f10, f31, f20 +fdiv.d f10, f31, f25 +fdiv.d f10, f31, f31 +fdiv.d f15, f0, f0 +fdiv.d f15, f0, f1 +fdiv.d f15, f0, f5 +fdiv.d f15, f0, f10 +fdiv.d f15, f0, f15 +fdiv.d f15, f0, f20 +fdiv.d f15, f0, f25 +fdiv.d f15, f0, f31 +fdiv.d f15, f1, f0 +fdiv.d f15, f1, f1 +fdiv.d f15, f1, f5 +fdiv.d f15, f1, f10 +fdiv.d f15, f1, f15 +fdiv.d f15, f1, f20 +fdiv.d f15, f1, f25 +fdiv.d f15, f1, f31 +fdiv.d f15, f5, f0 +fdiv.d f15, f5, f1 +fdiv.d f15, f5, f5 +fdiv.d f15, f5, f10 +fdiv.d f15, f5, f15 +fdiv.d f15, f5, f20 +fdiv.d f15, f5, f25 +fdiv.d f15, f5, f31 +fdiv.d f15, f10, f0 +fdiv.d f15, f10, f1 +fdiv.d f15, f10, f5 +fdiv.d f15, f10, f10 +fdiv.d f15, f10, f15 +fdiv.d f15, f10, f20 +fdiv.d f15, f10, f25 +fdiv.d f15, f10, f31 +fdiv.d f15, f15, f0 +fdiv.d f15, f15, f1 +fdiv.d f15, f15, f5 +fdiv.d f15, f15, f10 +fdiv.d f15, f15, f15 +fdiv.d f15, f15, f20 +fdiv.d f15, f15, f25 +fdiv.d f15, f15, f31 +fdiv.d f15, f20, f0 +fdiv.d f15, f20, f1 +fdiv.d f15, f20, f5 +fdiv.d f15, f20, f10 +fdiv.d f15, f20, f15 +fdiv.d f15, f20, f20 +fdiv.d f15, f20, f25 +fdiv.d f15, f20, f31 +fdiv.d f15, f25, f0 +fdiv.d f15, f25, f1 +fdiv.d f15, f25, f5 +fdiv.d f15, f25, f10 +fdiv.d f15, f25, f15 +fdiv.d f15, f25, f20 +fdiv.d f15, f25, f25 +fdiv.d f15, f25, f31 +fdiv.d f15, f31, f0 +fdiv.d f15, f31, f1 +fdiv.d f15, f31, f5 +fdiv.d f15, f31, f10 +fdiv.d f15, f31, f15 +fdiv.d f15, f31, f20 +fdiv.d f15, f31, f25 +fdiv.d f15, f31, f31 +fdiv.d f20, f0, f0 +fdiv.d f20, f0, f1 +fdiv.d f20, f0, f5 +fdiv.d f20, f0, f10 +fdiv.d f20, f0, f15 +fdiv.d f20, f0, f20 +fdiv.d f20, f0, f25 +fdiv.d f20, f0, f31 +fdiv.d f20, f1, f0 +fdiv.d f20, f1, f1 +fdiv.d f20, f1, f5 +fdiv.d f20, f1, f10 +fdiv.d f20, f1, f15 +fdiv.d f20, f1, f20 +fdiv.d f20, f1, f25 +fdiv.d f20, f1, f31 +fdiv.d f20, f5, f0 +fdiv.d f20, f5, f1 +fdiv.d f20, f5, f5 +fdiv.d f20, f5, f10 +fdiv.d f20, f5, f15 +fdiv.d f20, f5, f20 +fdiv.d f20, f5, f25 +fdiv.d f20, f5, f31 +fdiv.d f20, f10, f0 +fdiv.d f20, f10, f1 +fdiv.d f20, f10, f5 +fdiv.d f20, f10, f10 +fdiv.d f20, f10, f15 +fdiv.d f20, f10, f20 +fdiv.d f20, f10, f25 +fdiv.d f20, f10, f31 +fdiv.d f20, f15, f0 +fdiv.d f20, f15, f1 +fdiv.d f20, f15, f5 +fdiv.d f20, f15, f10 +fdiv.d f20, f15, f15 +fdiv.d f20, f15, f20 +fdiv.d f20, f15, f25 +fdiv.d f20, f15, f31 +fdiv.d f20, f20, f0 +fdiv.d f20, f20, f1 +fdiv.d f20, f20, f5 +fdiv.d f20, f20, f10 +fdiv.d f20, f20, f15 +fdiv.d f20, f20, f20 +fdiv.d f20, f20, f25 +fdiv.d f20, f20, f31 +fdiv.d f20, f25, f0 +fdiv.d f20, f25, f1 +fdiv.d f20, f25, f5 +fdiv.d f20, f25, f10 +fdiv.d f20, f25, f15 +fdiv.d f20, f25, f20 +fdiv.d f20, f25, f25 +fdiv.d f20, f25, f31 +fdiv.d f20, f31, f0 +fdiv.d f20, f31, f1 +fdiv.d f20, f31, f5 +fdiv.d f20, f31, f10 +fdiv.d f20, f31, f15 +fdiv.d f20, f31, f20 +fdiv.d f20, f31, f25 +fdiv.d f20, f31, f31 +fdiv.d f25, f0, f0 +fdiv.d f25, f0, f1 +fdiv.d f25, f0, f5 +fdiv.d f25, f0, f10 +fdiv.d f25, f0, f15 +fdiv.d f25, f0, f20 +fdiv.d f25, f0, f25 +fdiv.d f25, f0, f31 +fdiv.d f25, f1, f0 +fdiv.d f25, f1, f1 +fdiv.d f25, f1, f5 +fdiv.d f25, f1, f10 +fdiv.d f25, f1, f15 +fdiv.d f25, f1, f20 +fdiv.d f25, f1, f25 +fdiv.d f25, f1, f31 +fdiv.d f25, f5, f0 +fdiv.d f25, f5, f1 +fdiv.d f25, f5, f5 +fdiv.d f25, f5, f10 +fdiv.d f25, f5, f15 +fdiv.d f25, f5, f20 +fdiv.d f25, f5, f25 +fdiv.d f25, f5, f31 +fdiv.d f25, f10, f0 +fdiv.d f25, f10, f1 +fdiv.d f25, f10, f5 +fdiv.d f25, f10, f10 +fdiv.d f25, f10, f15 +fdiv.d f25, f10, f20 +fdiv.d f25, f10, f25 +fdiv.d f25, f10, f31 +fdiv.d f25, f15, f0 +fdiv.d f25, f15, f1 +fdiv.d f25, f15, f5 +fdiv.d f25, f15, f10 +fdiv.d f25, f15, f15 +fdiv.d f25, f15, f20 +fdiv.d f25, f15, f25 +fdiv.d f25, f15, f31 +fdiv.d f25, f20, f0 +fdiv.d f25, f20, f1 +fdiv.d f25, f20, f5 +fdiv.d f25, f20, f10 +fdiv.d f25, f20, f15 +fdiv.d f25, f20, f20 +fdiv.d f25, f20, f25 +fdiv.d f25, f20, f31 +fdiv.d f25, f25, f0 +fdiv.d f25, f25, f1 +fdiv.d f25, f25, f5 +fdiv.d f25, f25, f10 +fdiv.d f25, f25, f15 +fdiv.d f25, f25, f20 +fdiv.d f25, f25, f25 +fdiv.d f25, f25, f31 +fdiv.d f25, f31, f0 +fdiv.d f25, f31, f1 +fdiv.d f25, f31, f5 +fdiv.d f25, f31, f10 +fdiv.d f25, f31, f15 +fdiv.d f25, f31, f20 +fdiv.d f25, f31, f25 +fdiv.d f25, f31, f31 +fdiv.d f31, f0, f0 +fdiv.d f31, f0, f1 +fdiv.d f31, f0, f5 +fdiv.d f31, f0, f10 +fdiv.d f31, f0, f15 +fdiv.d f31, f0, f20 +fdiv.d f31, f0, f25 +fdiv.d f31, f0, f31 +fdiv.d f31, f1, f0 +fdiv.d f31, f1, f1 +fdiv.d f31, f1, f5 +fdiv.d f31, f1, f10 +fdiv.d f31, f1, f15 +fdiv.d f31, f1, f20 +fdiv.d f31, f1, f25 +fdiv.d f31, f1, f31 +fdiv.d f31, f5, f0 +fdiv.d f31, f5, f1 +fdiv.d f31, f5, f5 +fdiv.d f31, f5, f10 +fdiv.d f31, f5, f15 +fdiv.d f31, f5, f20 +fdiv.d f31, f5, f25 +fdiv.d f31, f5, f31 +fdiv.d f31, f10, f0 +fdiv.d f31, f10, f1 +fdiv.d f31, f10, f5 +fdiv.d f31, f10, f10 +fdiv.d f31, f10, f15 +fdiv.d f31, f10, f20 +fdiv.d f31, f10, f25 +fdiv.d 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+fdiv.d f20, f5, f0 +fdiv.d f20, f5, f1 +fdiv.d f20, f5, f5 +fdiv.d f20, f5, f10 +fdiv.d f20, f5, f15 +fdiv.d f20, f5, f20 +fdiv.d f20, f5, f25 +fdiv.d f20, f5, f31 +fdiv.d f20, f10, f0 +fdiv.d f20, f10, f1 +fdiv.d f20, f10, f5 +fdiv.d f20, f10, f10 +fdiv.d f20, f10, f15 +fdiv.d f20, f10, f20 +fdiv.d f20, f10, f25 +fdiv.d f20, f10, f31 +fdiv.d f20, f15, f0 +fdiv.d f20, f15, f1 +fdiv.d f20, f15, f5 +fdiv.d f20, f15, f10 +fdiv.d f20, f15, f15 +fdiv.d f20, f15, f20 +fdiv.d f20, f15, f25 +fdiv.d f20, f15, f31 +fdiv.d f20, f20, f0 +fdiv.d f20, f20, f1 +fdiv.d f20, f20, f5 +fdiv.d f20, f20, f10 +fdiv.d f20, f20, f15 +fdiv.d f20, f20, f20 +fdiv.d f20, f20, f25 +fdiv.d f20, f20, f31 +fdiv.d f20, f25, f0 +fdiv.d f20, f25, f1 +fdiv.d f20, f25, f5 +fdiv.d f20, f25, f10 +fdiv.d f20, f25, f15 +fdiv.d f20, f25, f20 +fdiv.d f20, f25, f25 +fdiv.d f20, f25, f31 +fdiv.d f20, f31, f0 +fdiv.d f20, f31, f1 +fdiv.d f20, f31, f5 +fdiv.d f20, f31, f10 +fdiv.d f20, f31, f15 +fdiv.d f20, f31, f20 +fdiv.d f20, f31, f25 +fdiv.d f20, f31, f31 +fdiv.d f25, f0, f0 +fdiv.d f25, f0, f1 +fdiv.d f25, f0, f5 +fdiv.d f25, f0, f10 +fdiv.d f25, f0, f15 +fdiv.d f25, f0, f20 +fdiv.d f25, f0, f25 +fdiv.d f25, f0, f31 +fdiv.d f25, f1, f0 +fdiv.d f25, f1, f1 +fdiv.d f25, f1, f5 +fdiv.d f25, f1, f10 +fdiv.d f25, f1, f15 +fdiv.d f25, f1, f20 +fdiv.d f25, f1, f25 +fdiv.d f25, f1, f31 +fdiv.d f25, f5, f0 +fdiv.d f25, f5, f1 +fdiv.d f25, f5, f5 +fdiv.d f25, f5, f10 +fdiv.d f25, f5, f15 +fdiv.d f25, f5, f20 +fdiv.d f25, f5, f25 +fdiv.d f25, f5, f31 +fdiv.d f25, f10, f0 +fdiv.d f25, f10, f1 +fdiv.d f25, f10, f5 +fdiv.d f25, f10, f10 +fdiv.d f25, f10, f15 +fdiv.d f25, f10, f20 +fdiv.d f25, f10, f25 +fdiv.d f25, f10, f31 +fdiv.d f25, f15, f0 +fdiv.d f25, f15, f1 +fdiv.d f25, f15, f5 +fdiv.d f25, f15, f10 +fdiv.d f25, f15, f15 +fdiv.d f25, f15, f20 +fdiv.d f25, f15, f25 +fdiv.d f25, f15, f31 +fdiv.d f25, f20, f0 +fdiv.d f25, f20, f1 +fdiv.d f25, f20, f5 +fdiv.d f25, f20, f10 +fdiv.d f25, f20, f15 +fdiv.d f25, f20, f20 +fdiv.d f25, f20, f25 +fdiv.d f25, f20, f31 +fdiv.d f25, f25, f0 +fdiv.d f25, f25, f1 +fdiv.d f25, f25, f5 +fdiv.d f25, f25, f10 +fdiv.d f25, f25, f15 +fdiv.d f25, f25, f20 +fdiv.d f25, f25, f25 +fdiv.d f25, f25, f31 +fdiv.d f25, f31, f0 +fdiv.d f25, f31, f1 +fdiv.d f25, f31, f5 +fdiv.d f25, f31, f10 +fdiv.d f25, f31, f15 +fdiv.d f25, f31, f20 +fdiv.d f25, f31, f25 +fdiv.d f25, f31, f31 +fdiv.d f31, f0, f0 +fdiv.d f31, f0, f1 +fdiv.d f31, f0, f5 +fdiv.d f31, f0, f10 +fdiv.d f31, f0, f15 +fdiv.d f31, f0, f20 +fdiv.d f31, f0, f25 +fdiv.d f31, f0, f31 +fdiv.d f31, f1, f0 +fdiv.d f31, f1, f1 +fdiv.d f31, f1, f5 +fdiv.d f31, f1, f10 +fdiv.d f31, f1, f15 +fdiv.d f31, f1, f20 +fdiv.d f31, f1, f25 +fdiv.d f31, f1, f31 +fdiv.d f31, f5, f0 +fdiv.d f31, f5, f1 +fdiv.d f31, f5, f5 +fdiv.d f31, f5, f10 +fdiv.d f31, f5, f15 +fdiv.d f31, f5, f20 +fdiv.d f31, f5, f25 +fdiv.d f31, f5, f31 +fdiv.d f31, f10, f0 +fdiv.d f31, f10, f1 +fdiv.d f31, f10, f5 +fdiv.d f31, f10, f10 +fdiv.d f31, f10, f15 +fdiv.d f31, f10, f20 +fdiv.d f31, f10, f25 +fdiv.d f31, f10, f31 +fdiv.d f31, f15, f0 +fdiv.d f31, f15, f1 +fdiv.d f31, f15, f5 +fdiv.d f31, f15, f10 +fdiv.d f31, f15, f15 +fdiv.d f31, f15, f20 +fdiv.d f31, f15, f25 +fdiv.d f31, f15, f31 +fdiv.d f31, f20, f0 +fdiv.d f31, f20, f1 +fdiv.d f31, f20, f5 +fdiv.d f31, f20, f10 +fdiv.d f31, f20, f15 +fdiv.d f31, f20, f20 +fdiv.d f31, f20, f25 +fdiv.d f31, f20, f31 +fdiv.d f31, f25, f0 +fdiv.d f31, f25, f1 +fdiv.d f31, f25, f5 +fdiv.d f31, f25, f10 +fdiv.d f31, f25, f15 +fdiv.d f31, f25, f20 +fdiv.d f31, f25, f25 +fdiv.d f31, f25, f31 +fdiv.d f31, f31, f0 +fdiv.d f31, f31, f1 +fdiv.d f31, f31, f5 +fdiv.d f31, f31, f10 +fdiv.d f31, f31, f15 +fdiv.d f31, f31, f20 +fdiv.d f31, f31, f25 +fdiv.d f31, f31, f31 diff --git a/tests/riscv/d-extension/fdiv_d.asm b/tests/riscv/d-extension/fdiv_d.asm new file mode 100644 index 0000000..b76eae0 --- /dev/null +++ b/tests/riscv/d-extension/fdiv_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fdiv.d f0, f1, f2 + diff --git a/tests/riscv/d-extension/fdiv_d.bin b/tests/riscv/d-extension/fdiv_d.bin new file mode 100644 index 0000000..27e98b3 --- /dev/null +++ b/tests/riscv/d-extension/fdiv_d.bin @@ -0,0 +1 @@ +S  \ No newline at end of file diff --git a/tests/riscv/d-extension/fdiv_d.disasm b/tests/riscv/d-extension/fdiv_d.disasm new file mode 100644 index 0000000..24415da --- /dev/null +++ b/tests/riscv/d-extension/fdiv_d.disasm @@ -0,0 +1 @@ +fdiv.d f0, f1, f2 diff --git a/tests/riscv/d-extension/feq.d.asm b/tests/riscv/d-extension/feq.d.asm new file mode 100644 index 0000000..b906c0e --- /dev/null +++ b/tests/riscv/d-extension/feq.d.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +feq.d zero, f0, f0 +feq.d zero, f0, f1 +feq.d zero, f0, f5 +feq.d zero, f0, f10 +feq.d zero, f0, f15 +feq.d zero, f0, f20 +feq.d zero, f0, f25 +feq.d zero, f0, f31 +feq.d zero, f1, f0 +feq.d zero, f1, f1 +feq.d zero, f1, f5 +feq.d zero, f1, f10 +feq.d zero, f1, f15 +feq.d zero, f1, f20 +feq.d zero, f1, f25 +feq.d zero, f1, f31 +feq.d zero, f5, f0 +feq.d zero, f5, f1 +feq.d zero, f5, f5 +feq.d zero, f5, f10 +feq.d zero, f5, f15 +feq.d zero, f5, f20 +feq.d zero, f5, f25 +feq.d zero, f5, f31 +feq.d zero, f10, f0 +feq.d zero, f10, f1 +feq.d zero, f10, f5 +feq.d zero, f10, f10 +feq.d zero, f10, f15 +feq.d zero, f10, f20 +feq.d zero, f10, f25 +feq.d zero, f10, f31 +feq.d zero, f15, f0 +feq.d zero, f15, f1 +feq.d zero, f15, f5 +feq.d zero, f15, f10 +feq.d zero, f15, f15 +feq.d zero, f15, f20 +feq.d zero, f15, f25 +feq.d zero, f15, f31 +feq.d zero, f20, f0 +feq.d zero, f20, f1 +feq.d zero, f20, f5 +feq.d zero, f20, f10 +feq.d zero, f20, f15 +feq.d zero, f20, f20 +feq.d zero, f20, f25 +feq.d zero, f20, f31 +feq.d zero, f25, f0 +feq.d zero, f25, f1 +feq.d zero, f25, f5 +feq.d zero, f25, f10 +feq.d zero, f25, f15 +feq.d zero, f25, f20 +feq.d zero, f25, f25 +feq.d zero, f25, f31 +feq.d zero, f31, f0 +feq.d zero, f31, f1 +feq.d zero, f31, f5 +feq.d zero, f31, f10 +feq.d zero, f31, f15 +feq.d zero, f31, f20 +feq.d zero, f31, f25 +feq.d zero, f31, f31 +feq.d ra, f0, f0 +feq.d ra, f0, f1 +feq.d ra, f0, f5 +feq.d ra, f0, f10 +feq.d ra, f0, f15 +feq.d ra, f0, f20 +feq.d ra, f0, f25 +feq.d ra, f0, f31 +feq.d ra, f1, f0 +feq.d ra, f1, f1 +feq.d ra, f1, f5 +feq.d ra, f1, f10 +feq.d ra, f1, f15 +feq.d ra, f1, f20 +feq.d ra, f1, f25 +feq.d ra, f1, f31 +feq.d ra, f5, f0 +feq.d ra, f5, f1 +feq.d ra, f5, f5 +feq.d ra, f5, f10 +feq.d ra, f5, f15 +feq.d ra, f5, f20 +feq.d ra, f5, f25 +feq.d ra, f5, f31 +feq.d ra, f10, f0 +feq.d ra, f10, f1 +feq.d ra, f10, f5 +feq.d ra, f10, f10 +feq.d ra, f10, f15 +feq.d ra, f10, f20 +feq.d ra, f10, f25 +feq.d ra, f10, f31 +feq.d ra, f15, f0 +feq.d ra, f15, f1 +feq.d ra, f15, f5 +feq.d ra, f15, f10 +feq.d ra, f15, f15 +feq.d ra, f15, f20 +feq.d ra, f15, f25 +feq.d ra, f15, f31 +feq.d ra, f20, f0 +feq.d ra, f20, f1 +feq.d ra, f20, f5 +feq.d ra, f20, f10 +feq.d ra, f20, f15 +feq.d ra, f20, f20 +feq.d ra, f20, f25 +feq.d ra, f20, f31 +feq.d ra, f25, f0 +feq.d ra, f25, f1 +feq.d ra, f25, f5 +feq.d ra, f25, f10 +feq.d ra, f25, f15 +feq.d ra, f25, f20 +feq.d ra, f25, f25 +feq.d ra, f25, f31 +feq.d ra, f31, f0 +feq.d ra, f31, f1 +feq.d ra, f31, f5 +feq.d ra, f31, f10 +feq.d ra, f31, f15 +feq.d ra, f31, f20 +feq.d ra, f31, f25 +feq.d ra, f31, f31 +feq.d t0, f0, f0 +feq.d t0, f0, f1 +feq.d t0, f0, f5 +feq.d t0, f0, f10 +feq.d t0, f0, f15 +feq.d t0, f0, f20 +feq.d t0, f0, f25 +feq.d t0, f0, f31 +feq.d t0, f1, f0 +feq.d t0, f1, f1 +feq.d t0, f1, f5 +feq.d t0, f1, f10 +feq.d t0, f1, f15 +feq.d t0, f1, f20 +feq.d t0, f1, f25 +feq.d t0, f1, f31 +feq.d t0, f5, f0 +feq.d t0, f5, f1 +feq.d t0, f5, f5 +feq.d t0, f5, f10 +feq.d t0, f5, f15 +feq.d t0, f5, f20 +feq.d t0, f5, f25 +feq.d t0, f5, f31 +feq.d t0, f10, f0 +feq.d t0, f10, f1 +feq.d t0, f10, f5 +feq.d t0, f10, f10 +feq.d t0, f10, f15 +feq.d t0, f10, f20 +feq.d t0, f10, f25 +feq.d t0, f10, f31 +feq.d t0, f15, f0 +feq.d t0, f15, f1 +feq.d t0, f15, f5 +feq.d t0, f15, f10 +feq.d t0, f15, f15 +feq.d t0, f15, f20 +feq.d t0, f15, f25 +feq.d t0, f15, f31 +feq.d t0, f20, f0 +feq.d t0, f20, f1 +feq.d t0, f20, f5 +feq.d t0, f20, f10 +feq.d t0, f20, f15 +feq.d t0, f20, f20 +feq.d t0, f20, f25 +feq.d t0, f20, f31 +feq.d t0, f25, f0 +feq.d t0, f25, f1 +feq.d t0, f25, f5 +feq.d t0, f25, f10 +feq.d t0, f25, f15 +feq.d t0, f25, f20 +feq.d t0, f25, f25 +feq.d t0, f25, f31 +feq.d t0, f31, f0 +feq.d t0, f31, f1 +feq.d t0, f31, f5 +feq.d t0, f31, f10 +feq.d t0, f31, f15 +feq.d t0, f31, f20 +feq.d t0, f31, f25 +feq.d t0, f31, f31 +feq.d a0, f0, f0 +feq.d a0, f0, f1 +feq.d a0, f0, f5 +feq.d a0, f0, f10 +feq.d a0, f0, f15 +feq.d a0, f0, f20 +feq.d a0, f0, f25 +feq.d a0, f0, f31 +feq.d a0, f1, f0 +feq.d a0, f1, f1 +feq.d a0, f1, f5 +feq.d a0, f1, f10 +feq.d a0, f1, f15 +feq.d a0, f1, f20 +feq.d a0, f1, f25 +feq.d a0, f1, f31 +feq.d a0, f5, f0 +feq.d a0, f5, f1 +feq.d a0, f5, f5 +feq.d a0, f5, f10 +feq.d a0, f5, f15 +feq.d a0, f5, f20 +feq.d a0, f5, f25 +feq.d a0, f5, f31 +feq.d a0, f10, f0 +feq.d a0, f10, f1 +feq.d a0, f10, f5 +feq.d a0, f10, f10 +feq.d a0, f10, f15 +feq.d a0, f10, f20 +feq.d a0, f10, f25 +feq.d a0, f10, f31 +feq.d a0, f15, f0 +feq.d a0, f15, f1 +feq.d a0, f15, f5 +feq.d a0, f15, f10 +feq.d a0, f15, f15 +feq.d a0, f15, f20 +feq.d a0, f15, f25 +feq.d a0, f15, f31 +feq.d a0, f20, f0 +feq.d a0, f20, f1 +feq.d a0, f20, f5 +feq.d a0, f20, f10 +feq.d a0, f20, f15 +feq.d a0, f20, f20 +feq.d a0, f20, f25 +feq.d a0, f20, f31 +feq.d a0, f25, f0 +feq.d a0, f25, f1 +feq.d a0, f25, f5 +feq.d a0, f25, f10 +feq.d a0, f25, f15 +feq.d a0, f25, f20 +feq.d a0, f25, f25 +feq.d a0, f25, f31 +feq.d a0, f31, f0 +feq.d a0, f31, f1 +feq.d a0, f31, f5 +feq.d a0, f31, f10 +feq.d a0, f31, f15 +feq.d a0, f31, f20 +feq.d a0, f31, f25 +feq.d a0, f31, f31 +feq.d a5, f0, f0 +feq.d a5, f0, f1 +feq.d a5, f0, f5 +feq.d a5, f0, f10 +feq.d a5, f0, f15 +feq.d a5, f0, f20 +feq.d a5, f0, f25 +feq.d a5, f0, f31 +feq.d a5, f1, f0 +feq.d a5, f1, f1 +feq.d a5, f1, f5 +feq.d a5, f1, f10 +feq.d a5, f1, f15 +feq.d a5, f1, f20 +feq.d a5, f1, f25 +feq.d a5, f1, f31 +feq.d a5, f5, f0 +feq.d a5, f5, f1 +feq.d a5, f5, f5 +feq.d a5, f5, f10 +feq.d a5, f5, f15 +feq.d a5, f5, f20 +feq.d a5, f5, f25 +feq.d a5, f5, f31 +feq.d a5, f10, f0 +feq.d a5, f10, f1 +feq.d a5, f10, f5 +feq.d a5, f10, f10 +feq.d a5, f10, f15 +feq.d a5, f10, f20 +feq.d a5, f10, f25 +feq.d a5, f10, f31 +feq.d a5, f15, f0 +feq.d a5, f15, f1 +feq.d a5, f15, f5 +feq.d a5, f15, f10 +feq.d a5, f15, f15 +feq.d a5, f15, f20 +feq.d a5, f15, f25 +feq.d a5, f15, f31 +feq.d a5, f20, f0 +feq.d a5, f20, f1 +feq.d a5, f20, f5 +feq.d a5, f20, f10 +feq.d a5, f20, f15 +feq.d a5, f20, f20 +feq.d a5, f20, f25 +feq.d a5, f20, f31 +feq.d a5, f25, f0 +feq.d a5, f25, f1 +feq.d a5, f25, f5 +feq.d a5, f25, f10 +feq.d a5, f25, f15 +feq.d a5, f25, f20 +feq.d a5, f25, f25 +feq.d a5, f25, f31 +feq.d a5, f31, f0 +feq.d a5, f31, f1 +feq.d a5, f31, f5 +feq.d a5, f31, f10 +feq.d a5, f31, f15 +feq.d a5, f31, f20 +feq.d a5, f31, f25 +feq.d a5, f31, f31 +feq.d s4, f0, f0 +feq.d s4, f0, f1 +feq.d s4, f0, f5 +feq.d s4, f0, f10 +feq.d s4, f0, f15 +feq.d s4, f0, f20 +feq.d s4, f0, f25 +feq.d s4, f0, f31 +feq.d s4, f1, f0 +feq.d s4, f1, f1 +feq.d s4, f1, f5 +feq.d s4, f1, f10 +feq.d s4, f1, f15 +feq.d s4, f1, f20 +feq.d s4, f1, f25 +feq.d s4, f1, f31 +feq.d s4, f5, f0 +feq.d s4, f5, f1 +feq.d s4, f5, f5 +feq.d s4, f5, f10 +feq.d s4, f5, f15 +feq.d s4, f5, f20 +feq.d s4, f5, f25 +feq.d s4, f5, f31 +feq.d s4, f10, f0 +feq.d s4, f10, f1 +feq.d s4, f10, f5 +feq.d s4, f10, f10 +feq.d s4, f10, f15 +feq.d s4, f10, f20 +feq.d s4, f10, f25 +feq.d s4, f10, f31 +feq.d s4, f15, f0 +feq.d s4, f15, f1 +feq.d s4, f15, f5 +feq.d s4, f15, f10 +feq.d s4, f15, f15 +feq.d s4, f15, f20 +feq.d s4, f15, f25 +feq.d s4, f15, f31 +feq.d s4, f20, f0 +feq.d s4, f20, f1 +feq.d s4, f20, f5 +feq.d s4, f20, f10 +feq.d s4, f20, f15 +feq.d s4, f20, f20 +feq.d s4, f20, f25 +feq.d s4, f20, f31 +feq.d s4, f25, f0 +feq.d s4, f25, f1 +feq.d s4, f25, f5 +feq.d s4, f25, f10 +feq.d s4, f25, f15 +feq.d s4, f25, f20 +feq.d s4, f25, f25 +feq.d s4, f25, f31 +feq.d s4, f31, f0 +feq.d s4, f31, f1 +feq.d s4, f31, f5 +feq.d s4, f31, f10 +feq.d s4, f31, f15 +feq.d s4, f31, f20 +feq.d s4, f31, f25 +feq.d s4, f31, f31 +feq.d s9, f0, f0 +feq.d s9, f0, f1 +feq.d s9, f0, f5 +feq.d s9, f0, f10 +feq.d s9, f0, f15 +feq.d s9, f0, f20 +feq.d s9, f0, f25 +feq.d s9, f0, f31 +feq.d s9, f1, f0 +feq.d s9, f1, f1 +feq.d s9, f1, f5 +feq.d s9, f1, f10 +feq.d s9, f1, f15 +feq.d s9, f1, f20 +feq.d s9, f1, f25 +feq.d s9, f1, f31 +feq.d s9, f5, f0 +feq.d s9, f5, f1 +feq.d s9, f5, f5 +feq.d s9, f5, f10 +feq.d s9, f5, f15 +feq.d s9, f5, f20 +feq.d s9, f5, f25 +feq.d s9, f5, f31 +feq.d s9, f10, f0 +feq.d s9, f10, f1 +feq.d s9, f10, f5 +feq.d s9, f10, f10 +feq.d s9, f10, f15 +feq.d s9, f10, f20 +feq.d s9, f10, f25 +feq.d s9, f10, f31 +feq.d s9, f15, f0 +feq.d s9, f15, f1 +feq.d s9, f15, f5 +feq.d s9, f15, f10 +feq.d s9, f15, f15 +feq.d s9, f15, f20 +feq.d s9, f15, f25 +feq.d s9, f15, f31 +feq.d s9, f20, f0 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b/tests/riscv/d-extension/fld.disasm @@ -0,0 +1,1600 @@ +fld f0, (#0xfffff801, zero) +fld f0, (#0xfffffc00, zero) +fld f0, (#0xfffffe00, zero) +fld f0, (#0xffffff00, zero) +fld f0, (#0xffffff80, zero) +fld f0, (#0xffffffc0, zero) +fld f0, (#0xffffffe0, zero) +fld f0, (#0xfffffff0, zero) +fld f0, (#0xfffffff8, zero) +fld f0, (#0xfffffffc, zero) +fld f0, (#0xfffffffe, zero) +fld f0, (#0xffffffff, zero) +fld f0, (#0, zero) +fld f0, (#1, zero) +fld f0, (#2, zero) +fld f0, (#4, zero) +fld f0, (#8, zero) +fld f0, (#0x10, zero) +fld f0, (#0x20, zero) +fld f0, (#0x40, zero) +fld f0, (#0x80, zero) +fld f0, (#0x100, zero) +fld f0, (#0x200, zero) +fld f0, (#0x400, zero) +fld f0, (#0x7ff, zero) +fld f0, (#0xfffff801, ra) +fld f0, (#0xfffffc00, ra) +fld f0, (#0xfffffe00, ra) +fld f0, (#0xffffff00, ra) +fld f0, (#0xffffff80, ra) +fld f0, (#0xffffffc0, ra) +fld f0, (#0xffffffe0, ra) +fld f0, (#0xfffffff0, ra) +fld f0, (#0xfffffff8, ra) +fld f0, (#0xfffffffc, ra) +fld f0, (#0xfffffffe, ra) +fld f0, (#0xffffffff, ra) +fld f0, (#0, ra) +fld f0, (#1, ra) +fld f0, (#2, ra) +fld f0, (#4, ra) +fld f0, (#8, ra) +fld f0, (#0x10, ra) +fld f0, (#0x20, ra) +fld f0, (#0x40, ra) +fld f0, (#0x80, ra) +fld f0, (#0x100, ra) +fld f0, (#0x200, ra) +fld f0, (#0x400, ra) +fld f0, (#0x7ff, ra) +fld f0, (#0xfffff801, t0) +fld f0, (#0xfffffc00, t0) +fld f0, (#0xfffffe00, t0) +fld f0, (#0xffffff00, t0) +fld f0, (#0xffffff80, t0) +fld f0, (#0xffffffc0, t0) +fld f0, (#0xffffffe0, t0) +fld f0, (#0xfffffff0, t0) +fld f0, (#0xfffffff8, t0) +fld f0, (#0xfffffffc, t0) +fld f0, (#0xfffffffe, t0) +fld f0, (#0xffffffff, t0) +fld f0, (#0, t0) +fld f0, (#1, t0) +fld f0, (#2, t0) +fld f0, (#4, t0) +fld f0, (#8, t0) +fld f0, (#0x10, t0) +fld f0, (#0x20, t0) +fld f0, (#0x40, t0) +fld f0, (#0x80, t0) +fld f0, (#0x100, t0) +fld f0, (#0x200, t0) +fld f0, (#0x400, t0) +fld f0, (#0x7ff, t0) +fld f0, (#0xfffff801, a0) +fld f0, (#0xfffffc00, a0) +fld f0, (#0xfffffe00, a0) +fld f0, (#0xffffff00, a0) +fld f0, (#0xffffff80, a0) +fld f0, (#0xffffffc0, a0) +fld f0, (#0xffffffe0, a0) +fld f0, (#0xfffffff0, a0) +fld f0, (#0xfffffff8, a0) +fld f0, (#0xfffffffc, a0) +fld f0, (#0xfffffffe, a0) +fld f0, (#0xffffffff, a0) +fld f0, (#0, a0) +fld f0, (#1, a0) +fld f0, (#2, a0) +fld f0, (#4, a0) +fld f0, (#8, a0) +fld f0, (#0x10, a0) +fld f0, (#0x20, a0) +fld f0, (#0x40, a0) +fld f0, (#0x80, a0) +fld f0, (#0x100, a0) +fld f0, (#0x200, a0) +fld f0, (#0x400, a0) +fld f0, (#0x7ff, a0) +fld f0, (#0xfffff801, a5) +fld f0, (#0xfffffc00, a5) +fld f0, (#0xfffffe00, a5) +fld f0, (#0xffffff00, a5) +fld f0, (#0xffffff80, a5) +fld f0, (#0xffffffc0, a5) +fld f0, (#0xffffffe0, a5) +fld f0, (#0xfffffff0, a5) +fld f0, (#0xfffffff8, a5) +fld f0, (#0xfffffffc, a5) +fld f0, (#0xfffffffe, a5) +fld f0, (#0xffffffff, a5) +fld f0, (#0, a5) +fld f0, (#1, a5) +fld f0, (#2, a5) +fld f0, (#4, a5) +fld f0, (#8, a5) +fld f0, (#0x10, a5) +fld f0, (#0x20, a5) +fld f0, (#0x40, a5) +fld f0, (#0x80, a5) +fld f0, (#0x100, a5) +fld f0, (#0x200, a5) +fld f0, (#0x400, a5) +fld f0, (#0x7ff, a5) +fld f0, (#0xfffff801, s4) +fld f0, (#0xfffffc00, s4) +fld f0, (#0xfffffe00, s4) +fld f0, (#0xffffff00, s4) +fld f0, (#0xffffff80, s4) +fld f0, (#0xffffffc0, s4) +fld f0, (#0xffffffe0, s4) +fld f0, (#0xfffffff0, s4) +fld f0, (#0xfffffff8, s4) +fld f0, (#0xfffffffc, s4) +fld f0, (#0xfffffffe, s4) +fld f0, (#0xffffffff, s4) +fld f0, (#0, s4) +fld f0, (#1, s4) +fld f0, (#2, s4) +fld f0, (#4, s4) +fld f0, (#8, s4) +fld f0, (#0x10, s4) +fld f0, (#0x20, s4) +fld f0, (#0x40, s4) +fld f0, (#0x80, s4) +fld f0, (#0x100, s4) +fld f0, (#0x200, s4) +fld f0, (#0x400, s4) +fld f0, (#0x7ff, s4) +fld f0, (#0xfffff801, s9) +fld f0, (#0xfffffc00, s9) +fld f0, (#0xfffffe00, s9) +fld f0, (#0xffffff00, s9) +fld f0, (#0xffffff80, s9) +fld f0, (#0xffffffc0, s9) +fld f0, (#0xffffffe0, s9) +fld f0, (#0xfffffff0, s9) +fld f0, (#0xfffffff8, s9) +fld f0, (#0xfffffffc, s9) +fld f0, (#0xfffffffe, s9) +fld f0, (#0xffffffff, s9) +fld f0, (#0, s9) +fld f0, (#1, s9) +fld f0, (#2, s9) +fld f0, (#4, s9) +fld f0, (#8, s9) +fld f0, (#0x10, s9) +fld f0, (#0x20, s9) +fld f0, (#0x40, s9) +fld f0, (#0x80, s9) +fld f0, (#0x100, s9) +fld f0, (#0x200, s9) +fld f0, (#0x400, s9) +fld f0, (#0x7ff, s9) +fld f0, (#0xfffff801, t6) +fld f0, (#0xfffffc00, t6) +fld f0, (#0xfffffe00, t6) +fld f0, (#0xffffff00, t6) +fld f0, (#0xffffff80, t6) +fld f0, (#0xffffffc0, t6) +fld f0, (#0xffffffe0, t6) +fld f0, (#0xfffffff0, t6) +fld f0, (#0xfffffff8, t6) +fld f0, (#0xfffffffc, t6) +fld f0, (#0xfffffffe, t6) +fld f0, (#0xffffffff, t6) +fld f0, (#0, t6) +fld f0, (#1, t6) +fld f0, (#2, t6) +fld f0, (#4, t6) +fld f0, (#8, t6) +fld f0, (#0x10, t6) +fld f0, (#0x20, t6) +fld f0, (#0x40, t6) +fld f0, (#0x80, t6) +fld f0, (#0x100, t6) +fld f0, (#0x200, t6) +fld f0, (#0x400, t6) +fld f0, (#0x7ff, t6) +fld f1, (#0xfffff801, zero) +fld f1, (#0xfffffc00, zero) +fld f1, (#0xfffffe00, zero) +fld f1, (#0xffffff00, zero) +fld f1, (#0xffffff80, zero) +fld f1, (#0xffffffc0, zero) +fld f1, (#0xffffffe0, zero) +fld f1, (#0xfffffff0, zero) +fld f1, (#0xfffffff8, zero) +fld f1, (#0xfffffffc, zero) +fld f1, (#0xfffffffe, zero) +fld f1, (#0xffffffff, zero) +fld f1, (#0, zero) +fld f1, (#1, zero) +fld f1, (#2, zero) +fld f1, (#4, zero) +fld f1, (#8, zero) +fld f1, (#0x10, zero) +fld f1, (#0x20, zero) +fld f1, (#0x40, zero) +fld f1, (#0x80, zero) +fld f1, (#0x100, zero) +fld f1, (#0x200, zero) +fld f1, (#0x400, zero) +fld f1, (#0x7ff, zero) +fld f1, (#0xfffff801, ra) +fld f1, (#0xfffffc00, ra) +fld f1, (#0xfffffe00, ra) +fld f1, (#0xffffff00, ra) +fld f1, (#0xffffff80, ra) +fld f1, (#0xffffffc0, ra) +fld f1, (#0xffffffe0, ra) +fld f1, (#0xfffffff0, ra) +fld f1, (#0xfffffff8, ra) +fld f1, (#0xfffffffc, ra) +fld f1, (#0xfffffffe, ra) +fld f1, (#0xffffffff, ra) +fld f1, (#0, ra) +fld f1, (#1, ra) +fld f1, (#2, ra) +fld f1, (#4, ra) +fld f1, (#8, ra) +fld f1, (#0x10, ra) +fld f1, (#0x20, ra) +fld f1, (#0x40, ra) +fld f1, (#0x80, ra) +fld f1, (#0x100, ra) +fld f1, (#0x200, ra) +fld f1, (#0x400, ra) +fld f1, (#0x7ff, ra) +fld f1, (#0xfffff801, t0) +fld f1, (#0xfffffc00, t0) +fld f1, (#0xfffffe00, t0) +fld f1, (#0xffffff00, t0) +fld f1, (#0xffffff80, t0) +fld f1, (#0xffffffc0, t0) +fld f1, (#0xffffffe0, t0) +fld f1, (#0xfffffff0, t0) +fld f1, (#0xfffffff8, t0) +fld f1, (#0xfffffffc, t0) +fld f1, (#0xfffffffe, t0) +fld f1, (#0xffffffff, t0) +fld f1, (#0, t0) +fld f1, (#1, t0) +fld f1, (#2, t0) +fld f1, (#4, t0) +fld f1, (#8, t0) +fld f1, (#0x10, t0) +fld f1, (#0x20, t0) +fld f1, (#0x40, t0) +fld f1, (#0x80, t0) +fld f1, (#0x100, t0) +fld f1, (#0x200, t0) +fld f1, (#0x400, t0) +fld f1, (#0x7ff, t0) +fld f1, (#0xfffff801, a0) +fld f1, (#0xfffffc00, a0) +fld f1, (#0xfffffe00, a0) +fld f1, (#0xffffff00, a0) +fld f1, (#0xffffff80, a0) +fld f1, (#0xffffffc0, a0) +fld f1, (#0xffffffe0, a0) +fld f1, (#0xfffffff0, a0) +fld f1, (#0xfffffff8, a0) +fld f1, (#0xfffffffc, a0) +fld f1, (#0xfffffffe, a0) +fld f1, (#0xffffffff, a0) +fld f1, (#0, a0) +fld f1, (#1, a0) +fld f1, (#2, a0) +fld f1, (#4, a0) +fld f1, (#8, a0) +fld f1, (#0x10, a0) +fld f1, (#0x20, a0) +fld f1, (#0x40, a0) +fld f1, (#0x80, a0) +fld f1, (#0x100, a0) +fld f1, (#0x200, a0) +fld f1, (#0x400, a0) +fld f1, (#0x7ff, a0) +fld f1, (#0xfffff801, a5) +fld f1, (#0xfffffc00, a5) +fld f1, (#0xfffffe00, a5) +fld f1, (#0xffffff00, a5) +fld f1, (#0xffffff80, a5) +fld f1, (#0xffffffc0, a5) +fld f1, (#0xffffffe0, a5) +fld f1, (#0xfffffff0, a5) +fld f1, (#0xfffffff8, a5) +fld f1, (#0xfffffffc, a5) +fld f1, (#0xfffffffe, a5) +fld f1, (#0xffffffff, a5) +fld f1, (#0, a5) +fld f1, (#1, a5) +fld f1, (#2, a5) +fld f1, (#4, a5) +fld f1, (#8, a5) +fld f1, (#0x10, a5) +fld f1, (#0x20, a5) +fld f1, (#0x40, a5) +fld f1, (#0x80, a5) +fld f1, (#0x100, a5) +fld f1, (#0x200, a5) +fld f1, (#0x400, a5) +fld f1, (#0x7ff, a5) +fld f1, (#0xfffff801, s4) +fld f1, (#0xfffffc00, s4) +fld f1, (#0xfffffe00, s4) +fld f1, (#0xffffff00, s4) +fld f1, (#0xffffff80, s4) +fld f1, (#0xffffffc0, s4) +fld f1, (#0xffffffe0, s4) +fld f1, (#0xfffffff0, s4) +fld f1, (#0xfffffff8, s4) +fld f1, (#0xfffffffc, s4) +fld f1, (#0xfffffffe, s4) +fld f1, (#0xffffffff, s4) +fld f1, (#0, s4) +fld f1, (#1, s4) +fld f1, (#2, s4) +fld f1, (#4, s4) +fld f1, (#8, s4) +fld f1, (#0x10, s4) +fld f1, (#0x20, s4) +fld f1, (#0x40, s4) +fld f1, (#0x80, s4) +fld f1, (#0x100, s4) +fld f1, (#0x200, s4) +fld f1, (#0x400, s4) +fld f1, (#0x7ff, s4) +fld f1, (#0xfffff801, s9) +fld f1, (#0xfffffc00, s9) +fld f1, (#0xfffffe00, s9) +fld f1, (#0xffffff00, s9) +fld f1, (#0xffffff80, s9) +fld f1, (#0xffffffc0, s9) +fld f1, (#0xffffffe0, s9) +fld f1, (#0xfffffff0, s9) +fld f1, (#0xfffffff8, s9) +fld f1, (#0xfffffffc, s9) +fld f1, (#0xfffffffe, s9) +fld f1, (#0xffffffff, s9) +fld f1, (#0, s9) +fld f1, (#1, s9) +fld f1, (#2, s9) +fld f1, (#4, s9) +fld f1, (#8, s9) +fld f1, (#0x10, s9) +fld f1, (#0x20, s9) +fld f1, (#0x40, s9) +fld f1, (#0x80, s9) +fld f1, (#0x100, s9) +fld f1, (#0x200, s9) +fld f1, (#0x400, s9) +fld f1, (#0x7ff, s9) +fld f1, (#0xfffff801, t6) +fld f1, (#0xfffffc00, t6) +fld f1, (#0xfffffe00, t6) +fld f1, (#0xffffff00, t6) +fld f1, (#0xffffff80, t6) +fld f1, (#0xffffffc0, t6) +fld f1, (#0xffffffe0, t6) +fld f1, (#0xfffffff0, t6) +fld f1, (#0xfffffff8, t6) +fld f1, (#0xfffffffc, t6) +fld f1, (#0xfffffffe, t6) +fld f1, (#0xffffffff, t6) +fld f1, (#0, t6) +fld f1, (#1, t6) +fld f1, (#2, t6) +fld f1, (#4, t6) +fld f1, (#8, t6) +fld f1, (#0x10, t6) +fld f1, (#0x20, t6) +fld f1, (#0x40, t6) +fld f1, (#0x80, t6) +fld f1, (#0x100, t6) +fld f1, (#0x200, t6) +fld f1, (#0x400, t6) +fld f1, (#0x7ff, t6) +fld f5, (#0xfffff801, zero) +fld f5, (#0xfffffc00, zero) +fld f5, (#0xfffffe00, zero) +fld f5, (#0xffffff00, zero) +fld f5, (#0xffffff80, zero) +fld f5, (#0xffffffc0, zero) +fld f5, (#0xffffffe0, zero) +fld f5, (#0xfffffff0, zero) +fld f5, (#0xfffffff8, zero) +fld f5, (#0xfffffffc, zero) +fld f5, (#0xfffffffe, zero) +fld f5, (#0xffffffff, zero) +fld f5, (#0, zero) +fld f5, (#1, zero) +fld f5, (#2, zero) +fld f5, (#4, zero) +fld f5, (#8, zero) +fld f5, (#0x10, zero) +fld f5, (#0x20, zero) +fld f5, (#0x40, zero) +fld f5, (#0x80, zero) +fld f5, (#0x100, zero) +fld f5, (#0x200, zero) +fld f5, (#0x400, zero) +fld f5, (#0x7ff, zero) +fld f5, (#0xfffff801, ra) +fld f5, (#0xfffffc00, ra) +fld f5, (#0xfffffe00, ra) +fld f5, (#0xffffff00, ra) +fld f5, (#0xffffff80, ra) +fld f5, (#0xffffffc0, ra) +fld f5, (#0xffffffe0, ra) +fld f5, (#0xfffffff0, ra) +fld f5, (#0xfffffff8, ra) +fld f5, (#0xfffffffc, ra) +fld f5, (#0xfffffffe, ra) +fld f5, (#0xffffffff, ra) +fld f5, (#0, ra) +fld f5, (#1, ra) +fld f5, (#2, ra) +fld f5, (#4, ra) +fld f5, (#8, ra) +fld f5, (#0x10, ra) +fld f5, (#0x20, ra) +fld f5, (#0x40, ra) +fld f5, (#0x80, ra) +fld f5, (#0x100, ra) +fld f5, (#0x200, ra) +fld f5, (#0x400, ra) +fld f5, (#0x7ff, ra) +fld f5, (#0xfffff801, t0) +fld f5, (#0xfffffc00, t0) +fld f5, (#0xfffffe00, t0) +fld f5, (#0xffffff00, t0) +fld f5, (#0xffffff80, t0) +fld f5, (#0xffffffc0, t0) +fld f5, (#0xffffffe0, t0) +fld f5, (#0xfffffff0, t0) +fld f5, (#0xfffffff8, t0) +fld f5, (#0xfffffffc, t0) +fld f5, (#0xfffffffe, t0) +fld f5, (#0xffffffff, t0) +fld f5, (#0, t0) +fld f5, (#1, t0) +fld f5, (#2, t0) +fld f5, (#4, t0) +fld f5, (#8, t0) +fld f5, (#0x10, t0) +fld f5, (#0x20, t0) +fld f5, (#0x40, t0) +fld f5, (#0x80, t0) +fld f5, (#0x100, t0) +fld f5, (#0x200, t0) +fld f5, (#0x400, t0) +fld f5, (#0x7ff, t0) +fld f5, (#0xfffff801, a0) +fld f5, (#0xfffffc00, a0) +fld f5, (#0xfffffe00, a0) +fld f5, (#0xffffff00, a0) +fld f5, (#0xffffff80, a0) +fld f5, (#0xffffffc0, a0) +fld f5, (#0xffffffe0, a0) +fld f5, (#0xfffffff0, a0) +fld f5, (#0xfffffff8, a0) +fld f5, (#0xfffffffc, a0) +fld f5, (#0xfffffffe, a0) +fld f5, (#0xffffffff, a0) +fld f5, (#0, a0) +fld f5, (#1, a0) +fld f5, (#2, a0) +fld f5, (#4, a0) +fld f5, (#8, a0) +fld f5, (#0x10, a0) +fld f5, (#0x20, a0) +fld f5, (#0x40, a0) +fld f5, (#0x80, a0) +fld f5, (#0x100, a0) +fld f5, (#0x200, a0) +fld f5, (#0x400, a0) +fld f5, (#0x7ff, a0) +fld f5, (#0xfffff801, a5) +fld f5, (#0xfffffc00, a5) +fld f5, (#0xfffffe00, a5) +fld f5, (#0xffffff00, a5) +fld f5, (#0xffffff80, a5) +fld f5, (#0xffffffc0, a5) +fld f5, (#0xffffffe0, a5) +fld f5, (#0xfffffff0, a5) +fld f5, (#0xfffffff8, a5) +fld f5, (#0xfffffffc, a5) +fld f5, (#0xfffffffe, a5) +fld f5, (#0xffffffff, a5) +fld f5, (#0, a5) +fld f5, (#1, a5) +fld f5, (#2, a5) +fld f5, (#4, a5) +fld f5, (#8, a5) +fld f5, (#0x10, a5) +fld f5, (#0x20, a5) +fld f5, (#0x40, a5) +fld f5, (#0x80, a5) +fld f5, (#0x100, a5) +fld f5, (#0x200, a5) +fld f5, (#0x400, a5) +fld f5, (#0x7ff, a5) +fld f5, (#0xfffff801, s4) +fld f5, (#0xfffffc00, s4) +fld f5, (#0xfffffe00, s4) +fld f5, (#0xffffff00, s4) +fld f5, (#0xffffff80, s4) +fld f5, (#0xffffffc0, s4) +fld f5, (#0xffffffe0, s4) +fld f5, (#0xfffffff0, s4) +fld f5, (#0xfffffff8, s4) +fld f5, (#0xfffffffc, s4) +fld f5, (#0xfffffffe, s4) +fld f5, (#0xffffffff, s4) +fld f5, (#0, s4) +fld f5, (#1, s4) +fld f5, (#2, s4) +fld f5, (#4, s4) +fld f5, (#8, s4) +fld f5, (#0x10, s4) +fld f5, (#0x20, s4) +fld f5, (#0x40, s4) +fld f5, (#0x80, s4) +fld f5, (#0x100, s4) +fld f5, (#0x200, s4) +fld f5, (#0x400, s4) +fld f5, (#0x7ff, s4) +fld f5, (#0xfffff801, s9) +fld f5, (#0xfffffc00, s9) +fld f5, (#0xfffffe00, s9) +fld f5, (#0xffffff00, s9) +fld f5, (#0xffffff80, s9) +fld f5, (#0xffffffc0, s9) +fld f5, (#0xffffffe0, s9) +fld f5, (#0xfffffff0, s9) +fld f5, (#0xfffffff8, s9) +fld f5, (#0xfffffffc, s9) +fld f5, (#0xfffffffe, s9) +fld f5, (#0xffffffff, s9) +fld f5, (#0, s9) +fld f5, (#1, s9) +fld f5, (#2, s9) +fld f5, (#4, s9) +fld f5, (#8, s9) +fld f5, (#0x10, s9) +fld f5, (#0x20, s9) +fld f5, (#0x40, s9) +fld f5, (#0x80, s9) +fld f5, (#0x100, s9) +fld f5, (#0x200, s9) +fld f5, (#0x400, s9) +fld f5, (#0x7ff, s9) +fld f5, (#0xfffff801, t6) +fld f5, (#0xfffffc00, t6) +fld f5, (#0xfffffe00, t6) +fld f5, (#0xffffff00, t6) +fld f5, (#0xffffff80, t6) +fld f5, (#0xffffffc0, t6) +fld f5, (#0xffffffe0, t6) +fld f5, (#0xfffffff0, t6) +fld f5, (#0xfffffff8, t6) +fld f5, (#0xfffffffc, t6) +fld f5, (#0xfffffffe, t6) +fld f5, (#0xffffffff, t6) +fld f5, (#0, t6) +fld f5, (#1, t6) +fld f5, (#2, t6) +fld f5, (#4, t6) +fld f5, (#8, t6) +fld f5, (#0x10, t6) +fld f5, (#0x20, t6) +fld f5, (#0x40, t6) +fld f5, (#0x80, t6) +fld f5, (#0x100, t6) +fld f5, (#0x200, t6) +fld f5, (#0x400, t6) +fld f5, (#0x7ff, t6) +fld f10, (#0xfffff801, zero) +fld f10, (#0xfffffc00, zero) +fld f10, (#0xfffffe00, zero) +fld f10, (#0xffffff00, zero) +fld f10, (#0xffffff80, zero) +fld f10, (#0xffffffc0, zero) +fld f10, (#0xffffffe0, zero) +fld f10, (#0xfffffff0, zero) +fld f10, (#0xfffffff8, zero) +fld f10, (#0xfffffffc, zero) +fld f10, (#0xfffffffe, zero) +fld f10, (#0xffffffff, zero) +fld f10, (#0, zero) +fld f10, (#1, zero) +fld f10, (#2, zero) +fld f10, (#4, zero) +fld f10, (#8, zero) +fld f10, (#0x10, zero) +fld f10, (#0x20, zero) +fld f10, (#0x40, zero) +fld f10, (#0x80, zero) +fld f10, (#0x100, zero) +fld f10, (#0x200, zero) +fld f10, (#0x400, zero) +fld f10, (#0x7ff, zero) +fld f10, (#0xfffff801, ra) +fld f10, (#0xfffffc00, ra) +fld f10, (#0xfffffe00, ra) +fld f10, (#0xffffff00, ra) +fld f10, (#0xffffff80, ra) +fld f10, (#0xffffffc0, ra) +fld f10, (#0xffffffe0, ra) +fld f10, (#0xfffffff0, ra) +fld f10, (#0xfffffff8, ra) +fld f10, (#0xfffffffc, ra) +fld f10, (#0xfffffffe, ra) +fld f10, (#0xffffffff, ra) +fld f10, (#0, ra) +fld f10, (#1, ra) +fld f10, (#2, ra) +fld f10, (#4, ra) +fld f10, (#8, ra) +fld f10, (#0x10, ra) +fld f10, (#0x20, ra) +fld f10, (#0x40, ra) +fld f10, (#0x80, ra) +fld f10, (#0x100, ra) +fld f10, (#0x200, ra) +fld f10, (#0x400, ra) +fld f10, (#0x7ff, ra) +fld f10, (#0xfffff801, t0) +fld f10, (#0xfffffc00, t0) +fld f10, (#0xfffffe00, t0) +fld f10, (#0xffffff00, t0) +fld f10, (#0xffffff80, t0) +fld f10, (#0xffffffc0, t0) +fld f10, (#0xffffffe0, t0) +fld f10, (#0xfffffff0, t0) +fld f10, (#0xfffffff8, t0) +fld f10, (#0xfffffffc, t0) +fld f10, (#0xfffffffe, t0) +fld f10, (#0xffffffff, t0) +fld f10, (#0, t0) +fld f10, (#1, t0) +fld f10, (#2, t0) +fld f10, (#4, t0) +fld f10, (#8, t0) +fld f10, (#0x10, t0) +fld f10, (#0x20, t0) +fld f10, (#0x40, t0) +fld f10, (#0x80, t0) +fld f10, (#0x100, t0) +fld f10, (#0x200, t0) +fld f10, (#0x400, t0) +fld f10, (#0x7ff, t0) +fld f10, (#0xfffff801, a0) +fld f10, (#0xfffffc00, a0) +fld f10, (#0xfffffe00, a0) +fld f10, (#0xffffff00, a0) +fld f10, (#0xffffff80, a0) +fld f10, (#0xffffffc0, a0) +fld f10, (#0xffffffe0, a0) +fld f10, (#0xfffffff0, a0) +fld f10, (#0xfffffff8, a0) +fld f10, (#0xfffffffc, a0) +fld f10, (#0xfffffffe, a0) +fld f10, (#0xffffffff, a0) +fld f10, (#0, a0) +fld f10, (#1, a0) +fld f10, (#2, a0) +fld f10, (#4, a0) +fld f10, (#8, a0) +fld f10, (#0x10, a0) +fld f10, (#0x20, a0) +fld f10, (#0x40, a0) +fld f10, (#0x80, a0) +fld f10, (#0x100, a0) +fld f10, (#0x200, a0) +fld f10, (#0x400, a0) +fld f10, (#0x7ff, a0) +fld f10, (#0xfffff801, a5) +fld f10, (#0xfffffc00, a5) +fld f10, (#0xfffffe00, a5) +fld f10, (#0xffffff00, a5) +fld f10, (#0xffffff80, a5) +fld f10, (#0xffffffc0, a5) +fld f10, (#0xffffffe0, a5) +fld f10, (#0xfffffff0, a5) +fld f10, (#0xfffffff8, a5) +fld f10, (#0xfffffffc, a5) +fld f10, (#0xfffffffe, a5) +fld f10, (#0xffffffff, a5) +fld f10, (#0, a5) +fld f10, (#1, a5) +fld f10, (#2, a5) +fld f10, (#4, a5) +fld f10, (#8, a5) +fld f10, (#0x10, a5) +fld f10, (#0x20, a5) +fld f10, (#0x40, a5) +fld f10, (#0x80, a5) +fld f10, (#0x100, a5) +fld f10, (#0x200, a5) +fld f10, (#0x400, a5) +fld f10, (#0x7ff, a5) +fld f10, (#0xfffff801, s4) +fld f10, (#0xfffffc00, s4) +fld f10, (#0xfffffe00, s4) +fld f10, (#0xffffff00, s4) +fld f10, (#0xffffff80, s4) +fld f10, (#0xffffffc0, s4) +fld f10, (#0xffffffe0, s4) +fld f10, (#0xfffffff0, s4) +fld f10, (#0xfffffff8, s4) +fld f10, (#0xfffffffc, s4) +fld f10, (#0xfffffffe, s4) +fld f10, (#0xffffffff, s4) +fld f10, (#0, s4) +fld f10, (#1, s4) +fld f10, (#2, s4) +fld f10, (#4, s4) +fld f10, (#8, s4) +fld f10, (#0x10, s4) +fld f10, (#0x20, s4) +fld f10, (#0x40, s4) +fld f10, (#0x80, s4) +fld f10, (#0x100, s4) +fld f10, (#0x200, s4) +fld f10, (#0x400, s4) +fld f10, (#0x7ff, s4) +fld f10, (#0xfffff801, s9) +fld f10, (#0xfffffc00, s9) +fld f10, (#0xfffffe00, s9) +fld f10, (#0xffffff00, s9) +fld f10, (#0xffffff80, s9) +fld f10, (#0xffffffc0, s9) +fld f10, (#0xffffffe0, s9) +fld f10, (#0xfffffff0, s9) +fld f10, (#0xfffffff8, s9) +fld f10, (#0xfffffffc, s9) +fld f10, (#0xfffffffe, s9) +fld f10, (#0xffffffff, s9) +fld f10, (#0, s9) +fld f10, (#1, s9) +fld f10, (#2, s9) +fld f10, (#4, s9) +fld f10, (#8, s9) +fld f10, (#0x10, s9) +fld f10, (#0x20, s9) +fld f10, (#0x40, s9) +fld f10, (#0x80, s9) +fld f10, (#0x100, s9) +fld f10, (#0x200, s9) +fld f10, (#0x400, s9) +fld f10, (#0x7ff, s9) +fld f10, (#0xfffff801, t6) +fld f10, (#0xfffffc00, t6) +fld f10, (#0xfffffe00, t6) +fld f10, (#0xffffff00, t6) +fld f10, (#0xffffff80, t6) +fld f10, (#0xffffffc0, t6) +fld f10, (#0xffffffe0, t6) +fld f10, (#0xfffffff0, t6) +fld f10, (#0xfffffff8, t6) +fld f10, (#0xfffffffc, t6) +fld f10, (#0xfffffffe, t6) +fld f10, (#0xffffffff, t6) +fld f10, (#0, t6) +fld f10, (#1, t6) +fld f10, (#2, t6) +fld f10, (#4, t6) +fld f10, (#8, t6) +fld f10, (#0x10, t6) +fld f10, (#0x20, t6) +fld f10, (#0x40, t6) +fld f10, (#0x80, t6) +fld f10, (#0x100, t6) +fld f10, (#0x200, t6) +fld f10, (#0x400, t6) +fld f10, (#0x7ff, t6) +fld f15, (#0xfffff801, zero) +fld f15, (#0xfffffc00, zero) +fld f15, (#0xfffffe00, zero) +fld f15, (#0xffffff00, zero) +fld f15, (#0xffffff80, zero) +fld f15, (#0xffffffc0, zero) +fld f15, (#0xffffffe0, zero) +fld f15, (#0xfffffff0, zero) +fld f15, (#0xfffffff8, zero) +fld f15, (#0xfffffffc, zero) +fld f15, (#0xfffffffe, zero) +fld f15, (#0xffffffff, zero) +fld f15, (#0, zero) +fld f15, (#1, zero) +fld f15, (#2, zero) +fld f15, (#4, zero) +fld f15, (#8, zero) +fld f15, (#0x10, zero) +fld f15, (#0x20, zero) +fld f15, (#0x40, zero) +fld f15, (#0x80, zero) +fld f15, (#0x100, zero) +fld f15, (#0x200, zero) +fld f15, (#0x400, zero) +fld f15, (#0x7ff, zero) +fld f15, (#0xfffff801, ra) +fld f15, (#0xfffffc00, ra) +fld f15, (#0xfffffe00, ra) +fld f15, (#0xffffff00, ra) +fld f15, (#0xffffff80, ra) +fld f15, (#0xffffffc0, ra) +fld f15, (#0xffffffe0, ra) +fld f15, (#0xfffffff0, ra) +fld f15, (#0xfffffff8, ra) +fld f15, (#0xfffffffc, ra) +fld f15, (#0xfffffffe, ra) +fld f15, (#0xffffffff, ra) +fld f15, (#0, ra) +fld f15, (#1, ra) +fld f15, (#2, ra) +fld f15, (#4, ra) +fld f15, (#8, ra) +fld f15, (#0x10, ra) +fld f15, (#0x20, ra) +fld f15, (#0x40, ra) +fld f15, (#0x80, ra) +fld f15, (#0x100, ra) +fld f15, (#0x200, ra) +fld f15, (#0x400, ra) +fld f15, (#0x7ff, ra) +fld f15, (#0xfffff801, t0) +fld f15, (#0xfffffc00, t0) +fld f15, (#0xfffffe00, t0) +fld f15, (#0xffffff00, t0) +fld f15, (#0xffffff80, t0) +fld f15, (#0xffffffc0, t0) +fld f15, (#0xffffffe0, t0) +fld f15, (#0xfffffff0, t0) +fld f15, (#0xfffffff8, t0) +fld f15, (#0xfffffffc, t0) +fld f15, (#0xfffffffe, t0) +fld f15, (#0xffffffff, t0) +fld f15, (#0, t0) +fld f15, (#1, t0) +fld f15, (#2, t0) +fld f15, (#4, t0) +fld f15, (#8, t0) +fld f15, (#0x10, t0) +fld f15, (#0x20, t0) +fld f15, (#0x40, t0) +fld f15, (#0x80, t0) +fld f15, (#0x100, t0) +fld f15, (#0x200, t0) +fld f15, (#0x400, t0) +fld f15, (#0x7ff, t0) +fld f15, (#0xfffff801, a0) +fld f15, (#0xfffffc00, a0) +fld f15, (#0xfffffe00, a0) +fld f15, (#0xffffff00, a0) +fld f15, (#0xffffff80, a0) +fld f15, (#0xffffffc0, a0) +fld f15, (#0xffffffe0, a0) +fld f15, (#0xfffffff0, a0) +fld f15, (#0xfffffff8, a0) +fld f15, (#0xfffffffc, a0) +fld f15, (#0xfffffffe, a0) +fld f15, (#0xffffffff, a0) +fld f15, (#0, a0) +fld f15, (#1, a0) +fld f15, (#2, a0) +fld f15, (#4, a0) +fld f15, (#8, a0) +fld f15, (#0x10, a0) +fld f15, (#0x20, a0) +fld f15, (#0x40, a0) +fld f15, (#0x80, a0) +fld f15, (#0x100, a0) +fld f15, (#0x200, a0) +fld f15, (#0x400, a0) +fld f15, (#0x7ff, a0) +fld f15, (#0xfffff801, a5) +fld f15, (#0xfffffc00, a5) +fld f15, (#0xfffffe00, a5) +fld f15, (#0xffffff00, a5) +fld f15, (#0xffffff80, a5) +fld f15, (#0xffffffc0, a5) +fld f15, (#0xffffffe0, a5) +fld f15, (#0xfffffff0, a5) +fld f15, (#0xfffffff8, a5) +fld f15, (#0xfffffffc, a5) +fld f15, (#0xfffffffe, a5) +fld f15, (#0xffffffff, a5) +fld f15, (#0, a5) +fld f15, (#1, a5) +fld f15, (#2, a5) +fld f15, (#4, a5) +fld f15, (#8, a5) +fld f15, (#0x10, a5) +fld f15, (#0x20, a5) +fld f15, (#0x40, a5) +fld f15, (#0x80, a5) +fld f15, (#0x100, a5) +fld f15, (#0x200, a5) +fld f15, (#0x400, a5) +fld f15, (#0x7ff, a5) +fld f15, (#0xfffff801, s4) +fld f15, (#0xfffffc00, s4) +fld f15, (#0xfffffe00, s4) +fld f15, (#0xffffff00, s4) +fld f15, (#0xffffff80, s4) +fld f15, (#0xffffffc0, s4) +fld f15, (#0xffffffe0, s4) +fld f15, (#0xfffffff0, s4) +fld f15, (#0xfffffff8, s4) +fld f15, (#0xfffffffc, s4) +fld f15, (#0xfffffffe, s4) +fld f15, (#0xffffffff, s4) +fld f15, (#0, s4) +fld f15, (#1, s4) +fld f15, (#2, s4) +fld f15, (#4, s4) +fld f15, (#8, s4) +fld f15, (#0x10, s4) +fld f15, (#0x20, s4) +fld f15, (#0x40, s4) +fld f15, (#0x80, s4) +fld f15, (#0x100, s4) +fld f15, (#0x200, s4) +fld f15, (#0x400, s4) +fld f15, (#0x7ff, s4) +fld f15, (#0xfffff801, s9) +fld f15, (#0xfffffc00, s9) +fld f15, (#0xfffffe00, s9) +fld f15, (#0xffffff00, s9) +fld f15, (#0xffffff80, s9) +fld f15, (#0xffffffc0, s9) +fld f15, (#0xffffffe0, s9) +fld f15, (#0xfffffff0, s9) +fld f15, (#0xfffffff8, s9) +fld f15, (#0xfffffffc, s9) +fld f15, (#0xfffffffe, s9) +fld f15, (#0xffffffff, s9) +fld f15, (#0, s9) +fld f15, (#1, s9) +fld f15, (#2, s9) +fld f15, (#4, s9) +fld f15, (#8, s9) +fld f15, (#0x10, s9) +fld f15, (#0x20, s9) +fld f15, (#0x40, s9) +fld f15, (#0x80, s9) +fld f15, (#0x100, s9) +fld f15, (#0x200, s9) +fld f15, (#0x400, s9) +fld f15, (#0x7ff, s9) +fld f15, (#0xfffff801, t6) +fld f15, (#0xfffffc00, t6) +fld f15, (#0xfffffe00, t6) +fld f15, (#0xffffff00, t6) +fld f15, (#0xffffff80, t6) +fld f15, (#0xffffffc0, t6) +fld f15, (#0xffffffe0, t6) +fld f15, (#0xfffffff0, t6) +fld f15, (#0xfffffff8, t6) +fld f15, (#0xfffffffc, t6) +fld f15, (#0xfffffffe, t6) +fld f15, (#0xffffffff, t6) +fld f15, (#0, t6) +fld f15, (#1, t6) +fld f15, (#2, t6) +fld f15, (#4, t6) +fld f15, (#8, t6) +fld f15, (#0x10, t6) +fld f15, (#0x20, t6) +fld f15, (#0x40, t6) +fld f15, (#0x80, t6) +fld f15, (#0x100, t6) +fld f15, (#0x200, t6) +fld f15, (#0x400, t6) +fld f15, (#0x7ff, t6) +fld f20, (#0xfffff801, zero) +fld f20, (#0xfffffc00, zero) +fld f20, (#0xfffffe00, zero) +fld f20, (#0xffffff00, zero) +fld f20, (#0xffffff80, zero) +fld f20, (#0xffffffc0, zero) +fld f20, (#0xffffffe0, zero) +fld f20, (#0xfffffff0, zero) +fld f20, (#0xfffffff8, zero) +fld f20, (#0xfffffffc, zero) +fld f20, (#0xfffffffe, zero) +fld f20, (#0xffffffff, zero) +fld f20, (#0, zero) +fld f20, (#1, zero) +fld f20, (#2, zero) +fld f20, (#4, zero) +fld f20, (#8, zero) +fld f20, (#0x10, zero) +fld f20, (#0x20, zero) +fld f20, (#0x40, zero) +fld f20, (#0x80, zero) +fld f20, (#0x100, zero) +fld f20, (#0x200, zero) +fld f20, (#0x400, zero) +fld f20, (#0x7ff, zero) +fld f20, (#0xfffff801, ra) +fld f20, (#0xfffffc00, ra) +fld f20, (#0xfffffe00, ra) +fld f20, (#0xffffff00, ra) +fld f20, (#0xffffff80, ra) +fld f20, (#0xffffffc0, ra) +fld f20, (#0xffffffe0, ra) +fld f20, (#0xfffffff0, ra) +fld f20, (#0xfffffff8, ra) +fld f20, (#0xfffffffc, ra) +fld f20, (#0xfffffffe, ra) +fld f20, (#0xffffffff, ra) +fld f20, (#0, ra) +fld f20, (#1, ra) +fld f20, (#2, ra) +fld f20, (#4, ra) +fld f20, (#8, ra) +fld f20, (#0x10, ra) +fld f20, (#0x20, ra) +fld f20, (#0x40, ra) +fld f20, (#0x80, ra) +fld f20, (#0x100, ra) +fld f20, (#0x200, ra) +fld f20, (#0x400, ra) +fld f20, (#0x7ff, ra) +fld f20, (#0xfffff801, t0) +fld f20, (#0xfffffc00, t0) +fld f20, (#0xfffffe00, t0) +fld f20, (#0xffffff00, t0) +fld f20, (#0xffffff80, t0) +fld f20, (#0xffffffc0, t0) +fld f20, (#0xffffffe0, t0) +fld f20, (#0xfffffff0, t0) +fld f20, (#0xfffffff8, t0) +fld f20, (#0xfffffffc, t0) +fld f20, (#0xfffffffe, t0) +fld f20, (#0xffffffff, t0) +fld f20, (#0, t0) +fld f20, (#1, t0) +fld f20, (#2, t0) +fld f20, (#4, t0) +fld f20, (#8, t0) +fld f20, (#0x10, t0) +fld f20, (#0x20, t0) +fld f20, (#0x40, t0) +fld f20, (#0x80, t0) +fld f20, (#0x100, t0) +fld f20, (#0x200, t0) +fld f20, (#0x400, t0) +fld f20, (#0x7ff, t0) +fld f20, (#0xfffff801, a0) +fld f20, (#0xfffffc00, a0) +fld f20, (#0xfffffe00, a0) +fld f20, (#0xffffff00, a0) +fld f20, (#0xffffff80, a0) +fld f20, (#0xffffffc0, a0) +fld f20, (#0xffffffe0, a0) +fld f20, (#0xfffffff0, a0) +fld f20, (#0xfffffff8, a0) +fld f20, (#0xfffffffc, a0) +fld f20, (#0xfffffffe, a0) +fld f20, (#0xffffffff, a0) +fld f20, (#0, a0) +fld f20, (#1, a0) +fld f20, (#2, a0) +fld f20, (#4, a0) +fld f20, (#8, a0) +fld f20, (#0x10, a0) +fld f20, (#0x20, a0) +fld f20, (#0x40, a0) +fld f20, (#0x80, a0) +fld f20, (#0x100, a0) +fld f20, (#0x200, a0) +fld f20, (#0x400, a0) +fld f20, (#0x7ff, a0) +fld f20, (#0xfffff801, a5) +fld f20, (#0xfffffc00, a5) +fld f20, (#0xfffffe00, a5) +fld f20, (#0xffffff00, a5) +fld f20, (#0xffffff80, a5) +fld f20, (#0xffffffc0, a5) +fld f20, (#0xffffffe0, a5) +fld f20, (#0xfffffff0, a5) +fld f20, (#0xfffffff8, a5) +fld f20, (#0xfffffffc, a5) +fld f20, (#0xfffffffe, a5) +fld f20, (#0xffffffff, a5) +fld f20, (#0, a5) +fld f20, (#1, a5) +fld f20, (#2, a5) +fld f20, (#4, a5) +fld f20, (#8, a5) +fld f20, (#0x10, a5) +fld f20, (#0x20, a5) +fld f20, (#0x40, a5) +fld f20, (#0x80, a5) +fld f20, (#0x100, a5) +fld f20, (#0x200, a5) +fld f20, (#0x400, a5) +fld f20, (#0x7ff, a5) +fld f20, (#0xfffff801, s4) +fld f20, (#0xfffffc00, s4) +fld f20, (#0xfffffe00, s4) +fld f20, (#0xffffff00, s4) +fld f20, (#0xffffff80, s4) +fld f20, (#0xffffffc0, s4) +fld f20, (#0xffffffe0, s4) +fld f20, (#0xfffffff0, s4) +fld f20, (#0xfffffff8, s4) +fld f20, (#0xfffffffc, s4) +fld f20, (#0xfffffffe, s4) +fld f20, (#0xffffffff, s4) +fld f20, (#0, s4) +fld f20, (#1, s4) +fld f20, (#2, s4) +fld f20, (#4, s4) +fld f20, (#8, s4) +fld f20, (#0x10, s4) +fld f20, (#0x20, s4) +fld f20, (#0x40, s4) +fld f20, (#0x80, s4) +fld f20, (#0x100, s4) +fld f20, (#0x200, s4) +fld f20, (#0x400, s4) +fld f20, (#0x7ff, s4) +fld f20, (#0xfffff801, s9) +fld f20, (#0xfffffc00, s9) +fld f20, (#0xfffffe00, s9) +fld f20, (#0xffffff00, s9) +fld f20, (#0xffffff80, s9) +fld f20, (#0xffffffc0, s9) +fld f20, (#0xffffffe0, s9) +fld f20, (#0xfffffff0, s9) +fld f20, (#0xfffffff8, s9) +fld f20, (#0xfffffffc, s9) +fld f20, (#0xfffffffe, s9) +fld f20, (#0xffffffff, s9) +fld f20, (#0, s9) +fld f20, (#1, s9) +fld f20, (#2, s9) +fld f20, (#4, s9) +fld f20, (#8, s9) +fld f20, (#0x10, s9) +fld f20, (#0x20, s9) +fld f20, (#0x40, s9) +fld f20, (#0x80, s9) +fld f20, (#0x100, s9) +fld f20, (#0x200, s9) +fld f20, (#0x400, s9) +fld f20, (#0x7ff, s9) +fld f20, (#0xfffff801, t6) +fld f20, (#0xfffffc00, t6) +fld f20, (#0xfffffe00, t6) +fld f20, (#0xffffff00, t6) +fld f20, (#0xffffff80, t6) +fld f20, (#0xffffffc0, t6) +fld f20, (#0xffffffe0, t6) +fld f20, (#0xfffffff0, t6) +fld f20, (#0xfffffff8, t6) +fld f20, (#0xfffffffc, t6) +fld f20, (#0xfffffffe, t6) +fld f20, (#0xffffffff, t6) +fld f20, (#0, t6) +fld f20, (#1, t6) +fld f20, (#2, t6) +fld f20, (#4, t6) +fld f20, (#8, t6) +fld f20, (#0x10, t6) +fld f20, (#0x20, t6) +fld f20, (#0x40, t6) +fld f20, (#0x80, t6) +fld f20, (#0x100, t6) +fld f20, (#0x200, t6) +fld f20, (#0x400, t6) +fld f20, (#0x7ff, t6) +fld f25, (#0xfffff801, zero) +fld f25, (#0xfffffc00, zero) +fld f25, (#0xfffffe00, zero) +fld f25, (#0xffffff00, zero) +fld f25, (#0xffffff80, zero) +fld f25, (#0xffffffc0, zero) +fld f25, (#0xffffffe0, zero) +fld f25, (#0xfffffff0, zero) +fld f25, (#0xfffffff8, zero) +fld f25, (#0xfffffffc, zero) +fld f25, (#0xfffffffe, zero) +fld f25, (#0xffffffff, zero) +fld f25, (#0, zero) +fld f25, (#1, zero) +fld f25, (#2, zero) +fld f25, (#4, zero) +fld f25, (#8, zero) +fld f25, (#0x10, zero) +fld f25, (#0x20, zero) +fld f25, (#0x40, zero) +fld f25, (#0x80, zero) +fld f25, (#0x100, zero) +fld f25, (#0x200, zero) +fld f25, (#0x400, zero) +fld f25, (#0x7ff, zero) +fld f25, (#0xfffff801, ra) +fld f25, (#0xfffffc00, ra) +fld f25, (#0xfffffe00, ra) +fld f25, (#0xffffff00, ra) +fld f25, (#0xffffff80, ra) +fld f25, (#0xffffffc0, ra) +fld f25, (#0xffffffe0, ra) +fld f25, (#0xfffffff0, ra) +fld f25, (#0xfffffff8, ra) +fld f25, (#0xfffffffc, ra) +fld f25, (#0xfffffffe, ra) +fld f25, (#0xffffffff, ra) +fld f25, (#0, ra) +fld f25, (#1, ra) +fld f25, (#2, ra) +fld f25, (#4, ra) +fld f25, (#8, ra) +fld f25, (#0x10, ra) +fld f25, (#0x20, ra) +fld f25, (#0x40, ra) +fld f25, (#0x80, ra) +fld f25, (#0x100, ra) +fld f25, (#0x200, ra) +fld f25, (#0x400, ra) +fld f25, (#0x7ff, ra) +fld f25, (#0xfffff801, t0) +fld f25, (#0xfffffc00, t0) +fld f25, (#0xfffffe00, t0) +fld f25, (#0xffffff00, t0) +fld f25, (#0xffffff80, t0) +fld f25, (#0xffffffc0, t0) +fld f25, (#0xffffffe0, t0) +fld f25, (#0xfffffff0, t0) +fld f25, (#0xfffffff8, t0) +fld f25, (#0xfffffffc, t0) +fld f25, (#0xfffffffe, t0) +fld f25, (#0xffffffff, t0) +fld f25, (#0, t0) +fld f25, (#1, t0) +fld f25, (#2, t0) +fld f25, (#4, t0) +fld f25, (#8, t0) +fld f25, (#0x10, t0) +fld f25, (#0x20, t0) +fld f25, (#0x40, t0) +fld f25, (#0x80, t0) +fld f25, (#0x100, t0) +fld f25, (#0x200, t0) +fld f25, (#0x400, t0) +fld f25, (#0x7ff, t0) +fld f25, (#0xfffff801, a0) +fld f25, (#0xfffffc00, a0) +fld f25, (#0xfffffe00, a0) +fld f25, (#0xffffff00, a0) +fld f25, (#0xffffff80, a0) +fld f25, (#0xffffffc0, a0) +fld f25, (#0xffffffe0, a0) +fld f25, (#0xfffffff0, a0) +fld f25, (#0xfffffff8, a0) +fld f25, (#0xfffffffc, a0) +fld f25, (#0xfffffffe, a0) +fld f25, (#0xffffffff, a0) +fld f25, (#0, a0) +fld f25, (#1, a0) +fld f25, (#2, a0) +fld f25, (#4, a0) +fld f25, (#8, a0) +fld f25, (#0x10, a0) +fld f25, (#0x20, a0) +fld f25, (#0x40, a0) +fld f25, (#0x80, a0) +fld f25, (#0x100, a0) +fld f25, (#0x200, a0) +fld f25, (#0x400, a0) +fld f25, (#0x7ff, a0) +fld f25, (#0xfffff801, a5) +fld f25, (#0xfffffc00, a5) +fld f25, (#0xfffffe00, a5) +fld f25, (#0xffffff00, a5) +fld f25, (#0xffffff80, a5) +fld f25, (#0xffffffc0, a5) +fld f25, (#0xffffffe0, a5) +fld f25, (#0xfffffff0, a5) +fld f25, (#0xfffffff8, a5) +fld f25, (#0xfffffffc, a5) +fld f25, (#0xfffffffe, a5) +fld f25, (#0xffffffff, a5) +fld f25, (#0, a5) +fld f25, (#1, a5) +fld f25, (#2, a5) +fld f25, (#4, a5) +fld f25, (#8, a5) +fld f25, (#0x10, a5) +fld f25, (#0x20, a5) +fld f25, (#0x40, a5) +fld f25, (#0x80, a5) +fld f25, (#0x100, a5) +fld f25, (#0x200, a5) +fld f25, (#0x400, a5) +fld f25, (#0x7ff, a5) +fld f25, (#0xfffff801, s4) +fld f25, (#0xfffffc00, s4) +fld f25, (#0xfffffe00, s4) +fld f25, (#0xffffff00, s4) +fld f25, (#0xffffff80, s4) +fld f25, (#0xffffffc0, s4) +fld f25, (#0xffffffe0, s4) +fld f25, (#0xfffffff0, s4) +fld f25, (#0xfffffff8, s4) +fld f25, (#0xfffffffc, s4) +fld f25, (#0xfffffffe, s4) +fld f25, (#0xffffffff, s4) +fld f25, (#0, s4) +fld f25, (#1, s4) +fld f25, (#2, s4) +fld f25, (#4, s4) +fld f25, (#8, s4) +fld f25, (#0x10, s4) +fld f25, (#0x20, s4) +fld f25, (#0x40, s4) +fld f25, (#0x80, s4) +fld f25, (#0x100, s4) +fld f25, (#0x200, s4) +fld f25, (#0x400, s4) +fld f25, (#0x7ff, s4) +fld f25, (#0xfffff801, s9) +fld f25, (#0xfffffc00, s9) +fld f25, (#0xfffffe00, s9) +fld f25, (#0xffffff00, s9) +fld f25, (#0xffffff80, s9) +fld f25, (#0xffffffc0, s9) +fld f25, (#0xffffffe0, s9) +fld f25, (#0xfffffff0, s9) +fld f25, (#0xfffffff8, s9) +fld f25, (#0xfffffffc, s9) +fld f25, (#0xfffffffe, s9) +fld f25, (#0xffffffff, s9) +fld f25, (#0, s9) +fld f25, (#1, s9) +fld f25, (#2, s9) +fld f25, (#4, s9) +fld f25, (#8, s9) +fld f25, (#0x10, s9) +fld f25, (#0x20, s9) +fld f25, (#0x40, s9) +fld f25, (#0x80, s9) +fld f25, (#0x100, s9) +fld f25, (#0x200, s9) +fld f25, (#0x400, s9) +fld f25, (#0x7ff, s9) +fld f25, (#0xfffff801, t6) +fld f25, (#0xfffffc00, t6) +fld f25, (#0xfffffe00, t6) +fld f25, (#0xffffff00, t6) +fld f25, (#0xffffff80, t6) +fld f25, (#0xffffffc0, t6) +fld f25, (#0xffffffe0, t6) +fld f25, (#0xfffffff0, t6) +fld f25, (#0xfffffff8, t6) +fld f25, (#0xfffffffc, t6) +fld f25, (#0xfffffffe, t6) +fld f25, (#0xffffffff, t6) +fld f25, (#0, t6) +fld f25, (#1, t6) +fld f25, (#2, t6) +fld f25, (#4, t6) +fld f25, (#8, t6) +fld f25, (#0x10, t6) +fld f25, (#0x20, t6) +fld f25, (#0x40, t6) +fld f25, (#0x80, t6) +fld f25, (#0x100, t6) +fld f25, (#0x200, t6) +fld f25, (#0x400, t6) +fld f25, (#0x7ff, t6) +fld f31, (#0xfffff801, zero) +fld f31, (#0xfffffc00, zero) +fld f31, (#0xfffffe00, zero) +fld f31, (#0xffffff00, zero) +fld f31, (#0xffffff80, zero) +fld f31, (#0xffffffc0, zero) +fld f31, (#0xffffffe0, zero) +fld f31, (#0xfffffff0, zero) +fld f31, (#0xfffffff8, zero) +fld f31, (#0xfffffffc, zero) +fld f31, (#0xfffffffe, zero) +fld f31, (#0xffffffff, zero) +fld f31, (#0, zero) +fld f31, (#1, zero) +fld f31, (#2, zero) +fld f31, (#4, zero) +fld f31, (#8, zero) +fld f31, (#0x10, zero) +fld f31, (#0x20, zero) +fld f31, (#0x40, zero) +fld f31, (#0x80, zero) +fld f31, (#0x100, zero) +fld f31, (#0x200, zero) +fld f31, (#0x400, zero) +fld f31, (#0x7ff, zero) +fld f31, (#0xfffff801, ra) +fld f31, (#0xfffffc00, ra) +fld f31, (#0xfffffe00, ra) +fld f31, (#0xffffff00, ra) +fld f31, (#0xffffff80, ra) +fld f31, (#0xffffffc0, ra) +fld f31, (#0xffffffe0, ra) +fld f31, (#0xfffffff0, ra) +fld f31, (#0xfffffff8, ra) +fld f31, (#0xfffffffc, ra) +fld f31, (#0xfffffffe, ra) +fld f31, (#0xffffffff, ra) +fld f31, (#0, ra) +fld f31, (#1, ra) +fld f31, (#2, ra) +fld f31, (#4, ra) +fld f31, (#8, ra) +fld f31, (#0x10, ra) +fld f31, (#0x20, ra) +fld f31, (#0x40, ra) +fld f31, (#0x80, ra) +fld f31, (#0x100, ra) +fld f31, (#0x200, ra) +fld f31, (#0x400, ra) +fld f31, (#0x7ff, ra) +fld f31, (#0xfffff801, t0) +fld f31, (#0xfffffc00, t0) +fld f31, (#0xfffffe00, t0) +fld f31, (#0xffffff00, t0) +fld f31, (#0xffffff80, t0) +fld f31, (#0xffffffc0, t0) +fld f31, (#0xffffffe0, t0) +fld f31, (#0xfffffff0, t0) +fld f31, (#0xfffffff8, t0) +fld f31, (#0xfffffffc, t0) +fld f31, (#0xfffffffe, t0) +fld f31, (#0xffffffff, t0) +fld f31, (#0, t0) +fld f31, (#1, t0) +fld f31, (#2, t0) +fld f31, (#4, t0) +fld f31, (#8, t0) +fld f31, (#0x10, t0) +fld f31, (#0x20, t0) +fld f31, (#0x40, t0) +fld f31, (#0x80, t0) +fld f31, (#0x100, t0) +fld f31, (#0x200, t0) +fld f31, (#0x400, t0) +fld f31, (#0x7ff, t0) +fld f31, (#0xfffff801, a0) +fld f31, (#0xfffffc00, a0) +fld f31, (#0xfffffe00, a0) +fld f31, (#0xffffff00, a0) +fld f31, (#0xffffff80, a0) +fld f31, (#0xffffffc0, a0) +fld f31, (#0xffffffe0, a0) +fld f31, (#0xfffffff0, a0) +fld f31, (#0xfffffff8, a0) +fld f31, (#0xfffffffc, a0) +fld f31, (#0xfffffffe, a0) +fld f31, (#0xffffffff, a0) +fld f31, (#0, a0) +fld f31, (#1, a0) +fld f31, (#2, a0) +fld f31, (#4, a0) +fld f31, (#8, a0) +fld f31, (#0x10, a0) +fld f31, (#0x20, a0) +fld f31, (#0x40, a0) +fld f31, (#0x80, a0) +fld f31, (#0x100, a0) +fld f31, (#0x200, a0) +fld f31, (#0x400, a0) +fld f31, (#0x7ff, a0) +fld f31, (#0xfffff801, a5) +fld f31, (#0xfffffc00, a5) +fld f31, (#0xfffffe00, a5) +fld f31, (#0xffffff00, a5) +fld f31, (#0xffffff80, a5) +fld f31, (#0xffffffc0, a5) +fld f31, (#0xffffffe0, a5) +fld f31, (#0xfffffff0, a5) +fld f31, (#0xfffffff8, a5) +fld f31, (#0xfffffffc, a5) +fld f31, (#0xfffffffe, a5) +fld f31, (#0xffffffff, a5) +fld f31, (#0, a5) +fld f31, (#1, a5) +fld f31, (#2, a5) +fld f31, (#4, a5) +fld f31, (#8, a5) +fld f31, (#0x10, a5) +fld f31, (#0x20, a5) +fld f31, (#0x40, a5) +fld f31, (#0x80, a5) +fld f31, (#0x100, a5) +fld f31, (#0x200, a5) +fld f31, (#0x400, a5) +fld f31, (#0x7ff, a5) +fld f31, (#0xfffff801, s4) +fld f31, (#0xfffffc00, s4) +fld f31, (#0xfffffe00, s4) +fld f31, (#0xffffff00, s4) +fld f31, (#0xffffff80, s4) +fld f31, (#0xffffffc0, s4) +fld f31, (#0xffffffe0, s4) +fld f31, (#0xfffffff0, s4) +fld f31, (#0xfffffff8, s4) +fld f31, (#0xfffffffc, s4) +fld f31, (#0xfffffffe, s4) +fld f31, (#0xffffffff, s4) +fld f31, (#0, s4) +fld f31, (#1, s4) +fld f31, (#2, s4) +fld f31, (#4, s4) +fld f31, (#8, s4) +fld f31, (#0x10, s4) +fld f31, (#0x20, s4) +fld f31, (#0x40, s4) +fld f31, (#0x80, s4) +fld f31, (#0x100, s4) +fld f31, (#0x200, s4) +fld f31, (#0x400, s4) +fld f31, (#0x7ff, s4) +fld f31, (#0xfffff801, s9) +fld f31, (#0xfffffc00, s9) +fld f31, (#0xfffffe00, s9) +fld f31, (#0xffffff00, s9) +fld f31, (#0xffffff80, s9) +fld f31, (#0xffffffc0, s9) +fld f31, (#0xffffffe0, s9) +fld f31, (#0xfffffff0, s9) +fld f31, (#0xfffffff8, s9) +fld f31, (#0xfffffffc, s9) +fld f31, (#0xfffffffe, s9) +fld f31, (#0xffffffff, s9) +fld f31, (#0, s9) +fld f31, (#1, s9) +fld f31, (#2, s9) +fld f31, (#4, s9) +fld f31, (#8, s9) +fld f31, (#0x10, s9) +fld f31, (#0x20, s9) +fld f31, (#0x40, s9) +fld f31, (#0x80, s9) +fld f31, (#0x100, s9) +fld f31, (#0x200, s9) +fld f31, (#0x400, s9) +fld f31, (#0x7ff, s9) +fld f31, (#0xfffff801, t6) +fld f31, (#0xfffffc00, t6) +fld f31, (#0xfffffe00, t6) +fld f31, (#0xffffff00, t6) +fld f31, (#0xffffff80, t6) +fld f31, (#0xffffffc0, t6) +fld f31, (#0xffffffe0, t6) +fld f31, (#0xfffffff0, t6) +fld f31, (#0xfffffff8, t6) +fld f31, (#0xfffffffc, t6) +fld f31, (#0xfffffffe, t6) +fld f31, (#0xffffffff, t6) +fld f31, (#0, t6) +fld f31, (#1, t6) +fld f31, (#2, t6) +fld f31, (#4, t6) +fld f31, (#8, t6) +fld f31, (#0x10, t6) +fld f31, (#0x20, t6) +fld f31, (#0x40, t6) +fld f31, (#0x80, t6) +fld f31, (#0x100, t6) +fld f31, (#0x200, t6) +fld f31, (#0x400, t6) +fld f31, (#0x7ff, t6) diff --git a/tests/riscv/d-extension/fle.d.asm b/tests/riscv/d-extension/fle.d.asm new file mode 100644 index 0000000..0e37e5a --- /dev/null +++ b/tests/riscv/d-extension/fle.d.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fle.d zero, f0, f0 +fle.d zero, f0, f1 +fle.d zero, f0, f5 +fle.d zero, f0, f10 +fle.d zero, f0, f15 +fle.d zero, f0, f20 +fle.d zero, f0, f25 +fle.d zero, f0, f31 +fle.d zero, f1, f0 +fle.d zero, f1, f1 +fle.d zero, f1, f5 +fle.d zero, f1, f10 +fle.d zero, f1, f15 +fle.d zero, f1, f20 +fle.d zero, f1, f25 +fle.d zero, f1, f31 +fle.d zero, f5, f0 +fle.d zero, f5, f1 +fle.d zero, f5, f5 +fle.d zero, f5, f10 +fle.d zero, f5, f15 +fle.d zero, f5, f20 +fle.d zero, f5, f25 +fle.d zero, f5, f31 +fle.d zero, f10, f0 +fle.d zero, f10, f1 +fle.d zero, f10, f5 +fle.d zero, f10, f10 +fle.d zero, f10, f15 +fle.d zero, f10, f20 +fle.d zero, f10, f25 +fle.d zero, f10, f31 +fle.d zero, f15, f0 +fle.d zero, f15, f1 +fle.d zero, f15, f5 +fle.d zero, f15, f10 +fle.d zero, f15, f15 +fle.d zero, f15, f20 +fle.d zero, f15, f25 +fle.d zero, f15, f31 +fle.d zero, f20, f0 +fle.d zero, f20, f1 +fle.d zero, f20, f5 +fle.d zero, f20, f10 +fle.d zero, f20, f15 +fle.d zero, f20, f20 +fle.d zero, f20, f25 +fle.d zero, f20, f31 +fle.d zero, f25, f0 +fle.d zero, f25, f1 +fle.d zero, f25, f5 +fle.d zero, f25, f10 +fle.d zero, f25, f15 +fle.d zero, f25, f20 +fle.d zero, f25, f25 +fle.d zero, f25, f31 +fle.d zero, f31, f0 +fle.d zero, f31, f1 +fle.d zero, f31, f5 +fle.d zero, f31, f10 +fle.d zero, f31, f15 +fle.d zero, f31, f20 +fle.d zero, f31, f25 +fle.d zero, f31, f31 +fle.d ra, f0, f0 +fle.d ra, f0, f1 +fle.d ra, f0, f5 +fle.d ra, f0, f10 +fle.d ra, f0, f15 +fle.d ra, f0, f20 +fle.d ra, f0, f25 +fle.d ra, f0, f31 +fle.d ra, f1, f0 +fle.d ra, f1, f1 +fle.d ra, f1, f5 +fle.d ra, f1, f10 +fle.d ra, f1, f15 +fle.d ra, f1, f20 +fle.d ra, f1, f25 +fle.d ra, f1, f31 +fle.d ra, f5, f0 +fle.d ra, f5, f1 +fle.d ra, f5, f5 +fle.d ra, f5, f10 +fle.d ra, f5, f15 +fle.d ra, f5, f20 +fle.d ra, f5, f25 +fle.d ra, f5, f31 +fle.d ra, f10, f0 +fle.d ra, f10, f1 +fle.d ra, f10, f5 +fle.d ra, f10, f10 +fle.d ra, f10, f15 +fle.d ra, f10, f20 +fle.d ra, f10, f25 +fle.d ra, f10, f31 +fle.d ra, f15, f0 +fle.d ra, f15, f1 +fle.d ra, f15, f5 +fle.d ra, f15, f10 +fle.d ra, f15, f15 +fle.d ra, f15, f20 +fle.d ra, f15, f25 +fle.d ra, f15, f31 +fle.d ra, f20, f0 +fle.d ra, f20, f1 +fle.d ra, f20, f5 +fle.d ra, f20, f10 +fle.d ra, f20, f15 +fle.d ra, f20, f20 +fle.d ra, f20, f25 +fle.d ra, f20, f31 +fle.d ra, f25, f0 +fle.d ra, f25, f1 +fle.d ra, f25, f5 +fle.d ra, f25, f10 +fle.d ra, f25, f15 +fle.d ra, f25, f20 +fle.d ra, f25, f25 +fle.d ra, f25, f31 +fle.d ra, f31, f0 +fle.d ra, f31, f1 +fle.d ra, f31, f5 +fle.d ra, f31, f10 +fle.d ra, f31, f15 +fle.d ra, f31, f20 +fle.d ra, f31, f25 +fle.d ra, f31, f31 +fle.d t0, f0, f0 +fle.d t0, f0, f1 +fle.d t0, f0, f5 +fle.d t0, f0, f10 +fle.d t0, f0, f15 +fle.d t0, f0, f20 +fle.d t0, f0, f25 +fle.d t0, f0, f31 +fle.d t0, f1, f0 +fle.d t0, f1, f1 +fle.d t0, f1, f5 +fle.d t0, f1, f10 +fle.d t0, f1, f15 +fle.d t0, f1, f20 +fle.d t0, f1, f25 +fle.d t0, f1, f31 +fle.d t0, f5, f0 +fle.d t0, f5, f1 +fle.d t0, f5, f5 +fle.d t0, f5, f10 +fle.d t0, f5, f15 +fle.d t0, f5, f20 +fle.d t0, f5, f25 +fle.d t0, f5, f31 +fle.d t0, f10, f0 +fle.d t0, f10, f1 +fle.d t0, f10, f5 +fle.d t0, f10, f10 +fle.d t0, f10, f15 +fle.d t0, f10, f20 +fle.d t0, f10, f25 +fle.d t0, f10, f31 +fle.d t0, f15, f0 +fle.d t0, f15, f1 +fle.d t0, f15, f5 +fle.d t0, f15, f10 +fle.d t0, f15, f15 +fle.d t0, f15, f20 +fle.d t0, f15, f25 +fle.d t0, f15, f31 +fle.d t0, f20, f0 +fle.d t0, f20, f1 +fle.d t0, f20, f5 +fle.d t0, f20, f10 +fle.d t0, f20, f15 +fle.d t0, f20, f20 +fle.d t0, f20, f25 +fle.d t0, f20, f31 +fle.d t0, f25, f0 +fle.d t0, f25, f1 +fle.d t0, f25, f5 +fle.d t0, f25, f10 +fle.d t0, f25, f15 +fle.d t0, f25, f20 +fle.d t0, f25, f25 +fle.d t0, f25, f31 +fle.d t0, f31, f0 +fle.d t0, f31, f1 +fle.d t0, f31, f5 +fle.d t0, f31, f10 +fle.d t0, f31, f15 +fle.d t0, f31, f20 +fle.d t0, f31, f25 +fle.d t0, f31, f31 +fle.d a0, f0, f0 +fle.d a0, f0, f1 +fle.d a0, f0, f5 +fle.d a0, f0, f10 +fle.d a0, f0, f15 +fle.d a0, f0, f20 +fle.d a0, f0, f25 +fle.d a0, f0, f31 +fle.d a0, f1, f0 +fle.d a0, f1, f1 +fle.d a0, f1, f5 +fle.d a0, f1, f10 +fle.d a0, f1, f15 +fle.d a0, f1, f20 +fle.d a0, f1, f25 +fle.d a0, f1, f31 +fle.d a0, f5, f0 +fle.d a0, f5, f1 +fle.d a0, f5, f5 +fle.d a0, f5, f10 +fle.d a0, f5, f15 +fle.d a0, f5, f20 +fle.d a0, f5, f25 +fle.d a0, f5, f31 +fle.d a0, f10, f0 +fle.d a0, f10, f1 +fle.d a0, f10, f5 +fle.d a0, f10, f10 +fle.d a0, f10, f15 +fle.d a0, f10, f20 +fle.d a0, f10, f25 +fle.d a0, f10, f31 +fle.d a0, f15, f0 +fle.d a0, f15, f1 +fle.d a0, f15, f5 +fle.d a0, f15, f10 +fle.d a0, f15, f15 +fle.d a0, f15, f20 +fle.d a0, f15, f25 +fle.d a0, f15, f31 +fle.d a0, f20, f0 +fle.d a0, f20, f1 +fle.d a0, f20, f5 +fle.d a0, f20, f10 +fle.d a0, f20, f15 +fle.d a0, f20, f20 +fle.d a0, f20, f25 +fle.d a0, f20, f31 +fle.d a0, f25, f0 +fle.d a0, f25, f1 +fle.d a0, f25, f5 +fle.d a0, f25, f10 +fle.d a0, f25, f15 +fle.d a0, f25, f20 +fle.d a0, f25, f25 +fle.d a0, f25, f31 +fle.d a0, f31, f0 +fle.d a0, f31, f1 +fle.d a0, f31, f5 +fle.d a0, f31, f10 +fle.d a0, f31, f15 +fle.d a0, f31, f20 +fle.d a0, f31, f25 +fle.d a0, f31, f31 +fle.d a5, f0, f0 +fle.d a5, f0, f1 +fle.d a5, f0, f5 +fle.d a5, f0, f10 +fle.d a5, f0, f15 +fle.d a5, f0, f20 +fle.d a5, f0, f25 +fle.d a5, f0, f31 +fle.d a5, f1, f0 +fle.d a5, f1, f1 +fle.d a5, f1, f5 +fle.d a5, f1, f10 +fle.d a5, f1, f15 +fle.d a5, f1, f20 +fle.d a5, f1, f25 +fle.d a5, f1, f31 +fle.d a5, f5, f0 +fle.d a5, f5, f1 +fle.d a5, f5, f5 +fle.d a5, f5, f10 +fle.d a5, f5, f15 +fle.d a5, f5, f20 +fle.d a5, f5, f25 +fle.d a5, f5, f31 +fle.d a5, f10, f0 +fle.d a5, f10, f1 +fle.d a5, f10, f5 +fle.d a5, f10, f10 +fle.d a5, f10, f15 +fle.d a5, f10, f20 +fle.d a5, f10, f25 +fle.d a5, f10, f31 +fle.d a5, f15, f0 +fle.d a5, f15, f1 +fle.d a5, f15, f5 +fle.d a5, f15, f10 +fle.d a5, f15, f15 +fle.d a5, f15, f20 +fle.d a5, f15, f25 +fle.d a5, f15, f31 +fle.d a5, f20, f0 +fle.d a5, f20, f1 +fle.d a5, f20, f5 +fle.d a5, f20, f10 +fle.d a5, f20, f15 +fle.d a5, f20, f20 +fle.d a5, f20, f25 +fle.d a5, f20, f31 +fle.d a5, f25, f0 +fle.d a5, f25, f1 +fle.d a5, f25, f5 +fle.d a5, f25, f10 +fle.d a5, f25, f15 +fle.d a5, f25, f20 +fle.d a5, f25, f25 +fle.d a5, f25, f31 +fle.d a5, f31, f0 +fle.d a5, f31, f1 +fle.d a5, f31, f5 +fle.d a5, f31, f10 +fle.d a5, f31, f15 +fle.d a5, f31, f20 +fle.d a5, f31, f25 +fle.d a5, f31, f31 +fle.d s4, f0, f0 +fle.d s4, f0, f1 +fle.d s4, f0, f5 +fle.d s4, f0, f10 +fle.d s4, f0, f15 +fle.d s4, f0, f20 +fle.d s4, f0, f25 +fle.d s4, f0, f31 +fle.d s4, f1, f0 +fle.d s4, f1, f1 +fle.d s4, f1, f5 +fle.d s4, f1, f10 +fle.d s4, f1, f15 +fle.d s4, f1, f20 +fle.d s4, f1, f25 +fle.d s4, f1, f31 +fle.d s4, f5, f0 +fle.d s4, f5, f1 +fle.d s4, f5, f5 +fle.d s4, f5, f10 +fle.d s4, f5, f15 +fle.d s4, f5, f20 +fle.d s4, f5, f25 +fle.d s4, f5, f31 +fle.d s4, f10, f0 +fle.d s4, f10, f1 +fle.d s4, f10, f5 +fle.d s4, f10, f10 +fle.d s4, f10, f15 +fle.d s4, f10, f20 +fle.d s4, f10, f25 +fle.d s4, f10, f31 +fle.d s4, f15, f0 +fle.d s4, f15, f1 +fle.d s4, f15, f5 +fle.d s4, f15, f10 +fle.d s4, f15, f15 +fle.d s4, f15, f20 +fle.d s4, f15, f25 +fle.d s4, f15, f31 +fle.d s4, f20, f0 +fle.d s4, f20, f1 +fle.d s4, f20, f5 +fle.d s4, f20, f10 +fle.d s4, f20, f15 +fle.d s4, f20, f20 +fle.d s4, f20, f25 +fle.d s4, f20, f31 +fle.d s4, f25, f0 +fle.d s4, f25, f1 +fle.d s4, f25, f5 +fle.d s4, f25, f10 +fle.d s4, f25, f15 +fle.d s4, f25, f20 +fle.d s4, f25, f25 +fle.d s4, f25, f31 +fle.d s4, f31, f0 +fle.d s4, f31, f1 +fle.d s4, f31, f5 +fle.d s4, f31, f10 +fle.d s4, f31, f15 +fle.d s4, f31, f20 +fle.d s4, f31, f25 +fle.d s4, f31, f31 +fle.d s9, f0, f0 +fle.d s9, f0, f1 +fle.d s9, f0, f5 +fle.d s9, f0, f10 +fle.d s9, f0, f15 +fle.d s9, f0, f20 +fle.d s9, f0, f25 +fle.d s9, f0, f31 +fle.d s9, f1, f0 +fle.d s9, f1, f1 +fle.d s9, f1, f5 +fle.d s9, f1, f10 +fle.d s9, f1, f15 +fle.d s9, f1, f20 +fle.d s9, f1, f25 +fle.d s9, f1, f31 +fle.d s9, f5, f0 +fle.d s9, f5, f1 +fle.d s9, f5, f5 +fle.d s9, f5, f10 +fle.d s9, f5, f15 +fle.d s9, f5, f20 +fle.d s9, f5, f25 +fle.d s9, f5, f31 +fle.d s9, f10, f0 +fle.d s9, f10, f1 +fle.d s9, f10, f5 +fle.d s9, f10, f10 +fle.d s9, f10, f15 +fle.d s9, f10, f20 +fle.d s9, f10, f25 +fle.d s9, f10, f31 +fle.d s9, f15, f0 +fle.d s9, f15, f1 +fle.d s9, f15, f5 +fle.d s9, f15, f10 +fle.d s9, f15, f15 +fle.d s9, f15, f20 +fle.d s9, f15, f25 +fle.d s9, f15, f31 +fle.d s9, f20, f0 +fle.d s9, f20, f1 +fle.d s9, f20, f5 +fle.d s9, f20, f10 +fle.d s9, f20, f15 +fle.d s9, f20, f20 +fle.d s9, f20, f25 +fle.d s9, f20, f31 +fle.d s9, f25, f0 +fle.d s9, f25, f1 +fle.d s9, f25, f5 +fle.d s9, f25, f10 +fle.d s9, f25, f15 +fle.d s9, f25, f20 +fle.d s9, f25, f25 +fle.d s9, f25, f31 +fle.d s9, f31, f0 +fle.d s9, f31, f1 +fle.d s9, f31, f5 +fle.d s9, f31, f10 +fle.d s9, f31, f15 +fle.d s9, f31, f20 +fle.d s9, f31, f25 +fle.d s9, f31, f31 +fle.d t6, f0, f0 +fle.d t6, f0, f1 +fle.d t6, f0, f5 +fle.d t6, f0, f10 +fle.d t6, f0, f15 +fle.d t6, f0, f20 +fle.d t6, f0, f25 +fle.d t6, f0, f31 +fle.d t6, f1, f0 +fle.d t6, f1, f1 +fle.d t6, f1, f5 +fle.d t6, f1, f10 +fle.d t6, f1, f15 +fle.d t6, f1, f20 +fle.d t6, f1, f25 +fle.d t6, f1, f31 +fle.d t6, f5, f0 +fle.d t6, f5, f1 +fle.d t6, f5, f5 +fle.d t6, f5, f10 +fle.d t6, f5, f15 +fle.d t6, f5, f20 +fle.d t6, f5, f25 +fle.d t6, f5, f31 +fle.d t6, f10, f0 +fle.d t6, f10, f1 +fle.d t6, f10, f5 +fle.d t6, f10, f10 +fle.d t6, f10, f15 +fle.d t6, f10, f20 +fle.d t6, f10, f25 +fle.d t6, f10, f31 +fle.d t6, f15, f0 +fle.d t6, f15, f1 +fle.d t6, f15, f5 +fle.d t6, f15, f10 +fle.d t6, f15, f15 +fle.d t6, f15, f20 +fle.d t6, f15, f25 +fle.d t6, f15, f31 +fle.d t6, f20, f0 +fle.d t6, f20, f1 +fle.d t6, f20, f5 +fle.d t6, f20, f10 +fle.d t6, f20, f15 +fle.d t6, f20, f20 +fle.d t6, f20, f25 +fle.d t6, f20, f31 +fle.d t6, f25, f0 +fle.d t6, f25, f1 +fle.d t6, f25, f5 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+fle.d t6, f10, f25 +fle.d t6, f10, f31 +fle.d t6, f15, f0 +fle.d t6, f15, f1 +fle.d t6, f15, f5 +fle.d t6, f15, f10 +fle.d t6, f15, f15 +fle.d t6, f15, f20 +fle.d t6, f15, f25 +fle.d t6, f15, f31 +fle.d t6, f20, f0 +fle.d t6, f20, f1 +fle.d t6, f20, f5 +fle.d t6, f20, f10 +fle.d t6, f20, f15 +fle.d t6, f20, f20 +fle.d t6, f20, f25 +fle.d t6, f20, f31 +fle.d t6, f25, f0 +fle.d t6, f25, f1 +fle.d t6, f25, f5 +fle.d t6, f25, f10 +fle.d t6, f25, f15 +fle.d t6, f25, f20 +fle.d t6, f25, f25 +fle.d t6, f25, f31 +fle.d t6, f31, f0 +fle.d t6, f31, f1 +fle.d t6, f31, f5 +fle.d t6, f31, f10 +fle.d t6, f31, f15 +fle.d t6, f31, f20 +fle.d t6, f31, f25 +fle.d t6, f31, f31 diff --git a/tests/riscv/d-extension/fle_d.asm b/tests/riscv/d-extension/fle_d.asm new file mode 100644 index 0000000..eff8fbe --- /dev/null +++ b/tests/riscv/d-extension/fle_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fle.d a0, f1, f2 + diff --git a/tests/riscv/d-extension/fle_d.bin b/tests/riscv/d-extension/fle_d.bin new file mode 100644 index 0000000..5406a1e --- /dev/null +++ b/tests/riscv/d-extension/fle_d.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/d-extension/fle_d.disasm b/tests/riscv/d-extension/fle_d.disasm new file mode 100644 index 0000000..46988ed --- /dev/null +++ b/tests/riscv/d-extension/fle_d.disasm @@ -0,0 +1 @@ +fle.d a0, f1, f2 diff --git a/tests/riscv/d-extension/flt.d.asm b/tests/riscv/d-extension/flt.d.asm new file mode 100644 index 0000000..fba244b --- /dev/null +++ b/tests/riscv/d-extension/flt.d.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +flt.d zero, f0, f0 +flt.d zero, f0, f1 +flt.d zero, f0, f5 +flt.d zero, f0, f10 +flt.d zero, f0, f15 +flt.d zero, f0, f20 +flt.d zero, f0, f25 +flt.d zero, f0, f31 +flt.d zero, f1, f0 +flt.d zero, f1, f1 +flt.d zero, f1, f5 +flt.d zero, f1, f10 +flt.d zero, f1, f15 +flt.d zero, f1, f20 +flt.d zero, f1, f25 +flt.d zero, f1, f31 +flt.d zero, f5, f0 +flt.d zero, f5, f1 +flt.d zero, f5, f5 +flt.d zero, f5, f10 +flt.d zero, f5, f15 +flt.d zero, f5, f20 +flt.d zero, f5, f25 +flt.d zero, f5, f31 +flt.d zero, f10, f0 +flt.d zero, f10, f1 +flt.d zero, f10, f5 +flt.d zero, f10, f10 +flt.d zero, f10, f15 +flt.d zero, f10, f20 +flt.d zero, f10, f25 +flt.d zero, f10, f31 +flt.d zero, f15, f0 +flt.d zero, f15, f1 +flt.d zero, f15, f5 +flt.d zero, f15, f10 +flt.d zero, f15, f15 +flt.d zero, f15, f20 +flt.d zero, f15, f25 +flt.d zero, f15, f31 +flt.d zero, f20, f0 +flt.d zero, f20, f1 +flt.d zero, f20, f5 +flt.d zero, f20, f10 +flt.d zero, f20, f15 +flt.d zero, f20, f20 +flt.d zero, f20, f25 +flt.d zero, f20, f31 +flt.d zero, f25, f0 +flt.d zero, f25, f1 +flt.d zero, f25, f5 +flt.d zero, f25, f10 +flt.d zero, f25, f15 +flt.d zero, f25, f20 +flt.d zero, f25, f25 +flt.d zero, f25, f31 +flt.d zero, f31, f0 +flt.d zero, f31, f1 +flt.d zero, f31, f5 +flt.d zero, f31, f10 +flt.d zero, f31, f15 +flt.d zero, f31, f20 +flt.d zero, f31, f25 +flt.d zero, f31, f31 +flt.d ra, f0, f0 +flt.d ra, f0, f1 +flt.d ra, f0, f5 +flt.d ra, f0, f10 +flt.d ra, f0, f15 +flt.d ra, f0, f20 +flt.d ra, f0, f25 +flt.d ra, f0, f31 +flt.d ra, f1, f0 +flt.d ra, f1, f1 +flt.d ra, f1, f5 +flt.d ra, f1, f10 +flt.d ra, f1, f15 +flt.d ra, f1, f20 +flt.d ra, f1, f25 +flt.d ra, f1, f31 +flt.d ra, f5, f0 +flt.d ra, f5, f1 +flt.d ra, f5, f5 +flt.d ra, f5, f10 +flt.d ra, f5, f15 +flt.d ra, f5, f20 +flt.d ra, f5, f25 +flt.d ra, f5, f31 +flt.d ra, f10, f0 +flt.d ra, f10, f1 +flt.d ra, f10, f5 +flt.d ra, f10, f10 +flt.d ra, f10, f15 +flt.d ra, f10, f20 +flt.d ra, f10, f25 +flt.d ra, f10, f31 +flt.d ra, f15, f0 +flt.d ra, f15, f1 +flt.d ra, f15, f5 +flt.d ra, f15, f10 +flt.d ra, f15, f15 +flt.d ra, f15, f20 +flt.d ra, f15, f25 +flt.d ra, f15, f31 +flt.d ra, f20, f0 +flt.d ra, f20, f1 +flt.d ra, f20, f5 +flt.d ra, f20, f10 +flt.d ra, f20, f15 +flt.d ra, f20, f20 +flt.d ra, f20, f25 +flt.d ra, f20, f31 +flt.d ra, f25, f0 +flt.d ra, f25, f1 +flt.d ra, f25, f5 +flt.d ra, f25, f10 +flt.d ra, f25, f15 +flt.d ra, f25, f20 +flt.d ra, f25, f25 +flt.d ra, f25, f31 +flt.d ra, f31, f0 +flt.d ra, f31, f1 +flt.d ra, f31, f5 +flt.d ra, f31, f10 +flt.d ra, f31, f15 +flt.d ra, f31, f20 +flt.d ra, f31, f25 +flt.d ra, f31, f31 +flt.d t0, f0, f0 +flt.d t0, f0, f1 +flt.d t0, f0, f5 +flt.d t0, f0, f10 +flt.d t0, f0, f15 +flt.d t0, f0, f20 +flt.d t0, f0, f25 +flt.d t0, f0, f31 +flt.d t0, f1, f0 +flt.d t0, f1, f1 +flt.d t0, f1, f5 +flt.d t0, f1, f10 +flt.d t0, f1, f15 +flt.d t0, f1, f20 +flt.d t0, f1, f25 +flt.d t0, f1, f31 +flt.d t0, f5, f0 +flt.d t0, f5, f1 +flt.d t0, f5, f5 +flt.d t0, f5, f10 +flt.d t0, f5, f15 +flt.d t0, f5, f20 +flt.d t0, f5, f25 +flt.d t0, f5, f31 +flt.d t0, f10, f0 +flt.d t0, f10, f1 +flt.d t0, f10, f5 +flt.d t0, f10, f10 +flt.d t0, f10, f15 +flt.d t0, f10, f20 +flt.d t0, f10, f25 +flt.d t0, f10, f31 +flt.d t0, f15, f0 +flt.d t0, f15, f1 +flt.d t0, f15, f5 +flt.d t0, f15, f10 +flt.d t0, f15, f15 +flt.d t0, f15, f20 +flt.d t0, f15, f25 +flt.d t0, f15, f31 +flt.d t0, f20, f0 +flt.d t0, f20, f1 +flt.d t0, f20, f5 +flt.d t0, f20, f10 +flt.d t0, f20, f15 +flt.d t0, f20, f20 +flt.d t0, f20, f25 +flt.d t0, f20, f31 +flt.d t0, f25, f0 +flt.d t0, f25, f1 +flt.d t0, f25, f5 +flt.d t0, f25, f10 +flt.d t0, f25, f15 +flt.d t0, f25, f20 +flt.d t0, f25, f25 +flt.d t0, f25, f31 +flt.d t0, f31, f0 +flt.d t0, f31, f1 +flt.d t0, f31, f5 +flt.d t0, f31, f10 +flt.d t0, f31, f15 +flt.d t0, f31, f20 +flt.d t0, f31, f25 +flt.d t0, f31, f31 +flt.d a0, f0, f0 +flt.d a0, f0, f1 +flt.d a0, f0, f5 +flt.d a0, f0, f10 +flt.d a0, f0, f15 +flt.d a0, f0, f20 +flt.d a0, f0, f25 +flt.d a0, f0, f31 +flt.d a0, f1, f0 +flt.d a0, f1, f1 +flt.d a0, f1, f5 +flt.d a0, f1, f10 +flt.d a0, f1, f15 +flt.d a0, f1, f20 +flt.d a0, f1, f25 +flt.d a0, f1, f31 +flt.d a0, f5, f0 +flt.d a0, f5, f1 +flt.d a0, f5, f5 +flt.d a0, f5, f10 +flt.d a0, f5, f15 +flt.d a0, f5, f20 +flt.d a0, f5, f25 +flt.d a0, f5, f31 +flt.d a0, f10, f0 +flt.d a0, f10, f1 +flt.d a0, f10, f5 +flt.d a0, f10, f10 +flt.d a0, f10, f15 +flt.d a0, f10, f20 +flt.d a0, f10, f25 +flt.d a0, f10, f31 +flt.d a0, f15, f0 +flt.d a0, f15, f1 +flt.d a0, f15, f5 +flt.d a0, f15, f10 +flt.d a0, f15, f15 +flt.d a0, f15, f20 +flt.d a0, f15, f25 +flt.d a0, f15, f31 +flt.d a0, f20, f0 +flt.d a0, f20, f1 +flt.d a0, f20, f5 +flt.d a0, f20, f10 +flt.d a0, f20, f15 +flt.d a0, f20, f20 +flt.d a0, f20, f25 +flt.d a0, f20, f31 +flt.d a0, f25, f0 +flt.d a0, f25, f1 +flt.d a0, f25, f5 +flt.d a0, f25, f10 +flt.d a0, f25, f15 +flt.d a0, f25, f20 +flt.d a0, f25, f25 +flt.d a0, f25, f31 +flt.d a0, f31, f0 +flt.d a0, f31, f1 +flt.d a0, f31, f5 +flt.d a0, f31, f10 +flt.d a0, f31, f15 +flt.d a0, f31, f20 +flt.d a0, f31, f25 +flt.d a0, f31, f31 +flt.d a5, f0, f0 +flt.d a5, f0, f1 +flt.d a5, f0, f5 +flt.d a5, f0, f10 +flt.d a5, f0, f15 +flt.d a5, f0, f20 +flt.d a5, f0, f25 +flt.d a5, f0, f31 +flt.d a5, f1, f0 +flt.d a5, f1, f1 +flt.d a5, f1, f5 +flt.d a5, f1, f10 +flt.d a5, f1, f15 +flt.d a5, f1, f20 +flt.d a5, f1, f25 +flt.d a5, f1, f31 +flt.d a5, f5, f0 +flt.d a5, f5, f1 +flt.d a5, f5, f5 +flt.d a5, f5, f10 +flt.d a5, f5, f15 +flt.d a5, f5, f20 +flt.d a5, f5, f25 +flt.d a5, f5, f31 +flt.d a5, f10, f0 +flt.d a5, f10, f1 +flt.d a5, f10, f5 +flt.d a5, f10, f10 +flt.d a5, f10, f15 +flt.d a5, f10, f20 +flt.d a5, f10, f25 +flt.d a5, f10, f31 +flt.d a5, f15, f0 +flt.d a5, f15, f1 +flt.d a5, f15, f5 +flt.d a5, f15, f10 +flt.d a5, f15, f15 +flt.d a5, f15, f20 +flt.d a5, f15, f25 +flt.d a5, f15, f31 +flt.d a5, f20, f0 +flt.d a5, f20, f1 +flt.d a5, f20, f5 +flt.d a5, f20, f10 +flt.d a5, f20, f15 +flt.d a5, f20, f20 +flt.d a5, f20, f25 +flt.d a5, f20, f31 +flt.d a5, f25, f0 +flt.d a5, f25, f1 +flt.d a5, f25, f5 +flt.d a5, f25, f10 +flt.d a5, f25, f15 +flt.d a5, f25, f20 +flt.d a5, f25, f25 +flt.d a5, f25, f31 +flt.d a5, f31, f0 +flt.d a5, f31, f1 +flt.d a5, f31, f5 +flt.d a5, f31, f10 +flt.d a5, f31, f15 +flt.d a5, f31, f20 +flt.d a5, f31, f25 +flt.d a5, f31, f31 +flt.d s4, f0, f0 +flt.d s4, f0, f1 +flt.d s4, f0, f5 +flt.d s4, f0, f10 +flt.d s4, f0, f15 +flt.d s4, f0, f20 +flt.d s4, f0, f25 +flt.d s4, f0, f31 +flt.d s4, f1, f0 +flt.d s4, f1, f1 +flt.d s4, f1, f5 +flt.d s4, f1, f10 +flt.d s4, f1, f15 +flt.d s4, f1, f20 +flt.d s4, f1, f25 +flt.d s4, f1, f31 +flt.d s4, f5, f0 +flt.d s4, f5, f1 +flt.d s4, f5, f5 +flt.d s4, f5, f10 +flt.d s4, f5, f15 +flt.d s4, f5, f20 +flt.d s4, f5, f25 +flt.d s4, f5, f31 +flt.d s4, f10, f0 +flt.d s4, f10, f1 +flt.d s4, f10, f5 +flt.d s4, f10, f10 +flt.d s4, f10, f15 +flt.d s4, f10, f20 +flt.d s4, f10, f25 +flt.d s4, f10, f31 +flt.d s4, f15, f0 +flt.d s4, f15, f1 +flt.d s4, f15, f5 +flt.d s4, f15, f10 +flt.d s4, f15, f15 +flt.d s4, f15, f20 +flt.d s4, f15, f25 +flt.d s4, f15, f31 +flt.d s4, f20, f0 +flt.d s4, f20, f1 +flt.d s4, f20, f5 +flt.d s4, f20, f10 +flt.d s4, f20, f15 +flt.d s4, f20, f20 +flt.d s4, f20, f25 +flt.d s4, f20, f31 +flt.d s4, f25, f0 +flt.d s4, f25, f1 +flt.d s4, f25, f5 +flt.d s4, f25, f10 +flt.d s4, f25, f15 +flt.d s4, f25, f20 +flt.d s4, f25, f25 +flt.d s4, f25, f31 +flt.d s4, f31, f0 +flt.d s4, f31, f1 +flt.d s4, f31, f5 +flt.d s4, f31, f10 +flt.d s4, f31, f15 +flt.d s4, f31, f20 +flt.d s4, f31, f25 +flt.d s4, f31, f31 +flt.d s9, f0, f0 +flt.d s9, f0, f1 +flt.d s9, f0, f5 +flt.d s9, f0, f10 +flt.d s9, f0, f15 +flt.d s9, f0, f20 +flt.d s9, f0, f25 +flt.d s9, f0, f31 +flt.d s9, f1, f0 +flt.d s9, f1, f1 +flt.d s9, f1, f5 +flt.d s9, f1, f10 +flt.d s9, f1, f15 +flt.d s9, f1, f20 +flt.d s9, f1, f25 +flt.d s9, f1, f31 +flt.d s9, f5, f0 +flt.d s9, f5, f1 +flt.d s9, f5, f5 +flt.d s9, f5, f10 +flt.d s9, f5, f15 +flt.d s9, f5, f20 +flt.d s9, f5, f25 +flt.d s9, f5, f31 +flt.d s9, f10, f0 +flt.d s9, f10, f1 +flt.d s9, f10, f5 +flt.d s9, f10, f10 +flt.d s9, f10, f15 +flt.d s9, f10, f20 +flt.d s9, f10, f25 +flt.d s9, f10, f31 +flt.d s9, f15, f0 +flt.d s9, f15, f1 +flt.d s9, f15, f5 +flt.d s9, f15, f10 +flt.d s9, f15, f15 +flt.d s9, f15, f20 +flt.d s9, f15, f25 +flt.d s9, f15, f31 +flt.d s9, f20, f0 +flt.d s9, f20, f1 +flt.d s9, f20, f5 +flt.d s9, f20, f10 +flt.d s9, f20, f15 +flt.d s9, f20, f20 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+fmin.d f15, f5, f1 +fmin.d f15, f5, f5 +fmin.d f15, f5, f10 +fmin.d f15, f5, f15 +fmin.d f15, f5, f20 +fmin.d f15, f5, f25 +fmin.d f15, f5, f31 +fmin.d f15, f10, f0 +fmin.d f15, f10, f1 +fmin.d f15, f10, f5 +fmin.d f15, f10, f10 +fmin.d f15, f10, f15 +fmin.d f15, f10, f20 +fmin.d f15, f10, f25 +fmin.d f15, f10, f31 +fmin.d f15, f15, f0 +fmin.d f15, f15, f1 +fmin.d f15, f15, f5 +fmin.d f15, f15, f10 +fmin.d f15, f15, f15 +fmin.d f15, f15, f20 +fmin.d f15, f15, f25 +fmin.d f15, f15, f31 +fmin.d f15, f20, f0 +fmin.d f15, f20, f1 +fmin.d f15, f20, f5 +fmin.d f15, f20, f10 +fmin.d f15, f20, f15 +fmin.d f15, f20, f20 +fmin.d f15, f20, f25 +fmin.d f15, f20, f31 +fmin.d f15, f25, f0 +fmin.d f15, f25, f1 +fmin.d f15, f25, f5 +fmin.d f15, f25, f10 +fmin.d f15, f25, f15 +fmin.d f15, f25, f20 +fmin.d f15, f25, f25 +fmin.d f15, f25, f31 +fmin.d f15, f31, f0 +fmin.d f15, f31, f1 +fmin.d f15, f31, f5 +fmin.d f15, f31, f10 +fmin.d f15, f31, f15 +fmin.d f15, f31, f20 +fmin.d f15, f31, f25 +fmin.d f15, f31, f31 +fmin.d f20, f0, f0 +fmin.d f20, f0, f1 +fmin.d f20, f0, f5 +fmin.d f20, f0, f10 +fmin.d f20, f0, f15 +fmin.d f20, f0, f20 +fmin.d f20, f0, f25 +fmin.d f20, f0, f31 +fmin.d f20, f1, f0 +fmin.d f20, f1, f1 +fmin.d f20, f1, f5 +fmin.d f20, f1, f10 +fmin.d f20, f1, f15 +fmin.d f20, f1, f20 +fmin.d f20, f1, f25 +fmin.d f20, f1, f31 +fmin.d f20, f5, f0 +fmin.d f20, f5, f1 +fmin.d f20, f5, f5 +fmin.d f20, f5, f10 +fmin.d f20, f5, f15 +fmin.d f20, f5, f20 +fmin.d f20, f5, f25 +fmin.d f20, f5, f31 +fmin.d f20, f10, f0 +fmin.d f20, f10, f1 +fmin.d f20, f10, f5 +fmin.d f20, f10, f10 +fmin.d f20, f10, f15 +fmin.d f20, f10, f20 +fmin.d f20, f10, f25 +fmin.d f20, f10, f31 +fmin.d f20, f15, f0 +fmin.d f20, f15, f1 +fmin.d f20, f15, f5 +fmin.d f20, f15, f10 +fmin.d f20, f15, f15 +fmin.d f20, f15, f20 +fmin.d f20, f15, f25 +fmin.d f20, f15, f31 +fmin.d f20, f20, f0 +fmin.d f20, f20, f1 +fmin.d f20, f20, f5 +fmin.d f20, f20, f10 +fmin.d f20, f20, f15 +fmin.d f20, f20, f20 +fmin.d f20, f20, f25 +fmin.d f20, f20, f31 +fmin.d f20, f25, f0 +fmin.d f20, f25, f1 +fmin.d f20, f25, f5 +fmin.d f20, f25, f10 +fmin.d f20, f25, f15 +fmin.d f20, f25, f20 +fmin.d f20, f25, f25 +fmin.d f20, f25, f31 +fmin.d f20, f31, f0 +fmin.d f20, f31, f1 +fmin.d f20, f31, f5 +fmin.d f20, f31, f10 +fmin.d f20, f31, f15 +fmin.d f20, f31, f20 +fmin.d f20, f31, f25 +fmin.d f20, f31, f31 +fmin.d f25, f0, f0 +fmin.d f25, f0, f1 +fmin.d f25, f0, f5 +fmin.d f25, f0, f10 +fmin.d f25, f0, f15 +fmin.d f25, f0, f20 +fmin.d f25, f0, f25 +fmin.d f25, f0, f31 +fmin.d f25, f1, f0 +fmin.d f25, f1, f1 +fmin.d f25, f1, f5 +fmin.d f25, f1, f10 +fmin.d f25, f1, f15 +fmin.d f25, f1, f20 +fmin.d f25, f1, f25 +fmin.d f25, f1, f31 +fmin.d f25, f5, f0 +fmin.d f25, f5, f1 +fmin.d f25, f5, f5 +fmin.d f25, f5, f10 +fmin.d f25, f5, f15 +fmin.d f25, f5, f20 +fmin.d f25, f5, f25 +fmin.d f25, f5, f31 +fmin.d f25, f10, f0 +fmin.d f25, f10, f1 +fmin.d f25, f10, f5 +fmin.d f25, f10, f10 +fmin.d f25, f10, f15 +fmin.d f25, f10, f20 +fmin.d f25, f10, f25 +fmin.d f25, f10, f31 +fmin.d f25, f15, f0 +fmin.d f25, f15, f1 +fmin.d f25, f15, f5 +fmin.d f25, f15, f10 +fmin.d f25, f15, f15 +fmin.d f25, f15, f20 +fmin.d f25, f15, f25 +fmin.d f25, f15, f31 +fmin.d f25, f20, f0 +fmin.d f25, f20, f1 +fmin.d f25, f20, f5 +fmin.d f25, f20, f10 +fmin.d f25, f20, f15 +fmin.d f25, f20, f20 +fmin.d f25, f20, f25 +fmin.d f25, f20, f31 +fmin.d f25, f25, f0 +fmin.d f25, f25, f1 +fmin.d f25, f25, f5 +fmin.d f25, f25, f10 +fmin.d f25, f25, f15 +fmin.d f25, f25, f20 +fmin.d f25, f25, f25 +fmin.d f25, f25, f31 +fmin.d f25, f31, f0 +fmin.d f25, f31, f1 +fmin.d f25, f31, f5 +fmin.d f25, f31, f10 +fmin.d f25, f31, f15 +fmin.d f25, f31, f20 +fmin.d f25, f31, f25 +fmin.d f25, f31, f31 +fmin.d f31, f0, f0 +fmin.d f31, f0, f1 +fmin.d f31, f0, f5 +fmin.d f31, f0, f10 +fmin.d f31, f0, f15 +fmin.d f31, f0, f20 +fmin.d f31, f0, f25 +fmin.d f31, f0, f31 +fmin.d f31, f1, f0 +fmin.d f31, f1, f1 +fmin.d f31, f1, f5 +fmin.d f31, f1, f10 +fmin.d f31, f1, f15 +fmin.d f31, f1, f20 +fmin.d f31, f1, f25 +fmin.d f31, f1, f31 +fmin.d f31, f5, f0 +fmin.d f31, f5, f1 +fmin.d f31, f5, f5 +fmin.d f31, f5, f10 +fmin.d f31, f5, f15 +fmin.d f31, f5, f20 +fmin.d f31, f5, f25 +fmin.d f31, f5, f31 +fmin.d f31, f10, f0 +fmin.d f31, f10, f1 +fmin.d f31, f10, f5 +fmin.d f31, f10, f10 +fmin.d f31, f10, f15 +fmin.d f31, f10, f20 +fmin.d f31, f10, f25 +fmin.d f31, f10, f31 +fmin.d f31, f15, f0 +fmin.d f31, f15, f1 +fmin.d f31, f15, f5 +fmin.d f31, f15, f10 +fmin.d f31, f15, f15 +fmin.d f31, f15, f20 +fmin.d f31, f15, f25 +fmin.d f31, f15, f31 +fmin.d f31, f20, f0 +fmin.d f31, f20, f1 +fmin.d f31, f20, f5 +fmin.d f31, f20, f10 +fmin.d f31, f20, f15 +fmin.d f31, f20, f20 +fmin.d f31, f20, f25 +fmin.d f31, f20, f31 +fmin.d f31, f25, f0 +fmin.d f31, f25, f1 +fmin.d f31, f25, f5 +fmin.d f31, f25, f10 +fmin.d f31, f25, f15 +fmin.d f31, f25, f20 +fmin.d f31, f25, f25 +fmin.d f31, f25, f31 +fmin.d f31, f31, f0 +fmin.d f31, f31, f1 +fmin.d f31, f31, f5 +fmin.d f31, f31, f10 +fmin.d f31, f31, f15 +fmin.d f31, f31, f20 +fmin.d f31, f31, f25 +fmin.d f31, f31, f31 diff --git a/tests/riscv/d-extension/fmin_d.asm b/tests/riscv/d-extension/fmin_d.asm new file mode 100644 index 0000000..4391a27 --- /dev/null +++ b/tests/riscv/d-extension/fmin_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fmin.d f0, f1, f2 + diff --git a/tests/riscv/d-extension/fmin_d.bin b/tests/riscv/d-extension/fmin_d.bin new file mode 100644 index 0000000..1ba9690 --- /dev/null +++ b/tests/riscv/d-extension/fmin_d.bin @@ -0,0 +1 @@ +S * \ No newline at end of file diff --git a/tests/riscv/d-extension/fmin_d.disasm b/tests/riscv/d-extension/fmin_d.disasm new file mode 100644 index 0000000..2a7b083 --- /dev/null +++ b/tests/riscv/d-extension/fmin_d.disasm @@ -0,0 +1 @@ +fmin.d f0, f1, f2 diff --git a/tests/riscv/d-extension/fmsub.d.asm b/tests/riscv/d-extension/fmsub.d.asm new file mode 100644 index 0000000..9f07df9 --- /dev/null +++ b/tests/riscv/d-extension/fmsub.d.asm @@ -0,0 +1,4100 @@ +.lang riscv32 +.org 0x0 + +fmsub.d f0, f0, f0, f0 +fmsub.d f0, f0, f0, f1 +fmsub.d f0, f0, f0, f5 +fmsub.d f0, f0, f0, f10 +fmsub.d f0, f0, f0, f15 +fmsub.d f0, f0, f0, f20 +fmsub.d f0, f0, f0, f25 +fmsub.d f0, f0, f0, f31 +fmsub.d f0, f0, f1, f0 +fmsub.d f0, f0, f1, f1 +fmsub.d f0, f0, f1, f5 +fmsub.d f0, f0, f1, f10 +fmsub.d f0, f0, f1, f15 +fmsub.d f0, f0, f1, f20 +fmsub.d f0, f0, f1, f25 +fmsub.d f0, f0, f1, f31 +fmsub.d f0, f0, f5, f0 +fmsub.d f0, f0, f5, f1 +fmsub.d f0, f0, f5, f5 +fmsub.d f0, f0, f5, f10 +fmsub.d f0, f0, f5, f15 +fmsub.d f0, f0, f5, f20 +fmsub.d f0, f0, f5, f25 +fmsub.d f0, f0, f5, f31 +fmsub.d f0, f0, f10, f0 +fmsub.d f0, f0, f10, f1 +fmsub.d f0, f0, f10, f5 +fmsub.d f0, f0, f10, f10 +fmsub.d f0, f0, f10, f15 +fmsub.d f0, f0, f10, f20 +fmsub.d f0, f0, f10, f25 +fmsub.d f0, f0, f10, f31 +fmsub.d f0, f0, f15, f0 +fmsub.d f0, f0, f15, f1 +fmsub.d f0, f0, f15, f5 +fmsub.d f0, f0, f15, f10 +fmsub.d f0, f0, f15, f15 +fmsub.d f0, f0, f15, f20 +fmsub.d f0, f0, f15, f25 +fmsub.d f0, f0, f15, f31 +fmsub.d f0, f0, f20, f0 +fmsub.d f0, f0, f20, f1 +fmsub.d f0, f0, f20, f5 +fmsub.d f0, f0, f20, f10 +fmsub.d f0, f0, f20, f15 +fmsub.d f0, f0, f20, f20 +fmsub.d f0, f0, f20, f25 +fmsub.d f0, f0, f20, f31 +fmsub.d f0, f0, f25, f0 +fmsub.d f0, f0, f25, f1 +fmsub.d f0, f0, f25, f5 +fmsub.d f0, f0, f25, f10 +fmsub.d f0, f0, f25, f15 +fmsub.d f0, f0, f25, f20 +fmsub.d f0, f0, f25, f25 +fmsub.d f0, f0, f25, f31 +fmsub.d f0, f0, f31, f0 +fmsub.d f0, f0, f31, f1 +fmsub.d f0, f0, f31, f5 +fmsub.d f0, f0, f31, f10 +fmsub.d f0, f0, f31, f15 +fmsub.d f0, f0, f31, f20 +fmsub.d f0, f0, f31, f25 +fmsub.d f0, f0, f31, f31 +fmsub.d f0, f1, f0, f0 +fmsub.d f0, f1, f0, f1 +fmsub.d f0, f1, f0, f5 +fmsub.d f0, f1, f0, f10 +fmsub.d f0, f1, f0, f15 +fmsub.d f0, f1, f0, f20 +fmsub.d f0, f1, f0, f25 +fmsub.d f0, f1, f0, f31 +fmsub.d f0, f1, f1, f0 +fmsub.d f0, f1, f1, f1 +fmsub.d f0, f1, f1, f5 +fmsub.d f0, f1, f1, f10 +fmsub.d f0, f1, f1, f15 +fmsub.d f0, f1, f1, f20 +fmsub.d f0, f1, f1, f25 +fmsub.d f0, f1, f1, f31 +fmsub.d f0, f1, f5, f0 +fmsub.d f0, f1, f5, f1 +fmsub.d f0, f1, f5, f5 +fmsub.d f0, f1, f5, f10 +fmsub.d f0, f1, f5, f15 +fmsub.d f0, f1, f5, f20 +fmsub.d f0, f1, f5, f25 +fmsub.d f0, f1, f5, f31 +fmsub.d f0, f1, f10, f0 +fmsub.d f0, f1, f10, f1 +fmsub.d f0, f1, f10, f5 +fmsub.d f0, f1, f10, f10 +fmsub.d f0, f1, f10, f15 +fmsub.d f0, f1, f10, f20 +fmsub.d f0, f1, f10, f25 +fmsub.d f0, f1, f10, f31 +fmsub.d f0, f1, f15, f0 +fmsub.d f0, f1, f15, f1 +fmsub.d f0, f1, f15, f5 +fmsub.d f0, f1, f15, f10 +fmsub.d f0, f1, f15, f15 +fmsub.d f0, f1, f15, f20 +fmsub.d f0, f1, f15, f25 +fmsub.d f0, f1, f15, f31 +fmsub.d f0, f1, f20, f0 +fmsub.d f0, f1, f20, f1 +fmsub.d f0, f1, f20, f5 +fmsub.d f0, f1, f20, f10 +fmsub.d f0, f1, f20, f15 +fmsub.d f0, f1, f20, f20 +fmsub.d f0, f1, f20, f25 +fmsub.d f0, f1, f20, f31 +fmsub.d f0, f1, f25, f0 +fmsub.d f0, f1, f25, f1 +fmsub.d f0, f1, f25, f5 +fmsub.d f0, f1, f25, f10 +fmsub.d f0, f1, f25, f15 +fmsub.d f0, f1, f25, f20 +fmsub.d f0, f1, f25, f25 +fmsub.d f0, f1, f25, f31 +fmsub.d f0, f1, f31, f0 +fmsub.d f0, f1, f31, f1 +fmsub.d f0, f1, f31, f5 +fmsub.d f0, f1, f31, f10 +fmsub.d f0, f1, f31, f15 +fmsub.d f0, f1, f31, f20 +fmsub.d f0, f1, f31, f25 +fmsub.d f0, f1, f31, f31 +fmsub.d f0, f5, f0, f0 +fmsub.d f0, f5, f0, f1 +fmsub.d f0, f5, f0, f5 +fmsub.d f0, f5, f0, f10 +fmsub.d f0, f5, f0, f15 +fmsub.d f0, f5, f0, f20 +fmsub.d f0, f5, f0, f25 +fmsub.d f0, f5, f0, f31 +fmsub.d f0, f5, f1, f0 +fmsub.d f0, f5, f1, f1 +fmsub.d f0, f5, f1, f5 +fmsub.d f0, f5, f1, f10 +fmsub.d f0, f5, f1, f15 +fmsub.d f0, f5, f1, f20 +fmsub.d f0, f5, f1, f25 +fmsub.d f0, f5, f1, f31 +fmsub.d f0, f5, f5, f0 +fmsub.d f0, f5, f5, f1 +fmsub.d f0, f5, f5, f5 +fmsub.d f0, f5, f5, f10 +fmsub.d f0, f5, f5, f15 +fmsub.d f0, f5, f5, f20 +fmsub.d f0, f5, f5, f25 +fmsub.d f0, f5, f5, f31 +fmsub.d f0, f5, f10, f0 +fmsub.d f0, f5, f10, f1 +fmsub.d f0, f5, f10, f5 +fmsub.d f0, f5, f10, f10 +fmsub.d f0, f5, f10, f15 +fmsub.d f0, f5, f10, f20 +fmsub.d f0, f5, f10, f25 +fmsub.d f0, f5, f10, f31 +fmsub.d f0, f5, f15, f0 +fmsub.d f0, f5, f15, f1 +fmsub.d f0, f5, f15, f5 +fmsub.d f0, f5, f15, f10 +fmsub.d f0, f5, f15, f15 +fmsub.d f0, f5, f15, f20 +fmsub.d f0, f5, f15, f25 +fmsub.d f0, f5, f15, f31 +fmsub.d f0, f5, f20, f0 +fmsub.d f0, f5, f20, f1 +fmsub.d f0, f5, f20, f5 +fmsub.d f0, f5, f20, f10 +fmsub.d f0, f5, f20, f15 +fmsub.d f0, f5, f20, f20 +fmsub.d f0, f5, f20, f25 +fmsub.d f0, f5, f20, f31 +fmsub.d f0, f5, f25, f0 +fmsub.d f0, f5, f25, f1 +fmsub.d f0, f5, f25, f5 +fmsub.d f0, f5, f25, f10 +fmsub.d f0, f5, f25, f15 +fmsub.d f0, f5, f25, f20 +fmsub.d f0, f5, f25, f25 +fmsub.d f0, f5, f25, f31 +fmsub.d f0, f5, f31, f0 +fmsub.d f0, f5, f31, f1 +fmsub.d f0, f5, f31, f5 +fmsub.d f0, f5, f31, f10 +fmsub.d f0, f5, f31, f15 +fmsub.d f0, f5, f31, f20 +fmsub.d f0, f5, f31, f25 +fmsub.d f0, f5, f31, f31 +fmsub.d f0, f10, f0, f0 +fmsub.d f0, f10, f0, f1 +fmsub.d f0, f10, f0, f5 +fmsub.d f0, f10, f0, f10 +fmsub.d f0, f10, f0, f15 +fmsub.d f0, f10, f0, f20 +fmsub.d f0, f10, f0, f25 +fmsub.d f0, f10, f0, f31 +fmsub.d f0, f10, f1, f0 +fmsub.d f0, f10, f1, f1 +fmsub.d f0, f10, f1, f5 +fmsub.d f0, f10, f1, f10 +fmsub.d f0, f10, f1, f15 +fmsub.d f0, f10, f1, f20 +fmsub.d f0, f10, f1, f25 +fmsub.d f0, f10, f1, f31 +fmsub.d f0, f10, f5, f0 +fmsub.d f0, f10, f5, f1 +fmsub.d f0, f10, f5, f5 +fmsub.d f0, f10, f5, f10 +fmsub.d f0, f10, f5, f15 +fmsub.d f0, f10, f5, f20 +fmsub.d f0, f10, f5, f25 +fmsub.d f0, f10, f5, f31 +fmsub.d f0, f10, f10, f0 +fmsub.d f0, f10, f10, f1 +fmsub.d f0, f10, f10, f5 +fmsub.d f0, f10, f10, f10 +fmsub.d f0, f10, f10, f15 +fmsub.d f0, f10, f10, f20 +fmsub.d f0, f10, f10, f25 +fmsub.d f0, f10, f10, f31 +fmsub.d f0, f10, f15, f0 +fmsub.d f0, f10, f15, f1 +fmsub.d f0, f10, f15, f5 +fmsub.d f0, f10, f15, f10 +fmsub.d f0, f10, f15, f15 +fmsub.d f0, f10, f15, f20 +fmsub.d f0, f10, f15, f25 +fmsub.d f0, f10, f15, f31 +fmsub.d f0, f10, f20, f0 +fmsub.d f0, f10, f20, f1 +fmsub.d f0, f10, f20, f5 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+fmul.d f0, f15, f0 +fmul.d f0, f15, f1 +fmul.d f0, f15, f5 +fmul.d f0, f15, f10 +fmul.d f0, f15, f15 +fmul.d f0, f15, f20 +fmul.d f0, f15, f25 +fmul.d f0, f15, f31 +fmul.d f0, f20, f0 +fmul.d f0, f20, f1 +fmul.d f0, f20, f5 +fmul.d f0, f20, f10 +fmul.d f0, f20, f15 +fmul.d f0, f20, f20 +fmul.d f0, f20, f25 +fmul.d f0, f20, f31 +fmul.d f0, f25, f0 +fmul.d f0, f25, f1 +fmul.d f0, f25, f5 +fmul.d f0, f25, f10 +fmul.d f0, f25, f15 +fmul.d f0, f25, f20 +fmul.d f0, f25, f25 +fmul.d f0, f25, f31 +fmul.d f0, f31, f0 +fmul.d f0, f31, f1 +fmul.d f0, f31, f5 +fmul.d f0, f31, f10 +fmul.d f0, f31, f15 +fmul.d f0, f31, f20 +fmul.d f0, f31, f25 +fmul.d f0, f31, f31 +fmul.d f1, f0, f0 +fmul.d f1, f0, f1 +fmul.d f1, f0, f5 +fmul.d f1, f0, f10 +fmul.d f1, f0, f15 +fmul.d f1, f0, f20 +fmul.d f1, f0, f25 +fmul.d f1, f0, f31 +fmul.d f1, f1, f0 +fmul.d f1, f1, f1 +fmul.d f1, f1, f5 +fmul.d f1, f1, f10 +fmul.d f1, f1, f15 +fmul.d f1, f1, f20 +fmul.d f1, f1, f25 +fmul.d f1, f1, f31 +fmul.d f1, f5, f0 +fmul.d f1, f5, f1 +fmul.d f1, f5, f5 +fmul.d f1, f5, f10 +fmul.d f1, f5, f15 +fmul.d f1, f5, f20 +fmul.d f1, f5, f25 +fmul.d f1, f5, f31 +fmul.d f1, f10, f0 +fmul.d f1, f10, f1 +fmul.d f1, f10, f5 +fmul.d f1, f10, f10 +fmul.d f1, f10, f15 +fmul.d f1, f10, f20 +fmul.d f1, f10, f25 +fmul.d f1, f10, f31 +fmul.d f1, f15, f0 +fmul.d f1, f15, f1 +fmul.d f1, f15, f5 +fmul.d f1, f15, f10 +fmul.d f1, f15, f15 +fmul.d f1, f15, f20 +fmul.d f1, f15, f25 +fmul.d f1, f15, f31 +fmul.d f1, f20, f0 +fmul.d f1, f20, f1 +fmul.d f1, f20, f5 +fmul.d f1, f20, f10 +fmul.d f1, f20, f15 +fmul.d f1, f20, f20 +fmul.d f1, f20, f25 +fmul.d f1, f20, f31 +fmul.d f1, f25, f0 +fmul.d f1, f25, f1 +fmul.d f1, f25, f5 +fmul.d f1, f25, f10 +fmul.d f1, f25, f15 +fmul.d f1, f25, f20 +fmul.d f1, f25, f25 +fmul.d f1, f25, f31 +fmul.d f1, f31, f0 +fmul.d f1, f31, f1 +fmul.d f1, f31, f5 +fmul.d f1, f31, f10 +fmul.d f1, f31, f15 +fmul.d f1, f31, f20 +fmul.d f1, f31, f25 +fmul.d f1, f31, f31 +fmul.d f5, f0, f0 +fmul.d f5, f0, f1 +fmul.d f5, f0, f5 +fmul.d f5, f0, f10 +fmul.d f5, f0, f15 +fmul.d f5, f0, f20 +fmul.d f5, f0, f25 +fmul.d f5, f0, f31 +fmul.d f5, f1, f0 +fmul.d f5, f1, f1 +fmul.d f5, f1, f5 +fmul.d f5, f1, f10 +fmul.d f5, f1, f15 +fmul.d f5, f1, f20 +fmul.d f5, f1, f25 +fmul.d f5, f1, f31 +fmul.d f5, f5, f0 +fmul.d f5, f5, f1 +fmul.d f5, f5, f5 +fmul.d f5, f5, f10 +fmul.d f5, f5, f15 +fmul.d f5, f5, f20 +fmul.d f5, f5, f25 +fmul.d f5, f5, f31 +fmul.d f5, f10, f0 +fmul.d f5, f10, f1 +fmul.d f5, f10, f5 +fmul.d f5, f10, f10 +fmul.d f5, f10, f15 +fmul.d f5, f10, f20 +fmul.d f5, f10, f25 +fmul.d f5, f10, f31 +fmul.d f5, f15, f0 +fmul.d f5, f15, f1 +fmul.d f5, f15, f5 +fmul.d f5, f15, f10 +fmul.d f5, f15, f15 +fmul.d f5, f15, f20 +fmul.d f5, f15, f25 +fmul.d f5, f15, f31 +fmul.d f5, f20, f0 +fmul.d f5, f20, f1 +fmul.d f5, f20, f5 +fmul.d f5, f20, f10 +fmul.d f5, f20, f15 +fmul.d f5, f20, f20 +fmul.d f5, f20, f25 +fmul.d f5, f20, f31 +fmul.d f5, f25, f0 +fmul.d f5, f25, f1 +fmul.d f5, f25, f5 +fmul.d f5, f25, f10 +fmul.d f5, f25, f15 +fmul.d f5, f25, f20 +fmul.d f5, f25, f25 +fmul.d f5, f25, f31 +fmul.d f5, f31, f0 +fmul.d f5, f31, f1 +fmul.d f5, f31, f5 +fmul.d f5, f31, f10 +fmul.d f5, f31, f15 +fmul.d f5, f31, f20 +fmul.d f5, f31, f25 +fmul.d f5, f31, f31 +fmul.d f10, f0, f0 +fmul.d f10, f0, f1 +fmul.d f10, f0, f5 +fmul.d f10, f0, f10 +fmul.d f10, f0, f15 +fmul.d f10, f0, f20 +fmul.d f10, f0, f25 +fmul.d f10, f0, f31 +fmul.d f10, f1, f0 +fmul.d f10, f1, f1 +fmul.d f10, f1, f5 +fmul.d f10, f1, f10 +fmul.d f10, f1, f15 +fmul.d f10, f1, f20 +fmul.d f10, f1, f25 +fmul.d f10, f1, f31 +fmul.d f10, f5, f0 +fmul.d f10, f5, f1 +fmul.d f10, f5, f5 +fmul.d f10, f5, f10 +fmul.d f10, f5, f15 +fmul.d f10, f5, f20 +fmul.d f10, f5, f25 +fmul.d f10, f5, f31 +fmul.d f10, f10, f0 +fmul.d f10, f10, f1 +fmul.d f10, f10, f5 +fmul.d f10, f10, f10 +fmul.d f10, f10, f15 +fmul.d f10, f10, f20 +fmul.d f10, f10, f25 +fmul.d f10, f10, f31 +fmul.d f10, f15, f0 +fmul.d f10, f15, f1 +fmul.d f10, f15, f5 +fmul.d f10, f15, f10 +fmul.d f10, f15, f15 +fmul.d f10, f15, f20 +fmul.d f10, f15, f25 +fmul.d f10, f15, f31 +fmul.d f10, f20, f0 +fmul.d f10, f20, f1 +fmul.d f10, f20, f5 +fmul.d f10, f20, f10 +fmul.d f10, f20, f15 +fmul.d f10, f20, f20 +fmul.d f10, f20, f25 +fmul.d f10, f20, f31 +fmul.d f10, f25, f0 +fmul.d f10, f25, f1 +fmul.d f10, f25, f5 +fmul.d f10, f25, f10 +fmul.d f10, f25, f15 +fmul.d f10, f25, f20 +fmul.d f10, f25, f25 +fmul.d f10, f25, f31 +fmul.d f10, f31, f0 +fmul.d f10, f31, f1 +fmul.d f10, f31, f5 +fmul.d f10, f31, f10 +fmul.d f10, f31, f15 +fmul.d f10, f31, f20 +fmul.d f10, f31, f25 +fmul.d f10, f31, f31 +fmul.d f15, f0, f0 +fmul.d f15, f0, f1 +fmul.d f15, f0, f5 +fmul.d f15, f0, f10 +fmul.d f15, f0, f15 +fmul.d f15, f0, f20 +fmul.d f15, f0, f25 +fmul.d f15, f0, f31 +fmul.d f15, f1, f0 +fmul.d f15, f1, f1 +fmul.d f15, f1, f5 +fmul.d f15, f1, f10 +fmul.d f15, f1, f15 +fmul.d f15, f1, f20 +fmul.d f15, f1, f25 +fmul.d f15, f1, f31 +fmul.d f15, f5, f0 +fmul.d f15, f5, f1 +fmul.d f15, f5, f5 +fmul.d f15, f5, f10 +fmul.d f15, f5, f15 +fmul.d f15, f5, f20 +fmul.d f15, f5, f25 +fmul.d f15, f5, f31 +fmul.d f15, f10, f0 +fmul.d f15, f10, f1 +fmul.d f15, f10, f5 +fmul.d f15, f10, f10 +fmul.d f15, f10, f15 +fmul.d f15, f10, f20 +fmul.d f15, f10, f25 +fmul.d f15, f10, f31 +fmul.d f15, f15, f0 +fmul.d f15, f15, f1 +fmul.d f15, f15, f5 +fmul.d f15, f15, f10 +fmul.d f15, f15, f15 +fmul.d f15, f15, f20 +fmul.d f15, f15, f25 +fmul.d f15, f15, f31 +fmul.d f15, f20, f0 +fmul.d f15, f20, f1 +fmul.d f15, f20, f5 +fmul.d f15, f20, f10 +fmul.d f15, f20, f15 +fmul.d f15, f20, f20 +fmul.d f15, f20, f25 +fmul.d f15, f20, f31 +fmul.d f15, f25, f0 +fmul.d f15, f25, f1 +fmul.d f15, f25, f5 +fmul.d f15, f25, f10 +fmul.d f15, f25, f15 +fmul.d f15, f25, f20 +fmul.d f15, f25, f25 +fmul.d f15, f25, f31 +fmul.d f15, f31, f0 +fmul.d f15, f31, f1 +fmul.d f15, f31, f5 +fmul.d f15, f31, f10 +fmul.d f15, f31, f15 +fmul.d f15, f31, f20 +fmul.d f15, f31, f25 +fmul.d f15, f31, f31 +fmul.d f20, f0, f0 +fmul.d f20, f0, f1 +fmul.d f20, f0, f5 +fmul.d f20, f0, f10 +fmul.d f20, f0, f15 +fmul.d f20, f0, f20 +fmul.d f20, f0, f25 +fmul.d f20, f0, f31 +fmul.d f20, f1, f0 +fmul.d f20, f1, f1 +fmul.d f20, f1, f5 +fmul.d f20, f1, f10 +fmul.d f20, f1, f15 +fmul.d f20, f1, f20 +fmul.d f20, f1, f25 +fmul.d f20, f1, f31 +fmul.d f20, f5, f0 +fmul.d f20, f5, f1 +fmul.d f20, f5, f5 +fmul.d f20, f5, f10 +fmul.d f20, f5, f15 +fmul.d f20, f5, f20 +fmul.d f20, f5, f25 +fmul.d f20, f5, f31 +fmul.d f20, f10, f0 +fmul.d f20, f10, f1 +fmul.d f20, f10, f5 +fmul.d f20, f10, f10 +fmul.d f20, f10, f15 +fmul.d f20, f10, f20 +fmul.d f20, f10, f25 +fmul.d f20, f10, f31 +fmul.d f20, f15, f0 +fmul.d f20, f15, f1 +fmul.d f20, f15, f5 +fmul.d f20, f15, f10 +fmul.d f20, f15, f15 +fmul.d f20, f15, f20 +fmul.d f20, f15, f25 +fmul.d f20, f15, f31 +fmul.d f20, f20, f0 +fmul.d f20, f20, f1 +fmul.d f20, f20, f5 +fmul.d f20, f20, f10 +fmul.d f20, f20, f15 +fmul.d f20, f20, f20 +fmul.d f20, f20, f25 +fmul.d f20, f20, f31 +fmul.d f20, f25, f0 +fmul.d f20, f25, f1 +fmul.d f20, f25, f5 +fmul.d f20, f25, f10 +fmul.d f20, f25, f15 +fmul.d f20, f25, f20 +fmul.d f20, f25, f25 +fmul.d f20, f25, f31 +fmul.d f20, f31, f0 +fmul.d f20, f31, f1 +fmul.d f20, f31, f5 +fmul.d f20, f31, f10 +fmul.d f20, f31, f15 +fmul.d f20, f31, f20 +fmul.d f20, f31, f25 +fmul.d f20, f31, f31 +fmul.d f25, f0, f0 +fmul.d f25, f0, f1 +fmul.d f25, f0, f5 +fmul.d f25, f0, f10 +fmul.d f25, f0, f15 +fmul.d f25, f0, f20 +fmul.d f25, f0, f25 +fmul.d f25, f0, f31 +fmul.d f25, f1, f0 +fmul.d f25, f1, f1 +fmul.d f25, f1, f5 +fmul.d f25, f1, f10 +fmul.d f25, f1, f15 +fmul.d f25, f1, f20 +fmul.d f25, f1, f25 +fmul.d f25, f1, f31 +fmul.d f25, f5, f0 +fmul.d f25, f5, f1 +fmul.d f25, f5, f5 +fmul.d f25, f5, f10 +fmul.d f25, f5, f15 +fmul.d f25, f5, f20 +fmul.d f25, f5, f25 +fmul.d f25, f5, f31 +fmul.d f25, f10, f0 +fmul.d f25, f10, f1 +fmul.d f25, f10, f5 +fmul.d f25, f10, f10 +fmul.d f25, f10, f15 +fmul.d f25, f10, f20 +fmul.d f25, f10, f25 +fmul.d f25, f10, f31 +fmul.d f25, f15, f0 +fmul.d f25, f15, f1 +fmul.d f25, f15, f5 +fmul.d f25, f15, f10 +fmul.d f25, f15, f15 +fmul.d f25, f15, f20 +fmul.d f25, f15, f25 +fmul.d f25, f15, f31 +fmul.d f25, f20, f0 +fmul.d f25, f20, f1 +fmul.d f25, f20, f5 +fmul.d f25, f20, f10 +fmul.d f25, f20, f15 +fmul.d f25, f20, f20 +fmul.d f25, f20, f25 +fmul.d f25, f20, f31 +fmul.d f25, f25, f0 +fmul.d f25, f25, f1 +fmul.d f25, f25, f5 +fmul.d f25, f25, f10 +fmul.d f25, f25, f15 +fmul.d f25, f25, f20 +fmul.d f25, f25, f25 +fmul.d f25, f25, f31 +fmul.d f25, f31, f0 +fmul.d f25, f31, f1 +fmul.d f25, f31, f5 +fmul.d f25, f31, f10 +fmul.d f25, f31, f15 +fmul.d f25, f31, f20 +fmul.d f25, f31, f25 +fmul.d f25, f31, f31 +fmul.d f31, f0, f0 +fmul.d f31, f0, f1 +fmul.d f31, f0, f5 +fmul.d f31, f0, f10 +fmul.d f31, f0, f15 +fmul.d f31, f0, f20 +fmul.d f31, f0, f25 +fmul.d f31, f0, f31 +fmul.d f31, f1, f0 +fmul.d f31, f1, f1 +fmul.d f31, f1, f5 +fmul.d f31, f1, f10 +fmul.d f31, f1, f15 +fmul.d f31, f1, f20 +fmul.d f31, f1, f25 +fmul.d f31, f1, f31 +fmul.d f31, f5, f0 +fmul.d f31, f5, f1 +fmul.d f31, f5, f5 +fmul.d f31, f5, f10 +fmul.d f31, f5, f15 +fmul.d f31, f5, f20 +fmul.d f31, f5, f25 +fmul.d f31, f5, f31 +fmul.d f31, f10, f0 +fmul.d f31, f10, f1 +fmul.d f31, f10, f5 +fmul.d f31, f10, f10 +fmul.d f31, f10, f15 +fmul.d f31, f10, f20 +fmul.d f31, f10, f25 +fmul.d f31, f10, f31 +fmul.d f31, f15, f0 +fmul.d f31, f15, f1 +fmul.d f31, f15, f5 +fmul.d f31, f15, f10 +fmul.d f31, f15, f15 +fmul.d f31, f15, f20 +fmul.d f31, f15, f25 +fmul.d f31, f15, f31 +fmul.d f31, f20, f0 +fmul.d f31, f20, f1 +fmul.d f31, f20, f5 +fmul.d f31, f20, f10 +fmul.d f31, f20, f15 +fmul.d f31, f20, f20 +fmul.d f31, f20, f25 +fmul.d f31, f20, f31 +fmul.d f31, f25, f0 +fmul.d f31, f25, f1 +fmul.d f31, f25, f5 +fmul.d f31, f25, f10 +fmul.d f31, f25, f15 +fmul.d f31, f25, f20 +fmul.d f31, f25, f25 +fmul.d f31, f25, f31 +fmul.d f31, f31, f0 +fmul.d f31, f31, f1 +fmul.d f31, f31, f5 +fmul.d f31, f31, f10 +fmul.d f31, f31, f15 +fmul.d f31, f31, f20 +fmul.d f31, f31, f25 +fmul.d f31, f31, f31 diff --git a/tests/riscv/d-extension/fmul_d.asm b/tests/riscv/d-extension/fmul_d.asm new file mode 100644 index 0000000..3d01026 --- /dev/null +++ b/tests/riscv/d-extension/fmul_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fmul.d f0, f1, f2 + diff --git a/tests/riscv/d-extension/fmul_d.bin b/tests/riscv/d-extension/fmul_d.bin new file mode 100644 index 0000000..d51ebe9 --- /dev/null +++ b/tests/riscv/d-extension/fmul_d.bin @@ -0,0 +1 @@ +S  \ No newline at end of file diff --git a/tests/riscv/d-extension/fmul_d.disasm b/tests/riscv/d-extension/fmul_d.disasm new file mode 100644 index 0000000..961625d --- /dev/null +++ b/tests/riscv/d-extension/fmul_d.disasm @@ -0,0 +1 @@ +fmul.d f0, f1, f2 diff --git a/tests/riscv/d-extension/fnmadd.d.asm b/tests/riscv/d-extension/fnmadd.d.asm new file mode 100644 index 0000000..b4dd7a3 --- /dev/null +++ b/tests/riscv/d-extension/fnmadd.d.asm @@ -0,0 +1,4100 @@ +.lang riscv32 +.org 0x0 + +fnmadd.d f0, f0, f0, f0 +fnmadd.d f0, f0, f0, f1 +fnmadd.d f0, f0, f0, f5 +fnmadd.d f0, f0, f0, f10 +fnmadd.d f0, f0, f0, f15 +fnmadd.d f0, f0, f0, f20 +fnmadd.d f0, f0, f0, f25 +fnmadd.d f0, f0, f0, f31 +fnmadd.d f0, f0, f1, f0 +fnmadd.d f0, f0, f1, f1 +fnmadd.d f0, f0, f1, f5 +fnmadd.d f0, f0, f1, f10 +fnmadd.d f0, f0, f1, f15 +fnmadd.d f0, f0, f1, f20 +fnmadd.d f0, f0, f1, f25 +fnmadd.d f0, f0, f1, f31 +fnmadd.d f0, f0, f5, f0 +fnmadd.d f0, f0, f5, f1 +fnmadd.d f0, f0, f5, f5 +fnmadd.d f0, f0, f5, f10 +fnmadd.d f0, f0, f5, f15 +fnmadd.d f0, f0, f5, f20 +fnmadd.d f0, f0, f5, f25 +fnmadd.d f0, f0, f5, f31 +fnmadd.d f0, f0, f10, f0 +fnmadd.d f0, f0, f10, f1 +fnmadd.d f0, f0, f10, f5 +fnmadd.d f0, f0, f10, f10 +fnmadd.d f0, f0, f10, f15 +fnmadd.d f0, f0, f10, f20 +fnmadd.d f0, f0, f10, f25 +fnmadd.d f0, f0, f10, f31 +fnmadd.d f0, f0, f15, f0 +fnmadd.d f0, f0, f15, f1 +fnmadd.d f0, f0, f15, f5 +fnmadd.d f0, f0, f15, f10 +fnmadd.d f0, f0, f15, f15 +fnmadd.d f0, f0, f15, f20 +fnmadd.d f0, f0, f15, f25 +fnmadd.d f0, f0, f15, f31 +fnmadd.d f0, f0, f20, f0 +fnmadd.d f0, f0, f20, f1 +fnmadd.d f0, f0, f20, f5 +fnmadd.d f0, f0, f20, f10 +fnmadd.d f0, f0, f20, f15 +fnmadd.d f0, f0, f20, f20 +fnmadd.d f0, f0, f20, f25 +fnmadd.d f0, f0, f20, f31 +fnmadd.d f0, f0, f25, f0 +fnmadd.d f0, f0, f25, f1 +fnmadd.d f0, f0, f25, f5 +fnmadd.d f0, f0, f25, f10 +fnmadd.d f0, f0, f25, f15 +fnmadd.d f0, f0, f25, f20 +fnmadd.d f0, f0, f25, f25 +fnmadd.d f0, f0, f25, f31 +fnmadd.d f0, f0, f31, f0 +fnmadd.d f0, f0, f31, f1 +fnmadd.d f0, f0, f31, f5 +fnmadd.d f0, f0, f31, f10 +fnmadd.d f0, f0, f31, f15 +fnmadd.d f0, f0, f31, f20 +fnmadd.d f0, f0, f31, f25 +fnmadd.d f0, f0, f31, f31 +fnmadd.d f0, f1, f0, f0 +fnmadd.d f0, f1, f0, f1 +fnmadd.d f0, f1, f0, f5 +fnmadd.d f0, f1, f0, f10 +fnmadd.d f0, f1, f0, f15 +fnmadd.d f0, f1, f0, f20 +fnmadd.d f0, f1, f0, f25 +fnmadd.d f0, f1, f0, f31 +fnmadd.d f0, f1, f1, f0 +fnmadd.d f0, f1, f1, f1 +fnmadd.d f0, f1, f1, f5 +fnmadd.d f0, f1, f1, f10 +fnmadd.d f0, f1, f1, f15 +fnmadd.d f0, f1, f1, f20 +fnmadd.d f0, f1, f1, f25 +fnmadd.d f0, f1, f1, f31 +fnmadd.d f0, f1, f5, f0 +fnmadd.d f0, f1, f5, f1 +fnmadd.d f0, f1, f5, f5 +fnmadd.d f0, f1, f5, f10 +fnmadd.d f0, f1, f5, f15 +fnmadd.d f0, f1, f5, f20 +fnmadd.d f0, f1, f5, f25 +fnmadd.d f0, f1, f5, f31 +fnmadd.d f0, f1, f10, f0 +fnmadd.d f0, f1, f10, f1 +fnmadd.d f0, f1, f10, f5 +fnmadd.d f0, f1, f10, f10 +fnmadd.d f0, f1, f10, f15 +fnmadd.d f0, f1, f10, f20 +fnmadd.d f0, f1, f10, f25 +fnmadd.d f0, f1, f10, f31 +fnmadd.d f0, f1, f15, f0 +fnmadd.d f0, f1, f15, f1 +fnmadd.d f0, f1, f15, f5 +fnmadd.d f0, f1, f15, f10 +fnmadd.d f0, f1, f15, f15 +fnmadd.d f0, f1, f15, f20 +fnmadd.d f0, f1, f15, f25 +fnmadd.d f0, f1, f15, f31 +fnmadd.d f0, f1, f20, f0 +fnmadd.d f0, f1, f20, f1 +fnmadd.d f0, f1, f20, f5 +fnmadd.d f0, f1, f20, f10 +fnmadd.d f0, f1, f20, f15 +fnmadd.d f0, f1, f20, f20 +fnmadd.d f0, f1, f20, f25 +fnmadd.d f0, f1, f20, f31 +fnmadd.d f0, f1, f25, f0 +fnmadd.d f0, f1, f25, f1 +fnmadd.d f0, f1, f25, f5 +fnmadd.d f0, f1, f25, f10 +fnmadd.d f0, f1, f25, f15 +fnmadd.d f0, f1, f25, f20 +fnmadd.d f0, f1, f25, f25 +fnmadd.d f0, f1, f25, f31 +fnmadd.d f0, f1, f31, f0 +fnmadd.d f0, f1, f31, f1 +fnmadd.d f0, f1, f31, f5 +fnmadd.d f0, f1, f31, f10 +fnmadd.d f0, f1, f31, f15 +fnmadd.d f0, f1, f31, f20 +fnmadd.d f0, f1, f31, f25 +fnmadd.d f0, f1, f31, f31 +fnmadd.d f0, f5, f0, f0 +fnmadd.d f0, f5, f0, f1 +fnmadd.d f0, f5, f0, f5 +fnmadd.d f0, f5, f0, f10 +fnmadd.d f0, f5, f0, f15 +fnmadd.d f0, f5, f0, f20 +fnmadd.d f0, f5, f0, f25 +fnmadd.d f0, f5, f0, f31 +fnmadd.d f0, f5, f1, f0 +fnmadd.d f0, f5, f1, f1 +fnmadd.d f0, f5, f1, f5 +fnmadd.d f0, f5, f1, f10 +fnmadd.d f0, f5, f1, f15 +fnmadd.d f0, f5, f1, f20 +fnmadd.d f0, f5, f1, f25 +fnmadd.d f0, f5, f1, f31 +fnmadd.d f0, f5, f5, f0 +fnmadd.d f0, f5, f5, f1 +fnmadd.d f0, f5, f5, f5 +fnmadd.d f0, f5, f5, f10 +fnmadd.d f0, f5, f5, f15 +fnmadd.d f0, f5, f5, f20 +fnmadd.d f0, f5, f5, f25 +fnmadd.d f0, f5, f5, f31 +fnmadd.d f0, f5, f10, f0 +fnmadd.d f0, f5, f10, f1 +fnmadd.d f0, f5, f10, f5 +fnmadd.d f0, f5, f10, f10 +fnmadd.d f0, f5, f10, f15 +fnmadd.d f0, f5, f10, f20 +fnmadd.d f0, f5, f10, f25 +fnmadd.d f0, f5, f10, f31 +fnmadd.d f0, f5, f15, f0 +fnmadd.d f0, f5, f15, f1 +fnmadd.d f0, f5, f15, f5 +fnmadd.d f0, f5, f15, f10 +fnmadd.d f0, f5, f15, f15 +fnmadd.d f0, f5, f15, f20 +fnmadd.d f0, f5, f15, f25 +fnmadd.d f0, f5, f15, f31 +fnmadd.d f0, f5, f20, f0 +fnmadd.d f0, f5, f20, f1 +fnmadd.d f0, f5, f20, f5 +fnmadd.d f0, f5, f20, f10 +fnmadd.d f0, f5, f20, f15 +fnmadd.d f0, f5, f20, f20 +fnmadd.d f0, f5, f20, f25 +fnmadd.d f0, f5, f20, f31 +fnmadd.d f0, f5, f25, f0 +fnmadd.d f0, f5, f25, f1 +fnmadd.d f0, f5, f25, f5 +fnmadd.d f0, f5, f25, f10 +fnmadd.d f0, f5, f25, f15 +fnmadd.d f0, f5, f25, f20 +fnmadd.d f0, f5, f25, f25 +fnmadd.d f0, f5, f25, f31 +fnmadd.d f0, f5, f31, f0 +fnmadd.d f0, f5, f31, f1 +fnmadd.d f0, f5, f31, f5 +fnmadd.d f0, f5, f31, f10 +fnmadd.d f0, f5, f31, f15 +fnmadd.d f0, f5, f31, f20 +fnmadd.d f0, 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+fnmadd.d f31, f5, f25, f0 +fnmadd.d f31, f5, f25, f1 +fnmadd.d f31, f5, f25, f5 +fnmadd.d f31, f5, f25, f10 +fnmadd.d f31, f5, f25, f15 +fnmadd.d f31, f5, f25, f20 +fnmadd.d f31, f5, f25, f25 +fnmadd.d f31, f5, f25, f31 +fnmadd.d f31, f5, f31, f0 +fnmadd.d f31, f5, f31, f1 +fnmadd.d f31, f5, f31, f5 +fnmadd.d f31, f5, f31, f10 +fnmadd.d f31, f5, f31, f15 +fnmadd.d f31, f5, f31, f20 +fnmadd.d f31, f5, f31, f25 +fnmadd.d f31, f5, f31, f31 +fnmadd.d f31, f10, f0, f0 +fnmadd.d f31, f10, f0, f1 +fnmadd.d f31, f10, f0, f5 +fnmadd.d f31, f10, f0, f10 +fnmadd.d f31, f10, f0, f15 +fnmadd.d f31, f10, f0, f20 +fnmadd.d f31, f10, f0, f25 +fnmadd.d f31, f10, f0, f31 +fnmadd.d f31, f10, f1, f0 +fnmadd.d f31, f10, f1, f1 +fnmadd.d f31, f10, f1, f5 +fnmadd.d f31, f10, f1, f10 +fnmadd.d f31, f10, f1, f15 +fnmadd.d f31, f10, f1, f20 +fnmadd.d f31, f10, f1, f25 +fnmadd.d f31, f10, f1, f31 +fnmadd.d f31, f10, f5, f0 +fnmadd.d f31, f10, f5, f1 +fnmadd.d f31, f10, f5, f5 +fnmadd.d f31, f10, f5, f10 +fnmadd.d f31, f10, f5, f15 +fnmadd.d f31, f10, f5, f20 +fnmadd.d f31, f10, f5, f25 +fnmadd.d f31, f10, f5, f31 +fnmadd.d f31, f10, f10, f0 +fnmadd.d f31, f10, f10, f1 +fnmadd.d f31, f10, f10, f5 +fnmadd.d f31, f10, f10, f10 +fnmadd.d f31, f10, f10, f15 +fnmadd.d f31, f10, f10, f20 +fnmadd.d f31, f10, f10, f25 +fnmadd.d f31, f10, f10, f31 +fnmadd.d f31, f10, f15, f0 +fnmadd.d f31, f10, f15, f1 +fnmadd.d f31, f10, f15, f5 +fnmadd.d f31, f10, f15, f10 +fnmadd.d f31, f10, f15, f15 +fnmadd.d f31, f10, f15, f20 +fnmadd.d f31, f10, f15, f25 +fnmadd.d f31, f10, f15, f31 +fnmadd.d f31, f10, f20, f0 +fnmadd.d f31, f10, f20, f1 +fnmadd.d f31, f10, f20, f5 +fnmadd.d f31, f10, f20, f10 +fnmadd.d f31, f10, f20, f15 +fnmadd.d f31, f10, f20, f20 +fnmadd.d f31, f10, f20, f25 +fnmadd.d f31, f10, f20, f31 +fnmadd.d f31, f10, f25, f0 +fnmadd.d f31, f10, f25, f1 +fnmadd.d f31, f10, f25, f5 +fnmadd.d f31, f10, f25, f10 +fnmadd.d f31, f10, f25, f15 +fnmadd.d f31, f10, f25, f20 +fnmadd.d f31, f10, f25, f25 +fnmadd.d f31, f10, f25, f31 +fnmadd.d f31, f10, f31, f0 +fnmadd.d f31, f10, f31, f1 +fnmadd.d f31, f10, f31, f5 +fnmadd.d f31, f10, f31, f10 +fnmadd.d f31, f10, f31, f15 +fnmadd.d f31, f10, f31, f20 +fnmadd.d f31, f10, f31, f25 +fnmadd.d f31, f10, f31, f31 +fnmadd.d f31, f15, f0, f0 +fnmadd.d f31, f15, f0, f1 +fnmadd.d f31, f15, f0, f5 +fnmadd.d f31, f15, f0, f10 +fnmadd.d f31, f15, f0, f15 +fnmadd.d f31, f15, f0, f20 +fnmadd.d f31, f15, f0, f25 +fnmadd.d f31, f15, f0, f31 +fnmadd.d f31, f15, f1, f0 +fnmadd.d f31, f15, f1, f1 +fnmadd.d f31, f15, f1, f5 +fnmadd.d f31, f15, f1, f10 +fnmadd.d f31, f15, f1, f15 +fnmadd.d f31, f15, f1, f20 +fnmadd.d f31, f15, f1, f25 +fnmadd.d f31, f15, f1, f31 +fnmadd.d f31, f15, f5, f0 +fnmadd.d f31, f15, f5, f1 +fnmadd.d f31, f15, f5, f5 +fnmadd.d f31, f15, f5, f10 +fnmadd.d f31, f15, f5, f15 +fnmadd.d f31, f15, f5, f20 +fnmadd.d f31, f15, f5, f25 +fnmadd.d f31, f15, f5, f31 +fnmadd.d f31, f15, f10, f0 +fnmadd.d f31, f15, f10, f1 +fnmadd.d f31, f15, f10, f5 +fnmadd.d f31, f15, f10, f10 +fnmadd.d f31, f15, f10, f15 +fnmadd.d f31, f15, f10, f20 +fnmadd.d f31, f15, f10, f25 +fnmadd.d f31, f15, f10, f31 +fnmadd.d f31, f15, f15, f0 +fnmadd.d f31, f15, f15, f1 +fnmadd.d f31, f15, f15, f5 +fnmadd.d f31, f15, f15, f10 +fnmadd.d f31, f15, f15, f15 +fnmadd.d f31, f15, f15, f20 +fnmadd.d f31, f15, f15, f25 +fnmadd.d f31, f15, f15, f31 +fnmadd.d f31, f15, f20, f0 +fnmadd.d f31, f15, f20, f1 +fnmadd.d f31, f15, f20, f5 +fnmadd.d f31, f15, f20, f10 +fnmadd.d f31, f15, f20, f15 +fnmadd.d f31, f15, f20, f20 +fnmadd.d f31, f15, f20, f25 +fnmadd.d f31, f15, f20, f31 +fnmadd.d f31, f15, f25, f0 +fnmadd.d f31, f15, f25, f1 +fnmadd.d f31, f15, f25, f5 +fnmadd.d f31, f15, f25, f10 +fnmadd.d f31, f15, f25, f15 +fnmadd.d f31, f15, f25, f20 +fnmadd.d f31, f15, f25, f25 +fnmadd.d f31, f15, f25, f31 +fnmadd.d f31, f15, f31, f0 +fnmadd.d f31, f15, f31, f1 +fnmadd.d f31, f15, f31, f5 +fnmadd.d f31, f15, f31, f10 +fnmadd.d f31, f15, f31, f15 +fnmadd.d f31, f15, f31, f20 +fnmadd.d f31, f15, f31, f25 +fnmadd.d f31, f15, f31, f31 +fnmadd.d f31, f20, f0, f0 +fnmadd.d f31, f20, f0, f1 +fnmadd.d f31, f20, f0, f5 +fnmadd.d f31, f20, f0, f10 +fnmadd.d f31, f20, f0, f15 +fnmadd.d f31, f20, f0, f20 +fnmadd.d f31, f20, f0, f25 +fnmadd.d f31, f20, f0, f31 +fnmadd.d f31, f20, f1, f0 +fnmadd.d f31, f20, f1, f1 +fnmadd.d f31, f20, f1, f5 +fnmadd.d f31, f20, f1, f10 +fnmadd.d f31, f20, f1, f15 +fnmadd.d f31, f20, f1, f20 +fnmadd.d f31, f20, f1, f25 +fnmadd.d f31, f20, f1, f31 +fnmadd.d f31, f20, f5, f0 +fnmadd.d f31, f20, f5, f1 +fnmadd.d f31, f20, f5, f5 +fnmadd.d f31, f20, f5, f10 +fnmadd.d f31, f20, f5, f15 +fnmadd.d f31, f20, f5, f20 +fnmadd.d f31, f20, f5, f25 +fnmadd.d f31, f20, f5, f31 +fnmadd.d f31, f20, f10, f0 +fnmadd.d f31, f20, f10, f1 +fnmadd.d f31, f20, f10, f5 +fnmadd.d f31, f20, f10, f10 +fnmadd.d f31, f20, f10, f15 +fnmadd.d f31, f20, f10, f20 +fnmadd.d f31, f20, f10, f25 +fnmadd.d f31, f20, f10, f31 +fnmadd.d f31, f20, f15, f0 +fnmadd.d f31, f20, f15, f1 +fnmadd.d f31, f20, f15, f5 +fnmadd.d f31, f20, f15, f10 +fnmadd.d f31, f20, f15, f15 +fnmadd.d f31, f20, f15, f20 +fnmadd.d f31, f20, f15, f25 +fnmadd.d f31, f20, f15, f31 +fnmadd.d f31, f20, f20, f0 +fnmadd.d f31, f20, f20, f1 +fnmadd.d f31, f20, f20, f5 +fnmadd.d f31, f20, f20, f10 +fnmadd.d f31, f20, f20, f15 +fnmadd.d f31, f20, f20, f20 +fnmadd.d f31, f20, f20, f25 +fnmadd.d f31, f20, f20, f31 +fnmadd.d f31, f20, f25, f0 +fnmadd.d f31, f20, f25, f1 +fnmadd.d f31, f20, f25, f5 +fnmadd.d f31, f20, f25, f10 +fnmadd.d f31, f20, f25, f15 +fnmadd.d f31, f20, f25, f20 +fnmadd.d f31, f20, f25, f25 +fnmadd.d f31, f20, f25, f31 +fnmadd.d f31, f20, f31, f0 +fnmadd.d f31, f20, f31, f1 +fnmadd.d f31, f20, f31, f5 +fnmadd.d f31, f20, f31, f10 +fnmadd.d f31, f20, f31, f15 +fnmadd.d f31, f20, f31, f20 +fnmadd.d f31, f20, f31, f25 +fnmadd.d f31, f20, f31, f31 +fnmadd.d f31, f25, f0, f0 +fnmadd.d f31, f25, f0, f1 +fnmadd.d f31, f25, f0, f5 +fnmadd.d f31, f25, f0, f10 +fnmadd.d f31, f25, f0, f15 +fnmadd.d f31, f25, f0, f20 +fnmadd.d f31, f25, f0, f25 +fnmadd.d f31, f25, f0, f31 +fnmadd.d f31, f25, f1, f0 +fnmadd.d f31, f25, f1, f1 +fnmadd.d f31, f25, f1, f5 +fnmadd.d f31, f25, f1, f10 +fnmadd.d f31, f25, f1, f15 +fnmadd.d f31, f25, f1, f20 +fnmadd.d f31, f25, f1, f25 +fnmadd.d f31, f25, f1, f31 +fnmadd.d f31, f25, f5, f0 +fnmadd.d f31, f25, f5, f1 +fnmadd.d f31, f25, f5, f5 +fnmadd.d f31, f25, f5, f10 +fnmadd.d f31, f25, f5, f15 +fnmadd.d f31, f25, f5, f20 +fnmadd.d f31, f25, f5, f25 +fnmadd.d f31, f25, f5, f31 +fnmadd.d f31, f25, f10, f0 +fnmadd.d f31, f25, f10, f1 +fnmadd.d f31, f25, f10, f5 +fnmadd.d f31, f25, f10, f10 +fnmadd.d f31, f25, f10, f15 +fnmadd.d f31, f25, f10, f20 +fnmadd.d f31, f25, f10, f25 +fnmadd.d f31, f25, f10, f31 +fnmadd.d f31, f25, f15, f0 +fnmadd.d f31, f25, f15, f1 +fnmadd.d f31, f25, f15, f5 +fnmadd.d f31, f25, f15, f10 +fnmadd.d f31, f25, f15, f15 +fnmadd.d f31, f25, f15, f20 +fnmadd.d f31, f25, f15, f25 +fnmadd.d f31, f25, f15, f31 +fnmadd.d f31, f25, f20, f0 +fnmadd.d f31, f25, f20, f1 +fnmadd.d f31, f25, f20, f5 +fnmadd.d f31, f25, f20, f10 +fnmadd.d f31, f25, f20, f15 +fnmadd.d f31, f25, f20, f20 +fnmadd.d f31, f25, f20, f25 +fnmadd.d f31, f25, f20, f31 +fnmadd.d f31, f25, f25, f0 +fnmadd.d f31, f25, f25, f1 +fnmadd.d f31, f25, f25, f5 +fnmadd.d f31, f25, f25, f10 +fnmadd.d f31, f25, f25, f15 +fnmadd.d f31, f25, f25, f20 +fnmadd.d f31, f25, f25, f25 +fnmadd.d f31, f25, f25, f31 +fnmadd.d f31, f25, f31, f0 +fnmadd.d f31, f25, f31, f1 +fnmadd.d f31, f25, f31, f5 +fnmadd.d f31, f25, f31, f10 +fnmadd.d f31, f25, f31, f15 +fnmadd.d f31, f25, f31, f20 +fnmadd.d f31, f25, f31, f25 +fnmadd.d f31, f25, f31, f31 +fnmadd.d f31, f31, f0, f0 +fnmadd.d f31, f31, f0, f1 +fnmadd.d f31, f31, f0, f5 +fnmadd.d f31, f31, f0, f10 +fnmadd.d f31, f31, f0, f15 +fnmadd.d f31, f31, f0, f20 +fnmadd.d f31, f31, f0, f25 +fnmadd.d f31, f31, f0, f31 +fnmadd.d f31, f31, f1, f0 +fnmadd.d f31, f31, f1, f1 +fnmadd.d f31, f31, f1, f5 +fnmadd.d f31, f31, f1, f10 +fnmadd.d f31, f31, f1, f15 +fnmadd.d f31, f31, f1, f20 +fnmadd.d f31, f31, f1, f25 +fnmadd.d f31, f31, f1, f31 +fnmadd.d f31, f31, f5, f0 +fnmadd.d f31, f31, f5, f1 +fnmadd.d f31, f31, f5, f5 +fnmadd.d f31, f31, f5, f10 +fnmadd.d f31, f31, f5, f15 +fnmadd.d f31, f31, f5, f20 +fnmadd.d f31, f31, f5, f25 +fnmadd.d f31, f31, f5, f31 +fnmadd.d f31, f31, f10, f0 +fnmadd.d f31, f31, f10, f1 +fnmadd.d f31, f31, f10, f5 +fnmadd.d f31, f31, f10, f10 +fnmadd.d f31, f31, f10, f15 +fnmadd.d f31, f31, f10, f20 +fnmadd.d f31, f31, f10, f25 +fnmadd.d f31, f31, f10, f31 +fnmadd.d f31, f31, f15, f0 +fnmadd.d f31, f31, f15, f1 +fnmadd.d f31, f31, f15, f5 +fnmadd.d f31, f31, f15, f10 +fnmadd.d f31, f31, f15, f15 +fnmadd.d f31, f31, f15, f20 +fnmadd.d f31, f31, f15, f25 +fnmadd.d f31, f31, f15, f31 +fnmadd.d f31, f31, f20, f0 +fnmadd.d f31, f31, f20, f1 +fnmadd.d f31, f31, f20, f5 +fnmadd.d f31, f31, f20, f10 +fnmadd.d f31, f31, f20, f15 +fnmadd.d f31, f31, f20, f20 +fnmadd.d f31, f31, f20, f25 +fnmadd.d f31, f31, f20, f31 +fnmadd.d f31, f31, f25, f0 +fnmadd.d f31, f31, f25, f1 +fnmadd.d f31, f31, f25, f5 +fnmadd.d f31, f31, f25, f10 +fnmadd.d f31, f31, f25, f15 +fnmadd.d f31, f31, f25, f20 +fnmadd.d f31, f31, f25, f25 +fnmadd.d f31, f31, f25, f31 +fnmadd.d f31, f31, f31, f0 +fnmadd.d f31, f31, f31, f1 +fnmadd.d f31, f31, f31, f5 +fnmadd.d f31, f31, f31, f10 +fnmadd.d f31, f31, f31, f15 +fnmadd.d f31, f31, f31, f20 +fnmadd.d f31, f31, f31, f25 +fnmadd.d f31, f31, f31, f31 diff --git a/tests/riscv/d-extension/fnmadd_d.asm b/tests/riscv/d-extension/fnmadd_d.asm new file mode 100644 index 0000000..ecfec1e --- /dev/null +++ b/tests/riscv/d-extension/fnmadd_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fnmadd.d f0, f1, f2, f3 + diff --git a/tests/riscv/d-extension/fnmadd_d.bin b/tests/riscv/d-extension/fnmadd_d.bin new file mode 100644 index 0000000..609e9db --- /dev/null +++ b/tests/riscv/d-extension/fnmadd_d.bin @@ -0,0 +1 @@ +O  \ No newline at end of file diff --git a/tests/riscv/d-extension/fnmadd_d.disasm b/tests/riscv/d-extension/fnmadd_d.disasm new file mode 100644 index 0000000..e930682 --- /dev/null +++ b/tests/riscv/d-extension/fnmadd_d.disasm @@ -0,0 +1 @@ +fnmadd.d f0, f1, f2, f3 diff --git a/tests/riscv/d-extension/fnmsub.d.asm b/tests/riscv/d-extension/fnmsub.d.asm new file mode 100644 index 0000000..2be4bd3 --- /dev/null +++ b/tests/riscv/d-extension/fnmsub.d.asm @@ -0,0 +1,4100 @@ +.lang riscv32 +.org 0x0 + +fnmsub.d f0, f0, f0, f0 +fnmsub.d f0, f0, f0, f1 +fnmsub.d f0, f0, f0, f5 +fnmsub.d f0, f0, f0, f10 +fnmsub.d f0, f0, f0, f15 +fnmsub.d f0, f0, f0, f20 +fnmsub.d f0, f0, f0, f25 +fnmsub.d f0, f0, f0, f31 +fnmsub.d f0, f0, f1, f0 +fnmsub.d f0, f0, f1, f1 +fnmsub.d f0, f0, f1, f5 +fnmsub.d f0, f0, f1, f10 +fnmsub.d f0, f0, f1, f15 +fnmsub.d f0, f0, f1, f20 +fnmsub.d f0, f0, f1, f25 +fnmsub.d f0, f0, f1, f31 +fnmsub.d f0, f0, f5, f0 +fnmsub.d f0, f0, f5, f1 +fnmsub.d f0, f0, f5, f5 +fnmsub.d f0, f0, f5, f10 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0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fsd.disasm b/tests/riscv/d-extension/fsd.disasm new file mode 100644 index 0000000..649ecba --- /dev/null +++ b/tests/riscv/d-extension/fsd.disasm @@ -0,0 +1,1600 @@ +fsd f0, (#-2047, zero) +fsd f0, (#-1024, zero) +fsd f0, (#-512, zero) +fsd f0, (#-256, zero) +fsd f0, (#-128, zero) +fsd f0, (#-64, zero) +fsd f0, (#-32, zero) +fsd f0, (#-16, zero) +fsd f0, (#-8, zero) +fsd f0, (#-4, zero) +fsd f0, (#-2, zero) +fsd f0, (#-1, zero) +fsd f0, (#0, zero) +fsd f0, (#1, zero) +fsd f0, (#2, zero) +fsd f0, (#4, zero) +fsd f0, (#8, zero) +fsd f0, (#16, zero) +fsd f0, (#32, zero) +fsd f0, (#64, zero) +fsd f0, (#128, zero) +fsd f0, (#256, zero) +fsd f0, (#512, zero) +fsd f0, (#1024, zero) +fsd f0, (#2047, zero) +fsd f0, (#-2047, ra) +fsd f0, (#-1024, ra) +fsd f0, (#-512, ra) +fsd f0, (#-256, ra) +fsd f0, (#-128, ra) +fsd f0, (#-64, ra) +fsd f0, (#-32, ra) +fsd f0, (#-16, ra) +fsd f0, (#-8, ra) +fsd f0, (#-4, ra) +fsd f0, (#-2, ra) +fsd f0, (#-1, ra) +fsd f0, (#0, ra) +fsd f0, (#1, ra) +fsd f0, (#2, ra) +fsd f0, (#4, ra) +fsd f0, (#8, ra) +fsd f0, (#16, ra) +fsd f0, (#32, ra) +fsd f0, (#64, ra) +fsd f0, (#128, ra) +fsd f0, (#256, ra) +fsd f0, (#512, ra) +fsd f0, (#1024, ra) +fsd f0, (#2047, ra) +fsd f0, (#-2047, t0) +fsd f0, (#-1024, t0) +fsd f0, (#-512, t0) +fsd f0, (#-256, t0) +fsd f0, (#-128, t0) +fsd f0, (#-64, t0) +fsd f0, (#-32, t0) +fsd f0, (#-16, t0) +fsd f0, (#-8, t0) +fsd f0, (#-4, t0) +fsd f0, (#-2, t0) +fsd f0, (#-1, t0) +fsd f0, (#0, t0) +fsd f0, (#1, t0) +fsd f0, (#2, t0) +fsd f0, (#4, t0) +fsd f0, (#8, t0) +fsd f0, (#16, t0) +fsd f0, (#32, t0) +fsd f0, (#64, t0) +fsd f0, (#128, t0) +fsd f0, (#256, t0) +fsd f0, (#512, t0) +fsd f0, (#1024, t0) +fsd f0, (#2047, t0) +fsd f0, (#-2047, a0) +fsd f0, (#-1024, a0) +fsd f0, (#-512, a0) +fsd f0, (#-256, a0) +fsd f0, (#-128, a0) +fsd f0, (#-64, a0) +fsd f0, (#-32, a0) +fsd f0, (#-16, a0) +fsd f0, (#-8, a0) +fsd f0, (#-4, a0) +fsd f0, (#-2, a0) +fsd f0, (#-1, a0) +fsd f0, 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f25, (#-32, t0) +fsd f25, (#-16, t0) +fsd f25, (#-8, t0) +fsd f25, (#-4, t0) +fsd f25, (#-2, t0) +fsd f25, (#-1, t0) +fsd f25, (#0, t0) +fsd f25, (#1, t0) +fsd f25, (#2, t0) +fsd f25, (#4, t0) +fsd f25, (#8, t0) +fsd f25, (#16, t0) +fsd f25, (#32, t0) +fsd f25, (#64, t0) +fsd f25, (#128, t0) +fsd f25, (#256, t0) +fsd f25, (#512, t0) +fsd f25, (#1024, t0) +fsd f25, (#2047, t0) +fsd f25, (#-2047, a0) +fsd f25, (#-1024, a0) +fsd f25, (#-512, a0) +fsd f25, (#-256, a0) +fsd f25, (#-128, a0) +fsd f25, (#-64, a0) +fsd f25, (#-32, a0) +fsd f25, (#-16, a0) +fsd f25, (#-8, a0) +fsd f25, (#-4, a0) +fsd f25, (#-2, a0) +fsd f25, (#-1, a0) +fsd f25, (#0, a0) +fsd f25, (#1, a0) +fsd f25, (#2, a0) +fsd f25, (#4, a0) +fsd f25, (#8, a0) +fsd f25, (#16, a0) +fsd f25, (#32, a0) +fsd f25, (#64, a0) +fsd f25, (#128, a0) +fsd f25, (#256, a0) +fsd f25, (#512, a0) +fsd f25, (#1024, a0) +fsd f25, (#2047, a0) +fsd f25, (#-2047, a5) +fsd f25, (#-1024, a5) +fsd f25, (#-512, a5) +fsd f25, (#-256, a5) +fsd f25, (#-128, a5) +fsd f25, (#-64, a5) +fsd f25, (#-32, a5) +fsd f25, (#-16, a5) +fsd f25, (#-8, a5) +fsd f25, (#-4, a5) +fsd f25, (#-2, a5) +fsd f25, (#-1, a5) +fsd f25, (#0, a5) +fsd f25, (#1, a5) +fsd f25, (#2, a5) +fsd f25, (#4, a5) +fsd f25, (#8, a5) +fsd f25, (#16, a5) +fsd f25, (#32, a5) +fsd f25, (#64, a5) +fsd f25, (#128, a5) +fsd f25, (#256, a5) +fsd f25, (#512, a5) +fsd f25, (#1024, a5) +fsd f25, (#2047, a5) +fsd f25, (#-2047, s4) +fsd f25, (#-1024, s4) +fsd f25, (#-512, s4) +fsd f25, (#-256, s4) +fsd f25, (#-128, s4) +fsd f25, (#-64, s4) +fsd f25, (#-32, s4) +fsd f25, (#-16, s4) +fsd f25, (#-8, s4) +fsd f25, (#-4, s4) +fsd f25, (#-2, s4) +fsd f25, (#-1, s4) +fsd f25, (#0, s4) +fsd f25, (#1, s4) +fsd f25, (#2, s4) +fsd f25, (#4, s4) +fsd f25, (#8, s4) +fsd f25, (#16, s4) +fsd f25, (#32, s4) +fsd f25, (#64, s4) +fsd f25, (#128, s4) +fsd f25, (#256, s4) +fsd f25, (#512, s4) +fsd f25, (#1024, s4) +fsd f25, (#2047, s4) +fsd f25, (#-2047, s9) +fsd f25, (#-1024, s9) +fsd f25, (#-512, s9) +fsd f25, (#-256, s9) +fsd f25, (#-128, s9) +fsd f25, (#-64, s9) +fsd f25, (#-32, s9) +fsd f25, (#-16, s9) +fsd f25, (#-8, s9) +fsd f25, (#-4, s9) +fsd f25, (#-2, s9) +fsd f25, (#-1, s9) +fsd f25, (#0, s9) +fsd f25, (#1, s9) +fsd f25, (#2, s9) +fsd f25, (#4, s9) +fsd f25, (#8, s9) +fsd f25, (#16, s9) +fsd f25, (#32, s9) +fsd f25, (#64, s9) +fsd f25, (#128, s9) +fsd f25, (#256, s9) +fsd f25, (#512, s9) +fsd f25, (#1024, s9) +fsd f25, (#2047, s9) +fsd f25, (#-2047, t6) +fsd f25, (#-1024, t6) +fsd f25, (#-512, t6) +fsd f25, (#-256, t6) +fsd f25, (#-128, t6) +fsd f25, (#-64, t6) +fsd f25, (#-32, t6) +fsd f25, (#-16, t6) +fsd f25, (#-8, t6) +fsd f25, (#-4, t6) +fsd f25, (#-2, t6) +fsd f25, (#-1, t6) +fsd f25, (#0, t6) +fsd f25, (#1, t6) +fsd f25, (#2, t6) +fsd f25, (#4, t6) +fsd f25, (#8, t6) +fsd f25, (#16, t6) +fsd f25, (#32, t6) +fsd f25, (#64, t6) +fsd f25, (#128, t6) +fsd f25, (#256, t6) +fsd f25, (#512, t6) +fsd f25, (#1024, t6) +fsd f25, (#2047, t6) +fsd f31, (#-2047, zero) +fsd f31, (#-1024, zero) +fsd f31, (#-512, zero) +fsd f31, (#-256, zero) +fsd f31, (#-128, zero) +fsd f31, (#-64, zero) +fsd f31, (#-32, zero) +fsd f31, (#-16, zero) +fsd f31, (#-8, zero) +fsd f31, (#-4, zero) +fsd f31, (#-2, zero) +fsd f31, (#-1, zero) +fsd f31, (#0, zero) +fsd f31, (#1, zero) +fsd f31, (#2, zero) +fsd f31, (#4, zero) +fsd f31, (#8, zero) +fsd f31, (#16, zero) +fsd f31, (#32, zero) +fsd f31, (#64, zero) +fsd f31, (#128, zero) +fsd f31, (#256, zero) +fsd f31, (#512, zero) +fsd f31, (#1024, zero) +fsd f31, (#2047, zero) +fsd f31, (#-2047, ra) +fsd f31, (#-1024, ra) +fsd f31, (#-512, ra) +fsd f31, (#-256, ra) +fsd f31, (#-128, ra) +fsd f31, (#-64, ra) +fsd f31, (#-32, ra) +fsd f31, (#-16, ra) +fsd f31, (#-8, ra) +fsd f31, (#-4, ra) +fsd f31, (#-2, ra) +fsd f31, (#-1, ra) +fsd f31, (#0, ra) +fsd f31, (#1, ra) +fsd f31, (#2, ra) +fsd f31, (#4, ra) +fsd f31, (#8, ra) +fsd f31, (#16, ra) +fsd f31, (#32, ra) +fsd f31, (#64, ra) +fsd f31, (#128, ra) +fsd f31, (#256, ra) +fsd f31, (#512, ra) +fsd f31, (#1024, ra) +fsd f31, (#2047, ra) +fsd f31, (#-2047, t0) +fsd f31, (#-1024, t0) +fsd f31, (#-512, t0) +fsd f31, (#-256, t0) +fsd f31, (#-128, t0) +fsd f31, (#-64, t0) +fsd f31, (#-32, t0) +fsd f31, (#-16, t0) +fsd f31, (#-8, t0) +fsd f31, (#-4, t0) +fsd f31, (#-2, t0) +fsd f31, (#-1, t0) +fsd f31, (#0, t0) +fsd f31, (#1, t0) +fsd f31, (#2, t0) +fsd f31, (#4, t0) +fsd f31, (#8, t0) +fsd f31, (#16, t0) +fsd f31, (#32, t0) +fsd f31, (#64, t0) +fsd f31, (#128, t0) +fsd f31, (#256, t0) +fsd f31, (#512, t0) +fsd f31, (#1024, t0) +fsd f31, (#2047, t0) +fsd f31, (#-2047, a0) +fsd f31, (#-1024, a0) +fsd f31, (#-512, a0) +fsd f31, (#-256, a0) +fsd f31, (#-128, a0) +fsd f31, (#-64, a0) +fsd f31, (#-32, a0) +fsd f31, (#-16, a0) +fsd f31, (#-8, a0) +fsd f31, (#-4, a0) +fsd f31, (#-2, a0) +fsd f31, (#-1, a0) +fsd f31, (#0, a0) +fsd f31, (#1, a0) +fsd f31, (#2, a0) +fsd f31, (#4, a0) +fsd f31, (#8, a0) +fsd f31, (#16, a0) +fsd f31, (#32, a0) +fsd f31, (#64, a0) +fsd f31, (#128, a0) +fsd f31, (#256, a0) +fsd f31, (#512, a0) +fsd f31, (#1024, a0) +fsd f31, (#2047, a0) +fsd f31, (#-2047, a5) +fsd f31, (#-1024, a5) +fsd f31, (#-512, a5) +fsd f31, (#-256, a5) +fsd f31, (#-128, a5) +fsd f31, (#-64, a5) +fsd f31, (#-32, a5) +fsd f31, (#-16, a5) +fsd f31, (#-8, a5) +fsd f31, (#-4, a5) +fsd f31, (#-2, a5) +fsd f31, (#-1, a5) +fsd f31, (#0, a5) +fsd f31, (#1, a5) +fsd f31, (#2, a5) +fsd f31, (#4, a5) +fsd f31, (#8, a5) +fsd f31, (#16, a5) +fsd f31, (#32, a5) +fsd f31, (#64, a5) +fsd f31, (#128, a5) +fsd f31, (#256, a5) +fsd f31, (#512, a5) +fsd f31, (#1024, a5) +fsd f31, (#2047, a5) +fsd f31, (#-2047, s4) +fsd f31, (#-1024, s4) +fsd f31, (#-512, s4) +fsd f31, (#-256, s4) +fsd f31, (#-128, s4) +fsd f31, (#-64, s4) +fsd f31, (#-32, s4) +fsd f31, (#-16, s4) +fsd f31, (#-8, s4) +fsd f31, (#-4, s4) +fsd f31, (#-2, s4) +fsd f31, (#-1, s4) +fsd f31, (#0, s4) +fsd f31, (#1, s4) +fsd f31, (#2, s4) +fsd f31, (#4, s4) +fsd f31, (#8, s4) +fsd f31, (#16, s4) +fsd f31, (#32, s4) +fsd f31, (#64, s4) +fsd f31, (#128, s4) +fsd f31, (#256, s4) +fsd f31, (#512, s4) +fsd f31, (#1024, s4) +fsd f31, (#2047, s4) +fsd f31, (#-2047, s9) +fsd f31, (#-1024, s9) +fsd f31, (#-512, s9) +fsd f31, (#-256, s9) +fsd f31, (#-128, s9) +fsd f31, (#-64, s9) +fsd f31, (#-32, s9) +fsd f31, (#-16, s9) +fsd f31, (#-8, s9) +fsd f31, (#-4, s9) +fsd f31, (#-2, s9) +fsd f31, (#-1, s9) +fsd f31, (#0, s9) +fsd f31, (#1, s9) +fsd f31, (#2, s9) +fsd f31, (#4, s9) +fsd f31, (#8, s9) +fsd f31, (#16, s9) +fsd f31, (#32, s9) +fsd f31, (#64, s9) +fsd f31, (#128, s9) +fsd f31, (#256, s9) +fsd f31, (#512, s9) +fsd f31, (#1024, s9) +fsd f31, (#2047, s9) +fsd f31, (#-2047, t6) +fsd f31, (#-1024, t6) +fsd f31, (#-512, t6) +fsd f31, (#-256, t6) +fsd f31, (#-128, t6) +fsd f31, (#-64, t6) +fsd f31, (#-32, t6) +fsd f31, (#-16, t6) +fsd f31, (#-8, t6) +fsd f31, (#-4, t6) +fsd f31, (#-2, t6) +fsd f31, (#-1, t6) +fsd f31, (#0, t6) +fsd f31, (#1, t6) +fsd f31, (#2, t6) +fsd f31, (#4, t6) +fsd f31, (#8, t6) +fsd f31, (#16, t6) +fsd f31, (#32, t6) +fsd f31, (#64, t6) +fsd f31, (#128, t6) +fsd f31, (#256, t6) +fsd f31, (#512, t6) +fsd f31, (#1024, t6) +fsd f31, (#2047, t6) diff --git a/tests/riscv/d-extension/fsgnj.d.asm b/tests/riscv/d-extension/fsgnj.d.asm new file mode 100644 index 0000000..bd76c48 --- /dev/null +++ b/tests/riscv/d-extension/fsgnj.d.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fsgnj.d f0, f0, f0 +fsgnj.d f0, f0, f1 +fsgnj.d f0, f0, f5 +fsgnj.d f0, f0, f10 +fsgnj.d f0, f0, f15 +fsgnj.d f0, f0, f20 +fsgnj.d f0, f0, f25 +fsgnj.d f0, f0, f31 +fsgnj.d f0, f1, f0 +fsgnj.d f0, f1, f1 +fsgnj.d f0, f1, f5 +fsgnj.d f0, f1, f10 +fsgnj.d f0, f1, f15 +fsgnj.d f0, f1, f20 +fsgnj.d f0, f1, f25 +fsgnj.d f0, f1, f31 +fsgnj.d f0, f5, f0 +fsgnj.d f0, f5, f1 +fsgnj.d f0, f5, f5 +fsgnj.d f0, f5, f10 +fsgnj.d f0, f5, f15 +fsgnj.d f0, f5, f20 +fsgnj.d f0, f5, f25 +fsgnj.d f0, f5, f31 +fsgnj.d f0, f10, f0 +fsgnj.d f0, f10, f1 +fsgnj.d f0, f10, f5 +fsgnj.d f0, f10, f10 +fsgnj.d f0, f10, f15 +fsgnj.d f0, f10, f20 +fsgnj.d f0, f10, f25 +fsgnj.d f0, f10, f31 +fsgnj.d f0, f15, f0 +fsgnj.d f0, f15, f1 +fsgnj.d f0, f15, f5 +fsgnj.d f0, f15, f10 +fsgnj.d f0, f15, f15 +fsgnj.d f0, f15, f20 +fsgnj.d f0, f15, f25 +fsgnj.d f0, f15, f31 +fsgnj.d f0, f20, f0 +fsgnj.d f0, f20, f1 +fsgnj.d f0, f20, f5 +fsgnj.d f0, f20, f10 +fsgnj.d f0, f20, f15 +fsgnj.d f0, f20, f20 +fsgnj.d f0, f20, f25 +fsgnj.d f0, f20, f31 +fsgnj.d f0, f25, f0 +fsgnj.d f0, f25, f1 +fsgnj.d f0, f25, f5 +fsgnj.d f0, f25, f10 +fsgnj.d f0, f25, f15 +fsgnj.d f0, f25, f20 +fsgnj.d f0, f25, f25 +fsgnj.d f0, f25, f31 +fsgnj.d f0, f31, f0 +fsgnj.d f0, f31, f1 +fsgnj.d f0, f31, f5 +fsgnj.d f0, f31, f10 +fsgnj.d f0, f31, f15 +fsgnj.d f0, f31, f20 +fsgnj.d f0, f31, f25 +fsgnj.d f0, f31, f31 +fsgnj.d f1, f0, f0 +fsgnj.d f1, f0, f1 +fsgnj.d f1, f0, f5 +fsgnj.d f1, f0, f10 +fsgnj.d f1, f0, f15 +fsgnj.d f1, f0, f20 +fsgnj.d f1, f0, f25 +fsgnj.d f1, f0, f31 +fsgnj.d f1, f1, f0 +fsgnj.d f1, f1, f1 +fsgnj.d f1, f1, f5 +fsgnj.d f1, f1, f10 +fsgnj.d f1, f1, f15 +fsgnj.d f1, f1, f20 +fsgnj.d f1, f1, f25 +fsgnj.d f1, f1, f31 +fsgnj.d f1, f5, f0 +fsgnj.d f1, f5, f1 +fsgnj.d f1, f5, f5 +fsgnj.d f1, f5, f10 +fsgnj.d f1, f5, f15 +fsgnj.d f1, f5, f20 +fsgnj.d f1, f5, f25 +fsgnj.d f1, f5, f31 +fsgnj.d f1, f10, f0 +fsgnj.d f1, f10, f1 +fsgnj.d f1, f10, f5 +fsgnj.d f1, f10, f10 +fsgnj.d f1, f10, f15 +fsgnj.d f1, f10, f20 +fsgnj.d f1, f10, f25 +fsgnj.d f1, f10, f31 +fsgnj.d f1, f15, f0 +fsgnj.d f1, f15, f1 +fsgnj.d f1, f15, f5 +fsgnj.d f1, f15, f10 +fsgnj.d f1, f15, f15 +fsgnj.d f1, f15, f20 +fsgnj.d f1, f15, f25 +fsgnj.d f1, f15, f31 +fsgnj.d f1, f20, f0 +fsgnj.d f1, f20, f1 +fsgnj.d f1, f20, f5 +fsgnj.d f1, f20, f10 +fsgnj.d f1, f20, f15 +fsgnj.d f1, f20, f20 +fsgnj.d f1, f20, f25 +fsgnj.d f1, f20, f31 +fsgnj.d f1, f25, f0 +fsgnj.d f1, f25, f1 +fsgnj.d f1, f25, f5 +fsgnj.d f1, f25, f10 +fsgnj.d f1, f25, f15 +fsgnj.d f1, f25, f20 +fsgnj.d f1, f25, f25 +fsgnj.d f1, f25, f31 +fsgnj.d f1, f31, f0 +fsgnj.d f1, f31, f1 +fsgnj.d f1, f31, f5 +fsgnj.d f1, f31, f10 +fsgnj.d f1, f31, f15 +fsgnj.d f1, f31, f20 +fsgnj.d f1, f31, f25 +fsgnj.d f1, f31, f31 +fsgnj.d f5, f0, f0 +fsgnj.d f5, f0, f1 +fsgnj.d f5, f0, f5 +fsgnj.d f5, f0, f10 +fsgnj.d f5, f0, f15 +fsgnj.d f5, f0, f20 +fsgnj.d f5, f0, f25 +fsgnj.d f5, f0, f31 +fsgnj.d f5, f1, f0 +fsgnj.d f5, f1, f1 +fsgnj.d f5, f1, f5 +fsgnj.d f5, f1, f10 +fsgnj.d f5, f1, f15 +fsgnj.d f5, f1, f20 +fsgnj.d f5, f1, f25 +fsgnj.d f5, f1, f31 +fsgnj.d f5, f5, f0 +fsgnj.d f5, f5, f1 +fsgnj.d f5, f5, f5 +fsgnj.d f5, f5, f10 +fsgnj.d f5, f5, f15 +fsgnj.d f5, f5, f20 +fsgnj.d f5, f5, f25 +fsgnj.d f5, f5, f31 +fsgnj.d f5, f10, f0 +fsgnj.d f5, f10, f1 +fsgnj.d f5, f10, f5 +fsgnj.d f5, f10, f10 +fsgnj.d f5, f10, f15 +fsgnj.d f5, f10, f20 +fsgnj.d f5, f10, f25 +fsgnj.d f5, f10, f31 +fsgnj.d f5, f15, f0 +fsgnj.d f5, f15, f1 +fsgnj.d f5, f15, f5 +fsgnj.d f5, f15, f10 +fsgnj.d f5, f15, f15 +fsgnj.d f5, f15, f20 +fsgnj.d f5, f15, f25 +fsgnj.d f5, f15, f31 +fsgnj.d f5, f20, f0 +fsgnj.d f5, f20, f1 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z0e`?B@CW<>f50E`2mBR(#b5DP{1t!2U-4J`6@SHF@mKs6f5l(%*So`Uv+vEmH~Ze~ zd$aG&zBl{c?7QikzUiC3>6^ak+qt*@X8+CpoBcQYZ}#8pzuEt0|C{}9_P^QxX8)W0 zZ}z|0f3yE)|IPlJ{Wtq>_TTKk+5cw$oBeP0zuEt0|C{}9_P^PGv;SuQ&HkJHH~Vk) z-|WBHf3yE)|IPlJ{Wtq>_TTKk@gMn({6>Bwzmea_Z{#=f+x1=F^k&VT1W@*nw+{73#H|B?U5f8@XO-}&$Scm6y7o&U~%=Rfiv`H%cZ{v-d9 z|Hyyjzw_Vu@BDZEJO7>k&VT2>^WXXJ{CEC4|DFHNf9F5(oA^!qCVmsYiQmL;;&-Lga5&Q<~Q@3 z`OW-helx$B-^}mSPyN(S{nStW)X#Iz|Kxx2Klz{hPyQ$WlmE!B_AVdC literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fsqrt.d.disasm b/tests/riscv/d-extension/fsqrt.d.disasm new file mode 100644 index 0000000..9082170 --- /dev/null +++ b/tests/riscv/d-extension/fsqrt.d.disasm @@ -0,0 +1,45 @@ +fsqrt.d f0, f0 +fsqrt.d f1, f1 +fsqrt.d f5, f5 +fsqrt.d f10, f10 +fsqrt.d f15, f15 +fsqrt.d f20, f20 +fsqrt.d f25, f25 +fsqrt.d f31, f31 +fsqrt.d f1, f0 +fsqrt.d f5, f0 +fsqrt.d f10, f0 +fsqrt.d f15, f0 +fsqrt.d f20, f0 +fsqrt.d f25, f0 +fsqrt.d f31, f0 +fsqrt.d f0, f1 +fsqrt.d f5, f1 +fsqrt.d f10, f1 +fsqrt.d f15, f1 +fsqrt.d f20, f1 +fsqrt.d f25, f1 +fsqrt.d f31, f1 +fsqrt.d f0, f10 +fsqrt.d f1, f10 +fsqrt.d f5, f10 +fsqrt.d f15, f10 +fsqrt.d f20, f10 +fsqrt.d f25, f10 +fsqrt.d f31, f10 +fsqrt.d f0, f31 +fsqrt.d f1, f31 +fsqrt.d f5, f31 +fsqrt.d f10, f31 +fsqrt.d f15, f31 +fsqrt.d f20, f31 +fsqrt.d f25, f31 +fsqrt.d f0, f1 +fsqrt.d f1, f2 +fsqrt.d f2, f3 +fsqrt.d f30, f31 +fsqrt.d f2, f29 +fsqrt.d f3, f28 +fsqrt.d f4, f27 +fsqrt.d f12, f19 +fsqrt.d f16, f8 diff --git a/tests/riscv/d-extension/fsqrt_d.asm b/tests/riscv/d-extension/fsqrt_d.asm new file mode 100644 index 0000000..35221b3 --- /dev/null +++ b/tests/riscv/d-extension/fsqrt_d.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fsqrt.d f0, f1 + diff --git a/tests/riscv/d-extension/fsqrt_d.bin b/tests/riscv/d-extension/fsqrt_d.bin new file mode 100644 index 0000000000000000000000000000000000000000..0a66864b540b498b46ca908d11e18145f735c00b GIT binary patch literal 4 LcmWG;V2A<$11bS7 literal 0 HcmV?d00001 diff --git a/tests/riscv/d-extension/fsqrt_d.disasm b/tests/riscv/d-extension/fsqrt_d.disasm new file mode 100644 index 0000000..93d4cbc --- /dev/null +++ b/tests/riscv/d-extension/fsqrt_d.disasm @@ -0,0 +1 @@ +fsqrt.d f0, f1 diff --git a/tests/riscv/d-extension/fsub.d.asm b/tests/riscv/d-extension/fsub.d.asm new file mode 100644 index 0000000..5658e2f --- /dev/null +++ b/tests/riscv/d-extension/fsub.d.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fsub.d f0, f0, f0 +fsub.d f0, f0, f1 +fsub.d f0, f0, f5 +fsub.d f0, f0, f10 +fsub.d f0, f0, f15 +fsub.d f0, f0, f20 +fsub.d f0, f0, f25 +fsub.d f0, f0, f31 +fsub.d f0, f1, f0 +fsub.d f0, f1, f1 +fsub.d f0, f1, f5 +fsub.d f0, f1, f10 +fsub.d f0, f1, f15 +fsub.d f0, f1, f20 +fsub.d f0, f1, f25 +fsub.d f0, f1, f31 +fsub.d f0, f5, f0 +fsub.d f0, f5, f1 +fsub.d f0, f5, f5 +fsub.d f0, f5, f10 +fsub.d f0, f5, f15 +fsub.d f0, f5, f20 +fsub.d f0, f5, f25 +fsub.d f0, f5, f31 +fsub.d f0, f10, f0 +fsub.d f0, f10, f1 +fsub.d f0, f10, f5 +fsub.d f0, f10, f10 +fsub.d f0, f10, f15 +fsub.d f0, f10, f20 +fsub.d f0, f10, f25 +fsub.d f0, f10, f31 +fsub.d f0, f15, f0 +fsub.d f0, f15, f1 +fsub.d f0, f15, f5 +fsub.d f0, f15, f10 +fsub.d f0, f15, f15 +fsub.d f0, f15, f20 +fsub.d f0, f15, f25 +fsub.d f0, f15, f31 +fsub.d f0, f20, f0 +fsub.d f0, f20, f1 +fsub.d f0, f20, f5 +fsub.d f0, f20, f10 +fsub.d f0, f20, f15 +fsub.d f0, f20, f20 +fsub.d f0, f20, f25 +fsub.d f0, f20, f31 +fsub.d f0, f25, f0 +fsub.d f0, f25, f1 +fsub.d f0, f25, f5 +fsub.d f0, f25, f10 +fsub.d f0, f25, f15 +fsub.d f0, f25, f20 +fsub.d f0, f25, f25 +fsub.d f0, f25, f31 +fsub.d f0, f31, f0 +fsub.d f0, f31, f1 +fsub.d f0, f31, f5 +fsub.d f0, f31, f10 +fsub.d f0, f31, f15 +fsub.d f0, f31, f20 +fsub.d f0, f31, f25 +fsub.d f0, f31, f31 +fsub.d f1, f0, f0 +fsub.d f1, f0, f1 +fsub.d f1, f0, f5 +fsub.d f1, f0, f10 +fsub.d f1, f0, f15 +fsub.d f1, f0, f20 +fsub.d f1, f0, f25 +fsub.d f1, f0, f31 +fsub.d f1, f1, f0 +fsub.d f1, f1, f1 +fsub.d f1, f1, f5 +fsub.d f1, f1, f10 +fsub.d f1, f1, f15 +fsub.d f1, f1, f20 +fsub.d f1, f1, f25 +fsub.d f1, f1, f31 +fsub.d f1, f5, f0 +fsub.d f1, f5, f1 +fsub.d f1, f5, f5 +fsub.d f1, f5, f10 +fsub.d f1, f5, f15 +fsub.d f1, f5, f20 +fsub.d f1, f5, f25 +fsub.d f1, f5, f31 +fsub.d f1, f10, f0 +fsub.d f1, f10, f1 +fsub.d f1, f10, f5 +fsub.d f1, f10, f10 +fsub.d f1, f10, f15 +fsub.d f1, f10, f20 +fsub.d f1, f10, f25 +fsub.d f1, f10, f31 +fsub.d f1, f15, f0 +fsub.d f1, f15, f1 +fsub.d f1, f15, f5 +fsub.d f1, f15, f10 +fsub.d f1, f15, f15 +fsub.d f1, f15, f20 +fsub.d f1, f15, f25 +fsub.d f1, f15, f31 +fsub.d f1, f20, f0 +fsub.d f1, f20, f1 +fsub.d f1, f20, f5 +fsub.d f1, f20, f10 +fsub.d f1, f20, f15 +fsub.d f1, f20, f20 +fsub.d f1, f20, f25 +fsub.d f1, f20, f31 +fsub.d f1, f25, f0 +fsub.d f1, f25, f1 +fsub.d f1, f25, f5 +fsub.d f1, f25, f10 +fsub.d f1, f25, f15 +fsub.d f1, f25, f20 +fsub.d f1, f25, f25 +fsub.d f1, f25, f31 +fsub.d f1, f31, f0 +fsub.d f1, f31, f1 +fsub.d f1, f31, f5 +fsub.d f1, f31, f10 +fsub.d f1, f31, f15 +fsub.d f1, f31, f20 +fsub.d f1, f31, f25 +fsub.d f1, f31, f31 +fsub.d f5, f0, f0 +fsub.d f5, f0, f1 +fsub.d f5, f0, f5 +fsub.d f5, f0, f10 +fsub.d f5, f0, f15 +fsub.d f5, f0, f20 +fsub.d f5, f0, f25 +fsub.d f5, f0, f31 +fsub.d f5, f1, f0 +fsub.d f5, f1, f1 +fsub.d f5, f1, f5 +fsub.d f5, f1, f10 +fsub.d f5, f1, f15 +fsub.d f5, f1, f20 +fsub.d f5, f1, f25 +fsub.d f5, f1, f31 +fsub.d f5, f5, f0 +fsub.d f5, f5, f1 +fsub.d f5, f5, f5 +fsub.d f5, f5, f10 +fsub.d f5, f5, f15 +fsub.d f5, f5, f20 +fsub.d f5, f5, f25 +fsub.d f5, f5, f31 +fsub.d f5, f10, f0 +fsub.d f5, f10, f1 +fsub.d f5, f10, f5 +fsub.d f5, f10, f10 +fsub.d f5, f10, f15 +fsub.d f5, f10, f20 +fsub.d f5, f10, f25 +fsub.d f5, f10, f31 +fsub.d f5, f15, f0 +fsub.d f5, f15, f1 +fsub.d f5, f15, f5 +fsub.d f5, f15, f10 +fsub.d f5, f15, f15 +fsub.d f5, f15, f20 +fsub.d f5, f15, f25 +fsub.d f5, f15, f31 +fsub.d f5, f20, f0 +fsub.d f5, f20, f1 +fsub.d f5, f20, f5 +fsub.d f5, f20, f10 +fsub.d f5, f20, f15 +fsub.d f5, f20, f20 +fsub.d f5, f20, f25 +fsub.d f5, f20, f31 +fsub.d f5, f25, f0 +fsub.d f5, f25, f1 +fsub.d f5, f25, f5 +fsub.d f5, f25, f10 +fsub.d f5, f25, f15 +fsub.d f5, f25, f20 +fsub.d f5, f25, f25 +fsub.d f5, f25, f31 +fsub.d f5, f31, f0 +fsub.d f5, f31, f1 +fsub.d f5, f31, f5 +fsub.d f5, f31, f10 +fsub.d f5, f31, f15 +fsub.d f5, f31, f20 +fsub.d f5, f31, f25 +fsub.d f5, f31, f31 +fsub.d f10, f0, f0 +fsub.d f10, f0, f1 +fsub.d f10, f0, f5 +fsub.d f10, f0, f10 +fsub.d f10, f0, f15 +fsub.d f10, f0, f20 +fsub.d f10, f0, f25 +fsub.d f10, f0, f31 +fsub.d f10, f1, f0 +fsub.d f10, f1, f1 +fsub.d f10, f1, f5 +fsub.d f10, f1, f10 +fsub.d f10, f1, f15 +fsub.d f10, f1, f20 +fsub.d f10, f1, f25 +fsub.d f10, f1, f31 +fsub.d f10, f5, f0 +fsub.d f10, f5, f1 +fsub.d f10, f5, f5 +fsub.d f10, f5, f10 +fsub.d f10, f5, f15 +fsub.d f10, f5, f20 +fsub.d f10, f5, f25 +fsub.d f10, f5, f31 +fsub.d f10, f10, f0 +fsub.d f10, f10, f1 +fsub.d f10, f10, f5 +fsub.d f10, f10, f10 +fsub.d f10, f10, f15 +fsub.d f10, f10, f20 +fsub.d f10, f10, f25 +fsub.d f10, f10, f31 +fsub.d f10, f15, f0 +fsub.d f10, f15, f1 +fsub.d f10, f15, f5 +fsub.d f10, f15, f10 +fsub.d f10, f15, f15 +fsub.d f10, f15, f20 +fsub.d f10, f15, f25 +fsub.d f10, f15, f31 +fsub.d f10, f20, f0 +fsub.d f10, f20, f1 +fsub.d f10, f20, f5 +fsub.d f10, f20, f10 +fsub.d f10, f20, f15 +fsub.d f10, f20, f20 +fsub.d f10, f20, f25 +fsub.d f10, f20, f31 +fsub.d f10, f25, f0 +fsub.d f10, f25, f1 +fsub.d f10, f25, f5 +fsub.d f10, f25, f10 +fsub.d f10, f25, f15 +fsub.d f10, f25, f20 +fsub.d f10, f25, f25 +fsub.d f10, f25, f31 +fsub.d f10, f31, f0 +fsub.d f10, f31, f1 +fsub.d f10, f31, f5 +fsub.d f10, f31, f10 +fsub.d f10, f31, f15 +fsub.d f10, f31, f20 +fsub.d f10, f31, f25 +fsub.d f10, f31, f31 +fsub.d f15, f0, f0 +fsub.d f15, f0, f1 +fsub.d f15, f0, f5 +fsub.d f15, f0, f10 +fsub.d f15, f0, f15 +fsub.d f15, f0, f20 +fsub.d f15, f0, f25 +fsub.d f15, f0, f31 +fsub.d f15, f1, f0 +fsub.d f15, f1, f1 +fsub.d f15, f1, f5 +fsub.d f15, f1, f10 +fsub.d f15, f1, f15 +fsub.d f15, f1, f20 +fsub.d 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z_+R`l{uloXf5lhvReTj+#aHoFd==l;Z~fM9{nl^&*6&k~f8*cyH~x)(lna}*m lmO1|93xD#3FZ{*UIsW1+fAN*C`mMD&{nnd)>rHRV_yb%ld+`7O literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fclass.s.disasm b/tests/riscv/f-extension/fclass.s.disasm new file mode 100644 index 0000000..a08a85c --- /dev/null +++ b/tests/riscv/f-extension/fclass.s.disasm @@ -0,0 +1,64 @@ +fclass.s zero, f0 +fclass.s zero, f1 +fclass.s zero, f5 +fclass.s zero, f10 +fclass.s zero, f15 +fclass.s zero, f20 +fclass.s zero, f25 +fclass.s zero, f31 +fclass.s ra, f0 +fclass.s ra, f1 +fclass.s ra, f5 +fclass.s ra, f10 +fclass.s ra, f15 +fclass.s ra, f20 +fclass.s ra, f25 +fclass.s ra, f31 +fclass.s t0, f0 +fclass.s t0, f1 +fclass.s t0, f5 +fclass.s t0, f10 +fclass.s t0, f15 +fclass.s t0, f20 +fclass.s t0, f25 +fclass.s t0, f31 +fclass.s a0, f0 +fclass.s a0, f1 +fclass.s a0, f5 +fclass.s a0, f10 +fclass.s a0, f15 +fclass.s a0, f20 +fclass.s a0, f25 +fclass.s a0, f31 +fclass.s a5, f0 +fclass.s a5, f1 +fclass.s a5, f5 +fclass.s a5, f10 +fclass.s a5, f15 +fclass.s a5, f20 +fclass.s a5, f25 +fclass.s a5, f31 +fclass.s s4, f0 +fclass.s s4, f1 +fclass.s s4, f5 +fclass.s s4, f10 +fclass.s s4, f15 +fclass.s s4, f20 +fclass.s s4, f25 +fclass.s s4, f31 +fclass.s s9, f0 +fclass.s s9, f1 +fclass.s s9, f5 +fclass.s s9, f10 +fclass.s s9, f15 +fclass.s s9, f20 +fclass.s s9, f25 +fclass.s s9, f31 +fclass.s t6, f0 +fclass.s t6, f1 +fclass.s t6, f5 +fclass.s t6, f10 +fclass.s t6, f15 +fclass.s t6, f20 +fclass.s t6, f25 +fclass.s t6, f31 diff --git a/tests/riscv/f-extension/fclass_s.asm b/tests/riscv/f-extension/fclass_s.asm new file mode 100644 index 0000000..e582df7 --- /dev/null +++ b/tests/riscv/f-extension/fclass_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fclass.s a0, f1 + diff --git a/tests/riscv/f-extension/fclass_s.bin b/tests/riscv/f-extension/fclass_s.bin new file mode 100644 index 0000000000000000000000000000000000000000..6490dcd91129a791ff3bc83d93d1e70e9533f9bf GIT binary patch literal 4 LcmWHZ%J2XH1MdOJ literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fclass_s.disasm b/tests/riscv/f-extension/fclass_s.disasm new file mode 100644 index 0000000..966e05d --- /dev/null +++ b/tests/riscv/f-extension/fclass_s.disasm @@ -0,0 +1 @@ +fclass.s a0, f1 diff --git a/tests/riscv/f-extension/fcvt.s.w.asm b/tests/riscv/f-extension/fcvt.s.w.asm new file mode 100644 index 0000000..73c204e --- /dev/null +++ b/tests/riscv/f-extension/fcvt.s.w.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +fcvt.s.w f0, zero +fcvt.s.w f0, ra +fcvt.s.w f0, t0 +fcvt.s.w f0, a0 +fcvt.s.w f0, a5 +fcvt.s.w f0, s4 +fcvt.s.w f0, s9 +fcvt.s.w f0, t6 +fcvt.s.w f1, zero +fcvt.s.w f1, ra +fcvt.s.w f1, t0 +fcvt.s.w f1, a0 +fcvt.s.w f1, a5 +fcvt.s.w f1, s4 +fcvt.s.w f1, s9 +fcvt.s.w f1, t6 +fcvt.s.w f5, zero +fcvt.s.w f5, ra +fcvt.s.w f5, t0 +fcvt.s.w f5, a0 +fcvt.s.w f5, a5 +fcvt.s.w f5, s4 +fcvt.s.w f5, s9 +fcvt.s.w f5, t6 +fcvt.s.w f10, zero +fcvt.s.w f10, ra +fcvt.s.w f10, t0 +fcvt.s.w f10, a0 +fcvt.s.w f10, a5 +fcvt.s.w f10, s4 +fcvt.s.w f10, s9 +fcvt.s.w f10, t6 +fcvt.s.w f15, zero +fcvt.s.w f15, ra +fcvt.s.w f15, t0 +fcvt.s.w f15, a0 +fcvt.s.w f15, a5 +fcvt.s.w f15, s4 +fcvt.s.w f15, s9 +fcvt.s.w f15, t6 +fcvt.s.w f20, zero +fcvt.s.w f20, ra +fcvt.s.w f20, t0 +fcvt.s.w f20, a0 +fcvt.s.w f20, a5 +fcvt.s.w f20, s4 +fcvt.s.w f20, s9 +fcvt.s.w f20, t6 +fcvt.s.w f25, zero +fcvt.s.w f25, ra +fcvt.s.w f25, t0 +fcvt.s.w f25, a0 +fcvt.s.w f25, a5 +fcvt.s.w f25, s4 +fcvt.s.w f25, s9 +fcvt.s.w f25, t6 +fcvt.s.w f31, zero +fcvt.s.w f31, ra +fcvt.s.w f31, t0 +fcvt.s.w f31, a0 +fcvt.s.w f31, a5 +fcvt.s.w f31, s4 +fcvt.s.w f31, s9 +fcvt.s.w f31, t6 + diff --git a/tests/riscv/f-extension/fcvt.s.w.bin b/tests/riscv/f-extension/fcvt.s.w.bin new file mode 100644 index 0000000000000000000000000000000000000000..9caee5093392d2fcc75706417a9a34c0dca8db1c GIT binary patch literal 256 zcmWm6Q3gdJ6o%0wa!53|GodRIiKZ4!=&l}q`{A?p_dNUi-G%)<(S6J?e4kVfQ=D`M>+0{NMdg{wMxm^BjNhnLqfrKD)rnja40bmYy@c;k- literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fcvt.s.wu.disasm b/tests/riscv/f-extension/fcvt.s.wu.disasm new file mode 100644 index 0000000..cde316f --- /dev/null +++ b/tests/riscv/f-extension/fcvt.s.wu.disasm @@ -0,0 +1,64 @@ +fcvt.s.wu f0, zero +fcvt.s.wu f0, ra +fcvt.s.wu f0, t0 +fcvt.s.wu f0, a0 +fcvt.s.wu f0, a5 +fcvt.s.wu f0, s4 +fcvt.s.wu f0, s9 +fcvt.s.wu f0, t6 +fcvt.s.wu f1, zero +fcvt.s.wu f1, ra +fcvt.s.wu f1, t0 +fcvt.s.wu f1, a0 +fcvt.s.wu f1, a5 +fcvt.s.wu f1, s4 +fcvt.s.wu f1, s9 +fcvt.s.wu f1, t6 +fcvt.s.wu f5, zero +fcvt.s.wu f5, ra +fcvt.s.wu f5, t0 +fcvt.s.wu f5, a0 +fcvt.s.wu f5, a5 +fcvt.s.wu f5, s4 +fcvt.s.wu f5, s9 +fcvt.s.wu f5, t6 +fcvt.s.wu f10, zero +fcvt.s.wu f10, ra +fcvt.s.wu f10, t0 +fcvt.s.wu f10, a0 +fcvt.s.wu f10, a5 +fcvt.s.wu f10, s4 +fcvt.s.wu f10, s9 +fcvt.s.wu f10, t6 +fcvt.s.wu f15, zero +fcvt.s.wu f15, ra +fcvt.s.wu f15, t0 +fcvt.s.wu f15, a0 +fcvt.s.wu f15, a5 +fcvt.s.wu f15, s4 +fcvt.s.wu f15, s9 +fcvt.s.wu f15, t6 +fcvt.s.wu f20, zero +fcvt.s.wu f20, ra +fcvt.s.wu f20, t0 +fcvt.s.wu f20, a0 +fcvt.s.wu f20, a5 +fcvt.s.wu f20, s4 +fcvt.s.wu f20, s9 +fcvt.s.wu f20, t6 +fcvt.s.wu f25, zero +fcvt.s.wu f25, ra +fcvt.s.wu f25, t0 +fcvt.s.wu f25, a0 +fcvt.s.wu f25, a5 +fcvt.s.wu f25, s4 +fcvt.s.wu f25, s9 +fcvt.s.wu f25, t6 +fcvt.s.wu f31, zero +fcvt.s.wu f31, ra +fcvt.s.wu f31, t0 +fcvt.s.wu f31, a0 +fcvt.s.wu f31, a5 +fcvt.s.wu f31, s4 +fcvt.s.wu f31, s9 +fcvt.s.wu f31, t6 diff --git a/tests/riscv/f-extension/fcvt.w.s.asm b/tests/riscv/f-extension/fcvt.w.s.asm new file mode 100644 index 0000000..a4bedfb --- /dev/null +++ b/tests/riscv/f-extension/fcvt.w.s.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +fcvt.w.s zero, f0 +fcvt.w.s zero, f1 +fcvt.w.s zero, f5 +fcvt.w.s zero, f10 +fcvt.w.s zero, f15 +fcvt.w.s zero, f20 +fcvt.w.s zero, f25 +fcvt.w.s zero, f31 +fcvt.w.s ra, f0 +fcvt.w.s ra, f1 +fcvt.w.s ra, f5 +fcvt.w.s ra, f10 +fcvt.w.s ra, f15 +fcvt.w.s ra, f20 +fcvt.w.s ra, f25 +fcvt.w.s ra, f31 +fcvt.w.s t0, f0 +fcvt.w.s t0, f1 +fcvt.w.s t0, f5 +fcvt.w.s t0, f10 +fcvt.w.s t0, f15 +fcvt.w.s t0, f20 +fcvt.w.s t0, f25 +fcvt.w.s t0, f31 +fcvt.w.s a0, f0 +fcvt.w.s a0, f1 +fcvt.w.s a0, f5 +fcvt.w.s a0, f10 +fcvt.w.s a0, f15 +fcvt.w.s a0, f20 +fcvt.w.s a0, f25 +fcvt.w.s a0, f31 +fcvt.w.s a5, f0 +fcvt.w.s a5, f1 +fcvt.w.s a5, f5 +fcvt.w.s a5, f10 +fcvt.w.s a5, f15 +fcvt.w.s a5, f20 +fcvt.w.s a5, f25 +fcvt.w.s a5, f31 +fcvt.w.s s4, f0 +fcvt.w.s s4, f1 +fcvt.w.s s4, f5 +fcvt.w.s s4, f10 +fcvt.w.s s4, f15 +fcvt.w.s s4, f20 +fcvt.w.s s4, f25 +fcvt.w.s s4, f31 +fcvt.w.s s9, f0 +fcvt.w.s s9, f1 +fcvt.w.s s9, f5 +fcvt.w.s s9, f10 +fcvt.w.s s9, f15 +fcvt.w.s s9, f20 +fcvt.w.s s9, f25 +fcvt.w.s s9, f31 +fcvt.w.s t6, f0 +fcvt.w.s t6, f1 +fcvt.w.s t6, f5 +fcvt.w.s t6, f10 +fcvt.w.s t6, f15 +fcvt.w.s t6, f20 +fcvt.w.s t6, f25 +fcvt.w.s t6, f31 + diff --git a/tests/riscv/f-extension/fcvt.w.s.bin b/tests/riscv/f-extension/fcvt.w.s.bin new file mode 100644 index 0000000000000000000000000000000000000000..f18c862fd294e226cc700f6b2e6da777c3a6ea8a GIT binary patch literal 256 zcmWm6Q3gdJ6o%0wa!53|GodRIiKf&Xn$TT6{Px3V?eBT^_qz-Gd!qZg$<0>w(T{%g zqaXd~M?bd*t={QDuX@m{Ud#TX-|f!-=zsG+`rrI-{LA(`{^dLW@}2K|V#ghy_`xTB c@Pp6nyyG)J`OHs#>P1_3deN6&^rf$||6kH?@c;k- literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fcvt.w.s.disasm b/tests/riscv/f-extension/fcvt.w.s.disasm new file mode 100644 index 0000000..ffda6de --- /dev/null +++ b/tests/riscv/f-extension/fcvt.w.s.disasm @@ -0,0 +1,64 @@ +fcvt.w.s zero, f0 +fcvt.w.s zero, f1 +fcvt.w.s zero, f5 +fcvt.w.s zero, f10 +fcvt.w.s zero, f15 +fcvt.w.s zero, f20 +fcvt.w.s zero, f25 +fcvt.w.s zero, f31 +fcvt.w.s ra, f0 +fcvt.w.s ra, f1 +fcvt.w.s ra, f5 +fcvt.w.s ra, f10 +fcvt.w.s ra, f15 +fcvt.w.s ra, f20 +fcvt.w.s ra, f25 +fcvt.w.s ra, f31 +fcvt.w.s t0, f0 +fcvt.w.s t0, f1 +fcvt.w.s t0, f5 +fcvt.w.s t0, f10 +fcvt.w.s t0, f15 +fcvt.w.s t0, f20 +fcvt.w.s t0, f25 +fcvt.w.s t0, f31 +fcvt.w.s a0, f0 +fcvt.w.s a0, f1 +fcvt.w.s a0, f5 +fcvt.w.s a0, f10 +fcvt.w.s a0, f15 +fcvt.w.s a0, f20 +fcvt.w.s a0, f25 +fcvt.w.s a0, f31 +fcvt.w.s a5, f0 +fcvt.w.s a5, f1 +fcvt.w.s a5, f5 +fcvt.w.s a5, f10 +fcvt.w.s a5, f15 +fcvt.w.s a5, f20 +fcvt.w.s a5, f25 +fcvt.w.s a5, f31 +fcvt.w.s s4, f0 +fcvt.w.s s4, f1 +fcvt.w.s s4, f5 +fcvt.w.s s4, f10 +fcvt.w.s s4, f15 +fcvt.w.s s4, f20 +fcvt.w.s s4, f25 +fcvt.w.s s4, f31 +fcvt.w.s s9, f0 +fcvt.w.s s9, f1 +fcvt.w.s s9, f5 +fcvt.w.s s9, f10 +fcvt.w.s s9, f15 +fcvt.w.s s9, f20 +fcvt.w.s s9, f25 +fcvt.w.s s9, f31 +fcvt.w.s t6, f0 +fcvt.w.s t6, f1 +fcvt.w.s t6, f5 +fcvt.w.s t6, f10 +fcvt.w.s t6, f15 +fcvt.w.s t6, f20 +fcvt.w.s t6, f25 +fcvt.w.s t6, f31 diff --git a/tests/riscv/f-extension/fcvt.wu.s.asm b/tests/riscv/f-extension/fcvt.wu.s.asm new file mode 100644 index 0000000..ad1eea6 --- /dev/null +++ b/tests/riscv/f-extension/fcvt.wu.s.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +fcvt.wu.s zero, f0 +fcvt.wu.s zero, f1 +fcvt.wu.s zero, f5 +fcvt.wu.s zero, f10 +fcvt.wu.s zero, f15 +fcvt.wu.s zero, f20 +fcvt.wu.s zero, f25 +fcvt.wu.s zero, f31 +fcvt.wu.s ra, f0 +fcvt.wu.s ra, f1 +fcvt.wu.s ra, f5 +fcvt.wu.s ra, f10 +fcvt.wu.s ra, f15 +fcvt.wu.s ra, f20 +fcvt.wu.s ra, f25 +fcvt.wu.s ra, f31 +fcvt.wu.s t0, f0 +fcvt.wu.s t0, f1 +fcvt.wu.s t0, f5 +fcvt.wu.s t0, f10 +fcvt.wu.s t0, f15 +fcvt.wu.s t0, f20 +fcvt.wu.s t0, f25 +fcvt.wu.s t0, f31 +fcvt.wu.s a0, f0 +fcvt.wu.s a0, f1 +fcvt.wu.s a0, f5 +fcvt.wu.s a0, f10 +fcvt.wu.s a0, f15 +fcvt.wu.s a0, f20 +fcvt.wu.s a0, f25 +fcvt.wu.s a0, f31 +fcvt.wu.s a5, f0 +fcvt.wu.s a5, f1 +fcvt.wu.s a5, f5 +fcvt.wu.s a5, f10 +fcvt.wu.s a5, f15 +fcvt.wu.s a5, f20 +fcvt.wu.s a5, f25 +fcvt.wu.s a5, f31 +fcvt.wu.s s4, f0 +fcvt.wu.s s4, f1 +fcvt.wu.s s4, f5 +fcvt.wu.s s4, f10 +fcvt.wu.s s4, f15 +fcvt.wu.s s4, f20 +fcvt.wu.s s4, f25 +fcvt.wu.s s4, f31 +fcvt.wu.s s9, f0 +fcvt.wu.s s9, f1 +fcvt.wu.s s9, f5 +fcvt.wu.s s9, f10 +fcvt.wu.s s9, f15 +fcvt.wu.s s9, f20 +fcvt.wu.s s9, f25 +fcvt.wu.s s9, f31 +fcvt.wu.s t6, f0 +fcvt.wu.s t6, f1 +fcvt.wu.s t6, f5 +fcvt.wu.s t6, f10 +fcvt.wu.s t6, f15 +fcvt.wu.s t6, f20 +fcvt.wu.s t6, f25 +fcvt.wu.s t6, f31 + diff --git a/tests/riscv/f-extension/fcvt.wu.s.bin b/tests/riscv/f-extension/fcvt.wu.s.bin new file mode 100644 index 0000000000000000000000000000000000000000..0d4b07eb834a1715c1f968243cad7c1e115d7edd GIT binary patch literal 256 zcmWm6Q3eAs6o%0%RjSMw#xRCiR5n&2LWFE3d&q`*^6|uSmZ};PV zZRtZF`p}0y^q~)Z%)V)HPT%yXZ+g_@(!=g|n)846Kl#7=pZrh!!R9&s;4^>lna}*m lmO1|93xD#3FZ{*UIsW1+fAN*C`mMD&{nnd)>rHP<{{v(2bMXKG literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fcvt.wu.s.disasm b/tests/riscv/f-extension/fcvt.wu.s.disasm new file mode 100644 index 0000000..e3988fa --- /dev/null +++ b/tests/riscv/f-extension/fcvt.wu.s.disasm @@ -0,0 +1,64 @@ +fcvt.wu.s zero, f0 +fcvt.wu.s zero, f1 +fcvt.wu.s zero, f5 +fcvt.wu.s zero, f10 +fcvt.wu.s zero, f15 +fcvt.wu.s zero, f20 +fcvt.wu.s zero, f25 +fcvt.wu.s zero, f31 +fcvt.wu.s ra, f0 +fcvt.wu.s ra, f1 +fcvt.wu.s ra, f5 +fcvt.wu.s ra, f10 +fcvt.wu.s ra, f15 +fcvt.wu.s ra, f20 +fcvt.wu.s ra, f25 +fcvt.wu.s ra, f31 +fcvt.wu.s t0, f0 +fcvt.wu.s t0, f1 +fcvt.wu.s t0, f5 +fcvt.wu.s t0, f10 +fcvt.wu.s t0, f15 +fcvt.wu.s t0, f20 +fcvt.wu.s t0, f25 +fcvt.wu.s t0, f31 +fcvt.wu.s a0, f0 +fcvt.wu.s a0, f1 +fcvt.wu.s a0, f5 +fcvt.wu.s a0, f10 +fcvt.wu.s a0, f15 +fcvt.wu.s a0, f20 +fcvt.wu.s a0, f25 +fcvt.wu.s a0, f31 +fcvt.wu.s a5, f0 +fcvt.wu.s a5, f1 +fcvt.wu.s a5, f5 +fcvt.wu.s a5, f10 +fcvt.wu.s a5, f15 +fcvt.wu.s a5, f20 +fcvt.wu.s a5, f25 +fcvt.wu.s a5, f31 +fcvt.wu.s s4, f0 +fcvt.wu.s s4, f1 +fcvt.wu.s s4, f5 +fcvt.wu.s s4, f10 +fcvt.wu.s s4, f15 +fcvt.wu.s s4, f20 +fcvt.wu.s s4, f25 +fcvt.wu.s s4, f31 +fcvt.wu.s s9, f0 +fcvt.wu.s s9, f1 +fcvt.wu.s s9, f5 +fcvt.wu.s s9, f10 +fcvt.wu.s s9, f15 +fcvt.wu.s s9, f20 +fcvt.wu.s s9, f25 +fcvt.wu.s s9, f31 +fcvt.wu.s t6, f0 +fcvt.wu.s t6, f1 +fcvt.wu.s t6, f5 +fcvt.wu.s t6, f10 +fcvt.wu.s t6, f15 +fcvt.wu.s t6, f20 +fcvt.wu.s t6, f25 +fcvt.wu.s t6, f31 diff --git a/tests/riscv/f-extension/fcvt_s_w.asm b/tests/riscv/f-extension/fcvt_s_w.asm new file mode 100644 index 0000000..9d564e3 --- /dev/null +++ b/tests/riscv/f-extension/fcvt_s_w.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.s.w f0, a1 + diff --git a/tests/riscv/f-extension/fcvt_s_w.bin b/tests/riscv/f-extension/fcvt_s_w.bin new file mode 100644 index 0000000..49f7b41 --- /dev/null +++ b/tests/riscv/f-extension/fcvt_s_w.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/f-extension/fcvt_s_w.disasm b/tests/riscv/f-extension/fcvt_s_w.disasm new file mode 100644 index 0000000..bbb735d --- /dev/null +++ b/tests/riscv/f-extension/fcvt_s_w.disasm @@ -0,0 +1 @@ +fcvt.s.w f0, a1 diff --git a/tests/riscv/f-extension/fcvt_s_wu.asm b/tests/riscv/f-extension/fcvt_s_wu.asm new file mode 100644 index 0000000..0d41932 --- /dev/null +++ b/tests/riscv/f-extension/fcvt_s_wu.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.s.wu f0, a1 + diff --git a/tests/riscv/f-extension/fcvt_s_wu.bin b/tests/riscv/f-extension/fcvt_s_wu.bin new file mode 100644 index 0000000..21b8900 --- /dev/null +++ b/tests/riscv/f-extension/fcvt_s_wu.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/f-extension/fcvt_s_wu.disasm b/tests/riscv/f-extension/fcvt_s_wu.disasm new file mode 100644 index 0000000..264cd1a --- /dev/null +++ b/tests/riscv/f-extension/fcvt_s_wu.disasm @@ -0,0 +1 @@ +fcvt.s.wu f0, a1 diff --git a/tests/riscv/f-extension/fcvt_w_s.asm b/tests/riscv/f-extension/fcvt_w_s.asm new file mode 100644 index 0000000..fece73d --- /dev/null +++ b/tests/riscv/f-extension/fcvt_w_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.w.s a0, f1 + diff --git a/tests/riscv/f-extension/fcvt_w_s.bin b/tests/riscv/f-extension/fcvt_w_s.bin new file mode 100644 index 0000000000000000000000000000000000000000..239c29a3d67b7e7ef4c96f6d3fd839e2ec0e80b6 GIT binary patch literal 4 LcmWG;WjFu;1D^qz literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fcvt_w_s.disasm b/tests/riscv/f-extension/fcvt_w_s.disasm new file mode 100644 index 0000000..164f51a --- /dev/null +++ b/tests/riscv/f-extension/fcvt_w_s.disasm @@ -0,0 +1 @@ +fcvt.w.s a0, f1 diff --git a/tests/riscv/f-extension/fcvt_wu_s.asm b/tests/riscv/f-extension/fcvt_wu_s.asm new file mode 100644 index 0000000..f71abd0 --- /dev/null +++ b/tests/riscv/f-extension/fcvt_wu_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fcvt.wu.s a0, f1 + diff --git a/tests/riscv/f-extension/fcvt_wu_s.bin b/tests/riscv/f-extension/fcvt_wu_s.bin new file mode 100644 index 0000000000000000000000000000000000000000..eea702ac8bb73645a37fad2b30cf228475ee0e8a GIT binary patch literal 4 LcmWHZ%5VSx1J41e literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fcvt_wu_s.disasm b/tests/riscv/f-extension/fcvt_wu_s.disasm new file mode 100644 index 0000000..d8d49cc --- /dev/null +++ b/tests/riscv/f-extension/fcvt_wu_s.disasm @@ -0,0 +1 @@ +fcvt.wu.s a0, f1 diff --git a/tests/riscv/f-extension/fdiv.s.asm b/tests/riscv/f-extension/fdiv.s.asm new file mode 100644 index 0000000..eb6e8ff --- /dev/null +++ b/tests/riscv/f-extension/fdiv.s.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fdiv.s f0, f0, f0 +fdiv.s f0, f0, f1 +fdiv.s f0, f0, f5 +fdiv.s f0, f0, f10 +fdiv.s f0, f0, f15 +fdiv.s f0, f0, f20 +fdiv.s f0, f0, f25 +fdiv.s f0, f0, f31 +fdiv.s f0, f1, f0 +fdiv.s f0, f1, f1 +fdiv.s f0, f1, f5 +fdiv.s f0, f1, f10 +fdiv.s f0, f1, f15 +fdiv.s f0, f1, f20 +fdiv.s f0, f1, f25 +fdiv.s f0, f1, f31 +fdiv.s f0, f5, f0 +fdiv.s f0, f5, f1 +fdiv.s f0, f5, f5 +fdiv.s f0, f5, f10 +fdiv.s f0, f5, f15 +fdiv.s f0, f5, f20 +fdiv.s f0, f5, f25 +fdiv.s f0, f5, f31 +fdiv.s f0, f10, f0 +fdiv.s f0, f10, f1 +fdiv.s f0, f10, f5 +fdiv.s f0, f10, f10 +fdiv.s f0, f10, f15 +fdiv.s f0, f10, f20 +fdiv.s f0, f10, f25 +fdiv.s f0, f10, f31 +fdiv.s f0, f15, f0 +fdiv.s f0, f15, f1 +fdiv.s f0, f15, f5 +fdiv.s f0, f15, f10 +fdiv.s f0, f15, f15 +fdiv.s f0, f15, f20 +fdiv.s f0, f15, f25 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f20 +fdiv.s f20, f5, f25 +fdiv.s f20, f5, f31 +fdiv.s f20, f10, f0 +fdiv.s f20, f10, f1 +fdiv.s f20, f10, f5 +fdiv.s f20, f10, f10 +fdiv.s f20, f10, f15 +fdiv.s f20, f10, f20 +fdiv.s f20, f10, f25 +fdiv.s f20, f10, f31 +fdiv.s f20, f15, f0 +fdiv.s f20, f15, f1 +fdiv.s f20, f15, f5 +fdiv.s f20, f15, f10 +fdiv.s f20, f15, f15 +fdiv.s f20, f15, f20 +fdiv.s f20, f15, f25 +fdiv.s f20, f15, f31 +fdiv.s f20, f20, f0 +fdiv.s f20, f20, f1 +fdiv.s f20, f20, f5 +fdiv.s f20, f20, f10 +fdiv.s f20, f20, f15 +fdiv.s f20, f20, f20 +fdiv.s f20, f20, f25 +fdiv.s f20, f20, f31 +fdiv.s f20, f25, f0 +fdiv.s f20, f25, f1 +fdiv.s f20, f25, f5 +fdiv.s f20, f25, f10 +fdiv.s f20, f25, f15 +fdiv.s f20, f25, f20 +fdiv.s f20, f25, f25 +fdiv.s f20, f25, f31 +fdiv.s f20, f31, f0 +fdiv.s f20, f31, f1 +fdiv.s f20, f31, f5 +fdiv.s f20, f31, f10 +fdiv.s f20, f31, f15 +fdiv.s f20, f31, f20 +fdiv.s f20, f31, f25 +fdiv.s f20, f31, f31 +fdiv.s f25, f0, f0 +fdiv.s f25, f0, f1 +fdiv.s f25, f0, f5 +fdiv.s f25, f0, f10 +fdiv.s f25, f0, f15 +fdiv.s f25, f0, f20 +fdiv.s f25, f0, f25 +fdiv.s f25, f0, f31 +fdiv.s f25, f1, f0 +fdiv.s f25, f1, f1 +fdiv.s f25, f1, f5 +fdiv.s f25, f1, f10 +fdiv.s f25, f1, f15 +fdiv.s f25, f1, f20 +fdiv.s f25, f1, f25 +fdiv.s f25, f1, f31 +fdiv.s f25, f5, f0 +fdiv.s f25, f5, f1 +fdiv.s f25, f5, f5 +fdiv.s f25, f5, f10 +fdiv.s f25, f5, f15 +fdiv.s f25, f5, f20 +fdiv.s f25, f5, f25 +fdiv.s f25, f5, f31 +fdiv.s f25, f10, f0 +fdiv.s f25, f10, f1 +fdiv.s f25, f10, f5 +fdiv.s f25, f10, f10 +fdiv.s f25, f10, f15 +fdiv.s f25, f10, f20 +fdiv.s f25, f10, f25 +fdiv.s f25, f10, f31 +fdiv.s f25, f15, f0 +fdiv.s f25, f15, f1 +fdiv.s f25, f15, f5 +fdiv.s f25, f15, f10 +fdiv.s f25, f15, f15 +fdiv.s f25, f15, f20 +fdiv.s f25, f15, f25 +fdiv.s f25, f15, f31 +fdiv.s f25, f20, f0 +fdiv.s f25, f20, f1 +fdiv.s f25, f20, f5 +fdiv.s f25, f20, f10 +fdiv.s f25, f20, f15 +fdiv.s f25, f20, f20 +fdiv.s f25, f20, f25 +fdiv.s f25, f20, f31 +fdiv.s f25, f25, f0 +fdiv.s f25, f25, f1 +fdiv.s f25, f25, f5 +fdiv.s f25, f25, f10 +fdiv.s f25, f25, f15 +fdiv.s f25, f25, f20 +fdiv.s f25, f25, f25 +fdiv.s f25, f25, f31 +fdiv.s f25, f31, f0 +fdiv.s f25, f31, f1 +fdiv.s f25, f31, f5 +fdiv.s f25, f31, f10 +fdiv.s f25, f31, f15 +fdiv.s f25, f31, f20 +fdiv.s f25, f31, f25 +fdiv.s f25, f31, f31 +fdiv.s f31, f0, f0 +fdiv.s f31, f0, f1 +fdiv.s f31, f0, f5 +fdiv.s f31, f0, f10 +fdiv.s f31, f0, f15 +fdiv.s f31, f0, f20 +fdiv.s f31, f0, f25 +fdiv.s f31, f0, f31 +fdiv.s f31, f1, f0 +fdiv.s f31, f1, f1 +fdiv.s f31, f1, f5 +fdiv.s f31, f1, f10 +fdiv.s f31, f1, f15 +fdiv.s f31, f1, f20 +fdiv.s f31, f1, f25 +fdiv.s f31, f1, f31 +fdiv.s f31, f5, f0 +fdiv.s f31, f5, f1 +fdiv.s f31, f5, f5 +fdiv.s f31, f5, f10 +fdiv.s f31, f5, f15 +fdiv.s f31, f5, f20 +fdiv.s f31, f5, f25 +fdiv.s f31, f5, f31 +fdiv.s f31, f10, f0 +fdiv.s f31, f10, f1 +fdiv.s f31, f10, f5 +fdiv.s f31, f10, f10 +fdiv.s f31, f10, f15 +fdiv.s f31, f10, f20 +fdiv.s f31, f10, f25 +fdiv.s f31, f10, f31 +fdiv.s f31, f15, f0 +fdiv.s f31, f15, f1 +fdiv.s f31, f15, f5 +fdiv.s f31, f15, f10 +fdiv.s f31, f15, f15 +fdiv.s f31, f15, f20 +fdiv.s f31, f15, f25 +fdiv.s f31, f15, f31 +fdiv.s f31, f20, f0 +fdiv.s f31, f20, f1 +fdiv.s f31, f20, f5 +fdiv.s f31, f20, f10 +fdiv.s f31, f20, f15 +fdiv.s f31, f20, f20 +fdiv.s f31, f20, f25 +fdiv.s f31, f20, f31 +fdiv.s f31, f25, f0 +fdiv.s f31, f25, f1 +fdiv.s f31, f25, f5 +fdiv.s f31, f25, f10 +fdiv.s f31, f25, f15 +fdiv.s f31, f25, f20 +fdiv.s f31, f25, f25 +fdiv.s f31, f25, f31 +fdiv.s f31, f31, f0 +fdiv.s f31, f31, f1 +fdiv.s f31, f31, f5 +fdiv.s f31, f31, f10 +fdiv.s f31, f31, f15 +fdiv.s f31, f31, f20 +fdiv.s f31, f31, f25 +fdiv.s f31, f31, f31 diff --git a/tests/riscv/f-extension/fdiv_s.asm b/tests/riscv/f-extension/fdiv_s.asm new file mode 100644 index 0000000..692fc1d --- /dev/null +++ b/tests/riscv/f-extension/fdiv_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fdiv.s f0, f1, f2 + diff --git a/tests/riscv/f-extension/fdiv_s.bin b/tests/riscv/f-extension/fdiv_s.bin new file mode 100644 index 0000000..131b499 --- /dev/null +++ b/tests/riscv/f-extension/fdiv_s.bin @@ -0,0 +1 @@ +S  \ No newline at end of file diff --git a/tests/riscv/f-extension/fdiv_s.disasm b/tests/riscv/f-extension/fdiv_s.disasm new file mode 100644 index 0000000..19f0d1e --- /dev/null +++ b/tests/riscv/f-extension/fdiv_s.disasm @@ -0,0 +1 @@ +fdiv.s f0, f1, f2 diff --git a/tests/riscv/f-extension/feq.s.asm b/tests/riscv/f-extension/feq.s.asm new file mode 100644 index 0000000..0f37daa --- /dev/null +++ b/tests/riscv/f-extension/feq.s.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +feq.s zero, f0, f0 +feq.s zero, f0, f1 +feq.s zero, f0, f5 +feq.s zero, f0, f10 +feq.s zero, f0, f15 +feq.s zero, f0, f20 +feq.s zero, f0, f25 +feq.s zero, f0, f31 +feq.s zero, f1, f0 +feq.s zero, f1, f1 +feq.s zero, f1, f5 +feq.s zero, f1, f10 +feq.s zero, f1, f15 +feq.s zero, f1, f20 +feq.s zero, f1, f25 +feq.s zero, f1, f31 +feq.s zero, f5, f0 +feq.s zero, f5, f1 +feq.s zero, f5, f5 +feq.s zero, f5, f10 +feq.s zero, f5, f15 +feq.s zero, f5, f20 +feq.s zero, f5, f25 +feq.s zero, f5, f31 +feq.s zero, f10, f0 +feq.s zero, f10, f1 +feq.s zero, f10, f5 +feq.s zero, f10, f10 +feq.s zero, f10, f15 +feq.s zero, f10, f20 +feq.s zero, f10, f25 +feq.s zero, f10, f31 +feq.s zero, f15, f0 +feq.s zero, f15, f1 +feq.s zero, f15, f5 +feq.s zero, f15, f10 +feq.s zero, f15, f15 +feq.s zero, f15, f20 +feq.s zero, f15, f25 +feq.s zero, f15, f31 +feq.s zero, f20, f0 +feq.s zero, f20, f1 +feq.s zero, f20, f5 +feq.s zero, f20, f10 +feq.s zero, f20, f15 +feq.s zero, f20, f20 +feq.s zero, f20, f25 +feq.s zero, f20, f31 +feq.s zero, f25, f0 +feq.s zero, f25, f1 +feq.s zero, f25, f5 +feq.s zero, f25, f10 +feq.s zero, f25, f15 +feq.s zero, f25, f20 +feq.s zero, f25, f25 +feq.s zero, f25, f31 +feq.s zero, f31, f0 +feq.s zero, f31, f1 +feq.s zero, f31, f5 +feq.s zero, f31, f10 +feq.s zero, f31, f15 +feq.s zero, f31, f20 +feq.s zero, f31, f25 +feq.s zero, f31, f31 +feq.s ra, f0, f0 +feq.s ra, f0, f1 +feq.s ra, f0, f5 +feq.s ra, f0, f10 +feq.s ra, f0, f15 +feq.s ra, f0, f20 +feq.s ra, f0, f25 +feq.s ra, f0, f31 +feq.s ra, f1, f0 +feq.s ra, f1, f1 +feq.s ra, f1, f5 +feq.s ra, f1, f10 +feq.s ra, f1, f15 +feq.s ra, f1, f20 +feq.s ra, f1, f25 +feq.s ra, f1, f31 +feq.s ra, f5, f0 +feq.s ra, f5, f1 +feq.s ra, f5, f5 +feq.s ra, f5, f10 +feq.s ra, f5, f15 +feq.s ra, f5, f20 +feq.s ra, f5, f25 +feq.s ra, f5, f31 +feq.s ra, f10, f0 +feq.s ra, f10, f1 +feq.s ra, f10, f5 +feq.s ra, f10, f10 +feq.s ra, f10, f15 +feq.s ra, f10, f20 +feq.s ra, f10, f25 +feq.s ra, f10, f31 +feq.s ra, f15, f0 +feq.s ra, f15, f1 +feq.s ra, f15, f5 +feq.s ra, f15, f10 +feq.s ra, f15, f15 +feq.s ra, f15, f20 +feq.s ra, f15, f25 +feq.s ra, f15, f31 +feq.s ra, f20, f0 +feq.s ra, f20, f1 +feq.s ra, f20, f5 +feq.s ra, f20, f10 +feq.s ra, f20, f15 +feq.s ra, f20, f20 +feq.s ra, f20, f25 +feq.s ra, f20, f31 +feq.s ra, f25, f0 +feq.s ra, f25, f1 +feq.s ra, f25, f5 +feq.s ra, f25, f10 +feq.s ra, f25, f15 +feq.s ra, f25, f20 +feq.s ra, f25, f25 +feq.s ra, f25, f31 +feq.s ra, f31, f0 +feq.s ra, f31, f1 +feq.s ra, f31, f5 +feq.s ra, f31, f10 +feq.s ra, f31, f15 +feq.s ra, f31, f20 +feq.s ra, f31, f25 +feq.s ra, f31, f31 +feq.s t0, f0, f0 +feq.s t0, f0, f1 +feq.s t0, f0, f5 +feq.s t0, f0, f10 +feq.s t0, f0, f15 +feq.s t0, f0, f20 +feq.s t0, f0, f25 +feq.s t0, f0, f31 +feq.s t0, f1, f0 +feq.s t0, f1, f1 +feq.s t0, f1, f5 +feq.s t0, f1, f10 +feq.s t0, f1, f15 +feq.s t0, f1, f20 +feq.s t0, f1, f25 +feq.s t0, f1, f31 +feq.s t0, f5, f0 +feq.s t0, f5, f1 +feq.s t0, f5, f5 +feq.s t0, f5, f10 +feq.s t0, f5, f15 +feq.s t0, f5, f20 +feq.s t0, f5, f25 +feq.s t0, f5, f31 +feq.s t0, f10, f0 +feq.s t0, f10, f1 +feq.s t0, f10, f5 +feq.s t0, f10, f10 +feq.s t0, f10, f15 +feq.s t0, f10, f20 +feq.s t0, f10, f25 +feq.s t0, f10, f31 +feq.s t0, f15, f0 +feq.s t0, f15, f1 +feq.s t0, f15, f5 +feq.s t0, f15, f10 +feq.s t0, f15, f15 +feq.s t0, f15, f20 +feq.s t0, f15, f25 +feq.s t0, f15, f31 +feq.s t0, f20, f0 +feq.s t0, f20, f1 +feq.s t0, f20, f5 +feq.s t0, f20, f10 +feq.s t0, f20, f15 +feq.s t0, f20, f20 +feq.s t0, f20, f25 +feq.s t0, f20, f31 +feq.s t0, f25, f0 +feq.s t0, f25, f1 +feq.s t0, f25, f5 +feq.s t0, f25, f10 +feq.s t0, f25, f15 +feq.s t0, f25, f20 +feq.s t0, f25, f25 +feq.s t0, f25, f31 +feq.s t0, f31, f0 +feq.s t0, f31, f1 +feq.s t0, f31, f5 +feq.s t0, f31, f10 +feq.s t0, f31, f15 +feq.s t0, f31, f20 +feq.s t0, f31, f25 +feq.s t0, f31, f31 +feq.s a0, f0, f0 +feq.s a0, f0, f1 +feq.s a0, f0, f5 +feq.s a0, f0, f10 +feq.s a0, f0, f15 +feq.s a0, f0, f20 +feq.s a0, f0, f25 +feq.s a0, f0, f31 +feq.s a0, f1, f0 +feq.s a0, f1, f1 +feq.s a0, f1, f5 +feq.s a0, f1, f10 +feq.s a0, f1, f15 +feq.s a0, f1, f20 +feq.s a0, f1, f25 +feq.s a0, f1, f31 +feq.s a0, f5, f0 +feq.s a0, f5, f1 +feq.s a0, f5, f5 +feq.s a0, f5, f10 +feq.s a0, f5, f15 +feq.s a0, f5, f20 +feq.s a0, f5, f25 +feq.s a0, f5, f31 +feq.s a0, f10, f0 +feq.s a0, f10, f1 +feq.s a0, f10, f5 +feq.s a0, f10, f10 +feq.s a0, f10, f15 +feq.s a0, f10, f20 +feq.s a0, f10, f25 +feq.s a0, f10, f31 +feq.s a0, f15, f0 +feq.s a0, f15, f1 +feq.s a0, f15, f5 +feq.s a0, f15, f10 +feq.s a0, f15, f15 +feq.s a0, f15, f20 +feq.s a0, f15, f25 +feq.s a0, f15, f31 +feq.s a0, f20, f0 +feq.s a0, f20, f1 +feq.s a0, f20, f5 +feq.s a0, f20, f10 +feq.s a0, f20, f15 +feq.s a0, f20, f20 +feq.s a0, f20, f25 +feq.s a0, f20, f31 +feq.s a0, f25, f0 +feq.s a0, f25, f1 +feq.s a0, f25, f5 +feq.s a0, f25, f10 +feq.s a0, f25, f15 +feq.s a0, f25, f20 +feq.s a0, f25, f25 +feq.s a0, f25, f31 +feq.s a0, f31, f0 +feq.s a0, f31, f1 +feq.s a0, f31, f5 +feq.s a0, f31, f10 +feq.s a0, f31, f15 +feq.s a0, f31, f20 +feq.s a0, f31, f25 +feq.s a0, f31, f31 +feq.s a5, f0, f0 +feq.s a5, f0, f1 +feq.s a5, f0, f5 +feq.s a5, f0, f10 +feq.s a5, f0, f15 +feq.s a5, f0, f20 +feq.s a5, f0, f25 +feq.s a5, f0, f31 +feq.s a5, f1, f0 +feq.s a5, f1, f1 +feq.s a5, f1, f5 +feq.s a5, f1, f10 +feq.s a5, f1, f15 +feq.s a5, f1, f20 +feq.s a5, f1, f25 +feq.s a5, f1, f31 +feq.s a5, f5, f0 +feq.s a5, f5, f1 +feq.s a5, f5, f5 +feq.s a5, f5, f10 +feq.s a5, f5, f15 +feq.s a5, f5, f20 +feq.s a5, f5, f25 +feq.s a5, f5, f31 +feq.s a5, f10, f0 +feq.s a5, f10, f1 +feq.s a5, f10, f5 +feq.s a5, f10, f10 +feq.s a5, f10, f15 +feq.s a5, f10, f20 +feq.s a5, f10, f25 +feq.s a5, f10, f31 +feq.s a5, f15, f0 +feq.s a5, f15, f1 +feq.s a5, f15, f5 +feq.s a5, f15, f10 +feq.s a5, f15, f15 +feq.s a5, f15, f20 +feq.s a5, f15, f25 +feq.s a5, f15, f31 +feq.s a5, f20, f0 +feq.s a5, f20, f1 +feq.s a5, f20, f5 +feq.s a5, f20, f10 +feq.s a5, f20, f15 +feq.s a5, f20, f20 +feq.s a5, f20, f25 +feq.s a5, f20, f31 +feq.s a5, f25, f0 +feq.s a5, f25, f1 +feq.s a5, f25, f5 +feq.s a5, f25, f10 +feq.s a5, f25, f15 +feq.s a5, f25, f20 +feq.s a5, f25, f25 +feq.s a5, f25, f31 +feq.s a5, f31, f0 +feq.s a5, f31, f1 +feq.s a5, f31, f5 +feq.s a5, f31, f10 +feq.s a5, f31, f15 +feq.s a5, f31, f20 +feq.s a5, f31, f25 +feq.s a5, f31, f31 +feq.s s4, f0, f0 +feq.s s4, f0, f1 +feq.s s4, f0, f5 +feq.s s4, f0, f10 +feq.s s4, f0, f15 +feq.s s4, f0, f20 +feq.s s4, f0, f25 +feq.s s4, f0, f31 +feq.s s4, f1, f0 +feq.s s4, f1, f1 +feq.s s4, f1, f5 +feq.s s4, f1, f10 +feq.s s4, f1, f15 +feq.s s4, f1, f20 +feq.s s4, f1, f25 +feq.s s4, f1, f31 +feq.s s4, f5, f0 +feq.s s4, f5, f1 +feq.s s4, f5, f5 +feq.s s4, f5, f10 +feq.s s4, f5, f15 +feq.s s4, f5, f20 +feq.s s4, f5, f25 +feq.s s4, f5, f31 +feq.s s4, f10, f0 +feq.s s4, f10, f1 +feq.s s4, f10, f5 +feq.s s4, f10, f10 +feq.s s4, f10, f15 +feq.s s4, f10, f20 +feq.s s4, f10, f25 +feq.s s4, f10, f31 +feq.s s4, f15, f0 +feq.s s4, f15, f1 +feq.s s4, f15, f5 +feq.s s4, f15, f10 +feq.s s4, f15, f15 +feq.s s4, f15, f20 +feq.s s4, f15, f25 +feq.s s4, f15, f31 +feq.s s4, f20, f0 +feq.s s4, f20, f1 +feq.s s4, f20, f5 +feq.s s4, f20, f10 +feq.s s4, f20, f15 +feq.s s4, f20, f20 +feq.s s4, f20, f25 +feq.s s4, f20, f31 +feq.s s4, f25, f0 +feq.s s4, f25, f1 +feq.s s4, f25, f5 +feq.s s4, f25, f10 +feq.s s4, f25, f15 +feq.s s4, f25, f20 +feq.s s4, f25, f25 +feq.s s4, f25, f31 +feq.s s4, f31, f0 +feq.s s4, f31, f1 +feq.s s4, f31, f5 +feq.s s4, f31, f10 +feq.s s4, f31, f15 +feq.s s4, f31, f20 +feq.s s4, f31, f25 +feq.s s4, f31, f31 +feq.s s9, f0, f0 +feq.s s9, f0, f1 +feq.s s9, f0, f5 +feq.s s9, f0, f10 +feq.s s9, f0, f15 +feq.s s9, f0, f20 +feq.s s9, f0, f25 +feq.s s9, f0, f31 +feq.s s9, f1, f0 +feq.s s9, f1, f1 +feq.s s9, f1, f5 +feq.s s9, f1, f10 +feq.s s9, f1, f15 +feq.s s9, f1, f20 +feq.s s9, f1, f25 +feq.s s9, f1, f31 +feq.s s9, f5, f0 +feq.s s9, f5, f1 +feq.s s9, f5, f5 +feq.s s9, f5, f10 +feq.s s9, f5, f15 +feq.s s9, f5, f20 +feq.s s9, f5, f25 +feq.s s9, f5, f31 +feq.s s9, f10, f0 +feq.s s9, f10, f1 +feq.s s9, f10, f5 +feq.s s9, f10, f10 +feq.s s9, f10, f15 +feq.s s9, f10, f20 +feq.s s9, f10, f25 +feq.s s9, f10, f31 +feq.s s9, f15, f0 +feq.s s9, f15, f1 +feq.s s9, f15, f5 +feq.s s9, f15, f10 +feq.s s9, f15, f15 +feq.s s9, f15, f20 +feq.s s9, f15, f25 +feq.s s9, f15, f31 +feq.s s9, f20, f0 +feq.s s9, f20, f1 +feq.s s9, f20, f5 +feq.s s9, f20, f10 +feq.s s9, f20, f15 +feq.s s9, f20, f20 +feq.s s9, f20, f25 +feq.s s9, f20, f31 +feq.s s9, f25, f0 +feq.s s9, f25, f1 +feq.s s9, f25, f5 +feq.s s9, f25, f10 +feq.s s9, f25, f15 +feq.s s9, f25, f20 +feq.s s9, f25, f25 +feq.s s9, f25, f31 +feq.s s9, f31, f0 +feq.s s9, f31, f1 +feq.s s9, f31, f5 +feq.s s9, f31, f10 +feq.s s9, f31, f15 +feq.s s9, f31, f20 +feq.s s9, f31, f25 +feq.s s9, f31, f31 +feq.s t6, f0, f0 +feq.s t6, f0, f1 +feq.s t6, f0, f5 +feq.s t6, f0, f10 +feq.s t6, f0, f15 +feq.s t6, f0, f20 +feq.s t6, f0, f25 +feq.s t6, f0, f31 +feq.s t6, f1, f0 +feq.s t6, f1, f1 +feq.s t6, f1, f5 +feq.s t6, f1, f10 +feq.s t6, f1, f15 +feq.s t6, f1, f20 +feq.s t6, f1, f25 +feq.s t6, f1, f31 +feq.s t6, f5, f0 +feq.s t6, f5, f1 +feq.s t6, f5, f5 +feq.s t6, f5, f10 +feq.s t6, f5, f15 +feq.s t6, f5, f20 +feq.s t6, f5, f25 +feq.s t6, f5, f31 +feq.s t6, f10, f0 +feq.s t6, f10, f1 +feq.s t6, f10, f5 +feq.s t6, f10, f10 +feq.s t6, f10, f15 +feq.s t6, f10, f20 +feq.s t6, f10, f25 +feq.s t6, f10, f31 +feq.s t6, f15, f0 +feq.s t6, f15, f1 +feq.s t6, f15, f5 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/dev/null +++ b/tests/riscv/f-extension/feq_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +feq.s a0, f1, f2 + diff --git a/tests/riscv/f-extension/feq_s.bin b/tests/riscv/f-extension/feq_s.bin new file mode 100644 index 0000000..bbff46e --- /dev/null +++ b/tests/riscv/f-extension/feq_s.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/f-extension/feq_s.disasm b/tests/riscv/f-extension/feq_s.disasm new file mode 100644 index 0000000..924a426 --- /dev/null +++ b/tests/riscv/f-extension/feq_s.disasm @@ -0,0 +1 @@ +feq.s a0, f1, f2 diff --git a/tests/riscv/f-extension/fle.s.asm b/tests/riscv/f-extension/fle.s.asm new file mode 100644 index 0000000..d29c104 --- /dev/null +++ b/tests/riscv/f-extension/fle.s.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fle.s zero, f0, f0 +fle.s zero, f0, f1 +fle.s zero, f0, f5 +fle.s zero, f0, f10 +fle.s zero, f0, f15 +fle.s zero, f0, f20 +fle.s zero, f0, f25 +fle.s zero, f0, f31 +fle.s zero, f1, f0 +fle.s zero, f1, f1 +fle.s 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100644 index 0000000..e121e81 --- /dev/null +++ b/tests/riscv/f-extension/flw.disasm @@ -0,0 +1,1600 @@ +flw f0, (#0xfffff801, zero) +flw f0, (#0xfffffc00, zero) +flw f0, (#0xfffffe00, zero) +flw f0, (#0xffffff00, zero) +flw f0, (#0xffffff80, zero) +flw f0, (#0xffffffc0, zero) +flw f0, (#0xffffffe0, zero) +flw f0, (#0xfffffff0, zero) +flw f0, (#0xfffffff8, zero) +flw f0, (#0xfffffffc, zero) +flw f0, (#0xfffffffe, zero) +flw f0, (#0xffffffff, zero) +flw f0, (#0, zero) +flw f0, (#1, zero) +flw f0, (#2, zero) +flw f0, (#4, zero) +flw f0, (#8, zero) +flw f0, (#0x10, zero) +flw f0, (#0x20, zero) +flw f0, (#0x40, zero) +flw f0, (#0x80, zero) +flw f0, (#0x100, zero) +flw f0, (#0x200, zero) +flw f0, (#0x400, zero) +flw f0, (#0x7ff, zero) +flw f0, (#0xfffff801, ra) +flw f0, (#0xfffffc00, ra) +flw f0, (#0xfffffe00, ra) +flw f0, (#0xffffff00, ra) +flw f0, (#0xffffff80, ra) +flw f0, (#0xffffffc0, ra) +flw f0, (#0xffffffe0, ra) +flw f0, (#0xfffffff0, ra) +flw f0, (#0xfffffff8, ra) +flw f0, (#0xfffffffc, ra) +flw f0, (#0xfffffffe, ra) +flw f0, (#0xffffffff, ra) +flw f0, (#0, ra) +flw f0, (#1, ra) +flw f0, (#2, ra) +flw f0, (#4, ra) +flw f0, (#8, ra) +flw f0, (#0x10, ra) +flw f0, (#0x20, ra) +flw f0, (#0x40, ra) +flw f0, (#0x80, ra) +flw f0, (#0x100, ra) +flw f0, (#0x200, ra) +flw f0, (#0x400, ra) +flw f0, (#0x7ff, ra) +flw f0, (#0xfffff801, t0) +flw f0, (#0xfffffc00, t0) +flw f0, (#0xfffffe00, t0) +flw f0, (#0xffffff00, t0) +flw f0, (#0xffffff80, t0) +flw f0, (#0xffffffc0, t0) +flw f0, (#0xffffffe0, t0) +flw f0, (#0xfffffff0, t0) +flw f0, (#0xfffffff8, t0) +flw f0, (#0xfffffffc, t0) +flw f0, (#0xfffffffe, t0) +flw f0, (#0xffffffff, t0) +flw f0, (#0, t0) +flw f0, (#1, t0) +flw f0, (#2, t0) +flw f0, (#4, t0) +flw f0, (#8, t0) +flw f0, (#0x10, t0) +flw f0, (#0x20, t0) +flw f0, (#0x40, t0) +flw f0, (#0x80, t0) +flw f0, (#0x100, t0) +flw f0, (#0x200, t0) +flw f0, (#0x400, t0) +flw f0, (#0x7ff, t0) +flw f0, (#0xfffff801, a0) +flw f0, (#0xfffffc00, a0) +flw f0, (#0xfffffe00, a0) +flw f0, (#0xffffff00, a0) +flw f0, (#0xffffff80, a0) +flw f0, (#0xffffffc0, a0) +flw f0, (#0xffffffe0, a0) +flw f0, (#0xfffffff0, a0) +flw f0, (#0xfffffff8, a0) +flw f0, (#0xfffffffc, a0) +flw f0, (#0xfffffffe, a0) +flw f0, (#0xffffffff, a0) +flw f0, (#0, a0) +flw f0, (#1, a0) +flw f0, (#2, a0) +flw f0, (#4, a0) +flw f0, (#8, a0) +flw f0, (#0x10, a0) +flw f0, (#0x20, a0) +flw f0, (#0x40, a0) +flw f0, (#0x80, a0) +flw f0, (#0x100, a0) +flw f0, (#0x200, a0) +flw f0, (#0x400, a0) +flw f0, (#0x7ff, a0) +flw f0, (#0xfffff801, a5) +flw f0, (#0xfffffc00, a5) +flw f0, (#0xfffffe00, a5) +flw f0, (#0xffffff00, a5) +flw f0, (#0xffffff80, a5) +flw f0, (#0xffffffc0, a5) +flw f0, (#0xffffffe0, a5) +flw f0, (#0xfffffff0, a5) +flw f0, (#0xfffffff8, a5) +flw f0, (#0xfffffffc, a5) +flw f0, (#0xfffffffe, a5) +flw f0, (#0xffffffff, a5) +flw f0, (#0, a5) +flw f0, (#1, a5) +flw f0, (#2, a5) +flw f0, (#4, a5) +flw f0, (#8, a5) +flw f0, (#0x10, a5) +flw f0, (#0x20, a5) +flw f0, (#0x40, a5) +flw f0, (#0x80, a5) +flw f0, (#0x100, a5) +flw f0, (#0x200, a5) +flw f0, (#0x400, a5) +flw f0, (#0x7ff, a5) +flw f0, (#0xfffff801, s4) +flw f0, (#0xfffffc00, s4) +flw f0, (#0xfffffe00, s4) +flw f0, (#0xffffff00, s4) +flw f0, (#0xffffff80, s4) +flw f0, (#0xffffffc0, s4) +flw f0, (#0xffffffe0, s4) +flw f0, (#0xfffffff0, s4) +flw f0, (#0xfffffff8, s4) +flw f0, (#0xfffffffc, s4) +flw f0, (#0xfffffffe, s4) +flw f0, (#0xffffffff, s4) +flw f0, (#0, s4) +flw f0, (#1, s4) +flw f0, (#2, s4) +flw f0, (#4, s4) +flw f0, (#8, s4) +flw f0, (#0x10, s4) +flw f0, (#0x20, s4) +flw f0, (#0x40, s4) +flw f0, (#0x80, s4) +flw f0, (#0x100, s4) +flw f0, (#0x200, s4) +flw f0, (#0x400, s4) +flw f0, (#0x7ff, s4) +flw f0, (#0xfffff801, s9) +flw f0, (#0xfffffc00, s9) +flw f0, (#0xfffffe00, s9) +flw f0, (#0xffffff00, s9) +flw f0, (#0xffffff80, s9) +flw f0, (#0xffffffc0, s9) +flw f0, (#0xffffffe0, s9) +flw f0, (#0xfffffff0, s9) +flw f0, (#0xfffffff8, s9) +flw f0, (#0xfffffffc, s9) +flw f0, (#0xfffffffe, s9) +flw f0, (#0xffffffff, s9) +flw f0, (#0, s9) +flw f0, (#1, s9) +flw f0, (#2, s9) +flw f0, (#4, s9) +flw f0, (#8, s9) +flw f0, (#0x10, s9) +flw f0, (#0x20, s9) +flw f0, (#0x40, s9) +flw f0, (#0x80, s9) +flw f0, (#0x100, s9) +flw f0, (#0x200, s9) +flw f0, (#0x400, s9) +flw f0, (#0x7ff, s9) +flw f0, (#0xfffff801, t6) +flw f0, (#0xfffffc00, t6) +flw f0, (#0xfffffe00, t6) +flw f0, (#0xffffff00, t6) +flw f0, (#0xffffff80, t6) +flw f0, (#0xffffffc0, t6) +flw f0, (#0xffffffe0, t6) +flw f0, (#0xfffffff0, t6) +flw f0, (#0xfffffff8, t6) +flw f0, (#0xfffffffc, t6) +flw f0, (#0xfffffffe, t6) +flw f0, (#0xffffffff, t6) +flw f0, (#0, t6) +flw f0, (#1, t6) +flw f0, (#2, t6) +flw f0, (#4, t6) +flw f0, (#8, t6) +flw f0, (#0x10, t6) +flw f0, (#0x20, t6) +flw f0, (#0x40, t6) +flw f0, (#0x80, t6) +flw f0, (#0x100, t6) +flw f0, (#0x200, t6) +flw f0, (#0x400, t6) +flw f0, (#0x7ff, t6) +flw f1, (#0xfffff801, zero) +flw f1, (#0xfffffc00, zero) +flw f1, (#0xfffffe00, zero) +flw f1, (#0xffffff00, zero) +flw f1, (#0xffffff80, zero) +flw f1, (#0xffffffc0, zero) +flw f1, (#0xffffffe0, zero) +flw f1, (#0xfffffff0, zero) +flw f1, (#0xfffffff8, zero) +flw f1, (#0xfffffffc, zero) +flw f1, (#0xfffffffe, zero) +flw f1, (#0xffffffff, zero) +flw f1, (#0, zero) +flw f1, (#1, zero) +flw f1, (#2, zero) +flw f1, (#4, zero) +flw f1, (#8, zero) +flw f1, (#0x10, zero) +flw f1, (#0x20, zero) +flw f1, (#0x40, zero) +flw f1, (#0x80, zero) +flw f1, (#0x100, zero) +flw f1, (#0x200, zero) +flw f1, (#0x400, zero) +flw f1, (#0x7ff, zero) +flw f1, (#0xfffff801, ra) +flw f1, (#0xfffffc00, ra) +flw f1, (#0xfffffe00, ra) +flw f1, (#0xffffff00, ra) +flw f1, (#0xffffff80, ra) +flw f1, (#0xffffffc0, ra) +flw f1, (#0xffffffe0, ra) +flw f1, (#0xfffffff0, ra) +flw f1, (#0xfffffff8, ra) +flw f1, (#0xfffffffc, ra) +flw f1, (#0xfffffffe, ra) +flw f1, (#0xffffffff, ra) +flw f1, (#0, ra) +flw f1, (#1, ra) +flw f1, (#2, ra) +flw f1, (#4, ra) +flw f1, (#8, ra) +flw f1, (#0x10, ra) +flw f1, (#0x20, ra) +flw f1, (#0x40, ra) +flw f1, (#0x80, ra) +flw f1, (#0x100, ra) +flw f1, (#0x200, ra) +flw f1, (#0x400, ra) +flw f1, (#0x7ff, ra) +flw f1, (#0xfffff801, t0) +flw f1, (#0xfffffc00, t0) +flw f1, (#0xfffffe00, t0) +flw f1, (#0xffffff00, t0) +flw f1, (#0xffffff80, t0) +flw f1, (#0xffffffc0, t0) +flw f1, (#0xffffffe0, t0) +flw f1, (#0xfffffff0, t0) +flw f1, (#0xfffffff8, t0) +flw f1, (#0xfffffffc, t0) +flw f1, (#0xfffffffe, t0) +flw f1, (#0xffffffff, t0) +flw f1, (#0, t0) +flw f1, (#1, t0) +flw f1, (#2, t0) +flw f1, (#4, t0) +flw f1, (#8, t0) +flw f1, (#0x10, t0) +flw f1, (#0x20, t0) +flw f1, (#0x40, t0) +flw f1, (#0x80, t0) +flw f1, (#0x100, t0) +flw f1, (#0x200, t0) +flw f1, (#0x400, t0) +flw f1, (#0x7ff, t0) +flw f1, (#0xfffff801, a0) +flw f1, (#0xfffffc00, a0) +flw f1, (#0xfffffe00, a0) +flw f1, (#0xffffff00, a0) +flw f1, (#0xffffff80, a0) +flw f1, (#0xffffffc0, a0) +flw f1, (#0xffffffe0, a0) +flw f1, (#0xfffffff0, a0) +flw f1, (#0xfffffff8, a0) +flw f1, (#0xfffffffc, a0) +flw f1, (#0xfffffffe, a0) +flw f1, (#0xffffffff, a0) +flw f1, (#0, a0) +flw f1, (#1, a0) +flw f1, (#2, a0) +flw f1, (#4, a0) +flw f1, (#8, a0) +flw f1, (#0x10, a0) +flw f1, (#0x20, a0) +flw f1, (#0x40, a0) +flw f1, (#0x80, a0) +flw f1, (#0x100, a0) +flw f1, (#0x200, a0) +flw f1, (#0x400, a0) +flw f1, (#0x7ff, a0) +flw f1, (#0xfffff801, a5) +flw f1, (#0xfffffc00, a5) +flw f1, (#0xfffffe00, a5) +flw f1, (#0xffffff00, a5) +flw f1, (#0xffffff80, a5) +flw f1, (#0xffffffc0, a5) +flw f1, (#0xffffffe0, a5) +flw f1, (#0xfffffff0, a5) +flw f1, (#0xfffffff8, a5) +flw f1, (#0xfffffffc, a5) +flw f1, (#0xfffffffe, a5) +flw f1, (#0xffffffff, a5) +flw f1, (#0, a5) +flw f1, (#1, a5) +flw f1, (#2, a5) +flw f1, (#4, a5) +flw f1, (#8, a5) +flw f1, (#0x10, a5) +flw f1, (#0x20, a5) +flw f1, (#0x40, a5) +flw f1, (#0x80, a5) +flw f1, (#0x100, a5) +flw f1, (#0x200, a5) +flw f1, (#0x400, a5) +flw f1, (#0x7ff, a5) +flw f1, (#0xfffff801, s4) +flw f1, (#0xfffffc00, s4) +flw f1, (#0xfffffe00, s4) +flw f1, (#0xffffff00, s4) +flw f1, (#0xffffff80, s4) +flw f1, (#0xffffffc0, s4) +flw f1, (#0xffffffe0, s4) +flw f1, (#0xfffffff0, s4) +flw f1, (#0xfffffff8, s4) +flw f1, (#0xfffffffc, s4) +flw f1, (#0xfffffffe, s4) +flw f1, (#0xffffffff, s4) +flw f1, (#0, s4) +flw f1, (#1, s4) +flw f1, (#2, s4) +flw f1, (#4, s4) +flw f1, (#8, s4) +flw f1, (#0x10, s4) +flw f1, (#0x20, s4) +flw f1, (#0x40, s4) +flw f1, (#0x80, s4) +flw f1, (#0x100, s4) +flw f1, (#0x200, s4) +flw f1, (#0x400, s4) +flw f1, (#0x7ff, s4) +flw f1, (#0xfffff801, s9) +flw f1, (#0xfffffc00, s9) +flw f1, (#0xfffffe00, s9) +flw f1, (#0xffffff00, s9) +flw f1, (#0xffffff80, s9) +flw f1, (#0xffffffc0, s9) +flw f1, (#0xffffffe0, s9) +flw f1, (#0xfffffff0, s9) +flw f1, (#0xfffffff8, s9) +flw f1, (#0xfffffffc, s9) +flw f1, (#0xfffffffe, s9) +flw f1, (#0xffffffff, s9) +flw f1, (#0, s9) +flw f1, (#1, s9) +flw f1, (#2, s9) +flw f1, (#4, s9) +flw f1, (#8, s9) +flw f1, (#0x10, s9) +flw f1, (#0x20, s9) +flw f1, (#0x40, s9) +flw f1, (#0x80, s9) +flw f1, (#0x100, s9) +flw f1, (#0x200, s9) +flw f1, (#0x400, s9) +flw f1, (#0x7ff, s9) +flw f1, (#0xfffff801, t6) +flw f1, (#0xfffffc00, t6) +flw f1, (#0xfffffe00, t6) +flw f1, (#0xffffff00, t6) +flw f1, (#0xffffff80, t6) +flw f1, (#0xffffffc0, t6) +flw f1, (#0xffffffe0, t6) +flw f1, (#0xfffffff0, t6) +flw f1, (#0xfffffff8, t6) +flw f1, (#0xfffffffc, t6) +flw f1, (#0xfffffffe, t6) +flw f1, (#0xffffffff, t6) +flw f1, (#0, t6) +flw f1, (#1, t6) +flw f1, (#2, t6) +flw f1, (#4, t6) +flw f1, (#8, t6) +flw f1, (#0x10, t6) +flw f1, (#0x20, t6) +flw f1, (#0x40, t6) +flw f1, (#0x80, t6) +flw f1, (#0x100, t6) +flw f1, (#0x200, t6) +flw f1, (#0x400, t6) +flw f1, (#0x7ff, t6) +flw f5, (#0xfffff801, zero) +flw f5, (#0xfffffc00, zero) +flw f5, (#0xfffffe00, zero) +flw f5, (#0xffffff00, zero) +flw f5, (#0xffffff80, zero) +flw f5, (#0xffffffc0, zero) +flw f5, (#0xffffffe0, zero) +flw f5, (#0xfffffff0, zero) +flw f5, (#0xfffffff8, zero) +flw f5, (#0xfffffffc, zero) +flw f5, (#0xfffffffe, zero) +flw f5, (#0xffffffff, zero) +flw f5, (#0, zero) +flw f5, (#1, zero) +flw f5, (#2, zero) +flw f5, (#4, zero) +flw f5, (#8, zero) +flw f5, (#0x10, zero) +flw f5, (#0x20, zero) +flw f5, (#0x40, zero) +flw f5, (#0x80, zero) +flw f5, (#0x100, zero) +flw f5, (#0x200, zero) +flw f5, (#0x400, zero) +flw f5, (#0x7ff, zero) +flw f5, (#0xfffff801, ra) +flw f5, (#0xfffffc00, ra) +flw f5, (#0xfffffe00, ra) +flw f5, (#0xffffff00, ra) +flw f5, (#0xffffff80, ra) +flw f5, (#0xffffffc0, ra) +flw f5, (#0xffffffe0, ra) +flw f5, (#0xfffffff0, ra) +flw f5, (#0xfffffff8, ra) +flw f5, (#0xfffffffc, ra) +flw f5, (#0xfffffffe, ra) +flw f5, (#0xffffffff, ra) +flw f5, (#0, ra) +flw f5, (#1, ra) +flw f5, (#2, ra) +flw f5, (#4, ra) +flw f5, (#8, ra) +flw f5, (#0x10, ra) +flw f5, (#0x20, ra) +flw f5, (#0x40, ra) +flw f5, (#0x80, ra) +flw f5, (#0x100, ra) +flw f5, (#0x200, ra) +flw f5, (#0x400, ra) +flw f5, (#0x7ff, ra) +flw f5, (#0xfffff801, t0) +flw f5, (#0xfffffc00, t0) +flw f5, (#0xfffffe00, t0) +flw f5, (#0xffffff00, t0) +flw f5, (#0xffffff80, t0) +flw f5, (#0xffffffc0, t0) +flw f5, (#0xffffffe0, t0) +flw f5, (#0xfffffff0, t0) +flw f5, (#0xfffffff8, t0) +flw f5, (#0xfffffffc, t0) +flw f5, (#0xfffffffe, t0) +flw f5, (#0xffffffff, t0) +flw f5, (#0, t0) +flw f5, (#1, t0) +flw f5, (#2, t0) +flw f5, (#4, t0) +flw f5, (#8, t0) +flw f5, (#0x10, t0) +flw f5, (#0x20, t0) +flw f5, (#0x40, t0) +flw f5, (#0x80, t0) +flw f5, (#0x100, t0) +flw f5, (#0x200, t0) +flw f5, (#0x400, t0) +flw f5, (#0x7ff, t0) +flw f5, (#0xfffff801, a0) +flw f5, (#0xfffffc00, a0) +flw f5, (#0xfffffe00, a0) +flw f5, (#0xffffff00, a0) +flw f5, (#0xffffff80, a0) +flw f5, (#0xffffffc0, a0) +flw f5, (#0xffffffe0, a0) +flw f5, (#0xfffffff0, a0) +flw f5, (#0xfffffff8, a0) +flw f5, (#0xfffffffc, a0) +flw f5, (#0xfffffffe, a0) +flw f5, (#0xffffffff, a0) +flw f5, (#0, a0) +flw f5, (#1, a0) +flw f5, (#2, a0) +flw f5, (#4, a0) +flw f5, (#8, a0) +flw f5, (#0x10, a0) +flw f5, (#0x20, a0) +flw f5, (#0x40, a0) +flw f5, (#0x80, a0) +flw f5, (#0x100, a0) +flw f5, (#0x200, a0) +flw f5, (#0x400, a0) +flw f5, (#0x7ff, a0) +flw f5, (#0xfffff801, a5) +flw f5, (#0xfffffc00, a5) +flw f5, (#0xfffffe00, a5) +flw f5, (#0xffffff00, a5) +flw f5, (#0xffffff80, a5) +flw f5, (#0xffffffc0, a5) +flw f5, (#0xffffffe0, a5) +flw f5, (#0xfffffff0, a5) +flw f5, (#0xfffffff8, a5) +flw f5, (#0xfffffffc, a5) +flw f5, (#0xfffffffe, a5) +flw f5, (#0xffffffff, a5) +flw f5, (#0, a5) +flw f5, (#1, a5) +flw f5, (#2, a5) +flw f5, (#4, a5) +flw f5, (#8, a5) +flw f5, (#0x10, a5) +flw f5, (#0x20, a5) +flw f5, (#0x40, a5) +flw f5, (#0x80, a5) +flw f5, (#0x100, a5) +flw f5, (#0x200, a5) +flw f5, (#0x400, a5) +flw f5, (#0x7ff, a5) +flw f5, (#0xfffff801, s4) +flw f5, (#0xfffffc00, s4) +flw f5, (#0xfffffe00, s4) +flw f5, (#0xffffff00, s4) +flw f5, (#0xffffff80, s4) +flw f5, (#0xffffffc0, s4) +flw f5, (#0xffffffe0, s4) +flw f5, (#0xfffffff0, s4) +flw f5, (#0xfffffff8, s4) +flw f5, (#0xfffffffc, s4) +flw f5, (#0xfffffffe, s4) +flw f5, (#0xffffffff, s4) +flw f5, (#0, s4) +flw f5, (#1, s4) +flw f5, (#2, s4) +flw f5, (#4, s4) +flw f5, (#8, s4) +flw f5, (#0x10, s4) +flw f5, (#0x20, s4) +flw f5, (#0x40, s4) +flw f5, (#0x80, s4) +flw f5, (#0x100, s4) +flw f5, (#0x200, s4) +flw f5, (#0x400, s4) +flw f5, (#0x7ff, s4) +flw f5, (#0xfffff801, s9) +flw f5, (#0xfffffc00, s9) +flw f5, (#0xfffffe00, s9) +flw f5, (#0xffffff00, s9) +flw f5, (#0xffffff80, s9) +flw f5, (#0xffffffc0, s9) +flw f5, (#0xffffffe0, s9) +flw f5, (#0xfffffff0, s9) +flw f5, (#0xfffffff8, s9) +flw f5, (#0xfffffffc, s9) +flw f5, (#0xfffffffe, s9) +flw f5, (#0xffffffff, s9) +flw f5, (#0, s9) +flw f5, (#1, s9) +flw f5, (#2, s9) +flw f5, (#4, s9) +flw f5, (#8, s9) +flw f5, (#0x10, s9) +flw f5, (#0x20, s9) +flw f5, (#0x40, s9) +flw f5, (#0x80, s9) +flw f5, (#0x100, s9) +flw f5, (#0x200, s9) +flw f5, (#0x400, s9) +flw f5, (#0x7ff, s9) +flw f5, (#0xfffff801, t6) +flw f5, (#0xfffffc00, t6) +flw f5, (#0xfffffe00, t6) +flw f5, (#0xffffff00, t6) +flw f5, (#0xffffff80, t6) +flw f5, (#0xffffffc0, t6) +flw f5, (#0xffffffe0, t6) +flw f5, (#0xfffffff0, t6) +flw f5, (#0xfffffff8, t6) +flw f5, (#0xfffffffc, t6) +flw f5, (#0xfffffffe, t6) +flw f5, (#0xffffffff, t6) +flw f5, (#0, t6) +flw f5, (#1, t6) +flw f5, (#2, t6) +flw f5, (#4, t6) +flw f5, (#8, t6) +flw f5, (#0x10, t6) +flw f5, (#0x20, t6) +flw f5, (#0x40, t6) +flw f5, (#0x80, t6) +flw f5, (#0x100, t6) +flw f5, (#0x200, t6) +flw f5, (#0x400, t6) +flw f5, (#0x7ff, t6) +flw f10, (#0xfffff801, zero) +flw f10, (#0xfffffc00, zero) +flw f10, (#0xfffffe00, zero) +flw f10, (#0xffffff00, zero) +flw f10, (#0xffffff80, zero) +flw f10, (#0xffffffc0, zero) +flw f10, (#0xffffffe0, zero) +flw f10, (#0xfffffff0, zero) +flw f10, (#0xfffffff8, zero) +flw f10, (#0xfffffffc, zero) +flw f10, (#0xfffffffe, zero) +flw f10, (#0xffffffff, zero) +flw f10, (#0, zero) +flw f10, (#1, zero) +flw f10, (#2, zero) +flw f10, (#4, zero) +flw f10, (#8, zero) +flw f10, (#0x10, zero) +flw f10, (#0x20, zero) +flw f10, (#0x40, zero) +flw f10, (#0x80, zero) +flw f10, (#0x100, zero) +flw f10, (#0x200, zero) +flw f10, (#0x400, zero) +flw f10, (#0x7ff, zero) +flw f10, (#0xfffff801, ra) +flw f10, (#0xfffffc00, ra) +flw f10, (#0xfffffe00, ra) +flw f10, (#0xffffff00, ra) +flw f10, (#0xffffff80, ra) +flw f10, (#0xffffffc0, ra) +flw f10, (#0xffffffe0, ra) +flw f10, (#0xfffffff0, ra) +flw f10, (#0xfffffff8, ra) +flw f10, (#0xfffffffc, ra) +flw f10, (#0xfffffffe, ra) +flw f10, (#0xffffffff, ra) +flw f10, (#0, ra) +flw f10, (#1, ra) +flw f10, (#2, ra) +flw f10, (#4, ra) +flw f10, (#8, ra) +flw f10, (#0x10, ra) +flw f10, (#0x20, ra) +flw f10, (#0x40, ra) +flw f10, (#0x80, ra) +flw f10, (#0x100, ra) +flw f10, (#0x200, ra) +flw f10, (#0x400, ra) +flw f10, (#0x7ff, ra) +flw f10, (#0xfffff801, t0) +flw f10, (#0xfffffc00, t0) +flw f10, (#0xfffffe00, t0) +flw f10, (#0xffffff00, t0) +flw f10, (#0xffffff80, t0) +flw f10, (#0xffffffc0, t0) +flw f10, (#0xffffffe0, t0) +flw f10, (#0xfffffff0, t0) +flw f10, (#0xfffffff8, t0) +flw f10, (#0xfffffffc, t0) +flw f10, (#0xfffffffe, t0) +flw f10, (#0xffffffff, t0) +flw f10, (#0, t0) +flw f10, (#1, t0) +flw f10, (#2, t0) +flw f10, (#4, t0) +flw f10, (#8, t0) +flw f10, (#0x10, t0) +flw f10, (#0x20, t0) +flw f10, (#0x40, t0) +flw f10, (#0x80, t0) +flw f10, (#0x100, t0) +flw f10, (#0x200, t0) +flw f10, (#0x400, t0) +flw f10, (#0x7ff, t0) +flw f10, (#0xfffff801, a0) +flw f10, (#0xfffffc00, a0) +flw f10, (#0xfffffe00, a0) +flw f10, (#0xffffff00, a0) +flw f10, (#0xffffff80, a0) +flw f10, (#0xffffffc0, a0) +flw f10, (#0xffffffe0, a0) +flw f10, (#0xfffffff0, a0) +flw f10, (#0xfffffff8, a0) +flw f10, (#0xfffffffc, a0) +flw f10, (#0xfffffffe, a0) +flw f10, (#0xffffffff, a0) +flw f10, (#0, a0) +flw f10, (#1, a0) +flw f10, (#2, a0) +flw f10, (#4, a0) +flw f10, (#8, a0) +flw f10, (#0x10, a0) +flw f10, (#0x20, a0) +flw f10, (#0x40, a0) +flw f10, (#0x80, a0) +flw f10, (#0x100, a0) +flw f10, (#0x200, a0) +flw f10, (#0x400, a0) +flw f10, (#0x7ff, a0) +flw f10, (#0xfffff801, a5) +flw f10, (#0xfffffc00, a5) +flw f10, (#0xfffffe00, a5) +flw f10, (#0xffffff00, a5) +flw f10, (#0xffffff80, a5) +flw f10, (#0xffffffc0, a5) +flw f10, (#0xffffffe0, a5) +flw f10, (#0xfffffff0, a5) +flw f10, (#0xfffffff8, a5) +flw f10, (#0xfffffffc, a5) +flw f10, (#0xfffffffe, a5) +flw f10, (#0xffffffff, a5) +flw f10, (#0, a5) +flw f10, (#1, a5) +flw f10, (#2, a5) +flw f10, (#4, a5) +flw f10, (#8, a5) +flw f10, (#0x10, a5) +flw f10, (#0x20, a5) +flw f10, (#0x40, a5) +flw f10, (#0x80, a5) +flw f10, (#0x100, a5) +flw f10, (#0x200, a5) +flw f10, (#0x400, a5) +flw f10, (#0x7ff, a5) +flw f10, (#0xfffff801, s4) +flw f10, (#0xfffffc00, s4) +flw f10, (#0xfffffe00, s4) +flw f10, (#0xffffff00, s4) +flw f10, (#0xffffff80, s4) +flw f10, (#0xffffffc0, s4) +flw f10, (#0xffffffe0, s4) +flw f10, (#0xfffffff0, s4) +flw f10, (#0xfffffff8, s4) +flw f10, (#0xfffffffc, s4) +flw f10, (#0xfffffffe, s4) +flw f10, (#0xffffffff, s4) +flw f10, (#0, s4) +flw f10, (#1, s4) +flw f10, (#2, s4) +flw f10, (#4, s4) +flw f10, (#8, s4) +flw f10, (#0x10, s4) +flw f10, (#0x20, s4) +flw f10, (#0x40, s4) +flw f10, (#0x80, s4) +flw f10, (#0x100, s4) +flw f10, (#0x200, s4) +flw f10, (#0x400, s4) +flw f10, (#0x7ff, s4) +flw f10, (#0xfffff801, s9) +flw f10, (#0xfffffc00, s9) +flw f10, (#0xfffffe00, s9) +flw f10, (#0xffffff00, s9) +flw f10, (#0xffffff80, s9) +flw f10, (#0xffffffc0, s9) +flw f10, (#0xffffffe0, s9) +flw f10, (#0xfffffff0, s9) +flw f10, (#0xfffffff8, s9) +flw f10, (#0xfffffffc, s9) +flw f10, (#0xfffffffe, s9) +flw f10, (#0xffffffff, s9) +flw f10, (#0, s9) +flw f10, (#1, s9) +flw f10, (#2, s9) +flw f10, (#4, s9) +flw f10, (#8, s9) +flw f10, (#0x10, s9) +flw f10, (#0x20, s9) +flw f10, (#0x40, s9) +flw f10, (#0x80, s9) +flw f10, (#0x100, s9) +flw f10, (#0x200, s9) +flw f10, (#0x400, s9) +flw f10, (#0x7ff, s9) +flw f10, (#0xfffff801, t6) +flw f10, (#0xfffffc00, t6) +flw f10, (#0xfffffe00, t6) +flw f10, (#0xffffff00, t6) +flw f10, (#0xffffff80, t6) +flw f10, (#0xffffffc0, t6) +flw f10, (#0xffffffe0, t6) +flw f10, (#0xfffffff0, t6) +flw f10, (#0xfffffff8, t6) +flw f10, (#0xfffffffc, t6) +flw f10, (#0xfffffffe, t6) +flw f10, (#0xffffffff, t6) +flw f10, (#0, t6) +flw f10, (#1, t6) +flw f10, (#2, t6) +flw f10, (#4, t6) +flw f10, (#8, t6) +flw f10, (#0x10, t6) +flw f10, (#0x20, t6) +flw f10, (#0x40, t6) +flw f10, (#0x80, t6) +flw f10, (#0x100, t6) +flw f10, (#0x200, t6) +flw f10, (#0x400, t6) +flw f10, (#0x7ff, t6) +flw f15, (#0xfffff801, zero) +flw f15, (#0xfffffc00, zero) +flw f15, (#0xfffffe00, zero) +flw f15, (#0xffffff00, zero) +flw f15, (#0xffffff80, zero) +flw f15, (#0xffffffc0, zero) +flw f15, (#0xffffffe0, zero) +flw f15, (#0xfffffff0, zero) +flw f15, (#0xfffffff8, zero) +flw f15, (#0xfffffffc, zero) +flw f15, (#0xfffffffe, zero) +flw f15, (#0xffffffff, zero) +flw f15, (#0, zero) +flw f15, (#1, zero) +flw f15, (#2, zero) +flw f15, (#4, zero) +flw f15, (#8, zero) +flw f15, (#0x10, zero) +flw f15, (#0x20, zero) +flw f15, (#0x40, zero) +flw f15, (#0x80, zero) +flw f15, (#0x100, zero) +flw f15, (#0x200, zero) +flw f15, (#0x400, zero) +flw f15, (#0x7ff, zero) +flw f15, (#0xfffff801, ra) +flw f15, (#0xfffffc00, ra) +flw f15, (#0xfffffe00, ra) +flw f15, (#0xffffff00, ra) +flw f15, (#0xffffff80, ra) +flw f15, (#0xffffffc0, ra) +flw f15, (#0xffffffe0, ra) +flw f15, (#0xfffffff0, ra) +flw f15, (#0xfffffff8, ra) +flw f15, (#0xfffffffc, ra) +flw f15, (#0xfffffffe, ra) +flw f15, (#0xffffffff, ra) +flw f15, (#0, ra) +flw f15, (#1, ra) +flw f15, (#2, ra) +flw f15, (#4, ra) +flw f15, (#8, ra) +flw f15, (#0x10, ra) +flw f15, (#0x20, ra) +flw f15, (#0x40, ra) +flw f15, (#0x80, ra) +flw f15, (#0x100, ra) +flw f15, (#0x200, ra) +flw f15, (#0x400, ra) +flw f15, (#0x7ff, ra) +flw f15, (#0xfffff801, t0) +flw f15, (#0xfffffc00, t0) +flw f15, (#0xfffffe00, t0) +flw f15, (#0xffffff00, t0) +flw f15, (#0xffffff80, t0) +flw f15, (#0xffffffc0, t0) +flw f15, (#0xffffffe0, t0) +flw f15, (#0xfffffff0, t0) +flw f15, (#0xfffffff8, t0) +flw f15, (#0xfffffffc, t0) +flw f15, (#0xfffffffe, t0) +flw f15, (#0xffffffff, t0) +flw f15, (#0, t0) +flw f15, (#1, t0) +flw f15, (#2, t0) +flw f15, (#4, t0) +flw f15, (#8, t0) +flw f15, (#0x10, t0) +flw f15, (#0x20, t0) +flw f15, (#0x40, t0) +flw f15, (#0x80, t0) +flw f15, (#0x100, t0) +flw f15, (#0x200, t0) +flw f15, (#0x400, t0) +flw f15, (#0x7ff, t0) +flw f15, (#0xfffff801, a0) +flw f15, (#0xfffffc00, a0) +flw f15, (#0xfffffe00, a0) +flw f15, (#0xffffff00, a0) +flw f15, (#0xffffff80, a0) +flw f15, (#0xffffffc0, a0) +flw f15, (#0xffffffe0, a0) +flw f15, (#0xfffffff0, a0) +flw f15, (#0xfffffff8, a0) +flw f15, (#0xfffffffc, a0) +flw f15, (#0xfffffffe, a0) +flw f15, (#0xffffffff, a0) +flw f15, (#0, a0) +flw f15, (#1, a0) +flw f15, (#2, a0) +flw f15, (#4, a0) +flw f15, (#8, a0) +flw f15, (#0x10, a0) +flw f15, (#0x20, a0) +flw f15, (#0x40, a0) +flw f15, (#0x80, a0) +flw f15, (#0x100, a0) +flw f15, (#0x200, a0) +flw f15, (#0x400, a0) +flw f15, (#0x7ff, a0) +flw f15, (#0xfffff801, a5) +flw f15, (#0xfffffc00, a5) +flw f15, (#0xfffffe00, a5) +flw f15, (#0xffffff00, a5) +flw f15, (#0xffffff80, a5) +flw f15, (#0xffffffc0, a5) +flw f15, (#0xffffffe0, a5) +flw f15, (#0xfffffff0, a5) +flw f15, (#0xfffffff8, a5) +flw f15, (#0xfffffffc, a5) +flw f15, (#0xfffffffe, a5) +flw f15, (#0xffffffff, a5) +flw f15, (#0, a5) +flw f15, (#1, a5) +flw f15, (#2, a5) +flw f15, (#4, a5) +flw f15, (#8, a5) +flw f15, (#0x10, a5) +flw f15, (#0x20, a5) +flw f15, (#0x40, a5) +flw f15, (#0x80, a5) +flw f15, (#0x100, a5) +flw f15, (#0x200, a5) +flw f15, (#0x400, a5) +flw f15, (#0x7ff, a5) +flw f15, (#0xfffff801, s4) +flw f15, (#0xfffffc00, s4) +flw f15, (#0xfffffe00, s4) +flw f15, (#0xffffff00, s4) +flw f15, (#0xffffff80, s4) +flw f15, (#0xffffffc0, s4) +flw f15, (#0xffffffe0, s4) +flw f15, (#0xfffffff0, s4) +flw f15, (#0xfffffff8, s4) +flw f15, (#0xfffffffc, s4) +flw f15, (#0xfffffffe, s4) +flw f15, (#0xffffffff, s4) +flw f15, (#0, s4) +flw f15, (#1, s4) +flw f15, (#2, s4) +flw f15, (#4, s4) +flw f15, (#8, s4) +flw f15, (#0x10, s4) +flw f15, (#0x20, s4) +flw f15, (#0x40, s4) +flw f15, (#0x80, s4) +flw f15, (#0x100, s4) +flw f15, (#0x200, s4) +flw f15, (#0x400, s4) +flw f15, (#0x7ff, s4) +flw f15, (#0xfffff801, s9) +flw f15, (#0xfffffc00, s9) +flw f15, (#0xfffffe00, s9) +flw f15, (#0xffffff00, s9) +flw f15, (#0xffffff80, s9) +flw f15, (#0xffffffc0, s9) +flw f15, (#0xffffffe0, s9) +flw f15, (#0xfffffff0, s9) +flw f15, (#0xfffffff8, s9) +flw f15, (#0xfffffffc, s9) +flw f15, (#0xfffffffe, s9) +flw f15, (#0xffffffff, s9) +flw f15, (#0, s9) +flw f15, (#1, s9) +flw f15, (#2, s9) +flw f15, (#4, s9) +flw f15, (#8, s9) +flw f15, (#0x10, s9) +flw f15, (#0x20, s9) +flw f15, (#0x40, s9) +flw f15, (#0x80, s9) +flw f15, (#0x100, s9) +flw f15, (#0x200, s9) +flw f15, (#0x400, s9) +flw f15, (#0x7ff, s9) +flw f15, (#0xfffff801, t6) +flw f15, (#0xfffffc00, t6) +flw f15, (#0xfffffe00, t6) +flw f15, (#0xffffff00, t6) +flw f15, (#0xffffff80, t6) +flw f15, (#0xffffffc0, t6) +flw f15, (#0xffffffe0, t6) +flw f15, (#0xfffffff0, t6) +flw f15, (#0xfffffff8, t6) +flw f15, (#0xfffffffc, t6) +flw f15, (#0xfffffffe, t6) +flw f15, (#0xffffffff, t6) +flw f15, (#0, t6) +flw f15, (#1, t6) +flw f15, (#2, t6) +flw f15, (#4, t6) +flw f15, (#8, t6) +flw f15, (#0x10, t6) +flw f15, (#0x20, t6) +flw f15, (#0x40, t6) +flw f15, (#0x80, t6) +flw f15, (#0x100, t6) +flw f15, (#0x200, t6) +flw f15, (#0x400, t6) +flw f15, (#0x7ff, t6) +flw f20, (#0xfffff801, zero) +flw f20, (#0xfffffc00, zero) +flw f20, (#0xfffffe00, zero) +flw f20, (#0xffffff00, zero) +flw f20, (#0xffffff80, zero) +flw f20, (#0xffffffc0, zero) +flw f20, (#0xffffffe0, zero) +flw f20, (#0xfffffff0, zero) +flw f20, (#0xfffffff8, zero) +flw f20, (#0xfffffffc, zero) +flw f20, (#0xfffffffe, zero) +flw f20, (#0xffffffff, zero) +flw f20, (#0, zero) +flw f20, (#1, zero) +flw f20, (#2, zero) +flw f20, (#4, zero) +flw f20, (#8, zero) +flw f20, (#0x10, zero) +flw f20, (#0x20, zero) +flw f20, (#0x40, zero) +flw f20, (#0x80, zero) +flw f20, (#0x100, zero) +flw f20, (#0x200, zero) +flw f20, (#0x400, zero) +flw f20, (#0x7ff, zero) +flw f20, (#0xfffff801, ra) +flw f20, (#0xfffffc00, ra) +flw f20, (#0xfffffe00, ra) +flw f20, (#0xffffff00, ra) +flw f20, (#0xffffff80, ra) +flw f20, (#0xffffffc0, ra) +flw f20, (#0xffffffe0, ra) +flw f20, (#0xfffffff0, ra) +flw f20, (#0xfffffff8, ra) +flw f20, (#0xfffffffc, ra) +flw f20, (#0xfffffffe, ra) +flw f20, (#0xffffffff, ra) +flw f20, (#0, ra) +flw f20, (#1, ra) +flw f20, (#2, ra) +flw f20, (#4, ra) +flw f20, (#8, ra) +flw f20, (#0x10, ra) +flw f20, (#0x20, ra) +flw f20, (#0x40, ra) +flw f20, (#0x80, ra) +flw f20, (#0x100, ra) +flw f20, (#0x200, ra) +flw f20, (#0x400, ra) +flw f20, (#0x7ff, ra) +flw f20, (#0xfffff801, t0) +flw f20, (#0xfffffc00, t0) +flw f20, (#0xfffffe00, t0) +flw f20, (#0xffffff00, t0) +flw f20, (#0xffffff80, t0) +flw f20, (#0xffffffc0, t0) +flw f20, (#0xffffffe0, t0) +flw f20, (#0xfffffff0, t0) +flw f20, (#0xfffffff8, t0) +flw f20, (#0xfffffffc, t0) +flw f20, (#0xfffffffe, t0) +flw f20, (#0xffffffff, t0) +flw f20, (#0, t0) +flw f20, (#1, t0) +flw f20, (#2, t0) +flw f20, (#4, t0) +flw f20, (#8, t0) +flw f20, (#0x10, t0) +flw f20, (#0x20, t0) +flw f20, (#0x40, t0) +flw f20, (#0x80, t0) +flw f20, (#0x100, t0) +flw f20, (#0x200, t0) +flw f20, (#0x400, t0) +flw f20, (#0x7ff, t0) +flw f20, (#0xfffff801, a0) +flw f20, (#0xfffffc00, a0) +flw f20, (#0xfffffe00, a0) +flw f20, (#0xffffff00, a0) +flw f20, (#0xffffff80, a0) +flw f20, (#0xffffffc0, a0) +flw f20, (#0xffffffe0, a0) +flw f20, (#0xfffffff0, a0) +flw f20, (#0xfffffff8, a0) +flw f20, (#0xfffffffc, a0) +flw f20, (#0xfffffffe, a0) +flw f20, (#0xffffffff, a0) +flw f20, (#0, a0) +flw f20, (#1, a0) +flw f20, (#2, a0) +flw f20, (#4, a0) +flw f20, (#8, a0) +flw f20, (#0x10, a0) +flw f20, (#0x20, a0) +flw f20, (#0x40, a0) +flw f20, (#0x80, a0) +flw f20, (#0x100, a0) +flw f20, (#0x200, a0) +flw f20, (#0x400, a0) +flw f20, (#0x7ff, a0) +flw f20, (#0xfffff801, a5) +flw f20, (#0xfffffc00, a5) +flw f20, (#0xfffffe00, a5) +flw f20, (#0xffffff00, a5) +flw f20, (#0xffffff80, a5) +flw f20, (#0xffffffc0, a5) +flw f20, (#0xffffffe0, a5) +flw f20, (#0xfffffff0, a5) +flw f20, (#0xfffffff8, a5) +flw f20, (#0xfffffffc, a5) +flw f20, (#0xfffffffe, a5) +flw f20, (#0xffffffff, a5) +flw f20, (#0, a5) +flw f20, (#1, a5) +flw f20, (#2, a5) +flw f20, (#4, a5) +flw f20, (#8, a5) +flw f20, (#0x10, a5) +flw f20, (#0x20, a5) +flw f20, (#0x40, a5) +flw f20, (#0x80, a5) +flw f20, (#0x100, a5) +flw f20, (#0x200, a5) +flw f20, (#0x400, a5) +flw f20, (#0x7ff, a5) +flw f20, (#0xfffff801, s4) +flw f20, (#0xfffffc00, s4) +flw f20, (#0xfffffe00, s4) +flw f20, (#0xffffff00, s4) +flw f20, (#0xffffff80, s4) +flw f20, (#0xffffffc0, s4) +flw f20, (#0xffffffe0, s4) +flw f20, (#0xfffffff0, s4) +flw f20, (#0xfffffff8, s4) +flw f20, (#0xfffffffc, s4) +flw f20, (#0xfffffffe, s4) +flw f20, (#0xffffffff, s4) +flw f20, (#0, s4) +flw f20, (#1, s4) +flw f20, (#2, s4) +flw f20, (#4, s4) +flw f20, (#8, s4) +flw f20, (#0x10, s4) +flw f20, (#0x20, s4) +flw f20, (#0x40, s4) +flw f20, (#0x80, s4) +flw f20, (#0x100, s4) +flw f20, (#0x200, s4) +flw f20, (#0x400, s4) +flw f20, (#0x7ff, s4) +flw f20, (#0xfffff801, s9) +flw f20, (#0xfffffc00, s9) +flw f20, (#0xfffffe00, s9) +flw f20, (#0xffffff00, s9) +flw f20, (#0xffffff80, s9) +flw f20, (#0xffffffc0, s9) +flw f20, (#0xffffffe0, s9) +flw f20, (#0xfffffff0, s9) +flw f20, (#0xfffffff8, s9) +flw f20, (#0xfffffffc, s9) +flw f20, (#0xfffffffe, s9) +flw f20, (#0xffffffff, s9) +flw f20, (#0, s9) +flw f20, (#1, s9) +flw f20, (#2, s9) +flw f20, (#4, s9) +flw f20, (#8, s9) +flw f20, (#0x10, s9) +flw f20, (#0x20, s9) +flw f20, (#0x40, s9) +flw f20, (#0x80, s9) +flw f20, (#0x100, s9) +flw f20, (#0x200, s9) +flw f20, (#0x400, s9) +flw f20, (#0x7ff, s9) +flw f20, (#0xfffff801, t6) +flw f20, (#0xfffffc00, t6) +flw f20, (#0xfffffe00, t6) +flw f20, (#0xffffff00, t6) +flw f20, (#0xffffff80, t6) +flw f20, (#0xffffffc0, t6) +flw f20, (#0xffffffe0, t6) +flw f20, (#0xfffffff0, t6) +flw f20, (#0xfffffff8, t6) +flw f20, (#0xfffffffc, t6) +flw f20, (#0xfffffffe, t6) +flw f20, (#0xffffffff, t6) +flw f20, (#0, t6) +flw f20, (#1, t6) +flw f20, (#2, t6) +flw f20, (#4, t6) +flw f20, (#8, t6) +flw f20, (#0x10, t6) +flw f20, (#0x20, t6) +flw f20, (#0x40, t6) +flw f20, (#0x80, t6) +flw f20, (#0x100, t6) +flw f20, (#0x200, t6) +flw f20, (#0x400, t6) +flw f20, (#0x7ff, t6) +flw f25, (#0xfffff801, zero) +flw f25, (#0xfffffc00, zero) +flw f25, (#0xfffffe00, zero) +flw f25, (#0xffffff00, zero) +flw f25, (#0xffffff80, zero) +flw f25, (#0xffffffc0, zero) +flw f25, (#0xffffffe0, zero) +flw f25, (#0xfffffff0, zero) +flw f25, (#0xfffffff8, zero) +flw f25, (#0xfffffffc, zero) +flw f25, (#0xfffffffe, zero) +flw f25, (#0xffffffff, zero) +flw f25, (#0, zero) +flw f25, (#1, zero) +flw f25, (#2, zero) +flw f25, (#4, zero) +flw f25, (#8, zero) +flw f25, (#0x10, zero) +flw f25, (#0x20, zero) +flw f25, (#0x40, zero) +flw f25, (#0x80, zero) +flw f25, (#0x100, zero) +flw f25, (#0x200, zero) +flw f25, (#0x400, zero) +flw f25, (#0x7ff, zero) +flw f25, (#0xfffff801, ra) +flw f25, (#0xfffffc00, ra) +flw f25, (#0xfffffe00, ra) +flw f25, (#0xffffff00, ra) +flw f25, (#0xffffff80, ra) +flw f25, (#0xffffffc0, ra) +flw f25, (#0xffffffe0, ra) +flw f25, (#0xfffffff0, ra) +flw f25, (#0xfffffff8, ra) +flw f25, (#0xfffffffc, ra) +flw f25, (#0xfffffffe, ra) +flw f25, (#0xffffffff, ra) +flw f25, (#0, ra) +flw f25, (#1, ra) +flw f25, (#2, ra) +flw f25, (#4, ra) +flw f25, (#8, ra) +flw f25, (#0x10, ra) +flw f25, (#0x20, ra) +flw f25, (#0x40, ra) +flw f25, (#0x80, ra) +flw f25, (#0x100, ra) +flw f25, (#0x200, ra) +flw f25, (#0x400, ra) +flw f25, (#0x7ff, ra) +flw f25, (#0xfffff801, t0) +flw f25, (#0xfffffc00, t0) +flw f25, (#0xfffffe00, t0) +flw f25, (#0xffffff00, t0) +flw f25, (#0xffffff80, t0) +flw f25, (#0xffffffc0, t0) +flw f25, (#0xffffffe0, t0) +flw f25, (#0xfffffff0, t0) +flw f25, (#0xfffffff8, t0) +flw f25, (#0xfffffffc, t0) +flw f25, (#0xfffffffe, t0) +flw f25, (#0xffffffff, t0) +flw f25, (#0, t0) +flw f25, (#1, t0) +flw f25, (#2, t0) +flw f25, (#4, t0) +flw f25, (#8, t0) +flw f25, (#0x10, t0) +flw f25, (#0x20, t0) +flw f25, (#0x40, t0) +flw f25, (#0x80, t0) +flw f25, (#0x100, t0) +flw f25, (#0x200, t0) +flw f25, (#0x400, t0) +flw f25, (#0x7ff, t0) +flw f25, (#0xfffff801, a0) +flw f25, (#0xfffffc00, a0) +flw f25, (#0xfffffe00, a0) +flw f25, (#0xffffff00, a0) +flw f25, (#0xffffff80, a0) +flw f25, (#0xffffffc0, a0) +flw f25, (#0xffffffe0, a0) +flw f25, (#0xfffffff0, a0) +flw f25, (#0xfffffff8, a0) +flw f25, (#0xfffffffc, a0) +flw f25, (#0xfffffffe, a0) +flw f25, (#0xffffffff, a0) +flw f25, (#0, a0) +flw f25, (#1, a0) +flw f25, (#2, a0) +flw f25, (#4, a0) +flw f25, (#8, a0) +flw f25, (#0x10, a0) +flw f25, (#0x20, a0) +flw f25, (#0x40, a0) +flw f25, (#0x80, a0) +flw f25, (#0x100, a0) +flw f25, (#0x200, a0) +flw f25, (#0x400, a0) +flw f25, (#0x7ff, a0) +flw f25, (#0xfffff801, a5) +flw f25, (#0xfffffc00, a5) +flw f25, (#0xfffffe00, a5) +flw f25, (#0xffffff00, a5) +flw f25, (#0xffffff80, a5) +flw f25, (#0xffffffc0, a5) +flw f25, (#0xffffffe0, a5) +flw f25, (#0xfffffff0, a5) +flw f25, (#0xfffffff8, a5) +flw f25, (#0xfffffffc, a5) +flw f25, (#0xfffffffe, a5) +flw f25, (#0xffffffff, a5) +flw f25, (#0, a5) +flw f25, (#1, a5) +flw f25, (#2, a5) +flw f25, (#4, a5) +flw f25, (#8, a5) +flw f25, (#0x10, a5) +flw f25, (#0x20, a5) +flw f25, (#0x40, a5) +flw f25, (#0x80, a5) +flw f25, (#0x100, a5) +flw f25, (#0x200, a5) +flw f25, (#0x400, a5) +flw f25, (#0x7ff, a5) +flw f25, (#0xfffff801, s4) +flw f25, (#0xfffffc00, s4) +flw f25, (#0xfffffe00, s4) +flw f25, (#0xffffff00, s4) +flw f25, (#0xffffff80, s4) +flw f25, (#0xffffffc0, s4) +flw f25, (#0xffffffe0, s4) +flw f25, (#0xfffffff0, s4) +flw f25, (#0xfffffff8, s4) +flw f25, (#0xfffffffc, s4) +flw f25, (#0xfffffffe, s4) +flw f25, (#0xffffffff, s4) +flw f25, (#0, s4) +flw f25, (#1, s4) +flw f25, (#2, s4) +flw f25, (#4, s4) +flw f25, (#8, s4) +flw f25, (#0x10, s4) +flw f25, (#0x20, s4) +flw f25, (#0x40, s4) +flw f25, (#0x80, s4) +flw f25, (#0x100, s4) +flw f25, (#0x200, s4) +flw f25, (#0x400, s4) +flw f25, (#0x7ff, s4) +flw f25, (#0xfffff801, s9) +flw f25, (#0xfffffc00, s9) +flw f25, (#0xfffffe00, s9) +flw f25, (#0xffffff00, s9) +flw f25, (#0xffffff80, s9) +flw f25, (#0xffffffc0, s9) +flw f25, (#0xffffffe0, s9) +flw f25, (#0xfffffff0, s9) +flw f25, (#0xfffffff8, s9) +flw f25, (#0xfffffffc, s9) +flw f25, (#0xfffffffe, s9) +flw f25, (#0xffffffff, s9) +flw f25, (#0, s9) +flw f25, (#1, s9) +flw f25, (#2, s9) +flw f25, (#4, s9) +flw f25, (#8, s9) +flw f25, (#0x10, s9) +flw f25, (#0x20, s9) +flw f25, (#0x40, s9) +flw f25, (#0x80, s9) +flw f25, (#0x100, s9) +flw f25, (#0x200, s9) +flw f25, (#0x400, s9) +flw f25, (#0x7ff, s9) +flw f25, (#0xfffff801, t6) +flw f25, (#0xfffffc00, t6) +flw f25, (#0xfffffe00, t6) +flw f25, (#0xffffff00, t6) +flw f25, (#0xffffff80, t6) +flw f25, (#0xffffffc0, t6) +flw f25, (#0xffffffe0, t6) +flw f25, (#0xfffffff0, t6) +flw f25, (#0xfffffff8, t6) +flw f25, (#0xfffffffc, t6) +flw f25, (#0xfffffffe, t6) +flw f25, (#0xffffffff, t6) +flw f25, (#0, t6) +flw f25, (#1, t6) +flw f25, (#2, t6) +flw f25, (#4, t6) +flw f25, (#8, t6) +flw f25, (#0x10, t6) +flw f25, (#0x20, t6) +flw f25, (#0x40, t6) +flw f25, (#0x80, t6) +flw f25, (#0x100, t6) +flw f25, (#0x200, t6) +flw f25, (#0x400, t6) +flw f25, (#0x7ff, t6) +flw f31, (#0xfffff801, zero) +flw f31, (#0xfffffc00, zero) +flw f31, (#0xfffffe00, zero) +flw f31, (#0xffffff00, zero) +flw f31, (#0xffffff80, zero) +flw f31, (#0xffffffc0, zero) +flw f31, (#0xffffffe0, zero) +flw f31, (#0xfffffff0, zero) +flw f31, (#0xfffffff8, zero) +flw f31, (#0xfffffffc, zero) +flw f31, (#0xfffffffe, zero) +flw f31, (#0xffffffff, zero) +flw f31, (#0, zero) +flw f31, (#1, zero) +flw f31, (#2, zero) +flw f31, (#4, zero) +flw f31, (#8, zero) +flw f31, (#0x10, zero) +flw f31, (#0x20, zero) +flw f31, (#0x40, zero) +flw f31, (#0x80, zero) +flw f31, (#0x100, zero) +flw f31, (#0x200, zero) +flw f31, (#0x400, zero) +flw f31, (#0x7ff, zero) +flw f31, (#0xfffff801, ra) +flw f31, (#0xfffffc00, ra) +flw f31, (#0xfffffe00, ra) +flw f31, (#0xffffff00, ra) +flw f31, (#0xffffff80, ra) +flw f31, (#0xffffffc0, ra) +flw f31, (#0xffffffe0, ra) +flw f31, (#0xfffffff0, ra) +flw f31, (#0xfffffff8, ra) +flw f31, (#0xfffffffc, ra) +flw f31, (#0xfffffffe, ra) +flw f31, (#0xffffffff, ra) +flw f31, (#0, ra) +flw f31, (#1, ra) +flw f31, (#2, ra) +flw f31, (#4, ra) +flw f31, (#8, ra) +flw f31, (#0x10, ra) +flw f31, (#0x20, ra) +flw f31, (#0x40, ra) +flw f31, (#0x80, ra) +flw f31, (#0x100, ra) +flw f31, (#0x200, ra) +flw f31, (#0x400, ra) +flw f31, (#0x7ff, ra) +flw f31, (#0xfffff801, t0) +flw f31, (#0xfffffc00, t0) +flw f31, (#0xfffffe00, t0) +flw f31, (#0xffffff00, t0) +flw f31, (#0xffffff80, t0) +flw f31, (#0xffffffc0, t0) +flw f31, (#0xffffffe0, t0) +flw f31, (#0xfffffff0, t0) +flw f31, (#0xfffffff8, t0) +flw f31, (#0xfffffffc, t0) +flw f31, (#0xfffffffe, t0) +flw f31, (#0xffffffff, t0) +flw f31, (#0, t0) +flw f31, (#1, t0) +flw f31, (#2, t0) +flw f31, (#4, t0) +flw f31, (#8, t0) +flw f31, (#0x10, t0) +flw f31, (#0x20, t0) +flw f31, (#0x40, t0) +flw f31, (#0x80, t0) +flw f31, (#0x100, t0) +flw f31, (#0x200, t0) +flw f31, (#0x400, t0) +flw f31, (#0x7ff, t0) +flw f31, (#0xfffff801, a0) +flw f31, (#0xfffffc00, a0) +flw f31, (#0xfffffe00, a0) +flw f31, (#0xffffff00, a0) +flw f31, (#0xffffff80, a0) +flw f31, (#0xffffffc0, a0) +flw f31, (#0xffffffe0, a0) +flw f31, (#0xfffffff0, a0) +flw f31, (#0xfffffff8, a0) +flw f31, (#0xfffffffc, a0) +flw f31, (#0xfffffffe, a0) +flw f31, (#0xffffffff, a0) +flw f31, (#0, a0) +flw f31, (#1, a0) +flw f31, (#2, a0) +flw f31, (#4, a0) +flw f31, (#8, a0) +flw f31, (#0x10, a0) +flw f31, (#0x20, a0) +flw f31, (#0x40, a0) +flw f31, (#0x80, a0) +flw f31, (#0x100, a0) +flw f31, (#0x200, a0) +flw f31, (#0x400, a0) +flw f31, (#0x7ff, a0) +flw f31, (#0xfffff801, a5) +flw f31, (#0xfffffc00, a5) +flw f31, (#0xfffffe00, a5) +flw f31, (#0xffffff00, a5) +flw f31, (#0xffffff80, a5) +flw f31, (#0xffffffc0, a5) +flw f31, (#0xffffffe0, a5) +flw f31, (#0xfffffff0, a5) +flw f31, (#0xfffffff8, a5) +flw f31, (#0xfffffffc, a5) +flw f31, (#0xfffffffe, a5) +flw f31, (#0xffffffff, a5) +flw f31, (#0, a5) +flw f31, (#1, a5) +flw f31, (#2, a5) +flw f31, (#4, a5) +flw f31, (#8, a5) +flw f31, (#0x10, a5) +flw f31, (#0x20, a5) +flw f31, (#0x40, a5) +flw f31, (#0x80, a5) +flw f31, (#0x100, a5) +flw f31, (#0x200, a5) +flw f31, (#0x400, a5) +flw f31, (#0x7ff, a5) +flw f31, (#0xfffff801, s4) +flw f31, (#0xfffffc00, s4) +flw f31, (#0xfffffe00, s4) +flw f31, (#0xffffff00, s4) +flw f31, (#0xffffff80, s4) +flw f31, (#0xffffffc0, s4) +flw f31, (#0xffffffe0, s4) +flw f31, (#0xfffffff0, s4) +flw f31, (#0xfffffff8, s4) +flw f31, (#0xfffffffc, s4) +flw f31, (#0xfffffffe, s4) +flw f31, (#0xffffffff, s4) +flw f31, (#0, s4) +flw f31, (#1, s4) +flw f31, (#2, s4) +flw f31, (#4, s4) +flw f31, (#8, s4) +flw f31, (#0x10, s4) +flw f31, (#0x20, s4) +flw f31, (#0x40, s4) +flw f31, (#0x80, s4) +flw f31, (#0x100, s4) +flw f31, (#0x200, s4) +flw f31, (#0x400, s4) +flw f31, (#0x7ff, s4) +flw f31, (#0xfffff801, s9) +flw f31, (#0xfffffc00, s9) +flw f31, (#0xfffffe00, s9) +flw f31, (#0xffffff00, s9) +flw f31, (#0xffffff80, s9) +flw f31, (#0xffffffc0, s9) +flw f31, (#0xffffffe0, s9) +flw f31, (#0xfffffff0, s9) +flw f31, (#0xfffffff8, s9) +flw f31, (#0xfffffffc, s9) +flw f31, (#0xfffffffe, s9) +flw f31, (#0xffffffff, s9) +flw f31, (#0, s9) +flw f31, (#1, s9) +flw f31, (#2, s9) +flw f31, (#4, s9) +flw f31, (#8, s9) +flw f31, (#0x10, s9) +flw f31, (#0x20, s9) +flw f31, (#0x40, s9) +flw f31, (#0x80, s9) +flw f31, (#0x100, s9) +flw f31, (#0x200, s9) +flw f31, (#0x400, s9) +flw f31, (#0x7ff, s9) +flw f31, (#0xfffff801, t6) +flw f31, (#0xfffffc00, t6) +flw f31, (#0xfffffe00, t6) +flw f31, (#0xffffff00, t6) +flw f31, (#0xffffff80, t6) +flw f31, (#0xffffffc0, t6) +flw f31, (#0xffffffe0, t6) +flw f31, (#0xfffffff0, t6) +flw f31, (#0xfffffff8, t6) +flw f31, (#0xfffffffc, t6) +flw f31, (#0xfffffffe, t6) +flw f31, (#0xffffffff, t6) +flw f31, (#0, t6) +flw f31, (#1, t6) +flw f31, (#2, t6) +flw f31, (#4, t6) +flw f31, (#8, t6) +flw f31, (#0x10, t6) +flw f31, (#0x20, t6) +flw f31, (#0x40, t6) +flw f31, (#0x80, t6) +flw f31, (#0x100, t6) +flw f31, (#0x200, t6) +flw f31, (#0x400, t6) +flw f31, (#0x7ff, t6) diff --git a/tests/riscv/f-extension/fmadd.s.asm b/tests/riscv/f-extension/fmadd.s.asm new file mode 100644 index 0000000..1dbb2e7 --- /dev/null +++ b/tests/riscv/f-extension/fmadd.s.asm @@ -0,0 +1,4100 @@ +.lang riscv32 +.org 0x0 + +fmadd.s f0, f0, f0, f0 +fmadd.s f0, f0, f0, f1 +fmadd.s f0, f0, f0, f5 +fmadd.s f0, f0, f0, f10 +fmadd.s f0, f0, f0, f15 +fmadd.s f0, f0, f0, f20 +fmadd.s f0, f0, f0, f25 +fmadd.s f0, f0, f0, f31 +fmadd.s f0, f0, f1, f0 +fmadd.s f0, f0, f1, f1 +fmadd.s f0, f0, f1, f5 +fmadd.s f0, f0, f1, f10 +fmadd.s f0, f0, f1, f15 +fmadd.s f0, f0, f1, f20 +fmadd.s f0, f0, f1, f25 +fmadd.s f0, f0, f1, f31 +fmadd.s f0, f0, f5, f0 +fmadd.s f0, f0, f5, f1 +fmadd.s f0, f0, f5, f5 +fmadd.s f0, f0, f5, f10 +fmadd.s f0, f0, f5, f15 +fmadd.s f0, f0, f5, f20 +fmadd.s f0, f0, f5, f25 +fmadd.s f0, f0, f5, f31 +fmadd.s f0, f0, f10, f0 +fmadd.s f0, f0, f10, f1 +fmadd.s f0, f0, f10, f5 +fmadd.s f0, f0, f10, f10 +fmadd.s f0, f0, f10, f15 +fmadd.s f0, f0, f10, f20 +fmadd.s f0, f0, f10, f25 +fmadd.s f0, f0, f10, f31 +fmadd.s f0, f0, f15, f0 +fmadd.s f0, f0, f15, f1 +fmadd.s f0, f0, f15, f5 +fmadd.s f0, f0, f15, f10 +fmadd.s f0, f0, f15, f15 +fmadd.s f0, f0, f15, f20 +fmadd.s f0, f0, f15, f25 +fmadd.s f0, f0, f15, f31 +fmadd.s f0, f0, f20, f0 +fmadd.s f0, f0, f20, f1 +fmadd.s f0, f0, f20, f5 +fmadd.s f0, f0, f20, f10 +fmadd.s f0, f0, f20, f15 +fmadd.s f0, f0, f20, f20 +fmadd.s f0, f0, f20, f25 +fmadd.s f0, f0, f20, f31 +fmadd.s f0, f0, f25, f0 +fmadd.s f0, f0, f25, f1 +fmadd.s f0, f0, f25, f5 +fmadd.s f0, f0, f25, f10 +fmadd.s f0, f0, f25, f15 +fmadd.s f0, f0, f25, f20 +fmadd.s f0, f0, f25, f25 +fmadd.s f0, f0, f25, f31 +fmadd.s f0, f0, f31, f0 +fmadd.s f0, f0, f31, f1 +fmadd.s f0, f0, f31, f5 +fmadd.s f0, f0, f31, f10 +fmadd.s f0, f0, f31, f15 +fmadd.s f0, f0, f31, f20 +fmadd.s f0, f0, f31, f25 +fmadd.s f0, f0, f31, f31 +fmadd.s f0, f1, f0, f0 +fmadd.s f0, f1, f0, f1 +fmadd.s f0, f1, f0, f5 +fmadd.s f0, f1, f0, f10 +fmadd.s f0, f1, f0, f15 +fmadd.s f0, f1, f0, f20 +fmadd.s f0, f1, f0, f25 +fmadd.s f0, f1, f0, f31 +fmadd.s f0, f1, f1, f0 +fmadd.s f0, f1, f1, f1 +fmadd.s f0, f1, f1, f5 +fmadd.s f0, f1, f1, f10 +fmadd.s f0, f1, f1, f15 +fmadd.s f0, f1, f1, f20 +fmadd.s f0, f1, f1, f25 +fmadd.s f0, f1, f1, f31 +fmadd.s f0, f1, f5, f0 +fmadd.s f0, f1, f5, f1 +fmadd.s f0, f1, f5, f5 +fmadd.s f0, f1, f5, f10 +fmadd.s f0, f1, f5, f15 +fmadd.s f0, f1, f5, f20 +fmadd.s f0, f1, f5, f25 +fmadd.s f0, f1, f5, f31 +fmadd.s f0, f1, f10, f0 +fmadd.s f0, f1, f10, f1 +fmadd.s f0, f1, f10, f5 +fmadd.s f0, f1, f10, f10 +fmadd.s f0, f1, f10, f15 +fmadd.s f0, f1, f10, f20 +fmadd.s f0, f1, f10, f25 +fmadd.s f0, f1, f10, f31 +fmadd.s f0, f1, f15, f0 +fmadd.s f0, f1, f15, f1 +fmadd.s f0, f1, f15, f5 +fmadd.s f0, f1, f15, f10 +fmadd.s f0, f1, f15, f15 +fmadd.s f0, f1, f15, f20 +fmadd.s f0, f1, f15, f25 +fmadd.s f0, f1, f15, f31 +fmadd.s f0, f1, f20, f0 +fmadd.s f0, f1, f20, f1 +fmadd.s f0, f1, f20, f5 +fmadd.s f0, f1, f20, f10 +fmadd.s f0, f1, f20, f15 +fmadd.s f0, f1, f20, f20 +fmadd.s f0, f1, f20, f25 +fmadd.s f0, f1, f20, f31 +fmadd.s f0, f1, f25, f0 +fmadd.s f0, f1, f25, f1 +fmadd.s f0, f1, f25, f5 +fmadd.s f0, f1, f25, f10 +fmadd.s f0, f1, f25, f15 +fmadd.s f0, f1, f25, f20 +fmadd.s f0, f1, f25, f25 +fmadd.s f0, f1, f25, f31 +fmadd.s f0, f1, f31, f0 +fmadd.s f0, f1, f31, f1 +fmadd.s f0, f1, f31, f5 +fmadd.s f0, f1, f31, f10 +fmadd.s f0, f1, f31, f15 +fmadd.s f0, f1, f31, f20 +fmadd.s f0, f1, f31, f25 +fmadd.s f0, f1, f31, f31 +fmadd.s f0, f5, f0, f0 +fmadd.s f0, f5, f0, f1 +fmadd.s f0, f5, f0, f5 +fmadd.s f0, f5, f0, f10 +fmadd.s f0, f5, f0, f15 +fmadd.s f0, f5, f0, f20 +fmadd.s f0, f5, f0, f25 +fmadd.s f0, f5, f0, f31 +fmadd.s f0, f5, f1, f0 +fmadd.s f0, f5, f1, f1 +fmadd.s f0, f5, f1, f5 +fmadd.s f0, f5, f1, f10 +fmadd.s f0, f5, f1, f15 +fmadd.s f0, f5, f1, f20 +fmadd.s f0, f5, f1, f25 +fmadd.s f0, f5, f1, f31 +fmadd.s f0, f5, f5, f0 +fmadd.s f0, f5, f5, f1 +fmadd.s f0, f5, f5, f5 +fmadd.s f0, f5, f5, f10 +fmadd.s f0, f5, f5, f15 +fmadd.s f0, f5, f5, f20 +fmadd.s f0, f5, f5, f25 +fmadd.s f0, f5, f5, f31 +fmadd.s f0, f5, f10, f0 +fmadd.s f0, f5, f10, f1 +fmadd.s f0, f5, f10, f5 +fmadd.s f0, f5, f10, f10 +fmadd.s f0, f5, f10, f15 +fmadd.s f0, f5, f10, f20 +fmadd.s f0, f5, f10, f25 +fmadd.s f0, f5, f10, f31 +fmadd.s f0, f5, f15, f0 +fmadd.s f0, f5, f15, f1 +fmadd.s f0, f5, f15, f5 +fmadd.s f0, f5, f15, f10 +fmadd.s f0, f5, f15, f15 +fmadd.s f0, f5, f15, f20 +fmadd.s f0, f5, f15, f25 +fmadd.s f0, f5, f15, f31 +fmadd.s f0, f5, f20, f0 +fmadd.s f0, f5, f20, f1 +fmadd.s f0, f5, f20, f5 +fmadd.s f0, f5, f20, f10 +fmadd.s f0, f5, f20, f15 +fmadd.s f0, f5, f20, f20 +fmadd.s f0, f5, f20, f25 +fmadd.s f0, f5, f20, f31 +fmadd.s f0, f5, f25, f0 +fmadd.s f0, f5, f25, f1 +fmadd.s f0, f5, f25, f5 +fmadd.s f0, f5, f25, f10 +fmadd.s f0, f5, f25, f15 +fmadd.s f0, f5, f25, f20 +fmadd.s f0, f5, f25, f25 +fmadd.s f0, f5, f25, f31 +fmadd.s f0, f5, f31, f0 +fmadd.s f0, f5, f31, f1 +fmadd.s f0, f5, f31, f5 +fmadd.s f0, f5, f31, f10 +fmadd.s f0, f5, f31, f15 +fmadd.s f0, f5, f31, f20 +fmadd.s f0, f5, f31, f25 +fmadd.s f0, f5, f31, f31 +fmadd.s f0, f10, f0, f0 +fmadd.s f0, f10, f0, f1 +fmadd.s f0, f10, f0, f5 +fmadd.s f0, f10, f0, f10 +fmadd.s f0, f10, f0, f15 +fmadd.s f0, f10, f0, f20 +fmadd.s f0, f10, f0, f25 +fmadd.s f0, f10, f0, f31 +fmadd.s f0, f10, f1, f0 +fmadd.s f0, f10, f1, f1 +fmadd.s f0, f10, f1, f5 +fmadd.s f0, f10, f1, f10 +fmadd.s f0, f10, f1, f15 +fmadd.s f0, f10, f1, f20 +fmadd.s f0, f10, f1, f25 +fmadd.s f0, f10, f1, f31 +fmadd.s f0, f10, f5, f0 +fmadd.s f0, f10, f5, f1 +fmadd.s f0, f10, f5, f5 +fmadd.s f0, f10, f5, f10 +fmadd.s f0, f10, f5, f15 +fmadd.s f0, f10, f5, f20 +fmadd.s f0, f10, f5, f25 +fmadd.s f0, f10, f5, f31 +fmadd.s f0, f10, f10, f0 +fmadd.s f0, f10, f10, f1 +fmadd.s f0, f10, f10, f5 +fmadd.s f0, f10, f10, f10 +fmadd.s f0, f10, f10, f15 +fmadd.s f0, f10, f10, f20 +fmadd.s f0, f10, f10, f25 +fmadd.s f0, f10, f10, f31 +fmadd.s f0, f10, f15, f0 +fmadd.s f0, f10, f15, f1 +fmadd.s f0, f10, f15, f5 +fmadd.s f0, f10, f15, f10 +fmadd.s f0, f10, f15, f15 +fmadd.s f0, f10, f15, f20 +fmadd.s f0, f10, f15, f25 +fmadd.s f0, f10, f15, f31 +fmadd.s f0, f10, f20, f0 +fmadd.s f0, f10, f20, f1 +fmadd.s f0, f10, f20, f5 +fmadd.s f0, f10, f20, f10 +fmadd.s f0, f10, f20, f15 +fmadd.s f0, f10, f20, f20 +fmadd.s f0, f10, f20, f25 +fmadd.s f0, f10, f20, f31 +fmadd.s f0, f10, f25, f0 +fmadd.s f0, f10, f25, f1 +fmadd.s f0, f10, f25, f5 +fmadd.s f0, f10, f25, f10 +fmadd.s f0, f10, f25, f15 +fmadd.s f0, f10, f25, f20 +fmadd.s f0, f10, f25, f25 +fmadd.s f0, f10, f25, f31 +fmadd.s f0, f10, f31, f0 +fmadd.s f0, f10, f31, f1 +fmadd.s f0, f10, f31, f5 +fmadd.s f0, f10, f31, f10 +fmadd.s f0, f10, f31, f15 +fmadd.s f0, f10, f31, f20 +fmadd.s f0, f10, f31, f25 +fmadd.s f0, f10, f31, f31 +fmadd.s f0, f15, f0, f0 +fmadd.s f0, f15, f0, f1 +fmadd.s f0, f15, f0, f5 +fmadd.s f0, f15, f0, f10 +fmadd.s f0, f15, f0, f15 +fmadd.s f0, f15, f0, f20 +fmadd.s f0, f15, f0, f25 +fmadd.s f0, f15, f0, f31 +fmadd.s f0, f15, f1, f0 +fmadd.s f0, f15, f1, f1 +fmadd.s f0, f15, f1, f5 +fmadd.s f0, f15, f1, f10 +fmadd.s f0, f15, f1, f15 +fmadd.s f0, f15, f1, f20 +fmadd.s f0, f15, f1, f25 +fmadd.s f0, f15, f1, f31 +fmadd.s f0, f15, f5, f0 +fmadd.s f0, f15, f5, f1 +fmadd.s f0, f15, f5, f5 +fmadd.s f0, f15, f5, f10 +fmadd.s f0, f15, f5, f15 +fmadd.s f0, f15, f5, f20 +fmadd.s f0, f15, f5, f25 +fmadd.s f0, f15, f5, f31 +fmadd.s f0, f15, f10, f0 +fmadd.s f0, f15, f10, f1 +fmadd.s f0, f15, f10, f5 +fmadd.s f0, f15, f10, f10 +fmadd.s f0, f15, f10, f15 +fmadd.s f0, f15, f10, f20 +fmadd.s f0, f15, f10, f25 +fmadd.s f0, f15, f10, f31 +fmadd.s f0, f15, f15, f0 +fmadd.s f0, f15, f15, f1 +fmadd.s f0, f15, f15, f5 +fmadd.s f0, f15, f15, f10 +fmadd.s f0, f15, f15, f15 +fmadd.s f0, f15, f15, f20 +fmadd.s f0, f15, f15, f25 +fmadd.s f0, f15, f15, f31 +fmadd.s f0, f15, f20, f0 +fmadd.s f0, f15, f20, f1 +fmadd.s f0, f15, f20, f5 +fmadd.s f0, f15, f20, f10 +fmadd.s f0, f15, f20, f15 +fmadd.s f0, f15, f20, f20 +fmadd.s f0, f15, f20, f25 +fmadd.s f0, f15, f20, f31 +fmadd.s f0, f15, f25, f0 +fmadd.s f0, f15, f25, f1 +fmadd.s f0, f15, f25, f5 +fmadd.s f0, f15, f25, f10 +fmadd.s f0, f15, f25, f15 +fmadd.s f0, f15, f25, f20 +fmadd.s f0, f15, f25, f25 +fmadd.s f0, f15, f25, f31 +fmadd.s f0, f15, f31, f0 +fmadd.s f0, f15, f31, f1 +fmadd.s f0, f15, f31, f5 +fmadd.s f0, f15, f31, f10 +fmadd.s f0, f15, f31, f15 +fmadd.s f0, f15, f31, f20 +fmadd.s f0, f15, f31, f25 +fmadd.s f0, f15, f31, f31 +fmadd.s f0, f20, f0, f0 +fmadd.s f0, f20, f0, f1 +fmadd.s f0, f20, f0, f5 +fmadd.s f0, f20, f0, f10 +fmadd.s f0, f20, f0, f15 +fmadd.s f0, f20, f0, f20 +fmadd.s f0, f20, f0, f25 +fmadd.s f0, f20, f0, f31 +fmadd.s f0, f20, f1, f0 +fmadd.s f0, f20, f1, f1 +fmadd.s f0, f20, f1, f5 +fmadd.s f0, f20, f1, f10 +fmadd.s f0, f20, f1, f15 +fmadd.s f0, f20, f1, f20 +fmadd.s f0, f20, f1, f25 +fmadd.s f0, f20, f1, f31 +fmadd.s f0, f20, f5, f0 +fmadd.s f0, f20, f5, f1 +fmadd.s f0, f20, f5, f5 +fmadd.s f0, f20, f5, f10 +fmadd.s f0, f20, f5, f15 +fmadd.s f0, f20, f5, f20 +fmadd.s f0, f20, f5, f25 +fmadd.s f0, f20, f5, f31 +fmadd.s f0, f20, f10, f0 +fmadd.s f0, f20, f10, f1 +fmadd.s f0, f20, f10, f5 +fmadd.s f0, f20, f10, f10 +fmadd.s f0, f20, f10, f15 +fmadd.s f0, f20, f10, f20 +fmadd.s f0, f20, f10, f25 +fmadd.s f0, f20, f10, f31 +fmadd.s f0, f20, f15, f0 +fmadd.s f0, f20, f15, f1 +fmadd.s f0, f20, f15, f5 +fmadd.s f0, f20, f15, f10 +fmadd.s f0, f20, f15, f15 +fmadd.s f0, f20, f15, f20 +fmadd.s f0, f20, f15, f25 +fmadd.s f0, f20, f15, f31 +fmadd.s f0, f20, f20, f0 +fmadd.s f0, f20, f20, f1 +fmadd.s f0, f20, f20, f5 +fmadd.s f0, f20, f20, f10 +fmadd.s f0, f20, f20, f15 +fmadd.s f0, f20, f20, f20 +fmadd.s f0, f20, f20, f25 +fmadd.s f0, f20, f20, f31 +fmadd.s f0, f20, f25, f0 +fmadd.s f0, f20, f25, f1 +fmadd.s f0, f20, f25, f5 +fmadd.s f0, f20, f25, f10 +fmadd.s f0, f20, f25, f15 +fmadd.s f0, f20, f25, f20 +fmadd.s f0, f20, f25, f25 +fmadd.s f0, f20, f25, f31 +fmadd.s f0, f20, f31, f0 +fmadd.s f0, f20, f31, f1 +fmadd.s f0, f20, f31, f5 +fmadd.s f0, f20, f31, f10 +fmadd.s f0, f20, f31, f15 +fmadd.s f0, f20, f31, f20 +fmadd.s f0, f20, f31, f25 +fmadd.s f0, f20, f31, f31 +fmadd.s f0, f25, f0, f0 +fmadd.s f0, f25, f0, f1 +fmadd.s f0, f25, f0, f5 +fmadd.s f0, f25, f0, f10 +fmadd.s f0, f25, f0, f15 +fmadd.s f0, f25, f0, f20 +fmadd.s f0, f25, f0, f25 +fmadd.s f0, f25, f0, f31 +fmadd.s f0, f25, f1, f0 +fmadd.s f0, f25, f1, f1 +fmadd.s f0, f25, f1, f5 +fmadd.s f0, f25, f1, f10 +fmadd.s f0, f25, f1, f15 +fmadd.s f0, f25, f1, f20 +fmadd.s f0, f25, f1, f25 +fmadd.s f0, f25, f1, f31 +fmadd.s f0, f25, f5, f0 +fmadd.s f0, f25, f5, f1 +fmadd.s f0, f25, f5, f5 +fmadd.s f0, f25, f5, f10 +fmadd.s f0, f25, f5, f15 +fmadd.s f0, f25, f5, f20 +fmadd.s f0, f25, f5, f25 +fmadd.s f0, f25, f5, f31 +fmadd.s f0, f25, f10, f0 +fmadd.s f0, f25, f10, f1 +fmadd.s f0, f25, f10, f5 +fmadd.s f0, f25, f10, f10 +fmadd.s f0, f25, f10, f15 +fmadd.s f0, f25, f10, f20 +fmadd.s f0, f25, f10, f25 +fmadd.s f0, f25, f10, f31 +fmadd.s f0, f25, f15, f0 +fmadd.s f0, f25, f15, f1 +fmadd.s f0, f25, f15, f5 +fmadd.s f0, f25, f15, f10 +fmadd.s f0, f25, f15, f15 +fmadd.s f0, f25, f15, f20 +fmadd.s f0, f25, f15, f25 +fmadd.s f0, f25, f15, f31 +fmadd.s f0, f25, f20, f0 +fmadd.s f0, f25, f20, f1 +fmadd.s f0, f25, f20, f5 +fmadd.s f0, f25, f20, f10 +fmadd.s f0, f25, f20, f15 +fmadd.s f0, f25, f20, f20 +fmadd.s f0, f25, f20, f25 +fmadd.s f0, f25, f20, f31 +fmadd.s f0, f25, f25, f0 +fmadd.s f0, f25, f25, f1 +fmadd.s f0, f25, f25, f5 +fmadd.s f0, f25, f25, f10 +fmadd.s f0, f25, f25, f15 +fmadd.s f0, f25, f25, f20 +fmadd.s f0, f25, f25, f25 +fmadd.s f0, f25, f25, f31 +fmadd.s f0, f25, f31, f0 +fmadd.s f0, f25, f31, f1 +fmadd.s f0, f25, f31, f5 +fmadd.s f0, f25, f31, f10 +fmadd.s f0, f25, f31, f15 +fmadd.s f0, f25, f31, f20 +fmadd.s f0, f25, f31, f25 +fmadd.s f0, f25, f31, f31 +fmadd.s f0, f31, f0, f0 +fmadd.s f0, f31, f0, f1 +fmadd.s f0, f31, f0, f5 +fmadd.s f0, f31, f0, f10 +fmadd.s f0, f31, f0, f15 +fmadd.s f0, f31, f0, f20 +fmadd.s f0, f31, f0, f25 +fmadd.s f0, f31, f0, f31 +fmadd.s f0, f31, f1, f0 +fmadd.s f0, f31, f1, f1 +fmadd.s f0, f31, f1, f5 +fmadd.s f0, f31, f1, f10 +fmadd.s f0, f31, f1, f15 +fmadd.s f0, f31, f1, f20 +fmadd.s f0, f31, f1, f25 +fmadd.s f0, f31, f1, f31 +fmadd.s f0, f31, f5, f0 +fmadd.s f0, f31, f5, f1 +fmadd.s f0, f31, f5, f5 +fmadd.s f0, f31, f5, f10 +fmadd.s f0, f31, f5, f15 +fmadd.s f0, f31, f5, f20 +fmadd.s f0, f31, f5, f25 +fmadd.s f0, f31, f5, f31 +fmadd.s f0, f31, f10, f0 +fmadd.s f0, f31, f10, f1 +fmadd.s f0, f31, f10, f5 +fmadd.s f0, f31, f10, f10 +fmadd.s f0, f31, f10, f15 +fmadd.s f0, f31, f10, f20 +fmadd.s f0, f31, f10, f25 +fmadd.s f0, f31, f10, f31 +fmadd.s f0, f31, f15, f0 +fmadd.s f0, f31, f15, f1 +fmadd.s f0, f31, f15, f5 +fmadd.s f0, f31, f15, f10 +fmadd.s f0, f31, f15, f15 +fmadd.s f0, f31, f15, f20 +fmadd.s f0, f31, f15, f25 +fmadd.s f0, f31, f15, f31 +fmadd.s f0, f31, f20, f0 +fmadd.s f0, f31, f20, f1 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f1, f25, f5, f15 +fmadd.s f1, f25, f5, f20 +fmadd.s f1, f25, f5, f25 +fmadd.s f1, f25, f5, f31 +fmadd.s f1, f25, f10, f0 +fmadd.s f1, f25, f10, f1 +fmadd.s f1, f25, f10, f5 +fmadd.s f1, f25, f10, f10 +fmadd.s f1, f25, f10, f15 +fmadd.s f1, f25, f10, f20 +fmadd.s f1, f25, f10, f25 +fmadd.s f1, f25, f10, f31 +fmadd.s f1, f25, f15, f0 +fmadd.s f1, f25, f15, f1 +fmadd.s f1, f25, f15, f5 +fmadd.s f1, f25, f15, f10 +fmadd.s f1, f25, f15, f15 +fmadd.s f1, f25, f15, f20 +fmadd.s f1, f25, f15, f25 +fmadd.s f1, f25, f15, f31 +fmadd.s f1, f25, f20, f0 +fmadd.s f1, f25, f20, f1 +fmadd.s f1, f25, f20, f5 +fmadd.s f1, f25, f20, f10 +fmadd.s f1, f25, f20, f15 +fmadd.s f1, f25, f20, f20 +fmadd.s f1, f25, f20, f25 +fmadd.s f1, f25, f20, f31 +fmadd.s f1, f25, f25, f0 +fmadd.s f1, f25, f25, f1 +fmadd.s f1, f25, f25, f5 +fmadd.s f1, f25, f25, f10 +fmadd.s f1, f25, f25, f15 +fmadd.s f1, f25, f25, f20 +fmadd.s f1, f25, f25, f25 +fmadd.s f1, f25, f25, f31 +fmadd.s f1, f25, f31, f0 +fmadd.s f1, f25, f31, f1 +fmadd.s f1, f25, f31, f5 +fmadd.s f1, f25, f31, f10 +fmadd.s f1, f25, f31, f15 +fmadd.s f1, f25, f31, f20 +fmadd.s f1, f25, f31, f25 +fmadd.s f1, f25, f31, f31 +fmadd.s f1, f31, f0, f0 +fmadd.s f1, f31, f0, f1 +fmadd.s f1, f31, f0, f5 +fmadd.s f1, f31, f0, f10 +fmadd.s f1, f31, f0, f15 +fmadd.s f1, f31, f0, f20 +fmadd.s f1, f31, f0, f25 +fmadd.s f1, f31, f0, f31 +fmadd.s f1, f31, f1, f0 +fmadd.s f1, f31, f1, f1 +fmadd.s f1, f31, f1, f5 +fmadd.s f1, f31, f1, f10 +fmadd.s f1, f31, f1, f15 +fmadd.s f1, f31, f1, f20 +fmadd.s f1, f31, f1, f25 +fmadd.s f1, f31, f1, f31 +fmadd.s f1, f31, f5, f0 +fmadd.s f1, f31, f5, f1 +fmadd.s f1, f31, f5, f5 +fmadd.s f1, f31, f5, f10 +fmadd.s f1, f31, f5, f15 +fmadd.s f1, f31, f5, f20 +fmadd.s f1, f31, f5, f25 +fmadd.s f1, f31, f5, f31 +fmadd.s f1, f31, f10, f0 +fmadd.s f1, f31, f10, f1 +fmadd.s f1, f31, f10, f5 +fmadd.s f1, f31, f10, f10 +fmadd.s f1, f31, f10, f15 +fmadd.s f1, f31, f10, f20 +fmadd.s f1, f31, f10, f25 +fmadd.s f1, f31, f10, f31 +fmadd.s f1, f31, f15, f0 +fmadd.s f1, f31, f15, f1 +fmadd.s f1, f31, f15, f5 +fmadd.s f1, f31, f15, f10 +fmadd.s f1, f31, f15, f15 +fmadd.s f1, f31, f15, f20 +fmadd.s f1, f31, f15, f25 +fmadd.s f1, f31, f15, f31 +fmadd.s f1, f31, f20, f0 +fmadd.s f1, f31, f20, f1 +fmadd.s f1, f31, f20, f5 +fmadd.s f1, f31, f20, f10 +fmadd.s f1, f31, f20, f15 +fmadd.s f1, f31, f20, f20 +fmadd.s f1, f31, f20, f25 +fmadd.s f1, f31, f20, f31 +fmadd.s f1, f31, f25, f0 +fmadd.s f1, f31, f25, f1 +fmadd.s f1, f31, f25, f5 +fmadd.s f1, f31, f25, f10 +fmadd.s f1, f31, f25, f15 +fmadd.s f1, f31, f25, f20 +fmadd.s f1, f31, f25, f25 +fmadd.s f1, f31, f25, f31 +fmadd.s f1, f31, f31, f0 +fmadd.s f1, f31, f31, f1 +fmadd.s f1, f31, f31, f5 +fmadd.s f1, f31, f31, f10 +fmadd.s f1, f31, f31, f15 +fmadd.s f1, f31, f31, f20 +fmadd.s f1, f31, f31, f25 +fmadd.s f1, f31, f31, f31 +fmadd.s f5, f0, f0, f0 +fmadd.s f5, f0, f0, f1 +fmadd.s f5, f0, f0, f5 +fmadd.s f5, f0, f0, f10 +fmadd.s f5, f0, f0, f15 +fmadd.s f5, f0, f0, f20 +fmadd.s f5, f0, f0, f25 +fmadd.s f5, f0, f0, f31 +fmadd.s f5, f0, f1, f0 +fmadd.s f5, f0, f1, f1 +fmadd.s f5, f0, f1, f5 +fmadd.s f5, f0, f1, f10 +fmadd.s f5, f0, f1, f15 +fmadd.s f5, f0, f1, f20 +fmadd.s f5, f0, f1, f25 +fmadd.s f5, f0, f1, f31 +fmadd.s f5, f0, f5, f0 +fmadd.s f5, f0, f5, f1 +fmadd.s f5, f0, f5, f5 +fmadd.s f5, f0, f5, f10 +fmadd.s f5, f0, f5, f15 +fmadd.s f5, f0, f5, f20 +fmadd.s f5, f0, f5, f25 +fmadd.s f5, f0, f5, f31 +fmadd.s f5, f0, f10, f0 +fmadd.s f5, f0, f10, f1 +fmadd.s f5, f0, f10, f5 +fmadd.s f5, f0, f10, f10 +fmadd.s f5, f0, f10, f15 +fmadd.s f5, f0, f10, f20 +fmadd.s f5, f0, f10, f25 +fmadd.s f5, f0, f10, f31 +fmadd.s f5, f0, f15, f0 +fmadd.s f5, f0, f15, f1 +fmadd.s f5, f0, f15, f5 +fmadd.s f5, f0, f15, f10 +fmadd.s f5, f0, f15, f15 +fmadd.s f5, f0, f15, f20 +fmadd.s f5, f0, f15, f25 +fmadd.s f5, f0, f15, f31 +fmadd.s f5, f0, f20, f0 +fmadd.s f5, f0, f20, f1 +fmadd.s f5, f0, f20, f5 +fmadd.s f5, f0, f20, f10 +fmadd.s f5, f0, f20, f15 +fmadd.s f5, f0, f20, f20 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f20 +fmadd.s f5, f1, f5, f25 +fmadd.s f5, f1, f5, f31 +fmadd.s f5, f1, f10, f0 +fmadd.s f5, f1, f10, f1 +fmadd.s f5, f1, f10, f5 +fmadd.s f5, f1, f10, f10 +fmadd.s f5, f1, f10, f15 +fmadd.s f5, f1, f10, f20 +fmadd.s f5, f1, f10, f25 +fmadd.s f5, f1, f10, f31 +fmadd.s f5, f1, f15, f0 +fmadd.s f5, f1, f15, f1 +fmadd.s f5, f1, f15, f5 +fmadd.s f5, f1, f15, f10 +fmadd.s f5, f1, f15, f15 +fmadd.s f5, f1, f15, f20 +fmadd.s f5, f1, f15, f25 +fmadd.s f5, f1, f15, f31 +fmadd.s f5, f1, f20, f0 +fmadd.s f5, f1, f20, f1 +fmadd.s f5, f1, f20, f5 +fmadd.s f5, f1, f20, f10 +fmadd.s f5, f1, f20, f15 +fmadd.s f5, f1, f20, f20 +fmadd.s f5, f1, f20, f25 +fmadd.s f5, f1, f20, f31 +fmadd.s f5, f1, f25, f0 +fmadd.s f5, f1, f25, f1 +fmadd.s f5, f1, f25, f5 +fmadd.s f5, f1, f25, f10 +fmadd.s f5, f1, f25, f15 +fmadd.s f5, f1, f25, f20 +fmadd.s f5, f1, f25, f25 +fmadd.s f5, f1, f25, f31 +fmadd.s f5, f1, f31, f0 +fmadd.s f5, f1, f31, f1 +fmadd.s f5, f1, f31, f5 +fmadd.s f5, f1, f31, f10 +fmadd.s f5, f1, f31, f15 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f25 +fmadd.s f20, f1, f31, f31 +fmadd.s f20, f5, f0, f0 +fmadd.s f20, f5, f0, f1 +fmadd.s f20, f5, f0, f5 +fmadd.s f20, f5, f0, f10 +fmadd.s f20, f5, f0, f15 +fmadd.s f20, f5, f0, f20 +fmadd.s f20, f5, f0, f25 +fmadd.s f20, f5, f0, f31 +fmadd.s f20, f5, f1, f0 +fmadd.s f20, f5, f1, f1 +fmadd.s f20, f5, f1, f5 +fmadd.s f20, f5, f1, f10 +fmadd.s f20, f5, f1, f15 +fmadd.s f20, f5, f1, f20 +fmadd.s f20, f5, f1, f25 +fmadd.s f20, f5, f1, f31 +fmadd.s f20, f5, f5, f0 +fmadd.s f20, f5, f5, f1 +fmadd.s f20, f5, f5, f5 +fmadd.s f20, f5, f5, f10 +fmadd.s f20, f5, f5, f15 +fmadd.s f20, f5, f5, f20 +fmadd.s f20, f5, f5, f25 +fmadd.s f20, f5, f5, f31 +fmadd.s f20, f5, f10, f0 +fmadd.s f20, f5, f10, f1 +fmadd.s f20, f5, f10, f5 +fmadd.s f20, f5, f10, f10 +fmadd.s f20, f5, f10, f15 +fmadd.s f20, f5, f10, f20 +fmadd.s f20, f5, f10, f25 +fmadd.s f20, f5, f10, f31 +fmadd.s f20, f5, f15, f0 +fmadd.s f20, f5, f15, f1 +fmadd.s f20, f5, f15, f5 +fmadd.s f20, f5, f15, f10 +fmadd.s f20, f5, f15, f15 +fmadd.s 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+fmadd.s f25, f20, f0, f1 +fmadd.s f25, f20, f0, f5 +fmadd.s f25, f20, f0, f10 +fmadd.s f25, f20, f0, f15 +fmadd.s f25, f20, f0, f20 +fmadd.s f25, f20, f0, f25 +fmadd.s f25, f20, f0, f31 +fmadd.s f25, f20, f1, f0 +fmadd.s f25, f20, f1, f1 +fmadd.s f25, f20, f1, f5 +fmadd.s f25, f20, f1, f10 +fmadd.s f25, f20, f1, f15 +fmadd.s f25, f20, f1, f20 +fmadd.s f25, f20, f1, f25 +fmadd.s f25, f20, f1, f31 +fmadd.s f25, f20, f5, f0 +fmadd.s f25, f20, f5, f1 +fmadd.s f25, f20, f5, f5 +fmadd.s f25, f20, f5, f10 +fmadd.s f25, f20, f5, f15 +fmadd.s f25, f20, f5, f20 +fmadd.s f25, f20, f5, f25 +fmadd.s f25, f20, f5, f31 +fmadd.s f25, f20, f10, f0 +fmadd.s f25, f20, f10, f1 +fmadd.s f25, f20, f10, f5 +fmadd.s f25, f20, f10, f10 +fmadd.s f25, f20, f10, f15 +fmadd.s f25, f20, f10, f20 +fmadd.s f25, f20, f10, f25 +fmadd.s f25, f20, f10, f31 +fmadd.s f25, f20, f15, f0 +fmadd.s f25, f20, f15, f1 +fmadd.s f25, f20, f15, f5 +fmadd.s f25, f20, f15, f10 +fmadd.s f25, f20, f15, f15 +fmadd.s f25, f20, f15, f20 +fmadd.s f25, f20, f15, f25 +fmadd.s f25, f20, f15, f31 +fmadd.s f25, f20, f20, f0 +fmadd.s f25, f20, f20, f1 +fmadd.s f25, f20, f20, f5 +fmadd.s f25, f20, f20, f10 +fmadd.s f25, f20, f20, f15 +fmadd.s f25, f20, f20, f20 +fmadd.s f25, f20, f20, f25 +fmadd.s f25, f20, f20, f31 +fmadd.s f25, f20, f25, f0 +fmadd.s f25, f20, f25, f1 +fmadd.s f25, f20, f25, f5 +fmadd.s f25, f20, f25, f10 +fmadd.s f25, f20, f25, f15 +fmadd.s f25, f20, f25, f20 +fmadd.s f25, f20, f25, f25 +fmadd.s f25, f20, f25, f31 +fmadd.s f25, f20, f31, f0 +fmadd.s f25, f20, f31, f1 +fmadd.s f25, f20, f31, f5 +fmadd.s f25, f20, f31, f10 +fmadd.s f25, f20, f31, f15 +fmadd.s f25, f20, f31, f20 +fmadd.s f25, f20, f31, f25 +fmadd.s f25, f20, f31, f31 +fmadd.s f25, f25, f0, f0 +fmadd.s f25, f25, f0, f1 +fmadd.s f25, f25, f0, f5 +fmadd.s f25, f25, f0, f10 +fmadd.s f25, f25, f0, f15 +fmadd.s f25, f25, f0, f20 +fmadd.s f25, f25, f0, f25 +fmadd.s f25, f25, f0, f31 +fmadd.s f25, f25, f1, f0 +fmadd.s f25, f25, f1, f1 +fmadd.s f25, f25, f1, f5 +fmadd.s f25, f25, f1, f10 +fmadd.s f25, f25, f1, f15 +fmadd.s f25, f25, f1, f20 +fmadd.s f25, f25, f1, f25 +fmadd.s f25, f25, f1, f31 +fmadd.s f25, f25, f5, f0 +fmadd.s f25, f25, f5, f1 +fmadd.s f25, f25, f5, f5 +fmadd.s f25, f25, f5, f10 +fmadd.s f25, f25, f5, f15 +fmadd.s f25, f25, f5, f20 +fmadd.s f25, f25, f5, f25 +fmadd.s f25, f25, f5, f31 +fmadd.s f25, f25, f10, f0 +fmadd.s f25, f25, f10, f1 +fmadd.s f25, f25, f10, f5 +fmadd.s f25, f25, f10, f10 +fmadd.s f25, f25, f10, f15 +fmadd.s f25, f25, f10, f20 +fmadd.s f25, f25, f10, f25 +fmadd.s f25, f25, f10, f31 +fmadd.s f25, f25, f15, f0 +fmadd.s f25, f25, f15, f1 +fmadd.s f25, f25, f15, f5 +fmadd.s f25, f25, f15, f10 +fmadd.s f25, f25, f15, f15 +fmadd.s f25, f25, f15, f20 +fmadd.s f25, f25, f15, f25 +fmadd.s f25, f25, f15, f31 +fmadd.s f25, f25, f20, f0 +fmadd.s f25, f25, f20, f1 +fmadd.s f25, f25, f20, f5 +fmadd.s f25, f25, f20, f10 +fmadd.s f25, f25, f20, f15 +fmadd.s f25, f25, f20, f20 +fmadd.s f25, f25, f20, f25 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f25, f31, f31, f0 +fmadd.s f25, f31, f31, f1 +fmadd.s f25, f31, f31, f5 +fmadd.s f25, f31, f31, f10 +fmadd.s f25, f31, f31, f15 +fmadd.s f25, f31, f31, f20 +fmadd.s f25, f31, f31, f25 +fmadd.s f25, f31, f31, f31 +fmadd.s f31, f0, f0, f0 +fmadd.s f31, f0, f0, f1 +fmadd.s f31, f0, f0, f5 +fmadd.s f31, f0, f0, f10 +fmadd.s f31, f0, f0, f15 +fmadd.s f31, f0, f0, f20 +fmadd.s f31, f0, f0, f25 +fmadd.s f31, f0, f0, f31 +fmadd.s f31, f0, f1, f0 +fmadd.s f31, f0, f1, f1 +fmadd.s f31, f0, f1, f5 +fmadd.s f31, f0, f1, f10 +fmadd.s f31, f0, f1, f15 +fmadd.s f31, f0, f1, f20 +fmadd.s f31, f0, f1, f25 +fmadd.s f31, f0, f1, f31 +fmadd.s f31, f0, f5, f0 +fmadd.s f31, f0, f5, f1 +fmadd.s f31, f0, f5, f5 +fmadd.s f31, f0, f5, f10 +fmadd.s f31, f0, f5, f15 +fmadd.s f31, f0, f5, f20 +fmadd.s f31, f0, f5, f25 +fmadd.s f31, f0, f5, f31 +fmadd.s f31, f0, f10, f0 +fmadd.s f31, f0, f10, f1 +fmadd.s f31, f0, f10, f5 +fmadd.s f31, f0, f10, f10 +fmadd.s f31, f0, f10, f15 +fmadd.s f31, f0, f10, f20 +fmadd.s f31, f0, f10, f25 +fmadd.s f31, f0, f10, f31 +fmadd.s f31, f0, f15, f0 +fmadd.s f31, f0, f15, f1 +fmadd.s f31, f0, f15, f5 +fmadd.s f31, f0, f15, f10 +fmadd.s f31, f0, f15, f15 +fmadd.s f31, f0, f15, f20 +fmadd.s f31, f0, f15, f25 +fmadd.s f31, f0, f15, f31 +fmadd.s f31, f0, f20, f0 +fmadd.s f31, f0, f20, f1 +fmadd.s f31, f0, f20, f5 +fmadd.s f31, f0, f20, f10 +fmadd.s f31, f0, f20, f15 +fmadd.s f31, f0, f20, f20 +fmadd.s f31, f0, f20, f25 +fmadd.s f31, f0, f20, f31 +fmadd.s f31, f0, f25, f0 +fmadd.s f31, f0, f25, f1 +fmadd.s f31, f0, f25, f5 +fmadd.s f31, f0, f25, f10 +fmadd.s f31, f0, f25, f15 +fmadd.s f31, f0, f25, f20 +fmadd.s f31, f0, f25, f25 +fmadd.s f31, f0, f25, f31 +fmadd.s f31, f0, f31, f0 +fmadd.s f31, f0, f31, f1 +fmadd.s f31, f0, f31, f5 +fmadd.s f31, f0, f31, f10 +fmadd.s f31, f0, f31, f15 +fmadd.s f31, f0, f31, f20 +fmadd.s f31, f0, f31, f25 +fmadd.s f31, f0, f31, f31 +fmadd.s f31, f1, f0, f0 +fmadd.s f31, f1, f0, f1 +fmadd.s f31, f1, f0, f5 +fmadd.s f31, f1, f0, f10 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f31, f1, f20, f5 +fmadd.s f31, f1, f20, f10 +fmadd.s f31, f1, f20, f15 +fmadd.s f31, f1, f20, f20 +fmadd.s f31, f1, f20, f25 +fmadd.s f31, f1, f20, f31 +fmadd.s f31, f1, f25, f0 +fmadd.s f31, f1, f25, f1 +fmadd.s f31, f1, f25, f5 +fmadd.s f31, f1, f25, f10 +fmadd.s f31, f1, f25, f15 +fmadd.s f31, f1, f25, f20 +fmadd.s f31, f1, f25, f25 +fmadd.s f31, f1, f25, f31 +fmadd.s f31, f1, f31, f0 +fmadd.s f31, f1, f31, f1 +fmadd.s f31, f1, f31, f5 +fmadd.s f31, f1, f31, f10 +fmadd.s f31, f1, f31, f15 +fmadd.s f31, f1, f31, f20 +fmadd.s f31, f1, f31, f25 +fmadd.s f31, f1, f31, f31 +fmadd.s f31, f5, f0, f0 +fmadd.s f31, f5, f0, f1 +fmadd.s f31, f5, f0, f5 +fmadd.s f31, f5, f0, f10 +fmadd.s f31, f5, f0, f15 +fmadd.s f31, f5, f0, f20 +fmadd.s f31, f5, f0, f25 +fmadd.s f31, f5, f0, f31 +fmadd.s f31, f5, f1, f0 +fmadd.s f31, f5, f1, f1 +fmadd.s f31, f5, f1, f5 +fmadd.s f31, f5, f1, f10 +fmadd.s f31, f5, f1, f15 +fmadd.s f31, f5, f1, f20 +fmadd.s f31, f5, f1, f25 +fmadd.s f31, f5, f1, f31 +fmadd.s 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f0, f0, f25 +fmadd.s f0, f0, f0, f31 +fmadd.s f0, f0, f1, f0 +fmadd.s f0, f0, f1, f1 +fmadd.s f0, f0, f1, f5 +fmadd.s f0, f0, f1, f10 +fmadd.s f0, f0, f1, f15 +fmadd.s f0, f0, f1, f20 +fmadd.s f0, f0, f1, f25 +fmadd.s f0, f0, f1, f31 +fmadd.s f0, f0, f5, f0 +fmadd.s f0, f0, f5, f1 +fmadd.s f0, f0, f5, f5 +fmadd.s f0, f0, f5, f10 +fmadd.s f0, f0, f5, f15 +fmadd.s f0, f0, f5, f20 +fmadd.s f0, f0, f5, f25 +fmadd.s f0, f0, f5, f31 +fmadd.s f0, f0, f10, f0 +fmadd.s f0, f0, f10, f1 +fmadd.s f0, f0, f10, f5 +fmadd.s f0, f0, f10, f10 +fmadd.s f0, f0, f10, f15 +fmadd.s f0, f0, f10, f20 +fmadd.s f0, f0, f10, f25 +fmadd.s f0, f0, f10, f31 +fmadd.s f0, f0, f15, f0 +fmadd.s f0, f0, f15, f1 +fmadd.s f0, f0, f15, f5 +fmadd.s f0, f0, f15, f10 +fmadd.s f0, f0, f15, f15 +fmadd.s f0, f0, f15, f20 +fmadd.s f0, f0, f15, f25 +fmadd.s f0, f0, f15, f31 +fmadd.s f0, f0, f20, f0 +fmadd.s f0, f0, f20, f1 +fmadd.s f0, f0, f20, f5 +fmadd.s f0, f0, f20, f10 +fmadd.s f0, f0, f20, f15 +fmadd.s f0, f0, f20, f20 +fmadd.s f0, f0, f20, f25 +fmadd.s f0, f0, f20, f31 +fmadd.s f0, f0, f25, f0 +fmadd.s f0, f0, f25, f1 +fmadd.s f0, f0, f25, f5 +fmadd.s f0, f0, f25, f10 +fmadd.s f0, f0, f25, f15 +fmadd.s f0, f0, f25, f20 +fmadd.s f0, f0, f25, f25 +fmadd.s f0, f0, f25, f31 +fmadd.s f0, f0, f31, f0 +fmadd.s f0, f0, f31, f1 +fmadd.s f0, f0, f31, f5 +fmadd.s f0, f0, f31, f10 +fmadd.s f0, f0, f31, f15 +fmadd.s f0, f0, f31, f20 +fmadd.s f0, f0, f31, f25 +fmadd.s f0, f0, f31, f31 +fmadd.s f0, f1, f0, f0 +fmadd.s f0, f1, f0, f1 +fmadd.s f0, f1, f0, f5 +fmadd.s f0, f1, f0, f10 +fmadd.s f0, f1, f0, f15 +fmadd.s f0, f1, f0, f20 +fmadd.s f0, f1, f0, f25 +fmadd.s f0, f1, f0, f31 +fmadd.s f0, f1, f1, f0 +fmadd.s f0, f1, f1, f1 +fmadd.s f0, f1, f1, f5 +fmadd.s f0, f1, f1, f10 +fmadd.s f0, f1, f1, f15 +fmadd.s f0, f1, f1, f20 +fmadd.s f0, f1, f1, f25 +fmadd.s f0, f1, f1, f31 +fmadd.s f0, f1, f5, f0 +fmadd.s f0, f1, f5, f1 +fmadd.s f0, f1, f5, f5 +fmadd.s f0, f1, f5, f10 +fmadd.s f0, f1, f5, f15 +fmadd.s f0, f1, f5, f20 +fmadd.s f0, f1, f5, f25 +fmadd.s f0, f1, f5, f31 +fmadd.s f0, f1, f10, f0 +fmadd.s f0, f1, f10, f1 +fmadd.s f0, f1, f10, f5 +fmadd.s f0, f1, f10, f10 +fmadd.s f0, f1, f10, f15 +fmadd.s f0, f1, f10, f20 +fmadd.s f0, f1, f10, f25 +fmadd.s f0, f1, f10, f31 +fmadd.s f0, f1, f15, f0 +fmadd.s f0, f1, f15, f1 +fmadd.s f0, f1, f15, f5 +fmadd.s f0, f1, f15, f10 +fmadd.s f0, f1, f15, f15 +fmadd.s f0, f1, f15, f20 +fmadd.s f0, f1, f15, f25 +fmadd.s f0, f1, f15, f31 +fmadd.s f0, f1, f20, f0 +fmadd.s f0, f1, f20, f1 +fmadd.s f0, f1, f20, f5 +fmadd.s f0, f1, f20, f10 +fmadd.s f0, f1, f20, f15 +fmadd.s f0, f1, f20, f20 +fmadd.s f0, f1, f20, f25 +fmadd.s f0, f1, f20, f31 +fmadd.s f0, f1, f25, f0 +fmadd.s f0, f1, f25, f1 +fmadd.s f0, f1, f25, f5 +fmadd.s f0, f1, f25, f10 +fmadd.s f0, f1, f25, f15 +fmadd.s f0, f1, f25, f20 +fmadd.s f0, f1, f25, f25 +fmadd.s f0, f1, f25, f31 +fmadd.s f0, f1, f31, f0 +fmadd.s f0, f1, f31, f1 +fmadd.s f0, f1, f31, f5 +fmadd.s f0, f1, f31, f10 +fmadd.s f0, f1, f31, f15 +fmadd.s f0, f1, f31, f20 +fmadd.s f0, f1, f31, f25 +fmadd.s f0, f1, f31, f31 +fmadd.s f0, f5, f0, f0 +fmadd.s f0, f5, f0, f1 +fmadd.s f0, f5, f0, f5 +fmadd.s f0, f5, f0, f10 +fmadd.s f0, f5, f0, f15 +fmadd.s f0, f5, f0, f20 +fmadd.s f0, f5, f0, f25 +fmadd.s f0, f5, f0, f31 +fmadd.s f0, f5, f1, f0 +fmadd.s f0, f5, f1, f1 +fmadd.s f0, f5, f1, f5 +fmadd.s f0, f5, f1, f10 +fmadd.s f0, f5, f1, f15 +fmadd.s f0, f5, f1, f20 +fmadd.s f0, f5, f1, f25 +fmadd.s f0, f5, f1, f31 +fmadd.s f0, f5, f5, f0 +fmadd.s f0, f5, f5, f1 +fmadd.s f0, f5, f5, f5 +fmadd.s f0, f5, f5, f10 +fmadd.s f0, f5, f5, f15 +fmadd.s f0, f5, f5, f20 +fmadd.s f0, f5, f5, f25 +fmadd.s f0, f5, f5, f31 +fmadd.s f0, f5, f10, f0 +fmadd.s f0, f5, f10, f1 +fmadd.s f0, f5, f10, f5 +fmadd.s f0, f5, f10, f10 +fmadd.s f0, f5, f10, f15 +fmadd.s f0, f5, f10, f20 +fmadd.s f0, f5, f10, f25 +fmadd.s f0, f5, f10, f31 +fmadd.s f0, f5, f15, f0 +fmadd.s f0, f5, f15, f1 +fmadd.s f0, f5, f15, f5 +fmadd.s f0, f5, f15, f10 +fmadd.s f0, f5, f15, f15 +fmadd.s f0, f5, f15, f20 +fmadd.s f0, f5, f15, f25 +fmadd.s f0, f5, f15, f31 +fmadd.s f0, f5, f20, f0 +fmadd.s f0, f5, f20, f1 +fmadd.s f0, f5, f20, f5 +fmadd.s f0, f5, f20, f10 +fmadd.s f0, f5, f20, f15 +fmadd.s f0, f5, f20, f20 +fmadd.s f0, f5, f20, f25 +fmadd.s f0, f5, f20, f31 +fmadd.s f0, f5, f25, f0 +fmadd.s f0, f5, f25, f1 +fmadd.s f0, f5, f25, f5 +fmadd.s f0, f5, f25, f10 +fmadd.s f0, f5, f25, f15 +fmadd.s f0, f5, f25, f20 +fmadd.s f0, f5, f25, f25 +fmadd.s f0, f5, f25, f31 +fmadd.s f0, f5, f31, f0 +fmadd.s f0, f5, f31, f1 +fmadd.s f0, f5, f31, f5 +fmadd.s f0, f5, f31, f10 +fmadd.s f0, f5, f31, f15 +fmadd.s f0, f5, f31, f20 +fmadd.s f0, f5, f31, f25 +fmadd.s f0, f5, f31, f31 +fmadd.s f0, f10, f0, f0 +fmadd.s f0, f10, f0, f1 +fmadd.s f0, f10, f0, f5 +fmadd.s f0, f10, f0, f10 +fmadd.s f0, f10, f0, f15 +fmadd.s f0, f10, f0, f20 +fmadd.s f0, f10, f0, f25 +fmadd.s f0, f10, f0, f31 +fmadd.s f0, f10, f1, f0 +fmadd.s f0, f10, f1, f1 +fmadd.s f0, f10, f1, f5 +fmadd.s f0, f10, f1, f10 +fmadd.s f0, f10, f1, f15 +fmadd.s f0, f10, f1, f20 +fmadd.s f0, f10, f1, f25 +fmadd.s f0, f10, f1, f31 +fmadd.s f0, f10, f5, f0 +fmadd.s f0, f10, f5, f1 +fmadd.s f0, f10, f5, f5 +fmadd.s f0, f10, f5, f10 +fmadd.s f0, f10, f5, f15 +fmadd.s f0, f10, f5, f20 +fmadd.s f0, f10, f5, f25 +fmadd.s f0, f10, f5, f31 +fmadd.s f0, f10, f10, f0 +fmadd.s f0, f10, f10, f1 +fmadd.s f0, f10, f10, f5 +fmadd.s f0, f10, f10, f10 +fmadd.s f0, f10, f10, f15 +fmadd.s f0, f10, f10, f20 +fmadd.s f0, f10, f10, f25 +fmadd.s f0, f10, f10, f31 +fmadd.s f0, f10, f15, f0 +fmadd.s f0, f10, f15, f1 +fmadd.s f0, f10, f15, f5 +fmadd.s f0, f10, f15, f10 +fmadd.s f0, f10, f15, f15 +fmadd.s f0, f10, f15, f20 +fmadd.s f0, f10, f15, f25 +fmadd.s f0, f10, f15, f31 +fmadd.s f0, f10, f20, f0 +fmadd.s f0, f10, f20, f1 +fmadd.s f0, f10, f20, f5 +fmadd.s f0, f10, f20, f10 +fmadd.s f0, f10, f20, f15 +fmadd.s f0, f10, f20, f20 +fmadd.s f0, f10, f20, f25 +fmadd.s f0, f10, f20, f31 +fmadd.s f0, f10, f25, f0 +fmadd.s f0, f10, f25, f1 +fmadd.s f0, f10, f25, f5 +fmadd.s f0, f10, f25, f10 +fmadd.s f0, f10, f25, f15 +fmadd.s f0, f10, f25, f20 +fmadd.s f0, f10, f25, f25 +fmadd.s f0, f10, f25, f31 +fmadd.s f0, f10, f31, f0 +fmadd.s f0, f10, f31, f1 +fmadd.s f0, f10, f31, f5 +fmadd.s f0, f10, f31, f10 +fmadd.s f0, f10, f31, f15 +fmadd.s f0, f10, f31, f20 +fmadd.s f0, f10, f31, f25 +fmadd.s f0, f10, f31, f31 +fmadd.s f0, f15, f0, f0 +fmadd.s f0, f15, f0, f1 +fmadd.s f0, f15, f0, f5 +fmadd.s f0, f15, f0, f10 +fmadd.s f0, f15, f0, f15 +fmadd.s f0, f15, f0, f20 +fmadd.s f0, f15, f0, f25 +fmadd.s f0, f15, f0, f31 +fmadd.s f0, f15, f1, f0 +fmadd.s f0, f15, f1, f1 +fmadd.s f0, f15, f1, f5 +fmadd.s f0, f15, f1, f10 +fmadd.s f0, f15, f1, f15 +fmadd.s f0, f15, f1, f20 +fmadd.s f0, f15, f1, f25 +fmadd.s f0, f15, f1, f31 +fmadd.s f0, f15, f5, f0 +fmadd.s f0, f15, f5, f1 +fmadd.s f0, f15, f5, f5 +fmadd.s f0, f15, f5, f10 +fmadd.s f0, f15, f5, f15 +fmadd.s f0, f15, f5, f20 +fmadd.s f0, f15, f5, f25 +fmadd.s f0, f15, f5, f31 +fmadd.s f0, f15, f10, f0 +fmadd.s f0, f15, f10, f1 +fmadd.s f0, f15, f10, f5 +fmadd.s f0, f15, f10, f10 +fmadd.s f0, f15, f10, f15 +fmadd.s f0, f15, f10, f20 +fmadd.s f0, f15, f10, f25 +fmadd.s f0, f15, f10, f31 +fmadd.s f0, f15, f15, f0 +fmadd.s f0, f15, f15, f1 +fmadd.s f0, f15, f15, f5 +fmadd.s f0, f15, f15, f10 +fmadd.s f0, f15, f15, f15 +fmadd.s f0, f15, f15, f20 +fmadd.s f0, f15, f15, f25 +fmadd.s f0, f15, f15, f31 +fmadd.s f0, f15, f20, f0 +fmadd.s f0, f15, f20, f1 +fmadd.s f0, f15, f20, f5 +fmadd.s f0, f15, f20, f10 +fmadd.s f0, f15, f20, f15 +fmadd.s f0, f15, f20, f20 +fmadd.s f0, f15, f20, f25 +fmadd.s f0, f15, f20, f31 +fmadd.s f0, f15, f25, f0 +fmadd.s f0, f15, f25, f1 +fmadd.s f0, f15, f25, f5 +fmadd.s f0, f15, f25, f10 +fmadd.s f0, f15, f25, f15 +fmadd.s f0, f15, f25, f20 +fmadd.s f0, f15, f25, f25 +fmadd.s f0, f15, f25, f31 +fmadd.s f0, f15, f31, f0 +fmadd.s f0, f15, f31, f1 +fmadd.s f0, f15, f31, f5 +fmadd.s f0, f15, f31, f10 +fmadd.s f0, f15, f31, f15 +fmadd.s f0, f15, f31, f20 +fmadd.s f0, f15, f31, f25 +fmadd.s f0, f15, f31, f31 +fmadd.s f0, f20, f0, f0 +fmadd.s f0, f20, f0, f1 +fmadd.s f0, f20, f0, f5 +fmadd.s f0, f20, f0, f10 +fmadd.s f0, f20, f0, f15 +fmadd.s f0, f20, f0, f20 +fmadd.s f0, f20, f0, f25 +fmadd.s f0, f20, f0, f31 +fmadd.s f0, f20, f1, f0 +fmadd.s f0, f20, f1, f1 +fmadd.s f0, f20, f1, f5 +fmadd.s f0, f20, f1, f10 +fmadd.s f0, f20, f1, f15 +fmadd.s f0, f20, f1, f20 +fmadd.s f0, f20, f1, f25 +fmadd.s f0, f20, f1, f31 +fmadd.s f0, f20, f5, f0 +fmadd.s f0, f20, f5, f1 +fmadd.s f0, f20, f5, f5 +fmadd.s f0, f20, f5, f10 +fmadd.s f0, f20, f5, f15 +fmadd.s f0, f20, f5, f20 +fmadd.s f0, f20, f5, f25 +fmadd.s f0, f20, f5, f31 +fmadd.s f0, f20, f10, f0 +fmadd.s f0, f20, f10, f1 +fmadd.s f0, f20, f10, f5 +fmadd.s f0, f20, f10, f10 +fmadd.s f0, f20, f10, f15 +fmadd.s f0, f20, f10, f20 +fmadd.s f0, f20, f10, f25 +fmadd.s f0, f20, f10, f31 +fmadd.s f0, f20, f15, f0 +fmadd.s f0, f20, f15, f1 +fmadd.s f0, f20, f15, f5 +fmadd.s f0, f20, f15, f10 +fmadd.s f0, f20, f15, f15 +fmadd.s f0, f20, f15, f20 +fmadd.s f0, f20, f15, f25 +fmadd.s f0, f20, f15, f31 +fmadd.s f0, f20, f20, f0 +fmadd.s f0, f20, f20, f1 +fmadd.s f0, f20, f20, f5 +fmadd.s f0, f20, f20, f10 +fmadd.s f0, f20, f20, f15 +fmadd.s f0, f20, f20, f20 +fmadd.s f0, f20, f20, f25 +fmadd.s f0, f20, f20, f31 +fmadd.s f0, f20, f25, f0 +fmadd.s f0, f20, f25, f1 +fmadd.s f0, f20, f25, f5 +fmadd.s f0, f20, f25, f10 +fmadd.s f0, f20, f25, f15 +fmadd.s f0, f20, f25, f20 +fmadd.s f0, f20, f25, f25 +fmadd.s f0, f20, f25, f31 +fmadd.s f0, f20, f31, f0 +fmadd.s f0, f20, f31, f1 +fmadd.s f0, f20, f31, f5 +fmadd.s f0, f20, f31, f10 +fmadd.s f0, f20, f31, f15 +fmadd.s f0, f20, f31, f20 +fmadd.s f0, f20, f31, f25 +fmadd.s f0, f20, f31, f31 +fmadd.s f0, f25, f0, f0 +fmadd.s f0, f25, f0, f1 +fmadd.s f0, f25, f0, f5 +fmadd.s f0, f25, f0, f10 +fmadd.s f0, f25, f0, f15 +fmadd.s f0, f25, f0, f20 +fmadd.s f0, f25, f0, f25 +fmadd.s f0, f25, f0, f31 +fmadd.s f0, f25, f1, f0 +fmadd.s f0, f25, f1, f1 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f0 +fmadd.s f10, f5, f0, f1 +fmadd.s f10, f5, f0, f5 +fmadd.s f10, f5, f0, f10 +fmadd.s f10, f5, f0, f15 +fmadd.s f10, f5, f0, f20 +fmadd.s f10, f5, f0, f25 +fmadd.s f10, f5, f0, f31 +fmadd.s f10, f5, f1, f0 +fmadd.s f10, f5, f1, f1 +fmadd.s f10, f5, f1, f5 +fmadd.s f10, f5, f1, f10 +fmadd.s f10, f5, f1, f15 +fmadd.s f10, f5, f1, f20 +fmadd.s f10, f5, f1, f25 +fmadd.s f10, f5, f1, f31 +fmadd.s f10, f5, f5, f0 +fmadd.s f10, f5, f5, f1 +fmadd.s f10, f5, f5, f5 +fmadd.s f10, f5, f5, f10 +fmadd.s f10, f5, f5, f15 +fmadd.s f10, f5, f5, f20 +fmadd.s f10, f5, f5, f25 +fmadd.s f10, f5, f5, f31 +fmadd.s f10, f5, f10, f0 +fmadd.s f10, f5, f10, f1 +fmadd.s f10, f5, f10, f5 +fmadd.s f10, f5, f10, f10 +fmadd.s f10, f5, f10, f15 +fmadd.s f10, f5, f10, f20 +fmadd.s f10, f5, f10, f25 +fmadd.s f10, f5, f10, f31 +fmadd.s f10, f5, f15, f0 +fmadd.s f10, f5, f15, f1 +fmadd.s f10, f5, f15, f5 +fmadd.s f10, f5, f15, f10 +fmadd.s f10, f5, f15, f15 +fmadd.s f10, f5, f15, f20 +fmadd.s f10, f5, f15, f25 +fmadd.s f10, f5, f15, f31 +fmadd.s f10, f5, f20, f0 +fmadd.s f10, f5, f20, f1 +fmadd.s f10, f5, f20, f5 +fmadd.s f10, f5, f20, f10 +fmadd.s f10, f5, f20, f15 +fmadd.s f10, f5, f20, f20 +fmadd.s f10, f5, f20, f25 +fmadd.s f10, f5, f20, f31 +fmadd.s f10, f5, f25, f0 +fmadd.s f10, f5, f25, f1 +fmadd.s f10, f5, f25, f5 +fmadd.s f10, f5, f25, f10 +fmadd.s f10, f5, f25, f15 +fmadd.s f10, f5, f25, f20 +fmadd.s f10, f5, f25, f25 +fmadd.s f10, f5, f25, f31 +fmadd.s f10, f5, f31, f0 +fmadd.s f10, f5, f31, f1 +fmadd.s f10, f5, f31, f5 +fmadd.s f10, f5, f31, f10 +fmadd.s f10, f5, f31, f15 +fmadd.s f10, f5, f31, f20 +fmadd.s f10, f5, f31, f25 +fmadd.s f10, f5, f31, f31 +fmadd.s f10, f10, f0, f0 +fmadd.s f10, f10, f0, f1 +fmadd.s f10, f10, f0, f5 +fmadd.s f10, f10, f0, f10 +fmadd.s f10, f10, f0, f15 +fmadd.s f10, f10, f0, f20 +fmadd.s f10, f10, f0, f25 +fmadd.s f10, f10, f0, f31 +fmadd.s f10, f10, f1, f0 +fmadd.s f10, f10, f1, f1 +fmadd.s f10, f10, f1, f5 +fmadd.s f10, f10, f1, f10 +fmadd.s f10, f10, f1, f15 +fmadd.s f10, f10, f1, f20 +fmadd.s f10, f10, f1, f25 +fmadd.s f10, f10, f1, f31 +fmadd.s f10, f10, f5, f0 +fmadd.s f10, f10, f5, f1 +fmadd.s f10, f10, f5, f5 +fmadd.s f10, f10, f5, f10 +fmadd.s f10, f10, f5, f15 +fmadd.s f10, f10, f5, f20 +fmadd.s f10, f10, f5, f25 +fmadd.s f10, f10, f5, f31 +fmadd.s f10, f10, f10, f0 +fmadd.s f10, f10, f10, f1 +fmadd.s f10, f10, f10, f5 +fmadd.s f10, f10, f10, f10 +fmadd.s f10, f10, f10, f15 +fmadd.s f10, f10, f10, f20 +fmadd.s f10, f10, f10, f25 +fmadd.s f10, f10, f10, f31 +fmadd.s f10, f10, f15, f0 +fmadd.s f10, f10, f15, f1 +fmadd.s f10, f10, f15, f5 +fmadd.s f10, f10, f15, f10 +fmadd.s f10, f10, f15, f15 +fmadd.s f10, f10, f15, f20 +fmadd.s f10, f10, f15, f25 +fmadd.s f10, f10, f15, f31 +fmadd.s f10, f10, f20, f0 +fmadd.s f10, f10, f20, f1 +fmadd.s f10, f10, f20, f5 +fmadd.s f10, f10, f20, f10 +fmadd.s f10, f10, f20, f15 +fmadd.s f10, f10, f20, f20 +fmadd.s f10, f10, f20, f25 +fmadd.s f10, f10, f20, f31 +fmadd.s f10, f10, f25, f0 +fmadd.s f10, f10, f25, f1 +fmadd.s f10, f10, f25, f5 +fmadd.s f10, f10, f25, f10 +fmadd.s f10, f10, f25, f15 +fmadd.s f10, f10, f25, f20 +fmadd.s f10, f10, f25, f25 +fmadd.s f10, f10, f25, f31 +fmadd.s f10, f10, f31, f0 +fmadd.s f10, f10, f31, f1 +fmadd.s f10, f10, f31, f5 +fmadd.s f10, f10, f31, f10 +fmadd.s f10, f10, f31, f15 +fmadd.s f10, f10, f31, f20 +fmadd.s f10, f10, f31, f25 +fmadd.s f10, f10, f31, f31 +fmadd.s f10, f15, f0, f0 +fmadd.s f10, f15, f0, f1 +fmadd.s f10, f15, f0, f5 +fmadd.s f10, f15, f0, f10 +fmadd.s f10, f15, f0, f15 +fmadd.s f10, f15, f0, f20 +fmadd.s f10, f15, f0, f25 +fmadd.s f10, f15, f0, f31 +fmadd.s f10, f15, f1, f0 +fmadd.s f10, f15, f1, f1 +fmadd.s f10, f15, f1, f5 +fmadd.s f10, f15, f1, f10 +fmadd.s f10, f15, f1, f15 +fmadd.s f10, f15, f1, f20 +fmadd.s f10, f15, f1, f25 +fmadd.s f10, f15, f1, f31 +fmadd.s f10, f15, f5, f0 +fmadd.s f10, f15, f5, f1 +fmadd.s f10, f15, f5, f5 +fmadd.s f10, f15, f5, f10 +fmadd.s f10, f15, f5, f15 +fmadd.s f10, f15, f5, f20 +fmadd.s f10, f15, f5, f25 +fmadd.s f10, f15, f5, f31 +fmadd.s f10, f15, f10, f0 +fmadd.s f10, f15, f10, f1 +fmadd.s f10, f15, f10, f5 +fmadd.s f10, f15, f10, f10 +fmadd.s f10, f15, f10, f15 +fmadd.s f10, f15, f10, f20 +fmadd.s f10, f15, f10, f25 +fmadd.s f10, f15, f10, f31 +fmadd.s f10, f15, f15, f0 +fmadd.s f10, f15, f15, f1 +fmadd.s f10, f15, f15, f5 +fmadd.s f10, f15, f15, f10 +fmadd.s f10, f15, f15, f15 +fmadd.s f10, f15, f15, f20 +fmadd.s f10, f15, f15, f25 +fmadd.s f10, f15, f15, f31 +fmadd.s f10, f15, f20, f0 +fmadd.s f10, f15, f20, f1 +fmadd.s f10, f15, f20, f5 +fmadd.s f10, f15, f20, f10 +fmadd.s f10, f15, f20, f15 +fmadd.s f10, f15, f20, f20 +fmadd.s f10, f15, f20, f25 +fmadd.s f10, f15, f20, f31 +fmadd.s f10, f15, f25, f0 +fmadd.s f10, f15, f25, f1 +fmadd.s f10, f15, f25, f5 +fmadd.s f10, f15, f25, f10 +fmadd.s f10, f15, f25, f15 +fmadd.s f10, f15, f25, f20 +fmadd.s f10, f15, f25, f25 +fmadd.s f10, f15, f25, f31 +fmadd.s f10, f15, f31, f0 +fmadd.s f10, f15, f31, f1 +fmadd.s f10, f15, f31, f5 +fmadd.s f10, f15, f31, f10 +fmadd.s f10, f15, f31, f15 +fmadd.s f10, f15, f31, f20 +fmadd.s f10, f15, f31, f25 +fmadd.s f10, f15, f31, f31 +fmadd.s f10, f20, f0, f0 +fmadd.s f10, f20, f0, f1 +fmadd.s f10, f20, f0, f5 +fmadd.s f10, f20, f0, f10 +fmadd.s f10, f20, f0, f15 +fmadd.s f10, f20, f0, f20 +fmadd.s f10, f20, f0, f25 +fmadd.s f10, f20, f0, f31 +fmadd.s f10, f20, f1, f0 +fmadd.s f10, f20, f1, f1 +fmadd.s f10, f20, f1, f5 +fmadd.s f10, f20, f1, f10 +fmadd.s f10, f20, f1, f15 +fmadd.s f10, f20, f1, f20 +fmadd.s f10, f20, f1, f25 +fmadd.s f10, f20, f1, f31 +fmadd.s f10, f20, f5, f0 +fmadd.s f10, f20, f5, f1 +fmadd.s f10, f20, f5, f5 +fmadd.s f10, f20, f5, f10 +fmadd.s f10, f20, f5, f15 +fmadd.s f10, f20, f5, f20 +fmadd.s f10, f20, f5, f25 +fmadd.s f10, f20, f5, f31 +fmadd.s f10, f20, f10, f0 +fmadd.s f10, f20, f10, f1 +fmadd.s f10, f20, f10, f5 +fmadd.s f10, f20, f10, f10 +fmadd.s f10, f20, f10, f15 +fmadd.s f10, f20, f10, f20 +fmadd.s f10, f20, f10, f25 +fmadd.s f10, f20, f10, f31 +fmadd.s f10, f20, f15, f0 +fmadd.s f10, f20, f15, f1 +fmadd.s f10, f20, f15, f5 +fmadd.s f10, f20, f15, f10 +fmadd.s f10, f20, f15, f15 +fmadd.s f10, f20, f15, f20 +fmadd.s f10, f20, f15, f25 +fmadd.s f10, f20, f15, f31 +fmadd.s f10, f20, f20, f0 +fmadd.s f10, f20, f20, f1 +fmadd.s f10, f20, f20, f5 +fmadd.s f10, f20, f20, f10 +fmadd.s f10, f20, f20, f15 +fmadd.s f10, f20, f20, f20 +fmadd.s f10, f20, f20, f25 +fmadd.s f10, f20, f20, f31 +fmadd.s f10, f20, f25, f0 +fmadd.s f10, f20, f25, f1 +fmadd.s f10, f20, f25, f5 +fmadd.s f10, f20, f25, f10 +fmadd.s f10, f20, f25, f15 +fmadd.s f10, f20, f25, f20 +fmadd.s f10, f20, f25, f25 +fmadd.s f10, f20, f25, f31 +fmadd.s f10, f20, f31, f0 +fmadd.s f10, f20, f31, f1 +fmadd.s f10, f20, f31, f5 +fmadd.s f10, f20, f31, f10 +fmadd.s f10, f20, f31, f15 +fmadd.s f10, f20, f31, f20 +fmadd.s f10, f20, f31, f25 +fmadd.s f10, f20, f31, f31 +fmadd.s f10, f25, f0, f0 +fmadd.s f10, f25, f0, f1 +fmadd.s f10, f25, f0, f5 +fmadd.s f10, f25, f0, f10 +fmadd.s f10, f25, f0, f15 +fmadd.s f10, f25, f0, f20 +fmadd.s f10, f25, f0, f25 +fmadd.s f10, f25, f0, f31 +fmadd.s f10, f25, f1, f0 +fmadd.s f10, f25, f1, f1 +fmadd.s f10, f25, f1, f5 +fmadd.s f10, f25, f1, f10 +fmadd.s f10, f25, f1, f15 +fmadd.s f10, f25, f1, f20 +fmadd.s f10, f25, f1, f25 +fmadd.s f10, f25, f1, f31 +fmadd.s f10, f25, f5, f0 +fmadd.s f10, f25, f5, f1 +fmadd.s f10, f25, f5, f5 +fmadd.s f10, f25, f5, f10 +fmadd.s f10, f25, f5, f15 +fmadd.s f10, f25, f5, f20 +fmadd.s f10, f25, f5, f25 +fmadd.s f10, f25, f5, f31 +fmadd.s f10, f25, f10, f0 +fmadd.s f10, f25, f10, f1 +fmadd.s f10, f25, f10, f5 +fmadd.s f10, f25, f10, f10 +fmadd.s f10, f25, f10, f15 +fmadd.s f10, f25, f10, f20 +fmadd.s f10, f25, f10, f25 +fmadd.s f10, f25, f10, f31 +fmadd.s f10, f25, f15, f0 +fmadd.s f10, f25, f15, f1 +fmadd.s f10, f25, f15, f5 +fmadd.s f10, f25, f15, f10 +fmadd.s f10, f25, f15, f15 +fmadd.s f10, f25, f15, f20 +fmadd.s f10, f25, f15, f25 +fmadd.s f10, f25, f15, f31 +fmadd.s f10, f25, f20, f0 +fmadd.s f10, f25, f20, f1 +fmadd.s f10, f25, f20, f5 +fmadd.s f10, f25, f20, f10 +fmadd.s f10, f25, f20, f15 +fmadd.s f10, f25, f20, f20 +fmadd.s f10, f25, f20, f25 +fmadd.s f10, f25, f20, f31 +fmadd.s f10, f25, f25, f0 +fmadd.s f10, f25, f25, f1 +fmadd.s f10, f25, f25, f5 +fmadd.s f10, f25, f25, f10 +fmadd.s f10, f25, f25, f15 +fmadd.s f10, f25, f25, f20 +fmadd.s f10, f25, f25, f25 +fmadd.s f10, f25, f25, f31 +fmadd.s f10, f25, f31, f0 +fmadd.s f10, f25, f31, f1 +fmadd.s f10, f25, f31, f5 +fmadd.s f10, f25, f31, f10 +fmadd.s f10, f25, f31, f15 +fmadd.s f10, f25, f31, f20 +fmadd.s f10, f25, f31, f25 +fmadd.s f10, f25, f31, f31 +fmadd.s f10, f31, f0, f0 +fmadd.s f10, f31, f0, f1 +fmadd.s f10, f31, f0, f5 +fmadd.s f10, f31, f0, f10 +fmadd.s f10, f31, f0, f15 +fmadd.s f10, f31, f0, f20 +fmadd.s f10, f31, f0, f25 +fmadd.s f10, f31, f0, f31 +fmadd.s f10, f31, f1, f0 +fmadd.s f10, f31, f1, f1 +fmadd.s f10, f31, f1, f5 +fmadd.s f10, f31, f1, f10 +fmadd.s f10, f31, f1, f15 +fmadd.s f10, f31, f1, f20 +fmadd.s f10, f31, f1, f25 +fmadd.s f10, f31, f1, f31 +fmadd.s f10, f31, f5, f0 +fmadd.s f10, f31, f5, f1 +fmadd.s f10, f31, f5, f5 +fmadd.s f10, f31, f5, f10 +fmadd.s f10, f31, f5, f15 +fmadd.s f10, f31, f5, f20 +fmadd.s f10, f31, f5, f25 +fmadd.s f10, f31, f5, f31 +fmadd.s f10, f31, f10, f0 +fmadd.s f10, f31, f10, f1 +fmadd.s f10, f31, f10, f5 +fmadd.s f10, f31, f10, f10 +fmadd.s f10, f31, f10, f15 +fmadd.s f10, f31, f10, f20 +fmadd.s f10, f31, f10, f25 +fmadd.s f10, f31, f10, f31 +fmadd.s f10, f31, f15, f0 +fmadd.s f10, f31, f15, f1 +fmadd.s f10, f31, f15, f5 +fmadd.s f10, f31, f15, f10 +fmadd.s f10, f31, f15, f15 +fmadd.s f10, f31, f15, f20 +fmadd.s f10, f31, f15, f25 +fmadd.s f10, f31, f15, f31 +fmadd.s f10, f31, f20, f0 +fmadd.s f10, f31, f20, f1 +fmadd.s f10, f31, f20, f5 +fmadd.s f10, f31, f20, f10 +fmadd.s f10, f31, f20, f15 +fmadd.s f10, f31, f20, f20 +fmadd.s f10, f31, f20, f25 +fmadd.s f10, f31, f20, f31 +fmadd.s f10, f31, f25, f0 +fmadd.s f10, f31, f25, f1 +fmadd.s f10, f31, f25, f5 +fmadd.s f10, f31, f25, f10 +fmadd.s f10, f31, f25, f15 +fmadd.s f10, f31, f25, f20 +fmadd.s f10, f31, f25, f25 +fmadd.s f10, f31, f25, f31 +fmadd.s f10, f31, f31, f0 +fmadd.s f10, f31, f31, f1 +fmadd.s f10, f31, f31, f5 +fmadd.s f10, f31, f31, f10 +fmadd.s f10, f31, f31, f15 +fmadd.s f10, f31, f31, f20 +fmadd.s f10, f31, f31, f25 +fmadd.s f10, f31, f31, f31 +fmadd.s f15, f0, f0, f0 +fmadd.s f15, f0, f0, f1 +fmadd.s f15, f0, f0, f5 +fmadd.s f15, f0, f0, f10 +fmadd.s f15, f0, f0, f15 +fmadd.s f15, f0, f0, f20 +fmadd.s f15, f0, f0, f25 +fmadd.s f15, f0, f0, f31 +fmadd.s f15, f0, f1, f0 +fmadd.s f15, f0, f1, f1 +fmadd.s f15, f0, f1, f5 +fmadd.s f15, f0, f1, f10 +fmadd.s f15, f0, f1, f15 +fmadd.s f15, f0, f1, f20 +fmadd.s f15, f0, f1, f25 +fmadd.s f15, f0, f1, f31 +fmadd.s f15, f0, f5, f0 +fmadd.s f15, f0, f5, f1 +fmadd.s f15, f0, f5, f5 +fmadd.s f15, f0, f5, f10 +fmadd.s f15, f0, f5, f15 +fmadd.s f15, f0, f5, f20 +fmadd.s f15, f0, f5, f25 +fmadd.s f15, f0, f5, f31 +fmadd.s f15, f0, f10, f0 +fmadd.s f15, f0, f10, f1 +fmadd.s f15, f0, f10, f5 +fmadd.s f15, f0, f10, f10 +fmadd.s f15, f0, f10, f15 +fmadd.s f15, f0, f10, f20 +fmadd.s f15, f0, f10, f25 +fmadd.s f15, f0, f10, f31 +fmadd.s f15, f0, f15, f0 +fmadd.s f15, f0, f15, f1 +fmadd.s f15, f0, f15, f5 +fmadd.s f15, f0, f15, f10 +fmadd.s f15, f0, f15, f15 +fmadd.s f15, f0, f15, f20 +fmadd.s f15, f0, f15, f25 +fmadd.s f15, f0, f15, f31 +fmadd.s f15, f0, f20, f0 +fmadd.s f15, f0, f20, f1 +fmadd.s f15, f0, f20, f5 +fmadd.s f15, f0, f20, f10 +fmadd.s f15, f0, f20, f15 +fmadd.s f15, f0, f20, f20 +fmadd.s f15, f0, f20, f25 +fmadd.s f15, f0, f20, f31 +fmadd.s f15, f0, f25, f0 +fmadd.s f15, f0, f25, f1 +fmadd.s f15, f0, f25, f5 +fmadd.s f15, f0, f25, f10 +fmadd.s f15, f0, f25, f15 +fmadd.s f15, f0, f25, f20 +fmadd.s f15, f0, f25, f25 +fmadd.s f15, f0, f25, f31 +fmadd.s f15, f0, f31, f0 +fmadd.s f15, f0, f31, f1 +fmadd.s f15, f0, f31, f5 +fmadd.s f15, f0, f31, f10 +fmadd.s f15, f0, f31, f15 +fmadd.s f15, f0, f31, f20 +fmadd.s f15, f0, f31, f25 +fmadd.s f15, f0, f31, f31 +fmadd.s f15, f1, f0, f0 +fmadd.s f15, f1, f0, f1 +fmadd.s f15, f1, f0, f5 +fmadd.s f15, f1, f0, f10 +fmadd.s f15, f1, f0, f15 +fmadd.s f15, f1, f0, f20 +fmadd.s f15, f1, f0, f25 +fmadd.s f15, f1, f0, f31 +fmadd.s f15, f1, f1, f0 +fmadd.s f15, f1, f1, f1 +fmadd.s f15, f1, f1, f5 +fmadd.s f15, f1, f1, f10 +fmadd.s f15, f1, f1, f15 +fmadd.s f15, f1, f1, f20 +fmadd.s f15, f1, f1, f25 +fmadd.s f15, f1, f1, f31 +fmadd.s f15, f1, f5, f0 +fmadd.s f15, f1, f5, f1 +fmadd.s f15, f1, f5, f5 +fmadd.s f15, f1, f5, f10 +fmadd.s f15, f1, f5, f15 +fmadd.s f15, f1, f5, f20 +fmadd.s f15, f1, f5, f25 +fmadd.s f15, f1, f5, f31 +fmadd.s f15, f1, f10, f0 +fmadd.s f15, f1, f10, f1 +fmadd.s f15, f1, f10, f5 +fmadd.s f15, f1, f10, f10 +fmadd.s f15, f1, f10, f15 +fmadd.s f15, f1, f10, f20 +fmadd.s f15, f1, f10, f25 +fmadd.s f15, f1, f10, f31 +fmadd.s f15, f1, f15, f0 +fmadd.s f15, f1, f15, f1 +fmadd.s f15, f1, f15, f5 +fmadd.s f15, f1, f15, f10 +fmadd.s f15, f1, f15, f15 +fmadd.s f15, f1, f15, f20 +fmadd.s f15, f1, f15, f25 +fmadd.s f15, f1, f15, f31 +fmadd.s f15, f1, f20, f0 +fmadd.s f15, f1, f20, f1 +fmadd.s f15, f1, f20, f5 +fmadd.s f15, f1, f20, f10 +fmadd.s f15, f1, f20, f15 +fmadd.s f15, f1, f20, f20 +fmadd.s f15, f1, f20, f25 +fmadd.s f15, f1, f20, f31 +fmadd.s f15, f1, f25, f0 +fmadd.s f15, f1, f25, f1 +fmadd.s f15, f1, f25, f5 +fmadd.s f15, f1, f25, f10 +fmadd.s f15, f1, f25, f15 +fmadd.s f15, f1, f25, f20 +fmadd.s f15, f1, f25, f25 +fmadd.s f15, f1, f25, f31 +fmadd.s f15, f1, f31, f0 +fmadd.s f15, f1, f31, f1 +fmadd.s f15, f1, f31, f5 +fmadd.s f15, f1, f31, f10 +fmadd.s f15, f1, f31, f15 +fmadd.s f15, f1, f31, f20 +fmadd.s f15, f1, f31, f25 +fmadd.s f15, f1, f31, f31 +fmadd.s f15, f5, f0, f0 +fmadd.s f15, f5, f0, f1 +fmadd.s f15, f5, f0, f5 +fmadd.s f15, f5, f0, f10 +fmadd.s f15, f5, f0, f15 +fmadd.s f15, f5, f0, f20 +fmadd.s f15, f5, f0, f25 +fmadd.s f15, f5, f0, f31 +fmadd.s f15, f5, f1, f0 +fmadd.s f15, f5, f1, f1 +fmadd.s f15, f5, f1, f5 +fmadd.s f15, f5, f1, f10 +fmadd.s f15, f5, f1, f15 +fmadd.s f15, f5, f1, f20 +fmadd.s f15, f5, f1, f25 +fmadd.s f15, f5, f1, f31 +fmadd.s f15, f5, f5, f0 +fmadd.s f15, f5, f5, f1 +fmadd.s f15, f5, f5, f5 +fmadd.s f15, f5, f5, f10 +fmadd.s f15, f5, f5, f15 +fmadd.s f15, f5, f5, f20 +fmadd.s f15, f5, f5, f25 +fmadd.s f15, f5, f5, f31 +fmadd.s f15, f5, f10, f0 +fmadd.s f15, f5, f10, f1 +fmadd.s f15, f5, f10, f5 +fmadd.s f15, f5, f10, f10 +fmadd.s f15, f5, f10, f15 +fmadd.s f15, f5, f10, f20 +fmadd.s f15, f5, f10, f25 +fmadd.s f15, f5, f10, f31 +fmadd.s f15, f5, f15, f0 +fmadd.s f15, f5, f15, f1 +fmadd.s f15, f5, f15, f5 +fmadd.s f15, f5, f15, f10 +fmadd.s f15, f5, f15, f15 +fmadd.s f15, f5, f15, f20 +fmadd.s f15, f5, f15, f25 +fmadd.s f15, f5, f15, f31 +fmadd.s f15, f5, f20, f0 +fmadd.s f15, f5, f20, f1 +fmadd.s f15, f5, f20, f5 +fmadd.s f15, f5, f20, f10 +fmadd.s f15, f5, f20, f15 +fmadd.s f15, f5, f20, f20 +fmadd.s f15, f5, f20, f25 +fmadd.s f15, f5, f20, f31 +fmadd.s f15, f5, f25, f0 +fmadd.s f15, f5, f25, f1 +fmadd.s f15, f5, f25, f5 +fmadd.s f15, f5, f25, f10 +fmadd.s f15, f5, f25, f15 +fmadd.s f15, f5, f25, f20 +fmadd.s f15, f5, f25, f25 +fmadd.s f15, f5, f25, f31 +fmadd.s f15, f5, f31, f0 +fmadd.s f15, f5, f31, f1 +fmadd.s f15, f5, f31, f5 +fmadd.s f15, f5, f31, f10 +fmadd.s f15, f5, f31, f15 +fmadd.s f15, f5, f31, f20 +fmadd.s f15, f5, f31, f25 +fmadd.s f15, f5, f31, f31 +fmadd.s f15, f10, f0, f0 +fmadd.s f15, f10, f0, f1 +fmadd.s f15, f10, f0, f5 +fmadd.s f15, f10, f0, f10 +fmadd.s f15, f10, f0, f15 +fmadd.s f15, f10, f0, f20 +fmadd.s f15, f10, f0, f25 +fmadd.s f15, f10, f0, f31 +fmadd.s f15, f10, f1, f0 +fmadd.s f15, f10, f1, f1 +fmadd.s f15, f10, f1, f5 +fmadd.s f15, f10, f1, f10 +fmadd.s f15, f10, f1, f15 +fmadd.s f15, f10, f1, f20 +fmadd.s f15, f10, f1, f25 +fmadd.s f15, f10, f1, f31 +fmadd.s f15, f10, f5, f0 +fmadd.s f15, f10, f5, f1 +fmadd.s f15, f10, f5, f5 +fmadd.s f15, f10, f5, f10 +fmadd.s f15, f10, f5, f15 +fmadd.s f15, f10, f5, f20 +fmadd.s f15, f10, f5, f25 +fmadd.s f15, f10, f5, f31 +fmadd.s f15, f10, f10, f0 +fmadd.s f15, f10, f10, f1 +fmadd.s f15, f10, f10, f5 +fmadd.s f15, f10, f10, f10 +fmadd.s f15, f10, f10, f15 +fmadd.s f15, f10, f10, f20 +fmadd.s f15, f10, f10, f25 +fmadd.s f15, f10, f10, f31 +fmadd.s f15, f10, f15, f0 +fmadd.s f15, f10, f15, f1 +fmadd.s f15, f10, f15, f5 +fmadd.s f15, f10, f15, f10 +fmadd.s f15, f10, f15, f15 +fmadd.s f15, f10, f15, f20 +fmadd.s f15, f10, f15, f25 +fmadd.s f15, f10, f15, f31 +fmadd.s f15, f10, f20, f0 +fmadd.s f15, f10, f20, f1 +fmadd.s f15, f10, f20, f5 +fmadd.s f15, f10, f20, f10 +fmadd.s f15, f10, f20, f15 +fmadd.s f15, f10, f20, f20 +fmadd.s f15, f10, f20, f25 +fmadd.s f15, f10, f20, f31 +fmadd.s f15, f10, f25, f0 +fmadd.s f15, f10, f25, f1 +fmadd.s f15, f10, f25, f5 +fmadd.s f15, f10, f25, f10 +fmadd.s f15, f10, f25, f15 +fmadd.s f15, f10, f25, f20 +fmadd.s f15, f10, f25, f25 +fmadd.s f15, f10, f25, f31 +fmadd.s f15, f10, f31, f0 +fmadd.s f15, f10, f31, f1 +fmadd.s f15, f10, f31, f5 +fmadd.s f15, f10, f31, f10 +fmadd.s f15, f10, f31, f15 +fmadd.s f15, f10, f31, f20 +fmadd.s f15, f10, f31, f25 +fmadd.s f15, f10, f31, f31 +fmadd.s f15, f15, f0, f0 +fmadd.s f15, f15, f0, f1 +fmadd.s f15, f15, f0, f5 +fmadd.s f15, f15, f0, f10 +fmadd.s f15, f15, f0, f15 +fmadd.s f15, f15, f0, f20 +fmadd.s f15, f15, f0, f25 +fmadd.s f15, f15, f0, f31 +fmadd.s f15, f15, f1, f0 +fmadd.s f15, f15, f1, f1 +fmadd.s f15, f15, f1, f5 +fmadd.s f15, f15, f1, f10 +fmadd.s f15, f15, f1, f15 +fmadd.s f15, f15, f1, f20 +fmadd.s f15, f15, f1, f25 +fmadd.s f15, f15, f1, f31 +fmadd.s f15, f15, f5, f0 +fmadd.s f15, f15, f5, f1 +fmadd.s f15, f15, f5, f5 +fmadd.s f15, f15, f5, f10 +fmadd.s f15, f15, f5, f15 +fmadd.s f15, f15, f5, f20 +fmadd.s f15, f15, f5, f25 +fmadd.s f15, f15, f5, f31 +fmadd.s f15, f15, f10, f0 +fmadd.s f15, f15, f10, f1 +fmadd.s f15, f15, f10, f5 +fmadd.s f15, f15, f10, f10 +fmadd.s f15, f15, f10, f15 +fmadd.s f15, f15, f10, f20 +fmadd.s f15, f15, f10, f25 +fmadd.s f15, f15, f10, f31 +fmadd.s f15, f15, f15, f0 +fmadd.s f15, f15, f15, f1 +fmadd.s f15, f15, f15, f5 +fmadd.s f15, f15, f15, f10 +fmadd.s f15, f15, f15, f15 +fmadd.s f15, f15, f15, f20 +fmadd.s f15, f15, f15, f25 +fmadd.s f15, f15, f15, f31 +fmadd.s f15, f15, f20, f0 +fmadd.s f15, f15, f20, f1 +fmadd.s f15, f15, f20, f5 +fmadd.s f15, f15, f20, f10 +fmadd.s f15, f15, f20, f15 +fmadd.s f15, f15, f20, f20 +fmadd.s f15, f15, f20, f25 +fmadd.s f15, f15, f20, f31 +fmadd.s f15, f15, f25, f0 +fmadd.s f15, f15, f25, f1 +fmadd.s f15, f15, f25, f5 +fmadd.s f15, f15, f25, f10 +fmadd.s f15, f15, f25, f15 +fmadd.s f15, f15, f25, f20 +fmadd.s f15, f15, f25, f25 +fmadd.s f15, f15, f25, f31 +fmadd.s f15, f15, f31, f0 +fmadd.s f15, f15, f31, f1 +fmadd.s f15, f15, f31, f5 +fmadd.s f15, f15, f31, f10 +fmadd.s f15, f15, f31, f15 +fmadd.s f15, f15, f31, f20 +fmadd.s f15, f15, f31, f25 +fmadd.s f15, f15, f31, f31 +fmadd.s f15, f20, f0, f0 +fmadd.s f15, f20, f0, f1 +fmadd.s f15, f20, f0, f5 +fmadd.s f15, f20, f0, f10 +fmadd.s f15, f20, f0, f15 +fmadd.s f15, f20, f0, f20 +fmadd.s f15, f20, f0, f25 +fmadd.s f15, f20, f0, f31 +fmadd.s f15, f20, f1, f0 +fmadd.s f15, f20, f1, f1 +fmadd.s f15, f20, f1, f5 +fmadd.s f15, f20, f1, f10 +fmadd.s f15, f20, f1, f15 +fmadd.s f15, f20, f1, f20 +fmadd.s f15, f20, f1, f25 +fmadd.s f15, f20, f1, f31 +fmadd.s f15, f20, f5, f0 +fmadd.s f15, f20, f5, f1 +fmadd.s f15, f20, f5, f5 +fmadd.s f15, f20, f5, f10 +fmadd.s f15, f20, f5, f15 +fmadd.s f15, f20, f5, f20 +fmadd.s f15, f20, f5, f25 +fmadd.s f15, f20, f5, f31 +fmadd.s f15, f20, f10, f0 +fmadd.s f15, f20, f10, f1 +fmadd.s f15, f20, f10, f5 +fmadd.s f15, f20, f10, f10 +fmadd.s f15, f20, f10, f15 +fmadd.s f15, f20, f10, f20 +fmadd.s f15, f20, f10, f25 +fmadd.s f15, f20, f10, f31 +fmadd.s f15, f20, f15, f0 +fmadd.s f15, f20, f15, f1 +fmadd.s f15, f20, f15, f5 +fmadd.s f15, f20, f15, f10 +fmadd.s f15, f20, f15, f15 +fmadd.s f15, f20, f15, f20 +fmadd.s f15, f20, f15, f25 +fmadd.s f15, f20, f15, f31 +fmadd.s f15, f20, f20, f0 +fmadd.s f15, f20, f20, f1 +fmadd.s f15, f20, f20, f5 +fmadd.s f15, f20, f20, f10 +fmadd.s f15, f20, f20, f15 +fmadd.s f15, f20, f20, f20 +fmadd.s f15, f20, f20, f25 +fmadd.s f15, f20, f20, f31 +fmadd.s f15, f20, f25, f0 +fmadd.s f15, f20, f25, f1 +fmadd.s f15, f20, f25, f5 +fmadd.s f15, f20, f25, f10 +fmadd.s f15, f20, f25, f15 +fmadd.s f15, f20, f25, f20 +fmadd.s f15, f20, f25, f25 +fmadd.s f15, f20, f25, f31 +fmadd.s f15, f20, f31, f0 +fmadd.s f15, f20, f31, f1 +fmadd.s f15, f20, f31, f5 +fmadd.s f15, f20, f31, f10 +fmadd.s f15, f20, f31, f15 +fmadd.s f15, f20, f31, f20 +fmadd.s f15, f20, f31, f25 +fmadd.s f15, f20, f31, f31 +fmadd.s f15, f25, f0, f0 +fmadd.s f15, f25, f0, f1 +fmadd.s f15, f25, f0, f5 +fmadd.s f15, f25, f0, f10 +fmadd.s f15, f25, f0, f15 +fmadd.s f15, f25, f0, f20 +fmadd.s f15, f25, f0, f25 +fmadd.s f15, f25, f0, f31 +fmadd.s f15, f25, f1, f0 +fmadd.s f15, f25, f1, f1 +fmadd.s f15, f25, f1, f5 +fmadd.s f15, f25, f1, f10 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f31, f10 +fmadd.s f31, f1, f31, f15 +fmadd.s f31, f1, f31, f20 +fmadd.s f31, f1, f31, f25 +fmadd.s f31, f1, f31, f31 +fmadd.s f31, f5, f0, f0 +fmadd.s f31, f5, f0, f1 +fmadd.s f31, f5, f0, f5 +fmadd.s f31, f5, f0, f10 +fmadd.s f31, f5, f0, f15 +fmadd.s f31, f5, f0, f20 +fmadd.s f31, f5, f0, f25 +fmadd.s f31, f5, f0, f31 +fmadd.s f31, f5, f1, f0 +fmadd.s f31, f5, f1, f1 +fmadd.s f31, f5, f1, f5 +fmadd.s f31, f5, f1, f10 +fmadd.s f31, f5, f1, f15 +fmadd.s f31, f5, f1, f20 +fmadd.s f31, f5, f1, f25 +fmadd.s f31, f5, f1, f31 +fmadd.s f31, f5, f5, f0 +fmadd.s f31, f5, f5, f1 +fmadd.s f31, f5, f5, f5 +fmadd.s f31, f5, f5, f10 +fmadd.s f31, f5, f5, f15 +fmadd.s f31, f5, f5, f20 +fmadd.s f31, f5, f5, f25 +fmadd.s f31, f5, f5, f31 +fmadd.s f31, f5, f10, f0 +fmadd.s f31, f5, f10, f1 +fmadd.s f31, f5, f10, f5 +fmadd.s f31, f5, f10, f10 +fmadd.s f31, f5, f10, f15 +fmadd.s f31, f5, f10, f20 +fmadd.s f31, f5, f10, f25 +fmadd.s f31, f5, f10, f31 +fmadd.s f31, f5, f15, f0 +fmadd.s f31, f5, f15, f1 +fmadd.s f31, f5, f15, f5 +fmadd.s f31, f5, f15, f10 +fmadd.s f31, f5, f15, f15 +fmadd.s f31, f5, f15, f20 +fmadd.s f31, f5, f15, f25 +fmadd.s f31, f5, f15, f31 +fmadd.s f31, f5, f20, f0 +fmadd.s f31, f5, f20, f1 +fmadd.s f31, f5, f20, f5 +fmadd.s f31, f5, f20, f10 +fmadd.s f31, f5, f20, f15 +fmadd.s f31, f5, f20, f20 +fmadd.s f31, f5, f20, f25 +fmadd.s f31, f5, f20, f31 +fmadd.s f31, f5, f25, f0 +fmadd.s f31, f5, f25, f1 +fmadd.s f31, f5, f25, f5 +fmadd.s f31, f5, f25, f10 +fmadd.s f31, f5, f25, f15 +fmadd.s f31, f5, f25, f20 +fmadd.s f31, f5, f25, f25 +fmadd.s f31, f5, f25, f31 +fmadd.s f31, f5, f31, f0 +fmadd.s f31, f5, f31, f1 +fmadd.s f31, f5, f31, f5 +fmadd.s f31, f5, f31, f10 +fmadd.s f31, f5, f31, f15 +fmadd.s f31, f5, f31, f20 +fmadd.s f31, f5, f31, f25 +fmadd.s f31, f5, f31, f31 +fmadd.s f31, f10, f0, f0 +fmadd.s f31, f10, f0, f1 +fmadd.s f31, f10, f0, f5 +fmadd.s f31, f10, f0, f10 +fmadd.s f31, f10, f0, f15 +fmadd.s f31, f10, f0, f20 +fmadd.s f31, f10, f0, f25 +fmadd.s f31, f10, f0, f31 +fmadd.s f31, f10, f1, f0 +fmadd.s f31, f10, f1, f1 +fmadd.s f31, f10, f1, f5 +fmadd.s f31, f10, f1, f10 +fmadd.s f31, f10, f1, f15 +fmadd.s f31, f10, f1, f20 +fmadd.s f31, f10, f1, f25 +fmadd.s f31, f10, f1, f31 +fmadd.s f31, f10, f5, f0 +fmadd.s f31, f10, f5, f1 +fmadd.s f31, f10, f5, f5 +fmadd.s f31, f10, f5, f10 +fmadd.s f31, f10, f5, f15 +fmadd.s f31, f10, f5, f20 +fmadd.s f31, f10, f5, f25 +fmadd.s f31, f10, f5, f31 +fmadd.s f31, f10, f10, f0 +fmadd.s f31, f10, f10, f1 +fmadd.s f31, f10, f10, f5 +fmadd.s f31, f10, f10, f10 +fmadd.s f31, f10, f10, f15 +fmadd.s f31, f10, f10, f20 +fmadd.s f31, f10, f10, f25 +fmadd.s f31, f10, f10, f31 +fmadd.s f31, f10, f15, f0 +fmadd.s f31, f10, f15, f1 +fmadd.s f31, f10, f15, f5 +fmadd.s f31, f10, f15, f10 +fmadd.s f31, f10, f15, f15 +fmadd.s f31, f10, f15, f20 +fmadd.s f31, f10, f15, f25 +fmadd.s f31, f10, f15, f31 +fmadd.s f31, f10, f20, f0 +fmadd.s f31, f10, f20, f1 +fmadd.s f31, f10, f20, f5 +fmadd.s f31, f10, f20, f10 +fmadd.s f31, f10, f20, f15 +fmadd.s f31, f10, f20, f20 +fmadd.s f31, f10, f20, f25 +fmadd.s f31, f10, f20, f31 +fmadd.s f31, f10, f25, f0 +fmadd.s f31, f10, f25, f1 +fmadd.s f31, f10, f25, f5 +fmadd.s f31, f10, f25, f10 +fmadd.s f31, f10, f25, f15 +fmadd.s f31, f10, f25, f20 +fmadd.s f31, f10, f25, f25 +fmadd.s f31, f10, f25, f31 +fmadd.s f31, f10, f31, f0 +fmadd.s f31, f10, f31, f1 +fmadd.s f31, f10, f31, f5 +fmadd.s f31, f10, f31, f10 +fmadd.s f31, f10, f31, f15 +fmadd.s f31, f10, f31, f20 +fmadd.s f31, f10, f31, f25 +fmadd.s f31, f10, f31, f31 +fmadd.s f31, f15, f0, f0 +fmadd.s f31, f15, f0, f1 +fmadd.s f31, f15, f0, f5 +fmadd.s f31, f15, f0, f10 +fmadd.s f31, f15, f0, f15 +fmadd.s f31, f15, f0, f20 +fmadd.s f31, f15, f0, f25 +fmadd.s f31, f15, f0, f31 +fmadd.s f31, f15, f1, f0 +fmadd.s f31, f15, f1, f1 +fmadd.s f31, f15, f1, f5 +fmadd.s f31, f15, f1, f10 +fmadd.s f31, f15, f1, f15 +fmadd.s f31, f15, f1, f20 +fmadd.s f31, f15, f1, f25 +fmadd.s f31, f15, f1, f31 +fmadd.s f31, f15, f5, f0 +fmadd.s f31, f15, f5, f1 +fmadd.s f31, f15, f5, f5 +fmadd.s f31, f15, f5, f10 +fmadd.s f31, f15, f5, f15 +fmadd.s f31, f15, f5, f20 +fmadd.s f31, f15, f5, f25 +fmadd.s f31, f15, f5, f31 +fmadd.s f31, f15, f10, f0 +fmadd.s f31, f15, f10, f1 +fmadd.s f31, f15, f10, f5 +fmadd.s f31, f15, f10, f10 +fmadd.s f31, f15, f10, f15 +fmadd.s f31, f15, f10, f20 +fmadd.s f31, f15, f10, f25 +fmadd.s f31, f15, f10, f31 +fmadd.s f31, f15, f15, f0 +fmadd.s f31, f15, f15, f1 +fmadd.s f31, f15, f15, f5 +fmadd.s f31, f15, f15, f10 +fmadd.s f31, f15, f15, f15 +fmadd.s f31, f15, f15, f20 +fmadd.s f31, f15, f15, f25 +fmadd.s f31, f15, f15, f31 +fmadd.s f31, f15, f20, f0 +fmadd.s f31, f15, f20, f1 +fmadd.s f31, f15, f20, f5 +fmadd.s f31, f15, f20, f10 +fmadd.s f31, f15, f20, f15 +fmadd.s f31, f15, f20, f20 +fmadd.s f31, f15, f20, f25 +fmadd.s f31, f15, f20, f31 +fmadd.s f31, f15, f25, f0 +fmadd.s f31, f15, f25, f1 +fmadd.s f31, f15, f25, f5 +fmadd.s f31, f15, f25, f10 +fmadd.s f31, f15, f25, f15 +fmadd.s f31, f15, f25, f20 +fmadd.s f31, f15, f25, f25 +fmadd.s f31, f15, f25, f31 +fmadd.s f31, f15, f31, f0 +fmadd.s f31, f15, f31, f1 +fmadd.s f31, f15, f31, f5 +fmadd.s f31, f15, f31, f10 +fmadd.s f31, f15, f31, f15 +fmadd.s f31, f15, f31, f20 +fmadd.s f31, f15, f31, f25 +fmadd.s f31, f15, f31, f31 +fmadd.s f31, f20, f0, f0 +fmadd.s f31, f20, f0, f1 +fmadd.s f31, f20, f0, f5 +fmadd.s f31, f20, f0, f10 +fmadd.s f31, f20, f0, f15 +fmadd.s f31, f20, f0, f20 +fmadd.s f31, f20, f0, f25 +fmadd.s f31, f20, f0, f31 +fmadd.s f31, f20, f1, f0 +fmadd.s f31, f20, f1, f1 +fmadd.s f31, f20, f1, f5 +fmadd.s f31, f20, f1, f10 +fmadd.s f31, f20, f1, f15 +fmadd.s f31, f20, f1, f20 +fmadd.s f31, f20, f1, f25 +fmadd.s f31, f20, f1, f31 +fmadd.s f31, f20, f5, f0 +fmadd.s f31, f20, f5, f1 +fmadd.s f31, f20, f5, f5 +fmadd.s f31, f20, f5, f10 +fmadd.s f31, f20, f5, f15 +fmadd.s f31, f20, f5, f20 +fmadd.s f31, f20, f5, f25 +fmadd.s f31, f20, f5, f31 +fmadd.s f31, f20, f10, f0 +fmadd.s f31, f20, f10, f1 +fmadd.s f31, f20, f10, f5 +fmadd.s f31, f20, f10, f10 +fmadd.s f31, f20, f10, f15 +fmadd.s f31, f20, f10, f20 +fmadd.s f31, f20, f10, f25 +fmadd.s f31, f20, f10, f31 +fmadd.s f31, f20, f15, f0 +fmadd.s f31, f20, f15, f1 +fmadd.s f31, f20, f15, f5 +fmadd.s f31, f20, f15, f10 +fmadd.s f31, f20, f15, f15 +fmadd.s f31, f20, f15, f20 +fmadd.s f31, f20, f15, f25 +fmadd.s f31, f20, f15, f31 +fmadd.s f31, f20, f20, f0 +fmadd.s f31, f20, f20, f1 +fmadd.s f31, f20, f20, f5 +fmadd.s f31, f20, f20, f10 +fmadd.s f31, f20, f20, f15 +fmadd.s f31, f20, f20, f20 +fmadd.s f31, f20, f20, f25 +fmadd.s f31, f20, f20, f31 +fmadd.s f31, f20, f25, f0 +fmadd.s f31, f20, f25, f1 +fmadd.s f31, f20, f25, f5 +fmadd.s f31, f20, f25, f10 +fmadd.s f31, f20, f25, f15 +fmadd.s f31, f20, f25, f20 +fmadd.s f31, f20, f25, f25 +fmadd.s f31, f20, f25, f31 +fmadd.s f31, f20, f31, f0 +fmadd.s f31, f20, f31, f1 +fmadd.s f31, f20, f31, f5 +fmadd.s f31, f20, f31, f10 +fmadd.s f31, f20, f31, f15 +fmadd.s f31, f20, f31, f20 +fmadd.s f31, f20, f31, f25 +fmadd.s f31, f20, f31, f31 +fmadd.s f31, f25, f0, f0 +fmadd.s f31, f25, f0, f1 +fmadd.s f31, f25, f0, f5 +fmadd.s f31, f25, f0, f10 +fmadd.s f31, f25, f0, f15 +fmadd.s f31, f25, f0, f20 +fmadd.s f31, f25, f0, f25 +fmadd.s f31, f25, f0, f31 +fmadd.s f31, f25, f1, f0 +fmadd.s f31, f25, f1, f1 +fmadd.s f31, f25, f1, f5 +fmadd.s f31, f25, f1, f10 +fmadd.s f31, f25, f1, f15 +fmadd.s f31, f25, f1, f20 +fmadd.s f31, f25, f1, f25 +fmadd.s f31, f25, f1, f31 +fmadd.s f31, f25, f5, f0 +fmadd.s f31, f25, f5, f1 +fmadd.s f31, f25, f5, f5 +fmadd.s f31, f25, f5, f10 +fmadd.s f31, f25, f5, f15 +fmadd.s f31, f25, f5, f20 +fmadd.s f31, f25, f5, f25 +fmadd.s f31, f25, f5, f31 +fmadd.s f31, f25, f10, f0 +fmadd.s f31, f25, f10, f1 +fmadd.s f31, f25, f10, f5 +fmadd.s f31, f25, f10, f10 +fmadd.s f31, f25, f10, f15 +fmadd.s f31, f25, f10, f20 +fmadd.s f31, f25, f10, f25 +fmadd.s f31, f25, f10, f31 +fmadd.s f31, f25, f15, f0 +fmadd.s f31, f25, f15, f1 +fmadd.s f31, f25, f15, f5 +fmadd.s f31, f25, f15, f10 +fmadd.s f31, f25, f15, f15 +fmadd.s f31, f25, f15, f20 +fmadd.s f31, f25, f15, f25 +fmadd.s f31, f25, f15, f31 +fmadd.s f31, f25, f20, f0 +fmadd.s f31, f25, f20, f1 +fmadd.s f31, f25, f20, f5 +fmadd.s f31, f25, f20, f10 +fmadd.s f31, f25, f20, f15 +fmadd.s f31, f25, f20, f20 +fmadd.s f31, f25, f20, f25 +fmadd.s f31, f25, f20, f31 +fmadd.s f31, f25, f25, f0 +fmadd.s f31, f25, f25, f1 +fmadd.s f31, f25, f25, f5 +fmadd.s f31, f25, f25, f10 +fmadd.s f31, f25, f25, f15 +fmadd.s f31, f25, f25, f20 +fmadd.s f31, f25, f25, f25 +fmadd.s f31, f25, f25, f31 +fmadd.s f31, f25, f31, f0 +fmadd.s f31, f25, f31, f1 +fmadd.s f31, f25, f31, f5 +fmadd.s f31, f25, f31, f10 +fmadd.s f31, f25, f31, f15 +fmadd.s f31, f25, f31, f20 +fmadd.s f31, f25, f31, f25 +fmadd.s f31, f25, f31, f31 +fmadd.s f31, f31, f0, f0 +fmadd.s f31, f31, f0, f1 +fmadd.s f31, f31, f0, f5 +fmadd.s f31, f31, f0, f10 +fmadd.s f31, f31, f0, f15 +fmadd.s f31, f31, f0, f20 +fmadd.s f31, f31, f0, f25 +fmadd.s f31, f31, f0, f31 +fmadd.s f31, f31, f1, f0 +fmadd.s f31, f31, f1, f1 +fmadd.s f31, f31, f1, f5 +fmadd.s f31, f31, f1, f10 +fmadd.s f31, f31, f1, f15 +fmadd.s f31, f31, f1, f20 +fmadd.s f31, f31, f1, f25 +fmadd.s f31, f31, f1, f31 +fmadd.s f31, f31, f5, f0 +fmadd.s f31, f31, f5, f1 +fmadd.s f31, f31, f5, f5 +fmadd.s f31, f31, f5, f10 +fmadd.s f31, f31, f5, f15 +fmadd.s f31, f31, f5, f20 +fmadd.s f31, f31, f5, f25 +fmadd.s f31, f31, f5, f31 +fmadd.s f31, f31, f10, f0 +fmadd.s f31, f31, f10, f1 +fmadd.s f31, f31, f10, f5 +fmadd.s f31, f31, f10, f10 +fmadd.s f31, f31, f10, f15 +fmadd.s f31, f31, f10, f20 +fmadd.s f31, f31, f10, f25 +fmadd.s f31, f31, f10, f31 +fmadd.s f31, f31, f15, f0 +fmadd.s f31, f31, f15, f1 +fmadd.s f31, f31, f15, f5 +fmadd.s f31, f31, f15, f10 +fmadd.s f31, f31, f15, f15 +fmadd.s f31, f31, f15, f20 +fmadd.s f31, f31, f15, f25 +fmadd.s f31, f31, f15, f31 +fmadd.s f31, f31, f20, f0 +fmadd.s f31, f31, f20, f1 +fmadd.s f31, f31, f20, f5 +fmadd.s f31, f31, f20, f10 +fmadd.s f31, f31, f20, f15 +fmadd.s f31, f31, f20, f20 +fmadd.s f31, f31, f20, f25 +fmadd.s f31, f31, f20, f31 +fmadd.s f31, f31, f25, f0 +fmadd.s f31, f31, f25, f1 +fmadd.s f31, f31, f25, f5 +fmadd.s f31, f31, f25, f10 +fmadd.s f31, f31, f25, f15 +fmadd.s f31, f31, f25, f20 +fmadd.s f31, f31, f25, f25 +fmadd.s f31, f31, f25, f31 +fmadd.s f31, f31, f31, f0 +fmadd.s f31, f31, f31, f1 +fmadd.s f31, f31, f31, f5 +fmadd.s f31, f31, f31, f10 +fmadd.s f31, f31, f31, f15 +fmadd.s f31, f31, f31, f20 +fmadd.s f31, f31, f31, f25 +fmadd.s f31, f31, f31, f31 diff --git a/tests/riscv/f-extension/fmadd_s.asm b/tests/riscv/f-extension/fmadd_s.asm new file mode 100644 index 0000000..bb4e67c --- /dev/null +++ b/tests/riscv/f-extension/fmadd_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fmadd.s f0, f1, f2, f3 + diff --git a/tests/riscv/f-extension/fmadd_s.bin b/tests/riscv/f-extension/fmadd_s.bin new file mode 100644 index 0000000..2c7a0dd --- /dev/null +++ b/tests/riscv/f-extension/fmadd_s.bin @@ -0,0 +1 @@ +C  \ No newline at end of file diff --git a/tests/riscv/f-extension/fmadd_s.disasm b/tests/riscv/f-extension/fmadd_s.disasm new file mode 100644 index 0000000..c8025c6 --- /dev/null +++ b/tests/riscv/f-extension/fmadd_s.disasm @@ -0,0 +1 @@ +fmadd.s f0, f1, f2, f3 diff --git a/tests/riscv/f-extension/fmax.s.asm b/tests/riscv/f-extension/fmax.s.asm new file mode 100644 index 0000000..a8b76e7 --- /dev/null +++ b/tests/riscv/f-extension/fmax.s.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fmax.s f0, f0, f0 +fmax.s f0, f0, f1 +fmax.s f0, f0, f5 +fmax.s f0, f0, f10 +fmax.s f0, f0, f15 +fmax.s f0, f0, f20 +fmax.s f0, f0, f25 +fmax.s f0, f0, f31 +fmax.s f0, f1, f0 +fmax.s f0, f1, f1 +fmax.s f0, f1, f5 +fmax.s f0, f1, f10 +fmax.s f0, f1, f15 +fmax.s f0, f1, f20 +fmax.s f0, f1, f25 +fmax.s f0, f1, f31 +fmax.s f0, f5, f0 +fmax.s f0, f5, f1 +fmax.s f0, f5, f5 +fmax.s f0, f5, f10 +fmax.s f0, f5, f15 +fmax.s f0, f5, f20 +fmax.s f0, f5, f25 +fmax.s f0, f5, f31 +fmax.s f0, f10, f0 +fmax.s f0, f10, f1 +fmax.s f0, f10, f5 +fmax.s f0, f10, f10 +fmax.s f0, f10, f15 +fmax.s f0, f10, f20 +fmax.s f0, f10, f25 +fmax.s f0, f10, f31 +fmax.s f0, f15, f0 +fmax.s f0, f15, f1 +fmax.s f0, f15, f5 +fmax.s f0, f15, f10 +fmax.s f0, f15, f15 +fmax.s f0, f15, f20 +fmax.s f0, f15, f25 +fmax.s f0, f15, f31 +fmax.s f0, f20, f0 +fmax.s f0, f20, f1 +fmax.s f0, f20, f5 +fmax.s f0, f20, f10 +fmax.s f0, f20, f15 +fmax.s f0, f20, f20 +fmax.s f0, f20, f25 +fmax.s f0, f20, f31 +fmax.s f0, f25, f0 +fmax.s f0, f25, f1 +fmax.s f0, f25, f5 +fmax.s f0, f25, f10 +fmax.s f0, f25, f15 +fmax.s f0, f25, f20 +fmax.s f0, f25, f25 +fmax.s f0, f25, f31 +fmax.s f0, f31, f0 +fmax.s f0, f31, f1 +fmax.s f0, f31, f5 +fmax.s f0, f31, f10 +fmax.s f0, f31, f15 +fmax.s f0, f31, f20 +fmax.s f0, f31, f25 +fmax.s f0, f31, f31 +fmax.s f1, f0, f0 +fmax.s f1, f0, f1 +fmax.s f1, f0, f5 +fmax.s f1, f0, f10 +fmax.s f1, f0, f15 +fmax.s f1, f0, f20 +fmax.s f1, f0, f25 +fmax.s f1, f0, f31 +fmax.s f1, f1, f0 +fmax.s f1, f1, f1 +fmax.s f1, f1, f5 +fmax.s f1, f1, f10 +fmax.s f1, f1, f15 +fmax.s f1, f1, f20 +fmax.s f1, f1, f25 +fmax.s f1, f1, f31 +fmax.s f1, f5, f0 +fmax.s f1, f5, f1 +fmax.s f1, f5, f5 +fmax.s f1, f5, f10 +fmax.s f1, f5, f15 +fmax.s f1, f5, f20 +fmax.s f1, f5, f25 +fmax.s f1, f5, f31 +fmax.s f1, f10, f0 +fmax.s f1, f10, f1 +fmax.s f1, f10, f5 +fmax.s f1, f10, f10 +fmax.s f1, f10, f15 +fmax.s f1, f10, f20 +fmax.s f1, f10, f25 +fmax.s f1, f10, f31 +fmax.s f1, f15, f0 +fmax.s f1, f15, f1 +fmax.s f1, f15, f5 +fmax.s f1, f15, f10 +fmax.s f1, f15, f15 +fmax.s f1, f15, f20 +fmax.s f1, f15, f25 +fmax.s f1, f15, f31 +fmax.s f1, f20, f0 +fmax.s f1, f20, f1 +fmax.s f1, f20, f5 +fmax.s f1, f20, f10 +fmax.s f1, f20, f15 +fmax.s f1, f20, f20 +fmax.s f1, f20, f25 +fmax.s f1, f20, f31 +fmax.s f1, f25, f0 +fmax.s f1, f25, f1 +fmax.s f1, f25, f5 +fmax.s f1, f25, f10 +fmax.s f1, f25, f15 +fmax.s f1, f25, f20 +fmax.s f1, f25, f25 +fmax.s f1, f25, f31 +fmax.s f1, f31, f0 +fmax.s f1, f31, f1 +fmax.s f1, f31, f5 +fmax.s f1, f31, f10 +fmax.s f1, f31, f15 +fmax.s f1, f31, f20 +fmax.s f1, f31, f25 +fmax.s f1, f31, f31 +fmax.s f5, f0, f0 +fmax.s f5, f0, f1 +fmax.s f5, f0, f5 +fmax.s f5, f0, f10 +fmax.s f5, f0, f15 +fmax.s f5, f0, f20 +fmax.s f5, f0, f25 +fmax.s f5, f0, f31 +fmax.s f5, f1, f0 +fmax.s f5, f1, f1 +fmax.s f5, f1, f5 +fmax.s f5, f1, f10 +fmax.s f5, f1, f15 +fmax.s f5, f1, f20 +fmax.s f5, f1, f25 +fmax.s f5, f1, f31 +fmax.s f5, f5, f0 +fmax.s f5, f5, f1 +fmax.s f5, f5, f5 +fmax.s f5, f5, f10 +fmax.s f5, f5, f15 +fmax.s f5, f5, f20 +fmax.s f5, f5, f25 +fmax.s f5, f5, f31 +fmax.s f5, f10, f0 +fmax.s f5, f10, f1 +fmax.s f5, f10, f5 +fmax.s f5, f10, f10 +fmax.s f5, f10, f15 +fmax.s f5, f10, f20 +fmax.s f5, f10, f25 +fmax.s f5, f10, f31 +fmax.s f5, f15, f0 +fmax.s f5, f15, f1 +fmax.s f5, f15, f5 +fmax.s f5, f15, f10 +fmax.s f5, f15, f15 +fmax.s f5, f15, f20 +fmax.s f5, f15, f25 +fmax.s f5, f15, f31 +fmax.s f5, f20, f0 +fmax.s f5, f20, f1 +fmax.s f5, f20, f5 +fmax.s f5, f20, f10 +fmax.s f5, f20, f15 +fmax.s f5, f20, f20 +fmax.s f5, f20, f25 +fmax.s f5, f20, f31 +fmax.s f5, f25, f0 +fmax.s f5, f25, f1 +fmax.s f5, f25, f5 +fmax.s f5, f25, f10 +fmax.s f5, f25, f15 +fmax.s f5, f25, f20 +fmax.s f5, f25, f25 +fmax.s f5, f25, f31 +fmax.s f5, f31, f0 +fmax.s f5, f31, f1 +fmax.s f5, f31, f5 +fmax.s f5, f31, f10 +fmax.s f5, f31, f15 +fmax.s f5, f31, f20 +fmax.s f5, f31, f25 +fmax.s f5, f31, f31 +fmax.s f10, f0, f0 +fmax.s f10, f0, f1 +fmax.s f10, f0, f5 +fmax.s f10, f0, f10 +fmax.s f10, f0, f15 +fmax.s f10, f0, f20 +fmax.s f10, f0, f25 +fmax.s f10, f0, f31 +fmax.s f10, f1, f0 +fmax.s f10, f1, f1 +fmax.s f10, f1, f5 +fmax.s f10, f1, f10 +fmax.s f10, f1, f15 +fmax.s f10, f1, f20 +fmax.s f10, f1, f25 +fmax.s f10, f1, f31 +fmax.s f10, f5, f0 +fmax.s f10, f5, f1 +fmax.s f10, f5, f5 +fmax.s f10, f5, f10 +fmax.s f10, f5, f15 +fmax.s f10, f5, f20 +fmax.s f10, f5, f25 +fmax.s f10, f5, f31 +fmax.s f10, f10, f0 +fmax.s f10, f10, f1 +fmax.s f10, f10, f5 +fmax.s f10, f10, f10 +fmax.s f10, f10, f15 +fmax.s f10, f10, f20 +fmax.s f10, f10, f25 +fmax.s f10, f10, f31 +fmax.s f10, f15, f0 +fmax.s f10, f15, f1 +fmax.s f10, f15, f5 +fmax.s f10, f15, f10 +fmax.s f10, f15, f15 +fmax.s f10, f15, f20 +fmax.s f10, f15, f25 +fmax.s f10, f15, f31 +fmax.s f10, f20, f0 +fmax.s f10, f20, f1 +fmax.s f10, f20, f5 +fmax.s f10, f20, f10 +fmax.s f10, f20, f15 +fmax.s f10, f20, f20 +fmax.s f10, f20, f25 +fmax.s f10, f20, f31 +fmax.s f10, f25, f0 +fmax.s f10, f25, f1 +fmax.s f10, f25, f5 +fmax.s f10, f25, f10 +fmax.s f10, f25, f15 +fmax.s f10, f25, f20 +fmax.s f10, f25, f25 +fmax.s f10, f25, f31 +fmax.s f10, f31, f0 +fmax.s f10, f31, f1 +fmax.s f10, f31, f5 +fmax.s f10, f31, f10 +fmax.s f10, f31, f15 +fmax.s f10, f31, f20 +fmax.s f10, f31, f25 +fmax.s f10, f31, f31 +fmax.s f15, f0, f0 +fmax.s f15, f0, f1 +fmax.s f15, f0, f5 +fmax.s f15, f0, f10 +fmax.s f15, f0, f15 +fmax.s f15, f0, f20 +fmax.s f15, f0, f25 +fmax.s f15, f0, f31 +fmax.s f15, f1, f0 +fmax.s f15, f1, f1 +fmax.s f15, f1, f5 +fmax.s f15, f1, f10 +fmax.s f15, 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f31, f10, f20 +fmin.s f31, f10, f25 +fmin.s f31, f10, f31 +fmin.s f31, f15, f0 +fmin.s f31, f15, f1 +fmin.s f31, f15, f5 +fmin.s f31, f15, f10 +fmin.s f31, f15, f15 +fmin.s f31, f15, f20 +fmin.s f31, f15, f25 +fmin.s f31, f15, f31 +fmin.s f31, f20, f0 +fmin.s f31, f20, f1 +fmin.s f31, f20, f5 +fmin.s f31, f20, f10 +fmin.s f31, f20, f15 +fmin.s f31, f20, f20 +fmin.s f31, f20, f25 +fmin.s f31, f20, f31 +fmin.s f31, f25, f0 +fmin.s f31, f25, f1 +fmin.s f31, f25, f5 +fmin.s f31, f25, f10 +fmin.s f31, f25, f15 +fmin.s f31, f25, f20 +fmin.s f31, f25, f25 +fmin.s f31, f25, f31 +fmin.s f31, f31, f0 +fmin.s f31, f31, f1 +fmin.s f31, f31, f5 +fmin.s f31, f31, f10 +fmin.s f31, f31, f15 +fmin.s f31, f31, f20 +fmin.s f31, f31, f25 +fmin.s f31, f31, f31 diff --git a/tests/riscv/f-extension/fmin_s.asm b/tests/riscv/f-extension/fmin_s.asm new file mode 100644 index 0000000..bfd068d --- /dev/null +++ b/tests/riscv/f-extension/fmin_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fmin.s f0, f1, f2 + diff --git a/tests/riscv/f-extension/fmin_s.bin b/tests/riscv/f-extension/fmin_s.bin new file mode 100644 index 0000000..99e895f --- /dev/null +++ b/tests/riscv/f-extension/fmin_s.bin @@ -0,0 +1 @@ +S ( \ No newline at end of file diff --git a/tests/riscv/f-extension/fmin_s.disasm b/tests/riscv/f-extension/fmin_s.disasm new file mode 100644 index 0000000..b7bb3cf --- /dev/null +++ b/tests/riscv/f-extension/fmin_s.disasm @@ -0,0 +1 @@ +fmin.s f0, f1, f2 diff --git a/tests/riscv/f-extension/fmsub.s.asm b/tests/riscv/f-extension/fmsub.s.asm new file mode 100644 index 0000000..2a93354 --- /dev/null +++ b/tests/riscv/f-extension/fmsub.s.asm @@ -0,0 +1,4100 @@ +.lang riscv32 +.org 0x0 + +fmsub.s f0, f0, f0, f0 +fmsub.s f0, f0, f0, f1 +fmsub.s f0, f0, f0, f5 +fmsub.s f0, f0, f0, f10 +fmsub.s f0, f0, f0, f15 +fmsub.s f0, f0, f0, f20 +fmsub.s f0, f0, f0, f25 +fmsub.s f0, f0, f0, f31 +fmsub.s f0, f0, f1, f0 +fmsub.s f0, f0, f1, f1 +fmsub.s f0, f0, f1, f5 +fmsub.s f0, f0, f1, f10 +fmsub.s f0, f0, f1, f15 +fmsub.s f0, f0, f1, f20 +fmsub.s f0, f0, f1, f25 +fmsub.s f0, f0, f1, f31 +fmsub.s f0, f0, f5, f0 +fmsub.s f0, f0, f5, f1 +fmsub.s f0, f0, f5, f5 +fmsub.s f0, f0, f5, f10 +fmsub.s f0, f0, f5, f15 +fmsub.s f0, f0, f5, f20 +fmsub.s f0, f0, f5, f25 +fmsub.s f0, f0, f5, f31 +fmsub.s f0, f0, f10, f0 +fmsub.s f0, f0, f10, f1 +fmsub.s f0, f0, f10, f5 +fmsub.s f0, f0, f10, f10 +fmsub.s f0, f0, f10, f15 +fmsub.s f0, f0, f10, f20 +fmsub.s f0, f0, f10, f25 +fmsub.s f0, f0, f10, f31 +fmsub.s f0, f0, f15, f0 +fmsub.s f0, f0, f15, f1 +fmsub.s f0, f0, f15, f5 +fmsub.s f0, f0, f15, f10 +fmsub.s f0, f0, f15, f15 +fmsub.s f0, f0, f15, f20 +fmsub.s f0, f0, f15, f25 +fmsub.s f0, f0, f15, f31 +fmsub.s f0, f0, f20, f0 +fmsub.s f0, f0, f20, f1 +fmsub.s f0, f0, f20, f5 +fmsub.s f0, f0, f20, f10 +fmsub.s f0, f0, f20, f15 +fmsub.s f0, f0, f20, f20 +fmsub.s f0, f0, f20, f25 +fmsub.s f0, f0, f20, f31 +fmsub.s f0, f0, f25, f0 +fmsub.s f0, f0, f25, f1 +fmsub.s f0, f0, f25, f5 +fmsub.s f0, f0, f25, f10 +fmsub.s f0, f0, f25, f15 +fmsub.s f0, f0, f25, f20 +fmsub.s f0, f0, f25, f25 +fmsub.s f0, f0, f25, f31 +fmsub.s f0, f0, f31, f0 +fmsub.s f0, f0, f31, f1 +fmsub.s f0, f0, f31, f5 +fmsub.s f0, f0, f31, f10 +fmsub.s f0, f0, f31, f15 +fmsub.s f0, f0, f31, f20 +fmsub.s f0, f0, f31, f25 +fmsub.s f0, f0, f31, f31 +fmsub.s f0, f1, f0, f0 +fmsub.s f0, f1, f0, f1 +fmsub.s f0, f1, f0, f5 +fmsub.s f0, f1, f0, f10 +fmsub.s f0, f1, f0, f15 +fmsub.s f0, f1, f0, f20 +fmsub.s f0, f1, f0, f25 +fmsub.s f0, f1, f0, f31 +fmsub.s f0, f1, f1, f0 +fmsub.s f0, f1, f1, f1 +fmsub.s f0, f1, f1, f5 +fmsub.s f0, f1, f1, f10 +fmsub.s f0, f1, f1, f15 +fmsub.s f0, f1, f1, f20 +fmsub.s f0, f1, f1, f25 +fmsub.s f0, f1, f1, f31 +fmsub.s f0, f1, f5, f0 +fmsub.s f0, f1, f5, f1 +fmsub.s f0, f1, f5, f5 +fmsub.s f0, f1, f5, f10 +fmsub.s f0, f1, f5, f15 +fmsub.s f0, f1, f5, f20 +fmsub.s f0, f1, f5, f25 +fmsub.s f0, f1, f5, f31 +fmsub.s f0, f1, f10, f0 +fmsub.s f0, f1, f10, f1 +fmsub.s f0, f1, f10, f5 +fmsub.s f0, f1, f10, f10 +fmsub.s f0, f1, f10, f15 +fmsub.s f0, f1, f10, f20 +fmsub.s f0, f1, f10, f25 +fmsub.s f0, f1, f10, f31 +fmsub.s f0, f1, f15, f0 +fmsub.s f0, f1, f15, f1 +fmsub.s f0, f1, f15, f5 +fmsub.s f0, f1, f15, f10 +fmsub.s f0, f1, f15, f15 +fmsub.s f0, f1, f15, f20 +fmsub.s f0, f1, f15, f25 +fmsub.s f0, f1, f15, f31 +fmsub.s f0, f1, f20, f0 +fmsub.s f0, f1, f20, f1 +fmsub.s f0, f1, f20, f5 +fmsub.s f0, f1, f20, f10 +fmsub.s f0, f1, f20, f15 +fmsub.s f0, f1, f20, f20 +fmsub.s f0, f1, f20, f25 +fmsub.s f0, f1, f20, f31 +fmsub.s f0, f1, f25, f0 +fmsub.s f0, f1, f25, f1 +fmsub.s f0, f1, f25, f5 +fmsub.s f0, f1, f25, f10 +fmsub.s f0, f1, f25, f15 +fmsub.s f0, f1, f25, f20 +fmsub.s f0, f1, f25, f25 +fmsub.s f0, f1, f25, f31 +fmsub.s f0, f1, f31, f0 +fmsub.s f0, f1, f31, f1 +fmsub.s f0, f1, f31, f5 +fmsub.s f0, f1, f31, f10 +fmsub.s f0, f1, f31, f15 +fmsub.s f0, f1, f31, f20 +fmsub.s f0, f1, f31, f25 +fmsub.s f0, f1, f31, f31 +fmsub.s f0, f5, f0, f0 +fmsub.s f0, f5, f0, f1 +fmsub.s f0, f5, f0, f5 +fmsub.s f0, f5, f0, f10 +fmsub.s f0, f5, f0, f15 +fmsub.s f0, f5, f0, f20 +fmsub.s f0, f5, f0, f25 +fmsub.s f0, f5, f0, f31 +fmsub.s f0, f5, f1, f0 +fmsub.s f0, f5, f1, f1 +fmsub.s f0, f5, f1, f5 +fmsub.s f0, f5, f1, f10 +fmsub.s f0, f5, f1, f15 +fmsub.s f0, f5, f1, f20 +fmsub.s f0, f5, f1, f25 +fmsub.s f0, f5, f1, f31 +fmsub.s f0, f5, f5, f0 +fmsub.s f0, f5, f5, f1 +fmsub.s f0, f5, f5, f5 +fmsub.s f0, f5, f5, f10 +fmsub.s f0, f5, f5, f15 +fmsub.s f0, f5, f5, f20 +fmsub.s f0, f5, f5, f25 +fmsub.s f0, f5, f5, f31 +fmsub.s f0, f5, f10, f0 +fmsub.s f0, f5, f10, f1 +fmsub.s f0, f5, f10, f5 +fmsub.s f0, f5, f10, f10 +fmsub.s f0, f5, f10, f15 +fmsub.s f0, f5, f10, f20 +fmsub.s f0, f5, f10, f25 +fmsub.s f0, f5, f10, f31 +fmsub.s f0, f5, f15, f0 +fmsub.s f0, f5, f15, f1 +fmsub.s f0, f5, f15, f5 +fmsub.s f0, f5, f15, f10 +fmsub.s f0, f5, f15, f15 +fmsub.s f0, f5, f15, f20 +fmsub.s f0, f5, f15, f25 +fmsub.s f0, f5, f15, f31 +fmsub.s f0, f5, f20, f0 +fmsub.s f0, f5, f20, f1 +fmsub.s f0, f5, f20, f5 +fmsub.s f0, f5, f20, f10 +fmsub.s f0, f5, f20, f15 +fmsub.s f0, f5, f20, f20 +fmsub.s f0, f5, f20, f25 +fmsub.s f0, f5, f20, f31 +fmsub.s f0, f5, f25, f0 +fmsub.s f0, f5, f25, f1 +fmsub.s f0, f5, f25, f5 +fmsub.s f0, f5, f25, f10 +fmsub.s f0, f5, f25, f15 +fmsub.s f0, f5, f25, f20 +fmsub.s f0, f5, f25, f25 +fmsub.s f0, f5, f25, f31 +fmsub.s f0, f5, f31, f0 +fmsub.s f0, f5, f31, f1 +fmsub.s f0, f5, f31, f5 +fmsub.s f0, f5, f31, f10 +fmsub.s f0, f5, f31, f15 +fmsub.s f0, f5, f31, f20 +fmsub.s f0, f5, f31, f25 +fmsub.s f0, f5, f31, f31 +fmsub.s f0, f10, f0, f0 +fmsub.s f0, f10, f0, f1 +fmsub.s f0, f10, f0, f5 +fmsub.s f0, f10, f0, f10 +fmsub.s f0, f10, f0, f15 +fmsub.s f0, f10, f0, f20 +fmsub.s f0, f10, f0, f25 +fmsub.s f0, f10, f0, f31 +fmsub.s f0, f10, f1, f0 +fmsub.s f0, f10, f1, f1 +fmsub.s f0, f10, f1, f5 +fmsub.s f0, f10, f1, f10 +fmsub.s f0, f10, f1, f15 +fmsub.s f0, f10, f1, f20 +fmsub.s f0, f10, f1, f25 +fmsub.s f0, f10, f1, f31 +fmsub.s f0, f10, f5, f0 +fmsub.s f0, f10, f5, f1 +fmsub.s f0, f10, f5, f5 +fmsub.s f0, f10, f5, f10 +fmsub.s f0, f10, f5, f15 +fmsub.s f0, f10, f5, f20 +fmsub.s f0, f10, f5, f25 +fmsub.s f0, f10, f5, f31 +fmsub.s f0, f10, f10, f0 +fmsub.s f0, f10, f10, f1 +fmsub.s f0, f10, f10, f5 +fmsub.s f0, f10, f10, f10 +fmsub.s f0, f10, f10, f15 +fmsub.s f0, f10, f10, f20 +fmsub.s f0, f10, f10, f25 +fmsub.s f0, f10, f10, f31 +fmsub.s f0, f10, f15, f0 +fmsub.s f0, f10, f15, f1 +fmsub.s f0, f10, f15, f5 +fmsub.s f0, f10, f15, f10 +fmsub.s f0, f10, f15, f15 +fmsub.s f0, f10, f15, f20 +fmsub.s f0, f10, f15, f25 +fmsub.s f0, f10, f15, f31 +fmsub.s f0, f10, f20, f0 +fmsub.s f0, f10, f20, f1 +fmsub.s f0, f10, f20, f5 +fmsub.s f0, f10, f20, f10 +fmsub.s f0, f10, f20, f15 +fmsub.s f0, f10, f20, f20 +fmsub.s f0, f10, f20, f25 +fmsub.s f0, f10, f20, f31 +fmsub.s f0, f10, f25, f0 +fmsub.s f0, f10, f25, f1 +fmsub.s f0, f10, f25, f5 +fmsub.s f0, f10, f25, f10 +fmsub.s f0, f10, f25, f15 +fmsub.s f0, f10, f25, f20 +fmsub.s f0, f10, f25, f25 +fmsub.s f0, f10, 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z{ulp?|Hc2}fAPQgU;Hor3;%`x!hhkv@L%{Z{1^Tg|BL^{|Kfk~zxZGLFa8(*i~q&{ z;(zhK_+R`l{1sotSMgPR6<@_y@l||Vzx7+c^;^I7Tfa{|{*8a*-}pEFjeq0c_$&U3 zzv8d>EB=bV;;;BO{*8a*-}pEFjeq0c_$&U3zv8d>EB=bV;;;BO{*8a*-}pEFjeq0c V_&5HIf8*cyH~x)(I*0;X( zt#5tnTi>?_t={QDuX@m{Ud#ES-|f!-=zsG+`rrI-{LA(`{^dLW@}2K|V#ghy_`xTB c@Pp6nyyG)J`OHs#>P1_3deN6&^rf$I{!}b`@c;k- literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fmv.w.x.disasm b/tests/riscv/f-extension/fmv.w.x.disasm new file mode 100644 index 0000000..15d477d --- /dev/null +++ b/tests/riscv/f-extension/fmv.w.x.disasm @@ -0,0 +1,64 @@ +fmv.w.x f0, zero +fmv.w.x f0, ra +fmv.w.x f0, t0 +fmv.w.x f0, a0 +fmv.w.x f0, a5 +fmv.w.x f0, s4 +fmv.w.x f0, s9 +fmv.w.x f0, t6 +fmv.w.x f1, zero +fmv.w.x f1, ra +fmv.w.x f1, t0 +fmv.w.x f1, a0 +fmv.w.x f1, a5 +fmv.w.x f1, s4 +fmv.w.x f1, s9 +fmv.w.x f1, t6 +fmv.w.x f5, zero +fmv.w.x f5, ra +fmv.w.x f5, t0 +fmv.w.x f5, a0 +fmv.w.x f5, a5 +fmv.w.x f5, s4 +fmv.w.x f5, s9 +fmv.w.x f5, t6 +fmv.w.x f10, zero +fmv.w.x f10, ra +fmv.w.x f10, t0 +fmv.w.x f10, a0 +fmv.w.x f10, a5 +fmv.w.x f10, s4 +fmv.w.x f10, s9 +fmv.w.x f10, t6 +fmv.w.x f15, zero +fmv.w.x f15, ra +fmv.w.x f15, t0 +fmv.w.x f15, a0 +fmv.w.x f15, a5 +fmv.w.x f15, s4 +fmv.w.x f15, s9 +fmv.w.x f15, t6 +fmv.w.x f20, zero +fmv.w.x f20, ra +fmv.w.x f20, t0 +fmv.w.x f20, a0 +fmv.w.x f20, a5 +fmv.w.x f20, s4 +fmv.w.x f20, s9 +fmv.w.x f20, t6 +fmv.w.x f25, zero +fmv.w.x f25, ra +fmv.w.x f25, t0 +fmv.w.x f25, a0 +fmv.w.x f25, a5 +fmv.w.x f25, s4 +fmv.w.x f25, s9 +fmv.w.x f25, t6 +fmv.w.x f31, zero +fmv.w.x f31, ra +fmv.w.x f31, t0 +fmv.w.x f31, a0 +fmv.w.x f31, a5 +fmv.w.x f31, s4 +fmv.w.x f31, s9 +fmv.w.x f31, t6 diff --git a/tests/riscv/f-extension/fmv.x.w.asm b/tests/riscv/f-extension/fmv.x.w.asm new file mode 100644 index 0000000..a3451a1 --- /dev/null +++ b/tests/riscv/f-extension/fmv.x.w.asm @@ -0,0 +1,68 @@ +.lang riscv32 +.org 0x0 + +fmv.x.w zero, f0 +fmv.x.w zero, f1 +fmv.x.w zero, f5 +fmv.x.w zero, f10 +fmv.x.w zero, f15 +fmv.x.w zero, f20 +fmv.x.w zero, f25 +fmv.x.w zero, f31 +fmv.x.w ra, f0 +fmv.x.w ra, f1 +fmv.x.w ra, f5 +fmv.x.w ra, f10 +fmv.x.w ra, f15 +fmv.x.w ra, f20 +fmv.x.w ra, f25 +fmv.x.w ra, f31 +fmv.x.w t0, f0 +fmv.x.w t0, f1 +fmv.x.w t0, f5 +fmv.x.w t0, f10 +fmv.x.w t0, f15 +fmv.x.w t0, f20 +fmv.x.w t0, f25 +fmv.x.w t0, f31 +fmv.x.w a0, f0 +fmv.x.w a0, f1 +fmv.x.w a0, f5 +fmv.x.w a0, f10 +fmv.x.w a0, f15 +fmv.x.w a0, f20 +fmv.x.w a0, f25 +fmv.x.w a0, f31 +fmv.x.w a5, f0 +fmv.x.w a5, f1 +fmv.x.w a5, f5 +fmv.x.w a5, f10 +fmv.x.w a5, f15 +fmv.x.w a5, f20 +fmv.x.w a5, f25 +fmv.x.w a5, f31 +fmv.x.w s4, f0 +fmv.x.w s4, f1 +fmv.x.w s4, f5 +fmv.x.w s4, f10 +fmv.x.w s4, f15 +fmv.x.w s4, f20 +fmv.x.w s4, f25 +fmv.x.w s4, f31 +fmv.x.w s9, f0 +fmv.x.w s9, f1 +fmv.x.w s9, f5 +fmv.x.w s9, f10 +fmv.x.w s9, f15 +fmv.x.w s9, f20 +fmv.x.w s9, f25 +fmv.x.w s9, f31 +fmv.x.w t6, f0 +fmv.x.w t6, f1 +fmv.x.w t6, f5 +fmv.x.w t6, f10 +fmv.x.w t6, f15 +fmv.x.w t6, f20 +fmv.x.w t6, f25 +fmv.x.w t6, f31 + diff --git a/tests/riscv/f-extension/fmv.x.w.bin b/tests/riscv/f-extension/fmv.x.w.bin new file mode 100644 index 0000000000000000000000000000000000000000..f5422697337253fb5292d0c8b648976638f03229 GIT binary patch literal 256 zcmWm6Q3gdJ6o%0wa!53|GodRIi3ZmM8p>Tg{Px3V?eBTc_qz+{d!qZg$<0>I*0;X( zt#5tnTi>?_t={QDuX@m{Ud#ES-|f!-=zsG+`rrI-{LA(`{^dLW@}2K|V#ghy_`xTB c@Pp6nyyG)J`OHs#>P1_3deN6&^rf$I{#Xuo@c;k- literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fmv.x.w.disasm b/tests/riscv/f-extension/fmv.x.w.disasm new file mode 100644 index 0000000..f09437d --- /dev/null +++ b/tests/riscv/f-extension/fmv.x.w.disasm @@ -0,0 +1,64 @@ +fmv.x.w zero, f0 +fmv.x.w zero, f1 +fmv.x.w zero, f5 +fmv.x.w zero, f10 +fmv.x.w zero, f15 +fmv.x.w zero, f20 +fmv.x.w zero, f25 +fmv.x.w zero, f31 +fmv.x.w ra, f0 +fmv.x.w ra, f1 +fmv.x.w ra, f5 +fmv.x.w ra, f10 +fmv.x.w ra, f15 +fmv.x.w ra, f20 +fmv.x.w ra, f25 +fmv.x.w ra, f31 +fmv.x.w t0, f0 +fmv.x.w t0, f1 +fmv.x.w t0, f5 +fmv.x.w t0, f10 +fmv.x.w t0, f15 +fmv.x.w t0, f20 +fmv.x.w t0, f25 +fmv.x.w t0, f31 +fmv.x.w a0, f0 +fmv.x.w a0, f1 +fmv.x.w a0, f5 +fmv.x.w a0, f10 +fmv.x.w a0, f15 +fmv.x.w a0, f20 +fmv.x.w a0, f25 +fmv.x.w a0, f31 +fmv.x.w a5, f0 +fmv.x.w a5, f1 +fmv.x.w a5, f5 +fmv.x.w a5, f10 +fmv.x.w a5, f15 +fmv.x.w a5, f20 +fmv.x.w a5, f25 +fmv.x.w a5, f31 +fmv.x.w s4, f0 +fmv.x.w s4, f1 +fmv.x.w s4, f5 +fmv.x.w s4, f10 +fmv.x.w s4, f15 +fmv.x.w s4, f20 +fmv.x.w s4, f25 +fmv.x.w s4, f31 +fmv.x.w s9, f0 +fmv.x.w s9, f1 +fmv.x.w s9, f5 +fmv.x.w s9, f10 +fmv.x.w s9, f15 +fmv.x.w s9, f20 +fmv.x.w s9, f25 +fmv.x.w s9, f31 +fmv.x.w t6, f0 +fmv.x.w t6, f1 +fmv.x.w t6, f5 +fmv.x.w t6, f10 +fmv.x.w t6, f15 +fmv.x.w t6, f20 +fmv.x.w t6, f25 +fmv.x.w t6, f31 diff --git a/tests/riscv/f-extension/fmv_w_x.asm b/tests/riscv/f-extension/fmv_w_x.asm new file mode 100644 index 0000000..5d89aad --- /dev/null +++ b/tests/riscv/f-extension/fmv_w_x.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fmv.w.x f0, a1 + diff --git a/tests/riscv/f-extension/fmv_w_x.bin b/tests/riscv/f-extension/fmv_w_x.bin new file mode 100644 index 0000000..ccc7f92 --- /dev/null +++ b/tests/riscv/f-extension/fmv_w_x.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/f-extension/fmv_w_x.disasm b/tests/riscv/f-extension/fmv_w_x.disasm new file mode 100644 index 0000000..e5ed82b --- /dev/null +++ b/tests/riscv/f-extension/fmv_w_x.disasm @@ -0,0 +1 @@ +fmv.w.x f0, a1 diff --git a/tests/riscv/f-extension/fmv_x_w.asm b/tests/riscv/f-extension/fmv_x_w.asm new file mode 100644 index 0000000..75e6bb8 --- /dev/null +++ b/tests/riscv/f-extension/fmv_x_w.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fmv.x.w a0, f1 + diff --git a/tests/riscv/f-extension/fmv_x_w.bin b/tests/riscv/f-extension/fmv_x_w.bin new file mode 100644 index 0000000000000000000000000000000000000000..2275986ff44e1e2773f79e06f71b2d4f0b2a05b5 GIT binary patch literal 4 LcmWG;Wq1Gp1HS>e literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fmv_x_w.disasm b/tests/riscv/f-extension/fmv_x_w.disasm new file mode 100644 index 0000000..8a99250 --- /dev/null +++ b/tests/riscv/f-extension/fmv_x_w.disasm @@ -0,0 +1 @@ +fmv.x.w a0, f1 diff --git a/tests/riscv/f-extension/fnmadd.s.asm b/tests/riscv/f-extension/fnmadd.s.asm new file mode 100644 index 0000000..50c0fb6 --- /dev/null +++ b/tests/riscv/f-extension/fnmadd.s.asm @@ -0,0 +1,4100 @@ +.lang riscv32 +.org 0x0 + +fnmadd.s f0, f0, f0, f0 +fnmadd.s f0, f0, f0, f1 +fnmadd.s f0, f0, f0, f5 +fnmadd.s f0, f0, f0, f10 +fnmadd.s f0, f0, f0, f15 +fnmadd.s f0, f0, f0, f20 +fnmadd.s f0, f0, f0, f25 +fnmadd.s f0, f0, f0, f31 +fnmadd.s f0, f0, f1, f0 +fnmadd.s f0, f0, f1, f1 +fnmadd.s f0, f0, f1, f5 +fnmadd.s f0, f0, f1, f10 +fnmadd.s f0, f0, f1, f15 +fnmadd.s f0, f0, f1, f20 +fnmadd.s f0, f0, f1, f25 +fnmadd.s f0, f0, f1, f31 +fnmadd.s f0, f0, f5, f0 +fnmadd.s f0, f0, f5, f1 +fnmadd.s f0, f0, f5, f5 +fnmadd.s f0, f0, f5, f10 +fnmadd.s f0, f0, f5, f15 +fnmadd.s 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f20 +fnmadd.s f0, f0, f1, f25 +fnmadd.s f0, f0, f1, f31 +fnmadd.s f0, f0, f5, f0 +fnmadd.s f0, f0, f5, f1 +fnmadd.s f0, f0, f5, f5 +fnmadd.s f0, f0, f5, f10 +fnmadd.s f0, f0, f5, f15 +fnmadd.s f0, f0, f5, f20 +fnmadd.s f0, f0, f5, f25 +fnmadd.s f0, f0, f5, f31 +fnmadd.s f0, f0, f10, f0 +fnmadd.s f0, f0, f10, f1 +fnmadd.s f0, f0, f10, f5 +fnmadd.s f0, f0, f10, f10 +fnmadd.s f0, f0, f10, f15 +fnmadd.s f0, f0, f10, f20 +fnmadd.s f0, f0, f10, f25 +fnmadd.s f0, f0, f10, f31 +fnmadd.s f0, f0, f15, f0 +fnmadd.s f0, f0, f15, f1 +fnmadd.s f0, f0, f15, f5 +fnmadd.s f0, f0, f15, f10 +fnmadd.s f0, f0, f15, f15 +fnmadd.s f0, f0, f15, f20 +fnmadd.s f0, f0, f15, f25 +fnmadd.s f0, f0, f15, f31 +fnmadd.s f0, f0, f20, f0 +fnmadd.s f0, f0, f20, f1 +fnmadd.s f0, f0, f20, f5 +fnmadd.s f0, f0, f20, f10 +fnmadd.s f0, f0, f20, f15 +fnmadd.s f0, f0, f20, f20 +fnmadd.s f0, f0, f20, f25 +fnmadd.s f0, f0, f20, f31 +fnmadd.s f0, f0, f25, f0 +fnmadd.s f0, f0, f25, f1 +fnmadd.s f0, f0, f25, f5 +fnmadd.s f0, f0, f25, f10 +fnmadd.s f0, f0, f25, f15 +fnmadd.s f0, f0, f25, f20 +fnmadd.s f0, f0, f25, f25 +fnmadd.s f0, f0, f25, f31 +fnmadd.s f0, f0, f31, f0 +fnmadd.s f0, f0, f31, f1 +fnmadd.s f0, f0, f31, f5 +fnmadd.s f0, f0, f31, f10 +fnmadd.s f0, f0, f31, f15 +fnmadd.s f0, f0, f31, f20 +fnmadd.s f0, f0, f31, f25 +fnmadd.s f0, f0, f31, f31 +fnmadd.s f0, f1, f0, f0 +fnmadd.s f0, f1, f0, f1 +fnmadd.s f0, f1, f0, f5 +fnmadd.s f0, f1, f0, f10 +fnmadd.s f0, f1, f0, f15 +fnmadd.s f0, f1, f0, f20 +fnmadd.s f0, f1, f0, f25 +fnmadd.s f0, f1, f0, f31 +fnmadd.s f0, f1, f1, f0 +fnmadd.s f0, f1, f1, f1 +fnmadd.s f0, f1, f1, f5 +fnmadd.s f0, f1, f1, f10 +fnmadd.s f0, f1, f1, f15 +fnmadd.s f0, f1, f1, f20 +fnmadd.s f0, f1, f1, f25 +fnmadd.s f0, f1, f1, f31 +fnmadd.s f0, f1, f5, f0 +fnmadd.s f0, f1, f5, f1 +fnmadd.s f0, f1, f5, f5 +fnmadd.s f0, f1, f5, f10 +fnmadd.s f0, f1, f5, f15 +fnmadd.s f0, f1, f5, f20 +fnmadd.s f0, f1, f5, f25 +fnmadd.s f0, f1, f5, f31 +fnmadd.s f0, f1, f10, f0 +fnmadd.s f0, f1, f10, f1 +fnmadd.s f0, f1, f10, f5 +fnmadd.s f0, f1, f10, f10 +fnmadd.s f0, f1, f10, f15 +fnmadd.s f0, f1, f10, f20 +fnmadd.s f0, f1, f10, f25 +fnmadd.s f0, f1, f10, f31 +fnmadd.s f0, f1, f15, f0 +fnmadd.s f0, f1, f15, f1 +fnmadd.s f0, f1, f15, f5 +fnmadd.s f0, f1, f15, f10 +fnmadd.s f0, f1, f15, f15 +fnmadd.s f0, f1, f15, f20 +fnmadd.s f0, f1, f15, f25 +fnmadd.s f0, f1, f15, f31 +fnmadd.s f0, f1, f20, f0 +fnmadd.s f0, f1, f20, f1 +fnmadd.s f0, f1, f20, f5 +fnmadd.s f0, f1, f20, f10 +fnmadd.s f0, f1, f20, f15 +fnmadd.s f0, f1, f20, f20 +fnmadd.s f0, f1, f20, f25 +fnmadd.s f0, f1, f20, f31 +fnmadd.s f0, f1, f25, f0 +fnmadd.s f0, f1, f25, f1 +fnmadd.s f0, f1, f25, f5 +fnmadd.s f0, f1, f25, f10 +fnmadd.s f0, f1, f25, f15 +fnmadd.s f0, f1, f25, f20 +fnmadd.s f0, f1, f25, f25 +fnmadd.s f0, f1, f25, f31 +fnmadd.s f0, f1, f31, f0 +fnmadd.s f0, f1, f31, f1 +fnmadd.s f0, f1, f31, f5 +fnmadd.s f0, f1, f31, f10 +fnmadd.s f0, f1, f31, f15 +fnmadd.s f0, f1, f31, f20 +fnmadd.s f0, f1, f31, f25 +fnmadd.s f0, f1, f31, f31 +fnmadd.s f0, f5, f0, f0 +fnmadd.s f0, f5, f0, f1 +fnmadd.s f0, f5, f0, f5 +fnmadd.s f0, f5, f0, f10 +fnmadd.s f0, f5, f0, f15 +fnmadd.s f0, f5, f0, f20 +fnmadd.s f0, f5, f0, f25 +fnmadd.s f0, f5, f0, f31 +fnmadd.s f0, f5, f1, f0 +fnmadd.s f0, f5, f1, f1 +fnmadd.s f0, f5, f1, f5 +fnmadd.s f0, f5, f1, f10 +fnmadd.s f0, f5, f1, f15 +fnmadd.s f0, f5, f1, f20 +fnmadd.s f0, f5, f1, f25 +fnmadd.s f0, f5, f1, f31 +fnmadd.s f0, f5, f5, f0 +fnmadd.s f0, f5, f5, f1 +fnmadd.s f0, f5, f5, f5 +fnmadd.s f0, f5, f5, f10 +fnmadd.s f0, f5, f5, f15 +fnmadd.s f0, f5, f5, f20 +fnmadd.s f0, f5, f5, f25 +fnmadd.s f0, f5, f5, f31 +fnmadd.s f0, f5, f10, f0 +fnmadd.s f0, f5, f10, f1 +fnmadd.s f0, f5, f10, f5 +fnmadd.s f0, f5, f10, f10 +fnmadd.s f0, f5, f10, f15 +fnmadd.s f0, f5, f10, f20 +fnmadd.s f0, f5, f10, f25 +fnmadd.s f0, f5, f10, f31 +fnmadd.s f0, f5, f15, f0 +fnmadd.s f0, f5, f15, f1 +fnmadd.s f0, f5, f15, f5 +fnmadd.s f0, f5, f15, f10 +fnmadd.s f0, f5, f15, f15 +fnmadd.s f0, f5, f15, f20 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f0, f1 +fnmadd.s f31, f1, f0, f5 +fnmadd.s f31, f1, f0, f10 +fnmadd.s f31, f1, f0, f15 +fnmadd.s f31, f1, f0, f20 +fnmadd.s f31, f1, f0, f25 +fnmadd.s f31, f1, f0, f31 +fnmadd.s f31, f1, f1, f0 +fnmadd.s f31, f1, f1, f1 +fnmadd.s f31, f1, f1, f5 +fnmadd.s f31, f1, f1, f10 +fnmadd.s f31, f1, f1, f15 +fnmadd.s f31, f1, f1, f20 +fnmadd.s f31, f1, f1, f25 +fnmadd.s f31, f1, f1, f31 +fnmadd.s f31, f1, f5, f0 +fnmadd.s f31, f1, f5, f1 +fnmadd.s f31, f1, f5, f5 +fnmadd.s f31, f1, f5, f10 +fnmadd.s f31, f1, f5, f15 +fnmadd.s f31, f1, f5, f20 +fnmadd.s f31, f1, f5, f25 +fnmadd.s f31, f1, f5, f31 +fnmadd.s f31, f1, f10, f0 +fnmadd.s f31, f1, f10, f1 +fnmadd.s f31, f1, f10, f5 +fnmadd.s f31, f1, f10, f10 +fnmadd.s f31, f1, f10, f15 +fnmadd.s f31, f1, f10, f20 +fnmadd.s f31, f1, f10, f25 +fnmadd.s f31, f1, f10, f31 +fnmadd.s f31, f1, f15, f0 +fnmadd.s f31, f1, f15, f1 +fnmadd.s f31, f1, f15, f5 +fnmadd.s f31, f1, f15, f10 +fnmadd.s f31, f1, f15, f15 +fnmadd.s f31, f1, f15, f20 +fnmadd.s f31, f1, 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f31, f5, f1, f10 +fnmadd.s f31, f5, f1, f15 +fnmadd.s f31, f5, f1, f20 +fnmadd.s f31, f5, f1, f25 +fnmadd.s f31, f5, f1, f31 +fnmadd.s f31, f5, f5, f0 +fnmadd.s f31, f5, f5, f1 +fnmadd.s f31, f5, f5, f5 +fnmadd.s f31, f5, f5, f10 +fnmadd.s f31, f5, f5, f15 +fnmadd.s f31, f5, f5, f20 +fnmadd.s f31, f5, f5, f25 +fnmadd.s f31, f5, f5, f31 +fnmadd.s f31, f5, f10, f0 +fnmadd.s f31, f5, f10, f1 +fnmadd.s f31, f5, f10, f5 +fnmadd.s f31, f5, f10, f10 +fnmadd.s f31, f5, f10, f15 +fnmadd.s f31, f5, f10, f20 +fnmadd.s f31, f5, f10, f25 +fnmadd.s f31, f5, f10, f31 +fnmadd.s f31, f5, f15, f0 +fnmadd.s f31, f5, f15, f1 +fnmadd.s f31, f5, f15, f5 +fnmadd.s f31, f5, f15, f10 +fnmadd.s f31, f5, f15, f15 +fnmadd.s f31, f5, f15, f20 +fnmadd.s f31, f5, f15, f25 +fnmadd.s f31, f5, f15, f31 +fnmadd.s f31, f5, f20, f0 +fnmadd.s f31, f5, f20, f1 +fnmadd.s f31, f5, f20, f5 +fnmadd.s f31, f5, f20, f10 +fnmadd.s f31, f5, f20, f15 +fnmadd.s f31, f5, f20, f20 +fnmadd.s f31, f5, f20, f25 +fnmadd.s f31, f5, f20, f31 +fnmadd.s f31, f5, f25, f0 +fnmadd.s f31, f5, f25, f1 +fnmadd.s f31, f5, f25, f5 +fnmadd.s f31, f5, f25, f10 +fnmadd.s f31, f5, f25, f15 +fnmadd.s f31, f5, f25, f20 +fnmadd.s f31, f5, f25, f25 +fnmadd.s f31, f5, f25, f31 +fnmadd.s f31, f5, f31, f0 +fnmadd.s f31, f5, f31, f1 +fnmadd.s f31, f5, f31, f5 +fnmadd.s f31, f5, f31, f10 +fnmadd.s f31, f5, f31, f15 +fnmadd.s f31, f5, f31, f20 +fnmadd.s f31, f5, f31, f25 +fnmadd.s f31, f5, f31, f31 +fnmadd.s f31, f10, f0, f0 +fnmadd.s f31, f10, f0, f1 +fnmadd.s f31, f10, f0, f5 +fnmadd.s f31, f10, f0, f10 +fnmadd.s f31, f10, f0, f15 +fnmadd.s f31, f10, f0, f20 +fnmadd.s f31, f10, f0, f25 +fnmadd.s f31, f10, f0, f31 +fnmadd.s f31, f10, f1, f0 +fnmadd.s f31, f10, f1, f1 +fnmadd.s f31, f10, f1, f5 +fnmadd.s f31, f10, f1, f10 +fnmadd.s f31, f10, f1, f15 +fnmadd.s f31, f10, f1, f20 +fnmadd.s f31, f10, f1, f25 +fnmadd.s f31, f10, f1, f31 +fnmadd.s f31, f10, f5, f0 +fnmadd.s f31, f10, f5, f1 +fnmadd.s f31, f10, f5, f5 +fnmadd.s f31, f10, f5, f10 +fnmadd.s f31, f10, f5, f15 +fnmadd.s f31, f10, f5, f20 +fnmadd.s f31, f10, f5, f25 +fnmadd.s f31, f10, f5, f31 +fnmadd.s f31, f10, f10, f0 +fnmadd.s f31, f10, f10, f1 +fnmadd.s f31, f10, f10, f5 +fnmadd.s f31, f10, f10, f10 +fnmadd.s f31, f10, f10, f15 +fnmadd.s f31, f10, f10, f20 +fnmadd.s f31, f10, f10, f25 +fnmadd.s f31, f10, f10, f31 +fnmadd.s f31, f10, f15, f0 +fnmadd.s f31, f10, f15, f1 +fnmadd.s f31, f10, f15, f5 +fnmadd.s f31, f10, f15, f10 +fnmadd.s f31, f10, f15, f15 +fnmadd.s f31, f10, f15, f20 +fnmadd.s f31, f10, f15, f25 +fnmadd.s f31, f10, f15, f31 +fnmadd.s f31, f10, f20, f0 +fnmadd.s f31, f10, f20, f1 +fnmadd.s f31, f10, f20, f5 +fnmadd.s f31, f10, f20, f10 +fnmadd.s f31, f10, f20, f15 +fnmadd.s f31, f10, f20, f20 +fnmadd.s f31, f10, f20, f25 +fnmadd.s f31, f10, f20, f31 +fnmadd.s f31, f10, f25, f0 +fnmadd.s f31, f10, f25, f1 +fnmadd.s f31, f10, f25, f5 +fnmadd.s f31, f10, f25, f10 +fnmadd.s f31, f10, f25, f15 +fnmadd.s f31, f10, f25, f20 +fnmadd.s f31, f10, f25, f25 +fnmadd.s f31, f10, f25, f31 +fnmadd.s f31, f10, f31, f0 +fnmadd.s f31, f10, f31, f1 +fnmadd.s f31, f10, f31, f5 +fnmadd.s f31, f10, f31, f10 +fnmadd.s f31, f10, f31, f15 +fnmadd.s f31, f10, f31, f20 +fnmadd.s f31, f10, f31, f25 +fnmadd.s f31, f10, f31, f31 +fnmadd.s f31, f15, f0, f0 +fnmadd.s f31, f15, f0, f1 +fnmadd.s f31, f15, f0, f5 +fnmadd.s f31, f15, f0, f10 +fnmadd.s f31, f15, f0, f15 +fnmadd.s f31, f15, f0, f20 +fnmadd.s f31, f15, f0, f25 +fnmadd.s f31, f15, f0, f31 +fnmadd.s f31, f15, f1, f0 +fnmadd.s f31, f15, f1, f1 +fnmadd.s f31, f15, f1, f5 +fnmadd.s f31, f15, f1, f10 +fnmadd.s f31, f15, f1, f15 +fnmadd.s f31, f15, f1, f20 +fnmadd.s f31, f15, f1, f25 +fnmadd.s f31, f15, f1, f31 +fnmadd.s f31, f15, f5, f0 +fnmadd.s f31, f15, f5, f1 +fnmadd.s f31, f15, f5, f5 +fnmadd.s f31, f15, f5, f10 +fnmadd.s f31, f15, f5, f15 +fnmadd.s f31, f15, f5, f20 +fnmadd.s f31, f15, f5, f25 +fnmadd.s f31, f15, f5, f31 +fnmadd.s f31, f15, f10, f0 +fnmadd.s f31, f15, f10, f1 +fnmadd.s f31, f15, f10, f5 +fnmadd.s f31, f15, f10, f10 +fnmadd.s f31, f15, f10, f15 +fnmadd.s f31, f15, f10, f20 +fnmadd.s f31, f15, f10, f25 +fnmadd.s f31, f15, f10, f31 +fnmadd.s f31, f15, f15, f0 +fnmadd.s f31, f15, f15, f1 +fnmadd.s f31, f15, f15, f5 +fnmadd.s f31, f15, f15, f10 +fnmadd.s f31, f15, f15, f15 +fnmadd.s f31, f15, f15, f20 +fnmadd.s f31, f15, f15, f25 +fnmadd.s f31, f15, f15, f31 +fnmadd.s f31, f15, f20, f0 +fnmadd.s f31, f15, f20, f1 +fnmadd.s f31, f15, f20, f5 +fnmadd.s f31, f15, f20, f10 +fnmadd.s f31, f15, f20, f15 +fnmadd.s f31, f15, f20, f20 +fnmadd.s f31, f15, f20, f25 +fnmadd.s f31, f15, f20, f31 +fnmadd.s f31, f15, f25, f0 +fnmadd.s f31, f15, f25, f1 +fnmadd.s f31, f15, f25, f5 +fnmadd.s f31, f15, f25, f10 +fnmadd.s f31, f15, f25, f15 +fnmadd.s f31, f15, f25, f20 +fnmadd.s f31, f15, f25, f25 +fnmadd.s f31, f15, f25, f31 +fnmadd.s f31, f15, f31, f0 +fnmadd.s f31, f15, f31, f1 +fnmadd.s f31, f15, f31, f5 +fnmadd.s f31, f15, f31, f10 +fnmadd.s f31, f15, f31, f15 +fnmadd.s f31, f15, f31, f20 +fnmadd.s f31, f15, f31, f25 +fnmadd.s f31, f15, f31, f31 +fnmadd.s f31, f20, f0, f0 +fnmadd.s f31, f20, f0, f1 +fnmadd.s f31, f20, f0, f5 +fnmadd.s f31, f20, f0, f10 +fnmadd.s f31, f20, f0, f15 +fnmadd.s f31, f20, f0, f20 +fnmadd.s f31, f20, f0, f25 +fnmadd.s f31, f20, f0, f31 +fnmadd.s f31, f20, f1, f0 +fnmadd.s f31, f20, f1, f1 +fnmadd.s f31, f20, f1, f5 +fnmadd.s f31, f20, f1, f10 +fnmadd.s f31, f20, f1, f15 +fnmadd.s f31, f20, f1, f20 +fnmadd.s f31, f20, f1, f25 +fnmadd.s f31, f20, f1, f31 +fnmadd.s f31, f20, f5, f0 +fnmadd.s f31, f20, f5, f1 +fnmadd.s f31, f20, f5, f5 +fnmadd.s f31, f20, f5, f10 +fnmadd.s f31, f20, f5, f15 +fnmadd.s f31, f20, f5, f20 +fnmadd.s f31, f20, f5, f25 +fnmadd.s f31, f20, f5, f31 +fnmadd.s f31, f20, f10, f0 +fnmadd.s f31, f20, f10, f1 +fnmadd.s f31, f20, f10, f5 +fnmadd.s f31, f20, f10, f10 +fnmadd.s f31, f20, f10, f15 +fnmadd.s f31, f20, f10, f20 +fnmadd.s f31, f20, f10, f25 +fnmadd.s f31, f20, f10, f31 +fnmadd.s f31, f20, f15, f0 +fnmadd.s f31, f20, f15, f1 +fnmadd.s f31, f20, f15, f5 +fnmadd.s f31, f20, f15, f10 +fnmadd.s f31, f20, f15, f15 +fnmadd.s f31, f20, f15, f20 +fnmadd.s f31, f20, f15, f25 +fnmadd.s f31, f20, f15, f31 +fnmadd.s f31, f20, f20, f0 +fnmadd.s f31, f20, f20, f1 +fnmadd.s f31, f20, f20, f5 +fnmadd.s f31, f20, f20, f10 +fnmadd.s f31, f20, f20, f15 +fnmadd.s f31, f20, f20, f20 +fnmadd.s f31, f20, f20, f25 +fnmadd.s f31, f20, f20, f31 +fnmadd.s f31, f20, f25, f0 +fnmadd.s f31, f20, f25, f1 +fnmadd.s f31, f20, f25, f5 +fnmadd.s f31, f20, f25, f10 +fnmadd.s f31, f20, f25, f15 +fnmadd.s f31, f20, f25, f20 +fnmadd.s f31, f20, f25, f25 +fnmadd.s f31, f20, f25, f31 +fnmadd.s f31, f20, f31, f0 +fnmadd.s f31, f20, f31, f1 +fnmadd.s f31, f20, f31, f5 +fnmadd.s f31, f20, f31, f10 +fnmadd.s f31, f20, f31, f15 +fnmadd.s f31, f20, f31, f20 +fnmadd.s f31, f20, f31, f25 +fnmadd.s f31, f20, f31, f31 +fnmadd.s f31, f25, f0, f0 +fnmadd.s f31, f25, f0, f1 +fnmadd.s f31, f25, f0, f5 +fnmadd.s f31, f25, f0, f10 +fnmadd.s f31, f25, f0, f15 +fnmadd.s f31, f25, f0, f20 +fnmadd.s f31, f25, f0, f25 +fnmadd.s f31, f25, f0, f31 +fnmadd.s f31, f25, f1, f0 +fnmadd.s f31, f25, f1, f1 +fnmadd.s f31, f25, f1, f5 +fnmadd.s f31, f25, f1, f10 +fnmadd.s f31, f25, f1, f15 +fnmadd.s f31, f25, f1, f20 +fnmadd.s f31, f25, f1, f25 +fnmadd.s f31, f25, f1, f31 +fnmadd.s f31, f25, f5, f0 +fnmadd.s f31, f25, f5, f1 +fnmadd.s f31, f25, f5, f5 +fnmadd.s f31, f25, f5, f10 +fnmadd.s f31, f25, f5, f15 +fnmadd.s f31, f25, f5, f20 +fnmadd.s f31, f25, f5, f25 +fnmadd.s f31, f25, f5, f31 +fnmadd.s f31, f25, f10, f0 +fnmadd.s f31, f25, f10, f1 +fnmadd.s f31, f25, f10, f5 +fnmadd.s f31, f25, f10, f10 +fnmadd.s f31, f25, f10, f15 +fnmadd.s f31, f25, f10, f20 +fnmadd.s f31, f25, f10, f25 +fnmadd.s f31, f25, f10, f31 +fnmadd.s f31, f25, f15, f0 +fnmadd.s f31, f25, f15, f1 +fnmadd.s f31, f25, f15, f5 +fnmadd.s f31, f25, f15, f10 +fnmadd.s f31, f25, f15, f15 +fnmadd.s f31, f25, f15, f20 +fnmadd.s f31, f25, f15, f25 +fnmadd.s f31, f25, f15, f31 +fnmadd.s f31, f25, f20, f0 +fnmadd.s f31, f25, f20, f1 +fnmadd.s f31, f25, f20, f5 +fnmadd.s f31, f25, f20, f10 +fnmadd.s f31, f25, f20, f15 +fnmadd.s f31, f25, f20, f20 +fnmadd.s f31, f25, f20, f25 +fnmadd.s f31, f25, f20, f31 +fnmadd.s f31, f25, f25, f0 +fnmadd.s f31, f25, f25, f1 +fnmadd.s f31, f25, f25, f5 +fnmadd.s f31, f25, f25, f10 +fnmadd.s f31, f25, f25, f15 +fnmadd.s f31, f25, f25, f20 +fnmadd.s f31, f25, f25, f25 +fnmadd.s f31, f25, f25, f31 +fnmadd.s f31, f25, f31, f0 +fnmadd.s f31, f25, f31, f1 +fnmadd.s f31, f25, f31, f5 +fnmadd.s f31, f25, f31, f10 +fnmadd.s f31, f25, f31, f15 +fnmadd.s f31, f25, f31, f20 +fnmadd.s f31, f25, f31, f25 +fnmadd.s f31, f25, f31, f31 +fnmadd.s f31, f31, f0, f0 +fnmadd.s f31, f31, f0, f1 +fnmadd.s f31, f31, f0, f5 +fnmadd.s f31, f31, f0, f10 +fnmadd.s f31, f31, f0, f15 +fnmadd.s f31, f31, f0, f20 +fnmadd.s f31, f31, f0, f25 +fnmadd.s f31, f31, f0, f31 +fnmadd.s f31, f31, f1, f0 +fnmadd.s f31, f31, f1, f1 +fnmadd.s f31, f31, f1, f5 +fnmadd.s f31, f31, f1, f10 +fnmadd.s f31, f31, f1, f15 +fnmadd.s f31, f31, f1, f20 +fnmadd.s f31, f31, f1, f25 +fnmadd.s f31, f31, f1, f31 +fnmadd.s f31, f31, f5, f0 +fnmadd.s f31, f31, f5, f1 +fnmadd.s f31, f31, f5, f5 +fnmadd.s f31, f31, f5, f10 +fnmadd.s f31, f31, f5, f15 +fnmadd.s f31, f31, f5, f20 +fnmadd.s f31, f31, f5, f25 +fnmadd.s f31, f31, f5, f31 +fnmadd.s f31, f31, f10, f0 +fnmadd.s f31, f31, f10, f1 +fnmadd.s f31, f31, f10, f5 +fnmadd.s f31, f31, f10, f10 +fnmadd.s f31, f31, f10, f15 +fnmadd.s f31, f31, f10, f20 +fnmadd.s f31, f31, f10, f25 +fnmadd.s f31, f31, f10, f31 +fnmadd.s f31, f31, f15, f0 +fnmadd.s f31, f31, f15, f1 +fnmadd.s f31, f31, f15, f5 +fnmadd.s f31, f31, f15, f10 +fnmadd.s f31, f31, f15, f15 +fnmadd.s f31, f31, f15, f20 +fnmadd.s f31, f31, f15, f25 +fnmadd.s f31, f31, f15, f31 +fnmadd.s f31, f31, f20, f0 +fnmadd.s f31, f31, f20, f1 +fnmadd.s f31, f31, f20, f5 +fnmadd.s f31, f31, f20, f10 +fnmadd.s f31, f31, f20, f15 +fnmadd.s f31, f31, f20, f20 +fnmadd.s f31, f31, f20, f25 +fnmadd.s f31, f31, f20, f31 +fnmadd.s f31, f31, f25, f0 +fnmadd.s f31, f31, f25, f1 +fnmadd.s f31, f31, f25, f5 +fnmadd.s f31, f31, f25, f10 +fnmadd.s f31, f31, f25, f15 +fnmadd.s f31, f31, f25, f20 +fnmadd.s f31, f31, f25, f25 +fnmadd.s f31, f31, f25, f31 +fnmadd.s f31, f31, f31, f0 +fnmadd.s f31, f31, f31, f1 +fnmadd.s f31, f31, f31, f5 +fnmadd.s f31, f31, f31, f10 +fnmadd.s f31, f31, f31, f15 +fnmadd.s f31, f31, f31, f20 +fnmadd.s f31, f31, f31, f25 +fnmadd.s f31, f31, f31, f31 diff --git a/tests/riscv/f-extension/fnmadd_s.asm b/tests/riscv/f-extension/fnmadd_s.asm new file mode 100644 index 0000000..2d300a1 --- /dev/null +++ b/tests/riscv/f-extension/fnmadd_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fnmadd.s f0, f1, f2, f3 + diff --git a/tests/riscv/f-extension/fnmadd_s.bin b/tests/riscv/f-extension/fnmadd_s.bin new file mode 100644 index 0000000..32b673a --- /dev/null +++ b/tests/riscv/f-extension/fnmadd_s.bin @@ -0,0 +1 @@ +O  \ No newline at end of file diff --git a/tests/riscv/f-extension/fnmadd_s.disasm b/tests/riscv/f-extension/fnmadd_s.disasm new file mode 100644 index 0000000..7d8837f --- /dev/null +++ b/tests/riscv/f-extension/fnmadd_s.disasm @@ -0,0 +1 @@ +fnmadd.s f0, f1, f2, f3 diff --git a/tests/riscv/f-extension/fnmsub.s.asm b/tests/riscv/f-extension/fnmsub.s.asm new file mode 100644 index 0000000..4f1ebdf --- /dev/null +++ b/tests/riscv/f-extension/fnmsub.s.asm @@ -0,0 +1,4100 @@ +.lang riscv32 +.org 0x0 + +fnmsub.s f0, f0, f0, f0 +fnmsub.s f0, f0, f0, f1 +fnmsub.s f0, f0, f0, f5 +fnmsub.s f0, f0, f0, f10 +fnmsub.s f0, f0, f0, f15 +fnmsub.s f0, f0, f0, f20 +fnmsub.s f0, f0, f0, f25 +fnmsub.s f0, f0, f0, f31 +fnmsub.s f0, f0, f1, f0 +fnmsub.s f0, f0, f1, f1 +fnmsub.s f0, f0, f1, f5 +fnmsub.s f0, f0, f1, f10 +fnmsub.s f0, f0, f1, f15 +fnmsub.s f0, f0, f1, f20 +fnmsub.s f0, f0, f1, f25 +fnmsub.s f0, f0, f1, f31 +fnmsub.s f0, f0, f5, f0 +fnmsub.s f0, f0, f5, f1 +fnmsub.s f0, f0, f5, f5 +fnmsub.s f0, f0, f5, f10 +fnmsub.s f0, f0, f5, f15 +fnmsub.s f0, f0, f5, f20 +fnmsub.s f0, f0, f5, f25 +fnmsub.s f0, f0, f5, f31 +fnmsub.s f0, f0, f10, f0 +fnmsub.s f0, f0, f10, f1 +fnmsub.s f0, f0, f10, f5 +fnmsub.s f0, f0, f10, f10 +fnmsub.s f0, f0, f10, f15 +fnmsub.s f0, f0, f10, f20 +fnmsub.s f0, f0, f10, f25 +fnmsub.s f0, f0, f10, f31 +fnmsub.s f0, f0, f15, f0 +fnmsub.s f0, f0, f15, f1 +fnmsub.s f0, f0, f15, f5 +fnmsub.s f0, f0, f15, f10 +fnmsub.s f0, f0, f15, f15 +fnmsub.s f0, f0, f15, f20 +fnmsub.s f0, f0, f15, f25 +fnmsub.s f0, f0, f15, f31 +fnmsub.s f0, f0, f20, f0 +fnmsub.s f0, f0, f20, f1 +fnmsub.s f0, f0, f20, f5 +fnmsub.s f0, f0, f20, f10 +fnmsub.s f0, f0, f20, f15 +fnmsub.s f0, f0, f20, f20 +fnmsub.s f0, f0, f20, f25 +fnmsub.s f0, f0, f20, f31 +fnmsub.s f0, f0, f25, f0 +fnmsub.s f0, f0, f25, f1 +fnmsub.s f0, f0, f25, f5 +fnmsub.s f0, f0, f25, f10 +fnmsub.s f0, f0, f25, f15 +fnmsub.s f0, f0, f25, f20 +fnmsub.s f0, f0, f25, f25 +fnmsub.s f0, f0, f25, f31 +fnmsub.s f0, f0, f31, f0 +fnmsub.s f0, f0, f31, f1 +fnmsub.s f0, f0, f31, f5 +fnmsub.s f0, f0, f31, f10 +fnmsub.s f0, f0, f31, f15 +fnmsub.s f0, f0, f31, f20 +fnmsub.s f0, f0, f31, f25 +fnmsub.s f0, f0, f31, f31 +fnmsub.s f0, f1, f0, f0 +fnmsub.s f0, f1, f0, f1 +fnmsub.s f0, f1, f0, f5 +fnmsub.s f0, f1, f0, f10 +fnmsub.s f0, f1, f0, f15 +fnmsub.s f0, f1, f0, f20 +fnmsub.s f0, f1, f0, f25 +fnmsub.s f0, f1, f0, f31 +fnmsub.s f0, f1, f1, f0 +fnmsub.s f0, f1, f1, f1 +fnmsub.s f0, f1, f1, f5 +fnmsub.s f0, f1, f1, f10 +fnmsub.s f0, f1, f1, f15 +fnmsub.s f0, f1, f1, f20 +fnmsub.s f0, f1, f1, f25 +fnmsub.s f0, f1, f1, f31 +fnmsub.s f0, f1, f5, f0 +fnmsub.s f0, f1, f5, f1 +fnmsub.s f0, f1, f5, f5 +fnmsub.s f0, f1, f5, f10 +fnmsub.s f0, f1, f5, f15 +fnmsub.s f0, f1, f5, f20 +fnmsub.s f0, f1, f5, f25 +fnmsub.s f0, f1, f5, f31 +fnmsub.s f0, f1, f10, f0 +fnmsub.s f0, f1, f10, f1 +fnmsub.s f0, f1, f10, f5 +fnmsub.s f0, f1, f10, f10 +fnmsub.s f0, f1, f10, f15 +fnmsub.s f0, f1, f10, f20 +fnmsub.s f0, f1, f10, f25 +fnmsub.s f0, f1, f10, f31 +fnmsub.s f0, f1, f15, f0 +fnmsub.s f0, f1, f15, f1 +fnmsub.s f0, f1, f15, f5 +fnmsub.s f0, f1, f15, f10 +fnmsub.s f0, f1, f15, f15 +fnmsub.s f0, f1, f15, f20 +fnmsub.s f0, f1, f15, f25 +fnmsub.s f0, f1, f15, f31 +fnmsub.s f0, f1, f20, f0 +fnmsub.s f0, f1, f20, f1 +fnmsub.s f0, f1, f20, f5 +fnmsub.s f0, f1, f20, f10 +fnmsub.s f0, f1, f20, f15 +fnmsub.s f0, f1, f20, f20 +fnmsub.s f0, f1, f20, f25 +fnmsub.s f0, f1, f20, f31 +fnmsub.s f0, f1, f25, f0 +fnmsub.s f0, f1, f25, f1 +fnmsub.s f0, f1, f25, f5 +fnmsub.s f0, f1, f25, f10 +fnmsub.s f0, f1, f25, f15 +fnmsub.s f0, f1, f25, f20 +fnmsub.s f0, f1, f25, f25 +fnmsub.s f0, f1, f25, f31 +fnmsub.s f0, f1, f31, f0 +fnmsub.s f0, f1, f31, f1 +fnmsub.s f0, f1, f31, f5 +fnmsub.s f0, f1, f31, f10 +fnmsub.s f0, f1, f31, f15 +fnmsub.s f0, f1, f31, f20 +fnmsub.s f0, f1, f31, f25 +fnmsub.s f0, f1, f31, f31 +fnmsub.s f0, f5, f0, f0 +fnmsub.s f0, f5, f0, f1 +fnmsub.s f0, f5, f0, f5 +fnmsub.s f0, f5, f0, f10 +fnmsub.s f0, f5, f0, f15 +fnmsub.s f0, f5, f0, f20 +fnmsub.s f0, f5, f0, f25 +fnmsub.s f0, f5, f0, f31 +fnmsub.s f0, f5, f1, f0 +fnmsub.s f0, f5, f1, f1 +fnmsub.s f0, f5, f1, f5 +fnmsub.s f0, f5, f1, f10 +fnmsub.s f0, f5, f1, f15 +fnmsub.s f0, f5, f1, f20 +fnmsub.s f0, f5, f1, f25 +fnmsub.s f0, f5, f1, f31 +fnmsub.s f0, f5, f5, f0 +fnmsub.s f0, f5, f5, f1 +fnmsub.s f0, f5, f5, f5 +fnmsub.s f0, f5, f5, f10 +fnmsub.s f0, f5, f5, f15 +fnmsub.s f0, f5, f5, f20 +fnmsub.s f0, f5, f5, f25 +fnmsub.s f0, f5, f5, f31 +fnmsub.s f0, f5, f10, f0 +fnmsub.s f0, f5, f10, f1 +fnmsub.s f0, f5, f10, f5 +fnmsub.s f0, f5, f10, f10 +fnmsub.s f0, f5, f10, f15 +fnmsub.s f0, f5, f10, f20 +fnmsub.s f0, f5, f10, f25 +fnmsub.s f0, f5, f10, f31 +fnmsub.s f0, f5, f15, f0 +fnmsub.s f0, f5, f15, f1 +fnmsub.s f0, f5, f15, f5 +fnmsub.s f0, f5, f15, f10 +fnmsub.s f0, f5, f15, f15 +fnmsub.s f0, f5, f15, f20 +fnmsub.s f0, f5, f15, f25 +fnmsub.s f0, f5, f15, f31 +fnmsub.s f0, f5, f20, f0 +fnmsub.s f0, f5, f20, f1 +fnmsub.s f0, f5, f20, f5 +fnmsub.s f0, f5, f20, f10 +fnmsub.s f0, f5, f20, f15 +fnmsub.s f0, f5, f20, f20 +fnmsub.s f0, f5, f20, f25 +fnmsub.s f0, f5, f20, f31 +fnmsub.s f0, f5, f25, f0 +fnmsub.s f0, f5, f25, f1 +fnmsub.s f0, f5, f25, f5 +fnmsub.s f0, f5, f25, f10 +fnmsub.s f0, f5, f25, f15 +fnmsub.s f0, f5, f25, f20 +fnmsub.s f0, f5, f25, f25 +fnmsub.s f0, f5, f25, f31 +fnmsub.s f0, f5, f31, f0 +fnmsub.s f0, f5, f31, f1 +fnmsub.s f0, f5, f31, f5 +fnmsub.s f0, f5, f31, f10 +fnmsub.s f0, f5, f31, f15 +fnmsub.s f0, f5, f31, f20 +fnmsub.s f0, f5, f31, f25 +fnmsub.s f0, f5, f31, f31 +fnmsub.s f0, f10, f0, f0 +fnmsub.s f0, f10, f0, f1 +fnmsub.s f0, f10, f0, f5 +fnmsub.s f0, f10, f0, f10 +fnmsub.s f0, f10, f0, f15 +fnmsub.s f0, f10, f0, f20 +fnmsub.s f0, f10, f0, f25 +fnmsub.s f0, f10, f0, f31 +fnmsub.s f0, f10, f1, f0 +fnmsub.s f0, f10, f1, f1 +fnmsub.s f0, f10, f1, f5 +fnmsub.s f0, f10, f1, f10 +fnmsub.s f0, f10, f1, f15 +fnmsub.s f0, f10, f1, f20 +fnmsub.s f0, f10, f1, f25 +fnmsub.s f0, f10, f1, f31 +fnmsub.s f0, f10, f5, f0 +fnmsub.s f0, f10, f5, f1 +fnmsub.s f0, f10, f5, f5 +fnmsub.s f0, f10, f5, f10 +fnmsub.s f0, f10, f5, f15 +fnmsub.s f0, f10, f5, f20 +fnmsub.s f0, f10, f5, f25 +fnmsub.s f0, f10, f5, f31 +fnmsub.s f0, f10, f10, f0 +fnmsub.s f0, f10, f10, f1 +fnmsub.s f0, f10, f10, f5 +fnmsub.s f0, f10, f10, f10 +fnmsub.s f0, f10, f10, f15 +fnmsub.s f0, f10, f10, f20 +fnmsub.s f0, f10, f10, f25 +fnmsub.s f0, f10, f10, f31 +fnmsub.s f0, f10, f15, f0 +fnmsub.s f0, f10, f15, f1 +fnmsub.s f0, f10, f15, f5 +fnmsub.s f0, f10, f15, f10 +fnmsub.s f0, f10, f15, f15 +fnmsub.s f0, f10, f15, f20 +fnmsub.s f0, f10, f15, f25 +fnmsub.s f0, f10, f15, f31 +fnmsub.s f0, f10, f20, f0 +fnmsub.s f0, f10, f20, f1 +fnmsub.s f0, f10, f20, f5 +fnmsub.s f0, f10, f20, f10 +fnmsub.s f0, f10, f20, f15 +fnmsub.s f0, f10, f20, f20 +fnmsub.s f0, f10, f20, f25 +fnmsub.s f0, f10, f20, f31 +fnmsub.s f0, f10, f25, f0 +fnmsub.s f0, f10, f25, f1 +fnmsub.s f0, f10, f25, f5 +fnmsub.s f0, f10, f25, f10 +fnmsub.s f0, f10, f25, f15 +fnmsub.s f0, f10, f25, f20 +fnmsub.s f0, f10, f25, f25 +fnmsub.s f0, f10, f25, f31 +fnmsub.s f0, f10, f31, f0 +fnmsub.s f0, f10, f31, f1 +fnmsub.s f0, f10, f31, f5 +fnmsub.s f0, f10, f31, f10 +fnmsub.s f0, f10, f31, f15 +fnmsub.s f0, f10, f31, f20 +fnmsub.s f0, f10, f31, f25 +fnmsub.s f0, f10, f31, f31 +fnmsub.s f0, f15, f0, f0 +fnmsub.s f0, f15, f0, f1 +fnmsub.s f0, f15, f0, f5 +fnmsub.s f0, f15, f0, f10 +fnmsub.s f0, f15, f0, f15 +fnmsub.s f0, f15, f0, f20 +fnmsub.s f0, f15, f0, f25 +fnmsub.s f0, f15, f0, f31 +fnmsub.s f0, f15, f1, f0 +fnmsub.s f0, f15, f1, f1 +fnmsub.s f0, f15, f1, f5 +fnmsub.s f0, f15, f1, f10 +fnmsub.s f0, f15, f1, f15 +fnmsub.s f0, f15, f1, f20 +fnmsub.s f0, f15, f1, f25 +fnmsub.s f0, f15, f1, f31 +fnmsub.s f0, f15, f5, f0 +fnmsub.s f0, f15, f5, f1 +fnmsub.s f0, f15, f5, f5 +fnmsub.s f0, f15, f5, f10 +fnmsub.s f0, f15, f5, f15 +fnmsub.s f0, f15, f5, f20 +fnmsub.s f0, f15, f5, f25 +fnmsub.s f0, f15, f5, f31 +fnmsub.s f0, f15, f10, f0 +fnmsub.s f0, f15, f10, f1 +fnmsub.s f0, f15, f10, f5 +fnmsub.s f0, f15, f10, f10 +fnmsub.s f0, f15, f10, f15 +fnmsub.s f0, f15, f10, f20 +fnmsub.s f0, f15, f10, f25 +fnmsub.s f0, f15, f10, f31 +fnmsub.s f0, f15, f15, f0 +fnmsub.s f0, f15, f15, f1 +fnmsub.s f0, f15, f15, f5 +fnmsub.s f0, f15, f15, f10 +fnmsub.s f0, f15, f15, f15 +fnmsub.s f0, f15, f15, f20 +fnmsub.s f0, f15, f15, f25 +fnmsub.s f0, f15, f15, f31 +fnmsub.s f0, f15, f20, f0 +fnmsub.s f0, f15, f20, f1 +fnmsub.s f0, f15, f20, f5 +fnmsub.s f0, f15, f20, f10 +fnmsub.s f0, f15, f20, f15 +fnmsub.s f0, f15, f20, f20 +fnmsub.s f0, f15, f20, f25 +fnmsub.s f0, f15, f20, f31 +fnmsub.s f0, f15, f25, f0 +fnmsub.s f0, f15, f25, f1 +fnmsub.s f0, f15, f25, f5 +fnmsub.s f0, f15, f25, f10 +fnmsub.s f0, f15, f25, f15 +fnmsub.s f0, f15, f25, f20 +fnmsub.s f0, f15, f25, f25 +fnmsub.s f0, f15, f25, f31 +fnmsub.s f0, f15, f31, f0 +fnmsub.s f0, f15, f31, f1 +fnmsub.s f0, f15, f31, f5 +fnmsub.s f0, f15, f31, f10 +fnmsub.s f0, f15, f31, f15 +fnmsub.s f0, f15, f31, f20 +fnmsub.s f0, f15, f31, f25 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f15 +fsgnj.s f0, f10, f20 +fsgnj.s f0, f10, f25 +fsgnj.s f0, f10, f31 +fsgnj.s f0, f15, f0 +fsgnj.s f0, f15, f1 +fsgnj.s f0, f15, f5 +fsgnj.s f0, f15, f10 +fsgnj.s f0, f15, f15 +fsgnj.s f0, f15, f20 +fsgnj.s f0, f15, f25 +fsgnj.s f0, f15, f31 +fsgnj.s f0, f20, f0 +fsgnj.s f0, f20, f1 +fsgnj.s f0, f20, f5 +fsgnj.s f0, f20, f10 +fsgnj.s f0, f20, f15 +fsgnj.s f0, f20, f20 +fsgnj.s f0, f20, f25 +fsgnj.s f0, f20, f31 +fsgnj.s f0, f25, f0 +fsgnj.s f0, f25, f1 +fsgnj.s f0, f25, f5 +fsgnj.s f0, f25, f10 +fsgnj.s f0, f25, f15 +fsgnj.s f0, f25, f20 +fsgnj.s f0, f25, f25 +fsgnj.s f0, f25, f31 +fsgnj.s f0, f31, f0 +fsgnj.s f0, f31, f1 +fsgnj.s f0, f31, f5 +fsgnj.s f0, f31, f10 +fsgnj.s f0, f31, f15 +fsgnj.s f0, f31, f20 +fsgnj.s f0, f31, f25 +fsgnj.s f0, f31, f31 +fsgnj.s f1, f0, f0 +fsgnj.s f1, f0, f1 +fsgnj.s f1, f0, f5 +fsgnj.s f1, f0, f10 +fsgnj.s f1, f0, f15 +fsgnj.s f1, f0, f20 +fsgnj.s f1, f0, f25 +fsgnj.s f1, f0, f31 +fsgnj.s f1, f1, f0 +fsgnj.s f1, f1, f1 +fsgnj.s f1, f1, f5 +fsgnj.s f1, f1, f10 +fsgnj.s f1, f1, f15 +fsgnj.s f1, f1, f20 +fsgnj.s f1, f1, f25 +fsgnj.s f1, f1, f31 +fsgnj.s f1, f5, f0 +fsgnj.s f1, f5, f1 +fsgnj.s f1, f5, f5 +fsgnj.s f1, f5, f10 +fsgnj.s f1, f5, f15 +fsgnj.s f1, f5, f20 +fsgnj.s f1, f5, f25 +fsgnj.s f1, f5, f31 +fsgnj.s f1, f10, f0 +fsgnj.s f1, f10, f1 +fsgnj.s f1, f10, f5 +fsgnj.s f1, f10, f10 +fsgnj.s f1, f10, f15 +fsgnj.s f1, f10, f20 +fsgnj.s f1, f10, f25 +fsgnj.s f1, f10, f31 +fsgnj.s f1, f15, f0 +fsgnj.s f1, f15, f1 +fsgnj.s f1, f15, f5 +fsgnj.s f1, f15, f10 +fsgnj.s f1, f15, f15 +fsgnj.s f1, f15, f20 +fsgnj.s f1, f15, f25 +fsgnj.s f1, f15, f31 +fsgnj.s f1, f20, f0 +fsgnj.s f1, f20, f1 +fsgnj.s f1, f20, f5 +fsgnj.s f1, f20, f10 +fsgnj.s f1, f20, f15 +fsgnj.s f1, f20, f20 +fsgnj.s f1, f20, f25 +fsgnj.s f1, f20, f31 +fsgnj.s f1, f25, f0 +fsgnj.s f1, f25, f1 +fsgnj.s f1, f25, f5 +fsgnj.s f1, f25, f10 +fsgnj.s f1, f25, f15 +fsgnj.s f1, f25, f20 +fsgnj.s f1, f25, f25 +fsgnj.s f1, f25, f31 +fsgnj.s f1, f31, f0 +fsgnj.s f1, f31, f1 +fsgnj.s f1, f31, f5 +fsgnj.s f1, f31, f10 +fsgnj.s f1, f31, f15 +fsgnj.s f1, f31, f20 +fsgnj.s f1, f31, f25 +fsgnj.s f1, f31, f31 +fsgnj.s f5, f0, f0 +fsgnj.s f5, f0, f1 +fsgnj.s f5, f0, f5 +fsgnj.s f5, f0, f10 +fsgnj.s f5, f0, f15 +fsgnj.s f5, f0, f20 +fsgnj.s f5, f0, f25 +fsgnj.s f5, f0, f31 +fsgnj.s f5, f1, f0 +fsgnj.s f5, f1, f1 +fsgnj.s f5, f1, f5 +fsgnj.s f5, f1, f10 +fsgnj.s f5, f1, f15 +fsgnj.s f5, f1, f20 +fsgnj.s f5, f1, f25 +fsgnj.s f5, f1, f31 +fsgnj.s f5, f5, f0 +fsgnj.s f5, f5, f1 +fsgnj.s f5, f5, f5 +fsgnj.s f5, f5, f10 +fsgnj.s f5, f5, f15 +fsgnj.s f5, f5, f20 +fsgnj.s f5, f5, f25 +fsgnj.s f5, f5, f31 +fsgnj.s f5, f10, f0 +fsgnj.s f5, f10, f1 +fsgnj.s f5, f10, f5 +fsgnj.s f5, f10, f10 +fsgnj.s f5, f10, f15 +fsgnj.s f5, f10, f20 +fsgnj.s f5, f10, f25 +fsgnj.s f5, f10, f31 +fsgnj.s f5, f15, f0 +fsgnj.s f5, f15, f1 +fsgnj.s f5, f15, f5 +fsgnj.s f5, f15, f10 +fsgnj.s f5, f15, f15 +fsgnj.s f5, f15, f20 +fsgnj.s f5, f15, f25 +fsgnj.s f5, f15, f31 +fsgnj.s f5, f20, f0 +fsgnj.s f5, f20, f1 +fsgnj.s f5, f20, f5 +fsgnj.s f5, f20, f10 +fsgnj.s f5, f20, f15 +fsgnj.s f5, f20, f20 +fsgnj.s f5, f20, f25 +fsgnj.s f5, f20, f31 +fsgnj.s f5, f25, f0 +fsgnj.s f5, f25, f1 +fsgnj.s f5, f25, f5 +fsgnj.s f5, f25, f10 +fsgnj.s f5, f25, f15 +fsgnj.s f5, f25, f20 +fsgnj.s f5, f25, f25 +fsgnj.s f5, f25, f31 +fsgnj.s f5, f31, f0 +fsgnj.s f5, f31, f1 +fsgnj.s f5, f31, f5 +fsgnj.s f5, f31, f10 +fsgnj.s f5, f31, f15 +fsgnj.s f5, f31, f20 +fsgnj.s f5, f31, f25 +fsgnj.s f5, f31, f31 +fsgnj.s f10, f0, f0 +fsgnj.s f10, f0, f1 +fsgnj.s f10, f0, f5 +fsgnj.s f10, f0, f10 +fsgnj.s f10, f0, f15 +fsgnj.s f10, f0, f20 +fsgnj.s f10, f0, f25 +fsgnj.s f10, f0, f31 +fsgnj.s f10, f1, f0 +fsgnj.s f10, f1, f1 +fsgnj.s f10, f1, f5 +fsgnj.s f10, f1, f10 +fsgnj.s f10, f1, f15 +fsgnj.s f10, f1, f20 +fsgnj.s f10, f1, f25 +fsgnj.s f10, f1, f31 +fsgnj.s f10, f5, f0 +fsgnj.s f10, f5, f1 +fsgnj.s f10, f5, f5 +fsgnj.s f10, f5, f10 +fsgnj.s f10, f5, f15 +fsgnj.s f10, f5, f20 +fsgnj.s f10, f5, f25 +fsgnj.s f10, f5, f31 +fsgnj.s f10, f10, f0 +fsgnj.s f10, f10, f1 +fsgnj.s f10, f10, f5 +fsgnj.s f10, f10, f10 +fsgnj.s f10, f10, f15 +fsgnj.s f10, f10, f20 +fsgnj.s f10, f10, f25 +fsgnj.s f10, f10, f31 +fsgnj.s f10, f15, f0 +fsgnj.s f10, f15, f1 +fsgnj.s f10, f15, f5 +fsgnj.s f10, f15, f10 +fsgnj.s f10, f15, f15 +fsgnj.s f10, f15, f20 +fsgnj.s f10, f15, f25 +fsgnj.s f10, f15, f31 +fsgnj.s f10, f20, f0 +fsgnj.s f10, f20, f1 +fsgnj.s f10, f20, f5 +fsgnj.s f10, f20, f10 +fsgnj.s f10, f20, f15 +fsgnj.s f10, f20, f20 +fsgnj.s f10, f20, f25 +fsgnj.s f10, f20, f31 +fsgnj.s f10, f25, f0 +fsgnj.s f10, f25, f1 +fsgnj.s f10, f25, f5 +fsgnj.s f10, f25, f10 +fsgnj.s f10, f25, f15 +fsgnj.s f10, f25, f20 +fsgnj.s f10, f25, f25 +fsgnj.s f10, f25, f31 +fsgnj.s f10, f31, f0 +fsgnj.s f10, f31, f1 +fsgnj.s f10, f31, f5 +fsgnj.s f10, f31, f10 +fsgnj.s f10, f31, f15 +fsgnj.s f10, f31, f20 +fsgnj.s f10, f31, f25 +fsgnj.s f10, f31, f31 +fsgnj.s f15, f0, f0 +fsgnj.s f15, f0, f1 +fsgnj.s f15, f0, f5 +fsgnj.s f15, f0, f10 +fsgnj.s f15, f0, f15 +fsgnj.s f15, f0, f20 +fsgnj.s f15, f0, f25 +fsgnj.s f15, f0, f31 +fsgnj.s f15, f1, f0 +fsgnj.s f15, f1, f1 +fsgnj.s f15, f1, f5 +fsgnj.s f15, f1, f10 +fsgnj.s f15, f1, f15 +fsgnj.s f15, f1, f20 +fsgnj.s f15, f1, f25 +fsgnj.s f15, f1, f31 +fsgnj.s f15, f5, f0 +fsgnj.s f15, f5, f1 +fsgnj.s f15, f5, f5 +fsgnj.s f15, f5, f10 +fsgnj.s f15, f5, f15 +fsgnj.s f15, f5, f20 +fsgnj.s f15, f5, f25 +fsgnj.s f15, f5, f31 +fsgnj.s f15, f10, f0 +fsgnj.s f15, f10, f1 +fsgnj.s f15, f10, f5 +fsgnj.s f15, f10, f10 +fsgnj.s f15, f10, f15 +fsgnj.s f15, f10, f20 +fsgnj.s f15, f10, f25 +fsgnj.s f15, f10, f31 +fsgnj.s f15, f15, f0 +fsgnj.s f15, f15, f1 +fsgnj.s f15, f15, f5 +fsgnj.s f15, f15, f10 +fsgnj.s f15, f15, f15 +fsgnj.s f15, f15, f20 +fsgnj.s f15, f15, f25 +fsgnj.s f15, f15, f31 +fsgnj.s f15, f20, f0 +fsgnj.s f15, f20, f1 +fsgnj.s f15, f20, f5 +fsgnj.s f15, f20, f10 +fsgnj.s f15, f20, f15 +fsgnj.s f15, f20, f20 +fsgnj.s f15, f20, f25 +fsgnj.s f15, f20, f31 +fsgnj.s f15, f25, f0 +fsgnj.s f15, f25, f1 +fsgnj.s f15, f25, f5 +fsgnj.s f15, f25, f10 +fsgnj.s f15, f25, f15 +fsgnj.s f15, f25, f20 +fsgnj.s f15, f25, f25 +fsgnj.s f15, f25, f31 +fsgnj.s f15, f31, f0 +fsgnj.s f15, f31, f1 +fsgnj.s f15, f31, f5 +fsgnj.s f15, f31, f10 +fsgnj.s f15, f31, f15 +fsgnj.s f15, f31, f20 +fsgnj.s f15, f31, f25 +fsgnj.s f15, f31, f31 +fsgnj.s f20, f0, f0 +fsgnj.s f20, f0, f1 +fsgnj.s f20, f0, f5 +fsgnj.s f20, f0, f10 +fsgnj.s f20, f0, f15 +fsgnj.s f20, f0, f20 +fsgnj.s f20, f0, f25 +fsgnj.s f20, f0, f31 +fsgnj.s f20, f1, f0 +fsgnj.s f20, f1, f1 +fsgnj.s f20, f1, f5 +fsgnj.s f20, f1, f10 +fsgnj.s f20, f1, f15 +fsgnj.s f20, f1, f20 +fsgnj.s f20, f1, f25 +fsgnj.s f20, f1, f31 +fsgnj.s f20, f5, f0 +fsgnj.s f20, f5, f1 +fsgnj.s f20, f5, f5 +fsgnj.s f20, f5, f10 +fsgnj.s f20, f5, f15 +fsgnj.s f20, f5, f20 +fsgnj.s f20, f5, f25 +fsgnj.s f20, f5, f31 +fsgnj.s f20, f10, f0 +fsgnj.s f20, f10, f1 +fsgnj.s f20, f10, f5 +fsgnj.s f20, f10, f10 +fsgnj.s f20, f10, f15 +fsgnj.s f20, f10, f20 +fsgnj.s f20, f10, f25 +fsgnj.s f20, f10, f31 +fsgnj.s f20, f15, f0 +fsgnj.s f20, f15, f1 +fsgnj.s f20, f15, f5 +fsgnj.s f20, f15, f10 +fsgnj.s f20, f15, f15 +fsgnj.s f20, f15, f20 +fsgnj.s f20, f15, f25 +fsgnj.s f20, f15, f31 +fsgnj.s f20, f20, f0 +fsgnj.s f20, f20, f1 +fsgnj.s f20, f20, f5 +fsgnj.s f20, f20, f10 +fsgnj.s f20, f20, f15 +fsgnj.s f20, f20, f20 +fsgnj.s f20, f20, f25 +fsgnj.s f20, f20, f31 +fsgnj.s f20, f25, f0 +fsgnj.s f20, f25, f1 +fsgnj.s f20, f25, f5 +fsgnj.s f20, f25, f10 +fsgnj.s f20, f25, f15 +fsgnj.s f20, f25, f20 +fsgnj.s f20, f25, f25 +fsgnj.s f20, f25, f31 +fsgnj.s f20, f31, f0 +fsgnj.s f20, f31, f1 +fsgnj.s f20, f31, f5 +fsgnj.s f20, f31, f10 +fsgnj.s f20, f31, f15 +fsgnj.s f20, f31, f20 +fsgnj.s f20, f31, f25 +fsgnj.s f20, f31, f31 +fsgnj.s f25, f0, f0 +fsgnj.s f25, f0, f1 +fsgnj.s f25, f0, f5 +fsgnj.s f25, f0, f10 +fsgnj.s f25, f0, f15 +fsgnj.s f25, f0, f20 +fsgnj.s f25, f0, f25 +fsgnj.s f25, f0, f31 +fsgnj.s f25, f1, f0 +fsgnj.s f25, f1, f1 +fsgnj.s f25, f1, f5 +fsgnj.s f25, f1, f10 +fsgnj.s f25, f1, f15 +fsgnj.s f25, f1, f20 +fsgnj.s f25, f1, f25 +fsgnj.s f25, f1, f31 +fsgnj.s f25, f5, f0 +fsgnj.s f25, f5, f1 +fsgnj.s f25, f5, f5 +fsgnj.s f25, f5, f10 +fsgnj.s f25, f5, f15 +fsgnj.s f25, f5, f20 +fsgnj.s f25, f5, f25 +fsgnj.s f25, f5, f31 +fsgnj.s f25, f10, f0 +fsgnj.s f25, f10, f1 +fsgnj.s f25, f10, f5 +fsgnj.s f25, f10, f10 +fsgnj.s f25, f10, f15 +fsgnj.s f25, f10, f20 +fsgnj.s f25, f10, f25 +fsgnj.s f25, f10, f31 +fsgnj.s f25, f15, f0 +fsgnj.s f25, f15, f1 +fsgnj.s f25, f15, f5 +fsgnj.s f25, f15, f10 +fsgnj.s f25, f15, f15 +fsgnj.s f25, f15, f20 +fsgnj.s f25, f15, f25 +fsgnj.s f25, f15, f31 +fsgnj.s f25, f20, f0 +fsgnj.s f25, f20, f1 +fsgnj.s f25, f20, f5 +fsgnj.s f25, f20, f10 +fsgnj.s f25, f20, f15 +fsgnj.s f25, f20, f20 +fsgnj.s f25, f20, f25 +fsgnj.s f25, f20, f31 +fsgnj.s f25, f25, f0 +fsgnj.s f25, f25, f1 +fsgnj.s f25, f25, f5 +fsgnj.s f25, f25, f10 +fsgnj.s f25, f25, f15 +fsgnj.s f25, f25, f20 +fsgnj.s f25, f25, f25 +fsgnj.s f25, f25, f31 +fsgnj.s f25, f31, f0 +fsgnj.s f25, f31, f1 +fsgnj.s f25, f31, f5 +fsgnj.s f25, f31, f10 +fsgnj.s f25, f31, f15 +fsgnj.s f25, f31, f20 +fsgnj.s f25, f31, f25 +fsgnj.s f25, f31, f31 +fsgnj.s f31, f0, f0 +fsgnj.s f31, f0, f1 +fsgnj.s f31, f0, f5 +fsgnj.s f31, f0, f10 +fsgnj.s f31, f0, f15 +fsgnj.s f31, f0, f20 +fsgnj.s f31, f0, f25 +fsgnj.s f31, f0, f31 +fsgnj.s f31, f1, f0 +fsgnj.s f31, f1, f1 +fsgnj.s f31, f1, f5 +fsgnj.s f31, f1, f10 +fsgnj.s f31, f1, f15 +fsgnj.s f31, f1, f20 +fsgnj.s f31, f1, f25 +fsgnj.s f31, f1, f31 +fsgnj.s f31, f5, f0 +fsgnj.s f31, f5, f1 +fsgnj.s f31, f5, f5 +fsgnj.s f31, f5, f10 +fsgnj.s f31, f5, f15 +fsgnj.s f31, f5, f20 +fsgnj.s f31, f5, f25 +fsgnj.s f31, f5, f31 +fsgnj.s f31, f10, f0 +fsgnj.s f31, f10, f1 +fsgnj.s f31, f10, f5 +fsgnj.s f31, f10, f10 +fsgnj.s f31, f10, f15 +fsgnj.s f31, f10, f20 +fsgnj.s f31, f10, f25 +fsgnj.s f31, f10, f31 +fsgnj.s f31, f15, f0 +fsgnj.s f31, f15, f1 +fsgnj.s f31, f15, f5 +fsgnj.s f31, f15, f10 +fsgnj.s f31, f15, f15 +fsgnj.s f31, f15, f20 +fsgnj.s f31, f15, f25 +fsgnj.s f31, f15, f31 +fsgnj.s f31, f20, f0 +fsgnj.s f31, f20, f1 +fsgnj.s f31, f20, f5 +fsgnj.s f31, f20, f10 +fsgnj.s f31, f20, f15 +fsgnj.s f31, f20, f20 +fsgnj.s f31, f20, f25 +fsgnj.s f31, f20, f31 +fsgnj.s f31, f25, f0 +fsgnj.s f31, f25, f1 +fsgnj.s f31, f25, f5 +fsgnj.s f31, f25, f10 +fsgnj.s f31, f25, f15 +fsgnj.s f31, f25, f20 +fsgnj.s f31, f25, f25 +fsgnj.s f31, f25, f31 +fsgnj.s f31, f31, f0 +fsgnj.s f31, f31, f1 +fsgnj.s f31, f31, f5 +fsgnj.s f31, f31, f10 +fsgnj.s f31, f31, f15 +fsgnj.s f31, f31, f20 +fsgnj.s f31, f31, f25 +fsgnj.s f31, f31, f31 diff --git a/tests/riscv/f-extension/fsgnj_s.asm b/tests/riscv/f-extension/fsgnj_s.asm new file mode 100644 index 0000000..cf9672e --- /dev/null +++ b/tests/riscv/f-extension/fsgnj_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fsgnj.s f0, f1, f2 + diff --git a/tests/riscv/f-extension/fsgnj_s.bin b/tests/riscv/f-extension/fsgnj_s.bin new file mode 100644 index 0000000..df00a83 --- /dev/null +++ b/tests/riscv/f-extension/fsgnj_s.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/f-extension/fsgnj_s.disasm b/tests/riscv/f-extension/fsgnj_s.disasm new file mode 100644 index 0000000..97ab03d --- /dev/null +++ b/tests/riscv/f-extension/fsgnj_s.disasm @@ -0,0 +1 @@ +fsgnj.s f0, f1, f2 diff --git a/tests/riscv/f-extension/fsgnjn.s.asm b/tests/riscv/f-extension/fsgnjn.s.asm new file mode 100644 index 0000000..a0642fd --- /dev/null +++ b/tests/riscv/f-extension/fsgnjn.s.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fsgnjn.s f0, f0, f0 +fsgnjn.s f0, f0, f1 +fsgnjn.s f0, f0, f5 +fsgnjn.s f0, f0, f10 +fsgnjn.s f0, f0, f15 +fsgnjn.s f0, f0, f20 +fsgnjn.s f0, f0, f25 +fsgnjn.s f0, f0, f31 +fsgnjn.s f0, f1, f0 +fsgnjn.s f0, f1, f1 +fsgnjn.s f0, f1, f5 +fsgnjn.s f0, f1, f10 +fsgnjn.s f0, f1, f15 +fsgnjn.s f0, f1, f20 +fsgnjn.s f0, f1, f25 +fsgnjn.s f0, f1, f31 +fsgnjn.s f0, f5, f0 +fsgnjn.s f0, f5, f1 +fsgnjn.s f0, f5, f5 +fsgnjn.s f0, f5, f10 +fsgnjn.s f0, f5, f15 +fsgnjn.s f0, f5, f20 +fsgnjn.s f0, f5, f25 +fsgnjn.s f0, f5, f31 +fsgnjn.s f0, f10, f0 +fsgnjn.s f0, f10, f1 +fsgnjn.s f0, f10, f5 +fsgnjn.s f0, f10, f10 +fsgnjn.s f0, f10, f15 +fsgnjn.s f0, f10, f20 +fsgnjn.s f0, f10, f25 +fsgnjn.s f0, f10, f31 +fsgnjn.s f0, f15, f0 +fsgnjn.s f0, f15, f1 +fsgnjn.s f0, f15, f5 +fsgnjn.s f0, f15, f10 +fsgnjn.s f0, f15, f15 +fsgnjn.s f0, f15, f20 +fsgnjn.s f0, f15, f25 +fsgnjn.s f0, f15, f31 +fsgnjn.s f0, f20, f0 +fsgnjn.s f0, f20, f1 +fsgnjn.s f0, f20, f5 +fsgnjn.s f0, f20, f10 +fsgnjn.s f0, f20, f15 +fsgnjn.s f0, f20, f20 +fsgnjn.s f0, f20, f25 +fsgnjn.s f0, f20, f31 +fsgnjn.s f0, f25, f0 +fsgnjn.s f0, f25, f1 +fsgnjn.s f0, f25, f5 +fsgnjn.s f0, f25, f10 +fsgnjn.s f0, f25, f15 +fsgnjn.s f0, f25, f20 +fsgnjn.s f0, f25, f25 +fsgnjn.s f0, f25, f31 +fsgnjn.s f0, f31, f0 +fsgnjn.s f0, f31, f1 +fsgnjn.s f0, f31, f5 +fsgnjn.s f0, f31, f10 +fsgnjn.s f0, f31, f15 +fsgnjn.s f0, f31, f20 +fsgnjn.s f0, f31, f25 +fsgnjn.s f0, f31, f31 +fsgnjn.s f1, f0, f0 +fsgnjn.s f1, f0, f1 +fsgnjn.s f1, f0, f5 +fsgnjn.s f1, f0, f10 +fsgnjn.s f1, f0, f15 +fsgnjn.s f1, f0, f20 +fsgnjn.s f1, f0, f25 +fsgnjn.s f1, f0, f31 +fsgnjn.s f1, f1, f0 +fsgnjn.s f1, f1, f1 +fsgnjn.s f1, f1, f5 +fsgnjn.s f1, f1, f10 +fsgnjn.s f1, f1, f15 +fsgnjn.s f1, f1, f20 +fsgnjn.s f1, f1, f25 +fsgnjn.s f1, f1, f31 +fsgnjn.s f1, f5, f0 +fsgnjn.s f1, f5, f1 +fsgnjn.s f1, f5, f5 +fsgnjn.s f1, f5, f10 +fsgnjn.s f1, f5, f15 +fsgnjn.s f1, f5, f20 +fsgnjn.s f1, f5, f25 +fsgnjn.s f1, f5, f31 +fsgnjn.s f1, f10, f0 +fsgnjn.s f1, f10, f1 +fsgnjn.s f1, f10, f5 +fsgnjn.s f1, f10, f10 +fsgnjn.s f1, f10, f15 +fsgnjn.s f1, f10, f20 +fsgnjn.s f1, f10, f25 +fsgnjn.s f1, f10, f31 +fsgnjn.s f1, f15, f0 +fsgnjn.s f1, f15, f1 +fsgnjn.s f1, f15, f5 +fsgnjn.s f1, f15, f10 +fsgnjn.s f1, f15, f15 +fsgnjn.s f1, f15, f20 +fsgnjn.s f1, f15, f25 +fsgnjn.s f1, f15, f31 +fsgnjn.s f1, f20, f0 +fsgnjn.s f1, f20, f1 +fsgnjn.s f1, f20, f5 +fsgnjn.s f1, f20, f10 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+fsgnjn.s f31, f25, f5 +fsgnjn.s f31, f25, f10 +fsgnjn.s f31, f25, f15 +fsgnjn.s f31, f25, f20 +fsgnjn.s f31, f25, f25 +fsgnjn.s f31, f25, f31 +fsgnjn.s f31, f31, f0 +fsgnjn.s f31, f31, f1 +fsgnjn.s f31, f31, f5 +fsgnjn.s f31, f31, f10 +fsgnjn.s f31, f31, f15 +fsgnjn.s f31, f31, f20 +fsgnjn.s f31, f31, f25 +fsgnjn.s f31, f31, f31 + diff --git a/tests/riscv/f-extension/fsgnjn.s.bin b/tests/riscv/f-extension/fsgnjn.s.bin new file mode 100644 index 0000000000000000000000000000000000000000..b63dbb2b083b4fb48677acd9328967dbc4bed22f GIT binary patch literal 2048 zcmWmC@rIo{7=`hpRH@PtB1Fj9cXE^}ReE$(snT28LWBr8N|h?TnD0hv7{eIm{PrJ< zz26ldk7r$9{q^_t)s_4!|H&Wu=X8B_mOrQKv;M3<>(BbL{;WUi&zJs*|3N;;H@T5l z?oDod!?nCapdG39d&+=35<*oaadv9KNU*wDY zk_UO`zT`n(`d{U%{FX;~@4n^nbl^YmANUXa2mS;9f#2`bf&ajN;6Lym_z(OCe!u03 z|3N;;H@T5l?oDod!?nCapdG39d&+=35<*oaa zdv9KNU*wDYk_UO`zT`n(`d{U%{FX;~@4f|pz!&fZd;wp;7w`pq0bkQMebYC6(>Hz7 zw@Z(|;cxgG{)WHdZ}=PjfIr|5_yhicKj07e1OA4;;cxgG{)WHdZ}=PjfIr|5_yhic zKj07e1OA4;;cxgG{)WHdZ}=PjhQHx&_#6I)zu|BA+vDjv+IO_?Xy4JkqkTvFj`khx zyX(8Y>$|?|yT0rDrMLfX|K0w({dfEC_TTNl+kdqGX#dgvqy0zwkM zyZv|j@AlvAzw@8?P5dT)6TgYy#Bbs^@jLWGKlDRC^g}=NgT2B zfAT;1pZrh$C;yZG$$#cQ^Pl<8{Ad0%|C#^H|Kxx2Klz{hPyQ$WlmE$o=0EeF`Oo}k z{xkoX|IGj7fAT;1pZrh$C;yZG$^Ybk@;~{X{7?QT|C9g8f8n?ATlg*f7JduAh2O&O z(l7neFa6Rl{nD>X&;R0o@xS;(zhK_+R`l z{ulp?|H6Oazwlr9FZ>t&3;%`x#sA`e@xS3?H&Ol|-G literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fsgnjn.s.disasm b/tests/riscv/f-extension/fsgnjn.s.disasm new file mode 100644 index 0000000..2aafe62 --- /dev/null +++ b/tests/riscv/f-extension/fsgnjn.s.disasm @@ -0,0 +1,512 @@ +fsgnjn.s f0, f0, f0 +fsgnjn.s f0, f0, f1 +fsgnjn.s f0, f0, f5 +fsgnjn.s f0, f0, f10 +fsgnjn.s f0, f0, f15 +fsgnjn.s f0, f0, f20 +fsgnjn.s f0, f0, f25 +fsgnjn.s f0, f0, f31 +fsgnjn.s f0, f1, f0 +fsgnjn.s f0, f1, f1 +fsgnjn.s f0, f1, f5 +fsgnjn.s f0, f1, f10 +fsgnjn.s f0, f1, f15 +fsgnjn.s f0, f1, f20 +fsgnjn.s f0, f1, f25 +fsgnjn.s f0, f1, f31 +fsgnjn.s f0, f5, f0 +fsgnjn.s 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f25, f10, f10 +fsgnjn.s f25, f10, f15 +fsgnjn.s f25, f10, f20 +fsgnjn.s f25, f10, f25 +fsgnjn.s f25, f10, f31 +fsgnjn.s f25, f15, f0 +fsgnjn.s f25, f15, f1 +fsgnjn.s f25, f15, f5 +fsgnjn.s f25, f15, f10 +fsgnjn.s f25, f15, f15 +fsgnjn.s f25, f15, f20 +fsgnjn.s f25, f15, f25 +fsgnjn.s f25, f15, f31 +fsgnjn.s f25, f20, f0 +fsgnjn.s f25, f20, f1 +fsgnjn.s f25, f20, f5 +fsgnjn.s f25, f20, f10 +fsgnjn.s f25, f20, f15 +fsgnjn.s f25, f20, f20 +fsgnjn.s f25, f20, f25 +fsgnjn.s f25, f20, f31 +fsgnjn.s f25, f25, f0 +fsgnjn.s f25, f25, f1 +fsgnjn.s f25, f25, f5 +fsgnjn.s f25, f25, f10 +fsgnjn.s f25, f25, f15 +fsgnjn.s f25, f25, f20 +fsgnjn.s f25, f25, f25 +fsgnjn.s f25, f25, f31 +fsgnjn.s f25, f31, f0 +fsgnjn.s f25, f31, f1 +fsgnjn.s f25, f31, f5 +fsgnjn.s f25, f31, f10 +fsgnjn.s f25, f31, f15 +fsgnjn.s f25, f31, f20 +fsgnjn.s f25, f31, f25 +fsgnjn.s f25, f31, f31 +fsgnjn.s f31, f0, f0 +fsgnjn.s f31, f0, f1 +fsgnjn.s f31, f0, f5 +fsgnjn.s f31, f0, f10 +fsgnjn.s f31, f0, f15 +fsgnjn.s f31, f0, f20 +fsgnjn.s f31, f0, f25 +fsgnjn.s f31, f0, f31 +fsgnjn.s f31, f1, f0 +fsgnjn.s f31, f1, f1 +fsgnjn.s f31, f1, f5 +fsgnjn.s f31, f1, f10 +fsgnjn.s f31, f1, f15 +fsgnjn.s f31, f1, f20 +fsgnjn.s f31, f1, f25 +fsgnjn.s f31, f1, f31 +fsgnjn.s f31, f5, f0 +fsgnjn.s f31, f5, f1 +fsgnjn.s f31, f5, f5 +fsgnjn.s f31, f5, f10 +fsgnjn.s f31, f5, f15 +fsgnjn.s f31, f5, f20 +fsgnjn.s f31, f5, f25 +fsgnjn.s f31, f5, f31 +fsgnjn.s f31, f10, f0 +fsgnjn.s f31, f10, f1 +fsgnjn.s f31, f10, f5 +fsgnjn.s f31, f10, f10 +fsgnjn.s f31, f10, f15 +fsgnjn.s f31, f10, f20 +fsgnjn.s f31, f10, f25 +fsgnjn.s f31, f10, f31 +fsgnjn.s f31, f15, f0 +fsgnjn.s f31, f15, f1 +fsgnjn.s f31, f15, f5 +fsgnjn.s f31, f15, f10 +fsgnjn.s f31, f15, f15 +fsgnjn.s f31, f15, f20 +fsgnjn.s f31, f15, f25 +fsgnjn.s f31, f15, f31 +fsgnjn.s f31, f20, f0 +fsgnjn.s f31, f20, f1 +fsgnjn.s f31, f20, f5 +fsgnjn.s f31, f20, f10 +fsgnjn.s f31, f20, f15 +fsgnjn.s f31, f20, f20 +fsgnjn.s f31, f20, f25 +fsgnjn.s f31, f20, f31 +fsgnjn.s f31, f25, f0 +fsgnjn.s f31, f25, f1 +fsgnjn.s f31, f25, f5 +fsgnjn.s f31, f25, f10 +fsgnjn.s f31, f25, f15 +fsgnjn.s f31, f25, f20 +fsgnjn.s f31, f25, f25 +fsgnjn.s f31, f25, f31 +fsgnjn.s f31, f31, f0 +fsgnjn.s f31, f31, f1 +fsgnjn.s f31, f31, f5 +fsgnjn.s f31, f31, f10 +fsgnjn.s f31, f31, f15 +fsgnjn.s f31, f31, f20 +fsgnjn.s f31, f31, f25 +fsgnjn.s f31, f31, f31 diff --git a/tests/riscv/f-extension/fsgnjn_s.asm b/tests/riscv/f-extension/fsgnjn_s.asm new file mode 100644 index 0000000..9e6c544 --- /dev/null +++ b/tests/riscv/f-extension/fsgnjn_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fsgnjn.s f0, f1, f2 + diff --git a/tests/riscv/f-extension/fsgnjn_s.bin b/tests/riscv/f-extension/fsgnjn_s.bin new file mode 100644 index 0000000..6d8b585 --- /dev/null +++ b/tests/riscv/f-extension/fsgnjn_s.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/f-extension/fsgnjn_s.disasm b/tests/riscv/f-extension/fsgnjn_s.disasm new file mode 100644 index 0000000..104163f --- /dev/null +++ b/tests/riscv/f-extension/fsgnjn_s.disasm @@ -0,0 +1 @@ +fsgnjn.s f0, f1, f2 diff --git a/tests/riscv/f-extension/fsgnjx.s.asm b/tests/riscv/f-extension/fsgnjx.s.asm new file mode 100644 index 0000000..e83e455 --- /dev/null +++ b/tests/riscv/f-extension/fsgnjx.s.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +fsgnjx.s f0, f0, f0 +fsgnjx.s f0, f0, f1 +fsgnjx.s f0, f0, f5 +fsgnjx.s f0, f0, f10 +fsgnjx.s f0, f0, f15 +fsgnjx.s f0, f0, f20 +fsgnjx.s f0, f0, f25 +fsgnjx.s f0, f0, f31 +fsgnjx.s f0, f1, f0 +fsgnjx.s f0, f1, f1 +fsgnjx.s f0, f1, f5 +fsgnjx.s f0, f1, f10 +fsgnjx.s f0, f1, f15 +fsgnjx.s f0, f1, f20 +fsgnjx.s f0, f1, f25 +fsgnjx.s f0, f1, f31 +fsgnjx.s f0, f5, f0 +fsgnjx.s f0, f5, f1 +fsgnjx.s f0, f5, f5 +fsgnjx.s f0, f5, f10 +fsgnjx.s f0, f5, f15 +fsgnjx.s f0, f5, f20 +fsgnjx.s f0, f5, f25 +fsgnjx.s f0, f5, f31 +fsgnjx.s f0, f10, f0 +fsgnjx.s f0, f10, f1 +fsgnjx.s f0, f10, f5 +fsgnjx.s f0, f10, f10 +fsgnjx.s f0, f10, f15 +fsgnjx.s f0, f10, f20 +fsgnjx.s f0, f10, f25 +fsgnjx.s f0, f10, f31 +fsgnjx.s f0, f15, f0 +fsgnjx.s f0, f15, f1 +fsgnjx.s f0, f15, f5 +fsgnjx.s f0, f15, f10 +fsgnjx.s f0, f15, f15 +fsgnjx.s f0, f15, f20 +fsgnjx.s f0, f15, f25 +fsgnjx.s f0, f15, f31 +fsgnjx.s f0, f20, f0 +fsgnjx.s f0, f20, f1 +fsgnjx.s f0, f20, f5 +fsgnjx.s f0, f20, f10 +fsgnjx.s f0, f20, f15 +fsgnjx.s f0, f20, f20 +fsgnjx.s f0, f20, f25 +fsgnjx.s f0, f20, f31 +fsgnjx.s f0, f25, f0 +fsgnjx.s f0, f25, f1 +fsgnjx.s f0, f25, f5 +fsgnjx.s f0, f25, f10 +fsgnjx.s f0, f25, f15 +fsgnjx.s f0, f25, f20 +fsgnjx.s f0, f25, f25 +fsgnjx.s f0, f25, f31 +fsgnjx.s f0, f31, f0 +fsgnjx.s f0, f31, f1 +fsgnjx.s f0, f31, f5 +fsgnjx.s f0, f31, f10 +fsgnjx.s f0, f31, f15 +fsgnjx.s f0, f31, f20 +fsgnjx.s f0, f31, f25 +fsgnjx.s f0, f31, f31 +fsgnjx.s f1, f0, f0 +fsgnjx.s f1, f0, f1 +fsgnjx.s f1, f0, f5 +fsgnjx.s f1, f0, f10 +fsgnjx.s f1, f0, f15 +fsgnjx.s f1, f0, f20 +fsgnjx.s f1, f0, f25 +fsgnjx.s f1, f0, f31 +fsgnjx.s f1, f1, f0 +fsgnjx.s f1, f1, f1 +fsgnjx.s f1, f1, f5 +fsgnjx.s f1, f1, f10 +fsgnjx.s f1, f1, f15 +fsgnjx.s f1, f1, f20 +fsgnjx.s f1, f1, f25 +fsgnjx.s f1, f1, f31 +fsgnjx.s f1, f5, f0 +fsgnjx.s f1, f5, f1 +fsgnjx.s f1, f5, f5 +fsgnjx.s f1, f5, f10 +fsgnjx.s f1, f5, f15 +fsgnjx.s f1, f5, f20 +fsgnjx.s f1, f5, f25 +fsgnjx.s f1, f5, f31 +fsgnjx.s f1, f10, f0 +fsgnjx.s f1, f10, f1 +fsgnjx.s f1, f10, f5 +fsgnjx.s f1, f10, f10 +fsgnjx.s f1, f10, f15 +fsgnjx.s f1, f10, f20 +fsgnjx.s f1, f10, f25 +fsgnjx.s f1, f10, f31 +fsgnjx.s f1, f15, f0 +fsgnjx.s f1, f15, f1 +fsgnjx.s f1, f15, f5 +fsgnjx.s f1, f15, f10 +fsgnjx.s f1, f15, f15 +fsgnjx.s f1, f15, f20 +fsgnjx.s f1, f15, f25 +fsgnjx.s f1, f15, f31 +fsgnjx.s f1, f20, f0 +fsgnjx.s f1, f20, f1 +fsgnjx.s f1, f20, f5 +fsgnjx.s f1, f20, f10 +fsgnjx.s f1, f20, f15 +fsgnjx.s f1, f20, f20 +fsgnjx.s f1, f20, f25 +fsgnjx.s f1, f20, f31 +fsgnjx.s f1, f25, f0 +fsgnjx.s f1, f25, f1 +fsgnjx.s f1, f25, f5 +fsgnjx.s f1, f25, f10 +fsgnjx.s f1, f25, f15 +fsgnjx.s f1, f25, f20 +fsgnjx.s f1, f25, f25 +fsgnjx.s f1, f25, f31 +fsgnjx.s f1, f31, f0 +fsgnjx.s f1, f31, f1 +fsgnjx.s f1, f31, f5 +fsgnjx.s f1, f31, f10 +fsgnjx.s f1, f31, f15 +fsgnjx.s f1, f31, f20 +fsgnjx.s f1, f31, f25 +fsgnjx.s f1, f31, f31 +fsgnjx.s f5, f0, f0 +fsgnjx.s f5, f0, f1 +fsgnjx.s f5, f0, f5 +fsgnjx.s f5, f0, f10 +fsgnjx.s f5, f0, f15 +fsgnjx.s f5, f0, f20 +fsgnjx.s f5, f0, f25 +fsgnjx.s f5, f0, f31 +fsgnjx.s f5, f1, f0 +fsgnjx.s f5, f1, f1 +fsgnjx.s f5, f1, f5 +fsgnjx.s f5, f1, f10 +fsgnjx.s f5, f1, f15 +fsgnjx.s f5, f1, f20 +fsgnjx.s f5, f1, f25 +fsgnjx.s f5, f1, f31 +fsgnjx.s f5, f5, f0 +fsgnjx.s f5, f5, f1 +fsgnjx.s f5, f5, f5 +fsgnjx.s f5, f5, f10 +fsgnjx.s f5, f5, f15 +fsgnjx.s f5, f5, f20 +fsgnjx.s f5, f5, f25 +fsgnjx.s f5, f5, f31 +fsgnjx.s f5, f10, f0 +fsgnjx.s f5, f10, f1 +fsgnjx.s f5, f10, f5 +fsgnjx.s f5, f10, f10 +fsgnjx.s f5, f10, f15 +fsgnjx.s f5, f10, f20 +fsgnjx.s f5, f10, f25 +fsgnjx.s f5, f10, f31 +fsgnjx.s f5, f15, f0 +fsgnjx.s f5, f15, f1 +fsgnjx.s f5, f15, f5 +fsgnjx.s f5, f15, f10 +fsgnjx.s f5, f15, f15 +fsgnjx.s f5, f15, f20 +fsgnjx.s f5, f15, f25 +fsgnjx.s f5, f15, f31 +fsgnjx.s f5, f20, f0 +fsgnjx.s f5, f20, f1 +fsgnjx.s f5, f20, f5 +fsgnjx.s f5, f20, f10 +fsgnjx.s f5, f20, f15 +fsgnjx.s f5, f20, f20 +fsgnjx.s f5, f20, f25 +fsgnjx.s f5, f20, f31 +fsgnjx.s f5, f25, f0 +fsgnjx.s f5, f25, f1 +fsgnjx.s f5, f25, f5 +fsgnjx.s f5, f25, f10 +fsgnjx.s f5, f25, f15 +fsgnjx.s f5, f25, f20 +fsgnjx.s f5, f25, f25 +fsgnjx.s f5, f25, f31 +fsgnjx.s f5, f31, f0 +fsgnjx.s f5, f31, f1 +fsgnjx.s f5, f31, f5 +fsgnjx.s f5, f31, f10 +fsgnjx.s f5, f31, f15 +fsgnjx.s f5, f31, f20 +fsgnjx.s f5, f31, f25 +fsgnjx.s f5, f31, f31 +fsgnjx.s f10, f0, f0 +fsgnjx.s f10, f0, f1 +fsgnjx.s f10, f0, f5 +fsgnjx.s f10, f0, f10 +fsgnjx.s f10, f0, f15 +fsgnjx.s f10, f0, f20 +fsgnjx.s f10, f0, f25 +fsgnjx.s f10, f0, f31 +fsgnjx.s f10, f1, f0 +fsgnjx.s f10, f1, f1 +fsgnjx.s f10, f1, f5 +fsgnjx.s f10, f1, f10 +fsgnjx.s f10, f1, f15 +fsgnjx.s f10, f1, f20 +fsgnjx.s f10, f1, f25 +fsgnjx.s f10, f1, f31 +fsgnjx.s f10, f5, f0 +fsgnjx.s f10, f5, f1 +fsgnjx.s f10, f5, f5 +fsgnjx.s f10, f5, f10 +fsgnjx.s f10, f5, f15 +fsgnjx.s f10, f5, f20 +fsgnjx.s f10, f5, f25 +fsgnjx.s f10, f5, f31 +fsgnjx.s f10, f10, f0 +fsgnjx.s f10, f10, f1 +fsgnjx.s f10, f10, f5 +fsgnjx.s f10, f10, f10 +fsgnjx.s f10, f10, f15 +fsgnjx.s f10, f10, f20 +fsgnjx.s f10, f10, f25 +fsgnjx.s f10, f10, f31 +fsgnjx.s f10, f15, f0 +fsgnjx.s f10, f15, f1 +fsgnjx.s f10, f15, f5 +fsgnjx.s f10, f15, f10 +fsgnjx.s f10, f15, f15 +fsgnjx.s f10, f15, f20 +fsgnjx.s f10, f15, f25 +fsgnjx.s f10, f15, f31 +fsgnjx.s f10, f20, f0 +fsgnjx.s f10, f20, f1 +fsgnjx.s f10, f20, f5 +fsgnjx.s f10, f20, f10 +fsgnjx.s f10, f20, f15 +fsgnjx.s f10, f20, f20 +fsgnjx.s f10, f20, f25 +fsgnjx.s f10, f20, f31 +fsgnjx.s f10, f25, f0 +fsgnjx.s f10, f25, f1 +fsgnjx.s f10, f25, f5 +fsgnjx.s f10, f25, f10 +fsgnjx.s f10, f25, f15 +fsgnjx.s f10, f25, f20 +fsgnjx.s f10, f25, f25 +fsgnjx.s f10, f25, f31 +fsgnjx.s f10, f31, f0 +fsgnjx.s f10, f31, f1 +fsgnjx.s f10, f31, f5 +fsgnjx.s f10, f31, f10 +fsgnjx.s f10, f31, f15 +fsgnjx.s f10, f31, f20 +fsgnjx.s f10, f31, f25 +fsgnjx.s f10, f31, f31 +fsgnjx.s f15, f0, f0 +fsgnjx.s f15, f0, f1 +fsgnjx.s f15, f0, f5 +fsgnjx.s f15, f0, f10 +fsgnjx.s f15, f0, f15 +fsgnjx.s f15, f0, f20 +fsgnjx.s f15, f0, f25 +fsgnjx.s f15, f0, f31 +fsgnjx.s f15, f1, f0 +fsgnjx.s f15, f1, f1 +fsgnjx.s f15, f1, f5 +fsgnjx.s f15, f1, f10 +fsgnjx.s f15, f1, f15 +fsgnjx.s f15, f1, f20 +fsgnjx.s f15, f1, f25 +fsgnjx.s f15, f1, f31 +fsgnjx.s f15, f5, f0 +fsgnjx.s f15, f5, f1 +fsgnjx.s f15, f5, f5 +fsgnjx.s f15, f5, f10 +fsgnjx.s f15, f5, f15 +fsgnjx.s f15, f5, f20 +fsgnjx.s f15, f5, f25 +fsgnjx.s f15, f5, f31 +fsgnjx.s f15, f10, f0 +fsgnjx.s f15, f10, f1 +fsgnjx.s f15, f10, f5 +fsgnjx.s f15, f10, f10 +fsgnjx.s f15, f10, f15 +fsgnjx.s f15, f10, f20 +fsgnjx.s f15, f10, f25 +fsgnjx.s f15, f10, f31 +fsgnjx.s f15, f15, f0 +fsgnjx.s f15, f15, f1 +fsgnjx.s f15, f15, f5 +fsgnjx.s f15, f15, f10 +fsgnjx.s f15, f15, f15 +fsgnjx.s f15, f15, f20 +fsgnjx.s f15, f15, f25 +fsgnjx.s f15, f15, f31 +fsgnjx.s f15, f20, f0 +fsgnjx.s f15, f20, f1 +fsgnjx.s f15, f20, f5 +fsgnjx.s f15, f20, f10 +fsgnjx.s f15, f20, f15 +fsgnjx.s f15, f20, f20 +fsgnjx.s f15, f20, f25 +fsgnjx.s f15, f20, f31 +fsgnjx.s f15, f25, f0 +fsgnjx.s f15, f25, f1 +fsgnjx.s f15, f25, f5 +fsgnjx.s f15, f25, f10 +fsgnjx.s f15, f25, f15 +fsgnjx.s f15, f25, f20 +fsgnjx.s f15, f25, f25 +fsgnjx.s f15, f25, f31 +fsgnjx.s f15, f31, f0 +fsgnjx.s f15, f31, f1 +fsgnjx.s f15, f31, f5 +fsgnjx.s f15, f31, f10 +fsgnjx.s f15, f31, f15 +fsgnjx.s f15, f31, f20 +fsgnjx.s f15, f31, f25 +fsgnjx.s f15, f31, f31 +fsgnjx.s f20, f0, f0 +fsgnjx.s f20, f0, f1 +fsgnjx.s f20, f0, f5 +fsgnjx.s f20, f0, f10 +fsgnjx.s f20, f0, f15 +fsgnjx.s f20, f0, f20 +fsgnjx.s f20, f0, f25 +fsgnjx.s f20, f0, f31 +fsgnjx.s f20, f1, f0 +fsgnjx.s f20, f1, f1 +fsgnjx.s f20, f1, f5 +fsgnjx.s f20, f1, f10 +fsgnjx.s f20, f1, f15 +fsgnjx.s f20, f1, f20 +fsgnjx.s f20, f1, f25 +fsgnjx.s f20, f1, f31 +fsgnjx.s f20, f5, f0 +fsgnjx.s f20, f5, f1 +fsgnjx.s f20, f5, f5 +fsgnjx.s f20, f5, f10 +fsgnjx.s f20, f5, f15 +fsgnjx.s f20, f5, f20 +fsgnjx.s f20, f5, f25 +fsgnjx.s f20, f5, f31 +fsgnjx.s f20, f10, f0 +fsgnjx.s f20, f10, f1 +fsgnjx.s f20, f10, f5 +fsgnjx.s f20, f10, f10 +fsgnjx.s f20, f10, f15 +fsgnjx.s f20, f10, f20 +fsgnjx.s f20, f10, f25 +fsgnjx.s f20, f10, f31 +fsgnjx.s f20, f15, f0 +fsgnjx.s f20, f15, f1 +fsgnjx.s f20, f15, f5 +fsgnjx.s f20, f15, f10 +fsgnjx.s f20, f15, f15 +fsgnjx.s f20, f15, f20 +fsgnjx.s f20, f15, f25 +fsgnjx.s f20, f15, f31 +fsgnjx.s f20, f20, f0 +fsgnjx.s f20, f20, f1 +fsgnjx.s f20, f20, f5 +fsgnjx.s f20, f20, f10 +fsgnjx.s f20, f20, f15 +fsgnjx.s f20, f20, f20 +fsgnjx.s f20, f20, f25 +fsgnjx.s f20, f20, f31 +fsgnjx.s f20, f25, f0 +fsgnjx.s f20, f25, f1 +fsgnjx.s f20, f25, f5 +fsgnjx.s f20, f25, f10 +fsgnjx.s f20, f25, f15 +fsgnjx.s f20, f25, f20 +fsgnjx.s f20, f25, f25 +fsgnjx.s f20, f25, f31 +fsgnjx.s f20, f31, f0 +fsgnjx.s f20, f31, f1 +fsgnjx.s f20, f31, f5 +fsgnjx.s f20, f31, f10 +fsgnjx.s f20, f31, f15 +fsgnjx.s f20, f31, f20 +fsgnjx.s f20, f31, f25 +fsgnjx.s f20, f31, f31 +fsgnjx.s f25, f0, f0 +fsgnjx.s f25, f0, f1 +fsgnjx.s f25, f0, f5 +fsgnjx.s f25, f0, f10 +fsgnjx.s f25, f0, f15 +fsgnjx.s f25, f0, f20 +fsgnjx.s f25, f0, f25 +fsgnjx.s f25, f0, f31 +fsgnjx.s f25, f1, f0 +fsgnjx.s f25, f1, f1 +fsgnjx.s f25, f1, f5 +fsgnjx.s f25, f1, f10 +fsgnjx.s f25, f1, f15 +fsgnjx.s f25, f1, f20 +fsgnjx.s f25, f1, f25 +fsgnjx.s f25, f1, f31 +fsgnjx.s f25, f5, f0 +fsgnjx.s f25, f5, f1 +fsgnjx.s f25, f5, f5 +fsgnjx.s f25, f5, f10 +fsgnjx.s f25, f5, f15 +fsgnjx.s f25, f5, f20 +fsgnjx.s f25, f5, f25 +fsgnjx.s f25, f5, f31 +fsgnjx.s f25, f10, f0 +fsgnjx.s f25, f10, f1 +fsgnjx.s f25, f10, f5 +fsgnjx.s f25, f10, f10 +fsgnjx.s f25, f10, f15 +fsgnjx.s f25, f10, f20 +fsgnjx.s f25, f10, f25 +fsgnjx.s f25, f10, f31 +fsgnjx.s f25, f15, f0 +fsgnjx.s f25, f15, f1 +fsgnjx.s f25, f15, f5 +fsgnjx.s f25, f15, f10 +fsgnjx.s f25, f15, f15 +fsgnjx.s f25, f15, f20 +fsgnjx.s f25, f15, f25 +fsgnjx.s f25, f15, f31 +fsgnjx.s f25, f20, f0 +fsgnjx.s f25, f20, f1 +fsgnjx.s f25, f20, f5 +fsgnjx.s f25, f20, f10 +fsgnjx.s f25, f20, f15 +fsgnjx.s f25, f20, f20 +fsgnjx.s f25, f20, f25 +fsgnjx.s f25, f20, f31 +fsgnjx.s f25, f25, f0 +fsgnjx.s f25, f25, f1 +fsgnjx.s f25, f25, f5 +fsgnjx.s f25, f25, f10 +fsgnjx.s f25, f25, f15 +fsgnjx.s f25, f25, f20 +fsgnjx.s f25, f25, f25 +fsgnjx.s f25, f25, f31 +fsgnjx.s f25, f31, f0 +fsgnjx.s f25, f31, f1 +fsgnjx.s f25, f31, f5 +fsgnjx.s f25, f31, f10 +fsgnjx.s f25, f31, f15 +fsgnjx.s f25, f31, f20 +fsgnjx.s f25, f31, f25 +fsgnjx.s f25, f31, f31 +fsgnjx.s f31, f0, f0 +fsgnjx.s f31, f0, f1 +fsgnjx.s f31, f0, f5 +fsgnjx.s f31, f0, f10 +fsgnjx.s f31, f0, f15 +fsgnjx.s f31, f0, f20 +fsgnjx.s f31, f0, f25 +fsgnjx.s f31, f0, f31 +fsgnjx.s f31, f1, f0 +fsgnjx.s f31, f1, f1 +fsgnjx.s f31, f1, f5 +fsgnjx.s f31, f1, f10 +fsgnjx.s f31, f1, f15 +fsgnjx.s f31, f1, f20 +fsgnjx.s f31, f1, f25 +fsgnjx.s f31, f1, f31 +fsgnjx.s f31, f5, f0 +fsgnjx.s f31, f5, f1 +fsgnjx.s f31, f5, f5 +fsgnjx.s f31, f5, f10 +fsgnjx.s f31, f5, f15 +fsgnjx.s f31, f5, f20 +fsgnjx.s f31, f5, f25 +fsgnjx.s f31, f5, f31 +fsgnjx.s f31, f10, f0 +fsgnjx.s f31, f10, f1 +fsgnjx.s f31, f10, f5 +fsgnjx.s f31, f10, f10 +fsgnjx.s f31, f10, f15 +fsgnjx.s f31, f10, f20 +fsgnjx.s f31, f10, f25 +fsgnjx.s f31, f10, f31 +fsgnjx.s f31, f15, f0 +fsgnjx.s f31, f15, f1 +fsgnjx.s f31, f15, f5 +fsgnjx.s f31, f15, f10 +fsgnjx.s f31, f15, f15 +fsgnjx.s f31, f15, f20 +fsgnjx.s f31, f15, f25 +fsgnjx.s f31, f15, f31 +fsgnjx.s f31, f20, f0 +fsgnjx.s f31, f20, f1 +fsgnjx.s f31, f20, f5 +fsgnjx.s f31, f20, f10 +fsgnjx.s f31, f20, f15 +fsgnjx.s f31, f20, f20 +fsgnjx.s f31, f20, f25 +fsgnjx.s f31, f20, f31 +fsgnjx.s f31, f25, f0 +fsgnjx.s f31, f25, f1 +fsgnjx.s f31, f25, f5 +fsgnjx.s f31, f25, f10 +fsgnjx.s f31, f25, f15 +fsgnjx.s f31, f25, f20 +fsgnjx.s f31, f25, f25 +fsgnjx.s f31, f25, f31 +fsgnjx.s f31, f31, f0 +fsgnjx.s f31, f31, f1 +fsgnjx.s f31, f31, f5 +fsgnjx.s f31, f31, f10 +fsgnjx.s f31, f31, f15 +fsgnjx.s f31, f31, f20 +fsgnjx.s f31, f31, f25 +fsgnjx.s f31, f31, f31 + diff --git a/tests/riscv/f-extension/fsgnjx.s.bin b/tests/riscv/f-extension/fsgnjx.s.bin new file mode 100644 index 0000000000000000000000000000000000000000..3d5c757d934aaa3711b568cef41cce32f38bff38 GIT binary patch literal 2048 zcmWmC@urna9LDh@5{ZsTB-(2j!)usZI3khgXh|fxr6UrFmSGHIn2ULDB%5usZT9)B zKOWZlJ>%u;`y4O+x;S3^E&s|%{>VRv@$dNkKJ55+{5$>~|Biph zzvK5??)m>jK1h{IdFB31E`8&^?>&`|(&S2ByMLD}ZytF6Og>4MYkA}TL$1Af=>2o~ zEJJSOt@}^8@#c~DFXW3%xs`YBzvNaP`~OnD%91;I@BUlx2Ydlvz!&fZd;wp;7w}bm z)mMGhSAEr2eLeU1EB=bV;;;BC{))fi5BLNAfIr|5_yhicKj5$UEB=bV;;;BC{))fi z5BLNAfIr|5_yhicKj5$UEB=bV;;;BC{))fiulOteiofEo_$&U3zup~=(Y~X7NBfTU z9ql{XceL+l-%a22P2coQ-}Fu2&b|FN`)~H&?7!K6v;SuQ&HkhPNBfWVAMHQdf3*K- z|Iz-N{Wtq>_TTKk*?+VDX8+Cpqy0zwkM z^WXXJ{CEC4|B3&^f8sy!pZHJwC;k)vo&U~%=fCsc`S1L9{yYDP|HOadKk=XVPy8qT z6aSt6&VT2>^WXXJ{CEC4|DFHNf9JpR-}&$Scm6y78^0UB8^0UB8^0UB8^0UBLqGIG zKlDRC^g}<+J^zFM!T;cY@IUw;{15&&{x|+N{x|+N{x|+N{x|*y|AYU*|KNY{KlmT~ z5B@j)H~u&NH~u&NH~u&NH~t6zga5(*;D7Kx_#gZa{s;eq|H1#@fABx}AN&vgGryVN z%x~s5^PBn2{APZqe(I-w>Zg9{r+%J${wM#F|H=R4fAT;1pZsV3Gyj?Y%zx%T^Pl<8 z{7?QT|C9g8|Kxx2Klz{hXZ|z)ng7gx=0EeF`Oo}M{wM#F|H=R4fAT;1pZrh$C;yZG z$^Ybk@;~{X_zS**uiz{A3ciA`;4Ao+e(9Hf>6d=#mwugl{0slWzwj^o3;)8u@E80A zf5Bhy7yJc(!C&w%{0slWzwj^o3;)8u@E80Af5Bhy7yJc(!C&w%{0slWzwj^o3;)8u V@Gtxe|H8lUFZ>Jt!oThg{{xEkY;FJm literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fsgnjx.s.disasm b/tests/riscv/f-extension/fsgnjx.s.disasm new file mode 100644 index 0000000..c405223 --- /dev/null +++ b/tests/riscv/f-extension/fsgnjx.s.disasm @@ -0,0 +1,512 @@ +fsgnjx.s f0, f0, f0 +fsgnjx.s f0, f0, f1 +fsgnjx.s f0, f0, f5 +fsgnjx.s f0, f0, f10 +fsgnjx.s f0, f0, f15 +fsgnjx.s f0, f0, f20 +fsgnjx.s f0, f0, f25 +fsgnjx.s f0, f0, f31 +fsgnjx.s f0, f1, f0 +fsgnjx.s f0, f1, f1 +fsgnjx.s f0, f1, f5 +fsgnjx.s f0, f1, f10 +fsgnjx.s f0, f1, f15 +fsgnjx.s f0, f1, f20 +fsgnjx.s f0, f1, f25 +fsgnjx.s f0, f1, f31 +fsgnjx.s f0, f5, f0 +fsgnjx.s f0, f5, f1 +fsgnjx.s f0, f5, f5 +fsgnjx.s f0, f5, f10 +fsgnjx.s f0, f5, f15 +fsgnjx.s f0, f5, f20 +fsgnjx.s f0, f5, f25 +fsgnjx.s f0, f5, f31 +fsgnjx.s f0, f10, f0 +fsgnjx.s f0, f10, f1 +fsgnjx.s f0, f10, f5 +fsgnjx.s f0, f10, f10 +fsgnjx.s f0, f10, f15 +fsgnjx.s f0, f10, f20 +fsgnjx.s f0, f10, f25 +fsgnjx.s f0, f10, f31 +fsgnjx.s f0, f15, f0 +fsgnjx.s f0, f15, f1 +fsgnjx.s f0, f15, f5 +fsgnjx.s f0, f15, f10 +fsgnjx.s f0, f15, f15 +fsgnjx.s f0, f15, f20 +fsgnjx.s f0, f15, f25 +fsgnjx.s f0, f15, f31 +fsgnjx.s f0, f20, f0 +fsgnjx.s f0, f20, f1 +fsgnjx.s f0, f20, f5 +fsgnjx.s f0, f20, f10 +fsgnjx.s f0, f20, f15 +fsgnjx.s f0, f20, f20 +fsgnjx.s f0, f20, f25 +fsgnjx.s f0, f20, f31 +fsgnjx.s f0, f25, f0 +fsgnjx.s f0, f25, f1 +fsgnjx.s f0, f25, f5 +fsgnjx.s f0, f25, f10 +fsgnjx.s f0, f25, f15 +fsgnjx.s f0, f25, f20 +fsgnjx.s f0, f25, f25 +fsgnjx.s f0, f25, f31 +fsgnjx.s f0, f31, f0 +fsgnjx.s f0, f31, f1 +fsgnjx.s f0, f31, f5 +fsgnjx.s f0, f31, f10 +fsgnjx.s f0, f31, f15 +fsgnjx.s f0, f31, f20 +fsgnjx.s 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f0 +fsgnjx.s f5, f10, f1 +fsgnjx.s f5, f10, f5 +fsgnjx.s f5, f10, f10 +fsgnjx.s f5, f10, f15 +fsgnjx.s f5, f10, f20 +fsgnjx.s f5, f10, f25 +fsgnjx.s f5, f10, f31 +fsgnjx.s f5, f15, f0 +fsgnjx.s f5, f15, f1 +fsgnjx.s f5, f15, f5 +fsgnjx.s f5, f15, f10 +fsgnjx.s f5, f15, f15 +fsgnjx.s f5, f15, f20 +fsgnjx.s f5, f15, f25 +fsgnjx.s f5, f15, f31 +fsgnjx.s f5, f20, f0 +fsgnjx.s f5, f20, f1 +fsgnjx.s f5, f20, f5 +fsgnjx.s f5, f20, f10 +fsgnjx.s f5, f20, f15 +fsgnjx.s f5, f20, f20 +fsgnjx.s f5, f20, f25 +fsgnjx.s f5, f20, f31 +fsgnjx.s f5, f25, f0 +fsgnjx.s f5, f25, f1 +fsgnjx.s f5, f25, f5 +fsgnjx.s f5, f25, f10 +fsgnjx.s f5, f25, f15 +fsgnjx.s f5, f25, f20 +fsgnjx.s f5, f25, f25 +fsgnjx.s f5, f25, f31 +fsgnjx.s f5, f31, f0 +fsgnjx.s f5, f31, f1 +fsgnjx.s f5, f31, f5 +fsgnjx.s f5, f31, f10 +fsgnjx.s f5, f31, f15 +fsgnjx.s f5, f31, f20 +fsgnjx.s f5, f31, f25 +fsgnjx.s f5, f31, f31 +fsgnjx.s f10, f0, f0 +fsgnjx.s f10, f0, f1 +fsgnjx.s f10, f0, f5 +fsgnjx.s f10, f0, f10 +fsgnjx.s f10, f0, f15 +fsgnjx.s f10, f0, f20 +fsgnjx.s f10, f0, f25 +fsgnjx.s f10, f0, f31 +fsgnjx.s f10, f1, f0 +fsgnjx.s f10, f1, f1 +fsgnjx.s f10, f1, f5 +fsgnjx.s f10, f1, f10 +fsgnjx.s f10, f1, f15 +fsgnjx.s f10, f1, f20 +fsgnjx.s f10, f1, f25 +fsgnjx.s f10, f1, f31 +fsgnjx.s f10, f5, f0 +fsgnjx.s f10, f5, f1 +fsgnjx.s f10, f5, f5 +fsgnjx.s f10, f5, f10 +fsgnjx.s f10, f5, f15 +fsgnjx.s f10, f5, f20 +fsgnjx.s f10, f5, f25 +fsgnjx.s f10, f5, f31 +fsgnjx.s f10, f10, f0 +fsgnjx.s f10, f10, f1 +fsgnjx.s f10, f10, f5 +fsgnjx.s f10, f10, f10 +fsgnjx.s f10, f10, f15 +fsgnjx.s f10, f10, f20 +fsgnjx.s f10, f10, f25 +fsgnjx.s f10, f10, f31 +fsgnjx.s f10, f15, f0 +fsgnjx.s f10, f15, f1 +fsgnjx.s f10, f15, f5 +fsgnjx.s f10, f15, f10 +fsgnjx.s f10, f15, f15 +fsgnjx.s f10, f15, f20 +fsgnjx.s f10, f15, f25 +fsgnjx.s f10, f15, f31 +fsgnjx.s f10, f20, f0 +fsgnjx.s f10, f20, f1 +fsgnjx.s f10, f20, f5 +fsgnjx.s f10, f20, f10 +fsgnjx.s f10, f20, f15 +fsgnjx.s f10, f20, f20 +fsgnjx.s f10, f20, f25 +fsgnjx.s f10, f20, f31 +fsgnjx.s f10, f25, f0 +fsgnjx.s f10, f25, f1 +fsgnjx.s f10, f25, f5 +fsgnjx.s f10, f25, f10 +fsgnjx.s f10, f25, f15 +fsgnjx.s f10, f25, f20 +fsgnjx.s f10, f25, f25 +fsgnjx.s f10, f25, f31 +fsgnjx.s f10, f31, f0 +fsgnjx.s f10, f31, f1 +fsgnjx.s f10, f31, f5 +fsgnjx.s f10, f31, f10 +fsgnjx.s f10, f31, f15 +fsgnjx.s f10, f31, f20 +fsgnjx.s f10, f31, f25 +fsgnjx.s f10, f31, f31 +fsgnjx.s f15, f0, f0 +fsgnjx.s f15, f0, f1 +fsgnjx.s f15, f0, f5 +fsgnjx.s f15, f0, f10 +fsgnjx.s f15, f0, f15 +fsgnjx.s f15, f0, f20 +fsgnjx.s f15, f0, f25 +fsgnjx.s f15, f0, f31 +fsgnjx.s f15, f1, f0 +fsgnjx.s f15, f1, f1 +fsgnjx.s f15, f1, f5 +fsgnjx.s f15, f1, f10 +fsgnjx.s f15, f1, f15 +fsgnjx.s f15, f1, f20 +fsgnjx.s f15, f1, f25 +fsgnjx.s f15, f1, f31 +fsgnjx.s f15, f5, f0 +fsgnjx.s f15, f5, f1 +fsgnjx.s f15, f5, f5 +fsgnjx.s f15, f5, f10 +fsgnjx.s f15, f5, f15 +fsgnjx.s f15, f5, f20 +fsgnjx.s f15, f5, f25 +fsgnjx.s f15, f5, f31 +fsgnjx.s f15, f10, f0 +fsgnjx.s f15, f10, f1 +fsgnjx.s f15, f10, f5 +fsgnjx.s f15, f10, f10 +fsgnjx.s f15, f10, f15 +fsgnjx.s f15, f10, f20 +fsgnjx.s f15, f10, f25 +fsgnjx.s f15, f10, f31 +fsgnjx.s f15, f15, f0 +fsgnjx.s f15, f15, f1 +fsgnjx.s f15, f15, f5 +fsgnjx.s f15, f15, f10 +fsgnjx.s f15, f15, f15 +fsgnjx.s f15, f15, f20 +fsgnjx.s f15, f15, f25 +fsgnjx.s f15, f15, f31 +fsgnjx.s f15, f20, f0 +fsgnjx.s f15, f20, f1 +fsgnjx.s f15, f20, f5 +fsgnjx.s f15, f20, f10 +fsgnjx.s f15, f20, f15 +fsgnjx.s f15, f20, f20 +fsgnjx.s f15, f20, f25 +fsgnjx.s f15, f20, f31 +fsgnjx.s f15, f25, f0 +fsgnjx.s f15, f25, f1 +fsgnjx.s f15, f25, f5 +fsgnjx.s f15, f25, f10 +fsgnjx.s f15, f25, f15 +fsgnjx.s f15, f25, f20 +fsgnjx.s f15, f25, f25 +fsgnjx.s f15, f25, f31 +fsgnjx.s f15, f31, f0 +fsgnjx.s f15, f31, f1 +fsgnjx.s f15, f31, f5 +fsgnjx.s f15, f31, f10 +fsgnjx.s f15, f31, f15 +fsgnjx.s f15, f31, f20 +fsgnjx.s f15, f31, f25 +fsgnjx.s f15, f31, f31 +fsgnjx.s f20, f0, f0 +fsgnjx.s f20, f0, f1 +fsgnjx.s f20, f0, f5 +fsgnjx.s f20, f0, f10 +fsgnjx.s f20, f0, f15 +fsgnjx.s f20, f0, f20 +fsgnjx.s f20, f0, f25 +fsgnjx.s f20, f0, f31 +fsgnjx.s f20, f1, f0 +fsgnjx.s f20, f1, f1 +fsgnjx.s f20, f1, f5 +fsgnjx.s f20, f1, f10 +fsgnjx.s f20, f1, f15 +fsgnjx.s f20, f1, f20 +fsgnjx.s f20, f1, f25 +fsgnjx.s f20, f1, f31 +fsgnjx.s f20, f5, f0 +fsgnjx.s f20, f5, f1 +fsgnjx.s f20, f5, f5 +fsgnjx.s f20, f5, f10 +fsgnjx.s f20, f5, f15 +fsgnjx.s f20, f5, f20 +fsgnjx.s f20, f5, f25 +fsgnjx.s f20, f5, f31 +fsgnjx.s f20, f10, f0 +fsgnjx.s f20, f10, f1 +fsgnjx.s f20, f10, f5 +fsgnjx.s f20, f10, f10 +fsgnjx.s f20, f10, f15 +fsgnjx.s f20, f10, f20 +fsgnjx.s f20, f10, f25 +fsgnjx.s f20, f10, f31 +fsgnjx.s f20, f15, f0 +fsgnjx.s f20, f15, f1 +fsgnjx.s f20, f15, f5 +fsgnjx.s f20, f15, f10 +fsgnjx.s f20, f15, f15 +fsgnjx.s f20, f15, f20 +fsgnjx.s f20, f15, f25 +fsgnjx.s f20, f15, f31 +fsgnjx.s f20, f20, f0 +fsgnjx.s f20, f20, f1 +fsgnjx.s f20, f20, f5 +fsgnjx.s f20, f20, f10 +fsgnjx.s f20, f20, f15 +fsgnjx.s f20, f20, f20 +fsgnjx.s f20, f20, f25 +fsgnjx.s f20, f20, f31 +fsgnjx.s f20, f25, f0 +fsgnjx.s f20, f25, f1 +fsgnjx.s f20, f25, f5 +fsgnjx.s f20, f25, f10 +fsgnjx.s f20, f25, f15 +fsgnjx.s f20, f25, f20 +fsgnjx.s f20, f25, f25 +fsgnjx.s f20, f25, f31 +fsgnjx.s f20, f31, f0 +fsgnjx.s f20, f31, f1 +fsgnjx.s f20, f31, f5 +fsgnjx.s f20, f31, f10 +fsgnjx.s f20, f31, f15 +fsgnjx.s f20, f31, f20 +fsgnjx.s f20, f31, f25 +fsgnjx.s f20, f31, f31 +fsgnjx.s f25, f0, f0 +fsgnjx.s f25, f0, f1 +fsgnjx.s f25, f0, f5 +fsgnjx.s f25, f0, f10 +fsgnjx.s f25, f0, f15 +fsgnjx.s f25, f0, f20 +fsgnjx.s f25, f0, f25 +fsgnjx.s f25, f0, f31 +fsgnjx.s f25, f1, f0 +fsgnjx.s f25, f1, f1 +fsgnjx.s f25, f1, f5 +fsgnjx.s f25, f1, f10 +fsgnjx.s f25, f1, f15 +fsgnjx.s f25, f1, f20 +fsgnjx.s f25, f1, f25 +fsgnjx.s f25, f1, f31 +fsgnjx.s f25, f5, f0 +fsgnjx.s f25, f5, f1 +fsgnjx.s f25, f5, f5 +fsgnjx.s f25, f5, f10 +fsgnjx.s f25, f5, f15 +fsgnjx.s f25, f5, f20 +fsgnjx.s f25, f5, f25 +fsgnjx.s f25, f5, f31 +fsgnjx.s f25, f10, f0 +fsgnjx.s f25, f10, f1 +fsgnjx.s f25, f10, f5 +fsgnjx.s f25, f10, f10 +fsgnjx.s f25, f10, f15 +fsgnjx.s f25, f10, f20 +fsgnjx.s f25, f10, f25 +fsgnjx.s f25, f10, f31 +fsgnjx.s f25, f15, f0 +fsgnjx.s f25, f15, f1 +fsgnjx.s f25, f15, f5 +fsgnjx.s f25, f15, f10 +fsgnjx.s f25, f15, f15 +fsgnjx.s f25, f15, f20 +fsgnjx.s f25, f15, f25 +fsgnjx.s f25, f15, f31 +fsgnjx.s f25, f20, f0 +fsgnjx.s f25, f20, f1 +fsgnjx.s f25, f20, f5 +fsgnjx.s f25, f20, f10 +fsgnjx.s f25, f20, f15 +fsgnjx.s f25, f20, f20 +fsgnjx.s f25, f20, f25 +fsgnjx.s f25, f20, f31 +fsgnjx.s f25, f25, f0 +fsgnjx.s f25, f25, f1 +fsgnjx.s f25, f25, f5 +fsgnjx.s f25, f25, f10 +fsgnjx.s f25, f25, f15 +fsgnjx.s f25, f25, f20 +fsgnjx.s f25, f25, f25 +fsgnjx.s f25, f25, f31 +fsgnjx.s f25, f31, f0 +fsgnjx.s f25, f31, f1 +fsgnjx.s f25, f31, f5 +fsgnjx.s f25, f31, f10 +fsgnjx.s f25, f31, f15 +fsgnjx.s f25, f31, f20 +fsgnjx.s f25, f31, f25 +fsgnjx.s f25, f31, f31 +fsgnjx.s f31, f0, f0 +fsgnjx.s f31, f0, f1 +fsgnjx.s f31, f0, f5 +fsgnjx.s f31, f0, f10 +fsgnjx.s f31, f0, f15 +fsgnjx.s f31, f0, f20 +fsgnjx.s f31, f0, f25 +fsgnjx.s f31, f0, f31 +fsgnjx.s f31, f1, f0 +fsgnjx.s f31, f1, f1 +fsgnjx.s f31, f1, f5 +fsgnjx.s f31, f1, f10 +fsgnjx.s f31, f1, f15 +fsgnjx.s f31, f1, f20 +fsgnjx.s f31, f1, f25 +fsgnjx.s f31, f1, f31 +fsgnjx.s f31, f5, f0 +fsgnjx.s f31, f5, f1 +fsgnjx.s f31, f5, f5 +fsgnjx.s f31, f5, f10 +fsgnjx.s f31, f5, f15 +fsgnjx.s f31, f5, f20 +fsgnjx.s f31, f5, f25 +fsgnjx.s f31, f5, f31 +fsgnjx.s f31, f10, f0 +fsgnjx.s f31, f10, f1 +fsgnjx.s f31, f10, f5 +fsgnjx.s f31, f10, f10 +fsgnjx.s f31, f10, f15 +fsgnjx.s f31, f10, f20 +fsgnjx.s f31, f10, f25 +fsgnjx.s f31, f10, f31 +fsgnjx.s f31, f15, f0 +fsgnjx.s f31, f15, f1 +fsgnjx.s f31, f15, f5 +fsgnjx.s f31, f15, f10 +fsgnjx.s f31, f15, f15 +fsgnjx.s f31, f15, f20 +fsgnjx.s f31, f15, f25 +fsgnjx.s f31, f15, f31 +fsgnjx.s f31, f20, f0 +fsgnjx.s f31, f20, f1 +fsgnjx.s f31, f20, f5 +fsgnjx.s f31, f20, f10 +fsgnjx.s f31, f20, f15 +fsgnjx.s f31, f20, f20 +fsgnjx.s f31, f20, f25 +fsgnjx.s f31, f20, f31 +fsgnjx.s f31, f25, f0 +fsgnjx.s f31, f25, f1 +fsgnjx.s f31, f25, f5 +fsgnjx.s f31, f25, f10 +fsgnjx.s f31, f25, f15 +fsgnjx.s f31, f25, f20 +fsgnjx.s f31, f25, f25 +fsgnjx.s f31, f25, f31 +fsgnjx.s f31, f31, f0 +fsgnjx.s f31, f31, f1 +fsgnjx.s f31, f31, f5 +fsgnjx.s f31, f31, f10 +fsgnjx.s f31, f31, f15 +fsgnjx.s f31, f31, f20 +fsgnjx.s f31, f31, f25 +fsgnjx.s f31, f31, f31 diff --git a/tests/riscv/f-extension/fsgnjx_s.asm b/tests/riscv/f-extension/fsgnjx_s.asm new file mode 100644 index 0000000..fe6faae --- /dev/null +++ b/tests/riscv/f-extension/fsgnjx_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fsgnjx.s f0, f1, f2 + diff --git a/tests/riscv/f-extension/fsgnjx_s.bin b/tests/riscv/f-extension/fsgnjx_s.bin new file mode 100644 index 0000000..e3e93f3 --- /dev/null +++ b/tests/riscv/f-extension/fsgnjx_s.bin @@ -0,0 +1 @@ +S \ No newline at end of file diff --git a/tests/riscv/f-extension/fsgnjx_s.disasm b/tests/riscv/f-extension/fsgnjx_s.disasm new file mode 100644 index 0000000..7ec0801 --- /dev/null +++ b/tests/riscv/f-extension/fsgnjx_s.disasm @@ -0,0 +1 @@ +fsgnjx.s f0, f1, f2 diff --git a/tests/riscv/f-extension/fsqrt.s.asm b/tests/riscv/f-extension/fsqrt.s.asm new file mode 100644 index 0000000..cd37c44 --- /dev/null +++ b/tests/riscv/f-extension/fsqrt.s.asm @@ -0,0 +1,65 @@ +.lang riscv32 +.org 0x0 + +; FSQRT.S - Floating-point square root (single precision) +; Format: fsqrt.s rd, rs1 +; Computes sqrt(rs1) and stores result in rd + +; Same register (rd == rs1) +fsqrt.s f0, f0 +fsqrt.s f1, f1 +fsqrt.s f5, f5 +fsqrt.s f10, f10 +fsqrt.s f15, f15 +fsqrt.s f20, f20 +fsqrt.s f25, f25 +fsqrt.s f31, f31 + +; Different registers - various rd values with f0 as source +fsqrt.s f1, f0 +fsqrt.s f5, f0 +fsqrt.s f10, f0 +fsqrt.s f15, f0 +fsqrt.s f20, f0 +fsqrt.s f25, f0 +fsqrt.s f31, f0 + +; Different registers - various rd values with f1 as source +fsqrt.s f0, f1 +fsqrt.s f5, f1 +fsqrt.s f10, f1 +fsqrt.s f15, f1 +fsqrt.s f20, f1 +fsqrt.s f25, f1 +fsqrt.s f31, f1 + +; Different registers - various rd values with f10 as source +fsqrt.s f0, f10 +fsqrt.s f1, f10 +fsqrt.s f5, f10 +fsqrt.s f15, f10 +fsqrt.s f20, f10 +fsqrt.s f25, f10 +fsqrt.s f31, f10 + +; Different registers - various rd values with f31 as source +fsqrt.s f0, f31 +fsqrt.s f1, f31 +fsqrt.s f5, f31 +fsqrt.s f10, f31 +fsqrt.s f15, f31 +fsqrt.s f20, f31 +fsqrt.s f25, f31 + +; Edge cases - adjacent registers +fsqrt.s f0, f1 +fsqrt.s f1, f2 +fsqrt.s f2, f3 +fsqrt.s f30, f31 + +; Mixed register combinations +fsqrt.s f2, f29 +fsqrt.s f3, f28 +fsqrt.s f4, f27 +fsqrt.s f12, f19 +fsqrt.s f16, f8 diff --git a/tests/riscv/f-extension/fsqrt.s.bin b/tests/riscv/f-extension/fsqrt.s.bin new file mode 100644 index 0000000000000000000000000000000000000000..6be42c25b1932e8b7bb614748bb59b9a85f136cc GIT binary patch literal 180 zcmW-aQ3}H#5JZhsY{kaI?av%15n3S#Iow{T&wf1K$TFjaAU~i-SxWMeWu?exmETRi z?lEw~85dlkk^epX;XUw$C*0(~)*?bq^l*hnKGov2f6YldH+D($alGxXYL>6+MDeCLwPGdqy0zwkM-LncvKB<~Q@3`OW-helx#Q zKlM{T^;19fQ$J5V|C9g8|Kxx2Klz{hPyRFing7gx=0EeF`Oo}k{wM#F|H=R4fAT;1 zpZrh$Gyj?Y%zx%T^Pl<8{Ad0r|C9g8|Kxx2Klz{hPyQ$WlmE&86d<;dj1#xi~q&{;(zhK_+R`N{tN$w|H6Oazwlr9 zFZ?h57ypa@#sA`e@xS>$iTNdi)#z#=r4z{2TwqzwuZ6 z6@SHF@mKs6f5l(%Z~Pno#=r4z{2TwqzwuZ66@SHF@mKs6f5l(%Z~Pno#=r4z{2Twq WzwvMU8~?_?@o)Sa|Hi-X&i@BswftWI literal 0 HcmV?d00001 diff --git a/tests/riscv/f-extension/fsub.s.disasm b/tests/riscv/f-extension/fsub.s.disasm new file mode 100644 index 0000000..79cc8ad --- /dev/null +++ b/tests/riscv/f-extension/fsub.s.disasm @@ -0,0 +1,512 @@ +fsub.s f0, f0, f0 +fsub.s f0, f0, f1 +fsub.s f0, f0, f5 +fsub.s f0, f0, f10 +fsub.s f0, f0, f15 +fsub.s f0, f0, f20 +fsub.s f0, f0, f25 +fsub.s f0, f0, f31 +fsub.s f0, f1, f0 +fsub.s f0, f1, f1 +fsub.s f0, f1, f5 +fsub.s f0, f1, f10 +fsub.s f0, f1, f15 +fsub.s f0, f1, f20 +fsub.s f0, f1, f25 +fsub.s f0, f1, f31 +fsub.s f0, f5, f0 +fsub.s f0, f5, f1 +fsub.s f0, f5, f5 +fsub.s f0, f5, f10 +fsub.s f0, f5, f15 +fsub.s f0, f5, f20 +fsub.s f0, f5, f25 +fsub.s f0, f5, f31 +fsub.s f0, f10, f0 +fsub.s f0, f10, f1 +fsub.s f0, f10, f5 +fsub.s f0, f10, f10 +fsub.s f0, f10, f15 +fsub.s f0, f10, f20 +fsub.s f0, f10, f25 +fsub.s f0, f10, f31 +fsub.s f0, f15, f0 +fsub.s f0, f15, f1 +fsub.s f0, f15, f5 +fsub.s f0, f15, f10 +fsub.s f0, f15, f15 +fsub.s f0, f15, f20 +fsub.s f0, f15, f25 +fsub.s f0, f15, f31 +fsub.s f0, f20, f0 +fsub.s f0, f20, f1 +fsub.s f0, f20, f5 +fsub.s f0, f20, f10 +fsub.s f0, f20, f15 +fsub.s f0, f20, f20 +fsub.s f0, f20, f25 +fsub.s f0, f20, f31 +fsub.s f0, f25, f0 +fsub.s f0, f25, f1 +fsub.s f0, f25, f5 +fsub.s f0, f25, f10 +fsub.s f0, f25, f15 +fsub.s f0, f25, f20 +fsub.s f0, f25, f25 +fsub.s f0, f25, f31 +fsub.s f0, f31, f0 +fsub.s f0, f31, f1 +fsub.s f0, f31, f5 +fsub.s f0, f31, f10 +fsub.s f0, f31, f15 +fsub.s f0, f31, f20 +fsub.s f0, f31, f25 +fsub.s f0, f31, f31 +fsub.s f1, f0, f0 +fsub.s f1, f0, f1 +fsub.s f1, f0, f5 +fsub.s f1, f0, f10 +fsub.s f1, f0, f15 +fsub.s f1, f0, f20 +fsub.s f1, f0, f25 +fsub.s f1, f0, f31 +fsub.s f1, f1, f0 +fsub.s f1, f1, f1 +fsub.s f1, f1, f5 +fsub.s f1, f1, f10 +fsub.s f1, f1, f15 +fsub.s f1, f1, f20 +fsub.s f1, f1, f25 +fsub.s f1, f1, f31 +fsub.s f1, f5, f0 +fsub.s f1, f5, f1 +fsub.s f1, f5, f5 +fsub.s f1, f5, f10 +fsub.s f1, f5, f15 +fsub.s f1, f5, f20 +fsub.s f1, f5, f25 +fsub.s f1, f5, f31 +fsub.s f1, f10, f0 +fsub.s f1, f10, f1 +fsub.s f1, f10, f5 +fsub.s f1, f10, f10 +fsub.s f1, f10, f15 +fsub.s f1, f10, f20 +fsub.s f1, f10, f25 +fsub.s f1, f10, f31 +fsub.s f1, f15, f0 +fsub.s f1, f15, f1 +fsub.s f1, f15, f5 +fsub.s f1, f15, f10 +fsub.s f1, f15, f15 +fsub.s f1, f15, f20 +fsub.s f1, f15, f25 +fsub.s f1, f15, f31 +fsub.s f1, f20, f0 +fsub.s f1, f20, f1 +fsub.s f1, f20, f5 +fsub.s f1, f20, f10 +fsub.s f1, f20, f15 +fsub.s f1, f20, f20 +fsub.s f1, f20, f25 +fsub.s f1, f20, f31 +fsub.s f1, f25, f0 +fsub.s f1, f25, f1 +fsub.s f1, f25, f5 +fsub.s f1, f25, f10 +fsub.s f1, f25, f15 +fsub.s f1, f25, f20 +fsub.s f1, f25, f25 +fsub.s f1, f25, f31 +fsub.s f1, f31, f0 +fsub.s f1, f31, f1 +fsub.s f1, f31, f5 +fsub.s f1, f31, f10 +fsub.s f1, f31, f15 +fsub.s f1, f31, f20 +fsub.s f1, f31, f25 +fsub.s f1, f31, f31 +fsub.s f5, f0, f0 +fsub.s f5, f0, f1 +fsub.s f5, f0, f5 +fsub.s f5, f0, f10 +fsub.s f5, f0, f15 +fsub.s f5, f0, f20 +fsub.s f5, f0, f25 +fsub.s f5, f0, f31 +fsub.s f5, f1, f0 +fsub.s f5, f1, f1 +fsub.s f5, f1, f5 +fsub.s f5, f1, f10 +fsub.s f5, f1, f15 +fsub.s f5, f1, f20 +fsub.s f5, f1, f25 +fsub.s f5, f1, f31 +fsub.s f5, f5, f0 +fsub.s f5, f5, f1 +fsub.s f5, f5, f5 +fsub.s f5, f5, f10 +fsub.s f5, f5, f15 +fsub.s f5, f5, f20 +fsub.s f5, f5, f25 +fsub.s f5, f5, f31 +fsub.s f5, f10, f0 +fsub.s f5, f10, f1 +fsub.s f5, f10, f5 +fsub.s f5, f10, f10 +fsub.s f5, f10, f15 +fsub.s f5, f10, f20 +fsub.s f5, f10, f25 +fsub.s f5, f10, f31 +fsub.s f5, f15, f0 +fsub.s f5, f15, f1 +fsub.s f5, f15, f5 +fsub.s f5, f15, f10 +fsub.s f5, f15, f15 +fsub.s f5, f15, f20 +fsub.s f5, f15, f25 +fsub.s f5, f15, f31 +fsub.s f5, f20, f0 +fsub.s f5, f20, f1 +fsub.s f5, f20, f5 +fsub.s f5, f20, f10 +fsub.s f5, f20, f15 +fsub.s f5, f20, f20 +fsub.s f5, f20, f25 +fsub.s f5, f20, f31 +fsub.s f5, f25, f0 +fsub.s f5, f25, f1 +fsub.s f5, f25, f5 +fsub.s f5, f25, f10 +fsub.s f5, f25, f15 +fsub.s f5, f25, f20 +fsub.s f5, f25, f25 +fsub.s f5, f25, f31 +fsub.s f5, f31, f0 +fsub.s f5, f31, f1 +fsub.s f5, f31, f5 +fsub.s f5, f31, f10 +fsub.s f5, f31, f15 +fsub.s f5, f31, f20 +fsub.s f5, f31, f25 +fsub.s f5, f31, f31 +fsub.s f10, f0, f0 +fsub.s f10, f0, f1 +fsub.s f10, f0, f5 +fsub.s f10, f0, f10 +fsub.s f10, f0, f15 +fsub.s f10, f0, f20 +fsub.s f10, f0, f25 +fsub.s f10, f0, f31 +fsub.s f10, f1, f0 +fsub.s f10, f1, f1 +fsub.s f10, f1, f5 +fsub.s f10, f1, f10 +fsub.s f10, f1, f15 +fsub.s f10, f1, f20 +fsub.s f10, f1, f25 +fsub.s f10, f1, f31 +fsub.s f10, f5, f0 +fsub.s f10, f5, f1 +fsub.s f10, f5, f5 +fsub.s f10, f5, f10 +fsub.s f10, f5, f15 +fsub.s f10, f5, f20 +fsub.s f10, f5, f25 +fsub.s f10, f5, f31 +fsub.s f10, f10, f0 +fsub.s f10, f10, f1 +fsub.s f10, f10, f5 +fsub.s f10, f10, f10 +fsub.s f10, f10, f15 +fsub.s f10, f10, f20 +fsub.s f10, f10, f25 +fsub.s f10, f10, f31 +fsub.s f10, f15, f0 +fsub.s f10, f15, f1 +fsub.s f10, f15, f5 +fsub.s f10, f15, f10 +fsub.s f10, f15, f15 +fsub.s f10, f15, f20 +fsub.s f10, f15, f25 +fsub.s f10, f15, f31 +fsub.s f10, f20, f0 +fsub.s f10, f20, f1 +fsub.s f10, f20, f5 +fsub.s f10, f20, f10 +fsub.s f10, f20, f15 +fsub.s f10, f20, f20 +fsub.s f10, f20, f25 +fsub.s f10, f20, f31 +fsub.s f10, f25, f0 +fsub.s f10, f25, f1 +fsub.s f10, f25, f5 +fsub.s f10, f25, f10 +fsub.s f10, f25, f15 +fsub.s f10, f25, f20 +fsub.s f10, f25, f25 +fsub.s f10, f25, f31 +fsub.s f10, f31, f0 +fsub.s f10, f31, f1 +fsub.s f10, f31, f5 +fsub.s f10, f31, f10 +fsub.s f10, f31, f15 +fsub.s f10, f31, f20 +fsub.s f10, f31, f25 +fsub.s f10, f31, f31 +fsub.s f15, f0, f0 +fsub.s f15, f0, f1 +fsub.s f15, f0, f5 +fsub.s f15, f0, f10 +fsub.s f15, f0, f15 +fsub.s f15, f0, f20 +fsub.s f15, f0, f25 +fsub.s f15, f0, f31 +fsub.s f15, f1, f0 +fsub.s f15, f1, f1 +fsub.s f15, f1, f5 +fsub.s f15, f1, f10 +fsub.s f15, f1, f15 +fsub.s f15, f1, f20 +fsub.s f15, f1, f25 +fsub.s f15, f1, f31 +fsub.s f15, f5, f0 +fsub.s f15, f5, f1 +fsub.s f15, f5, f5 +fsub.s f15, f5, f10 +fsub.s f15, f5, f15 +fsub.s f15, f5, f20 +fsub.s f15, f5, f25 +fsub.s f15, f5, f31 +fsub.s f15, f10, f0 +fsub.s f15, f10, f1 +fsub.s f15, f10, f5 +fsub.s f15, f10, f10 +fsub.s f15, f10, f15 +fsub.s f15, f10, f20 +fsub.s f15, f10, f25 +fsub.s f15, f10, f31 +fsub.s f15, f15, f0 +fsub.s f15, f15, f1 +fsub.s f15, f15, f5 +fsub.s f15, f15, f10 +fsub.s f15, f15, f15 +fsub.s f15, f15, f20 +fsub.s f15, f15, f25 +fsub.s f15, f15, f31 +fsub.s f15, f20, f0 +fsub.s f15, f20, f1 +fsub.s f15, f20, f5 +fsub.s f15, f20, f10 +fsub.s f15, f20, f15 +fsub.s f15, f20, f20 +fsub.s f15, f20, f25 +fsub.s f15, f20, f31 +fsub.s f15, f25, f0 +fsub.s f15, f25, f1 +fsub.s f15, f25, f5 +fsub.s f15, f25, f10 +fsub.s f15, f25, f15 +fsub.s f15, f25, f20 +fsub.s f15, f25, f25 +fsub.s f15, f25, f31 +fsub.s f15, f31, f0 +fsub.s f15, f31, f1 +fsub.s f15, f31, f5 +fsub.s f15, f31, f10 +fsub.s f15, f31, f15 +fsub.s f15, f31, f20 +fsub.s f15, f31, f25 +fsub.s f15, f31, f31 +fsub.s f20, f0, f0 +fsub.s f20, f0, f1 +fsub.s f20, f0, f5 +fsub.s f20, f0, f10 +fsub.s f20, f0, f15 +fsub.s f20, f0, f20 +fsub.s f20, f0, f25 +fsub.s f20, f0, f31 +fsub.s f20, f1, f0 +fsub.s f20, f1, f1 +fsub.s f20, f1, f5 +fsub.s f20, f1, f10 +fsub.s f20, f1, f15 +fsub.s f20, f1, f20 +fsub.s f20, f1, f25 +fsub.s f20, f1, f31 +fsub.s f20, f5, f0 +fsub.s f20, f5, f1 +fsub.s f20, f5, f5 +fsub.s f20, f5, f10 +fsub.s f20, f5, f15 +fsub.s f20, f5, f20 +fsub.s f20, f5, f25 +fsub.s f20, f5, f31 +fsub.s f20, f10, f0 +fsub.s f20, f10, f1 +fsub.s f20, f10, f5 +fsub.s f20, f10, f10 +fsub.s f20, f10, f15 +fsub.s f20, f10, f20 +fsub.s f20, f10, f25 +fsub.s f20, f10, f31 +fsub.s f20, f15, f0 +fsub.s f20, f15, f1 +fsub.s f20, f15, f5 +fsub.s f20, f15, f10 +fsub.s f20, f15, f15 +fsub.s f20, f15, f20 +fsub.s f20, f15, f25 +fsub.s f20, f15, f31 +fsub.s f20, f20, f0 +fsub.s f20, f20, f1 +fsub.s f20, f20, f5 +fsub.s f20, f20, f10 +fsub.s f20, f20, f15 +fsub.s f20, f20, f20 +fsub.s f20, f20, f25 +fsub.s f20, f20, f31 +fsub.s f20, f25, f0 +fsub.s f20, f25, f1 +fsub.s f20, f25, f5 +fsub.s f20, f25, f10 +fsub.s f20, f25, f15 +fsub.s f20, f25, f20 +fsub.s f20, f25, f25 +fsub.s f20, f25, f31 +fsub.s f20, f31, f0 +fsub.s f20, f31, f1 +fsub.s f20, f31, f5 +fsub.s f20, f31, f10 +fsub.s f20, f31, f15 +fsub.s f20, f31, f20 +fsub.s f20, f31, f25 +fsub.s f20, f31, f31 +fsub.s f25, f0, f0 +fsub.s f25, f0, f1 +fsub.s f25, f0, f5 +fsub.s f25, f0, f10 +fsub.s f25, f0, f15 +fsub.s f25, f0, f20 +fsub.s f25, f0, f25 +fsub.s f25, f0, f31 +fsub.s f25, f1, f0 +fsub.s f25, f1, f1 +fsub.s f25, f1, f5 +fsub.s f25, f1, f10 +fsub.s f25, f1, f15 +fsub.s f25, f1, f20 +fsub.s f25, f1, f25 +fsub.s f25, f1, f31 +fsub.s f25, f5, f0 +fsub.s f25, f5, f1 +fsub.s f25, f5, f5 +fsub.s f25, f5, f10 +fsub.s f25, f5, f15 +fsub.s f25, f5, f20 +fsub.s f25, f5, f25 +fsub.s f25, f5, f31 +fsub.s f25, f10, f0 +fsub.s f25, f10, f1 +fsub.s f25, f10, f5 +fsub.s f25, f10, f10 +fsub.s f25, f10, f15 +fsub.s f25, f10, f20 +fsub.s f25, f10, f25 +fsub.s f25, f10, f31 +fsub.s f25, f15, f0 +fsub.s f25, f15, f1 +fsub.s f25, f15, f5 +fsub.s f25, f15, f10 +fsub.s f25, f15, f15 +fsub.s f25, f15, f20 +fsub.s f25, f15, f25 +fsub.s f25, f15, f31 +fsub.s f25, f20, f0 +fsub.s f25, f20, f1 +fsub.s f25, f20, f5 +fsub.s f25, f20, f10 +fsub.s f25, f20, f15 +fsub.s f25, f20, f20 +fsub.s f25, f20, f25 +fsub.s f25, f20, f31 +fsub.s f25, f25, f0 +fsub.s f25, f25, f1 +fsub.s f25, f25, f5 +fsub.s f25, f25, f10 +fsub.s f25, f25, f15 +fsub.s f25, f25, f20 +fsub.s f25, f25, f25 +fsub.s f25, f25, f31 +fsub.s f25, f31, f0 +fsub.s f25, f31, f1 +fsub.s f25, f31, f5 +fsub.s f25, f31, f10 +fsub.s f25, f31, f15 +fsub.s f25, f31, f20 +fsub.s f25, f31, f25 +fsub.s f25, f31, f31 +fsub.s f31, f0, f0 +fsub.s f31, f0, f1 +fsub.s f31, f0, f5 +fsub.s f31, f0, f10 +fsub.s f31, f0, f15 +fsub.s f31, f0, f20 +fsub.s f31, f0, f25 +fsub.s f31, f0, f31 +fsub.s f31, f1, f0 +fsub.s f31, f1, f1 +fsub.s f31, f1, f5 +fsub.s f31, f1, f10 +fsub.s f31, f1, f15 +fsub.s f31, f1, f20 +fsub.s f31, f1, f25 +fsub.s f31, f1, f31 +fsub.s f31, f5, f0 +fsub.s f31, f5, f1 +fsub.s f31, f5, f5 +fsub.s f31, f5, f10 +fsub.s f31, f5, f15 +fsub.s f31, f5, f20 +fsub.s f31, f5, f25 +fsub.s f31, f5, f31 +fsub.s f31, f10, f0 +fsub.s f31, f10, f1 +fsub.s f31, f10, f5 +fsub.s f31, f10, f10 +fsub.s f31, f10, f15 +fsub.s f31, f10, f20 +fsub.s f31, f10, f25 +fsub.s f31, f10, f31 +fsub.s f31, f15, f0 +fsub.s f31, f15, f1 +fsub.s f31, f15, f5 +fsub.s f31, f15, f10 +fsub.s f31, f15, f15 +fsub.s f31, f15, f20 +fsub.s f31, f15, f25 +fsub.s f31, f15, f31 +fsub.s f31, f20, f0 +fsub.s f31, f20, f1 +fsub.s f31, f20, f5 +fsub.s f31, f20, f10 +fsub.s f31, f20, f15 +fsub.s f31, f20, f20 +fsub.s f31, f20, f25 +fsub.s f31, f20, f31 +fsub.s f31, f25, f0 +fsub.s f31, f25, f1 +fsub.s f31, f25, f5 +fsub.s f31, f25, f10 +fsub.s f31, f25, f15 +fsub.s f31, f25, f20 +fsub.s f31, f25, f25 +fsub.s f31, f25, f31 +fsub.s f31, f31, f0 +fsub.s f31, f31, f1 +fsub.s f31, f31, f5 +fsub.s f31, f31, f10 +fsub.s f31, f31, f15 +fsub.s f31, f31, f20 +fsub.s f31, f31, f25 +fsub.s f31, f31, f31 diff --git a/tests/riscv/f-extension/fsub_s.asm b/tests/riscv/f-extension/fsub_s.asm new file mode 100644 index 0000000..c9c11bd --- /dev/null +++ b/tests/riscv/f-extension/fsub_s.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fsub.s f0, f1, f2 + diff --git a/tests/riscv/f-extension/fsub_s.bin b/tests/riscv/f-extension/fsub_s.bin new file mode 100644 index 0000000..b340b91 --- /dev/null +++ b/tests/riscv/f-extension/fsub_s.bin @@ -0,0 +1 @@ +S  \ No newline at end of file diff --git a/tests/riscv/f-extension/fsub_s.disasm b/tests/riscv/f-extension/fsub_s.disasm new file mode 100644 index 0000000..4538ea8 --- /dev/null +++ b/tests/riscv/f-extension/fsub_s.disasm @@ -0,0 +1 @@ +fsub.s f0, f1, f2 diff --git a/tests/riscv/f-extension/fsw.asm b/tests/riscv/f-extension/fsw.asm new file mode 100644 index 0000000..8c3d2c7 --- /dev/null +++ b/tests/riscv/f-extension/fsw.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +fsw f0, (#-2047, zero) +fsw f0, (#-1024, zero) +fsw f0, (#-512, zero) +fsw f0, (#-256, zero) +fsw f0, (#-128, zero) +fsw f0, (#-64, zero) +fsw f0, (#-32, zero) +fsw f0, (#-16, zero) +fsw f0, (#-8, zero) +fsw f0, (#-4, zero) +fsw f0, (#-2, zero) +fsw f0, (#-1, zero) +fsw f0, (#0, zero) +fsw f0, (#1, zero) +fsw f0, (#2, zero) +fsw f0, (#4, zero) +fsw f0, (#8, zero) +fsw f0, (#16, zero) +fsw f0, (#32, zero) +fsw f0, (#64, zero) +fsw f0, (#128, zero) +fsw f0, (#256, zero) +fsw f0, (#512, zero) +fsw f0, (#1024, zero) +fsw f0, (#2047, zero) +fsw f0, (#-2047, ra) +fsw f0, (#-1024, ra) +fsw f0, (#-512, ra) +fsw f0, (#-256, ra) +fsw f0, (#-128, ra) +fsw f0, (#-64, ra) +fsw f0, (#-32, ra) +fsw f0, (#-16, ra) +fsw f0, (#-8, ra) +fsw f0, (#-4, ra) +fsw f0, (#-2, ra) +fsw f0, (#-1, ra) +fsw f0, (#0, ra) +fsw f0, (#1, ra) +fsw f0, (#2, ra) +fsw f0, (#4, ra) +fsw f0, (#8, ra) +fsw f0, (#16, ra) +fsw f0, (#32, ra) +fsw f0, (#64, ra) +fsw f0, (#128, ra) +fsw f0, (#256, ra) +fsw f0, (#512, ra) +fsw f0, (#1024, ra) +fsw f0, (#2047, ra) +fsw f0, (#-2047, t0) +fsw f0, (#-1024, t0) +fsw f0, (#-512, t0) +fsw f0, (#-256, t0) +fsw f0, (#-128, t0) +fsw f0, (#-64, t0) +fsw f0, (#-32, t0) +fsw f0, (#-16, t0) +fsw f0, (#-8, t0) +fsw f0, (#-4, t0) +fsw f0, (#-2, t0) +fsw f0, (#-1, t0) +fsw f0, (#0, t0) +fsw f0, (#1, t0) +fsw f0, (#2, t0) +fsw f0, (#4, t0) +fsw f0, (#8, t0) +fsw f0, (#16, t0) +fsw f0, (#32, t0) +fsw f0, (#64, t0) +fsw f0, (#128, t0) +fsw f0, (#256, t0) +fsw f0, (#512, t0) +fsw f0, (#1024, t0) +fsw f0, (#2047, t0) +fsw f0, (#-2047, a0) +fsw f0, (#-1024, a0) +fsw f0, (#-512, a0) +fsw f0, (#-256, a0) +fsw f0, (#-128, a0) +fsw f0, (#-64, a0) +fsw f0, (#-32, a0) +fsw f0, (#-16, a0) +fsw f0, (#-8, a0) +fsw f0, (#-4, a0) +fsw f0, (#-2, a0) +fsw f0, (#-1, a0) +fsw f0, (#0, a0) +fsw f0, (#1, a0) +fsw f0, (#2, a0) +fsw f0, (#4, a0) +fsw f0, (#8, a0) +fsw f0, (#16, a0) +fsw f0, (#32, a0) +fsw f0, (#64, a0) +fsw f0, (#128, a0) +fsw f0, (#256, a0) +fsw f0, (#512, a0) +fsw f0, (#1024, a0) +fsw f0, (#2047, a0) +fsw f0, (#-2047, a5) +fsw f0, (#-1024, a5) +fsw f0, (#-512, a5) +fsw f0, (#-256, a5) +fsw f0, (#-128, a5) +fsw f0, (#-64, a5) +fsw f0, (#-32, a5) +fsw f0, (#-16, a5) +fsw f0, (#-8, a5) +fsw f0, (#-4, a5) +fsw f0, (#-2, a5) +fsw f0, (#-1, a5) +fsw f0, (#0, a5) +fsw f0, (#1, a5) +fsw f0, (#2, a5) +fsw f0, (#4, a5) +fsw f0, (#8, a5) +fsw f0, (#16, a5) +fsw f0, (#32, a5) +fsw f0, (#64, a5) +fsw f0, (#128, a5) +fsw f0, (#256, a5) +fsw f0, (#512, a5) +fsw f0, (#1024, a5) +fsw f0, (#2047, a5) +fsw f0, (#-2047, s4) +fsw f0, (#-1024, s4) +fsw f0, (#-512, s4) +fsw f0, (#-256, s4) +fsw f0, (#-128, s4) +fsw f0, (#-64, s4) +fsw f0, (#-32, s4) +fsw f0, (#-16, s4) +fsw f0, (#-8, s4) +fsw f0, (#-4, s4) +fsw f0, (#-2, s4) +fsw f0, (#-1, s4) +fsw f0, (#0, s4) +fsw f0, (#1, s4) +fsw f0, (#2, s4) +fsw f0, (#4, s4) +fsw f0, (#8, s4) +fsw f0, (#16, s4) +fsw f0, (#32, s4) +fsw f0, (#64, s4) +fsw f0, (#128, s4) +fsw f0, (#256, s4) +fsw f0, (#512, s4) +fsw f0, (#1024, s4) +fsw f0, (#2047, s4) +fsw f0, (#-2047, s9) +fsw f0, (#-1024, s9) +fsw f0, (#-512, s9) +fsw f0, (#-256, s9) +fsw f0, (#-128, s9) +fsw f0, (#-64, s9) +fsw f0, (#-32, s9) +fsw f0, (#-16, s9) +fsw f0, (#-8, s9) +fsw f0, (#-4, s9) +fsw f0, (#-2, s9) +fsw f0, (#-1, s9) +fsw f0, (#0, s9) +fsw f0, (#1, s9) +fsw f0, (#2, s9) +fsw f0, (#4, s9) +fsw f0, (#8, s9) +fsw f0, (#16, s9) +fsw f0, (#32, s9) +fsw f0, (#64, s9) +fsw f0, (#128, s9) +fsw f0, (#256, s9) +fsw f0, (#512, s9) +fsw f0, (#1024, s9) +fsw f0, (#2047, s9) +fsw f0, (#-2047, t6) +fsw f0, (#-1024, t6) +fsw f0, (#-512, t6) +fsw f0, (#-256, t6) +fsw f0, (#-128, t6) +fsw f0, (#-64, t6) +fsw f0, (#-32, t6) +fsw f0, (#-16, t6) +fsw f0, (#-8, t6) +fsw f0, (#-4, t6) +fsw f0, (#-2, t6) +fsw f0, (#-1, t6) +fsw f0, (#0, t6) +fsw f0, (#1, t6) +fsw f0, (#2, t6) +fsw f0, (#4, t6) +fsw f0, (#8, t6) +fsw f0, (#16, t6) +fsw f0, (#32, t6) +fsw f0, (#64, t6) +fsw f0, (#128, t6) +fsw f0, (#256, t6) +fsw f0, (#512, t6) +fsw f0, (#1024, t6) +fsw f0, (#2047, t6) +fsw f1, (#-2047, zero) +fsw f1, (#-1024, zero) +fsw f1, (#-512, zero) +fsw f1, (#-256, zero) +fsw f1, (#-128, zero) +fsw f1, (#-64, zero) +fsw f1, (#-32, zero) +fsw f1, (#-16, zero) +fsw f1, (#-8, zero) +fsw f1, (#-4, zero) +fsw f1, (#-2, zero) +fsw f1, (#-1, zero) +fsw f1, (#0, zero) +fsw f1, (#1, zero) +fsw f1, (#2, zero) +fsw f1, (#4, zero) +fsw f1, (#8, zero) +fsw f1, (#16, zero) +fsw f1, (#32, zero) +fsw f1, (#64, zero) +fsw f1, (#128, zero) +fsw f1, (#256, zero) +fsw f1, (#512, zero) +fsw f1, (#1024, zero) +fsw f1, (#2047, zero) +fsw f1, (#-2047, ra) +fsw f1, (#-1024, ra) +fsw f1, (#-512, ra) +fsw f1, (#-256, ra) +fsw f1, (#-128, ra) +fsw f1, (#-64, ra) +fsw f1, (#-32, ra) +fsw f1, (#-16, ra) +fsw f1, (#-8, ra) +fsw f1, (#-4, ra) +fsw f1, (#-2, ra) +fsw f1, (#-1, ra) +fsw f1, (#0, ra) +fsw f1, (#1, ra) +fsw f1, (#2, ra) +fsw f1, (#4, ra) +fsw f1, (#8, ra) +fsw f1, (#16, ra) +fsw f1, (#32, ra) +fsw f1, (#64, ra) +fsw f1, (#128, ra) +fsw f1, (#256, ra) +fsw f1, (#512, ra) +fsw f1, (#1024, ra) +fsw f1, (#2047, ra) +fsw f1, (#-2047, t0) +fsw f1, (#-1024, t0) +fsw f1, (#-512, t0) +fsw f1, (#-256, t0) +fsw f1, (#-128, t0) +fsw f1, (#-64, t0) +fsw f1, (#-32, t0) +fsw f1, (#-16, t0) +fsw f1, (#-8, t0) +fsw f1, (#-4, t0) +fsw f1, (#-2, t0) +fsw f1, (#-1, t0) +fsw f1, (#0, t0) +fsw f1, (#1, t0) +fsw f1, (#2, t0) +fsw f1, (#4, t0) +fsw f1, (#8, t0) +fsw f1, (#16, t0) +fsw f1, (#32, t0) +fsw f1, (#64, t0) +fsw f1, (#128, t0) +fsw f1, (#256, t0) +fsw f1, (#512, t0) +fsw f1, (#1024, t0) +fsw f1, (#2047, t0) +fsw f1, (#-2047, a0) +fsw f1, (#-1024, a0) +fsw f1, (#-512, a0) +fsw f1, (#-256, a0) +fsw f1, (#-128, a0) +fsw f1, (#-64, a0) +fsw f1, (#-32, a0) +fsw f1, (#-16, a0) +fsw f1, (#-8, a0) +fsw f1, (#-4, a0) +fsw f1, (#-2, a0) +fsw f1, (#-1, a0) +fsw f1, (#0, a0) +fsw f1, (#1, a0) +fsw f1, (#2, a0) +fsw f1, (#4, a0) +fsw f1, (#8, a0) +fsw f1, (#16, a0) +fsw f1, (#32, a0) +fsw f1, (#64, a0) +fsw f1, (#128, a0) +fsw f1, (#256, a0) +fsw f1, (#512, a0) +fsw f1, (#1024, a0) +fsw f1, (#2047, a0) +fsw f1, (#-2047, a5) +fsw f1, (#-1024, a5) +fsw f1, (#-512, a5) +fsw f1, (#-256, a5) +fsw f1, (#-128, a5) +fsw f1, (#-64, a5) +fsw f1, (#-32, a5) +fsw f1, (#-16, a5) +fsw f1, (#-8, a5) +fsw f1, (#-4, a5) +fsw f1, (#-2, a5) +fsw f1, (#-1, a5) +fsw f1, (#0, a5) +fsw f1, (#1, a5) +fsw f1, (#2, a5) +fsw f1, (#4, a5) +fsw f1, (#8, a5) +fsw f1, (#16, a5) +fsw f1, (#32, a5) +fsw f1, (#64, a5) +fsw f1, (#128, a5) +fsw f1, (#256, a5) +fsw f1, (#512, a5) +fsw f1, (#1024, a5) +fsw f1, (#2047, a5) +fsw f1, (#-2047, s4) +fsw f1, (#-1024, s4) +fsw f1, (#-512, s4) +fsw f1, (#-256, s4) +fsw f1, (#-128, s4) +fsw f1, (#-64, s4) +fsw f1, (#-32, s4) +fsw f1, (#-16, s4) +fsw f1, (#-8, s4) +fsw f1, (#-4, s4) +fsw f1, (#-2, s4) +fsw f1, (#-1, s4) +fsw f1, (#0, s4) +fsw f1, (#1, s4) +fsw f1, (#2, s4) +fsw f1, (#4, s4) +fsw f1, (#8, s4) +fsw f1, (#16, s4) +fsw f1, (#32, s4) +fsw f1, (#64, s4) +fsw f1, (#128, s4) +fsw f1, (#256, s4) +fsw f1, (#512, s4) +fsw f1, (#1024, s4) +fsw f1, (#2047, s4) +fsw f1, (#-2047, s9) +fsw f1, (#-1024, s9) +fsw f1, (#-512, s9) +fsw f1, (#-256, s9) +fsw f1, (#-128, s9) +fsw f1, (#-64, s9) +fsw f1, (#-32, s9) +fsw f1, (#-16, s9) +fsw f1, (#-8, s9) +fsw f1, (#-4, s9) +fsw f1, (#-2, s9) +fsw f1, (#-1, s9) +fsw f1, (#0, s9) +fsw f1, (#1, s9) +fsw f1, (#2, s9) +fsw f1, (#4, s9) +fsw f1, (#8, s9) +fsw f1, (#16, s9) +fsw f1, (#32, s9) +fsw f1, (#64, s9) +fsw f1, (#128, s9) +fsw f1, (#256, s9) +fsw f1, (#512, s9) +fsw f1, (#1024, s9) +fsw f1, (#2047, s9) +fsw f1, (#-2047, t6) +fsw f1, (#-1024, t6) +fsw f1, (#-512, t6) +fsw f1, (#-256, t6) +fsw f1, (#-128, t6) +fsw f1, (#-64, t6) +fsw f1, (#-32, t6) +fsw f1, (#-16, t6) +fsw f1, (#-8, t6) +fsw f1, (#-4, t6) +fsw f1, (#-2, t6) +fsw f1, (#-1, t6) +fsw f1, (#0, t6) +fsw f1, (#1, t6) +fsw f1, (#2, t6) +fsw f1, (#4, t6) +fsw f1, (#8, t6) +fsw f1, (#16, t6) +fsw f1, (#32, t6) +fsw f1, (#64, t6) +fsw f1, (#128, t6) +fsw f1, (#256, t6) +fsw f1, (#512, t6) +fsw f1, (#1024, t6) +fsw f1, (#2047, t6) +fsw f5, (#-2047, zero) +fsw f5, (#-1024, zero) +fsw f5, (#-512, zero) +fsw f5, (#-256, zero) +fsw f5, (#-128, zero) +fsw f5, (#-64, zero) +fsw f5, (#-32, zero) +fsw f5, (#-16, zero) +fsw f5, (#-8, zero) +fsw f5, (#-4, zero) +fsw f5, (#-2, zero) +fsw f5, (#-1, zero) +fsw f5, (#0, zero) +fsw f5, (#1, zero) +fsw f5, (#2, zero) +fsw f5, (#4, zero) +fsw f5, (#8, zero) +fsw f5, (#16, zero) +fsw f5, (#32, zero) +fsw f5, (#64, zero) +fsw f5, (#128, zero) +fsw f5, (#256, zero) +fsw f5, (#512, zero) +fsw f5, (#1024, zero) +fsw f5, (#2047, zero) +fsw f5, (#-2047, ra) +fsw f5, (#-1024, ra) +fsw f5, (#-512, ra) +fsw f5, (#-256, ra) +fsw f5, (#-128, ra) +fsw f5, (#-64, ra) +fsw f5, (#-32, ra) +fsw f5, (#-16, ra) +fsw f5, (#-8, ra) +fsw f5, (#-4, ra) +fsw f5, (#-2, ra) +fsw f5, (#-1, ra) +fsw f5, (#0, ra) +fsw f5, (#1, ra) +fsw f5, (#2, ra) +fsw f5, (#4, ra) +fsw f5, (#8, ra) +fsw f5, (#16, ra) +fsw f5, (#32, ra) +fsw f5, (#64, ra) +fsw f5, (#128, ra) +fsw f5, (#256, ra) +fsw f5, (#512, ra) +fsw f5, (#1024, ra) +fsw f5, (#2047, ra) +fsw f5, (#-2047, t0) +fsw f5, (#-1024, t0) +fsw f5, (#-512, t0) +fsw f5, (#-256, t0) +fsw f5, (#-128, t0) +fsw f5, (#-64, t0) +fsw f5, (#-32, t0) +fsw f5, (#-16, t0) +fsw f5, (#-8, t0) +fsw f5, (#-4, t0) +fsw f5, (#-2, t0) +fsw f5, (#-1, t0) +fsw f5, (#0, t0) +fsw f5, (#1, t0) +fsw f5, (#2, t0) +fsw f5, (#4, t0) +fsw f5, (#8, t0) +fsw f5, (#16, t0) +fsw f5, (#32, t0) +fsw f5, (#64, t0) +fsw f5, (#128, t0) +fsw f5, (#256, t0) +fsw f5, (#512, t0) +fsw f5, (#1024, t0) +fsw f5, (#2047, t0) +fsw f5, (#-2047, a0) +fsw f5, (#-1024, a0) +fsw f5, (#-512, a0) +fsw f5, (#-256, a0) +fsw f5, (#-128, a0) +fsw f5, (#-64, a0) +fsw f5, (#-32, a0) +fsw f5, (#-16, a0) +fsw f5, (#-8, a0) +fsw f5, (#-4, a0) +fsw f5, (#-2, a0) +fsw f5, (#-1, a0) +fsw f5, (#0, a0) +fsw f5, (#1, a0) +fsw f5, (#2, a0) +fsw f5, (#4, a0) +fsw f5, (#8, a0) +fsw f5, (#16, a0) +fsw f5, (#32, a0) +fsw f5, (#64, a0) +fsw f5, (#128, a0) +fsw f5, (#256, a0) +fsw f5, (#512, a0) +fsw f5, (#1024, a0) +fsw f5, (#2047, a0) +fsw f5, (#-2047, a5) +fsw f5, (#-1024, a5) +fsw f5, (#-512, a5) +fsw f5, (#-256, a5) +fsw f5, (#-128, a5) +fsw f5, (#-64, a5) +fsw f5, (#-32, a5) +fsw f5, (#-16, a5) +fsw f5, (#-8, a5) +fsw f5, (#-4, a5) +fsw f5, (#-2, a5) +fsw f5, (#-1, a5) +fsw f5, (#0, a5) +fsw f5, (#1, a5) +fsw f5, (#2, a5) +fsw f5, (#4, a5) +fsw f5, (#8, a5) +fsw f5, (#16, a5) +fsw f5, (#32, a5) +fsw f5, (#64, a5) +fsw f5, (#128, a5) +fsw f5, (#256, a5) +fsw f5, (#512, a5) +fsw f5, (#1024, a5) +fsw f5, (#2047, a5) +fsw f5, (#-2047, s4) +fsw f5, (#-1024, s4) +fsw f5, (#-512, s4) +fsw f5, (#-256, s4) +fsw f5, (#-128, s4) +fsw f5, (#-64, s4) +fsw f5, (#-32, s4) +fsw f5, (#-16, s4) +fsw f5, (#-8, s4) +fsw f5, (#-4, s4) +fsw f5, (#-2, s4) +fsw f5, (#-1, s4) +fsw f5, (#0, s4) +fsw f5, (#1, s4) +fsw f5, (#2, s4) +fsw f5, (#4, s4) +fsw f5, (#8, s4) +fsw f5, (#16, s4) +fsw f5, (#32, s4) +fsw f5, (#64, s4) +fsw f5, (#128, s4) +fsw f5, (#256, s4) +fsw f5, (#512, s4) +fsw f5, (#1024, s4) +fsw f5, (#2047, s4) +fsw f5, (#-2047, s9) +fsw f5, (#-1024, s9) +fsw f5, (#-512, s9) +fsw f5, (#-256, s9) +fsw f5, (#-128, s9) +fsw f5, (#-64, s9) +fsw f5, (#-32, s9) +fsw f5, (#-16, s9) +fsw f5, (#-8, s9) +fsw f5, (#-4, s9) +fsw f5, (#-2, s9) +fsw f5, (#-1, s9) +fsw f5, (#0, s9) +fsw f5, (#1, s9) +fsw f5, (#2, s9) +fsw f5, (#4, s9) +fsw f5, (#8, s9) +fsw f5, (#16, s9) +fsw f5, (#32, s9) +fsw f5, (#64, s9) +fsw f5, (#128, s9) +fsw f5, (#256, s9) +fsw f5, (#512, s9) +fsw f5, (#1024, s9) +fsw f5, (#2047, s9) +fsw f5, (#-2047, t6) +fsw f5, (#-1024, t6) +fsw f5, (#-512, t6) +fsw f5, (#-256, t6) +fsw f5, (#-128, t6) +fsw f5, (#-64, t6) +fsw f5, (#-32, t6) +fsw f5, (#-16, t6) +fsw f5, (#-8, t6) +fsw f5, (#-4, t6) +fsw f5, (#-2, t6) +fsw f5, (#-1, t6) +fsw f5, (#0, t6) +fsw f5, (#1, t6) +fsw f5, (#2, t6) +fsw f5, (#4, t6) +fsw f5, (#8, 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f25, (#-32, s9) +fsw f25, (#-16, s9) +fsw f25, (#-8, s9) +fsw f25, (#-4, s9) +fsw f25, (#-2, s9) +fsw f25, (#-1, s9) +fsw f25, (#0, s9) +fsw f25, (#1, s9) +fsw f25, (#2, s9) +fsw f25, (#4, s9) +fsw f25, (#8, s9) +fsw f25, (#16, s9) +fsw f25, (#32, s9) +fsw f25, (#64, s9) +fsw f25, (#128, s9) +fsw f25, (#256, s9) +fsw f25, (#512, s9) +fsw f25, (#1024, s9) +fsw f25, (#2047, s9) +fsw f25, (#-2047, t6) +fsw f25, (#-1024, t6) +fsw f25, (#-512, t6) +fsw f25, (#-256, t6) +fsw f25, (#-128, t6) +fsw f25, (#-64, t6) +fsw f25, (#-32, t6) +fsw f25, (#-16, t6) +fsw f25, (#-8, t6) +fsw f25, (#-4, t6) +fsw f25, (#-2, t6) +fsw f25, (#-1, t6) +fsw f25, (#0, t6) +fsw f25, (#1, t6) +fsw f25, (#2, t6) +fsw f25, (#4, t6) +fsw f25, (#8, t6) +fsw f25, (#16, t6) +fsw f25, (#32, t6) +fsw f25, (#64, t6) +fsw f25, (#128, t6) +fsw f25, (#256, t6) +fsw f25, (#512, t6) +fsw f25, (#1024, t6) +fsw f25, (#2047, t6) +fsw f31, (#-2047, zero) +fsw f31, (#-1024, zero) +fsw f31, (#-512, zero) +fsw f31, (#-256, zero) +fsw f31, (#-128, zero) +fsw f31, (#-64, zero) +fsw f31, (#-32, zero) +fsw f31, (#-16, zero) +fsw f31, (#-8, zero) +fsw f31, (#-4, zero) +fsw f31, (#-2, zero) +fsw f31, (#-1, zero) +fsw f31, (#0, zero) +fsw f31, (#1, zero) +fsw f31, (#2, zero) +fsw f31, (#4, zero) +fsw f31, (#8, zero) +fsw f31, (#16, zero) +fsw f31, (#32, zero) +fsw f31, (#64, zero) +fsw f31, (#128, zero) +fsw f31, (#256, zero) +fsw f31, (#512, zero) +fsw f31, (#1024, zero) +fsw f31, (#2047, zero) +fsw f31, (#-2047, ra) +fsw f31, (#-1024, ra) +fsw f31, (#-512, ra) +fsw f31, (#-256, ra) +fsw f31, (#-128, ra) +fsw f31, (#-64, ra) +fsw f31, (#-32, ra) +fsw f31, (#-16, ra) +fsw f31, (#-8, ra) +fsw f31, (#-4, ra) +fsw f31, (#-2, ra) +fsw f31, (#-1, ra) +fsw f31, (#0, ra) +fsw f31, (#1, ra) +fsw f31, (#2, ra) +fsw f31, (#4, ra) +fsw f31, (#8, ra) +fsw f31, (#16, ra) +fsw f31, (#32, ra) +fsw f31, (#64, ra) +fsw f31, (#128, ra) +fsw f31, (#256, ra) +fsw f31, (#512, ra) +fsw f31, (#1024, ra) +fsw f31, (#2047, ra) +fsw f31, (#-2047, t0) +fsw f31, (#-1024, t0) +fsw f31, (#-512, t0) +fsw f31, (#-256, t0) +fsw f31, (#-128, t0) +fsw f31, (#-64, t0) +fsw f31, (#-32, t0) +fsw f31, (#-16, t0) +fsw f31, (#-8, t0) +fsw f31, (#-4, t0) +fsw f31, (#-2, t0) +fsw f31, (#-1, t0) +fsw f31, (#0, t0) +fsw f31, (#1, t0) +fsw f31, (#2, t0) +fsw f31, (#4, t0) +fsw f31, (#8, t0) +fsw f31, (#16, t0) +fsw f31, (#32, t0) +fsw f31, (#64, t0) +fsw f31, (#128, t0) +fsw f31, (#256, t0) +fsw f31, (#512, t0) +fsw f31, (#1024, t0) +fsw f31, (#2047, t0) +fsw f31, (#-2047, a0) +fsw f31, (#-1024, a0) +fsw f31, (#-512, a0) +fsw f31, (#-256, a0) +fsw f31, (#-128, a0) +fsw f31, (#-64, a0) +fsw f31, (#-32, a0) +fsw f31, (#-16, a0) +fsw f31, (#-8, a0) +fsw f31, (#-4, a0) +fsw f31, (#-2, a0) +fsw f31, (#-1, a0) +fsw f31, (#0, a0) +fsw f31, (#1, a0) +fsw f31, (#2, a0) +fsw f31, (#4, a0) +fsw f31, (#8, a0) +fsw f31, (#16, a0) +fsw f31, (#32, a0) +fsw f31, (#64, a0) +fsw f31, (#128, a0) +fsw f31, (#256, a0) +fsw f31, (#512, a0) +fsw f31, (#1024, a0) +fsw f31, (#2047, a0) +fsw f31, (#-2047, a5) +fsw f31, (#-1024, a5) +fsw f31, (#-512, a5) +fsw f31, (#-256, a5) +fsw f31, (#-128, a5) +fsw f31, (#-64, a5) +fsw f31, (#-32, a5) +fsw f31, (#-16, a5) +fsw f31, (#-8, a5) +fsw f31, (#-4, a5) +fsw f31, (#-2, a5) +fsw f31, (#-1, a5) +fsw f31, (#0, a5) +fsw f31, (#1, a5) +fsw f31, (#2, a5) +fsw f31, (#4, a5) +fsw f31, (#8, a5) +fsw f31, (#16, a5) +fsw f31, (#32, a5) +fsw f31, (#64, a5) +fsw f31, (#128, a5) +fsw f31, (#256, a5) +fsw f31, (#512, a5) +fsw f31, (#1024, a5) +fsw f31, (#2047, a5) +fsw f31, (#-2047, s4) +fsw f31, (#-1024, s4) +fsw f31, (#-512, s4) +fsw f31, (#-256, s4) +fsw f31, (#-128, s4) +fsw f31, (#-64, s4) +fsw f31, (#-32, s4) +fsw f31, (#-16, s4) +fsw f31, (#-8, s4) +fsw f31, (#-4, s4) +fsw f31, (#-2, s4) +fsw f31, (#-1, s4) +fsw f31, (#0, s4) +fsw f31, (#1, s4) +fsw f31, (#2, s4) +fsw f31, (#4, s4) +fsw f31, (#8, s4) +fsw f31, (#16, s4) +fsw f31, (#32, s4) +fsw f31, (#64, s4) +fsw f31, (#128, s4) +fsw f31, (#256, s4) +fsw f31, (#512, s4) +fsw f31, (#1024, s4) +fsw f31, (#2047, s4) +fsw f31, (#-2047, s9) +fsw f31, (#-1024, s9) +fsw f31, (#-512, s9) +fsw f31, (#-256, s9) +fsw f31, (#-128, s9) +fsw f31, (#-64, s9) +fsw f31, (#-32, s9) +fsw f31, (#-16, s9) +fsw f31, (#-8, s9) +fsw f31, (#-4, s9) +fsw f31, (#-2, s9) +fsw f31, (#-1, s9) +fsw f31, (#0, s9) +fsw f31, (#1, s9) +fsw f31, (#2, s9) +fsw f31, (#4, s9) +fsw f31, (#8, s9) +fsw f31, (#16, s9) +fsw f31, (#32, s9) +fsw f31, (#64, s9) +fsw f31, (#128, s9) +fsw f31, (#256, s9) +fsw f31, (#512, s9) +fsw f31, (#1024, s9) +fsw f31, (#2047, s9) +fsw f31, (#-2047, t6) +fsw f31, (#-1024, t6) +fsw f31, (#-512, t6) +fsw f31, (#-256, t6) +fsw f31, (#-128, t6) +fsw f31, (#-64, t6) +fsw f31, (#-32, t6) +fsw f31, (#-16, t6) +fsw f31, (#-8, t6) +fsw f31, (#-4, t6) +fsw f31, (#-2, t6) +fsw f31, (#-1, t6) +fsw f31, (#0, t6) +fsw f31, (#1, t6) +fsw f31, (#2, t6) +fsw f31, (#4, t6) +fsw f31, (#8, t6) +fsw f31, (#16, t6) +fsw f31, (#32, t6) +fsw f31, (#64, t6) +fsw f31, (#128, t6) +fsw f31, (#256, t6) +fsw f31, (#512, t6) +fsw f31, (#1024, t6) +fsw f31, (#2047, t6) diff --git a/tests/riscv/generate_riscv_tests.py b/tests/riscv/generate_riscv_tests.py new file mode 100755 index 0000000..27cb0a4 --- /dev/null +++ b/tests/riscv/generate_riscv_tests.py @@ -0,0 +1,551 @@ +#!/usr/bin/env python3 +""" +Generate comprehensive test cases for all RISC-V instructions. +Creates one test file per instruction with all valid register combinations +and immediate values (min, max, and samples in between). +""" + +import os +from pathlib import Path + +# RISC-V register names (x0-x31) +REGISTERS = [ + "zero", "ra", "sp", "gp", "tp", + "t0", "t1", "t2", + "s0", "s1", + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", + "t3", "t4", "t5", "t6" +] + +# Floating point registers +FREGISTERS = [f"f{i}" for i in range(32)] + +# Compressed registers (x8-x15, encoded as 0-7) +COMPRESSED_REGS = ["s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5"] + +# Immediate value ranges and samples +IMM12_RANGE = (-2048, 2047) +IMM12_SAMPLES = [-2047, -1024, -512, -256, -128, -64, -32, -16, -8, -4, -2, -1, + 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2047] + +SHAMT5_RANGE = (0, 31) +SHAMT5_SAMPLES = [0, 1, 2, 4, 8, 16, 31] + +IMM20_RANGE = (0, 0xFFFFF) +IMM20_SAMPLES = [0, 0x1000, 0x10000, 0x100000, 0xFFFFF] + +# For branch/jump instructions, we use labels +# We'll generate small offsets that can be represented + +def generate_test_file(extension_dir, instruction_name, test_cases): + """Generate a test file for an instruction.""" + test_dir = Path("tests/riscv") / extension_dir + test_dir.mkdir(parents=True, exist_ok=True) + + test_file = test_dir / f"{instruction_name}.asm" + + with open(test_file, 'w') as f: + f.write(".lang riscv32\n") + f.write(".org 0x0\n\n") + + for case in test_cases: + f.write(f"{case}\n") + + f.write("\n") + +def generate_r_type_tests(extension_dir, mnemonic): + """Generate tests for R-type instructions (rd, rs1, rs2).""" + test_cases = [] + + # Test all register combinations (sample a subset to avoid too many tests) + # Test with different register combinations + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs2_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = REGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + rs2 = REGISTERS[rs2_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}, {rs2}") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_i_type_tests(extension_dir, mnemonic): + """Generate tests for I-type instructions (rd, rs1, imm12).""" + test_cases = [] + + # Test with different registers and immediate values + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for imm in IMM12_SAMPLES: + rd = REGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}, #{imm}") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_shift_imm_tests(extension_dir, mnemonic): + """Generate tests for shift immediate instructions (rd, rs1, shamt5).""" + test_cases = [] + + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for shamt in SHAMT5_SAMPLES: + rd = REGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}, #{shamt}") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_u_type_tests(extension_dir, mnemonic): + """Generate tests for U-type instructions (rd, imm20).""" + test_cases = [] + + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for imm in IMM20_SAMPLES: + rd = REGISTERS[rd_idx] + test_cases.append(f"{mnemonic} {rd}, #{hex(imm)}") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_j_type_tests(extension_dir, mnemonic): + """Generate tests for J-type instructions (rd, label).""" + test_cases = [] + + # Generate multiple labels at different offsets + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = REGISTERS[rd_idx] + for i in range(10): + label = f"label_{i}" + test_cases.append(f"{mnemonic} {rd}, {label}") + test_cases.append(f"{label}:") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_b_type_tests(extension_dir, mnemonic): + """Generate tests for B-type instructions (rs1, rs2, label).""" + test_cases = [] + + label_count = 0 + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs2_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rs1 = REGISTERS[rs1_idx] + rs2 = REGISTERS[rs2_idx] + label = f"label_{label_count}" + test_cases.append(f"{mnemonic} {rs1}, {rs2}, {label}") + test_cases.append(f"{label}:") + label_count += 1 + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_load_tests(extension_dir, mnemonic): + """Generate tests for load instructions (rd, imm(rs1)).""" + test_cases = [] + + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for imm in IMM12_SAMPLES: + rd = REGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, (#{imm}, {rs1})") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_store_tests(extension_dir, mnemonic): + """Generate tests for store instructions (rs2, imm(rs1)).""" + test_cases = [] + + for rs2_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for imm in IMM12_SAMPLES: + rs2 = REGISTERS[rs2_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rs2}, (#{imm}, {rs1})") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_jalr_tests(extension_dir, mnemonic): + """Generate tests for JALR (rd, rs1, imm12).""" + test_cases = [] + + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for imm in IMM12_SAMPLES: + rd = REGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}, #{imm}") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_system_tests(extension_dir, mnemonic): + """Generate tests for system instructions (ecall, ebreak, fence, fence.i).""" + test_cases = [] + + if mnemonic == "ecall" or mnemonic == "ebreak": + test_cases.append(f"{mnemonic}") + elif mnemonic == "fence.i": + test_cases.append(f"{mnemonic}") + elif mnemonic == "fence": + # Fence has pred/succ fields + for pred in [0, 0xF, 0xFF]: + test_cases.append(f"{mnemonic} #{hex(pred)}, zero, zero") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_csr_tests(extension_dir, mnemonic): + """Generate tests for CSR instructions.""" + test_cases = [] + + # CSR register numbers (sample some common ones) + csr_regs = [0x000, 0x001, 0x002, 0x300, 0x301, 0x304, 0x305, 0x340, 0x341, 0xFFF] + + if mnemonic in ["csrrw", "csrrs", "csrrc"]: + # rd, csr, rs1 + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for csr in csr_regs: + rd = REGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, #{hex(csr)}, {rs1}") + elif mnemonic in ["csrrwi", "csrrsi", "csrrci"]: + # rd, csr, uimm5 + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for uimm in [0, 1, 5, 10, 15, 20, 25, 31]: + for csr in csr_regs: + rd = REGISTERS[rd_idx] + test_cases.append(f"{mnemonic} {rd}, #{hex(csr)}, #{uimm}") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_atomic_tests(extension_dir, mnemonic): + """Generate tests for atomic instructions.""" + test_cases = [] + + # Atomic instructions: rd, (rs1), rs2 or rd, rs2, (rs1) + if mnemonic in ["lr.w"]: + # lr.w rd, (rs1) + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = REGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, ({rs1})") + elif mnemonic in ["sc.w"]: + # sc.w rd, rs2, (rs1) + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs2_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = REGISTERS[rd_idx] + rs2 = REGISTERS[rs2_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs2}, ({rs1})") + else: + # amo* rd, rs2, (rs1) + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs2_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = REGISTERS[rd_idx] + rs2 = REGISTERS[rs2_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs2}, ({rs1})") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_float_tests(extension_dir, mnemonic): + """Generate tests for floating point instructions.""" + test_cases = [] + + # Determine instruction type from mnemonic + if mnemonic in ["flw", "fsw"]: + # Load/store: rd/rs2, imm(rs1) where rd/rs2 is FP register + for frd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for imm in IMM12_SAMPLES: + frd = FREGISTERS[frd_idx] + rs1 = REGISTERS[rs1_idx] + if mnemonic == "flw": + test_cases.append(f"{mnemonic} {frd}, (#{imm}, {rs1})") + else: + test_cases.append(f"{mnemonic} {frd}, (#{imm}, {rs1})") + elif mnemonic in ["fld", "fsd"]: + # Double precision load/store + for frd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for imm in IMM12_SAMPLES: + frd = FREGISTERS[frd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {frd}, (#{imm}, {rs1})") + elif mnemonic.startswith("fmadd") or mnemonic.startswith("fmsub") or \ + mnemonic.startswith("fnmsub") or mnemonic.startswith("fnmadd"): + # FMA instructions: rd, rs1, rs2, rs3 + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs2_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs3_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = FREGISTERS[rd_idx] + rs1 = FREGISTERS[rs1_idx] + rs2 = FREGISTERS[rs2_idx] + rs3 = FREGISTERS[rs3_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}, {rs2}, {rs3}") + elif mnemonic.startswith("fcvt.w") or mnemonic.startswith("fcvt.wu"): + # Convert to integer: rd (integer), rs1 (float) + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = REGISTERS[rd_idx] + rs1 = FREGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}") + elif mnemonic.startswith("fcvt.") and (".w" in mnemonic or ".wu" in mnemonic): + # Convert from integer: rd (float), rs1 (integer) + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = FREGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}") + elif mnemonic.startswith("fcvt.s.d") or mnemonic.startswith("fcvt.d.s"): + # Convert between float and double + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = FREGISTERS[rd_idx] + rs1 = FREGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}") + elif mnemonic.startswith("fmv.x.w") or mnemonic.startswith("fmv.w.x"): + # Move between float and integer registers + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + if "x.w" in mnemonic: + rd = REGISTERS[rd_idx] + rs1 = FREGISTERS[rs1_idx] + else: + rd = FREGISTERS[rd_idx] + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}") + elif mnemonic.startswith("fclass"): + # Classify: rd (integer), rs1 (float) + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = REGISTERS[rd_idx] + rs1 = FREGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}") + else: + # Most FP instructions: rd, rs1, rs2 + for rd_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs1_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + for rs2_idx in [0, 1, 5, 10, 15, 20, 25, 31]: + rd = FREGISTERS[rd_idx] + rs1 = FREGISTERS[rs1_idx] + rs2 = FREGISTERS[rs2_idx] + test_cases.append(f"{mnemonic} {rd}, {rs1}, {rs2}") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def generate_compressed_tests(extension_dir, mnemonic): + """Generate tests for compressed instructions.""" + test_cases = [] + + if mnemonic == "c.nop": + test_cases.append("c.nop") + elif mnemonic == "c.ebreak": + test_cases.append("c.ebreak") + elif mnemonic == "c.addi4spn": + # c.addi4spn rd', uimm[9:2] + for rd_idx in range(8): # Compressed registers + rd = COMPRESSED_REGS[rd_idx] + for imm in [0, 4, 8, 16, 32, 64, 128, 256, 512, 1020]: + test_cases.append(f"{mnemonic} {rd}, #{imm}") + elif mnemonic == "c.lw": + # c.lw rd', uimm[6:2](rs1') + for rd_idx in range(8): + for rs1_idx in range(8): + rd = COMPRESSED_REGS[rd_idx] + rs1 = COMPRESSED_REGS[rs1_idx] + for imm in [0, 4, 8, 16, 32, 64, 124]: + test_cases.append(f"{mnemonic} {rd}, #{imm}({rs1})") + elif mnemonic == "c.sw": + # c.sw rs2', uimm[6:2](rs1') + for rs2_idx in range(8): + for rs1_idx in range(8): + rs2 = COMPRESSED_REGS[rs2_idx] + rs1 = COMPRESSED_REGS[rs1_idx] + for imm in [0, 4, 8, 16, 32, 64, 124]: + test_cases.append(f"{mnemonic} {rs2}, #{imm}({rs1})") + elif mnemonic == "c.li": + # c.li rd, imm[5:0] + for rd_idx in [1, 5, 10, 15, 20, 25, 31]: # rd != 0 + rd = REGISTERS[rd_idx] + for imm in [-32, -16, -8, -4, -2, -1, 0, 1, 2, 4, 8, 16, 31]: + test_cases.append(f"{mnemonic} {rd}, #{imm}") + elif mnemonic == "c.addi16sp": + # c.addi16sp imm[9:4] + for imm in [-512, -256, -128, -64, -32, 32, 64, 128, 256, 496]: + test_cases.append(f"{mnemonic} #{imm}") + elif mnemonic == "c.lui": + # c.lui rd, imm[17:12] + for rd_idx in [3, 4, 5, 6, 7, 28, 29, 30, 31]: # rd != 0, 2 + rd = REGISTERS[rd_idx] + for imm in [0x1000, 0x2000, 0x4000, 0x8000, 0xF000, 0xFF000]: + test_cases.append(f"{mnemonic} {rd}, #{hex(imm)}") + elif mnemonic == "c.srli" or mnemonic == "c.srai": + # c.srli/c.srai rd', uimm[5:0] + for rd_idx in range(8): + rd = COMPRESSED_REGS[rd_idx] + for shamt in [0, 1, 2, 4, 8, 16, 31]: + test_cases.append(f"{mnemonic} {rd}, #{shamt}") + elif mnemonic == "c.andi": + # c.andi rd', imm[5:0] + for rd_idx in range(8): + rd = COMPRESSED_REGS[rd_idx] + for imm in [-32, -16, -8, -4, -2, -1, 0, 1, 2, 4, 8, 16, 31]: + test_cases.append(f"{mnemonic} {rd}, #{imm}") + elif mnemonic == "c.sub" or mnemonic == "c.xor" or mnemonic == "c.or" or mnemonic == "c.and": + # c.sub/c.xor/c.or/c.and rd', rs2' + for rd_idx in range(8): + for rs2_idx in range(8): + rd = COMPRESSED_REGS[rd_idx] + rs2 = COMPRESSED_REGS[rs2_idx] + test_cases.append(f"{mnemonic} {rd}, {rs2}") + elif mnemonic == "c.j": + # c.j imm[11:1] + for i in range(10): + label = f"label_{i}" + test_cases.append(f"{mnemonic} {label}") + test_cases.append(f"{label}:") + elif mnemonic == "c.beqz" or mnemonic == "c.bnez": + # c.beqz/c.bnez rs1', imm[8:1] + for rs1_idx in range(8): + rs1 = COMPRESSED_REGS[rs1_idx] + for i in range(10): + label = f"label_{i}" + test_cases.append(f"{mnemonic} {rs1}, {label}") + test_cases.append(f"{label}:") + elif mnemonic == "c.slli": + # c.slli rd, uimm[5:0] + for rd_idx in [1, 5, 10, 15, 20, 25, 31]: # rd != 0 + rd = REGISTERS[rd_idx] + for shamt in [0, 1, 2, 4, 8, 16, 31]: + test_cases.append(f"{mnemonic} {rd}, #{shamt}") + elif mnemonic == "c.lwsp": + # c.lwsp rd, uimm[7:2](sp) + for rd_idx in [1, 5, 10, 15, 20, 25, 31]: # rd != 0 + rd = REGISTERS[rd_idx] + for imm in [0, 4, 8, 16, 32, 64, 128, 252]: + test_cases.append(f"{mnemonic} {rd}, #{imm}(sp)") + elif mnemonic == "c.jr" or mnemonic == "c.jalr": + # c.jr/c.jalr rs1 + for rs1_idx in [1, 5, 10, 15, 20, 25, 31]: # rs1 != 0 + rs1 = REGISTERS[rs1_idx] + test_cases.append(f"{mnemonic} {rs1}") + elif mnemonic == "c.add": + # c.add rd, rs2 + for rd_idx in [1, 5, 10, 15, 20, 25, 31]: # rd != 0 + for rs2_idx in [1, 5, 10, 15, 20, 25, 31]: # rs2 != 0 + rd = REGISTERS[rd_idx] + rs2 = REGISTERS[rs2_idx] + test_cases.append(f"{mnemonic} {rd}, {rs2}") + elif mnemonic == "c.mv": + # c.mv rd, rs2 + for rd_idx in [1, 5, 10, 15, 20, 25, 31]: # rd != 0 + for rs2_idx in [1, 5, 10, 15, 20, 25, 31]: # rs2 != 0 + rd = REGISTERS[rd_idx] + rs2 = REGISTERS[rs2_idx] + test_cases.append(f"{mnemonic} {rd}, {rs2}") + elif mnemonic == "c.swsp": + # c.swsp rs2, uimm[7:2](sp) + for rs2_idx in [1, 5, 10, 15, 20, 25, 31]: # rs2 != 0 + rs2 = REGISTERS[rs2_idx] + for imm in [0, 4, 8, 16, 32, 64, 128, 252]: + test_cases.append(f"{mnemonic} {rs2}, #{imm}(sp)") + elif mnemonic == "c.addi": + # c.addi rd, imm[5:0] + for rd_idx in [1, 5, 10, 15, 20, 25, 31]: # rd != 0 + rd = REGISTERS[rd_idx] + for imm in [-32, -16, -8, -4, -2, -1, 0, 1, 2, 4, 8, 16, 31]: + test_cases.append(f"{mnemonic} {rd}, #{imm}") + + generate_test_file(extension_dir, mnemonic, test_cases) + +def main(): + """Generate all test files.""" + + # RV32I Base Instructions + rv32i_instructions = { + "R-type": ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and"], + "I-type": ["addi", "slti", "sltiu", "xori", "ori", "andi"], + "Shift-imm": ["slli", "srli", "srai"], + "U-type": ["lui", "auipc"], + "J-type": ["jal"], + "JALR": ["jalr"], + "B-type": ["beq", "bne", "blt", "bge", "bltu", "bgeu"], + "Load": ["lb", "lh", "lw", "lbu", "lhu"], + "Store": ["sb", "sh", "sw"], + "System": ["fence", "fence.i", "ecall", "ebreak"] + } + + for category, instructions in rv32i_instructions.items(): + for mnemonic in instructions: + if category == "R-type": + generate_r_type_tests("rv32i", mnemonic) + elif category == "I-type": + generate_i_type_tests("rv32i", mnemonic) + elif category == "Shift-imm": + generate_shift_imm_tests("rv32i", mnemonic) + elif category == "U-type": + generate_u_type_tests("rv32i", mnemonic) + elif category == "J-type": + generate_j_type_tests("rv32i", mnemonic) + elif category == "JALR": + generate_jalr_tests("rv32i", mnemonic) + elif category == "B-type": + generate_b_type_tests("rv32i", mnemonic) + elif category == "Load": + generate_load_tests("rv32i", mnemonic) + elif category == "Store": + generate_store_tests("rv32i", mnemonic) + elif category == "System": + generate_system_tests("rv32i", mnemonic) + + # M Extension + m_instructions = ["mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu"] + for mnemonic in m_instructions: + generate_r_type_tests("m-extension", mnemonic) + + # A Extension + a_instructions = ["lr.w", "sc.w", "amoadd.w", "amoswap.w", "amoand.w", "amoor.w", + "amoxor.w", "amomax.w", "amomaxu.w", "amomin.w", "amominu.w"] + for mnemonic in a_instructions: + generate_atomic_tests("a-extension", mnemonic) + + # Zicsr Extension + zicsr_instructions = ["csrrw", "csrrs", "csrrc", "csrrwi", "csrrsi", "csrrci"] + for mnemonic in zicsr_instructions: + generate_csr_tests("zicsr-extension", mnemonic) + + # F Extension + f_instructions = ["flw", "fsw", "fmadd.s", "fmsub.s", "fnmsub.s", "fnmadd.s", + "fadd.s", "fsub.s", "fmul.s", "fdiv.s", "fsqrt.s", + "fsgnj.s", "fsgnjn.s", "fsgnjx.s", "fmin.s", "fmax.s", + "feq.s", "flt.s", "fle.s", "fcvt.w.s", "fcvt.wu.s", + "fcvt.s.w", "fcvt.s.wu", "fmv.x.w", "fmv.w.x", "fclass.s"] + for mnemonic in f_instructions: + generate_float_tests("f-extension", mnemonic) + + # D Extension + d_instructions = ["fld", "fsd", "fmadd.d", "fmsub.d", "fnmsub.d", "fnmadd.d", + "fadd.d", "fsub.d", "fmul.d", "fdiv.d", "fsqrt.d", + "fsgnj.d", "fsgnjn.d", "fsgnjx.d", "fmin.d", "fmax.d", + "fcvt.s.d", "fcvt.d.s", "feq.d", "flt.d", "fle.d", + "fcvt.w.d", "fcvt.wu.d", "fcvt.d.w", "fcvt.d.wu", "fclass.d"] + for mnemonic in d_instructions: + generate_float_tests("d-extension", mnemonic) + + # C Extension + c_instructions = ["c.addi4spn", "c.lw", "c.sw", "c.nop", "c.addi", "c.jalr", + "c.li", "c.addi16sp", "c.lui", "c.srli", "c.srai", "c.andi", + "c.sub", "c.xor", "c.or", "c.and", "c.j", "c.beqz", "c.bnez", + "c.slli", "c.lwsp", "c.jr", "c.add", "c.mv", "c.swsp", "c.ebreak"] + for mnemonic in c_instructions: + generate_compressed_tests("c-extension", mnemonic) + + print("Generated all test files!") + +if __name__ == "__main__": + main() + diff --git a/tests/riscv/m-extension/div.asm b/tests/riscv/m-extension/div.asm new file mode 100644 index 0000000..0cedfa5 --- /dev/null +++ b/tests/riscv/m-extension/div.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +div zero, zero, zero +div zero, zero, ra +div zero, zero, t0 +div zero, zero, a0 +div zero, zero, a5 +div zero, zero, s4 +div zero, zero, s9 +div zero, zero, t6 +div zero, ra, zero +div zero, ra, ra +div zero, ra, t0 +div zero, ra, a0 +div zero, ra, a5 +div zero, ra, s4 +div zero, ra, s9 +div zero, ra, t6 +div zero, t0, zero +div zero, t0, ra +div zero, t0, t0 +div zero, t0, a0 +div zero, t0, a5 +div zero, t0, s4 +div zero, t0, s9 +div zero, t0, t6 +div zero, a0, zero +div zero, a0, ra +div zero, a0, t0 +div zero, a0, a0 +div zero, a0, a5 +div zero, a0, s4 +div zero, a0, s9 +div zero, a0, t6 +div zero, a5, zero +div zero, a5, ra +div zero, a5, t0 +div zero, a5, a0 +div zero, a5, a5 +div zero, a5, s4 +div zero, a5, s9 +div zero, a5, t6 +div zero, s4, zero +div zero, s4, ra +div zero, s4, t0 +div zero, s4, a0 +div zero, s4, a5 +div zero, s4, s4 +div zero, s4, s9 +div zero, s4, t6 +div zero, s9, zero +div zero, s9, ra +div zero, s9, t0 +div zero, s9, a0 +div zero, s9, a5 +div zero, s9, s4 +div zero, s9, s9 +div zero, s9, t6 +div zero, t6, zero +div zero, t6, ra +div zero, t6, t0 +div zero, t6, a0 +div zero, t6, a5 +div zero, t6, s4 +div zero, t6, s9 +div zero, t6, t6 +div ra, zero, zero +div ra, zero, ra +div ra, zero, t0 +div ra, zero, a0 +div ra, zero, a5 +div ra, zero, s4 +div ra, zero, s9 +div ra, zero, t6 +div ra, ra, zero +div ra, ra, ra +div ra, ra, t0 +div ra, ra, a0 +div ra, ra, a5 +div ra, ra, s4 +div ra, ra, s9 +div ra, ra, t6 +div ra, t0, zero +div ra, t0, ra +div ra, t0, t0 +div ra, t0, a0 +div ra, t0, a5 +div ra, t0, s4 +div ra, t0, s9 +div ra, t0, t6 +div ra, a0, zero +div ra, a0, ra +div ra, a0, t0 +div ra, a0, a0 +div ra, a0, a5 +div ra, a0, s4 +div ra, a0, s9 +div ra, a0, t6 +div ra, a5, zero +div ra, a5, ra +div ra, a5, t0 +div ra, a5, a0 +div ra, a5, a5 +div ra, a5, s4 +div ra, a5, s9 +div ra, a5, t6 +div ra, s4, zero +div ra, s4, ra +div ra, s4, t0 +div ra, s4, a0 +div ra, s4, a5 +div ra, s4, s4 +div ra, s4, s9 +div ra, s4, t6 +div ra, s9, zero +div ra, s9, ra +div ra, s9, t0 +div ra, s9, a0 +div ra, s9, a5 +div ra, s9, s4 +div ra, s9, s9 +div ra, s9, t6 +div ra, t6, zero +div ra, t6, ra +div ra, t6, t0 +div ra, t6, a0 +div ra, t6, a5 +div ra, t6, s4 +div ra, t6, s9 +div ra, t6, t6 +div t0, zero, zero +div t0, zero, ra +div t0, zero, t0 +div t0, zero, a0 +div t0, zero, a5 +div t0, zero, s4 +div t0, zero, s9 +div t0, zero, t6 +div t0, ra, zero +div t0, ra, ra +div t0, ra, t0 +div t0, ra, a0 +div t0, ra, a5 +div t0, ra, s4 +div t0, ra, s9 +div t0, ra, t6 +div t0, t0, zero +div t0, t0, ra +div t0, t0, t0 +div t0, t0, a0 +div t0, t0, a5 +div t0, t0, s4 +div t0, t0, s9 +div t0, t0, t6 +div t0, a0, zero +div t0, a0, ra +div t0, a0, t0 +div t0, a0, a0 +div t0, a0, a5 +div t0, a0, s4 +div t0, a0, s9 +div t0, a0, t6 +div t0, a5, zero +div t0, a5, ra +div t0, a5, t0 +div t0, a5, a0 +div t0, a5, a5 +div t0, a5, s4 +div t0, a5, s9 +div t0, a5, t6 +div t0, s4, zero +div t0, s4, ra +div t0, s4, t0 +div t0, s4, a0 +div t0, s4, a5 +div t0, s4, s4 +div t0, s4, s9 +div t0, s4, t6 +div t0, s9, zero +div t0, s9, ra +div t0, s9, t0 +div t0, s9, a0 +div t0, s9, a5 +div t0, s9, s4 +div t0, s9, s9 +div t0, s9, t6 +div t0, t6, zero +div t0, t6, ra +div t0, t6, t0 +div t0, t6, a0 +div t0, t6, a5 +div t0, t6, s4 +div t0, t6, s9 +div t0, t6, t6 +div a0, zero, zero +div a0, zero, ra +div a0, zero, t0 +div a0, zero, a0 +div a0, zero, a5 +div a0, zero, s4 +div a0, zero, s9 +div a0, zero, t6 +div a0, ra, zero +div a0, ra, ra +div a0, ra, t0 +div a0, ra, a0 +div a0, ra, a5 +div a0, ra, s4 +div a0, ra, s9 +div a0, ra, t6 +div a0, t0, zero +div a0, t0, ra +div a0, t0, t0 +div a0, t0, a0 +div a0, t0, a5 +div a0, t0, s4 +div a0, t0, s9 +div a0, t0, t6 +div a0, a0, zero +div a0, a0, ra +div a0, a0, t0 +div a0, a0, a0 +div a0, a0, a5 +div a0, a0, s4 +div a0, a0, s9 +div a0, a0, t6 +div a0, a5, zero +div a0, a5, ra +div a0, a5, t0 +div a0, a5, a0 +div a0, a5, a5 +div a0, a5, s4 +div a0, a5, s9 +div a0, a5, t6 +div a0, s4, zero +div a0, s4, ra +div a0, s4, t0 +div a0, s4, a0 +div a0, s4, a5 +div a0, s4, s4 +div a0, s4, s9 +div a0, s4, t6 +div a0, s9, zero +div a0, s9, ra +div a0, s9, t0 +div a0, s9, a0 +div a0, s9, a5 +div a0, s9, s4 +div a0, s9, s9 +div a0, s9, t6 +div a0, t6, zero +div a0, t6, ra +div a0, t6, t0 +div a0, t6, a0 +div a0, t6, a5 +div a0, t6, s4 +div a0, t6, s9 +div a0, t6, t6 +div a5, zero, zero +div a5, zero, ra +div a5, zero, t0 +div a5, zero, a0 +div a5, zero, a5 +div a5, zero, s4 +div a5, zero, s9 +div a5, zero, t6 +div a5, ra, zero +div a5, ra, ra +div a5, ra, t0 +div a5, ra, a0 +div a5, ra, a5 +div a5, ra, s4 +div a5, ra, s9 +div a5, ra, t6 +div a5, t0, zero +div a5, t0, ra +div a5, t0, t0 +div a5, t0, a0 +div a5, t0, a5 +div a5, t0, s4 +div a5, t0, s9 +div a5, t0, t6 +div a5, a0, zero +div a5, a0, ra +div a5, a0, t0 +div a5, a0, a0 +div a5, a0, a5 +div a5, a0, s4 +div a5, a0, s9 +div a5, a0, t6 +div a5, a5, zero +div a5, a5, ra +div a5, a5, t0 +div a5, a5, a0 +div a5, a5, a5 +div a5, a5, s4 +div a5, a5, s9 +div a5, a5, t6 +div a5, s4, zero +div a5, s4, ra +div a5, s4, t0 +div a5, s4, a0 +div a5, s4, a5 +div a5, s4, s4 +div a5, s4, s9 +div a5, s4, t6 +div a5, s9, zero +div a5, s9, ra +div a5, s9, t0 +div a5, s9, a0 +div a5, s9, a5 +div a5, s9, s4 +div a5, s9, s9 +div a5, s9, t6 +div a5, t6, zero +div a5, t6, ra +div a5, t6, t0 +div a5, t6, a0 +div a5, t6, a5 +div a5, t6, s4 +div a5, t6, s9 +div a5, t6, t6 +div s4, zero, zero +div s4, zero, ra +div s4, zero, t0 +div s4, zero, a0 +div s4, zero, a5 +div s4, zero, s4 +div s4, zero, s9 +div s4, zero, t6 +div s4, ra, zero +div s4, ra, ra +div s4, ra, t0 +div s4, ra, a0 +div s4, ra, a5 +div s4, ra, s4 +div s4, ra, s9 +div s4, ra, t6 +div s4, t0, zero +div s4, t0, ra +div s4, t0, t0 +div s4, t0, a0 +div s4, t0, a5 +div s4, t0, s4 +div s4, t0, s9 +div s4, t0, t6 +div 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a5 +div s9, t0, s4 +div s9, t0, s9 +div s9, t0, t6 +div s9, a0, zero +div s9, a0, ra +div s9, a0, t0 +div s9, a0, a0 +div s9, a0, a5 +div s9, a0, s4 +div s9, a0, s9 +div s9, a0, t6 +div s9, a5, zero +div s9, a5, ra +div s9, a5, t0 +div s9, a5, a0 +div s9, a5, a5 +div s9, a5, s4 +div s9, a5, s9 +div s9, a5, t6 +div s9, s4, zero +div s9, s4, ra +div s9, s4, t0 +div s9, s4, a0 +div s9, s4, a5 +div s9, s4, s4 +div s9, s4, s9 +div s9, s4, t6 +div s9, s9, zero +div s9, s9, ra +div s9, s9, t0 +div s9, s9, a0 +div s9, s9, a5 +div s9, s9, s4 +div s9, s9, s9 +div s9, s9, t6 +div s9, t6, zero +div s9, t6, ra +div s9, t6, t0 +div s9, t6, a0 +div s9, t6, a5 +div s9, t6, s4 +div s9, t6, s9 +div s9, t6, t6 +div t6, zero, zero +div t6, zero, ra +div t6, zero, t0 +div t6, zero, a0 +div t6, zero, a5 +div t6, zero, s4 +div t6, zero, s9 +div t6, zero, t6 +div t6, ra, zero +div t6, ra, ra +div t6, ra, t0 +div t6, ra, a0 +div t6, ra, a5 +div t6, ra, s4 +div t6, ra, s9 +div t6, ra, t6 +div t6, t0, zero +div t6, t0, ra +div t6, t0, t0 +div t6, t0, a0 +div t6, t0, a5 +div t6, t0, s4 +div t6, t0, s9 +div t6, t0, t6 +div t6, a0, zero +div t6, a0, ra +div t6, a0, t0 +div t6, a0, a0 +div t6, a0, a5 +div t6, a0, s4 +div t6, a0, s9 +div t6, a0, t6 +div t6, a5, zero +div t6, a5, ra +div t6, a5, t0 +div t6, a5, a0 +div t6, a5, a5 +div t6, a5, s4 +div t6, a5, s9 +div t6, a5, t6 +div t6, s4, zero +div t6, s4, ra +div t6, s4, t0 +div t6, s4, a0 +div t6, s4, a5 +div t6, s4, s4 +div t6, s4, s9 +div t6, s4, t6 +div t6, s9, zero +div t6, s9, ra +div t6, s9, t0 +div t6, s9, a0 +div t6, s9, a5 +div t6, s9, s4 +div t6, s9, s9 +div t6, s9, t6 +div t6, t6, zero +div t6, t6, ra +div t6, t6, t0 +div t6, t6, a0 +div t6, t6, a5 +div t6, t6, s4 +div t6, t6, s9 +div t6, t6, t6 + diff --git a/tests/riscv/m-extension/div.bin b/tests/riscv/m-extension/div.bin new file mode 100644 index 0000000000000000000000000000000000000000..d206712ea5aa9e84e330620c69f6ef4e56d0345c GIT binary patch literal 2048 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zero, a0 +mulh zero, zero, a5 +mulh zero, zero, s4 +mulh zero, zero, s9 +mulh zero, zero, t6 +mulh zero, ra, zero +mulh zero, ra, ra +mulh zero, ra, t0 +mulh zero, ra, a0 +mulh zero, ra, a5 +mulh zero, ra, s4 +mulh zero, ra, s9 +mulh zero, ra, t6 +mulh zero, t0, zero +mulh zero, t0, ra +mulh zero, t0, t0 +mulh zero, t0, a0 +mulh zero, t0, a5 +mulh zero, t0, s4 +mulh zero, t0, s9 +mulh zero, t0, t6 +mulh zero, a0, zero +mulh zero, a0, ra +mulh zero, a0, t0 +mulh zero, a0, a0 +mulh zero, a0, a5 +mulh zero, a0, s4 +mulh zero, a0, s9 +mulh zero, a0, t6 +mulh zero, a5, zero +mulh zero, a5, ra +mulh zero, a5, t0 +mulh zero, a5, a0 +mulh zero, a5, a5 +mulh zero, a5, s4 +mulh zero, a5, s9 +mulh zero, a5, t6 +mulh zero, s4, zero +mulh zero, s4, ra +mulh zero, s4, t0 +mulh zero, s4, a0 +mulh zero, s4, a5 +mulh zero, s4, s4 +mulh zero, s4, s9 +mulh zero, s4, t6 +mulh zero, s9, zero +mulh zero, s9, ra +mulh zero, s9, t0 +mulh zero, s9, a0 +mulh zero, s9, a5 +mulh zero, s9, s4 +mulh zero, s9, s9 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+mulh t0, s4, zero +mulh t0, s4, ra +mulh t0, s4, t0 +mulh t0, s4, a0 +mulh t0, s4, a5 +mulh t0, s4, s4 +mulh t0, s4, s9 +mulh t0, s4, t6 +mulh t0, s9, zero +mulh t0, s9, ra +mulh t0, s9, t0 +mulh t0, s9, a0 +mulh t0, s9, a5 +mulh t0, s9, s4 +mulh t0, s9, s9 +mulh t0, s9, t6 +mulh t0, t6, zero +mulh t0, t6, ra +mulh t0, t6, t0 +mulh t0, t6, a0 +mulh t0, t6, a5 +mulh t0, t6, s4 +mulh t0, t6, s9 +mulh t0, t6, t6 +mulh a0, zero, zero +mulh a0, zero, ra +mulh a0, zero, t0 +mulh a0, zero, a0 +mulh a0, zero, a5 +mulh a0, zero, s4 +mulh a0, zero, s9 +mulh a0, zero, t6 +mulh a0, ra, zero +mulh a0, ra, ra +mulh a0, ra, t0 +mulh a0, ra, a0 +mulh a0, ra, a5 +mulh a0, ra, s4 +mulh a0, ra, s9 +mulh a0, ra, t6 +mulh a0, t0, zero +mulh a0, t0, ra +mulh a0, t0, t0 +mulh a0, t0, a0 +mulh a0, t0, a5 +mulh a0, t0, s4 +mulh a0, t0, s9 +mulh a0, t0, t6 +mulh a0, a0, zero +mulh a0, a0, ra +mulh a0, a0, t0 +mulh a0, a0, a0 +mulh a0, a0, a5 +mulh a0, a0, s4 +mulh a0, a0, s9 +mulh a0, a0, t6 +mulh a0, a5, zero +mulh a0, a5, ra +mulh a0, a5, t0 +mulh a0, a5, a0 +mulh a0, a5, a5 +mulh a0, a5, s4 +mulh a0, a5, s9 +mulh a0, a5, t6 +mulh a0, s4, zero +mulh a0, s4, ra +mulh a0, s4, t0 +mulh a0, s4, a0 +mulh a0, s4, a5 +mulh a0, s4, s4 +mulh a0, s4, s9 +mulh a0, s4, t6 +mulh a0, s9, zero +mulh a0, s9, ra +mulh a0, s9, t0 +mulh a0, s9, a0 +mulh a0, s9, a5 +mulh a0, s9, s4 +mulh a0, s9, s9 +mulh a0, s9, t6 +mulh a0, t6, zero +mulh a0, t6, ra +mulh a0, t6, t0 +mulh a0, t6, a0 +mulh a0, t6, a5 +mulh a0, t6, s4 +mulh a0, t6, s9 +mulh a0, t6, t6 +mulh a5, zero, zero +mulh a5, zero, ra +mulh a5, zero, t0 +mulh a5, zero, a0 +mulh a5, zero, a5 +mulh a5, zero, s4 +mulh a5, zero, s9 +mulh a5, zero, t6 +mulh a5, ra, zero +mulh a5, ra, ra +mulh a5, ra, t0 +mulh a5, ra, a0 +mulh a5, ra, a5 +mulh a5, ra, s4 +mulh a5, ra, s9 +mulh a5, ra, t6 +mulh a5, t0, zero +mulh a5, t0, ra +mulh a5, t0, t0 +mulh a5, t0, a0 +mulh a5, t0, a5 +mulh a5, t0, s4 +mulh a5, t0, s9 +mulh a5, t0, t6 +mulh a5, a0, zero +mulh a5, a0, ra +mulh a5, a0, t0 +mulh a5, a0, a0 +mulh a5, a0, a5 +mulh a5, a0, s4 +mulh a5, a0, s9 +mulh a5, a0, t6 +mulh a5, a5, zero +mulh a5, a5, ra +mulh a5, a5, t0 +mulh a5, a5, a0 +mulh a5, a5, a5 +mulh a5, a5, s4 +mulh a5, a5, s9 +mulh a5, a5, t6 +mulh a5, s4, zero +mulh a5, s4, ra +mulh a5, s4, t0 +mulh a5, s4, a0 +mulh a5, s4, a5 +mulh a5, s4, s4 +mulh a5, s4, s9 +mulh a5, s4, t6 +mulh a5, s9, zero +mulh a5, s9, ra +mulh a5, s9, t0 +mulh a5, s9, a0 +mulh a5, s9, a5 +mulh a5, s9, s4 +mulh a5, s9, s9 +mulh a5, s9, t6 +mulh a5, t6, zero +mulh a5, t6, ra +mulh a5, t6, t0 +mulh a5, t6, a0 +mulh a5, t6, a5 +mulh a5, t6, s4 +mulh a5, t6, s9 +mulh a5, t6, t6 +mulh s4, zero, zero +mulh s4, zero, ra +mulh s4, zero, t0 +mulh s4, zero, a0 +mulh s4, zero, a5 +mulh s4, zero, s4 +mulh s4, zero, s9 +mulh s4, zero, t6 +mulh s4, ra, zero +mulh s4, ra, ra +mulh s4, ra, t0 +mulh s4, ra, a0 +mulh s4, ra, a5 +mulh s4, ra, s4 +mulh s4, ra, s9 +mulh s4, ra, t6 +mulh s4, t0, zero +mulh s4, t0, ra +mulh s4, t0, t0 +mulh s4, t0, a0 +mulh s4, t0, a5 +mulh s4, t0, s4 +mulh s4, t0, s9 +mulh s4, t0, t6 +mulh s4, a0, zero +mulh s4, a0, ra +mulh s4, a0, t0 +mulh s4, a0, a0 +mulh s4, a0, a5 +mulh s4, a0, s4 +mulh s4, a0, s9 +mulh s4, a0, t6 +mulh s4, a5, zero +mulh s4, a5, ra +mulh s4, a5, t0 +mulh s4, a5, a0 +mulh s4, a5, a5 +mulh s4, a5, s4 +mulh s4, a5, s9 +mulh s4, a5, t6 +mulh s4, s4, zero +mulh s4, s4, ra +mulh s4, s4, t0 +mulh s4, s4, a0 +mulh s4, s4, a5 +mulh s4, s4, s4 +mulh s4, s4, s9 +mulh s4, s4, t6 +mulh s4, s9, zero +mulh s4, s9, ra +mulh s4, s9, t0 +mulh s4, s9, a0 +mulh s4, s9, a5 +mulh s4, s9, s4 +mulh s4, s9, s9 +mulh s4, s9, t6 +mulh s4, t6, zero +mulh s4, t6, ra +mulh s4, t6, t0 +mulh s4, t6, a0 +mulh s4, t6, a5 +mulh s4, t6, s4 +mulh s4, t6, s9 +mulh s4, t6, t6 +mulh s9, zero, zero +mulh s9, zero, ra +mulh s9, zero, t0 +mulh s9, zero, a0 +mulh s9, zero, a5 +mulh s9, zero, s4 +mulh s9, zero, s9 +mulh s9, zero, t6 +mulh s9, ra, zero +mulh s9, ra, ra +mulh s9, ra, t0 +mulh s9, ra, a0 +mulh s9, ra, a5 +mulh s9, ra, s4 +mulh s9, ra, s9 +mulh s9, ra, t6 +mulh s9, t0, zero +mulh s9, t0, ra +mulh s9, t0, t0 +mulh s9, t0, a0 +mulh s9, t0, a5 +mulh s9, t0, s4 +mulh s9, t0, s9 +mulh s9, t0, t6 +mulh s9, a0, zero +mulh s9, a0, ra +mulh s9, a0, t0 +mulh s9, a0, a0 +mulh s9, a0, a5 +mulh s9, a0, s4 +mulh s9, a0, s9 +mulh s9, a0, t6 +mulh s9, a5, zero +mulh s9, a5, ra +mulh s9, a5, t0 +mulh s9, a5, a0 +mulh s9, a5, a5 +mulh s9, a5, s4 +mulh s9, a5, s9 +mulh s9, a5, t6 +mulh s9, s4, zero +mulh s9, s4, ra +mulh s9, s4, t0 +mulh s9, s4, a0 +mulh s9, s4, a5 +mulh s9, s4, s4 +mulh s9, s4, s9 +mulh s9, s4, t6 +mulh s9, s9, zero +mulh s9, s9, ra +mulh s9, s9, t0 +mulh s9, s9, a0 +mulh s9, s9, a5 +mulh s9, s9, s4 +mulh s9, s9, s9 +mulh s9, s9, t6 +mulh s9, t6, zero +mulh s9, t6, ra +mulh s9, t6, t0 +mulh s9, t6, a0 +mulh s9, t6, a5 +mulh s9, t6, s4 +mulh s9, t6, s9 +mulh s9, t6, t6 +mulh t6, zero, zero +mulh t6, zero, ra +mulh t6, zero, t0 +mulh t6, zero, a0 +mulh t6, zero, a5 +mulh t6, zero, s4 +mulh t6, zero, s9 +mulh t6, zero, t6 +mulh t6, ra, zero +mulh t6, ra, ra +mulh t6, ra, t0 +mulh t6, ra, a0 +mulh t6, ra, a5 +mulh t6, ra, s4 +mulh t6, ra, s9 +mulh t6, ra, t6 +mulh t6, t0, zero +mulh t6, t0, ra +mulh t6, t0, t0 +mulh t6, t0, a0 +mulh t6, t0, a5 +mulh t6, t0, s4 +mulh t6, t0, s9 +mulh t6, t0, t6 +mulh t6, a0, zero +mulh t6, a0, ra +mulh t6, a0, t0 +mulh t6, a0, a0 +mulh t6, a0, a5 +mulh t6, a0, s4 +mulh t6, a0, s9 +mulh t6, a0, t6 +mulh t6, a5, zero +mulh t6, a5, ra +mulh t6, a5, t0 +mulh t6, a5, a0 +mulh t6, a5, a5 +mulh t6, a5, s4 +mulh t6, a5, s9 +mulh t6, a5, t6 +mulh t6, s4, zero +mulh t6, s4, ra +mulh t6, s4, t0 +mulh t6, s4, a0 +mulh t6, s4, a5 +mulh t6, s4, s4 +mulh t6, s4, s9 +mulh t6, s4, t6 +mulh t6, s9, zero +mulh t6, s9, ra +mulh t6, s9, t0 +mulh t6, s9, a0 +mulh t6, s9, a5 +mulh t6, s9, s4 +mulh t6, s9, s9 +mulh t6, s9, t6 +mulh t6, t6, zero +mulh t6, t6, ra +mulh t6, t6, t0 +mulh t6, t6, a0 +mulh t6, t6, a5 +mulh t6, t6, s4 +mulh t6, t6, s9 +mulh t6, t6, t6 diff --git a/tests/riscv/m-extension/mulhsu.asm b/tests/riscv/m-extension/mulhsu.asm new file mode 100644 index 0000000..c52a0db --- /dev/null +++ b/tests/riscv/m-extension/mulhsu.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +mulhsu zero, zero, zero +mulhsu zero, zero, ra +mulhsu zero, zero, t0 +mulhsu zero, zero, a0 +mulhsu zero, zero, a5 +mulhsu zero, zero, s4 +mulhsu zero, zero, s9 +mulhsu zero, zero, t6 +mulhsu zero, ra, zero +mulhsu zero, ra, ra +mulhsu zero, ra, t0 +mulhsu zero, ra, a0 +mulhsu zero, ra, a5 +mulhsu zero, ra, s4 +mulhsu zero, ra, s9 +mulhsu zero, ra, t6 +mulhsu zero, t0, zero +mulhsu zero, t0, ra +mulhsu zero, t0, t0 +mulhsu zero, t0, a0 +mulhsu zero, t0, a5 +mulhsu zero, t0, s4 +mulhsu zero, t0, s9 +mulhsu zero, t0, t6 +mulhsu zero, a0, zero +mulhsu zero, a0, ra +mulhsu zero, a0, t0 +mulhsu zero, a0, a0 +mulhsu zero, a0, a5 +mulhsu zero, a0, s4 +mulhsu zero, a0, s9 +mulhsu zero, a0, t6 +mulhsu zero, a5, zero +mulhsu zero, a5, ra +mulhsu zero, a5, t0 +mulhsu zero, a5, a0 +mulhsu zero, a5, a5 +mulhsu zero, a5, s4 +mulhsu zero, a5, s9 +mulhsu zero, a5, t6 +mulhsu zero, s4, zero +mulhsu zero, s4, ra +mulhsu zero, s4, t0 +mulhsu zero, s4, a0 +mulhsu zero, s4, a5 +mulhsu zero, s4, s4 +mulhsu zero, s4, s9 +mulhsu zero, s4, t6 +mulhsu zero, s9, zero +mulhsu zero, s9, ra +mulhsu zero, s9, t0 +mulhsu zero, s9, a0 +mulhsu zero, s9, a5 +mulhsu zero, s9, s4 +mulhsu zero, s9, s9 +mulhsu zero, s9, t6 +mulhsu zero, t6, zero +mulhsu zero, t6, ra +mulhsu zero, t6, t0 +mulhsu zero, t6, a0 +mulhsu zero, t6, a5 +mulhsu zero, t6, s4 +mulhsu zero, t6, s9 +mulhsu zero, t6, t6 +mulhsu ra, zero, zero +mulhsu ra, zero, ra +mulhsu ra, zero, t0 +mulhsu ra, zero, a0 +mulhsu ra, zero, a5 +mulhsu ra, zero, s4 +mulhsu ra, zero, s9 +mulhsu ra, zero, t6 +mulhsu ra, ra, zero +mulhsu ra, ra, ra +mulhsu ra, ra, t0 +mulhsu ra, ra, a0 +mulhsu ra, ra, a5 +mulhsu ra, ra, s4 +mulhsu ra, ra, s9 +mulhsu ra, ra, t6 +mulhsu ra, t0, zero +mulhsu ra, t0, ra +mulhsu ra, t0, t0 +mulhsu ra, t0, a0 +mulhsu ra, t0, a5 +mulhsu ra, t0, s4 +mulhsu ra, t0, s9 +mulhsu ra, t0, t6 +mulhsu ra, a0, zero +mulhsu ra, a0, ra +mulhsu ra, a0, t0 +mulhsu ra, a0, a0 +mulhsu ra, a0, a5 +mulhsu ra, a0, s4 +mulhsu ra, a0, s9 +mulhsu ra, a0, t6 +mulhsu ra, a5, zero +mulhsu ra, a5, ra +mulhsu ra, a5, t0 +mulhsu ra, a5, a0 +mulhsu ra, a5, a5 +mulhsu ra, a5, s4 +mulhsu ra, a5, s9 +mulhsu ra, a5, t6 +mulhsu ra, s4, zero +mulhsu ra, s4, ra +mulhsu ra, s4, t0 +mulhsu ra, s4, a0 +mulhsu ra, s4, a5 +mulhsu ra, s4, s4 +mulhsu ra, s4, s9 +mulhsu ra, s4, t6 +mulhsu ra, s9, zero +mulhsu ra, s9, ra +mulhsu ra, s9, t0 +mulhsu ra, s9, a0 +mulhsu ra, s9, a5 +mulhsu ra, s9, s4 +mulhsu ra, s9, s9 +mulhsu ra, s9, t6 +mulhsu ra, t6, zero +mulhsu ra, t6, ra +mulhsu ra, t6, t0 +mulhsu ra, t6, a0 +mulhsu ra, t6, a5 +mulhsu ra, t6, s4 +mulhsu ra, t6, s9 +mulhsu ra, t6, t6 +mulhsu t0, zero, zero +mulhsu t0, zero, ra +mulhsu t0, zero, t0 +mulhsu t0, zero, a0 +mulhsu t0, zero, a5 +mulhsu t0, zero, s4 +mulhsu t0, zero, s9 +mulhsu t0, zero, t6 +mulhsu t0, ra, zero +mulhsu t0, ra, ra +mulhsu t0, ra, t0 +mulhsu t0, ra, a0 +mulhsu t0, ra, a5 +mulhsu t0, ra, s4 +mulhsu t0, ra, s9 +mulhsu t0, ra, t6 +mulhsu t0, t0, zero +mulhsu t0, t0, ra +mulhsu t0, t0, t0 +mulhsu t0, t0, a0 +mulhsu t0, t0, a5 +mulhsu t0, t0, s4 +mulhsu t0, t0, s9 +mulhsu t0, t0, t6 +mulhsu t0, a0, zero +mulhsu t0, a0, ra +mulhsu t0, a0, t0 +mulhsu t0, a0, a0 +mulhsu t0, a0, a5 +mulhsu t0, a0, s4 +mulhsu t0, a0, s9 +mulhsu t0, a0, t6 +mulhsu t0, a5, zero +mulhsu t0, a5, ra +mulhsu t0, a5, t0 +mulhsu t0, a5, a0 +mulhsu t0, a5, a5 +mulhsu t0, a5, s4 +mulhsu t0, a5, s9 +mulhsu t0, a5, t6 +mulhsu t0, s4, zero +mulhsu t0, s4, ra +mulhsu t0, s4, t0 +mulhsu t0, s4, a0 +mulhsu t0, s4, a5 +mulhsu t0, s4, s4 +mulhsu t0, s4, s9 +mulhsu t0, s4, t6 +mulhsu t0, s9, zero +mulhsu t0, s9, ra +mulhsu t0, s9, t0 +mulhsu t0, s9, a0 +mulhsu t0, s9, a5 +mulhsu t0, s9, s4 +mulhsu t0, s9, s9 +mulhsu t0, s9, t6 +mulhsu t0, t6, zero +mulhsu t0, t6, ra +mulhsu t0, t6, t0 +mulhsu t0, t6, a0 +mulhsu t0, t6, a5 +mulhsu t0, t6, s4 +mulhsu t0, t6, s9 +mulhsu t0, t6, t6 +mulhsu a0, zero, zero +mulhsu a0, zero, ra +mulhsu a0, zero, t0 +mulhsu a0, zero, a0 +mulhsu a0, zero, a5 +mulhsu a0, zero, s4 +mulhsu a0, zero, s9 +mulhsu a0, zero, t6 +mulhsu a0, ra, zero +mulhsu a0, ra, ra +mulhsu a0, ra, t0 +mulhsu a0, ra, a0 +mulhsu a0, ra, a5 +mulhsu a0, ra, s4 +mulhsu a0, ra, s9 +mulhsu a0, ra, t6 +mulhsu a0, t0, zero +mulhsu a0, t0, ra +mulhsu a0, t0, t0 +mulhsu a0, t0, a0 +mulhsu a0, t0, a5 +mulhsu a0, t0, s4 +mulhsu a0, t0, s9 +mulhsu a0, t0, t6 +mulhsu a0, a0, zero +mulhsu a0, a0, ra +mulhsu a0, a0, t0 +mulhsu a0, a0, a0 +mulhsu a0, a0, a5 +mulhsu a0, a0, s4 +mulhsu a0, a0, s9 +mulhsu a0, a0, t6 +mulhsu a0, a5, zero +mulhsu a0, a5, ra +mulhsu a0, a5, t0 +mulhsu a0, a5, a0 +mulhsu a0, a5, a5 +mulhsu a0, a5, s4 +mulhsu a0, a5, s9 +mulhsu a0, a5, t6 +mulhsu a0, s4, zero +mulhsu a0, s4, ra +mulhsu a0, s4, t0 +mulhsu a0, s4, a0 +mulhsu a0, s4, a5 +mulhsu a0, s4, s4 +mulhsu a0, s4, s9 +mulhsu a0, s4, t6 +mulhsu a0, s9, zero +mulhsu a0, s9, ra +mulhsu a0, s9, t0 +mulhsu a0, s9, a0 +mulhsu a0, s9, a5 +mulhsu a0, s9, s4 +mulhsu a0, s9, s9 +mulhsu a0, s9, t6 +mulhsu a0, t6, zero +mulhsu a0, t6, ra +mulhsu a0, t6, t0 +mulhsu a0, t6, a0 +mulhsu a0, t6, a5 +mulhsu a0, t6, s4 +mulhsu a0, t6, s9 +mulhsu a0, t6, t6 +mulhsu a5, zero, zero +mulhsu a5, zero, ra +mulhsu a5, zero, t0 +mulhsu a5, zero, a0 +mulhsu a5, zero, a5 +mulhsu a5, zero, s4 +mulhsu a5, zero, s9 +mulhsu a5, zero, t6 +mulhsu a5, ra, zero +mulhsu a5, ra, ra +mulhsu a5, ra, t0 +mulhsu a5, ra, a0 +mulhsu a5, ra, a5 +mulhsu a5, ra, s4 +mulhsu a5, ra, s9 +mulhsu a5, ra, t6 +mulhsu a5, t0, zero +mulhsu a5, t0, ra +mulhsu a5, t0, t0 +mulhsu a5, t0, a0 +mulhsu a5, t0, a5 +mulhsu a5, t0, s4 +mulhsu a5, t0, s9 +mulhsu a5, t0, t6 +mulhsu a5, a0, zero +mulhsu a5, a0, ra +mulhsu a5, a0, t0 +mulhsu a5, a0, a0 +mulhsu a5, a0, a5 +mulhsu a5, a0, s4 +mulhsu a5, a0, s9 +mulhsu a5, a0, t6 +mulhsu a5, a5, zero +mulhsu a5, a5, ra +mulhsu a5, a5, t0 +mulhsu a5, a5, a0 +mulhsu a5, a5, a5 +mulhsu a5, a5, s4 +mulhsu a5, a5, s9 +mulhsu a5, a5, t6 +mulhsu a5, s4, zero +mulhsu a5, s4, ra +mulhsu a5, s4, t0 +mulhsu a5, s4, a0 +mulhsu a5, s4, a5 +mulhsu a5, s4, s4 +mulhsu a5, s4, s9 +mulhsu a5, s4, t6 +mulhsu a5, s9, zero +mulhsu a5, s9, ra +mulhsu a5, s9, t0 +mulhsu a5, s9, a0 +mulhsu a5, s9, a5 +mulhsu a5, s9, s4 +mulhsu a5, s9, s9 +mulhsu a5, s9, t6 +mulhsu a5, t6, zero +mulhsu a5, t6, ra +mulhsu a5, t6, t0 +mulhsu a5, t6, a0 +mulhsu a5, t6, a5 +mulhsu a5, t6, s4 +mulhsu a5, t6, s9 +mulhsu a5, t6, t6 +mulhsu s4, zero, zero +mulhsu s4, zero, ra +mulhsu s4, zero, t0 +mulhsu s4, zero, a0 +mulhsu s4, zero, a5 +mulhsu s4, zero, s4 +mulhsu s4, zero, s9 +mulhsu s4, zero, t6 +mulhsu s4, ra, zero +mulhsu s4, ra, ra +mulhsu s4, ra, t0 +mulhsu s4, ra, a0 +mulhsu s4, ra, a5 +mulhsu s4, ra, s4 +mulhsu s4, ra, s9 +mulhsu s4, ra, t6 +mulhsu s4, t0, zero +mulhsu s4, t0, ra +mulhsu s4, t0, t0 +mulhsu s4, t0, a0 +mulhsu s4, t0, a5 +mulhsu s4, t0, s4 +mulhsu s4, t0, s9 +mulhsu s4, t0, t6 +mulhsu s4, a0, zero +mulhsu s4, a0, ra +mulhsu s4, a0, t0 +mulhsu s4, a0, a0 +mulhsu s4, a0, a5 +mulhsu s4, a0, s4 +mulhsu s4, a0, s9 +mulhsu s4, a0, t6 +mulhsu s4, a5, zero +mulhsu s4, a5, ra +mulhsu s4, a5, t0 +mulhsu s4, a5, a0 +mulhsu s4, a5, a5 +mulhsu s4, a5, s4 +mulhsu s4, a5, s9 +mulhsu s4, a5, t6 +mulhsu s4, s4, zero +mulhsu s4, s4, ra +mulhsu s4, s4, t0 +mulhsu s4, s4, a0 +mulhsu s4, s4, a5 +mulhsu s4, s4, s4 +mulhsu s4, s4, s9 +mulhsu s4, s4, t6 +mulhsu s4, s9, zero +mulhsu s4, s9, ra +mulhsu s4, s9, t0 +mulhsu s4, s9, a0 +mulhsu s4, s9, a5 +mulhsu s4, s9, s4 +mulhsu s4, s9, s9 +mulhsu s4, s9, t6 +mulhsu s4, t6, zero +mulhsu s4, t6, ra +mulhsu s4, t6, t0 +mulhsu s4, t6, a0 +mulhsu s4, t6, a5 +mulhsu s4, t6, s4 +mulhsu s4, t6, s9 +mulhsu s4, t6, t6 +mulhsu s9, zero, zero +mulhsu s9, zero, ra +mulhsu s9, zero, t0 +mulhsu s9, zero, a0 +mulhsu s9, zero, a5 +mulhsu s9, zero, s4 +mulhsu s9, zero, s9 +mulhsu s9, zero, t6 +mulhsu s9, ra, zero +mulhsu s9, ra, ra +mulhsu s9, ra, t0 +mulhsu s9, ra, a0 +mulhsu s9, ra, a5 +mulhsu s9, ra, s4 +mulhsu s9, ra, s9 +mulhsu s9, ra, t6 +mulhsu s9, t0, zero +mulhsu s9, t0, ra +mulhsu s9, t0, t0 +mulhsu s9, t0, a0 +mulhsu s9, t0, a5 +mulhsu s9, t0, s4 +mulhsu s9, t0, s9 +mulhsu s9, t0, t6 +mulhsu s9, a0, zero +mulhsu s9, a0, ra +mulhsu s9, a0, t0 +mulhsu s9, a0, a0 +mulhsu s9, a0, a5 +mulhsu s9, a0, s4 +mulhsu s9, a0, s9 +mulhsu s9, a0, t6 +mulhsu s9, a5, zero +mulhsu s9, a5, ra +mulhsu s9, a5, t0 +mulhsu s9, a5, a0 +mulhsu s9, a5, a5 +mulhsu s9, a5, s4 +mulhsu s9, a5, s9 +mulhsu s9, a5, t6 +mulhsu s9, s4, zero +mulhsu s9, s4, ra +mulhsu s9, s4, t0 +mulhsu s9, s4, a0 +mulhsu s9, s4, a5 +mulhsu s9, s4, s4 +mulhsu s9, s4, s9 +mulhsu s9, s4, t6 +mulhsu s9, s9, zero +mulhsu s9, s9, ra +mulhsu s9, s9, t0 +mulhsu s9, s9, a0 +mulhsu s9, s9, a5 +mulhsu s9, s9, s4 +mulhsu s9, s9, s9 +mulhsu s9, s9, t6 +mulhsu s9, t6, zero +mulhsu s9, t6, ra +mulhsu s9, t6, t0 +mulhsu s9, t6, a0 +mulhsu s9, t6, a5 +mulhsu s9, t6, s4 +mulhsu s9, t6, s9 +mulhsu s9, t6, t6 +mulhsu t6, zero, zero +mulhsu t6, zero, ra +mulhsu t6, zero, t0 +mulhsu t6, zero, a0 +mulhsu t6, zero, a5 +mulhsu t6, zero, s4 +mulhsu t6, zero, s9 +mulhsu t6, zero, t6 +mulhsu t6, ra, zero +mulhsu t6, ra, ra +mulhsu t6, ra, t0 +mulhsu t6, ra, a0 +mulhsu t6, ra, a5 +mulhsu t6, ra, s4 +mulhsu t6, ra, s9 +mulhsu t6, ra, t6 +mulhsu t6, t0, zero +mulhsu t6, t0, ra +mulhsu t6, t0, t0 +mulhsu t6, t0, a0 +mulhsu t6, t0, a5 +mulhsu t6, t0, s4 +mulhsu t6, t0, s9 +mulhsu t6, t0, t6 +mulhsu t6, a0, zero +mulhsu t6, a0, ra +mulhsu t6, a0, t0 +mulhsu t6, a0, a0 +mulhsu t6, a0, a5 +mulhsu t6, a0, s4 +mulhsu t6, a0, s9 +mulhsu t6, a0, t6 +mulhsu t6, a5, zero +mulhsu t6, a5, ra +mulhsu t6, a5, t0 +mulhsu t6, a5, a0 +mulhsu t6, a5, a5 +mulhsu t6, a5, s4 +mulhsu t6, a5, s9 +mulhsu t6, a5, t6 +mulhsu t6, s4, zero +mulhsu t6, s4, ra +mulhsu t6, s4, t0 +mulhsu t6, s4, a0 +mulhsu t6, s4, a5 +mulhsu t6, s4, s4 +mulhsu t6, s4, s9 +mulhsu t6, s4, t6 +mulhsu t6, s9, zero +mulhsu t6, s9, ra +mulhsu t6, s9, t0 +mulhsu t6, s9, a0 +mulhsu t6, s9, a5 +mulhsu t6, s9, s4 +mulhsu t6, s9, s9 +mulhsu t6, s9, t6 +mulhsu t6, t6, zero +mulhsu t6, t6, ra +mulhsu t6, t6, t0 +mulhsu t6, t6, a0 +mulhsu t6, t6, a5 +mulhsu t6, t6, s4 +mulhsu t6, t6, s9 +mulhsu t6, t6, t6 + diff --git a/tests/riscv/m-extension/mulhsu.bin b/tests/riscv/m-extension/mulhsu.bin new file mode 100644 index 0000000000000000000000000000000000000000..847929c72ac119c57608bd6f5abce787aa108eab GIT binary patch literal 2048 zcmWmCafg*n9LDj-9*IPcNF-XrZ5YG+v2P%eNc4zAqPO&jM51FD!x-j|`;BE;%UZV2 z`Qzf8-!*Q&zSqV1KW7)`|H^-Ilt1$FaB=>>{5f14^+)|tf7BoKNBvQMJoRV(Kb8+t z2o~B2#YVo%=7jl}G-+kgu}jPTsr!mb=4_f5*S$-|_GGcl z@$dNkmNWk!%Ll1)DX-kW$)#`H^SvkXQJP%IYxnPR<;{KXpUNlcaxHJ%f5^2r54?XS zpJm96ymkL6H{Lw-{<(aSDYx>@{g>RzBmZB>S6Ol=@7;e3{(vvw3-|)QfG^++_yWGF zullO5`l_$`s;{RWf5l(%SNs)!#b5DP`~iQ!AMgkK0e`?B@CW=Af5l(%SNs)!#b5DP z`~iQ!AMgkK0e`?B@CW=Af5l(%SNs)!#b5DP{1t!2U-4J`6@SHF@z=Y<#b)1|eQ)-? z+4pAOn|*Kgz1eruH+|DLebYC6)3;M^|IPlJ{Wtq>_TTKk*?+VD&Hgw0-|T<0|IPk4 z``_$;v;SuQ&HkJHH~Vk)-|WBHf3yG1{x|#I?0>WW&Hgw0-|T<0|7QQq{+sAK~$|?|`>E%@ z^WXXJ{CEC4|DFHNf8;;%ANh~`NB$%Kk^jhl=fCsc`S1L9{yYDj|IUBpKk^^>kNije zBma^A$baX*^WXXJ{CEC4|DFHNf9JpR-}&$Scm6y7o&U~%;y3Y|_)YvKeiOfm-^B0G z5B<;&{m>8n(2rBk|KNY{KlmT~5B>-Lga5>T;y>}9_)q*N{uBR+|H1#@fABx}AN&vg z2mgcr#DC&H@t^ol{3res|B3&>|KNY{KlmT~5B>-Lga5(*;D7Kx_#gZa{s;eq|IBaZ zH}jkM&HQG5GryVNsh|3(pZckv`l+9%p8v`J@Gtxe|H8lUFZ>06 z!C&wf`~`o(U+@?F3;)8u@Gtxe|H8lUFZ>06!C&wf`~`o(U+@?F3;)8u@Gtxe|H8lU VFZ>Jt!oTn@{0slWzwocS!(S=o@LvD` literal 0 HcmV?d00001 diff --git a/tests/riscv/m-extension/mulhsu.disasm b/tests/riscv/m-extension/mulhsu.disasm new file mode 100644 index 0000000..f55a08f --- /dev/null +++ b/tests/riscv/m-extension/mulhsu.disasm @@ -0,0 +1,512 @@ +mulhsu zero, zero, zero +mulhsu zero, zero, ra +mulhsu zero, zero, t0 +mulhsu zero, zero, a0 +mulhsu zero, zero, a5 +mulhsu zero, zero, s4 +mulhsu zero, zero, s9 +mulhsu zero, zero, t6 +mulhsu zero, ra, zero +mulhsu zero, ra, ra +mulhsu zero, ra, t0 +mulhsu zero, ra, a0 +mulhsu zero, ra, a5 +mulhsu zero, ra, s4 +mulhsu zero, ra, s9 +mulhsu zero, ra, t6 +mulhsu zero, t0, zero +mulhsu zero, t0, ra +mulhsu zero, t0, t0 +mulhsu zero, t0, a0 +mulhsu zero, t0, a5 +mulhsu zero, t0, s4 +mulhsu zero, t0, s9 +mulhsu zero, t0, t6 +mulhsu zero, a0, zero +mulhsu zero, a0, ra +mulhsu zero, a0, t0 +mulhsu zero, a0, a0 +mulhsu zero, a0, a5 +mulhsu zero, a0, s4 +mulhsu zero, a0, s9 +mulhsu zero, a0, t6 +mulhsu zero, a5, zero +mulhsu zero, a5, ra +mulhsu zero, a5, t0 +mulhsu zero, a5, a0 +mulhsu zero, a5, a5 +mulhsu zero, a5, s4 +mulhsu zero, a5, s9 +mulhsu zero, a5, t6 +mulhsu zero, s4, zero +mulhsu zero, s4, ra +mulhsu zero, s4, t0 +mulhsu zero, s4, a0 +mulhsu zero, s4, a5 +mulhsu zero, s4, s4 +mulhsu zero, s4, s9 +mulhsu zero, s4, t6 +mulhsu zero, s9, zero +mulhsu zero, s9, ra +mulhsu zero, s9, t0 +mulhsu zero, s9, a0 +mulhsu zero, s9, a5 +mulhsu zero, s9, s4 +mulhsu zero, s9, s9 +mulhsu zero, s9, t6 +mulhsu zero, t6, zero +mulhsu zero, t6, ra +mulhsu zero, t6, t0 +mulhsu zero, t6, a0 +mulhsu zero, t6, a5 +mulhsu zero, t6, s4 +mulhsu zero, t6, s9 +mulhsu zero, t6, t6 +mulhsu ra, zero, zero +mulhsu ra, zero, ra +mulhsu ra, zero, t0 +mulhsu ra, zero, a0 +mulhsu ra, zero, a5 +mulhsu ra, zero, s4 +mulhsu ra, zero, s9 +mulhsu ra, zero, t6 +mulhsu ra, ra, zero +mulhsu ra, ra, ra +mulhsu ra, ra, t0 +mulhsu ra, ra, a0 +mulhsu ra, ra, a5 +mulhsu ra, ra, s4 +mulhsu ra, ra, s9 +mulhsu ra, ra, t6 +mulhsu ra, t0, zero +mulhsu ra, t0, ra +mulhsu ra, t0, t0 +mulhsu ra, t0, a0 +mulhsu ra, t0, a5 +mulhsu ra, t0, s4 +mulhsu ra, t0, s9 +mulhsu ra, t0, t6 +mulhsu ra, a0, zero +mulhsu ra, a0, ra +mulhsu ra, a0, t0 +mulhsu ra, a0, a0 +mulhsu ra, a0, a5 +mulhsu ra, a0, s4 +mulhsu ra, a0, s9 +mulhsu ra, a0, t6 +mulhsu ra, a5, zero +mulhsu ra, a5, ra +mulhsu ra, a5, t0 +mulhsu ra, a5, a0 +mulhsu ra, a5, a5 +mulhsu ra, a5, s4 +mulhsu ra, a5, s9 +mulhsu ra, a5, t6 +mulhsu ra, s4, zero +mulhsu ra, s4, ra +mulhsu ra, s4, t0 +mulhsu ra, s4, a0 +mulhsu ra, s4, a5 +mulhsu ra, s4, s4 +mulhsu ra, s4, s9 +mulhsu ra, s4, t6 +mulhsu ra, s9, zero +mulhsu ra, s9, ra +mulhsu ra, s9, t0 +mulhsu ra, s9, a0 +mulhsu ra, s9, a5 +mulhsu ra, s9, s4 +mulhsu ra, s9, s9 +mulhsu ra, s9, t6 +mulhsu ra, t6, zero +mulhsu ra, t6, ra +mulhsu ra, t6, t0 +mulhsu ra, t6, a0 +mulhsu ra, t6, a5 +mulhsu ra, t6, s4 +mulhsu ra, t6, s9 +mulhsu ra, t6, t6 +mulhsu t0, zero, zero +mulhsu t0, zero, ra +mulhsu t0, zero, t0 +mulhsu t0, zero, a0 +mulhsu t0, zero, a5 +mulhsu t0, zero, s4 +mulhsu t0, zero, s9 +mulhsu t0, zero, t6 +mulhsu t0, ra, zero +mulhsu t0, ra, ra +mulhsu t0, ra, t0 +mulhsu t0, ra, a0 +mulhsu t0, ra, a5 +mulhsu t0, ra, s4 +mulhsu t0, ra, s9 +mulhsu t0, ra, t6 +mulhsu t0, t0, zero +mulhsu t0, t0, ra +mulhsu t0, t0, t0 +mulhsu t0, t0, a0 +mulhsu t0, t0, a5 +mulhsu t0, t0, s4 +mulhsu t0, t0, s9 +mulhsu t0, t0, t6 +mulhsu t0, a0, zero +mulhsu t0, a0, ra +mulhsu t0, a0, t0 +mulhsu t0, a0, a0 +mulhsu t0, a0, a5 +mulhsu t0, a0, s4 +mulhsu t0, a0, s9 +mulhsu t0, a0, t6 +mulhsu t0, a5, zero +mulhsu t0, a5, ra +mulhsu t0, a5, t0 +mulhsu t0, a5, a0 +mulhsu t0, a5, a5 +mulhsu t0, a5, s4 +mulhsu t0, a5, s9 +mulhsu t0, a5, t6 +mulhsu t0, s4, zero +mulhsu t0, s4, ra +mulhsu t0, s4, t0 +mulhsu t0, s4, a0 +mulhsu t0, s4, a5 +mulhsu t0, s4, s4 +mulhsu t0, s4, s9 +mulhsu t0, s4, t6 +mulhsu t0, s9, zero +mulhsu t0, s9, ra +mulhsu t0, s9, t0 +mulhsu t0, s9, a0 +mulhsu t0, s9, a5 +mulhsu t0, s9, s4 +mulhsu t0, s9, s9 +mulhsu t0, s9, t6 +mulhsu t0, t6, zero +mulhsu t0, t6, ra +mulhsu t0, t6, t0 +mulhsu t0, t6, a0 +mulhsu t0, t6, a5 +mulhsu t0, t6, s4 +mulhsu t0, t6, s9 +mulhsu t0, t6, t6 +mulhsu a0, zero, zero +mulhsu a0, zero, ra +mulhsu a0, zero, t0 +mulhsu a0, zero, a0 +mulhsu a0, zero, a5 +mulhsu a0, zero, s4 +mulhsu a0, zero, s9 +mulhsu a0, zero, t6 +mulhsu a0, ra, zero +mulhsu a0, ra, ra +mulhsu a0, ra, t0 +mulhsu a0, ra, a0 +mulhsu a0, ra, a5 +mulhsu a0, ra, s4 +mulhsu a0, ra, s9 +mulhsu a0, ra, t6 +mulhsu a0, t0, zero +mulhsu a0, t0, ra +mulhsu a0, t0, t0 +mulhsu a0, t0, a0 +mulhsu a0, t0, a5 +mulhsu a0, t0, s4 +mulhsu a0, t0, s9 +mulhsu a0, t0, t6 +mulhsu a0, a0, zero +mulhsu a0, a0, ra +mulhsu a0, a0, t0 +mulhsu a0, a0, a0 +mulhsu a0, a0, a5 +mulhsu a0, a0, s4 +mulhsu a0, a0, s9 +mulhsu a0, a0, t6 +mulhsu a0, a5, zero +mulhsu a0, a5, ra +mulhsu a0, a5, t0 +mulhsu a0, a5, a0 +mulhsu a0, a5, a5 +mulhsu a0, a5, s4 +mulhsu a0, a5, s9 +mulhsu a0, a5, t6 +mulhsu a0, s4, zero +mulhsu a0, s4, ra +mulhsu a0, s4, t0 +mulhsu a0, s4, a0 +mulhsu a0, s4, a5 +mulhsu a0, s4, s4 +mulhsu a0, s4, s9 +mulhsu a0, s4, t6 +mulhsu a0, s9, zero +mulhsu a0, s9, ra +mulhsu a0, s9, t0 +mulhsu a0, s9, a0 +mulhsu a0, s9, a5 +mulhsu a0, s9, s4 +mulhsu a0, s9, s9 +mulhsu a0, s9, t6 +mulhsu a0, t6, zero +mulhsu a0, t6, ra +mulhsu a0, t6, t0 +mulhsu a0, t6, a0 +mulhsu a0, t6, a5 +mulhsu a0, t6, s4 +mulhsu a0, t6, s9 +mulhsu a0, t6, t6 +mulhsu a5, zero, zero +mulhsu a5, zero, ra +mulhsu a5, zero, t0 +mulhsu a5, zero, a0 +mulhsu a5, zero, a5 +mulhsu a5, zero, s4 +mulhsu a5, zero, s9 +mulhsu a5, zero, t6 +mulhsu a5, ra, zero +mulhsu a5, ra, ra +mulhsu a5, ra, t0 +mulhsu a5, ra, a0 +mulhsu a5, ra, a5 +mulhsu a5, ra, s4 +mulhsu a5, ra, s9 +mulhsu a5, ra, t6 +mulhsu a5, t0, zero +mulhsu a5, t0, ra +mulhsu a5, t0, t0 +mulhsu a5, t0, a0 +mulhsu a5, t0, a5 +mulhsu a5, t0, s4 +mulhsu a5, t0, s9 +mulhsu a5, t0, t6 +mulhsu a5, a0, zero +mulhsu a5, a0, ra +mulhsu a5, a0, t0 +mulhsu a5, a0, a0 +mulhsu a5, a0, a5 +mulhsu a5, a0, s4 +mulhsu a5, a0, s9 +mulhsu a5, a0, t6 +mulhsu a5, a5, zero +mulhsu a5, a5, ra +mulhsu a5, a5, t0 +mulhsu a5, a5, a0 +mulhsu a5, a5, a5 +mulhsu a5, a5, s4 +mulhsu a5, a5, s9 +mulhsu a5, a5, t6 +mulhsu a5, s4, zero +mulhsu a5, s4, ra +mulhsu a5, s4, t0 +mulhsu a5, s4, a0 +mulhsu a5, s4, a5 +mulhsu a5, s4, s4 +mulhsu a5, s4, s9 +mulhsu a5, s4, t6 +mulhsu a5, s9, zero +mulhsu a5, s9, ra +mulhsu a5, s9, t0 +mulhsu a5, s9, a0 +mulhsu a5, s9, a5 +mulhsu a5, s9, s4 +mulhsu a5, s9, s9 +mulhsu a5, s9, t6 +mulhsu a5, t6, zero +mulhsu a5, t6, ra +mulhsu a5, t6, t0 +mulhsu a5, t6, a0 +mulhsu a5, t6, a5 +mulhsu a5, t6, s4 +mulhsu a5, t6, s9 +mulhsu a5, t6, t6 +mulhsu s4, zero, zero +mulhsu s4, zero, ra +mulhsu s4, zero, t0 +mulhsu s4, zero, a0 +mulhsu s4, zero, a5 +mulhsu s4, zero, s4 +mulhsu s4, zero, s9 +mulhsu s4, zero, t6 +mulhsu s4, ra, zero +mulhsu s4, ra, ra +mulhsu s4, ra, t0 +mulhsu s4, ra, a0 +mulhsu s4, ra, a5 +mulhsu s4, ra, s4 +mulhsu s4, ra, s9 +mulhsu s4, ra, t6 +mulhsu s4, t0, zero +mulhsu s4, t0, ra +mulhsu s4, t0, t0 +mulhsu s4, t0, a0 +mulhsu s4, t0, a5 +mulhsu s4, t0, s4 +mulhsu s4, t0, s9 +mulhsu s4, t0, t6 +mulhsu s4, a0, zero +mulhsu s4, a0, ra +mulhsu s4, a0, t0 +mulhsu s4, a0, a0 +mulhsu s4, a0, a5 +mulhsu s4, a0, s4 +mulhsu s4, a0, s9 +mulhsu s4, a0, t6 +mulhsu s4, a5, zero +mulhsu s4, a5, ra +mulhsu s4, a5, t0 +mulhsu s4, a5, a0 +mulhsu s4, a5, a5 +mulhsu s4, a5, s4 +mulhsu s4, a5, s9 +mulhsu s4, a5, t6 +mulhsu s4, s4, zero +mulhsu s4, s4, ra +mulhsu s4, s4, t0 +mulhsu s4, s4, a0 +mulhsu s4, s4, a5 +mulhsu s4, s4, s4 +mulhsu s4, s4, s9 +mulhsu s4, s4, t6 +mulhsu s4, s9, zero +mulhsu s4, s9, ra +mulhsu s4, s9, t0 +mulhsu s4, s9, a0 +mulhsu s4, s9, a5 +mulhsu s4, s9, s4 +mulhsu s4, s9, s9 +mulhsu s4, s9, t6 +mulhsu s4, t6, zero +mulhsu s4, t6, ra +mulhsu s4, t6, t0 +mulhsu s4, t6, a0 +mulhsu s4, t6, a5 +mulhsu s4, t6, s4 +mulhsu s4, t6, s9 +mulhsu s4, t6, t6 +mulhsu s9, zero, zero +mulhsu s9, zero, ra +mulhsu s9, zero, t0 +mulhsu s9, zero, a0 +mulhsu s9, zero, a5 +mulhsu s9, zero, s4 +mulhsu s9, zero, s9 +mulhsu s9, zero, t6 +mulhsu s9, ra, zero +mulhsu s9, ra, ra +mulhsu s9, ra, t0 +mulhsu s9, ra, a0 +mulhsu s9, ra, a5 +mulhsu s9, ra, s4 +mulhsu s9, ra, s9 +mulhsu s9, ra, t6 +mulhsu s9, t0, zero +mulhsu s9, t0, ra +mulhsu s9, t0, t0 +mulhsu s9, t0, a0 +mulhsu s9, t0, a5 +mulhsu s9, t0, s4 +mulhsu s9, t0, s9 +mulhsu s9, t0, t6 +mulhsu s9, a0, zero +mulhsu s9, a0, ra +mulhsu s9, a0, t0 +mulhsu s9, a0, a0 +mulhsu s9, a0, a5 +mulhsu s9, a0, s4 +mulhsu s9, a0, s9 +mulhsu s9, a0, t6 +mulhsu s9, a5, zero +mulhsu s9, a5, ra +mulhsu s9, a5, t0 +mulhsu s9, a5, a0 +mulhsu s9, a5, a5 +mulhsu s9, a5, s4 +mulhsu s9, a5, s9 +mulhsu s9, a5, t6 +mulhsu s9, s4, zero +mulhsu s9, s4, ra +mulhsu s9, s4, t0 +mulhsu s9, s4, a0 +mulhsu s9, s4, a5 +mulhsu s9, s4, s4 +mulhsu s9, s4, s9 +mulhsu s9, s4, t6 +mulhsu s9, s9, zero +mulhsu s9, s9, ra +mulhsu s9, s9, t0 +mulhsu s9, s9, a0 +mulhsu s9, s9, a5 +mulhsu s9, s9, s4 +mulhsu s9, s9, s9 +mulhsu s9, s9, t6 +mulhsu s9, t6, zero +mulhsu s9, t6, ra +mulhsu s9, t6, t0 +mulhsu s9, t6, a0 +mulhsu s9, t6, a5 +mulhsu s9, t6, s4 +mulhsu s9, t6, s9 +mulhsu s9, t6, t6 +mulhsu t6, zero, zero +mulhsu t6, zero, ra +mulhsu t6, zero, t0 +mulhsu t6, zero, a0 +mulhsu t6, zero, a5 +mulhsu t6, zero, s4 +mulhsu t6, zero, s9 +mulhsu t6, zero, t6 +mulhsu t6, ra, zero +mulhsu t6, ra, ra +mulhsu t6, ra, t0 +mulhsu t6, ra, a0 +mulhsu t6, ra, a5 +mulhsu t6, ra, s4 +mulhsu t6, ra, s9 +mulhsu t6, ra, t6 +mulhsu t6, t0, zero +mulhsu t6, t0, ra +mulhsu t6, t0, t0 +mulhsu t6, t0, a0 +mulhsu t6, t0, a5 +mulhsu t6, t0, s4 +mulhsu t6, t0, s9 +mulhsu t6, t0, t6 +mulhsu t6, a0, zero +mulhsu t6, a0, ra +mulhsu t6, a0, t0 +mulhsu t6, a0, a0 +mulhsu t6, a0, a5 +mulhsu t6, a0, s4 +mulhsu t6, a0, s9 +mulhsu t6, a0, t6 +mulhsu t6, a5, zero +mulhsu t6, a5, ra +mulhsu t6, a5, t0 +mulhsu t6, a5, a0 +mulhsu t6, a5, a5 +mulhsu t6, a5, s4 +mulhsu t6, a5, s9 +mulhsu t6, a5, t6 +mulhsu t6, s4, zero +mulhsu t6, s4, ra +mulhsu t6, s4, t0 +mulhsu t6, s4, a0 +mulhsu t6, s4, a5 +mulhsu t6, s4, s4 +mulhsu t6, s4, s9 +mulhsu t6, s4, t6 +mulhsu t6, s9, zero +mulhsu t6, s9, ra +mulhsu t6, s9, t0 +mulhsu t6, s9, a0 +mulhsu t6, s9, a5 +mulhsu t6, s9, s4 +mulhsu t6, s9, s9 +mulhsu t6, s9, t6 +mulhsu t6, t6, zero +mulhsu t6, t6, ra +mulhsu t6, t6, t0 +mulhsu t6, t6, a0 +mulhsu t6, t6, a5 +mulhsu t6, t6, s4 +mulhsu t6, t6, s9 +mulhsu t6, t6, t6 diff --git a/tests/riscv/m-extension/mulhu.asm b/tests/riscv/m-extension/mulhu.asm new file mode 100644 index 0000000..218a720 --- /dev/null +++ b/tests/riscv/m-extension/mulhu.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +mulhu zero, zero, zero +mulhu zero, zero, ra +mulhu zero, zero, t0 +mulhu zero, zero, a0 +mulhu zero, zero, a5 +mulhu zero, zero, s4 +mulhu zero, zero, s9 +mulhu zero, zero, t6 +mulhu zero, ra, zero +mulhu zero, ra, ra +mulhu zero, ra, t0 +mulhu zero, ra, a0 +mulhu zero, ra, a5 +mulhu zero, ra, s4 +mulhu zero, ra, s9 +mulhu zero, ra, t6 +mulhu zero, t0, zero +mulhu zero, t0, ra +mulhu zero, t0, t0 +mulhu zero, t0, a0 +mulhu zero, t0, a5 +mulhu zero, t0, s4 +mulhu zero, t0, s9 +mulhu zero, t0, t6 +mulhu zero, a0, zero +mulhu zero, a0, ra +mulhu zero, a0, t0 +mulhu zero, a0, a0 +mulhu zero, a0, a5 +mulhu zero, a0, s4 +mulhu zero, a0, s9 +mulhu zero, a0, t6 +mulhu zero, a5, zero +mulhu zero, a5, ra +mulhu zero, a5, t0 +mulhu zero, a5, a0 +mulhu zero, a5, a5 +mulhu zero, a5, s4 +mulhu zero, a5, s9 +mulhu zero, a5, t6 +mulhu zero, s4, zero +mulhu zero, s4, ra +mulhu zero, s4, t0 +mulhu zero, s4, a0 +mulhu zero, s4, a5 +mulhu zero, s4, s4 +mulhu zero, s4, s9 +mulhu zero, s4, t6 +mulhu zero, s9, zero +mulhu zero, s9, ra +mulhu zero, s9, t0 +mulhu zero, s9, a0 +mulhu zero, s9, a5 +mulhu zero, s9, s4 +mulhu zero, s9, s9 +mulhu zero, s9, t6 +mulhu zero, t6, zero +mulhu zero, t6, ra +mulhu zero, t6, t0 +mulhu zero, t6, a0 +mulhu zero, t6, a5 +mulhu zero, t6, s4 +mulhu zero, t6, s9 +mulhu zero, t6, t6 +mulhu ra, zero, zero +mulhu ra, zero, ra +mulhu ra, zero, t0 +mulhu ra, zero, a0 +mulhu ra, zero, a5 +mulhu ra, zero, s4 +mulhu ra, zero, s9 +mulhu ra, zero, t6 +mulhu ra, ra, zero +mulhu ra, ra, ra +mulhu ra, ra, t0 +mulhu ra, ra, a0 +mulhu ra, ra, a5 +mulhu ra, ra, s4 +mulhu ra, ra, s9 +mulhu ra, ra, t6 +mulhu ra, t0, zero +mulhu ra, t0, ra +mulhu ra, t0, t0 +mulhu ra, t0, a0 +mulhu ra, t0, a5 +mulhu ra, t0, s4 +mulhu ra, t0, s9 +mulhu ra, t0, t6 +mulhu ra, a0, zero +mulhu ra, a0, ra +mulhu ra, a0, t0 +mulhu ra, a0, a0 +mulhu ra, a0, a5 +mulhu ra, a0, s4 +mulhu ra, a0, s9 +mulhu ra, a0, t6 +mulhu ra, a5, zero +mulhu ra, a5, ra +mulhu ra, a5, t0 +mulhu ra, a5, a0 +mulhu ra, a5, a5 +mulhu ra, a5, s4 +mulhu ra, a5, s9 +mulhu ra, a5, t6 +mulhu ra, s4, zero +mulhu ra, s4, ra +mulhu ra, s4, t0 +mulhu ra, s4, a0 +mulhu ra, s4, a5 +mulhu ra, s4, s4 +mulhu ra, s4, s9 +mulhu ra, s4, t6 +mulhu ra, s9, zero +mulhu ra, s9, ra +mulhu ra, s9, t0 +mulhu ra, s9, a0 +mulhu ra, s9, a5 +mulhu ra, s9, s4 +mulhu ra, s9, s9 +mulhu ra, s9, t6 +mulhu ra, t6, zero +mulhu ra, t6, ra +mulhu ra, t6, t0 +mulhu ra, t6, a0 +mulhu ra, t6, a5 +mulhu ra, t6, s4 +mulhu ra, t6, s9 +mulhu ra, t6, t6 +mulhu t0, zero, zero +mulhu t0, zero, ra +mulhu t0, zero, t0 +mulhu t0, zero, a0 +mulhu t0, zero, a5 +mulhu t0, zero, s4 +mulhu t0, zero, s9 +mulhu t0, zero, t6 +mulhu t0, ra, zero +mulhu t0, ra, ra +mulhu t0, ra, t0 +mulhu t0, ra, a0 +mulhu t0, ra, a5 +mulhu t0, ra, s4 +mulhu t0, ra, s9 +mulhu t0, ra, t6 +mulhu t0, t0, zero +mulhu t0, t0, ra +mulhu t0, t0, t0 +mulhu t0, t0, a0 +mulhu t0, t0, a5 +mulhu t0, t0, s4 +mulhu t0, t0, s9 +mulhu t0, t0, t6 +mulhu t0, a0, zero +mulhu t0, a0, ra +mulhu t0, a0, t0 +mulhu t0, a0, a0 +mulhu t0, a0, a5 +mulhu t0, a0, s4 +mulhu t0, a0, s9 +mulhu t0, a0, t6 +mulhu t0, a5, zero +mulhu t0, a5, ra +mulhu t0, a5, t0 +mulhu t0, a5, a0 +mulhu t0, a5, a5 +mulhu t0, a5, s4 +mulhu t0, a5, s9 +mulhu t0, a5, t6 +mulhu t0, s4, zero +mulhu t0, s4, ra +mulhu t0, s4, t0 +mulhu t0, s4, a0 +mulhu t0, s4, a5 +mulhu t0, s4, s4 +mulhu t0, s4, s9 +mulhu t0, s4, t6 +mulhu t0, s9, zero +mulhu t0, s9, ra +mulhu t0, s9, t0 +mulhu t0, s9, a0 +mulhu t0, s9, a5 +mulhu t0, s9, s4 +mulhu t0, s9, s9 +mulhu t0, s9, t6 +mulhu t0, t6, zero +mulhu t0, t6, ra +mulhu t0, t6, t0 +mulhu t0, t6, a0 +mulhu t0, t6, a5 +mulhu t0, t6, s4 +mulhu t0, t6, s9 +mulhu t0, t6, t6 +mulhu a0, zero, zero +mulhu a0, zero, ra +mulhu a0, zero, t0 +mulhu a0, zero, a0 +mulhu a0, zero, a5 +mulhu a0, zero, s4 +mulhu a0, zero, s9 +mulhu a0, zero, t6 +mulhu a0, ra, zero +mulhu a0, ra, ra +mulhu a0, ra, t0 +mulhu a0, ra, a0 +mulhu a0, ra, a5 +mulhu a0, ra, s4 +mulhu a0, ra, s9 +mulhu a0, ra, t6 +mulhu a0, t0, zero +mulhu a0, t0, ra +mulhu a0, t0, t0 +mulhu a0, t0, a0 +mulhu a0, t0, a5 +mulhu a0, t0, s4 +mulhu a0, t0, s9 +mulhu a0, t0, t6 +mulhu a0, a0, zero +mulhu a0, a0, ra +mulhu a0, a0, t0 +mulhu a0, a0, a0 +mulhu a0, a0, a5 +mulhu a0, a0, s4 +mulhu a0, a0, s9 +mulhu a0, a0, t6 +mulhu a0, a5, zero +mulhu a0, a5, ra +mulhu a0, a5, t0 +mulhu a0, a5, a0 +mulhu a0, a5, a5 +mulhu a0, a5, s4 +mulhu a0, a5, s9 +mulhu a0, a5, t6 +mulhu a0, s4, zero +mulhu a0, s4, ra +mulhu a0, s4, t0 +mulhu a0, s4, a0 +mulhu a0, s4, a5 +mulhu a0, s4, s4 +mulhu a0, s4, s9 +mulhu a0, s4, t6 +mulhu a0, s9, zero +mulhu a0, s9, ra +mulhu a0, s9, t0 +mulhu a0, s9, a0 +mulhu a0, s9, a5 +mulhu a0, s9, s4 +mulhu a0, s9, s9 +mulhu a0, s9, t6 +mulhu a0, t6, zero +mulhu a0, t6, ra +mulhu a0, t6, t0 +mulhu a0, t6, a0 +mulhu a0, t6, a5 +mulhu a0, t6, s4 +mulhu a0, t6, s9 +mulhu a0, t6, t6 +mulhu a5, zero, zero +mulhu a5, zero, ra +mulhu a5, zero, t0 +mulhu a5, zero, a0 +mulhu a5, zero, a5 +mulhu a5, zero, s4 +mulhu a5, zero, s9 +mulhu a5, zero, t6 +mulhu a5, ra, zero +mulhu a5, ra, ra +mulhu a5, ra, t0 +mulhu a5, ra, a0 +mulhu a5, ra, a5 +mulhu a5, ra, s4 +mulhu a5, ra, s9 +mulhu a5, ra, t6 +mulhu a5, t0, zero +mulhu a5, t0, ra +mulhu a5, t0, t0 +mulhu a5, t0, a0 +mulhu a5, t0, a5 +mulhu a5, t0, s4 +mulhu a5, t0, s9 +mulhu a5, t0, t6 +mulhu a5, a0, zero +mulhu a5, a0, ra +mulhu a5, a0, t0 +mulhu a5, a0, a0 +mulhu a5, a0, a5 +mulhu a5, a0, s4 +mulhu a5, a0, s9 +mulhu a5, a0, t6 +mulhu a5, a5, zero +mulhu a5, a5, ra +mulhu a5, a5, t0 +mulhu a5, a5, a0 +mulhu a5, a5, a5 +mulhu a5, a5, s4 +mulhu a5, a5, s9 +mulhu a5, a5, t6 +mulhu a5, s4, zero +mulhu a5, s4, ra +mulhu a5, s4, t0 +mulhu a5, s4, a0 +mulhu a5, s4, a5 +mulhu a5, s4, s4 +mulhu a5, s4, s9 +mulhu a5, s4, t6 +mulhu a5, s9, zero +mulhu a5, s9, ra +mulhu a5, s9, t0 +mulhu a5, s9, a0 +mulhu a5, s9, a5 +mulhu a5, s9, s4 +mulhu a5, s9, s9 +mulhu a5, s9, t6 +mulhu a5, t6, zero +mulhu a5, t6, ra +mulhu a5, t6, t0 +mulhu a5, t6, a0 +mulhu a5, t6, a5 +mulhu a5, t6, s4 +mulhu a5, t6, s9 +mulhu a5, t6, t6 +mulhu s4, zero, zero +mulhu s4, zero, ra +mulhu s4, zero, t0 +mulhu s4, zero, a0 +mulhu s4, zero, a5 +mulhu s4, zero, s4 +mulhu s4, zero, s9 +mulhu s4, zero, t6 +mulhu s4, ra, zero +mulhu s4, ra, ra +mulhu s4, ra, t0 +mulhu s4, ra, a0 +mulhu s4, ra, a5 +mulhu s4, ra, s4 +mulhu s4, ra, s9 +mulhu s4, ra, t6 +mulhu s4, t0, zero +mulhu s4, t0, ra +mulhu s4, t0, t0 +mulhu s4, t0, a0 +mulhu s4, t0, a5 +mulhu s4, t0, s4 +mulhu s4, t0, s9 +mulhu s4, t0, t6 +mulhu s4, a0, zero +mulhu s4, a0, ra +mulhu s4, a0, t0 +mulhu s4, a0, a0 +mulhu s4, a0, a5 +mulhu s4, a0, s4 +mulhu s4, a0, s9 +mulhu s4, a0, t6 +mulhu s4, a5, zero +mulhu s4, a5, ra +mulhu s4, a5, t0 +mulhu s4, a5, a0 +mulhu s4, a5, a5 +mulhu s4, a5, s4 +mulhu s4, a5, s9 +mulhu s4, a5, t6 +mulhu s4, s4, zero +mulhu s4, s4, ra +mulhu s4, s4, t0 +mulhu s4, s4, a0 +mulhu s4, s4, a5 +mulhu s4, s4, s4 +mulhu s4, s4, s9 +mulhu s4, s4, t6 +mulhu s4, s9, zero +mulhu s4, s9, ra +mulhu s4, s9, t0 +mulhu s4, s9, a0 +mulhu s4, s9, a5 +mulhu s4, s9, s4 +mulhu s4, s9, s9 +mulhu s4, s9, t6 +mulhu s4, t6, zero +mulhu s4, t6, ra +mulhu s4, t6, t0 +mulhu s4, t6, a0 +mulhu s4, t6, a5 +mulhu s4, t6, s4 +mulhu s4, t6, s9 +mulhu s4, t6, t6 +mulhu s9, zero, zero +mulhu s9, zero, ra +mulhu s9, zero, t0 +mulhu s9, zero, a0 +mulhu s9, zero, a5 +mulhu s9, zero, s4 +mulhu s9, zero, s9 +mulhu s9, zero, t6 +mulhu s9, ra, zero +mulhu s9, ra, ra +mulhu s9, ra, t0 +mulhu s9, ra, a0 +mulhu s9, ra, a5 +mulhu s9, ra, s4 +mulhu s9, ra, s9 +mulhu s9, ra, t6 +mulhu s9, t0, zero +mulhu s9, t0, ra +mulhu s9, t0, t0 +mulhu s9, t0, a0 +mulhu s9, t0, a5 +mulhu s9, t0, s4 +mulhu s9, t0, s9 +mulhu s9, t0, t6 +mulhu s9, a0, zero +mulhu s9, a0, ra +mulhu s9, a0, t0 +mulhu s9, a0, a0 +mulhu s9, a0, a5 +mulhu s9, a0, s4 +mulhu s9, a0, s9 +mulhu s9, a0, t6 +mulhu s9, a5, zero +mulhu s9, a5, ra +mulhu s9, a5, t0 +mulhu s9, a5, a0 +mulhu s9, a5, a5 +mulhu s9, a5, s4 +mulhu s9, a5, s9 +mulhu s9, a5, t6 +mulhu s9, s4, zero +mulhu s9, s4, ra +mulhu s9, s4, t0 +mulhu s9, s4, a0 +mulhu s9, s4, a5 +mulhu s9, s4, s4 +mulhu s9, s4, s9 +mulhu s9, s4, t6 +mulhu s9, s9, zero +mulhu s9, s9, ra +mulhu s9, s9, t0 +mulhu s9, s9, a0 +mulhu s9, s9, a5 +mulhu s9, s9, s4 +mulhu s9, s9, s9 +mulhu s9, s9, t6 +mulhu s9, t6, zero +mulhu s9, t6, ra +mulhu s9, t6, t0 +mulhu s9, t6, a0 +mulhu s9, t6, a5 +mulhu s9, t6, s4 +mulhu s9, t6, s9 +mulhu s9, t6, t6 +mulhu t6, zero, zero +mulhu t6, zero, ra +mulhu t6, zero, t0 +mulhu t6, zero, a0 +mulhu t6, zero, a5 +mulhu t6, zero, s4 +mulhu t6, zero, s9 +mulhu t6, zero, t6 +mulhu t6, ra, zero +mulhu t6, ra, ra +mulhu t6, ra, t0 +mulhu t6, ra, a0 +mulhu t6, ra, a5 +mulhu t6, ra, s4 +mulhu t6, ra, s9 +mulhu t6, ra, t6 +mulhu t6, t0, zero +mulhu t6, t0, ra +mulhu t6, t0, t0 +mulhu t6, t0, a0 +mulhu t6, t0, a5 +mulhu t6, t0, s4 +mulhu t6, t0, s9 +mulhu t6, t0, t6 +mulhu t6, a0, zero +mulhu t6, a0, ra +mulhu t6, a0, t0 +mulhu t6, a0, a0 +mulhu t6, a0, a5 +mulhu t6, a0, s4 +mulhu t6, a0, s9 +mulhu t6, a0, t6 +mulhu t6, a5, zero +mulhu t6, a5, ra +mulhu t6, a5, t0 +mulhu t6, a5, a0 +mulhu t6, a5, a5 +mulhu t6, a5, s4 +mulhu t6, a5, s9 +mulhu t6, a5, t6 +mulhu t6, s4, zero +mulhu t6, s4, ra +mulhu t6, s4, t0 +mulhu t6, s4, a0 +mulhu t6, s4, a5 +mulhu t6, s4, s4 +mulhu t6, s4, s9 +mulhu t6, s4, t6 +mulhu t6, s9, zero +mulhu t6, s9, ra +mulhu t6, s9, t0 +mulhu t6, s9, a0 +mulhu t6, s9, a5 +mulhu t6, s9, s4 +mulhu t6, s9, s9 +mulhu t6, s9, t6 +mulhu t6, t6, zero +mulhu t6, t6, ra +mulhu t6, t6, t0 +mulhu t6, t6, a0 +mulhu t6, t6, a5 +mulhu t6, t6, s4 +mulhu t6, t6, s9 +mulhu t6, t6, t6 + diff --git a/tests/riscv/m-extension/mulhu.bin b/tests/riscv/m-extension/mulhu.bin new file mode 100644 index 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zero, a0 +rem zero, zero, a5 +rem zero, zero, s4 +rem zero, zero, s9 +rem zero, zero, t6 +rem zero, ra, zero +rem zero, ra, ra +rem zero, ra, t0 +rem zero, ra, a0 +rem zero, ra, a5 +rem zero, ra, s4 +rem zero, ra, s9 +rem zero, ra, t6 +rem zero, t0, zero +rem zero, t0, ra +rem zero, t0, t0 +rem zero, t0, a0 +rem zero, t0, a5 +rem zero, t0, s4 +rem zero, t0, s9 +rem zero, t0, t6 +rem zero, a0, zero +rem zero, a0, ra +rem zero, a0, t0 +rem zero, a0, a0 +rem zero, a0, a5 +rem zero, a0, s4 +rem zero, a0, s9 +rem zero, a0, t6 +rem zero, a5, zero +rem zero, a5, ra +rem zero, a5, t0 +rem zero, a5, a0 +rem zero, a5, a5 +rem zero, a5, s4 +rem zero, a5, s9 +rem zero, a5, t6 +rem zero, s4, zero +rem zero, s4, ra +rem zero, s4, t0 +rem zero, s4, a0 +rem zero, s4, a5 +rem zero, s4, s4 +rem zero, s4, s9 +rem zero, s4, t6 +rem zero, s9, zero +rem zero, s9, ra +rem zero, s9, t0 +rem zero, s9, a0 +rem zero, s9, a5 +rem zero, s9, s4 +rem zero, s9, s9 +rem zero, s9, t6 +rem zero, t6, zero +rem zero, t6, ra +rem zero, t6, t0 +rem zero, t6, a0 +rem zero, t6, a5 +rem zero, t6, s4 +rem zero, t6, s9 +rem zero, t6, t6 +rem ra, zero, zero +rem ra, zero, ra +rem ra, zero, t0 +rem ra, zero, a0 +rem ra, zero, a5 +rem ra, zero, s4 +rem ra, zero, s9 +rem ra, zero, t6 +rem ra, ra, zero +rem ra, ra, ra +rem ra, ra, t0 +rem ra, ra, a0 +rem ra, ra, a5 +rem ra, ra, s4 +rem ra, ra, s9 +rem ra, ra, t6 +rem ra, t0, zero +rem ra, t0, ra +rem ra, t0, t0 +rem ra, t0, a0 +rem ra, t0, a5 +rem ra, t0, s4 +rem ra, t0, s9 +rem ra, t0, t6 +rem ra, a0, zero +rem ra, a0, ra +rem ra, a0, t0 +rem ra, a0, a0 +rem ra, a0, a5 +rem ra, a0, s4 +rem ra, a0, s9 +rem ra, a0, t6 +rem ra, a5, zero +rem ra, a5, ra +rem ra, a5, t0 +rem ra, a5, a0 +rem ra, a5, a5 +rem ra, a5, s4 +rem ra, a5, s9 +rem ra, a5, t6 +rem ra, s4, zero +rem ra, s4, ra +rem ra, s4, t0 +rem ra, s4, a0 +rem ra, s4, a5 +rem ra, s4, s4 +rem ra, s4, s9 +rem ra, s4, t6 +rem ra, s9, zero +rem ra, s9, ra +rem ra, s9, t0 +rem ra, s9, a0 +rem ra, s9, a5 +rem ra, s9, s4 +rem ra, s9, s9 +rem ra, s9, t6 +rem ra, t6, zero +rem ra, t6, ra +rem ra, t6, t0 +rem ra, t6, a0 +rem ra, t6, a5 +rem ra, t6, s4 +rem ra, t6, s9 +rem ra, t6, t6 +rem t0, zero, zero +rem t0, zero, ra +rem t0, zero, t0 +rem t0, zero, a0 +rem t0, zero, a5 +rem t0, zero, s4 +rem t0, zero, s9 +rem t0, zero, t6 +rem t0, ra, zero +rem t0, ra, ra +rem t0, ra, t0 +rem t0, ra, a0 +rem t0, ra, a5 +rem t0, ra, s4 +rem t0, ra, s9 +rem t0, ra, t6 +rem t0, t0, zero +rem t0, t0, ra +rem t0, t0, t0 +rem t0, t0, a0 +rem t0, t0, a5 +rem t0, t0, s4 +rem t0, t0, s9 +rem t0, t0, t6 +rem t0, a0, zero +rem t0, a0, ra +rem t0, a0, t0 +rem t0, a0, a0 +rem t0, a0, a5 +rem t0, a0, s4 +rem t0, a0, s9 +rem t0, a0, t6 +rem t0, a5, zero +rem t0, a5, ra +rem t0, a5, t0 +rem t0, a5, a0 +rem t0, a5, a5 +rem t0, a5, s4 +rem t0, a5, s9 +rem t0, a5, t6 +rem t0, s4, zero +rem t0, s4, ra +rem t0, s4, t0 +rem t0, s4, a0 +rem t0, s4, a5 +rem t0, s4, s4 +rem t0, s4, s9 +rem t0, s4, t6 +rem t0, s9, zero +rem t0, s9, ra +rem t0, s9, t0 +rem t0, s9, a0 +rem t0, s9, a5 +rem t0, s9, s4 +rem t0, s9, s9 +rem t0, s9, t6 +rem t0, t6, zero +rem t0, t6, ra +rem t0, t6, t0 +rem t0, t6, a0 +rem t0, t6, a5 +rem t0, t6, s4 +rem t0, t6, s9 +rem t0, t6, t6 +rem a0, zero, zero +rem a0, zero, ra +rem a0, zero, t0 +rem a0, zero, a0 +rem a0, zero, a5 +rem a0, zero, s4 +rem a0, zero, s9 +rem a0, zero, t6 +rem a0, ra, zero +rem a0, ra, ra +rem a0, ra, t0 +rem a0, ra, a0 +rem a0, ra, a5 +rem a0, ra, s4 +rem a0, ra, s9 +rem a0, ra, t6 +rem a0, t0, zero +rem a0, t0, ra +rem a0, t0, t0 +rem a0, t0, a0 +rem a0, t0, a5 +rem a0, t0, s4 +rem a0, t0, s9 +rem a0, t0, t6 +rem a0, a0, zero +rem a0, a0, ra +rem a0, a0, t0 +rem a0, a0, a0 +rem a0, a0, a5 +rem a0, a0, s4 +rem a0, a0, s9 +rem a0, a0, t6 +rem a0, a5, zero +rem a0, a5, ra +rem a0, a5, t0 +rem a0, a5, a0 +rem a0, a5, a5 +rem a0, a5, s4 +rem a0, a5, s9 +rem a0, a5, t6 +rem a0, s4, zero +rem a0, s4, ra +rem a0, s4, t0 +rem a0, s4, a0 +rem a0, s4, a5 +rem a0, s4, s4 +rem a0, s4, s9 +rem a0, s4, t6 +rem a0, s9, zero +rem a0, s9, ra +rem a0, s9, t0 +rem a0, s9, a0 +rem a0, s9, a5 +rem a0, s9, s4 +rem a0, s9, s9 +rem a0, s9, t6 +rem a0, t6, zero +rem a0, t6, ra +rem a0, t6, t0 +rem a0, t6, a0 +rem a0, t6, a5 +rem a0, t6, s4 +rem a0, t6, s9 +rem a0, t6, t6 +rem a5, zero, zero +rem a5, zero, ra +rem a5, zero, t0 +rem a5, zero, a0 +rem a5, zero, a5 +rem a5, zero, s4 +rem a5, zero, s9 +rem a5, zero, t6 +rem a5, ra, zero +rem a5, ra, ra +rem a5, ra, t0 +rem a5, ra, a0 +rem a5, ra, a5 +rem a5, ra, s4 +rem a5, ra, s9 +rem a5, ra, t6 +rem a5, t0, zero +rem a5, t0, ra +rem a5, t0, t0 +rem a5, t0, a0 +rem a5, t0, a5 +rem a5, t0, s4 +rem a5, t0, s9 +rem a5, t0, t6 +rem a5, a0, zero +rem a5, a0, ra +rem a5, a0, t0 +rem a5, a0, a0 +rem a5, a0, a5 +rem a5, a0, s4 +rem a5, a0, s9 +rem a5, a0, t6 +rem a5, a5, zero +rem a5, a5, ra +rem a5, a5, t0 +rem a5, a5, a0 +rem a5, a5, a5 +rem a5, a5, s4 +rem a5, a5, s9 +rem a5, a5, t6 +rem a5, s4, zero +rem a5, s4, ra +rem a5, s4, t0 +rem a5, s4, a0 +rem a5, s4, a5 +rem a5, s4, s4 +rem a5, s4, s9 +rem a5, s4, t6 +rem a5, s9, zero +rem a5, s9, ra +rem a5, s9, t0 +rem a5, s9, a0 +rem a5, s9, a5 +rem a5, s9, s4 +rem a5, s9, s9 +rem a5, s9, t6 +rem a5, t6, zero +rem a5, t6, ra +rem a5, t6, t0 +rem a5, t6, a0 +rem a5, t6, a5 +rem a5, t6, s4 +rem a5, t6, s9 +rem a5, t6, t6 +rem s4, zero, zero +rem s4, zero, ra +rem s4, zero, t0 +rem s4, zero, a0 +rem s4, zero, a5 +rem s4, zero, s4 +rem s4, zero, s9 +rem s4, zero, t6 +rem s4, ra, zero +rem s4, ra, ra +rem s4, ra, t0 +rem s4, ra, a0 +rem s4, ra, a5 +rem s4, ra, s4 +rem s4, ra, s9 +rem s4, ra, t6 +rem s4, t0, zero +rem s4, t0, ra +rem s4, t0, t0 +rem s4, t0, a0 +rem s4, t0, a5 +rem s4, t0, s4 +rem s4, t0, s9 +rem s4, t0, t6 +rem s4, a0, zero +rem s4, a0, ra +rem s4, a0, t0 +rem s4, a0, a0 +rem s4, a0, a5 +rem s4, a0, s4 +rem s4, a0, s9 +rem s4, a0, t6 +rem s4, a5, zero +rem s4, a5, ra +rem s4, a5, t0 +rem s4, a5, a0 +rem s4, a5, a5 +rem s4, a5, s4 +rem s4, a5, s9 +rem s4, a5, t6 +rem s4, s4, zero +rem s4, s4, ra +rem s4, s4, t0 +rem s4, s4, a0 +rem s4, s4, a5 +rem s4, s4, s4 +rem s4, s4, s9 +rem s4, s4, t6 +rem s4, s9, zero +rem s4, s9, ra +rem s4, s9, t0 +rem s4, s9, a0 +rem s4, s9, a5 +rem s4, s9, s4 +rem s4, s9, s9 +rem s4, s9, t6 +rem s4, t6, zero +rem s4, t6, ra +rem s4, t6, t0 +rem s4, t6, a0 +rem s4, t6, a5 +rem s4, t6, s4 +rem s4, t6, s9 +rem s4, t6, t6 +rem s9, zero, zero +rem s9, zero, ra +rem s9, zero, t0 +rem s9, zero, a0 +rem s9, zero, a5 +rem s9, zero, s4 +rem s9, zero, s9 +rem s9, zero, t6 +rem s9, ra, zero +rem s9, ra, ra +rem s9, ra, t0 +rem s9, ra, a0 +rem s9, ra, a5 +rem s9, ra, s4 +rem s9, ra, s9 +rem s9, ra, t6 +rem s9, t0, zero +rem s9, t0, ra +rem s9, t0, t0 +rem s9, t0, a0 +rem s9, t0, a5 +rem s9, t0, s4 +rem s9, t0, s9 +rem s9, t0, t6 +rem s9, a0, zero +rem s9, a0, ra +rem s9, a0, t0 +rem s9, a0, a0 +rem s9, a0, a5 +rem s9, a0, s4 +rem s9, a0, s9 +rem s9, a0, t6 +rem s9, a5, zero +rem s9, a5, ra +rem s9, a5, t0 +rem s9, a5, a0 +rem s9, a5, a5 +rem s9, a5, s4 +rem s9, a5, s9 +rem s9, a5, t6 +rem s9, s4, zero +rem s9, s4, ra +rem s9, s4, t0 +rem s9, s4, a0 +rem s9, s4, a5 +rem s9, s4, s4 +rem s9, s4, s9 +rem s9, s4, t6 +rem s9, s9, zero +rem s9, s9, ra +rem s9, s9, t0 +rem s9, s9, a0 +rem s9, s9, a5 +rem s9, s9, s4 +rem s9, s9, s9 +rem s9, s9, t6 +rem s9, t6, zero +rem s9, t6, ra +rem s9, t6, t0 +rem s9, t6, a0 +rem s9, t6, a5 +rem s9, t6, s4 +rem s9, t6, s9 +rem s9, t6, t6 +rem t6, zero, zero +rem t6, zero, ra +rem t6, zero, t0 +rem t6, zero, a0 +rem t6, zero, a5 +rem t6, zero, s4 +rem t6, zero, s9 +rem t6, zero, t6 +rem t6, ra, zero +rem t6, ra, ra +rem t6, ra, t0 +rem t6, ra, a0 +rem t6, ra, a5 +rem t6, ra, s4 +rem t6, ra, s9 +rem t6, ra, t6 +rem t6, t0, zero +rem t6, t0, ra +rem t6, t0, t0 +rem t6, t0, a0 +rem t6, t0, a5 +rem t6, t0, s4 +rem t6, t0, s9 +rem t6, t0, t6 +rem t6, a0, zero +rem t6, a0, ra +rem t6, a0, t0 +rem t6, a0, a0 +rem t6, a0, a5 +rem t6, a0, s4 +rem t6, a0, s9 +rem t6, a0, t6 +rem t6, a5, zero +rem t6, a5, ra +rem t6, a5, t0 +rem t6, a5, a0 +rem t6, a5, a5 +rem t6, a5, s4 +rem t6, a5, s9 +rem t6, a5, t6 +rem t6, s4, zero +rem t6, s4, ra +rem t6, s4, t0 +rem t6, s4, a0 +rem t6, s4, a5 +rem t6, s4, s4 +rem t6, s4, s9 +rem t6, s4, t6 +rem t6, s9, zero +rem t6, s9, ra +rem t6, s9, t0 +rem t6, s9, a0 +rem t6, s9, a5 +rem t6, s9, s4 +rem t6, s9, s9 +rem t6, s9, t6 +rem t6, t6, zero +rem t6, t6, ra +rem t6, t6, t0 +rem t6, t6, a0 +rem t6, t6, a5 +rem t6, t6, s4 +rem t6, t6, s9 +rem t6, t6, t6 diff --git a/tests/riscv/m-extension/remu.asm b/tests/riscv/m-extension/remu.asm new file mode 100644 index 0000000..3a33408 --- /dev/null +++ b/tests/riscv/m-extension/remu.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +remu zero, zero, zero +remu zero, zero, ra +remu zero, zero, t0 +remu zero, zero, a0 +remu zero, zero, a5 +remu zero, zero, s4 +remu zero, zero, s9 +remu zero, zero, t6 +remu zero, ra, zero +remu zero, ra, ra +remu zero, ra, t0 +remu zero, ra, a0 +remu zero, ra, a5 +remu zero, ra, s4 +remu zero, ra, s9 +remu zero, ra, t6 +remu zero, t0, zero +remu zero, t0, ra +remu zero, t0, t0 +remu zero, t0, a0 +remu zero, t0, a5 +remu zero, t0, s4 +remu zero, t0, s9 +remu zero, t0, t6 +remu zero, a0, zero +remu zero, a0, ra +remu zero, a0, t0 +remu zero, a0, a0 +remu zero, a0, a5 +remu zero, a0, s4 +remu zero, a0, s9 +remu zero, a0, t6 +remu zero, a5, zero +remu zero, a5, ra +remu zero, a5, t0 +remu zero, a5, a0 +remu zero, a5, a5 +remu zero, a5, s4 +remu zero, a5, s9 +remu zero, a5, t6 +remu zero, s4, zero +remu zero, s4, ra +remu zero, s4, t0 +remu zero, s4, a0 +remu zero, s4, a5 +remu zero, s4, s4 +remu zero, s4, s9 +remu zero, s4, t6 +remu zero, s9, zero +remu zero, s9, ra +remu zero, s9, t0 +remu zero, s9, a0 +remu zero, s9, a5 +remu zero, s9, s4 +remu zero, s9, s9 +remu zero, s9, t6 +remu zero, t6, zero +remu zero, t6, ra +remu zero, t6, t0 +remu zero, t6, a0 +remu zero, t6, a5 +remu zero, t6, s4 +remu zero, t6, s9 +remu zero, t6, t6 +remu ra, zero, zero +remu ra, zero, ra +remu ra, zero, t0 +remu ra, zero, a0 +remu ra, zero, a5 +remu ra, zero, s4 +remu ra, zero, s9 +remu ra, zero, t6 +remu ra, ra, zero +remu ra, ra, ra +remu ra, ra, t0 +remu ra, ra, a0 +remu ra, ra, a5 +remu ra, ra, s4 +remu ra, ra, s9 +remu ra, ra, t6 +remu ra, t0, zero +remu ra, t0, ra +remu ra, t0, t0 +remu ra, t0, a0 +remu ra, t0, a5 +remu ra, t0, s4 +remu ra, t0, s9 +remu ra, t0, t6 +remu ra, a0, zero +remu ra, a0, ra +remu ra, a0, t0 +remu ra, a0, a0 +remu ra, a0, a5 +remu ra, a0, s4 +remu ra, a0, s9 +remu ra, a0, t6 +remu ra, a5, zero +remu ra, a5, ra +remu ra, a5, t0 +remu ra, a5, a0 +remu ra, a5, a5 +remu ra, a5, s4 +remu ra, a5, s9 +remu ra, a5, t6 +remu ra, s4, zero +remu ra, s4, ra +remu ra, s4, t0 +remu ra, s4, a0 +remu ra, s4, a5 +remu ra, s4, s4 +remu ra, s4, s9 +remu ra, s4, t6 +remu ra, s9, zero +remu ra, s9, ra +remu ra, s9, t0 +remu ra, s9, a0 +remu ra, s9, a5 +remu ra, s9, s4 +remu ra, s9, s9 +remu ra, s9, t6 +remu ra, t6, zero +remu ra, t6, ra +remu ra, t6, t0 +remu ra, t6, a0 +remu ra, t6, a5 +remu ra, t6, s4 +remu ra, t6, s9 +remu ra, t6, t6 +remu t0, zero, zero +remu t0, zero, ra +remu t0, zero, t0 +remu t0, zero, a0 +remu t0, zero, a5 +remu t0, zero, s4 +remu t0, zero, s9 +remu t0, zero, t6 +remu t0, ra, zero +remu t0, ra, ra +remu t0, ra, t0 +remu t0, ra, a0 +remu t0, ra, a5 +remu t0, ra, s4 +remu t0, ra, s9 +remu t0, ra, t6 +remu t0, t0, zero +remu t0, t0, ra +remu t0, t0, t0 +remu t0, t0, a0 +remu t0, t0, a5 +remu t0, t0, s4 +remu t0, t0, s9 +remu t0, t0, t6 +remu t0, a0, zero +remu t0, a0, ra +remu t0, a0, t0 +remu t0, a0, a0 +remu t0, a0, a5 +remu t0, a0, s4 +remu t0, a0, s9 +remu t0, a0, t6 +remu t0, a5, zero +remu t0, a5, ra +remu t0, a5, t0 +remu t0, a5, a0 +remu t0, a5, a5 +remu t0, a5, s4 +remu t0, a5, s9 +remu t0, a5, t6 +remu t0, s4, zero +remu t0, s4, ra +remu t0, s4, t0 +remu t0, s4, a0 +remu t0, s4, a5 +remu t0, s4, s4 +remu t0, s4, s9 +remu t0, s4, t6 +remu t0, s9, zero +remu t0, s9, ra +remu t0, s9, t0 +remu t0, s9, a0 +remu t0, s9, a5 +remu t0, s9, s4 +remu t0, s9, s9 +remu t0, s9, t6 +remu t0, t6, zero +remu t0, t6, ra +remu t0, t6, t0 +remu t0, t6, a0 +remu t0, t6, a5 +remu t0, t6, s4 +remu t0, t6, s9 +remu t0, t6, t6 +remu a0, zero, zero +remu a0, zero, ra +remu a0, zero, t0 +remu a0, zero, a0 +remu a0, zero, a5 +remu a0, zero, s4 +remu a0, zero, s9 +remu a0, zero, t6 +remu a0, ra, zero +remu a0, ra, ra +remu a0, ra, t0 +remu a0, ra, a0 +remu a0, ra, a5 +remu a0, ra, s4 +remu a0, ra, s9 +remu a0, ra, t6 +remu a0, t0, zero +remu a0, t0, ra +remu a0, t0, t0 +remu a0, t0, a0 +remu a0, t0, a5 +remu a0, t0, s4 +remu a0, t0, s9 +remu a0, t0, t6 +remu a0, a0, zero +remu a0, a0, ra +remu a0, a0, t0 +remu a0, a0, a0 +remu a0, a0, a5 +remu a0, a0, s4 +remu a0, a0, s9 +remu a0, a0, t6 +remu a0, a5, zero +remu a0, a5, ra +remu a0, a5, t0 +remu a0, a5, a0 +remu a0, a5, a5 +remu a0, a5, s4 +remu a0, a5, s9 +remu a0, a5, t6 +remu a0, s4, zero +remu a0, s4, ra +remu a0, s4, t0 +remu a0, s4, a0 +remu a0, s4, a5 +remu a0, s4, s4 +remu a0, s4, s9 +remu a0, s4, t6 +remu a0, s9, zero +remu a0, s9, ra +remu a0, s9, t0 +remu a0, s9, a0 +remu a0, s9, a5 +remu a0, s9, s4 +remu a0, s9, s9 +remu a0, s9, t6 +remu a0, t6, zero +remu a0, t6, ra +remu a0, t6, t0 +remu a0, t6, a0 +remu a0, t6, a5 +remu a0, t6, s4 +remu a0, t6, s9 +remu a0, t6, t6 +remu a5, zero, zero +remu a5, zero, ra +remu a5, zero, t0 +remu a5, zero, a0 +remu a5, zero, a5 +remu a5, zero, s4 +remu a5, zero, s9 +remu a5, zero, t6 +remu a5, ra, zero +remu a5, ra, ra +remu a5, ra, t0 +remu a5, ra, a0 +remu a5, ra, a5 +remu a5, ra, s4 +remu a5, ra, s9 +remu a5, ra, t6 +remu a5, t0, zero +remu a5, t0, ra +remu a5, t0, t0 +remu a5, t0, a0 +remu a5, t0, a5 +remu a5, t0, s4 +remu a5, t0, s9 +remu a5, t0, t6 +remu a5, a0, zero +remu a5, a0, ra +remu a5, a0, t0 +remu a5, a0, a0 +remu a5, a0, a5 +remu a5, a0, s4 +remu a5, a0, s9 +remu a5, a0, t6 +remu a5, a5, zero +remu a5, a5, ra +remu a5, a5, t0 +remu a5, a5, a0 +remu a5, a5, a5 +remu a5, a5, s4 +remu a5, a5, s9 +remu a5, a5, t6 +remu a5, s4, zero +remu a5, s4, ra +remu a5, s4, t0 +remu a5, s4, a0 +remu a5, s4, a5 +remu a5, s4, s4 +remu a5, s4, s9 +remu a5, s4, t6 +remu a5, s9, zero +remu a5, s9, ra +remu a5, s9, t0 +remu a5, s9, a0 +remu a5, s9, a5 +remu a5, s9, s4 +remu a5, s9, s9 +remu a5, s9, t6 +remu a5, t6, zero +remu a5, t6, ra +remu a5, t6, t0 +remu a5, t6, a0 +remu a5, t6, a5 +remu a5, t6, s4 +remu a5, t6, s9 +remu a5, t6, t6 +remu s4, zero, zero +remu s4, zero, ra +remu s4, zero, t0 +remu s4, zero, a0 +remu s4, zero, a5 +remu s4, zero, s4 +remu s4, zero, s9 +remu s4, zero, t6 +remu s4, ra, zero +remu s4, ra, ra +remu s4, ra, t0 +remu s4, ra, a0 +remu s4, ra, a5 +remu s4, ra, s4 +remu s4, ra, s9 +remu s4, ra, t6 +remu s4, t0, zero +remu s4, t0, ra +remu s4, t0, t0 +remu s4, t0, a0 +remu s4, t0, a5 +remu s4, t0, s4 +remu s4, t0, s9 +remu s4, t0, t6 +remu s4, a0, zero +remu s4, a0, ra +remu s4, a0, t0 +remu s4, a0, a0 +remu s4, a0, a5 +remu s4, a0, s4 +remu s4, a0, s9 +remu s4, a0, t6 +remu s4, a5, zero +remu s4, a5, ra +remu s4, a5, t0 +remu s4, a5, a0 +remu s4, a5, a5 +remu s4, a5, s4 +remu s4, a5, s9 +remu s4, a5, t6 +remu s4, s4, zero +remu s4, s4, ra +remu s4, s4, t0 +remu s4, s4, a0 +remu s4, s4, a5 +remu s4, s4, s4 +remu s4, s4, s9 +remu s4, s4, t6 +remu s4, s9, zero +remu s4, s9, ra +remu s4, s9, t0 +remu s4, s9, a0 +remu s4, s9, a5 +remu s4, s9, s4 +remu s4, s9, s9 +remu s4, s9, t6 +remu s4, t6, zero +remu s4, t6, ra +remu s4, t6, t0 +remu s4, t6, a0 +remu s4, t6, a5 +remu s4, t6, s4 +remu s4, t6, s9 +remu s4, t6, t6 +remu s9, zero, zero +remu s9, zero, ra +remu s9, zero, t0 +remu s9, zero, a0 +remu s9, zero, a5 +remu s9, zero, s4 +remu s9, zero, s9 +remu s9, zero, t6 +remu s9, ra, zero +remu s9, ra, ra +remu s9, ra, t0 +remu s9, ra, a0 +remu s9, ra, a5 +remu s9, ra, s4 +remu s9, ra, s9 +remu s9, ra, t6 +remu s9, t0, zero +remu s9, t0, ra +remu s9, t0, t0 +remu s9, t0, a0 +remu s9, t0, a5 +remu s9, t0, s4 +remu s9, t0, s9 +remu s9, t0, t6 +remu s9, a0, zero +remu s9, a0, ra +remu s9, a0, t0 +remu s9, a0, a0 +remu s9, a0, a5 +remu s9, a0, s4 +remu s9, a0, s9 +remu s9, a0, t6 +remu s9, a5, zero +remu s9, a5, ra +remu s9, a5, t0 +remu s9, a5, a0 +remu s9, a5, a5 +remu s9, a5, s4 +remu s9, a5, s9 +remu s9, a5, t6 +remu s9, s4, zero +remu s9, s4, ra +remu s9, s4, t0 +remu s9, s4, a0 +remu s9, s4, a5 +remu s9, s4, s4 +remu s9, s4, s9 +remu s9, s4, t6 +remu s9, s9, zero +remu s9, s9, ra +remu s9, s9, t0 +remu s9, s9, a0 +remu s9, s9, a5 +remu s9, s9, s4 +remu s9, s9, s9 +remu s9, s9, t6 +remu s9, t6, zero +remu s9, t6, ra +remu s9, t6, t0 +remu s9, t6, a0 +remu s9, t6, a5 +remu s9, t6, s4 +remu s9, t6, s9 +remu s9, t6, t6 +remu t6, zero, zero +remu t6, zero, ra +remu t6, zero, t0 +remu t6, zero, a0 +remu t6, zero, a5 +remu t6, zero, s4 +remu t6, zero, s9 +remu t6, zero, t6 +remu t6, ra, zero +remu t6, ra, ra +remu t6, ra, t0 +remu t6, ra, a0 +remu t6, ra, a5 +remu t6, ra, s4 +remu t6, ra, s9 +remu t6, ra, t6 +remu t6, t0, zero +remu t6, t0, ra +remu t6, t0, t0 +remu t6, t0, a0 +remu t6, t0, a5 +remu t6, t0, s4 +remu t6, t0, s9 +remu t6, t0, t6 +remu t6, a0, zero +remu t6, a0, ra +remu t6, a0, t0 +remu t6, a0, a0 +remu t6, a0, a5 +remu t6, a0, s4 +remu t6, a0, s9 +remu t6, a0, t6 +remu t6, a5, zero +remu t6, a5, ra +remu t6, a5, t0 +remu t6, a5, a0 +remu t6, a5, a5 +remu t6, a5, s4 +remu t6, a5, s9 +remu t6, a5, t6 +remu t6, s4, zero +remu t6, s4, ra +remu t6, s4, t0 +remu t6, s4, a0 +remu t6, s4, a5 +remu t6, s4, s4 +remu t6, s4, s9 +remu t6, s4, t6 +remu t6, s9, zero +remu t6, s9, ra +remu t6, s9, t0 +remu t6, s9, a0 +remu t6, s9, a5 +remu t6, s9, s4 +remu t6, s9, s9 +remu t6, s9, t6 +remu t6, t6, zero +remu t6, t6, ra +remu t6, t6, t0 +remu t6, t6, a0 +remu t6, t6, a5 +remu t6, t6, s4 +remu t6, t6, s9 +remu t6, t6, t6 + diff --git a/tests/riscv/m-extension/remu.bin b/tests/riscv/m-extension/remu.bin new file mode 100644 index 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SUMMARY" +echo "==========================================" +echo "" + +# Extract summary information +grep -E "Summary:|Total tests:|Passed:|Failed:" /tmp/riscv_full_test.log | tail -20 + +echo "" +echo "==========================================" +echo "FAILED TESTS (if any)" +echo "==========================================" +grep "^ FAIL:" /tmp/riscv_full_test.log | head -50 + +if [ $EXIT_CODE -eq 0 ]; then + echo "" + echo "✅ All tests passed!" +else + echo "" + echo "❌ Some tests failed. See /tmp/riscv_full_test.log for details." + echo "" + echo "Total failures: $(grep -c '^ FAIL:' /tmp/riscv_full_test.log)" +fi + +exit $EXIT_CODE + diff --git a/tests/riscv/rv32i/.bin b/tests/riscv/rv32i/.bin new file mode 100644 index 0000000000000000000000000000000000000000..5c3e4ce8cf3f4af1eb20c2132b892559cf58f024 GIT binary patch literal 6400 zcmWmGVaMH2y2kNLGBA!tB|l#{ti(^Q=10s`IQm&*l>%{)&I2Ys}ycMtnl&S#_RO=UH{0Rp(iCcl2f+xBbsg zxBax^fIUw3IN9T5kCWg183}*Ge{gEd;4LP6#>pNhdz|cXvd76Dr#pHxk6ZsgPq+TO z%_w{RJ6+$A58d%-|hne8JfsXM3FOakj_V9_KrHGmqQ;zfZUQvg3d~ zF7~+C<6@7C-~AN@|G-aN8Z&s01z&No$Hg8OdtB^svB%|(-pu2+|KHPXzwS67<0|7S z<0|9oZ+=6?KkPyE93rXQPrZ2Gb3hkt9#K!$$! zf5^}eyueGm!X3St$EF{fe&B$NRz@qMmC^c}9}(~u{0nVk2Cp&TBU%})j8;Y~qm|L# z(VKZ}{hyvT{lEdws`IQm&#LpRI?v`4BL0ehqif9I4Mu!I=UH{0Rp(iCo>k{rb$9e; z9-Dq_`hf%XIN9T5kCQ!4e)nf2{0;xXsWF4MnD7}Vdz|cXvd76DCwrXk=*>Jf{n+#a z2kddS$Jriddz}65FUa^i{)=;C2JbNA3(od9+v9AHvpvrCIN#Bmd2ITz=?4zj<6@7C zJuddR_}yPo@DKdNr7?r|Snw4WdtB^svB$+87kgap=*>Jf{n+#a2V`7jTxDEkT>Z^& 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zero, zero, #0xffffffff +xori zero, zero, #0 +xori zero, zero, #1 +xori zero, zero, #2 +xori zero, zero, #4 +xori zero, zero, #8 +xori zero, zero, #0x10 +xori zero, zero, #0x20 +xori zero, zero, #0x40 +xori zero, zero, #0x80 +xori zero, zero, #0x100 +xori zero, zero, #0x200 +xori zero, zero, #0x400 +xori zero, zero, #0x7ff +xori zero, ra, #0xfffff801 +xori zero, ra, #0xfffffc00 +xori zero, ra, #0xfffffe00 +xori zero, ra, #0xffffff00 +xori zero, ra, #0xffffff80 +xori zero, ra, #0xffffffc0 +xori zero, ra, #0xffffffe0 +xori zero, ra, #0xfffffff0 +xori zero, ra, #0xfffffff8 +xori zero, ra, #0xfffffffc +xori zero, ra, #0xfffffffe +xori zero, ra, #0xffffffff +xori zero, ra, #0 +xori zero, ra, #1 +xori zero, ra, #2 +xori zero, ra, #4 +xori zero, ra, #8 +xori zero, ra, #0x10 +xori zero, ra, #0x20 +xori zero, ra, #0x40 +xori zero, ra, #0x80 +xori zero, ra, #0x100 +xori zero, ra, #0x200 +xori zero, ra, #0x400 +xori zero, ra, #0x7ff +xori zero, t0, #0xfffff801 +xori zero, t0, #0xfffffc00 +xori zero, t0, #0xfffffe00 +xori zero, t0, #0xffffff00 +xori zero, t0, #0xffffff80 +xori zero, t0, #0xffffffc0 +xori zero, t0, #0xffffffe0 +xori zero, t0, #0xfffffff0 +xori zero, t0, #0xfffffff8 +xori zero, t0, #0xfffffffc +xori zero, t0, #0xfffffffe +xori zero, t0, #0xffffffff +xori zero, t0, #0 +xori zero, t0, #1 +xori zero, t0, #2 +xori zero, t0, #4 +xori zero, t0, #8 +xori zero, t0, #0x10 +xori zero, t0, #0x20 +xori zero, t0, #0x40 +xori zero, t0, #0x80 +xori zero, t0, #0x100 +xori zero, t0, #0x200 +xori zero, t0, #0x400 +xori zero, t0, #0x7ff +xori zero, a0, #0xfffff801 +xori zero, a0, #0xfffffc00 +xori zero, a0, #0xfffffe00 +xori zero, a0, #0xffffff00 +xori zero, a0, #0xffffff80 +xori zero, a0, #0xffffffc0 +xori zero, a0, #0xffffffe0 +xori zero, a0, #0xfffffff0 +xori zero, a0, #0xfffffff8 +xori zero, a0, #0xfffffffc +xori zero, a0, #0xfffffffe +xori zero, a0, #0xffffffff +xori zero, a0, #0 +xori zero, a0, #1 +xori zero, a0, #2 +xori zero, a0, #4 +xori zero, a0, #8 +xori zero, a0, #0x10 +xori zero, a0, #0x20 +xori zero, a0, #0x40 +xori zero, a0, #0x80 +xori zero, a0, #0x100 +xori zero, a0, #0x200 +xori zero, a0, #0x400 +xori zero, a0, #0x7ff +xori zero, a5, #0xfffff801 +xori zero, a5, #0xfffffc00 +xori zero, a5, #0xfffffe00 +xori zero, a5, #0xffffff00 +xori zero, a5, #0xffffff80 +xori zero, a5, #0xffffffc0 +xori zero, a5, #0xffffffe0 +xori zero, a5, #0xfffffff0 +xori zero, a5, #0xfffffff8 +xori zero, a5, #0xfffffffc +xori zero, a5, #0xfffffffe +xori zero, a5, #0xffffffff +xori zero, a5, #0 +xori zero, a5, #1 +xori zero, a5, #2 +xori zero, a5, #4 +xori zero, a5, #8 +xori zero, a5, #0x10 +xori zero, a5, #0x20 +xori zero, a5, #0x40 +xori zero, a5, #0x80 +xori zero, a5, #0x100 +xori zero, a5, #0x200 +xori zero, a5, #0x400 +xori zero, a5, #0x7ff +xori zero, s4, #0xfffff801 +xori zero, s4, #0xfffffc00 +xori zero, s4, #0xfffffe00 +xori zero, s4, #0xffffff00 +xori zero, s4, #0xffffff80 +xori zero, s4, #0xffffffc0 +xori zero, s4, #0xffffffe0 +xori zero, s4, #0xfffffff0 +xori zero, s4, #0xfffffff8 +xori zero, s4, #0xfffffffc +xori zero, s4, #0xfffffffe +xori zero, s4, #0xffffffff +xori zero, s4, #0 +xori zero, s4, #1 +xori zero, s4, #2 +xori zero, s4, #4 +xori zero, s4, #8 +xori zero, s4, #0x10 +xori zero, s4, #0x20 +xori zero, s4, #0x40 +xori zero, s4, #0x80 +xori zero, s4, #0x100 +xori zero, s4, #0x200 +xori zero, s4, #0x400 +xori zero, s4, #0x7ff +xori zero, s9, #0xfffff801 +xori zero, s9, #0xfffffc00 +xori zero, s9, #0xfffffe00 +xori zero, s9, #0xffffff00 +xori zero, s9, #0xffffff80 +xori zero, s9, #0xffffffc0 +xori zero, s9, #0xffffffe0 +xori zero, s9, #0xfffffff0 +xori zero, s9, #0xfffffff8 +xori zero, s9, #0xfffffffc +xori zero, s9, #0xfffffffe +xori zero, s9, #0xffffffff +xori zero, s9, #0 +xori zero, s9, #1 +xori zero, s9, #2 +xori zero, s9, #4 +xori zero, s9, #8 +xori zero, s9, #0x10 +xori zero, s9, #0x20 +xori zero, s9, #0x40 +xori zero, s9, #0x80 +xori zero, s9, #0x100 +xori zero, s9, #0x200 +xori zero, s9, #0x400 +xori zero, s9, #0x7ff +xori zero, t6, #0xfffff801 +xori zero, t6, #0xfffffc00 +xori zero, t6, #0xfffffe00 +xori zero, t6, #0xffffff00 +xori zero, t6, #0xffffff80 +xori zero, t6, #0xffffffc0 +xori zero, t6, #0xffffffe0 +xori zero, t6, #0xfffffff0 +xori zero, t6, #0xfffffff8 +xori zero, t6, #0xfffffffc +xori zero, t6, #0xfffffffe +xori zero, t6, #0xffffffff +xori zero, t6, #0 +xori zero, t6, #1 +xori zero, t6, #2 +xori zero, t6, #4 +xori zero, t6, #8 +xori zero, t6, #0x10 +xori zero, t6, #0x20 +xori zero, t6, #0x40 +xori zero, t6, #0x80 +xori zero, t6, #0x100 +xori zero, t6, #0x200 +xori zero, t6, #0x400 +xori zero, t6, #0x7ff +xori ra, zero, #0xfffff801 +xori ra, zero, #0xfffffc00 +xori ra, zero, #0xfffffe00 +xori ra, zero, #0xffffff00 +xori ra, zero, #0xffffff80 +xori ra, zero, #0xffffffc0 +xori ra, zero, #0xffffffe0 +xori ra, zero, #0xfffffff0 +xori ra, zero, #0xfffffff8 +xori ra, zero, #0xfffffffc +xori ra, zero, #0xfffffffe +xori ra, zero, #0xffffffff +xori ra, zero, #0 +xori ra, zero, #1 +xori ra, zero, #2 +xori ra, zero, #4 +xori ra, zero, #8 +xori ra, zero, #0x10 +xori ra, zero, #0x20 +xori ra, zero, #0x40 +xori ra, zero, #0x80 +xori ra, zero, #0x100 +xori ra, zero, #0x200 +xori ra, zero, #0x400 +xori ra, zero, #0x7ff +xori ra, ra, #0xfffff801 +xori ra, ra, #0xfffffc00 +xori ra, ra, #0xfffffe00 +xori ra, ra, #0xffffff00 +xori ra, ra, #0xffffff80 +xori ra, ra, #0xffffffc0 +xori ra, ra, #0xffffffe0 +xori ra, ra, #0xfffffff0 +xori ra, ra, #0xfffffff8 +xori ra, ra, #0xfffffffc +xori ra, ra, #0xfffffffe +xori ra, ra, #0xffffffff +xori ra, ra, #0 +xori ra, ra, #1 +xori ra, ra, #2 +xori ra, ra, #4 +xori ra, ra, #8 +xori ra, ra, #0x10 +xori ra, ra, #0x20 +xori ra, ra, #0x40 +xori ra, ra, #0x80 +xori ra, ra, #0x100 +xori ra, ra, #0x200 +xori ra, ra, #0x400 +xori ra, ra, #0x7ff +xori ra, t0, #0xfffff801 +xori ra, t0, #0xfffffc00 +xori ra, t0, #0xfffffe00 +xori ra, t0, #0xffffff00 +xori ra, t0, #0xffffff80 +xori ra, t0, #0xffffffc0 +xori ra, t0, #0xffffffe0 +xori ra, t0, #0xfffffff0 +xori ra, t0, #0xfffffff8 +xori ra, t0, #0xfffffffc +xori ra, t0, #0xfffffffe +xori ra, t0, #0xffffffff +xori ra, t0, #0 +xori ra, t0, #1 +xori ra, t0, #2 +xori ra, t0, #4 +xori ra, t0, #8 +xori ra, t0, #0x10 +xori ra, t0, #0x20 +xori ra, t0, #0x40 +xori ra, t0, #0x80 +xori ra, t0, #0x100 +xori ra, t0, #0x200 +xori ra, t0, #0x400 +xori ra, t0, #0x7ff +xori ra, a0, #0xfffff801 +xori ra, a0, #0xfffffc00 +xori ra, a0, #0xfffffe00 +xori ra, a0, #0xffffff00 +xori ra, a0, #0xffffff80 +xori ra, a0, #0xffffffc0 +xori ra, a0, #0xffffffe0 +xori ra, a0, #0xfffffff0 +xori ra, a0, #0xfffffff8 +xori ra, a0, #0xfffffffc +xori ra, a0, #0xfffffffe +xori ra, a0, #0xffffffff +xori ra, a0, #0 +xori ra, a0, #1 +xori ra, a0, #2 +xori ra, a0, #4 +xori ra, a0, #8 +xori ra, a0, #0x10 +xori ra, a0, #0x20 +xori ra, a0, #0x40 +xori ra, a0, #0x80 +xori ra, a0, #0x100 +xori ra, a0, #0x200 +xori ra, a0, #0x400 +xori ra, a0, #0x7ff +xori ra, a5, #0xfffff801 +xori ra, a5, #0xfffffc00 +xori ra, a5, #0xfffffe00 +xori ra, a5, #0xffffff00 +xori ra, a5, #0xffffff80 +xori ra, a5, #0xffffffc0 +xori ra, a5, #0xffffffe0 +xori ra, a5, #0xfffffff0 +xori ra, a5, #0xfffffff8 +xori ra, a5, #0xfffffffc +xori ra, a5, #0xfffffffe +xori ra, a5, #0xffffffff +xori ra, a5, #0 +xori ra, a5, #1 +xori ra, a5, #2 +xori ra, a5, #4 +xori ra, a5, #8 +xori ra, a5, #0x10 +xori ra, a5, #0x20 +xori ra, a5, #0x40 +xori ra, a5, #0x80 +xori ra, a5, #0x100 +xori ra, a5, #0x200 +xori ra, a5, #0x400 +xori ra, a5, #0x7ff +xori ra, s4, #0xfffff801 +xori ra, s4, #0xfffffc00 +xori ra, s4, #0xfffffe00 +xori ra, s4, #0xffffff00 +xori ra, s4, #0xffffff80 +xori ra, s4, #0xffffffc0 +xori ra, s4, #0xffffffe0 +xori ra, s4, #0xfffffff0 +xori ra, s4, #0xfffffff8 +xori ra, s4, #0xfffffffc +xori ra, s4, #0xfffffffe +xori ra, s4, #0xffffffff +xori ra, s4, #0 +xori ra, s4, #1 +xori ra, s4, #2 +xori ra, s4, #4 +xori ra, s4, #8 +xori ra, s4, #0x10 +xori ra, s4, #0x20 +xori ra, s4, #0x40 +xori ra, s4, #0x80 +xori ra, s4, #0x100 +xori ra, s4, #0x200 +xori ra, s4, #0x400 +xori ra, s4, #0x7ff +xori ra, s9, #0xfffff801 +xori ra, s9, #0xfffffc00 +xori ra, s9, #0xfffffe00 +xori ra, s9, #0xffffff00 +xori ra, s9, #0xffffff80 +xori ra, s9, #0xffffffc0 +xori ra, s9, #0xffffffe0 +xori ra, s9, #0xfffffff0 +xori ra, s9, #0xfffffff8 +xori ra, s9, #0xfffffffc +xori ra, s9, #0xfffffffe +xori ra, s9, #0xffffffff +xori ra, s9, #0 +xori ra, s9, #1 +xori ra, s9, #2 +xori ra, s9, #4 +xori ra, s9, #8 +xori ra, s9, #0x10 +xori ra, s9, #0x20 +xori ra, s9, #0x40 +xori ra, s9, #0x80 +xori ra, s9, #0x100 +xori ra, s9, #0x200 +xori ra, s9, #0x400 +xori ra, s9, #0x7ff +xori ra, t6, #0xfffff801 +xori ra, t6, #0xfffffc00 +xori ra, t6, #0xfffffe00 +xori ra, t6, #0xffffff00 +xori ra, t6, #0xffffff80 +xori ra, t6, #0xffffffc0 +xori ra, t6, #0xffffffe0 +xori ra, t6, #0xfffffff0 +xori ra, t6, #0xfffffff8 +xori ra, t6, #0xfffffffc +xori ra, t6, #0xfffffffe +xori ra, t6, #0xffffffff +xori ra, t6, #0 +xori ra, t6, #1 +xori ra, t6, #2 +xori ra, t6, #4 +xori ra, t6, #8 +xori ra, t6, #0x10 +xori ra, t6, #0x20 +xori ra, t6, #0x40 +xori ra, t6, #0x80 +xori ra, t6, #0x100 +xori ra, t6, #0x200 +xori ra, t6, #0x400 +xori ra, t6, #0x7ff +xori t0, zero, #0xfffff801 +xori t0, zero, #0xfffffc00 +xori t0, zero, #0xfffffe00 +xori t0, zero, #0xffffff00 +xori t0, zero, #0xffffff80 +xori t0, zero, #0xffffffc0 +xori t0, zero, #0xffffffe0 +xori t0, zero, #0xfffffff0 +xori t0, zero, #0xfffffff8 +xori t0, zero, #0xfffffffc +xori t0, zero, #0xfffffffe +xori t0, zero, #0xffffffff +xori t0, zero, #0 +xori t0, zero, #1 +xori t0, zero, #2 +xori t0, zero, #4 +xori t0, zero, #8 +xori t0, zero, #0x10 +xori t0, zero, #0x20 +xori t0, zero, #0x40 +xori t0, zero, #0x80 +xori t0, zero, #0x100 +xori t0, zero, #0x200 +xori t0, zero, #0x400 +xori t0, zero, #0x7ff +xori t0, ra, #0xfffff801 +xori t0, ra, #0xfffffc00 +xori t0, ra, #0xfffffe00 +xori t0, ra, #0xffffff00 +xori t0, ra, #0xffffff80 +xori t0, ra, #0xffffffc0 +xori t0, ra, #0xffffffe0 +xori t0, ra, #0xfffffff0 +xori t0, ra, #0xfffffff8 +xori t0, ra, #0xfffffffc +xori t0, ra, #0xfffffffe +xori t0, ra, #0xffffffff +xori t0, ra, #0 +xori t0, ra, #1 +xori t0, ra, #2 +xori t0, ra, #4 +xori t0, ra, #8 +xori t0, ra, #0x10 +xori t0, ra, #0x20 +xori t0, ra, #0x40 +xori t0, ra, #0x80 +xori t0, ra, #0x100 +xori t0, ra, #0x200 +xori t0, ra, #0x400 +xori t0, ra, #0x7ff +xori t0, t0, #0xfffff801 +xori t0, t0, #0xfffffc00 +xori t0, t0, #0xfffffe00 +xori t0, t0, #0xffffff00 +xori t0, t0, #0xffffff80 +xori t0, t0, #0xffffffc0 +xori t0, t0, #0xffffffe0 +xori t0, t0, #0xfffffff0 +xori t0, t0, #0xfffffff8 +xori t0, t0, #0xfffffffc +xori t0, t0, #0xfffffffe +xori t0, t0, #0xffffffff +xori t0, t0, #0 +xori t0, t0, #1 +xori t0, t0, #2 +xori t0, t0, #4 +xori t0, t0, #8 +xori t0, t0, #0x10 +xori t0, t0, #0x20 +xori t0, t0, #0x40 +xori t0, t0, #0x80 +xori t0, t0, #0x100 +xori t0, t0, #0x200 +xori t0, t0, #0x400 +xori t0, t0, #0x7ff +xori t0, a0, #0xfffff801 +xori t0, a0, #0xfffffc00 +xori t0, a0, #0xfffffe00 +xori t0, a0, #0xffffff00 +xori t0, a0, #0xffffff80 +xori t0, a0, #0xffffffc0 +xori t0, a0, #0xffffffe0 +xori t0, a0, #0xfffffff0 +xori t0, a0, #0xfffffff8 +xori t0, a0, #0xfffffffc +xori t0, a0, #0xfffffffe +xori t0, a0, #0xffffffff +xori t0, a0, #0 +xori t0, a0, #1 +xori t0, a0, #2 +xori t0, a0, #4 +xori t0, a0, #8 +xori t0, a0, #0x10 +xori t0, a0, #0x20 +xori t0, a0, #0x40 +xori t0, a0, #0x80 +xori t0, a0, #0x100 +xori t0, a0, #0x200 +xori t0, a0, #0x400 +xori t0, a0, #0x7ff +xori t0, a5, #0xfffff801 +xori t0, a5, #0xfffffc00 +xori t0, a5, #0xfffffe00 +xori t0, a5, #0xffffff00 +xori t0, a5, #0xffffff80 +xori t0, a5, #0xffffffc0 +xori t0, a5, #0xffffffe0 +xori t0, a5, #0xfffffff0 +xori t0, a5, #0xfffffff8 +xori t0, a5, #0xfffffffc +xori t0, a5, #0xfffffffe +xori t0, a5, #0xffffffff +xori t0, a5, #0 +xori t0, a5, #1 +xori t0, a5, #2 +xori t0, a5, #4 +xori t0, a5, #8 +xori t0, a5, #0x10 +xori t0, a5, #0x20 +xori t0, a5, #0x40 +xori t0, a5, #0x80 +xori t0, a5, #0x100 +xori t0, a5, #0x200 +xori t0, a5, #0x400 +xori t0, a5, #0x7ff +xori t0, s4, #0xfffff801 +xori t0, s4, #0xfffffc00 +xori t0, s4, #0xfffffe00 +xori t0, s4, #0xffffff00 +xori t0, s4, #0xffffff80 +xori t0, s4, #0xffffffc0 +xori t0, s4, #0xffffffe0 +xori t0, s4, #0xfffffff0 +xori t0, s4, #0xfffffff8 +xori t0, s4, #0xfffffffc +xori t0, s4, #0xfffffffe +xori t0, s4, #0xffffffff +xori t0, s4, #0 +xori t0, s4, #1 +xori t0, s4, #2 +xori t0, s4, #4 +xori t0, s4, #8 +xori t0, s4, #0x10 +xori t0, s4, #0x20 +xori t0, s4, #0x40 +xori t0, s4, #0x80 +xori t0, s4, #0x100 +xori t0, s4, #0x200 +xori t0, s4, #0x400 +xori t0, s4, #0x7ff +xori t0, s9, #0xfffff801 +xori t0, s9, #0xfffffc00 +xori t0, s9, #0xfffffe00 +xori t0, s9, #0xffffff00 +xori t0, s9, #0xffffff80 +xori t0, s9, #0xffffffc0 +xori t0, s9, #0xffffffe0 +xori t0, s9, #0xfffffff0 +xori t0, s9, #0xfffffff8 +xori t0, s9, #0xfffffffc +xori t0, s9, #0xfffffffe +xori t0, s9, #0xffffffff +xori t0, s9, #0 +xori t0, s9, #1 +xori t0, s9, #2 +xori t0, s9, #4 +xori t0, s9, #8 +xori t0, s9, #0x10 +xori t0, s9, #0x20 +xori t0, s9, #0x40 +xori t0, s9, #0x80 +xori t0, s9, #0x100 +xori t0, s9, #0x200 +xori t0, s9, #0x400 +xori t0, s9, #0x7ff +xori t0, t6, #0xfffff801 +xori t0, t6, #0xfffffc00 +xori t0, t6, #0xfffffe00 +xori t0, t6, #0xffffff00 +xori t0, t6, #0xffffff80 +xori t0, t6, #0xffffffc0 +xori t0, t6, #0xffffffe0 +xori t0, t6, #0xfffffff0 +xori t0, t6, #0xfffffff8 +xori t0, t6, #0xfffffffc +xori t0, t6, #0xfffffffe +xori t0, t6, #0xffffffff +xori t0, t6, #0 +xori t0, t6, #1 +xori t0, t6, #2 +xori t0, t6, #4 +xori t0, t6, #8 +xori t0, t6, #0x10 +xori t0, t6, #0x20 +xori t0, t6, #0x40 +xori t0, t6, #0x80 +xori t0, t6, #0x100 +xori t0, t6, #0x200 +xori t0, t6, #0x400 +xori t0, t6, #0x7ff +xori a0, zero, #0xfffff801 +xori a0, zero, #0xfffffc00 +xori a0, zero, #0xfffffe00 +xori a0, zero, #0xffffff00 +xori a0, zero, #0xffffff80 +xori a0, zero, #0xffffffc0 +xori a0, zero, #0xffffffe0 +xori a0, zero, #0xfffffff0 +xori a0, zero, #0xfffffff8 +xori a0, zero, #0xfffffffc +xori a0, zero, #0xfffffffe +xori a0, zero, #0xffffffff +xori a0, zero, #0 +xori a0, zero, #1 +xori a0, zero, #2 +xori a0, zero, #4 +xori a0, zero, #8 +xori a0, zero, #0x10 +xori a0, zero, #0x20 +xori a0, zero, #0x40 +xori a0, zero, #0x80 +xori a0, zero, #0x100 +xori a0, zero, #0x200 +xori a0, zero, #0x400 +xori a0, zero, #0x7ff +xori a0, ra, #0xfffff801 +xori a0, ra, #0xfffffc00 +xori a0, ra, #0xfffffe00 +xori a0, ra, #0xffffff00 +xori a0, ra, #0xffffff80 +xori a0, ra, #0xffffffc0 +xori a0, ra, #0xffffffe0 +xori a0, ra, #0xfffffff0 +xori a0, ra, #0xfffffff8 +xori a0, ra, #0xfffffffc +xori a0, ra, #0xfffffffe +xori a0, ra, #0xffffffff +xori a0, ra, #0 +xori a0, ra, #1 +xori a0, ra, #2 +xori a0, ra, #4 +xori a0, ra, #8 +xori a0, ra, #0x10 +xori a0, ra, #0x20 +xori a0, ra, #0x40 +xori a0, ra, #0x80 +xori a0, ra, #0x100 +xori a0, ra, #0x200 +xori a0, ra, #0x400 +xori a0, ra, #0x7ff +xori a0, t0, #0xfffff801 +xori a0, t0, #0xfffffc00 +xori a0, t0, #0xfffffe00 +xori a0, t0, #0xffffff00 +xori a0, t0, #0xffffff80 +xori a0, t0, #0xffffffc0 +xori a0, t0, #0xffffffe0 +xori a0, t0, #0xfffffff0 +xori a0, t0, #0xfffffff8 +xori a0, t0, #0xfffffffc +xori a0, t0, #0xfffffffe +xori a0, t0, #0xffffffff +xori a0, t0, #0 +xori a0, t0, #1 +xori a0, t0, #2 +xori a0, t0, #4 +xori a0, t0, #8 +xori a0, t0, #0x10 +xori a0, t0, #0x20 +xori a0, t0, #0x40 +xori a0, t0, #0x80 +xori a0, t0, #0x100 +xori a0, t0, #0x200 +xori a0, t0, #0x400 +xori a0, t0, #0x7ff +xori a0, a0, #0xfffff801 +xori a0, a0, #0xfffffc00 +xori a0, a0, #0xfffffe00 +xori a0, a0, #0xffffff00 +xori a0, a0, #0xffffff80 +xori a0, a0, #0xffffffc0 +xori a0, a0, #0xffffffe0 +xori a0, a0, #0xfffffff0 +xori a0, a0, #0xfffffff8 +xori a0, a0, #0xfffffffc +xori a0, a0, #0xfffffffe +xori a0, a0, #0xffffffff +xori a0, a0, #0 +xori a0, a0, #1 +xori a0, a0, #2 +xori a0, a0, #4 +xori a0, a0, #8 +xori a0, a0, #0x10 +xori a0, a0, #0x20 +xori a0, a0, #0x40 +xori a0, a0, #0x80 +xori a0, a0, #0x100 +xori a0, a0, #0x200 +xori a0, a0, #0x400 +xori a0, a0, #0x7ff +xori a0, a5, #0xfffff801 +xori a0, a5, #0xfffffc00 +xori a0, a5, #0xfffffe00 +xori a0, a5, #0xffffff00 +xori a0, a5, #0xffffff80 +xori a0, a5, #0xffffffc0 +xori a0, a5, #0xffffffe0 +xori a0, a5, #0xfffffff0 +xori a0, a5, #0xfffffff8 +xori a0, a5, #0xfffffffc +xori a0, a5, #0xfffffffe +xori a0, a5, #0xffffffff +xori a0, a5, #0 +xori a0, a5, #1 +xori a0, a5, #2 +xori a0, a5, #4 +xori a0, a5, #8 +xori a0, a5, #0x10 +xori a0, a5, #0x20 +xori a0, a5, #0x40 +xori a0, a5, #0x80 +xori a0, a5, #0x100 +xori a0, a5, #0x200 +xori a0, a5, #0x400 +xori a0, a5, #0x7ff +xori a0, s4, #0xfffff801 +xori a0, s4, #0xfffffc00 +xori a0, s4, #0xfffffe00 +xori a0, s4, #0xffffff00 +xori a0, s4, #0xffffff80 +xori a0, s4, #0xffffffc0 +xori a0, s4, #0xffffffe0 +xori a0, s4, #0xfffffff0 +xori a0, s4, #0xfffffff8 +xori a0, s4, #0xfffffffc +xori a0, s4, #0xfffffffe +xori a0, s4, #0xffffffff +xori a0, s4, #0 +xori a0, s4, #1 +xori a0, s4, #2 +xori a0, s4, #4 +xori a0, s4, #8 +xori a0, s4, #0x10 +xori a0, s4, #0x20 +xori a0, s4, #0x40 +xori a0, s4, #0x80 +xori a0, s4, #0x100 +xori a0, s4, #0x200 +xori a0, s4, #0x400 +xori a0, s4, #0x7ff +xori a0, s9, #0xfffff801 +xori a0, s9, #0xfffffc00 +xori a0, s9, #0xfffffe00 +xori a0, s9, #0xffffff00 +xori a0, s9, #0xffffff80 +xori a0, s9, #0xffffffc0 +xori a0, s9, #0xffffffe0 +xori a0, s9, #0xfffffff0 +xori a0, s9, #0xfffffff8 +xori a0, s9, #0xfffffffc +xori a0, s9, #0xfffffffe +xori a0, s9, #0xffffffff +xori a0, s9, #0 +xori a0, s9, #1 +xori a0, s9, #2 +xori a0, s9, #4 +xori a0, s9, #8 +xori a0, s9, #0x10 +xori a0, s9, #0x20 +xori a0, s9, #0x40 +xori a0, s9, #0x80 +xori a0, s9, #0x100 +xori a0, s9, #0x200 +xori a0, s9, #0x400 +xori a0, s9, #0x7ff +xori a0, t6, #0xfffff801 +xori a0, t6, #0xfffffc00 +xori a0, t6, #0xfffffe00 +xori a0, t6, #0xffffff00 +xori a0, t6, #0xffffff80 +xori a0, t6, #0xffffffc0 +xori a0, t6, #0xffffffe0 +xori a0, t6, #0xfffffff0 +xori a0, t6, #0xfffffff8 +xori a0, t6, #0xfffffffc +xori a0, t6, #0xfffffffe +xori a0, t6, #0xffffffff +xori a0, t6, #0 +xori a0, t6, #1 +xori a0, t6, #2 +xori a0, t6, #4 +xori a0, t6, #8 +xori a0, t6, #0x10 +xori a0, t6, #0x20 +xori a0, t6, #0x40 +xori a0, t6, #0x80 +xori a0, t6, #0x100 +xori a0, t6, #0x200 +xori a0, t6, #0x400 +xori a0, t6, #0x7ff +xori a5, zero, #0xfffff801 +xori a5, zero, #0xfffffc00 +xori a5, zero, #0xfffffe00 +xori a5, zero, #0xffffff00 +xori a5, zero, #0xffffff80 +xori a5, zero, #0xffffffc0 +xori a5, zero, #0xffffffe0 +xori a5, zero, #0xfffffff0 +xori a5, zero, #0xfffffff8 +xori a5, zero, #0xfffffffc +xori a5, zero, #0xfffffffe +xori a5, zero, #0xffffffff +xori a5, zero, #0 +xori a5, zero, #1 +xori a5, zero, #2 +xori a5, zero, #4 +xori a5, zero, #8 +xori a5, zero, #0x10 +xori a5, zero, #0x20 +xori a5, zero, #0x40 +xori a5, zero, #0x80 +xori a5, zero, #0x100 +xori a5, zero, #0x200 +xori a5, zero, #0x400 +xori a5, zero, #0x7ff +xori a5, ra, #0xfffff801 +xori a5, ra, #0xfffffc00 +xori a5, ra, #0xfffffe00 +xori a5, ra, #0xffffff00 +xori a5, ra, #0xffffff80 +xori a5, ra, #0xffffffc0 +xori a5, ra, #0xffffffe0 +xori a5, ra, #0xfffffff0 +xori a5, ra, #0xfffffff8 +xori a5, ra, #0xfffffffc +xori a5, ra, #0xfffffffe +xori a5, ra, #0xffffffff +xori a5, ra, #0 +xori a5, ra, #1 +xori a5, ra, #2 +xori a5, ra, #4 +xori a5, ra, #8 +xori a5, ra, #0x10 +xori a5, ra, #0x20 +xori a5, ra, #0x40 +xori a5, ra, #0x80 +xori a5, ra, #0x100 +xori a5, ra, #0x200 +xori a5, ra, #0x400 +xori a5, ra, #0x7ff +xori a5, t0, #0xfffff801 +xori a5, t0, #0xfffffc00 +xori a5, t0, #0xfffffe00 +xori a5, t0, #0xffffff00 +xori a5, t0, #0xffffff80 +xori a5, t0, #0xffffffc0 +xori a5, t0, #0xffffffe0 +xori a5, t0, #0xfffffff0 +xori a5, t0, #0xfffffff8 +xori a5, t0, #0xfffffffc +xori a5, t0, #0xfffffffe +xori a5, t0, #0xffffffff +xori a5, t0, #0 +xori a5, t0, #1 +xori a5, t0, #2 +xori a5, t0, #4 +xori a5, t0, #8 +xori a5, t0, #0x10 +xori a5, t0, #0x20 +xori a5, t0, #0x40 +xori a5, t0, #0x80 +xori a5, t0, #0x100 +xori a5, t0, #0x200 +xori a5, t0, #0x400 +xori a5, t0, #0x7ff +xori a5, a0, #0xfffff801 +xori a5, a0, #0xfffffc00 +xori a5, a0, #0xfffffe00 +xori a5, a0, #0xffffff00 +xori a5, a0, #0xffffff80 +xori a5, a0, #0xffffffc0 +xori a5, a0, #0xffffffe0 +xori a5, a0, #0xfffffff0 +xori a5, a0, #0xfffffff8 +xori a5, a0, #0xfffffffc +xori a5, a0, #0xfffffffe +xori a5, a0, #0xffffffff +xori a5, a0, #0 +xori a5, a0, #1 +xori a5, a0, #2 +xori a5, a0, #4 +xori a5, a0, #8 +xori a5, a0, #0x10 +xori a5, a0, #0x20 +xori a5, a0, #0x40 +xori a5, a0, #0x80 +xori a5, a0, #0x100 +xori a5, a0, #0x200 +xori a5, a0, #0x400 +xori a5, a0, #0x7ff +xori a5, a5, #0xfffff801 +xori a5, a5, #0xfffffc00 +xori a5, a5, #0xfffffe00 +xori a5, a5, #0xffffff00 +xori a5, a5, #0xffffff80 +xori a5, a5, #0xffffffc0 +xori a5, a5, #0xffffffe0 +xori a5, a5, #0xfffffff0 +xori a5, a5, #0xfffffff8 +xori a5, a5, #0xfffffffc +xori a5, a5, #0xfffffffe +xori a5, a5, #0xffffffff +xori a5, a5, #0 +xori a5, a5, #1 +xori a5, a5, #2 +xori a5, a5, #4 +xori a5, a5, #8 +xori a5, a5, #0x10 +xori a5, a5, #0x20 +xori a5, a5, #0x40 +xori a5, a5, #0x80 +xori a5, a5, #0x100 +xori a5, a5, #0x200 +xori a5, a5, #0x400 +xori a5, a5, #0x7ff +xori a5, s4, #0xfffff801 +xori a5, s4, #0xfffffc00 +xori a5, s4, #0xfffffe00 +xori a5, s4, #0xffffff00 +xori a5, s4, #0xffffff80 +xori a5, s4, #0xffffffc0 +xori a5, s4, #0xffffffe0 +xori a5, s4, #0xfffffff0 +xori a5, s4, #0xfffffff8 +xori a5, s4, #0xfffffffc +xori a5, s4, #0xfffffffe +xori a5, s4, #0xffffffff +xori a5, s4, #0 +xori a5, s4, #1 +xori a5, s4, #2 +xori a5, s4, #4 +xori a5, s4, #8 +xori a5, s4, #0x10 +xori a5, s4, #0x20 +xori a5, s4, #0x40 +xori a5, s4, #0x80 +xori a5, s4, #0x100 +xori a5, s4, #0x200 +xori a5, s4, #0x400 +xori a5, s4, #0x7ff +xori a5, s9, #0xfffff801 +xori a5, s9, #0xfffffc00 +xori a5, s9, #0xfffffe00 +xori a5, s9, #0xffffff00 +xori a5, s9, #0xffffff80 +xori a5, s9, #0xffffffc0 +xori a5, s9, #0xffffffe0 +xori a5, s9, #0xfffffff0 +xori a5, s9, #0xfffffff8 +xori a5, s9, #0xfffffffc +xori a5, s9, #0xfffffffe +xori a5, s9, #0xffffffff +xori a5, s9, #0 +xori a5, s9, #1 +xori a5, s9, #2 +xori a5, s9, #4 +xori a5, s9, #8 +xori a5, s9, #0x10 +xori a5, s9, #0x20 +xori a5, s9, #0x40 +xori a5, s9, #0x80 +xori a5, s9, #0x100 +xori a5, s9, #0x200 +xori a5, s9, #0x400 +xori a5, s9, #0x7ff +xori a5, t6, #0xfffff801 +xori a5, t6, #0xfffffc00 +xori a5, t6, #0xfffffe00 +xori a5, t6, #0xffffff00 +xori a5, t6, #0xffffff80 +xori a5, t6, #0xffffffc0 +xori a5, t6, #0xffffffe0 +xori a5, t6, #0xfffffff0 +xori a5, t6, #0xfffffff8 +xori a5, t6, #0xfffffffc +xori a5, t6, #0xfffffffe +xori a5, t6, #0xffffffff +xori a5, t6, #0 +xori a5, t6, #1 +xori a5, t6, #2 +xori a5, t6, #4 +xori a5, t6, #8 +xori a5, t6, #0x10 +xori a5, t6, #0x20 +xori a5, t6, #0x40 +xori a5, t6, #0x80 +xori a5, t6, #0x100 +xori a5, t6, #0x200 +xori a5, t6, #0x400 +xori a5, t6, #0x7ff +xori s4, zero, #0xfffff801 +xori s4, zero, #0xfffffc00 +xori s4, zero, #0xfffffe00 +xori s4, zero, #0xffffff00 +xori s4, zero, #0xffffff80 +xori s4, zero, #0xffffffc0 +xori s4, zero, #0xffffffe0 +xori s4, zero, #0xfffffff0 +xori s4, zero, #0xfffffff8 +xori s4, zero, #0xfffffffc +xori s4, zero, #0xfffffffe +xori s4, zero, #0xffffffff +xori s4, zero, #0 +xori s4, zero, #1 +xori s4, zero, #2 +xori s4, zero, #4 +xori s4, zero, #8 +xori s4, zero, #0x10 +xori s4, zero, #0x20 +xori s4, zero, #0x40 +xori s4, zero, #0x80 +xori s4, zero, #0x100 +xori s4, zero, #0x200 +xori s4, zero, #0x400 +xori s4, zero, #0x7ff +xori s4, ra, #0xfffff801 +xori s4, ra, #0xfffffc00 +xori s4, ra, #0xfffffe00 +xori s4, ra, #0xffffff00 +xori s4, ra, #0xffffff80 +xori s4, ra, #0xffffffc0 +xori s4, ra, #0xffffffe0 +xori s4, ra, #0xfffffff0 +xori s4, ra, #0xfffffff8 +xori s4, ra, #0xfffffffc +xori s4, ra, #0xfffffffe +xori s4, ra, #0xffffffff +xori s4, ra, #0 +xori s4, ra, #1 +xori s4, ra, #2 +xori s4, ra, #4 +xori s4, ra, #8 +xori s4, ra, #0x10 +xori s4, ra, #0x20 +xori s4, ra, #0x40 +xori s4, ra, #0x80 +xori s4, ra, #0x100 +xori s4, ra, #0x200 +xori s4, ra, #0x400 +xori s4, ra, #0x7ff +xori s4, t0, #0xfffff801 +xori s4, t0, #0xfffffc00 +xori s4, t0, #0xfffffe00 +xori s4, t0, #0xffffff00 +xori s4, t0, #0xffffff80 +xori s4, t0, #0xffffffc0 +xori s4, t0, #0xffffffe0 +xori s4, t0, #0xfffffff0 +xori s4, t0, #0xfffffff8 +xori s4, t0, #0xfffffffc +xori s4, t0, #0xfffffffe +xori s4, t0, #0xffffffff +xori s4, t0, #0 +xori s4, t0, #1 +xori s4, t0, #2 +xori s4, t0, #4 +xori s4, t0, #8 +xori s4, t0, #0x10 +xori s4, t0, #0x20 +xori s4, t0, #0x40 +xori s4, t0, #0x80 +xori s4, t0, #0x100 +xori s4, t0, #0x200 +xori s4, t0, #0x400 +xori s4, t0, #0x7ff +xori s4, a0, #0xfffff801 +xori s4, a0, #0xfffffc00 +xori s4, a0, #0xfffffe00 +xori s4, a0, #0xffffff00 +xori s4, a0, #0xffffff80 +xori s4, a0, #0xffffffc0 +xori s4, a0, #0xffffffe0 +xori s4, a0, #0xfffffff0 +xori s4, a0, #0xfffffff8 +xori s4, a0, #0xfffffffc +xori s4, a0, #0xfffffffe +xori s4, a0, #0xffffffff +xori s4, a0, #0 +xori s4, a0, #1 +xori s4, a0, #2 +xori s4, a0, #4 +xori s4, a0, #8 +xori s4, a0, #0x10 +xori s4, a0, #0x20 +xori s4, a0, #0x40 +xori s4, a0, #0x80 +xori s4, a0, #0x100 +xori s4, a0, #0x200 +xori s4, a0, #0x400 +xori s4, a0, #0x7ff +xori s4, a5, #0xfffff801 +xori s4, a5, #0xfffffc00 +xori s4, a5, #0xfffffe00 +xori s4, a5, #0xffffff00 +xori s4, a5, #0xffffff80 +xori s4, a5, #0xffffffc0 +xori s4, a5, #0xffffffe0 +xori s4, a5, #0xfffffff0 +xori s4, a5, #0xfffffff8 +xori s4, a5, #0xfffffffc +xori s4, a5, #0xfffffffe +xori s4, a5, #0xffffffff +xori s4, a5, #0 +xori s4, a5, #1 +xori s4, a5, #2 +xori s4, a5, #4 +xori s4, a5, #8 +xori s4, a5, #0x10 +xori s4, a5, #0x20 +xori s4, a5, #0x40 +xori s4, a5, #0x80 +xori s4, a5, #0x100 +xori s4, a5, #0x200 +xori s4, a5, #0x400 +xori s4, a5, #0x7ff +xori s4, s4, #0xfffff801 +xori s4, s4, #0xfffffc00 +xori s4, s4, #0xfffffe00 +xori s4, s4, #0xffffff00 +xori s4, s4, #0xffffff80 +xori s4, s4, #0xffffffc0 +xori s4, s4, #0xffffffe0 +xori s4, s4, #0xfffffff0 +xori s4, s4, #0xfffffff8 +xori s4, s4, #0xfffffffc +xori s4, s4, #0xfffffffe +xori s4, s4, #0xffffffff +xori s4, s4, #0 +xori s4, s4, #1 +xori s4, s4, #2 +xori s4, s4, #4 +xori s4, s4, #8 +xori s4, s4, #0x10 +xori s4, s4, #0x20 +xori s4, s4, #0x40 +xori s4, s4, #0x80 +xori s4, s4, #0x100 +xori s4, s4, #0x200 +xori s4, s4, #0x400 +xori s4, s4, #0x7ff +xori s4, s9, #0xfffff801 +xori s4, s9, #0xfffffc00 +xori s4, s9, #0xfffffe00 +xori s4, s9, #0xffffff00 +xori s4, s9, #0xffffff80 +xori s4, s9, #0xffffffc0 +xori s4, s9, #0xffffffe0 +xori s4, s9, #0xfffffff0 +xori s4, s9, #0xfffffff8 +xori s4, s9, #0xfffffffc +xori s4, s9, #0xfffffffe +xori s4, s9, #0xffffffff +xori s4, s9, #0 +xori s4, s9, #1 +xori s4, s9, #2 +xori s4, s9, #4 +xori s4, s9, #8 +xori s4, s9, #0x10 +xori s4, s9, #0x20 +xori s4, s9, #0x40 +xori s4, s9, #0x80 +xori s4, s9, #0x100 +xori s4, s9, #0x200 +xori s4, s9, #0x400 +xori s4, s9, #0x7ff +xori s4, t6, #0xfffff801 +xori s4, t6, #0xfffffc00 +xori s4, t6, #0xfffffe00 +xori s4, t6, #0xffffff00 +xori s4, t6, #0xffffff80 +xori s4, t6, #0xffffffc0 +xori s4, t6, #0xffffffe0 +xori s4, t6, #0xfffffff0 +xori s4, t6, #0xfffffff8 +xori s4, t6, #0xfffffffc +xori s4, t6, #0xfffffffe +xori s4, t6, #0xffffffff +xori s4, t6, #0 +xori s4, t6, #1 +xori s4, t6, #2 +xori s4, t6, #4 +xori s4, t6, #8 +xori s4, t6, #0x10 +xori s4, t6, #0x20 +xori s4, t6, #0x40 +xori s4, t6, #0x80 +xori s4, t6, #0x100 +xori s4, t6, #0x200 +xori s4, t6, #0x400 +xori s4, t6, #0x7ff +xori s9, zero, #0xfffff801 +xori s9, zero, #0xfffffc00 +xori s9, zero, #0xfffffe00 +xori s9, zero, #0xffffff00 +xori s9, zero, #0xffffff80 +xori s9, zero, #0xffffffc0 +xori s9, zero, #0xffffffe0 +xori s9, zero, #0xfffffff0 +xori s9, zero, #0xfffffff8 +xori s9, zero, #0xfffffffc +xori s9, zero, #0xfffffffe +xori s9, zero, #0xffffffff +xori s9, zero, #0 +xori s9, zero, #1 +xori s9, zero, #2 +xori s9, zero, #4 +xori s9, zero, #8 +xori s9, zero, #0x10 +xori s9, zero, #0x20 +xori s9, zero, #0x40 +xori s9, zero, #0x80 +xori s9, zero, #0x100 +xori s9, zero, #0x200 +xori s9, zero, #0x400 +xori s9, zero, #0x7ff +xori s9, ra, #0xfffff801 +xori s9, ra, #0xfffffc00 +xori s9, ra, #0xfffffe00 +xori s9, ra, #0xffffff00 +xori s9, ra, #0xffffff80 +xori s9, ra, #0xffffffc0 +xori s9, ra, #0xffffffe0 +xori s9, ra, #0xfffffff0 +xori s9, ra, #0xfffffff8 +xori s9, ra, #0xfffffffc +xori s9, ra, #0xfffffffe +xori s9, ra, #0xffffffff +xori s9, ra, #0 +xori s9, ra, #1 +xori s9, ra, #2 +xori s9, ra, #4 +xori s9, ra, #8 +xori s9, ra, #0x10 +xori s9, ra, #0x20 +xori s9, ra, #0x40 +xori s9, ra, #0x80 +xori s9, ra, #0x100 +xori s9, ra, #0x200 +xori s9, ra, #0x400 +xori s9, ra, #0x7ff +xori s9, t0, #0xfffff801 +xori s9, t0, #0xfffffc00 +xori s9, t0, #0xfffffe00 +xori s9, t0, #0xffffff00 +xori s9, t0, #0xffffff80 +xori s9, t0, #0xffffffc0 +xori s9, t0, #0xffffffe0 +xori s9, t0, #0xfffffff0 +xori s9, t0, #0xfffffff8 +xori s9, t0, #0xfffffffc +xori s9, t0, #0xfffffffe +xori s9, t0, #0xffffffff +xori s9, t0, #0 +xori s9, t0, #1 +xori s9, t0, #2 +xori s9, t0, #4 +xori s9, t0, #8 +xori s9, t0, #0x10 +xori s9, t0, #0x20 +xori s9, t0, #0x40 +xori s9, t0, #0x80 +xori s9, t0, #0x100 +xori s9, t0, #0x200 +xori s9, t0, #0x400 +xori s9, t0, #0x7ff +xori s9, a0, #0xfffff801 +xori s9, a0, #0xfffffc00 +xori s9, a0, #0xfffffe00 +xori s9, a0, #0xffffff00 +xori s9, a0, #0xffffff80 +xori s9, a0, #0xffffffc0 +xori s9, a0, #0xffffffe0 +xori s9, a0, #0xfffffff0 +xori s9, a0, #0xfffffff8 +xori s9, a0, #0xfffffffc +xori s9, a0, #0xfffffffe +xori s9, a0, #0xffffffff +xori s9, a0, #0 +xori s9, a0, #1 +xori s9, a0, #2 +xori s9, a0, #4 +xori s9, a0, #8 +xori s9, a0, #0x10 +xori s9, a0, #0x20 +xori s9, a0, #0x40 +xori s9, a0, #0x80 +xori s9, a0, #0x100 +xori s9, a0, #0x200 +xori s9, a0, #0x400 +xori s9, a0, #0x7ff +xori s9, a5, #0xfffff801 +xori s9, a5, #0xfffffc00 +xori s9, a5, #0xfffffe00 +xori s9, a5, #0xffffff00 +xori s9, a5, #0xffffff80 +xori s9, a5, #0xffffffc0 +xori s9, a5, #0xffffffe0 +xori s9, a5, #0xfffffff0 +xori s9, a5, #0xfffffff8 +xori s9, a5, #0xfffffffc +xori s9, a5, #0xfffffffe +xori s9, a5, #0xffffffff +xori s9, a5, #0 +xori s9, a5, #1 +xori s9, a5, #2 +xori s9, a5, #4 +xori s9, a5, #8 +xori s9, a5, #0x10 +xori s9, a5, #0x20 +xori s9, a5, #0x40 +xori s9, a5, #0x80 +xori s9, a5, #0x100 +xori s9, a5, #0x200 +xori s9, a5, #0x400 +xori s9, a5, #0x7ff +xori s9, s4, #0xfffff801 +xori s9, s4, #0xfffffc00 +xori s9, s4, #0xfffffe00 +xori s9, s4, #0xffffff00 +xori s9, s4, #0xffffff80 +xori s9, s4, #0xffffffc0 +xori s9, s4, #0xffffffe0 +xori s9, s4, #0xfffffff0 +xori s9, s4, #0xfffffff8 +xori s9, s4, #0xfffffffc +xori s9, s4, #0xfffffffe +xori s9, s4, #0xffffffff +xori s9, s4, #0 +xori s9, s4, #1 +xori s9, s4, #2 +xori s9, s4, #4 +xori s9, s4, #8 +xori s9, s4, #0x10 +xori s9, s4, #0x20 +xori s9, s4, #0x40 +xori s9, s4, #0x80 +xori s9, s4, #0x100 +xori s9, s4, #0x200 +xori s9, s4, #0x400 +xori s9, s4, #0x7ff +xori s9, s9, #0xfffff801 +xori s9, s9, #0xfffffc00 +xori s9, s9, #0xfffffe00 +xori s9, s9, #0xffffff00 +xori s9, s9, #0xffffff80 +xori s9, s9, #0xffffffc0 +xori s9, s9, #0xffffffe0 +xori s9, s9, #0xfffffff0 +xori s9, s9, #0xfffffff8 +xori s9, s9, #0xfffffffc +xori s9, s9, #0xfffffffe +xori s9, s9, #0xffffffff +xori s9, s9, #0 +xori s9, s9, #1 +xori s9, s9, #2 +xori s9, s9, #4 +xori s9, s9, #8 +xori s9, s9, #0x10 +xori s9, s9, #0x20 +xori s9, s9, #0x40 +xori s9, s9, #0x80 +xori s9, s9, #0x100 +xori s9, s9, #0x200 +xori s9, s9, #0x400 +xori s9, s9, #0x7ff +xori s9, t6, #0xfffff801 +xori s9, t6, #0xfffffc00 +xori s9, t6, #0xfffffe00 +xori s9, t6, #0xffffff00 +xori s9, t6, #0xffffff80 +xori s9, t6, #0xffffffc0 +xori s9, t6, #0xffffffe0 +xori s9, t6, #0xfffffff0 +xori s9, t6, #0xfffffff8 +xori s9, t6, #0xfffffffc +xori s9, t6, #0xfffffffe +xori s9, t6, #0xffffffff +xori s9, t6, #0 +xori s9, t6, #1 +xori s9, t6, #2 +xori s9, t6, #4 +xori s9, t6, #8 +xori s9, t6, #0x10 +xori s9, t6, #0x20 +xori s9, t6, #0x40 +xori s9, t6, #0x80 +xori s9, t6, #0x100 +xori s9, t6, #0x200 +xori s9, t6, #0x400 +xori s9, t6, #0x7ff +xori t6, zero, #0xfffff801 +xori t6, zero, #0xfffffc00 +xori t6, zero, #0xfffffe00 +xori t6, zero, #0xffffff00 +xori t6, zero, #0xffffff80 +xori t6, zero, #0xffffffc0 +xori t6, zero, #0xffffffe0 +xori t6, zero, #0xfffffff0 +xori t6, zero, #0xfffffff8 +xori t6, zero, #0xfffffffc +xori t6, zero, #0xfffffffe +xori t6, zero, #0xffffffff +xori t6, zero, #0 +xori t6, zero, #1 +xori t6, zero, #2 +xori t6, zero, #4 +xori t6, zero, #8 +xori t6, zero, #0x10 +xori t6, zero, #0x20 +xori t6, zero, #0x40 +xori t6, zero, #0x80 +xori t6, zero, #0x100 +xori t6, zero, #0x200 +xori t6, zero, #0x400 +xori t6, zero, #0x7ff +xori t6, ra, #0xfffff801 +xori t6, ra, #0xfffffc00 +xori t6, ra, #0xfffffe00 +xori t6, ra, #0xffffff00 +xori t6, ra, #0xffffff80 +xori t6, ra, #0xffffffc0 +xori t6, ra, #0xffffffe0 +xori t6, ra, #0xfffffff0 +xori t6, ra, #0xfffffff8 +xori t6, ra, #0xfffffffc +xori t6, ra, #0xfffffffe +xori t6, ra, #0xffffffff +xori t6, ra, #0 +xori t6, ra, #1 +xori t6, ra, #2 +xori t6, ra, #4 +xori t6, ra, #8 +xori t6, ra, #0x10 +xori t6, ra, #0x20 +xori t6, ra, #0x40 +xori t6, ra, #0x80 +xori t6, ra, #0x100 +xori t6, ra, #0x200 +xori t6, ra, #0x400 +xori t6, ra, #0x7ff +xori t6, t0, #0xfffff801 +xori t6, t0, #0xfffffc00 +xori t6, t0, #0xfffffe00 +xori t6, t0, #0xffffff00 +xori t6, t0, #0xffffff80 +xori t6, t0, #0xffffffc0 +xori t6, t0, #0xffffffe0 +xori t6, t0, #0xfffffff0 +xori t6, t0, #0xfffffff8 +xori t6, t0, #0xfffffffc +xori t6, t0, #0xfffffffe +xori t6, t0, #0xffffffff +xori t6, t0, #0 +xori t6, t0, #1 +xori t6, t0, #2 +xori t6, t0, #4 +xori t6, t0, #8 +xori t6, t0, #0x10 +xori t6, t0, #0x20 +xori t6, t0, #0x40 +xori t6, t0, #0x80 +xori t6, t0, #0x100 +xori t6, t0, #0x200 +xori t6, t0, #0x400 +xori t6, t0, #0x7ff +xori t6, a0, #0xfffff801 +xori t6, a0, #0xfffffc00 +xori t6, a0, #0xfffffe00 +xori t6, a0, #0xffffff00 +xori t6, a0, #0xffffff80 +xori t6, a0, #0xffffffc0 +xori t6, a0, #0xffffffe0 +xori t6, a0, #0xfffffff0 +xori t6, a0, #0xfffffff8 +xori t6, a0, #0xfffffffc +xori t6, a0, #0xfffffffe +xori t6, a0, #0xffffffff +xori t6, a0, #0 +xori t6, a0, #1 +xori t6, a0, #2 +xori t6, a0, #4 +xori t6, a0, #8 +xori t6, a0, #0x10 +xori t6, a0, #0x20 +xori t6, a0, #0x40 +xori t6, a0, #0x80 +xori t6, a0, #0x100 +xori t6, a0, #0x200 +xori t6, a0, #0x400 +xori t6, a0, #0x7ff +xori t6, a5, #0xfffff801 +xori t6, a5, #0xfffffc00 +xori t6, a5, #0xfffffe00 +xori t6, a5, #0xffffff00 +xori t6, a5, #0xffffff80 +xori t6, a5, #0xffffffc0 +xori t6, a5, #0xffffffe0 +xori t6, a5, #0xfffffff0 +xori t6, a5, #0xfffffff8 +xori t6, a5, #0xfffffffc +xori t6, a5, #0xfffffffe +xori t6, a5, #0xffffffff +xori t6, a5, #0 +xori t6, a5, #1 +xori t6, a5, #2 +xori t6, a5, #4 +xori t6, a5, #8 +xori t6, a5, #0x10 +xori t6, a5, #0x20 +xori t6, a5, #0x40 +xori t6, a5, #0x80 +xori t6, a5, #0x100 +xori t6, a5, #0x200 +xori t6, a5, #0x400 +xori t6, a5, #0x7ff +xori t6, s4, #0xfffff801 +xori t6, s4, #0xfffffc00 +xori t6, s4, #0xfffffe00 +xori t6, s4, #0xffffff00 +xori t6, s4, #0xffffff80 +xori t6, s4, #0xffffffc0 +xori t6, s4, #0xffffffe0 +xori t6, s4, #0xfffffff0 +xori t6, s4, #0xfffffff8 +xori t6, s4, #0xfffffffc +xori t6, s4, #0xfffffffe +xori t6, s4, #0xffffffff +xori t6, s4, #0 +xori t6, s4, #1 +xori t6, s4, #2 +xori t6, s4, #4 +xori t6, s4, #8 +xori t6, s4, #0x10 +xori t6, s4, #0x20 +xori t6, s4, #0x40 +xori t6, s4, #0x80 +xori t6, s4, #0x100 +xori t6, s4, #0x200 +xori t6, s4, #0x400 +xori t6, s4, #0x7ff +xori t6, s9, #0xfffff801 +xori t6, s9, #0xfffffc00 +xori t6, s9, #0xfffffe00 +xori t6, s9, #0xffffff00 +xori t6, s9, #0xffffff80 +xori t6, s9, #0xffffffc0 +xori t6, s9, #0xffffffe0 +xori t6, s9, #0xfffffff0 +xori t6, s9, #0xfffffff8 +xori t6, s9, #0xfffffffc +xori t6, s9, #0xfffffffe +xori t6, s9, #0xffffffff +xori t6, s9, #0 +xori t6, s9, #1 +xori t6, s9, #2 +xori t6, s9, #4 +xori t6, s9, #8 +xori t6, s9, #0x10 +xori t6, s9, #0x20 +xori t6, s9, #0x40 +xori t6, s9, #0x80 +xori t6, s9, #0x100 +xori t6, s9, #0x200 +xori t6, s9, #0x400 +xori t6, s9, #0x7ff +xori t6, t6, #0xfffff801 +xori t6, t6, #0xfffffc00 +xori t6, t6, #0xfffffe00 +xori t6, t6, #0xffffff00 +xori t6, t6, #0xffffff80 +xori t6, t6, #0xffffffc0 +xori t6, t6, #0xffffffe0 +xori t6, t6, #0xfffffff0 +xori t6, t6, #0xfffffff8 +xori t6, t6, #0xfffffffc +xori t6, t6, #0xfffffffe +xori t6, t6, #0xffffffff +xori t6, t6, #0 +xori t6, t6, #1 +xori t6, t6, #2 +xori t6, t6, #4 +xori t6, t6, #8 +xori t6, t6, #0x10 +xori t6, t6, #0x20 +xori t6, t6, #0x40 +xori t6, t6, #0x80 +xori t6, t6, #0x100 +xori t6, t6, #0x200 +xori t6, t6, #0x400 +xori t6, t6, #0x7ff diff --git a/tests/riscv/rv32i/add.asm b/tests/riscv/rv32i/add.asm new file mode 100644 index 0000000..81271e6 --- /dev/null +++ b/tests/riscv/rv32i/add.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +add zero, zero, zero +add zero, zero, ra +add zero, zero, t0 +add zero, zero, a0 +add zero, zero, a5 +add zero, zero, s4 +add zero, zero, s9 +add zero, zero, t6 +add zero, ra, zero +add zero, ra, ra +add zero, ra, t0 +add zero, ra, a0 +add zero, ra, a5 +add zero, ra, s4 +add zero, ra, s9 +add zero, ra, t6 +add zero, t0, zero +add zero, t0, ra +add zero, t0, t0 +add zero, t0, a0 +add zero, t0, a5 +add zero, t0, s4 +add zero, t0, s9 +add zero, t0, t6 +add zero, a0, zero +add zero, a0, ra +add zero, a0, t0 +add zero, a0, a0 +add zero, a0, a5 +add zero, a0, s4 +add zero, a0, s9 +add zero, a0, t6 +add zero, a5, zero +add zero, a5, ra +add zero, a5, t0 +add zero, a5, a0 +add zero, a5, a5 +add zero, a5, s4 +add zero, a5, s9 +add zero, a5, t6 +add zero, s4, zero +add zero, s4, ra +add zero, s4, t0 +add zero, s4, a0 +add zero, s4, a5 +add zero, s4, s4 +add zero, s4, s9 +add zero, s4, t6 +add zero, s9, zero +add zero, s9, ra +add zero, s9, t0 +add zero, s9, a0 +add zero, s9, a5 +add zero, s9, s4 +add zero, s9, s9 +add zero, s9, t6 +add zero, t6, zero +add zero, t6, ra +add zero, t6, t0 +add zero, t6, a0 +add zero, t6, a5 +add zero, t6, s4 +add zero, t6, s9 +add zero, t6, t6 +add ra, zero, zero +add ra, zero, ra +add ra, zero, t0 +add ra, zero, a0 +add ra, zero, a5 +add ra, zero, s4 +add ra, zero, s9 +add ra, zero, t6 +add ra, ra, zero +add ra, ra, ra +add ra, ra, t0 +add ra, ra, a0 +add ra, ra, a5 +add ra, ra, s4 +add ra, ra, s9 +add ra, ra, t6 +add ra, t0, zero +add ra, t0, ra +add ra, t0, t0 +add ra, t0, a0 +add ra, t0, a5 +add ra, t0, s4 +add ra, t0, s9 +add ra, t0, t6 +add ra, a0, zero +add ra, a0, ra +add ra, a0, t0 +add ra, a0, a0 +add ra, a0, a5 +add ra, a0, s4 +add ra, a0, s9 +add ra, a0, t6 +add ra, a5, zero +add ra, a5, ra +add ra, a5, t0 +add ra, a5, a0 +add ra, a5, a5 +add ra, a5, s4 +add ra, a5, s9 +add ra, a5, t6 +add ra, s4, zero +add ra, s4, ra +add ra, s4, t0 +add ra, s4, a0 +add ra, s4, a5 +add ra, s4, s4 +add ra, s4, s9 +add ra, s4, t6 +add ra, s9, zero +add ra, s9, ra +add ra, s9, t0 +add ra, s9, a0 +add ra, s9, a5 +add ra, s9, s4 +add ra, s9, s9 +add ra, s9, t6 +add ra, t6, zero +add ra, t6, ra +add ra, t6, t0 +add ra, t6, a0 +add ra, t6, a5 +add ra, t6, s4 +add ra, t6, s9 +add ra, t6, t6 +add t0, zero, zero +add t0, zero, ra +add t0, zero, t0 +add t0, zero, a0 +add t0, zero, a5 +add t0, zero, s4 +add t0, zero, s9 +add t0, zero, t6 +add t0, ra, zero +add t0, ra, ra +add t0, ra, t0 +add t0, ra, a0 +add t0, ra, a5 +add t0, ra, s4 +add t0, ra, s9 +add t0, ra, t6 +add t0, t0, zero +add t0, t0, ra +add t0, t0, t0 +add t0, t0, a0 +add t0, t0, a5 +add t0, t0, s4 +add t0, t0, s9 +add t0, t0, t6 +add t0, a0, zero +add t0, a0, ra +add t0, a0, t0 +add t0, a0, a0 +add t0, a0, a5 +add t0, a0, s4 +add t0, a0, s9 +add t0, a0, t6 +add t0, a5, zero +add t0, a5, ra +add t0, a5, t0 +add t0, a5, a0 +add t0, a5, a5 +add t0, a5, s4 +add t0, a5, s9 +add t0, a5, t6 +add t0, s4, zero +add t0, s4, ra +add t0, s4, t0 +add t0, s4, a0 +add t0, s4, a5 +add t0, s4, s4 +add t0, s4, s9 +add t0, s4, t6 +add t0, s9, zero +add t0, s9, ra +add t0, s9, t0 +add t0, s9, a0 +add t0, s9, a5 +add t0, s9, s4 +add t0, s9, s9 +add t0, s9, t6 +add t0, t6, zero +add t0, t6, ra +add t0, t6, t0 +add t0, t6, a0 +add t0, t6, a5 +add t0, t6, s4 +add t0, t6, s9 +add t0, t6, t6 +add a0, zero, zero +add a0, zero, ra +add a0, zero, t0 +add a0, zero, a0 +add a0, zero, a5 +add a0, zero, s4 +add a0, zero, s9 +add a0, zero, t6 +add a0, ra, zero +add a0, ra, ra +add a0, ra, t0 +add a0, ra, a0 +add a0, ra, a5 +add a0, ra, s4 +add a0, ra, s9 +add a0, ra, t6 +add a0, t0, zero +add a0, t0, ra +add a0, t0, t0 +add a0, t0, a0 +add a0, t0, a5 +add a0, t0, s4 +add a0, t0, s9 +add a0, t0, t6 +add a0, a0, zero +add a0, a0, ra +add a0, a0, t0 +add a0, a0, a0 +add a0, a0, a5 +add a0, a0, s4 +add a0, a0, s9 +add a0, a0, t6 +add a0, a5, zero +add a0, a5, ra +add a0, a5, t0 +add a0, a5, a0 +add a0, a5, a5 +add a0, a5, s4 +add a0, a5, s9 +add a0, a5, t6 +add a0, s4, zero +add a0, s4, ra +add a0, s4, t0 +add a0, s4, a0 +add a0, s4, a5 +add a0, s4, s4 +add a0, s4, s9 +add a0, s4, t6 +add a0, s9, zero +add a0, s9, ra +add a0, s9, t0 +add a0, s9, a0 +add a0, s9, a5 +add a0, s9, s4 +add a0, s9, s9 +add a0, s9, t6 +add a0, t6, zero +add a0, t6, ra +add a0, t6, t0 +add a0, t6, a0 +add a0, t6, a5 +add a0, t6, s4 +add a0, t6, s9 +add a0, t6, t6 +add a5, zero, zero +add a5, zero, ra +add a5, zero, t0 +add a5, zero, a0 +add a5, zero, a5 +add a5, zero, s4 +add a5, zero, s9 +add a5, zero, t6 +add a5, ra, zero +add a5, ra, ra +add a5, ra, t0 +add a5, ra, a0 +add a5, ra, a5 +add a5, ra, s4 +add a5, ra, s9 +add a5, ra, t6 +add a5, t0, zero +add a5, t0, ra +add a5, t0, t0 +add a5, t0, a0 +add a5, t0, a5 +add a5, t0, s4 +add a5, t0, s9 +add a5, t0, t6 +add a5, a0, zero +add a5, a0, ra +add a5, a0, t0 +add a5, a0, a0 +add a5, a0, a5 +add a5, a0, s4 +add a5, a0, s9 +add a5, a0, t6 +add a5, a5, zero +add a5, a5, ra +add a5, a5, t0 +add a5, a5, a0 +add a5, a5, a5 +add a5, a5, s4 +add a5, a5, s9 +add a5, a5, t6 +add a5, s4, zero +add a5, s4, ra +add a5, s4, t0 +add a5, s4, a0 +add a5, s4, a5 +add a5, s4, s4 +add a5, s4, s9 +add a5, s4, t6 +add a5, s9, zero +add a5, s9, ra +add a5, s9, t0 +add a5, s9, a0 +add a5, s9, a5 +add a5, s9, s4 +add a5, s9, s9 +add a5, s9, t6 +add a5, t6, zero +add a5, t6, ra +add a5, t6, t0 +add a5, t6, a0 +add a5, t6, a5 +add a5, t6, s4 +add a5, t6, s9 +add a5, t6, t6 +add s4, zero, zero +add s4, zero, ra +add s4, zero, t0 +add s4, zero, a0 +add s4, zero, a5 +add s4, zero, s4 +add s4, zero, s9 +add s4, zero, t6 +add s4, ra, zero +add s4, ra, ra +add s4, ra, t0 +add s4, ra, a0 +add s4, ra, a5 +add s4, ra, s4 +add s4, ra, s9 +add s4, ra, t6 +add s4, t0, zero +add s4, t0, ra +add s4, t0, t0 +add s4, t0, a0 +add s4, t0, a5 +add s4, t0, s4 +add s4, t0, s9 +add s4, t0, t6 +add s4, a0, zero +add s4, a0, ra +add s4, a0, t0 +add s4, a0, a0 +add s4, a0, a5 +add s4, a0, s4 +add s4, a0, s9 +add s4, a0, t6 +add s4, a5, zero +add s4, a5, ra +add s4, a5, t0 +add s4, a5, a0 +add s4, a5, a5 +add s4, a5, s4 +add s4, a5, s9 +add s4, a5, t6 +add s4, s4, zero +add s4, s4, ra +add s4, s4, t0 +add s4, s4, a0 +add s4, s4, a5 +add s4, s4, s4 +add s4, s4, s9 +add s4, s4, t6 +add s4, s9, zero +add s4, s9, ra +add s4, s9, t0 +add s4, s9, a0 +add s4, s9, a5 +add s4, s9, s4 +add s4, s9, s9 +add s4, s9, t6 +add s4, t6, zero +add s4, t6, ra +add s4, t6, t0 +add s4, t6, a0 +add s4, t6, a5 +add s4, t6, s4 +add s4, t6, s9 +add s4, t6, t6 +add s9, zero, zero +add s9, zero, ra +add s9, zero, t0 +add s9, zero, a0 +add s9, zero, a5 +add s9, zero, s4 +add s9, zero, s9 +add s9, zero, t6 +add s9, ra, zero +add s9, ra, ra +add s9, ra, t0 +add s9, ra, a0 +add s9, ra, a5 +add s9, ra, s4 +add s9, ra, s9 +add s9, ra, t6 +add s9, t0, zero +add s9, t0, ra +add s9, t0, t0 +add s9, t0, a0 +add s9, t0, a5 +add s9, t0, s4 +add s9, t0, s9 +add s9, t0, t6 +add s9, a0, zero +add s9, a0, ra +add s9, a0, t0 +add s9, a0, a0 +add s9, a0, a5 +add s9, a0, s4 +add s9, a0, s9 +add s9, a0, t6 +add s9, a5, zero +add s9, a5, ra +add s9, a5, t0 +add s9, a5, a0 +add s9, a5, a5 +add s9, a5, s4 +add s9, a5, s9 +add s9, a5, t6 +add s9, s4, zero +add s9, s4, ra +add s9, s4, t0 +add s9, s4, a0 +add s9, s4, a5 +add s9, s4, s4 +add s9, s4, s9 +add s9, s4, t6 +add s9, s9, zero +add s9, s9, ra +add s9, s9, t0 +add s9, s9, a0 +add s9, s9, a5 +add s9, s9, s4 +add s9, s9, s9 +add s9, s9, t6 +add s9, t6, zero +add s9, t6, ra +add s9, t6, t0 +add s9, t6, a0 +add s9, t6, a5 +add s9, t6, s4 +add s9, t6, s9 +add s9, t6, t6 +add t6, zero, zero +add t6, zero, ra +add t6, zero, t0 +add t6, zero, a0 +add t6, zero, a5 +add t6, zero, s4 +add t6, zero, s9 +add t6, zero, t6 +add t6, ra, zero +add t6, ra, ra +add t6, ra, t0 +add t6, ra, a0 +add t6, ra, a5 +add t6, ra, s4 +add t6, ra, s9 +add t6, ra, t6 +add t6, t0, zero +add t6, t0, ra +add t6, t0, t0 +add t6, t0, a0 +add t6, t0, a5 +add t6, t0, s4 +add t6, t0, s9 +add t6, t0, t6 +add t6, a0, zero +add t6, a0, ra +add t6, a0, t0 +add t6, a0, a0 +add t6, a0, a5 +add t6, a0, s4 +add t6, a0, s9 +add t6, a0, t6 +add t6, a5, zero +add t6, a5, ra +add t6, a5, t0 +add t6, a5, a0 +add t6, a5, a5 +add t6, a5, s4 +add t6, a5, s9 +add t6, a5, t6 +add t6, s4, zero +add t6, s4, ra +add t6, s4, t0 +add t6, s4, a0 +add t6, s4, a5 +add t6, s4, s4 +add t6, s4, s9 +add t6, s4, t6 +add t6, s9, zero +add t6, s9, ra +add t6, s9, t0 +add t6, s9, a0 +add t6, s9, a5 +add t6, s9, s4 +add t6, s9, s9 +add t6, s9, t6 +add t6, t6, zero +add t6, t6, ra +add t6, t6, t0 +add t6, t6, a0 +add t6, t6, a5 +add t6, t6, s4 +add t6, t6, s9 +add t6, t6, t6 + diff --git a/tests/riscv/rv32i/add.bin b/tests/riscv/rv32i/add.bin new file mode 100644 index 0000000000000000000000000000000000000000..7ce9fb38125a7d9c9f4624d09cfd6511d6da4da2 GIT binary patch literal 2048 zcmWmCafj7Q9LMq9VGLuKD-www#6E#55{a%zBzh{xForSA6^TSwBoh5`o>-Q(tYz=( z{PE$O?`QmYdw(v@&dx5*{*r&>KlvknpI@B)D}T-}4*G-spg-sj`h)(UKb-pD|2=sn z-{exBxPOpK--y0uALYuMqy0zwkM-LncvKB<~Q@3`OW-helx#Q zKlM{T^;19fQ$J5V|C9g8|Kxx2Klz{hPyRFing7gx=0EeF`Oo}k{wM#F|H=R4fAT;1 zpZrh$Gyj?Y%zx%T^Pl<8{Ad0r|C9g8|Kxx2Klz{hPyQ$WlmE&86d<;dj1#xi~q&{;(zhK_+R`N{tN$w|H6Oazwlr9 zFZ?h57ypa@#sA`e@xS>$iTNdi)#z#=r4z{2TwqzwuZ6 z6@SHF@mKs6f5l(%Z~Pno#=r4z{2TwqzwuZ66@SHF@mKs6f5l(%Z~Pno#=r4z{2Twq WzwvMU8~?_?@o)Sa|Hi-X&i@D9=B!@; literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/add.disasm b/tests/riscv/rv32i/add.disasm new file mode 100644 index 0000000..2da826d --- /dev/null +++ b/tests/riscv/rv32i/add.disasm @@ -0,0 +1,512 @@ +add zero, zero, zero +add zero, zero, ra +add zero, zero, t0 +add zero, zero, a0 +add zero, zero, a5 +add zero, zero, s4 +add zero, zero, s9 +add zero, zero, t6 +add zero, ra, zero +add zero, ra, ra +add zero, ra, t0 +add zero, ra, a0 +add zero, ra, a5 +add zero, ra, s4 +add zero, ra, s9 +add zero, ra, t6 +add zero, t0, zero +add zero, t0, ra +add zero, t0, t0 +add zero, t0, a0 +add zero, t0, a5 +add zero, t0, s4 +add zero, t0, s9 +add zero, t0, t6 +add zero, a0, zero +add zero, a0, ra +add zero, a0, t0 +add zero, a0, a0 +add zero, a0, a5 +add zero, a0, s4 +add zero, a0, s9 +add zero, a0, t6 +add zero, a5, zero +add zero, a5, ra +add zero, a5, t0 +add zero, a5, a0 +add zero, a5, a5 +add zero, a5, s4 +add zero, a5, s9 +add zero, a5, t6 +add zero, s4, zero +add zero, s4, ra +add zero, s4, t0 +add zero, s4, a0 +add zero, s4, a5 +add zero, s4, s4 +add zero, s4, s9 +add zero, s4, t6 +add zero, s9, zero +add zero, s9, ra +add zero, s9, t0 +add zero, s9, a0 +add zero, s9, a5 +add zero, s9, s4 +add zero, s9, s9 +add zero, s9, t6 +add zero, t6, zero +add zero, t6, ra +add zero, t6, t0 +add zero, t6, a0 +add zero, t6, a5 +add zero, t6, s4 +add zero, t6, s9 +add zero, t6, t6 +add ra, zero, zero +add ra, zero, ra +add ra, zero, t0 +add ra, zero, a0 +add ra, zero, a5 +add ra, zero, s4 +add ra, zero, s9 +add ra, zero, t6 +add ra, ra, zero +add ra, ra, ra +add ra, ra, t0 +add ra, ra, a0 +add ra, ra, a5 +add ra, ra, s4 +add ra, ra, s9 +add ra, ra, t6 +add ra, t0, zero +add ra, t0, ra +add ra, t0, t0 +add ra, t0, a0 +add ra, t0, a5 +add ra, t0, s4 +add ra, t0, s9 +add ra, t0, t6 +add ra, a0, zero +add ra, a0, ra +add ra, a0, t0 +add ra, a0, a0 +add ra, a0, a5 +add ra, a0, s4 +add ra, a0, s9 +add ra, a0, t6 +add ra, a5, zero +add ra, a5, ra +add ra, a5, t0 +add ra, a5, a0 +add ra, a5, a5 +add ra, a5, s4 +add ra, a5, s9 +add ra, a5, t6 +add ra, s4, zero +add ra, s4, ra +add ra, s4, t0 +add ra, s4, a0 +add ra, s4, a5 +add ra, s4, s4 +add ra, s4, s9 +add ra, s4, t6 +add ra, s9, zero +add ra, s9, ra +add ra, s9, t0 +add ra, s9, a0 +add ra, s9, a5 +add ra, s9, s4 +add ra, s9, s9 +add ra, s9, t6 +add ra, t6, zero +add ra, t6, ra +add ra, t6, t0 +add ra, t6, a0 +add ra, t6, a5 +add ra, t6, s4 +add ra, t6, s9 +add ra, t6, t6 +add t0, zero, zero +add t0, zero, ra +add t0, zero, t0 +add t0, zero, a0 +add t0, zero, a5 +add t0, zero, s4 +add t0, zero, s9 +add t0, zero, t6 +add t0, ra, zero +add t0, ra, ra +add t0, ra, t0 +add t0, ra, a0 +add t0, ra, a5 +add t0, ra, s4 +add t0, ra, s9 +add t0, ra, t6 +add t0, t0, zero +add t0, t0, ra +add t0, t0, t0 +add t0, t0, a0 +add t0, t0, a5 +add t0, t0, s4 +add t0, t0, s9 +add t0, t0, t6 +add t0, a0, zero +add t0, a0, ra +add t0, a0, t0 +add t0, a0, a0 +add t0, a0, a5 +add t0, a0, s4 +add t0, a0, s9 +add t0, a0, t6 +add t0, a5, zero +add t0, a5, ra +add t0, a5, t0 +add t0, a5, a0 +add t0, a5, a5 +add t0, a5, s4 +add t0, a5, s9 +add t0, a5, t6 +add t0, s4, zero +add t0, s4, ra +add t0, s4, t0 +add t0, s4, a0 +add t0, s4, a5 +add t0, s4, s4 +add t0, s4, s9 +add t0, s4, t6 +add t0, s9, zero +add t0, s9, ra +add t0, s9, t0 +add t0, s9, a0 +add t0, s9, a5 +add t0, s9, s4 +add t0, s9, s9 +add t0, s9, t6 +add t0, t6, zero +add t0, t6, ra +add t0, t6, t0 +add t0, t6, a0 +add t0, t6, a5 +add t0, t6, s4 +add t0, t6, s9 +add t0, t6, t6 +add a0, zero, zero +add a0, zero, ra +add a0, zero, t0 +add a0, zero, a0 +add a0, zero, a5 +add a0, zero, s4 +add a0, zero, s9 +add a0, zero, t6 +add a0, ra, zero +add a0, ra, ra +add a0, ra, t0 +add a0, ra, a0 +add a0, ra, a5 +add a0, ra, s4 +add a0, ra, s9 +add a0, ra, t6 +add a0, t0, zero +add a0, t0, ra +add a0, t0, t0 +add a0, t0, a0 +add a0, t0, a5 +add a0, t0, s4 +add a0, t0, s9 +add a0, t0, t6 +add a0, a0, zero +add a0, a0, ra +add a0, a0, t0 +add a0, a0, a0 +add a0, a0, a5 +add a0, a0, s4 +add a0, a0, s9 +add a0, a0, t6 +add a0, a5, zero +add a0, a5, ra +add a0, a5, t0 +add a0, a5, a0 +add a0, a5, a5 +add a0, a5, s4 +add a0, a5, s9 +add a0, a5, t6 +add a0, s4, zero +add a0, s4, ra +add a0, s4, t0 +add a0, s4, a0 +add a0, s4, a5 +add a0, s4, s4 +add a0, s4, s9 +add a0, s4, t6 +add a0, s9, zero +add a0, s9, ra +add a0, s9, t0 +add a0, s9, a0 +add a0, s9, a5 +add a0, s9, s4 +add a0, s9, s9 +add a0, s9, t6 +add a0, t6, zero +add a0, t6, ra +add a0, t6, t0 +add a0, t6, a0 +add a0, t6, a5 +add a0, t6, s4 +add a0, t6, s9 +add a0, t6, t6 +add a5, zero, zero +add a5, zero, ra +add a5, zero, t0 +add a5, zero, a0 +add a5, zero, a5 +add a5, zero, s4 +add a5, zero, s9 +add a5, zero, t6 +add a5, ra, zero +add a5, ra, ra +add a5, ra, t0 +add a5, ra, a0 +add a5, ra, a5 +add a5, ra, s4 +add a5, ra, s9 +add a5, ra, t6 +add a5, t0, zero +add a5, t0, ra +add a5, t0, t0 +add a5, t0, a0 +add a5, t0, a5 +add a5, t0, s4 +add a5, t0, s9 +add a5, t0, t6 +add a5, a0, zero +add a5, a0, ra +add a5, a0, t0 +add a5, a0, a0 +add a5, a0, a5 +add a5, a0, s4 +add a5, a0, s9 +add a5, a0, t6 +add a5, a5, zero +add a5, a5, ra +add a5, a5, t0 +add a5, a5, a0 +add a5, a5, a5 +add a5, a5, s4 +add a5, a5, s9 +add a5, a5, t6 +add a5, s4, zero +add a5, s4, ra +add a5, s4, t0 +add a5, s4, a0 +add a5, s4, a5 +add a5, s4, s4 +add a5, s4, s9 +add a5, s4, t6 +add a5, s9, zero +add a5, s9, ra +add a5, s9, t0 +add a5, s9, a0 +add a5, s9, a5 +add a5, s9, s4 +add a5, s9, s9 +add a5, s9, t6 +add a5, t6, zero +add a5, t6, ra +add a5, t6, t0 +add a5, t6, a0 +add a5, t6, a5 +add a5, t6, s4 +add a5, t6, s9 +add a5, t6, t6 +add s4, zero, zero +add s4, zero, ra +add s4, zero, t0 +add s4, zero, a0 +add s4, zero, a5 +add s4, zero, s4 +add s4, zero, s9 +add s4, zero, t6 +add s4, ra, zero +add s4, ra, ra +add s4, ra, t0 +add s4, ra, a0 +add s4, ra, a5 +add s4, ra, s4 +add s4, ra, s9 +add s4, ra, t6 +add s4, t0, zero +add s4, t0, ra +add s4, t0, t0 +add s4, t0, a0 +add s4, t0, a5 +add s4, t0, s4 +add s4, t0, s9 +add s4, t0, t6 +add s4, a0, zero +add s4, a0, ra +add s4, a0, t0 +add s4, a0, a0 +add s4, a0, a5 +add s4, a0, s4 +add s4, a0, s9 +add s4, a0, t6 +add s4, a5, zero +add s4, a5, ra +add s4, a5, t0 +add s4, a5, a0 +add s4, a5, a5 +add s4, a5, s4 +add s4, a5, s9 +add s4, a5, t6 +add s4, s4, zero +add s4, s4, ra +add s4, s4, t0 +add s4, s4, a0 +add s4, s4, a5 +add s4, s4, s4 +add s4, s4, s9 +add s4, s4, t6 +add s4, s9, zero +add s4, s9, ra +add s4, s9, t0 +add s4, s9, a0 +add s4, s9, a5 +add s4, s9, s4 +add s4, s9, s9 +add s4, s9, t6 +add s4, t6, zero +add s4, t6, ra +add s4, t6, t0 +add s4, t6, a0 +add s4, t6, a5 +add s4, t6, s4 +add s4, t6, s9 +add s4, t6, t6 +add s9, zero, zero +add s9, zero, ra +add s9, zero, t0 +add s9, zero, a0 +add s9, zero, a5 +add s9, zero, s4 +add s9, zero, s9 +add s9, zero, t6 +add s9, ra, zero +add s9, ra, ra +add s9, ra, t0 +add s9, ra, a0 +add s9, ra, a5 +add s9, ra, s4 +add s9, ra, s9 +add s9, ra, t6 +add s9, t0, zero +add s9, t0, ra +add s9, t0, t0 +add s9, t0, a0 +add s9, t0, a5 +add s9, t0, s4 +add s9, t0, s9 +add s9, t0, t6 +add s9, a0, zero +add s9, a0, ra +add s9, a0, t0 +add s9, a0, a0 +add s9, a0, a5 +add s9, a0, s4 +add s9, a0, s9 +add s9, a0, t6 +add s9, a5, zero +add s9, a5, ra +add s9, a5, t0 +add s9, a5, a0 +add s9, a5, a5 +add s9, a5, s4 +add s9, a5, s9 +add s9, a5, t6 +add s9, s4, zero +add s9, s4, ra +add s9, s4, t0 +add s9, s4, a0 +add s9, s4, a5 +add s9, s4, s4 +add s9, s4, s9 +add s9, s4, t6 +add s9, s9, zero +add s9, s9, ra +add s9, s9, t0 +add s9, s9, a0 +add s9, s9, a5 +add s9, s9, s4 +add s9, s9, s9 +add s9, s9, t6 +add s9, t6, zero +add s9, t6, ra +add s9, t6, t0 +add s9, t6, a0 +add s9, t6, a5 +add s9, t6, s4 +add s9, t6, s9 +add s9, t6, t6 +add t6, zero, zero +add t6, zero, ra +add t6, zero, t0 +add t6, zero, a0 +add t6, zero, a5 +add t6, zero, s4 +add t6, zero, s9 +add t6, zero, t6 +add t6, ra, zero +add t6, ra, ra +add t6, ra, t0 +add t6, ra, a0 +add t6, ra, a5 +add t6, ra, s4 +add t6, ra, s9 +add t6, ra, t6 +add t6, t0, zero +add t6, t0, ra +add t6, t0, t0 +add t6, t0, a0 +add t6, t0, a5 +add t6, t0, s4 +add t6, t0, s9 +add t6, t0, t6 +add t6, a0, zero +add t6, a0, ra +add t6, a0, t0 +add t6, a0, a0 +add t6, a0, a5 +add t6, a0, s4 +add t6, a0, s9 +add t6, a0, t6 +add t6, a5, zero +add t6, a5, ra +add t6, a5, t0 +add t6, a5, a0 +add t6, a5, a5 +add t6, a5, s4 +add t6, a5, s9 +add t6, a5, t6 +add t6, s4, zero +add t6, s4, ra +add t6, s4, t0 +add t6, s4, a0 +add t6, s4, a5 +add t6, s4, s4 +add t6, s4, s9 +add t6, s4, t6 +add t6, s9, zero +add t6, s9, ra +add t6, s9, t0 +add t6, s9, a0 +add t6, s9, a5 +add t6, s9, s4 +add t6, s9, s9 +add t6, s9, t6 +add t6, t6, zero +add t6, t6, ra +add t6, t6, t0 +add t6, t6, a0 +add t6, t6, a5 +add t6, t6, s4 +add t6, t6, s9 +add t6, t6, t6 diff --git a/tests/riscv/rv32i/addi.asm b/tests/riscv/rv32i/addi.asm new file mode 100644 index 0000000..039c7d4 --- /dev/null +++ b/tests/riscv/rv32i/addi.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +addi zero, zero, #-2047 +addi zero, zero, #-1024 +addi zero, zero, #-512 +addi zero, zero, #-256 +addi zero, zero, #-128 +addi zero, zero, #-64 +addi zero, zero, #-32 +addi zero, zero, #-16 +addi zero, zero, #-8 +addi zero, zero, #-4 +addi zero, zero, #-2 +addi zero, zero, #-1 +addi zero, zero, #0 +addi zero, zero, #1 +addi zero, zero, #2 +addi zero, zero, #4 +addi zero, zero, #8 +addi zero, zero, #16 +addi zero, zero, #32 +addi zero, zero, #64 +addi zero, zero, #128 +addi zero, zero, #256 +addi zero, zero, #512 +addi zero, zero, #1024 +addi zero, zero, #2047 +addi zero, ra, #-2047 +addi zero, ra, #-1024 +addi zero, ra, #-512 +addi zero, ra, #-256 +addi zero, ra, #-128 +addi zero, ra, #-64 +addi zero, ra, #-32 +addi zero, ra, #-16 +addi zero, ra, #-8 +addi zero, ra, #-4 +addi zero, ra, #-2 +addi zero, ra, #-1 +addi zero, ra, #0 +addi zero, ra, #1 +addi zero, ra, #2 +addi zero, ra, #4 +addi zero, ra, #8 +addi zero, ra, #16 +addi zero, ra, #32 +addi zero, ra, #64 +addi zero, ra, #128 +addi zero, ra, #256 +addi zero, ra, #512 +addi zero, ra, #1024 +addi zero, ra, #2047 +addi zero, t0, #-2047 +addi zero, t0, #-1024 +addi zero, t0, #-512 +addi zero, t0, #-256 +addi zero, t0, #-128 +addi zero, t0, #-64 +addi zero, t0, #-32 +addi zero, t0, #-16 +addi zero, t0, #-8 +addi zero, t0, #-4 +addi zero, t0, #-2 +addi zero, t0, #-1 +addi zero, t0, #0 +addi zero, t0, #1 +addi zero, t0, #2 +addi zero, t0, #4 +addi zero, t0, #8 +addi zero, t0, #16 +addi zero, t0, #32 +addi zero, t0, #64 +addi zero, t0, #128 +addi zero, t0, #256 +addi zero, t0, #512 +addi zero, t0, #1024 +addi zero, t0, #2047 +addi zero, a0, #-2047 +addi zero, a0, #-1024 +addi zero, a0, #-512 +addi zero, a0, #-256 +addi zero, a0, #-128 +addi zero, a0, #-64 +addi zero, a0, #-32 +addi zero, a0, #-16 +addi zero, a0, #-8 +addi zero, a0, #-4 +addi zero, a0, #-2 +addi zero, a0, #-1 +addi zero, a0, #0 +addi zero, a0, #1 +addi zero, a0, #2 +addi zero, a0, #4 +addi zero, a0, #8 +addi zero, a0, #16 +addi zero, a0, #32 +addi zero, a0, #64 +addi zero, a0, #128 +addi zero, a0, #256 +addi zero, a0, #512 +addi zero, a0, #1024 +addi zero, a0, #2047 +addi zero, a5, #-2047 +addi zero, a5, #-1024 +addi zero, a5, #-512 +addi zero, a5, #-256 +addi zero, a5, #-128 +addi zero, a5, #-64 +addi zero, a5, #-32 +addi zero, a5, #-16 +addi zero, a5, #-8 +addi zero, a5, #-4 +addi zero, a5, #-2 +addi zero, a5, #-1 +addi zero, a5, #0 +addi zero, a5, #1 +addi zero, a5, #2 +addi zero, a5, #4 +addi zero, a5, #8 +addi zero, a5, #16 +addi zero, a5, #32 +addi zero, a5, #64 +addi zero, a5, #128 +addi zero, a5, #256 +addi zero, a5, #512 +addi zero, a5, #1024 +addi zero, a5, #2047 +addi zero, s4, #-2047 +addi zero, s4, #-1024 +addi zero, s4, #-512 +addi zero, s4, #-256 +addi zero, s4, #-128 +addi zero, s4, #-64 +addi zero, s4, #-32 +addi zero, s4, #-16 +addi zero, s4, #-8 +addi zero, s4, #-4 +addi zero, s4, #-2 +addi zero, s4, #-1 +addi zero, s4, #0 +addi zero, s4, #1 +addi zero, s4, #2 +addi zero, s4, #4 +addi zero, s4, #8 +addi zero, s4, #16 +addi zero, s4, #32 +addi zero, s4, #64 +addi zero, s4, #128 +addi zero, s4, #256 +addi zero, s4, #512 +addi zero, s4, #1024 +addi zero, s4, #2047 +addi zero, s9, #-2047 +addi zero, s9, #-1024 +addi zero, s9, #-512 +addi zero, s9, #-256 +addi zero, s9, #-128 +addi zero, s9, #-64 +addi zero, s9, #-32 +addi zero, s9, #-16 +addi zero, s9, #-8 +addi zero, s9, #-4 +addi zero, s9, #-2 +addi zero, s9, #-1 +addi zero, s9, #0 +addi zero, s9, #1 +addi zero, s9, #2 +addi zero, s9, #4 +addi zero, s9, #8 +addi zero, s9, #16 +addi zero, s9, #32 +addi zero, s9, #64 +addi zero, s9, #128 +addi zero, s9, #256 +addi zero, s9, #512 +addi zero, s9, #1024 +addi zero, s9, #2047 +addi zero, t6, #-2047 +addi zero, t6, #-1024 +addi zero, t6, #-512 +addi zero, t6, #-256 +addi zero, t6, #-128 +addi zero, t6, #-64 +addi zero, t6, #-32 +addi zero, t6, #-16 +addi zero, t6, #-8 +addi zero, t6, #-4 +addi zero, t6, #-2 +addi zero, t6, #-1 +addi zero, t6, #0 +addi zero, t6, #1 +addi zero, t6, #2 +addi zero, t6, #4 +addi zero, t6, #8 +addi zero, t6, #16 +addi zero, t6, #32 +addi zero, t6, #64 +addi zero, t6, #128 +addi zero, t6, #256 +addi zero, t6, #512 +addi zero, t6, #1024 +addi zero, t6, #2047 +addi ra, zero, #-2047 +addi ra, zero, #-1024 +addi ra, zero, #-512 +addi ra, zero, #-256 +addi ra, zero, #-128 +addi ra, zero, #-64 +addi ra, zero, #-32 +addi ra, zero, #-16 +addi ra, zero, #-8 +addi ra, zero, #-4 +addi ra, zero, #-2 +addi ra, zero, #-1 +addi ra, zero, #0 +addi ra, zero, #1 +addi ra, zero, #2 +addi ra, zero, #4 +addi ra, zero, #8 +addi ra, zero, #16 +addi ra, zero, #32 +addi ra, zero, #64 +addi ra, zero, #128 +addi ra, zero, #256 +addi ra, zero, #512 +addi ra, zero, #1024 +addi ra, zero, #2047 +addi ra, ra, #-2047 +addi ra, ra, #-1024 +addi ra, ra, #-512 +addi ra, ra, #-256 +addi ra, ra, #-128 +addi ra, ra, #-64 +addi ra, ra, #-32 +addi ra, ra, #-16 +addi ra, ra, #-8 +addi ra, ra, #-4 +addi ra, ra, #-2 +addi ra, ra, #-1 +addi ra, ra, #0 +addi ra, ra, #1 +addi ra, ra, #2 +addi ra, ra, #4 +addi ra, ra, #8 +addi ra, ra, #16 +addi ra, ra, #32 +addi ra, ra, #64 +addi ra, ra, #128 +addi ra, ra, #256 +addi ra, ra, #512 +addi ra, ra, #1024 +addi ra, ra, #2047 +addi ra, t0, #-2047 +addi ra, t0, #-1024 +addi ra, t0, #-512 +addi ra, t0, #-256 +addi ra, t0, #-128 +addi ra, t0, #-64 +addi ra, t0, #-32 +addi ra, t0, #-16 +addi ra, t0, #-8 +addi ra, t0, #-4 +addi ra, t0, #-2 +addi ra, t0, #-1 +addi ra, t0, #0 +addi ra, t0, #1 +addi ra, t0, #2 +addi ra, t0, #4 +addi ra, t0, #8 +addi ra, t0, #16 +addi ra, t0, #32 +addi ra, t0, #64 +addi ra, t0, #128 +addi ra, t0, #256 +addi ra, t0, #512 +addi ra, t0, #1024 +addi ra, t0, #2047 +addi ra, a0, #-2047 +addi ra, a0, #-1024 +addi ra, a0, #-512 +addi ra, a0, #-256 +addi ra, a0, #-128 +addi ra, a0, #-64 +addi ra, a0, #-32 +addi ra, a0, #-16 +addi ra, a0, #-8 +addi ra, a0, #-4 +addi ra, a0, #-2 +addi ra, a0, #-1 +addi ra, a0, #0 +addi ra, a0, #1 +addi ra, a0, #2 +addi ra, a0, #4 +addi ra, a0, #8 +addi ra, a0, #16 +addi ra, a0, #32 +addi ra, a0, #64 +addi ra, a0, #128 +addi ra, a0, #256 +addi ra, a0, #512 +addi ra, a0, #1024 +addi ra, a0, #2047 +addi ra, a5, #-2047 +addi ra, a5, #-1024 +addi ra, a5, #-512 +addi ra, a5, #-256 +addi ra, a5, #-128 +addi ra, a5, #-64 +addi ra, a5, #-32 +addi ra, a5, #-16 +addi ra, a5, #-8 +addi ra, a5, #-4 +addi ra, a5, #-2 +addi ra, a5, #-1 +addi ra, a5, #0 +addi ra, a5, #1 +addi ra, a5, #2 +addi ra, a5, #4 +addi ra, a5, #8 +addi ra, a5, #16 +addi ra, a5, #32 +addi ra, a5, #64 +addi ra, a5, #128 +addi ra, a5, #256 +addi ra, a5, #512 +addi ra, a5, #1024 +addi ra, a5, #2047 +addi ra, s4, #-2047 +addi ra, s4, #-1024 +addi ra, s4, #-512 +addi ra, s4, #-256 +addi ra, s4, #-128 +addi ra, s4, #-64 +addi ra, s4, #-32 +addi ra, s4, #-16 +addi ra, s4, #-8 +addi ra, s4, #-4 +addi ra, s4, #-2 +addi ra, s4, #-1 +addi ra, s4, #0 +addi ra, s4, #1 +addi ra, s4, #2 +addi ra, s4, #4 +addi ra, s4, #8 +addi ra, s4, #16 +addi ra, s4, #32 +addi ra, s4, #64 +addi ra, s4, #128 +addi ra, s4, #256 +addi ra, s4, #512 +addi ra, s4, #1024 +addi ra, s4, #2047 +addi ra, s9, #-2047 +addi ra, s9, #-1024 +addi ra, s9, #-512 +addi ra, s9, #-256 +addi ra, s9, #-128 +addi ra, s9, #-64 +addi ra, s9, #-32 +addi ra, s9, #-16 +addi ra, s9, #-8 +addi ra, s9, #-4 +addi ra, s9, #-2 +addi ra, s9, #-1 +addi ra, s9, #0 +addi ra, s9, #1 +addi ra, s9, #2 +addi ra, s9, #4 +addi ra, s9, #8 +addi ra, s9, #16 +addi ra, s9, #32 +addi ra, s9, #64 +addi ra, s9, #128 +addi ra, s9, #256 +addi ra, s9, #512 +addi ra, s9, #1024 +addi ra, s9, #2047 +addi ra, t6, #-2047 +addi ra, t6, #-1024 +addi ra, t6, #-512 +addi ra, t6, #-256 +addi ra, t6, #-128 +addi ra, t6, #-64 +addi ra, t6, #-32 +addi ra, t6, #-16 +addi ra, t6, #-8 +addi ra, t6, #-4 +addi ra, t6, #-2 +addi ra, t6, #-1 +addi ra, t6, #0 +addi ra, t6, #1 +addi ra, t6, #2 +addi ra, t6, #4 +addi ra, t6, #8 +addi ra, t6, #16 +addi ra, t6, #32 +addi ra, t6, #64 +addi ra, t6, #128 +addi ra, t6, #256 +addi ra, t6, #512 +addi ra, t6, #1024 +addi ra, t6, #2047 +addi t0, zero, #-2047 +addi t0, zero, #-1024 +addi t0, zero, #-512 +addi t0, zero, #-256 +addi t0, zero, #-128 +addi t0, zero, #-64 +addi t0, zero, #-32 +addi t0, zero, #-16 +addi t0, zero, #-8 +addi t0, zero, #-4 +addi t0, zero, #-2 +addi t0, zero, #-1 +addi t0, zero, #0 +addi t0, zero, #1 +addi t0, zero, #2 +addi t0, zero, #4 +addi t0, zero, #8 +addi t0, zero, #16 +addi t0, zero, #32 +addi t0, zero, #64 +addi t0, zero, #128 +addi t0, zero, #256 +addi t0, zero, #512 +addi t0, zero, #1024 +addi t0, zero, #2047 +addi t0, ra, #-2047 +addi t0, ra, #-1024 +addi t0, ra, #-512 +addi t0, ra, #-256 +addi t0, ra, #-128 +addi t0, ra, #-64 +addi t0, ra, #-32 +addi t0, ra, #-16 +addi t0, ra, #-8 +addi t0, ra, #-4 +addi t0, ra, #-2 +addi t0, ra, #-1 +addi t0, ra, #0 +addi t0, ra, #1 +addi t0, ra, #2 +addi t0, ra, #4 +addi t0, ra, #8 +addi t0, ra, #16 +addi t0, ra, #32 +addi t0, ra, #64 +addi t0, ra, #128 +addi t0, ra, #256 +addi t0, ra, #512 +addi t0, ra, #1024 +addi t0, ra, #2047 +addi t0, t0, #-2047 +addi t0, t0, #-1024 +addi t0, t0, #-512 +addi t0, t0, #-256 +addi t0, t0, #-128 +addi t0, t0, #-64 +addi t0, t0, #-32 +addi t0, t0, #-16 +addi t0, t0, #-8 +addi t0, t0, #-4 +addi t0, t0, #-2 +addi t0, t0, #-1 +addi t0, t0, #0 +addi t0, t0, #1 +addi t0, t0, #2 +addi t0, t0, #4 +addi t0, t0, #8 +addi t0, t0, #16 +addi t0, t0, #32 +addi t0, t0, #64 +addi t0, t0, #128 +addi t0, t0, #256 +addi t0, t0, #512 +addi t0, t0, #1024 +addi t0, t0, #2047 +addi t0, a0, #-2047 +addi t0, a0, #-1024 +addi t0, a0, #-512 +addi t0, a0, #-256 +addi t0, a0, #-128 +addi t0, a0, #-64 +addi t0, a0, #-32 +addi t0, a0, #-16 +addi t0, a0, #-8 +addi t0, a0, #-4 +addi t0, a0, #-2 +addi t0, a0, #-1 +addi t0, a0, #0 +addi t0, a0, #1 +addi t0, a0, #2 +addi t0, a0, #4 +addi t0, a0, #8 +addi t0, a0, #16 +addi t0, a0, #32 +addi t0, a0, #64 +addi t0, a0, #128 +addi t0, a0, #256 +addi t0, a0, #512 +addi t0, a0, #1024 +addi t0, a0, #2047 +addi t0, a5, #-2047 +addi t0, a5, #-1024 +addi t0, a5, #-512 +addi t0, a5, #-256 +addi t0, a5, #-128 +addi t0, a5, #-64 +addi t0, a5, #-32 +addi t0, a5, #-16 +addi t0, a5, #-8 +addi t0, a5, #-4 +addi t0, a5, #-2 +addi t0, a5, #-1 +addi t0, a5, #0 +addi t0, a5, #1 +addi t0, a5, #2 +addi t0, a5, #4 +addi t0, a5, #8 +addi t0, a5, #16 +addi t0, a5, #32 +addi t0, a5, #64 +addi t0, a5, #128 +addi t0, a5, #256 +addi t0, a5, #512 +addi t0, a5, #1024 +addi t0, a5, #2047 +addi t0, s4, #-2047 +addi t0, s4, #-1024 +addi t0, s4, #-512 +addi t0, s4, #-256 +addi t0, s4, #-128 +addi t0, s4, #-64 +addi t0, s4, #-32 +addi t0, s4, #-16 +addi t0, s4, #-8 +addi t0, s4, #-4 +addi t0, s4, #-2 +addi t0, s4, #-1 +addi t0, s4, #0 +addi t0, s4, #1 +addi t0, s4, #2 +addi t0, s4, #4 +addi t0, s4, #8 +addi t0, s4, #16 +addi t0, s4, #32 +addi t0, s4, #64 +addi t0, s4, #128 +addi t0, s4, #256 +addi t0, s4, #512 +addi t0, s4, #1024 +addi t0, s4, #2047 +addi t0, s9, #-2047 +addi t0, s9, #-1024 +addi t0, s9, #-512 +addi t0, s9, #-256 +addi t0, s9, #-128 +addi t0, s9, #-64 +addi t0, s9, #-32 +addi t0, s9, #-16 +addi t0, s9, #-8 +addi t0, s9, #-4 +addi t0, s9, #-2 +addi t0, s9, #-1 +addi t0, s9, #0 +addi t0, s9, #1 +addi t0, s9, #2 +addi t0, s9, #4 +addi t0, s9, #8 +addi t0, s9, #16 +addi t0, s9, #32 +addi t0, s9, #64 +addi t0, s9, #128 +addi t0, s9, #256 +addi t0, s9, #512 +addi t0, s9, #1024 +addi t0, s9, #2047 +addi t0, t6, #-2047 +addi t0, t6, #-1024 +addi t0, t6, #-512 +addi t0, t6, #-256 +addi t0, t6, #-128 +addi t0, t6, #-64 +addi t0, t6, #-32 +addi t0, t6, #-16 +addi t0, t6, #-8 +addi t0, t6, #-4 +addi t0, t6, #-2 +addi t0, t6, #-1 +addi t0, t6, #0 +addi t0, t6, #1 +addi t0, t6, #2 +addi t0, t6, #4 +addi t0, t6, #8 +addi t0, t6, #16 +addi t0, t6, #32 +addi t0, t6, #64 +addi t0, t6, #128 +addi t0, t6, #256 +addi t0, t6, #512 +addi t0, t6, #1024 +addi t0, t6, #2047 +addi a0, zero, #-2047 +addi a0, zero, #-1024 +addi a0, zero, #-512 +addi a0, zero, #-256 +addi a0, zero, #-128 +addi a0, zero, #-64 +addi a0, zero, #-32 +addi a0, zero, #-16 +addi a0, zero, #-8 +addi a0, zero, #-4 +addi a0, zero, #-2 +addi a0, zero, #-1 +addi a0, zero, #0 +addi a0, zero, #1 +addi a0, zero, #2 +addi a0, zero, #4 +addi a0, zero, #8 +addi a0, zero, #16 +addi a0, zero, #32 +addi a0, zero, #64 +addi a0, zero, #128 +addi a0, zero, #256 +addi a0, zero, #512 +addi a0, zero, #1024 +addi a0, zero, #2047 +addi a0, ra, #-2047 +addi a0, ra, #-1024 +addi a0, ra, #-512 +addi a0, ra, #-256 +addi a0, ra, #-128 +addi a0, ra, #-64 +addi a0, ra, #-32 +addi a0, ra, #-16 +addi a0, ra, #-8 +addi a0, ra, #-4 +addi a0, ra, #-2 +addi a0, ra, #-1 +addi a0, ra, #0 +addi a0, ra, #1 +addi a0, ra, #2 +addi a0, ra, #4 +addi a0, ra, #8 +addi a0, ra, #16 +addi a0, ra, #32 +addi a0, ra, #64 +addi a0, ra, #128 +addi a0, ra, #256 +addi a0, ra, #512 +addi a0, ra, #1024 +addi a0, ra, #2047 +addi a0, t0, #-2047 +addi a0, t0, #-1024 +addi a0, t0, #-512 +addi a0, t0, #-256 +addi a0, t0, #-128 +addi a0, t0, #-64 +addi a0, t0, #-32 +addi a0, t0, #-16 +addi a0, t0, #-8 +addi a0, t0, #-4 +addi a0, t0, #-2 +addi a0, t0, #-1 +addi a0, t0, #0 +addi a0, t0, #1 +addi a0, t0, #2 +addi a0, t0, #4 +addi a0, t0, #8 +addi a0, t0, #16 +addi a0, t0, #32 +addi a0, t0, #64 +addi a0, t0, #128 +addi a0, t0, #256 +addi a0, t0, #512 +addi a0, t0, #1024 +addi a0, t0, #2047 +addi a0, a0, #-2047 +addi a0, a0, #-1024 +addi a0, a0, #-512 +addi a0, a0, #-256 +addi a0, a0, #-128 +addi a0, a0, #-64 +addi a0, a0, #-32 +addi a0, a0, #-16 +addi a0, a0, #-8 +addi a0, a0, #-4 +addi a0, a0, #-2 +addi a0, a0, #-1 +addi a0, a0, #0 +addi a0, a0, #1 +addi a0, a0, #2 +addi a0, a0, #4 +addi a0, a0, #8 +addi a0, a0, #16 +addi a0, a0, #32 +addi a0, a0, #64 +addi a0, a0, #128 +addi a0, a0, #256 +addi a0, a0, #512 +addi a0, a0, #1024 +addi a0, a0, #2047 +addi a0, a5, #-2047 +addi a0, a5, #-1024 +addi a0, a5, #-512 +addi a0, a5, #-256 +addi a0, a5, #-128 +addi a0, a5, #-64 +addi a0, a5, #-32 +addi a0, a5, #-16 +addi a0, a5, #-8 +addi a0, a5, #-4 +addi a0, a5, #-2 +addi a0, a5, #-1 +addi a0, a5, #0 +addi a0, a5, #1 +addi a0, a5, #2 +addi a0, a5, #4 +addi a0, a5, #8 +addi a0, a5, #16 +addi a0, a5, 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+addi s9, a0, #2047 +addi s9, a5, #-2047 +addi s9, a5, #-1024 +addi s9, a5, #-512 +addi s9, a5, #-256 +addi s9, a5, #-128 +addi s9, a5, #-64 +addi s9, a5, #-32 +addi s9, a5, #-16 +addi s9, a5, #-8 +addi s9, a5, #-4 +addi s9, a5, #-2 +addi s9, a5, #-1 +addi s9, a5, #0 +addi s9, a5, #1 +addi s9, a5, #2 +addi s9, a5, #4 +addi s9, a5, #8 +addi s9, a5, #16 +addi s9, a5, #32 +addi s9, a5, #64 +addi s9, a5, #128 +addi s9, a5, #256 +addi s9, a5, #512 +addi s9, a5, #1024 +addi s9, a5, #2047 +addi s9, s4, #-2047 +addi s9, s4, #-1024 +addi s9, s4, #-512 +addi s9, s4, #-256 +addi s9, s4, #-128 +addi s9, s4, #-64 +addi s9, s4, #-32 +addi s9, s4, #-16 +addi s9, s4, #-8 +addi s9, s4, #-4 +addi s9, s4, #-2 +addi s9, s4, #-1 +addi s9, s4, #0 +addi s9, s4, #1 +addi s9, s4, #2 +addi s9, s4, #4 +addi s9, s4, #8 +addi s9, s4, #16 +addi s9, s4, #32 +addi s9, s4, #64 +addi s9, s4, #128 +addi s9, s4, #256 +addi s9, s4, #512 +addi s9, s4, #1024 +addi s9, s4, #2047 +addi s9, s9, #-2047 +addi s9, s9, #-1024 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#-128 +addi t6, zero, #-64 +addi t6, zero, #-32 +addi t6, zero, #-16 +addi t6, zero, #-8 +addi t6, zero, #-4 +addi t6, zero, #-2 +addi t6, zero, #-1 +addi t6, zero, #0 +addi t6, zero, #1 +addi t6, zero, #2 +addi t6, zero, #4 +addi t6, zero, #8 +addi t6, zero, #16 +addi t6, zero, #32 +addi t6, zero, #64 +addi t6, zero, #128 +addi t6, zero, #256 +addi t6, zero, #512 +addi t6, zero, #1024 +addi t6, zero, #2047 +addi t6, ra, #-2047 +addi t6, ra, #-1024 +addi t6, ra, #-512 +addi t6, ra, #-256 +addi t6, ra, #-128 +addi t6, ra, #-64 +addi t6, ra, #-32 +addi t6, ra, #-16 +addi t6, ra, #-8 +addi t6, ra, #-4 +addi t6, ra, #-2 +addi t6, ra, #-1 +addi t6, ra, #0 +addi t6, ra, #1 +addi t6, ra, #2 +addi t6, ra, #4 +addi t6, ra, #8 +addi t6, ra, #16 +addi t6, ra, #32 +addi t6, ra, #64 +addi t6, ra, #128 +addi t6, ra, #256 +addi t6, ra, #512 +addi t6, ra, #1024 +addi t6, ra, #2047 +addi t6, t0, #-2047 +addi t6, t0, #-1024 +addi t6, t0, #-512 +addi t6, t0, #-256 +addi t6, t0, #-128 +addi t6, t0, #-64 +addi t6, t0, #-32 +addi t6, t0, #-16 +addi t6, t0, #-8 +addi t6, t0, #-4 +addi t6, t0, #-2 +addi t6, t0, #-1 +addi t6, t0, #0 +addi t6, t0, #1 +addi t6, t0, #2 +addi t6, t0, #4 +addi t6, t0, #8 +addi t6, t0, #16 +addi t6, t0, #32 +addi t6, t0, #64 +addi t6, t0, #128 +addi t6, t0, #256 +addi t6, t0, #512 +addi t6, t0, #1024 +addi t6, t0, #2047 +addi t6, a0, #-2047 +addi t6, a0, #-1024 +addi t6, a0, #-512 +addi t6, a0, #-256 +addi t6, a0, #-128 +addi t6, a0, #-64 +addi t6, a0, #-32 +addi t6, a0, #-16 +addi t6, a0, #-8 +addi t6, a0, #-4 +addi t6, a0, #-2 +addi t6, a0, #-1 +addi t6, a0, #0 +addi t6, a0, #1 +addi t6, a0, #2 +addi t6, a0, #4 +addi t6, a0, #8 +addi t6, a0, #16 +addi t6, a0, #32 +addi t6, a0, #64 +addi t6, a0, #128 +addi t6, a0, #256 +addi t6, a0, #512 +addi t6, a0, #1024 +addi t6, a0, #2047 +addi t6, a5, #-2047 +addi t6, a5, #-1024 +addi t6, a5, #-512 +addi t6, a5, #-256 +addi t6, a5, #-128 +addi t6, a5, #-64 +addi t6, a5, #-32 +addi t6, a5, #-16 +addi t6, a5, #-8 +addi t6, a5, #-4 +addi t6, a5, #-2 +addi t6, a5, #-1 +addi t6, a5, #0 +addi t6, a5, #1 +addi t6, a5, #2 +addi t6, a5, #4 +addi t6, a5, #8 +addi t6, a5, #16 +addi t6, a5, #32 +addi t6, a5, #64 +addi t6, a5, #128 +addi t6, a5, #256 +addi t6, a5, #512 +addi t6, a5, #1024 +addi t6, a5, #2047 +addi t6, s4, #-2047 +addi t6, s4, #-1024 +addi t6, s4, #-512 +addi t6, s4, #-256 +addi t6, s4, #-128 +addi t6, s4, #-64 +addi t6, s4, #-32 +addi t6, s4, #-16 +addi t6, s4, #-8 +addi t6, s4, #-4 +addi t6, s4, #-2 +addi t6, s4, #-1 +addi t6, s4, #0 +addi t6, s4, #1 +addi t6, s4, #2 +addi t6, s4, #4 +addi t6, s4, #8 +addi t6, s4, #16 +addi t6, s4, #32 +addi t6, s4, #64 +addi t6, s4, #128 +addi t6, s4, #256 +addi t6, s4, #512 +addi t6, s4, #1024 +addi t6, s4, #2047 +addi t6, s9, #-2047 +addi t6, s9, #-1024 +addi t6, s9, #-512 +addi t6, s9, #-256 +addi t6, s9, #-128 +addi t6, s9, #-64 +addi t6, s9, #-32 +addi t6, s9, #-16 +addi t6, s9, #-8 +addi t6, s9, #-4 +addi t6, s9, #-2 +addi t6, s9, #-1 +addi t6, s9, #0 +addi t6, s9, #1 +addi t6, s9, #2 +addi t6, s9, #4 +addi t6, s9, #8 +addi t6, s9, #16 +addi t6, s9, #32 +addi t6, s9, #64 +addi t6, s9, #128 +addi t6, s9, #256 +addi t6, s9, #512 +addi t6, s9, #1024 +addi t6, s9, #2047 +addi t6, t6, #-2047 +addi t6, t6, #-1024 +addi t6, t6, #-512 +addi t6, t6, #-256 +addi t6, t6, #-128 +addi t6, t6, #-64 +addi t6, t6, #-32 +addi t6, t6, #-16 +addi t6, t6, #-8 +addi t6, t6, #-4 +addi t6, t6, #-2 +addi t6, t6, #-1 +addi t6, t6, #0 +addi t6, t6, #1 +addi t6, t6, #2 +addi t6, t6, #4 +addi t6, t6, #8 +addi t6, t6, #16 +addi t6, t6, #32 +addi t6, t6, #64 +addi t6, t6, #128 +addi t6, t6, #256 +addi t6, t6, #512 +addi t6, t6, #1024 +addi t6, t6, #2047 + diff --git a/tests/riscv/rv32i/addi.bin b/tests/riscv/rv32i/addi.bin new file mode 100644 index 0000000000000000000000000000000000000000..262aa2055974a1ab14f9ae7f565e01f54aba899e GIT binary patch literal 6400 zcmWmG;l>?Jy2kO^C8eS@9ede^ZL^mUA;NnKEkua$9@1(>DN0cv`h*^vF^pkOp$%gg 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zero, #0xffffffff +addi zero, zero, #0 +addi zero, zero, #1 +addi zero, zero, #2 +addi zero, zero, #4 +addi zero, zero, #8 +addi zero, zero, #0x10 +addi zero, zero, #0x20 +addi zero, zero, #0x40 +addi zero, zero, #0x80 +addi zero, zero, #0x100 +addi zero, zero, #0x200 +addi zero, zero, #0x400 +addi zero, zero, #0x7ff +addi zero, ra, #0xfffff801 +addi zero, ra, #0xfffffc00 +addi zero, ra, #0xfffffe00 +addi zero, ra, #0xffffff00 +addi zero, ra, #0xffffff80 +addi zero, ra, #0xffffffc0 +addi zero, ra, #0xffffffe0 +addi zero, ra, #0xfffffff0 +addi zero, ra, #0xfffffff8 +addi zero, ra, #0xfffffffc +addi zero, ra, #0xfffffffe +addi zero, ra, #0xffffffff +addi zero, ra, #0 +addi zero, ra, #1 +addi zero, ra, #2 +addi zero, ra, #4 +addi zero, ra, #8 +addi zero, ra, #0x10 +addi zero, ra, #0x20 +addi zero, ra, #0x40 +addi zero, ra, #0x80 +addi zero, ra, #0x100 +addi zero, ra, #0x200 +addi zero, ra, #0x400 +addi zero, ra, #0x7ff +addi zero, t0, #0xfffff801 +addi zero, t0, #0xfffffc00 +addi zero, t0, #0xfffffe00 +addi zero, t0, #0xffffff00 +addi zero, t0, #0xffffff80 +addi zero, t0, #0xffffffc0 +addi zero, t0, #0xffffffe0 +addi zero, t0, #0xfffffff0 +addi zero, t0, #0xfffffff8 +addi zero, t0, #0xfffffffc +addi zero, t0, #0xfffffffe +addi zero, t0, #0xffffffff +addi zero, t0, #0 +addi zero, t0, #1 +addi zero, t0, #2 +addi zero, t0, #4 +addi zero, t0, #8 +addi zero, t0, #0x10 +addi zero, t0, #0x20 +addi zero, t0, #0x40 +addi zero, t0, #0x80 +addi zero, t0, #0x100 +addi zero, t0, #0x200 +addi zero, t0, #0x400 +addi zero, t0, #0x7ff +addi zero, a0, #0xfffff801 +addi zero, a0, #0xfffffc00 +addi zero, a0, #0xfffffe00 +addi zero, a0, #0xffffff00 +addi zero, a0, #0xffffff80 +addi zero, a0, #0xffffffc0 +addi zero, a0, #0xffffffe0 +addi zero, a0, #0xfffffff0 +addi zero, a0, #0xfffffff8 +addi zero, a0, #0xfffffffc +addi zero, a0, #0xfffffffe +addi zero, a0, #0xffffffff +addi zero, a0, #0 +addi zero, a0, #1 +addi zero, a0, #2 +addi zero, a0, #4 +addi zero, a0, #8 +addi zero, a0, #0x10 +addi zero, a0, #0x20 +addi zero, a0, #0x40 +addi zero, a0, #0x80 +addi zero, a0, #0x100 +addi zero, a0, #0x200 +addi zero, a0, #0x400 +addi zero, a0, #0x7ff +addi zero, a5, #0xfffff801 +addi zero, a5, #0xfffffc00 +addi zero, a5, #0xfffffe00 +addi zero, a5, #0xffffff00 +addi zero, a5, #0xffffff80 +addi zero, a5, #0xffffffc0 +addi zero, a5, #0xffffffe0 +addi zero, a5, #0xfffffff0 +addi zero, a5, #0xfffffff8 +addi zero, a5, #0xfffffffc +addi zero, a5, #0xfffffffe +addi zero, a5, #0xffffffff +addi zero, a5, #0 +addi zero, a5, #1 +addi zero, a5, #2 +addi zero, a5, #4 +addi zero, a5, #8 +addi zero, a5, #0x10 +addi zero, a5, #0x20 +addi zero, a5, #0x40 +addi zero, a5, #0x80 +addi zero, a5, #0x100 +addi zero, a5, #0x200 +addi zero, a5, #0x400 +addi zero, a5, #0x7ff +addi zero, s4, #0xfffff801 +addi zero, s4, #0xfffffc00 +addi zero, s4, #0xfffffe00 +addi zero, s4, #0xffffff00 +addi zero, s4, #0xffffff80 +addi zero, s4, #0xffffffc0 +addi zero, s4, #0xffffffe0 +addi zero, s4, #0xfffffff0 +addi zero, s4, #0xfffffff8 +addi zero, s4, #0xfffffffc +addi zero, s4, #0xfffffffe +addi zero, s4, #0xffffffff +addi zero, s4, #0 +addi zero, s4, #1 +addi zero, s4, #2 +addi zero, s4, #4 +addi zero, s4, #8 +addi zero, s4, #0x10 +addi zero, s4, #0x20 +addi zero, s4, #0x40 +addi zero, s4, #0x80 +addi zero, s4, #0x100 +addi zero, s4, #0x200 +addi zero, s4, #0x400 +addi zero, s4, #0x7ff +addi zero, s9, #0xfffff801 +addi zero, s9, #0xfffffc00 +addi zero, s9, #0xfffffe00 +addi zero, s9, #0xffffff00 +addi zero, s9, #0xffffff80 +addi zero, s9, #0xffffffc0 +addi zero, s9, #0xffffffe0 +addi zero, s9, #0xfffffff0 +addi zero, s9, #0xfffffff8 +addi zero, s9, #0xfffffffc +addi zero, s9, #0xfffffffe +addi zero, s9, #0xffffffff +addi zero, s9, #0 +addi zero, s9, #1 +addi zero, s9, #2 +addi zero, s9, #4 +addi zero, s9, #8 +addi zero, s9, #0x10 +addi zero, s9, #0x20 +addi zero, s9, #0x40 +addi zero, s9, #0x80 +addi zero, s9, #0x100 +addi zero, s9, #0x200 +addi zero, s9, #0x400 +addi zero, s9, #0x7ff +addi zero, t6, #0xfffff801 +addi zero, t6, #0xfffffc00 +addi zero, t6, #0xfffffe00 +addi zero, t6, #0xffffff00 +addi zero, t6, #0xffffff80 +addi zero, t6, #0xffffffc0 +addi zero, t6, #0xffffffe0 +addi zero, t6, #0xfffffff0 +addi zero, t6, #0xfffffff8 +addi zero, t6, #0xfffffffc +addi zero, t6, #0xfffffffe +addi zero, t6, #0xffffffff +addi zero, t6, #0 +addi zero, t6, #1 +addi zero, t6, #2 +addi zero, t6, #4 +addi zero, t6, #8 +addi zero, t6, #0x10 +addi zero, t6, #0x20 +addi zero, t6, #0x40 +addi zero, t6, #0x80 +addi zero, t6, #0x100 +addi zero, t6, #0x200 +addi zero, t6, #0x400 +addi zero, t6, #0x7ff +addi ra, zero, #0xfffff801 +addi ra, zero, #0xfffffc00 +addi ra, zero, #0xfffffe00 +addi ra, zero, #0xffffff00 +addi ra, zero, #0xffffff80 +addi ra, zero, #0xffffffc0 +addi ra, zero, #0xffffffe0 +addi ra, zero, #0xfffffff0 +addi ra, zero, #0xfffffff8 +addi ra, zero, #0xfffffffc +addi ra, zero, #0xfffffffe +addi ra, zero, #0xffffffff +addi ra, zero, #0 +addi ra, zero, #1 +addi ra, zero, #2 +addi ra, zero, #4 +addi ra, zero, #8 +addi ra, zero, #0x10 +addi ra, zero, #0x20 +addi ra, zero, #0x40 +addi ra, zero, #0x80 +addi ra, zero, #0x100 +addi ra, zero, #0x200 +addi ra, zero, #0x400 +addi ra, zero, #0x7ff +addi ra, ra, #0xfffff801 +addi ra, ra, #0xfffffc00 +addi ra, ra, #0xfffffe00 +addi ra, ra, #0xffffff00 +addi ra, ra, #0xffffff80 +addi ra, ra, #0xffffffc0 +addi ra, ra, #0xffffffe0 +addi ra, ra, #0xfffffff0 +addi ra, ra, #0xfffffff8 +addi ra, ra, #0xfffffffc +addi ra, ra, #0xfffffffe +addi ra, ra, #0xffffffff +addi ra, ra, #0 +addi ra, ra, #1 +addi ra, ra, #2 +addi ra, ra, #4 +addi ra, ra, #8 +addi ra, ra, #0x10 +addi ra, ra, #0x20 +addi ra, ra, #0x40 +addi ra, ra, #0x80 +addi ra, ra, #0x100 +addi ra, ra, #0x200 +addi ra, ra, #0x400 +addi ra, ra, #0x7ff +addi ra, t0, #0xfffff801 +addi ra, t0, #0xfffffc00 +addi ra, t0, #0xfffffe00 +addi ra, t0, #0xffffff00 +addi ra, t0, #0xffffff80 +addi ra, t0, #0xffffffc0 +addi ra, t0, #0xffffffe0 +addi ra, t0, #0xfffffff0 +addi ra, t0, #0xfffffff8 +addi ra, t0, #0xfffffffc +addi ra, t0, #0xfffffffe +addi ra, t0, #0xffffffff +addi ra, t0, #0 +addi ra, t0, #1 +addi ra, t0, #2 +addi ra, t0, #4 +addi ra, t0, #8 +addi ra, t0, #0x10 +addi ra, t0, #0x20 +addi ra, t0, #0x40 +addi ra, t0, #0x80 +addi ra, t0, #0x100 +addi ra, t0, #0x200 +addi ra, t0, #0x400 +addi ra, t0, #0x7ff +addi ra, a0, #0xfffff801 +addi ra, a0, #0xfffffc00 +addi ra, a0, #0xfffffe00 +addi ra, a0, #0xffffff00 +addi ra, a0, #0xffffff80 +addi ra, a0, #0xffffffc0 +addi ra, a0, #0xffffffe0 +addi ra, a0, #0xfffffff0 +addi ra, a0, #0xfffffff8 +addi ra, a0, #0xfffffffc +addi ra, a0, #0xfffffffe +addi ra, a0, #0xffffffff +addi ra, a0, #0 +addi ra, a0, #1 +addi ra, a0, #2 +addi ra, a0, #4 +addi ra, a0, #8 +addi ra, a0, #0x10 +addi ra, a0, #0x20 +addi ra, a0, #0x40 +addi ra, a0, #0x80 +addi ra, a0, #0x100 +addi ra, a0, #0x200 +addi ra, a0, #0x400 +addi ra, a0, #0x7ff +addi ra, a5, #0xfffff801 +addi ra, a5, #0xfffffc00 +addi ra, a5, #0xfffffe00 +addi ra, a5, #0xffffff00 +addi ra, a5, #0xffffff80 +addi ra, a5, #0xffffffc0 +addi ra, a5, #0xffffffe0 +addi ra, a5, #0xfffffff0 +addi ra, a5, #0xfffffff8 +addi ra, a5, #0xfffffffc +addi ra, a5, #0xfffffffe +addi ra, a5, #0xffffffff +addi ra, a5, #0 +addi ra, a5, #1 +addi ra, a5, #2 +addi ra, a5, #4 +addi ra, a5, #8 +addi ra, a5, #0x10 +addi ra, a5, #0x20 +addi ra, a5, #0x40 +addi ra, a5, #0x80 +addi ra, a5, #0x100 +addi ra, a5, #0x200 +addi ra, a5, #0x400 +addi ra, a5, #0x7ff +addi ra, s4, #0xfffff801 +addi ra, s4, #0xfffffc00 +addi ra, s4, #0xfffffe00 +addi ra, s4, #0xffffff00 +addi ra, s4, #0xffffff80 +addi ra, s4, #0xffffffc0 +addi ra, s4, #0xffffffe0 +addi ra, s4, #0xfffffff0 +addi ra, s4, #0xfffffff8 +addi ra, s4, #0xfffffffc +addi ra, s4, #0xfffffffe +addi ra, s4, #0xffffffff +addi ra, s4, #0 +addi ra, s4, #1 +addi ra, s4, #2 +addi ra, s4, #4 +addi ra, s4, #8 +addi ra, s4, #0x10 +addi ra, s4, #0x20 +addi ra, s4, #0x40 +addi ra, s4, #0x80 +addi ra, s4, #0x100 +addi ra, s4, #0x200 +addi ra, s4, #0x400 +addi ra, s4, #0x7ff +addi ra, s9, #0xfffff801 +addi ra, s9, #0xfffffc00 +addi ra, s9, #0xfffffe00 +addi ra, s9, #0xffffff00 +addi ra, s9, #0xffffff80 +addi ra, s9, #0xffffffc0 +addi ra, s9, #0xffffffe0 +addi ra, s9, #0xfffffff0 +addi ra, s9, #0xfffffff8 +addi ra, s9, #0xfffffffc +addi ra, s9, #0xfffffffe +addi ra, s9, #0xffffffff +addi ra, s9, #0 +addi ra, s9, #1 +addi ra, s9, #2 +addi ra, s9, #4 +addi ra, s9, #8 +addi ra, s9, #0x10 +addi ra, s9, #0x20 +addi ra, s9, #0x40 +addi ra, s9, #0x80 +addi ra, s9, #0x100 +addi ra, s9, #0x200 +addi ra, s9, #0x400 +addi ra, s9, #0x7ff +addi ra, t6, #0xfffff801 +addi ra, t6, #0xfffffc00 +addi ra, t6, #0xfffffe00 +addi ra, t6, #0xffffff00 +addi ra, t6, #0xffffff80 +addi ra, t6, #0xffffffc0 +addi ra, t6, #0xffffffe0 +addi ra, t6, #0xfffffff0 +addi ra, t6, #0xfffffff8 +addi ra, t6, #0xfffffffc +addi ra, t6, #0xfffffffe +addi ra, t6, #0xffffffff +addi ra, t6, #0 +addi ra, t6, #1 +addi ra, t6, #2 +addi ra, t6, #4 +addi ra, t6, #8 +addi ra, t6, #0x10 +addi ra, t6, #0x20 +addi ra, t6, #0x40 +addi ra, t6, #0x80 +addi ra, t6, #0x100 +addi ra, t6, #0x200 +addi ra, t6, #0x400 +addi ra, t6, #0x7ff +addi t0, zero, #0xfffff801 +addi t0, zero, #0xfffffc00 +addi t0, zero, #0xfffffe00 +addi t0, zero, #0xffffff00 +addi t0, zero, #0xffffff80 +addi t0, zero, #0xffffffc0 +addi t0, zero, #0xffffffe0 +addi t0, zero, #0xfffffff0 +addi t0, zero, #0xfffffff8 +addi t0, zero, #0xfffffffc +addi t0, zero, #0xfffffffe +addi t0, zero, #0xffffffff +addi t0, zero, #0 +addi t0, zero, #1 +addi t0, zero, #2 +addi t0, zero, #4 +addi t0, zero, #8 +addi t0, zero, #0x10 +addi t0, zero, #0x20 +addi t0, zero, #0x40 +addi t0, zero, #0x80 +addi t0, zero, #0x100 +addi t0, zero, #0x200 +addi t0, zero, #0x400 +addi t0, zero, #0x7ff +addi t0, ra, #0xfffff801 +addi t0, ra, #0xfffffc00 +addi t0, ra, #0xfffffe00 +addi t0, ra, #0xffffff00 +addi t0, ra, #0xffffff80 +addi t0, ra, #0xffffffc0 +addi t0, ra, #0xffffffe0 +addi t0, ra, #0xfffffff0 +addi t0, ra, #0xfffffff8 +addi t0, ra, #0xfffffffc +addi t0, ra, #0xfffffffe +addi t0, ra, #0xffffffff +addi t0, ra, #0 +addi t0, ra, #1 +addi t0, ra, #2 +addi t0, ra, #4 +addi t0, ra, #8 +addi t0, ra, #0x10 +addi t0, ra, #0x20 +addi t0, ra, #0x40 +addi t0, ra, #0x80 +addi t0, ra, #0x100 +addi t0, ra, #0x200 +addi t0, ra, #0x400 +addi t0, ra, #0x7ff +addi t0, t0, #0xfffff801 +addi t0, t0, #0xfffffc00 +addi t0, t0, #0xfffffe00 +addi t0, t0, #0xffffff00 +addi t0, t0, #0xffffff80 +addi t0, t0, #0xffffffc0 +addi t0, t0, #0xffffffe0 +addi t0, t0, #0xfffffff0 +addi t0, t0, #0xfffffff8 +addi t0, t0, #0xfffffffc +addi t0, t0, #0xfffffffe +addi t0, t0, #0xffffffff +addi t0, t0, #0 +addi t0, t0, #1 +addi t0, t0, #2 +addi t0, t0, #4 +addi t0, t0, #8 +addi t0, t0, #0x10 +addi t0, t0, #0x20 +addi t0, t0, #0x40 +addi t0, t0, #0x80 +addi t0, t0, #0x100 +addi t0, t0, #0x200 +addi t0, t0, #0x400 +addi t0, t0, #0x7ff +addi t0, a0, #0xfffff801 +addi t0, a0, #0xfffffc00 +addi t0, a0, #0xfffffe00 +addi t0, a0, #0xffffff00 +addi t0, a0, #0xffffff80 +addi t0, a0, #0xffffffc0 +addi t0, a0, #0xffffffe0 +addi t0, a0, #0xfffffff0 +addi t0, a0, #0xfffffff8 +addi t0, a0, #0xfffffffc +addi t0, a0, #0xfffffffe +addi t0, a0, #0xffffffff +addi t0, a0, #0 +addi t0, a0, #1 +addi t0, a0, #2 +addi t0, a0, #4 +addi t0, a0, #8 +addi t0, a0, #0x10 +addi t0, a0, #0x20 +addi t0, a0, #0x40 +addi t0, a0, #0x80 +addi t0, a0, #0x100 +addi t0, a0, #0x200 +addi t0, a0, #0x400 +addi t0, a0, #0x7ff +addi t0, a5, #0xfffff801 +addi t0, a5, #0xfffffc00 +addi t0, a5, #0xfffffe00 +addi t0, a5, #0xffffff00 +addi t0, a5, #0xffffff80 +addi t0, a5, #0xffffffc0 +addi t0, a5, #0xffffffe0 +addi t0, a5, #0xfffffff0 +addi t0, a5, #0xfffffff8 +addi t0, a5, #0xfffffffc +addi t0, a5, #0xfffffffe +addi t0, a5, #0xffffffff +addi t0, a5, #0 +addi t0, a5, #1 +addi t0, a5, #2 +addi t0, a5, #4 +addi t0, a5, #8 +addi t0, a5, #0x10 +addi t0, a5, #0x20 +addi t0, a5, #0x40 +addi t0, a5, #0x80 +addi t0, a5, #0x100 +addi t0, a5, #0x200 +addi t0, a5, #0x400 +addi t0, a5, #0x7ff +addi t0, s4, #0xfffff801 +addi t0, s4, #0xfffffc00 +addi t0, s4, #0xfffffe00 +addi t0, s4, #0xffffff00 +addi t0, s4, #0xffffff80 +addi t0, s4, #0xffffffc0 +addi t0, s4, #0xffffffe0 +addi t0, s4, #0xfffffff0 +addi t0, s4, #0xfffffff8 +addi t0, s4, #0xfffffffc +addi t0, s4, #0xfffffffe +addi t0, s4, #0xffffffff +addi t0, s4, #0 +addi t0, s4, #1 +addi t0, s4, #2 +addi t0, s4, #4 +addi t0, s4, #8 +addi t0, s4, #0x10 +addi t0, s4, #0x20 +addi t0, s4, #0x40 +addi t0, s4, #0x80 +addi t0, s4, #0x100 +addi t0, s4, #0x200 +addi t0, s4, #0x400 +addi t0, s4, #0x7ff +addi t0, s9, #0xfffff801 +addi t0, s9, #0xfffffc00 +addi t0, s9, #0xfffffe00 +addi t0, s9, #0xffffff00 +addi t0, s9, #0xffffff80 +addi t0, s9, #0xffffffc0 +addi t0, s9, #0xffffffe0 +addi t0, s9, #0xfffffff0 +addi t0, s9, #0xfffffff8 +addi t0, s9, #0xfffffffc +addi t0, s9, #0xfffffffe +addi t0, s9, #0xffffffff +addi t0, s9, #0 +addi t0, s9, #1 +addi t0, s9, #2 +addi t0, s9, #4 +addi t0, s9, #8 +addi t0, s9, #0x10 +addi t0, s9, #0x20 +addi t0, s9, #0x40 +addi t0, s9, #0x80 +addi t0, s9, #0x100 +addi t0, s9, #0x200 +addi t0, s9, #0x400 +addi t0, s9, #0x7ff +addi t0, t6, #0xfffff801 +addi t0, t6, #0xfffffc00 +addi t0, t6, #0xfffffe00 +addi t0, t6, #0xffffff00 +addi t0, t6, #0xffffff80 +addi t0, t6, #0xffffffc0 +addi t0, t6, #0xffffffe0 +addi t0, t6, #0xfffffff0 +addi t0, t6, #0xfffffff8 +addi t0, t6, #0xfffffffc +addi t0, t6, #0xfffffffe +addi t0, t6, #0xffffffff +addi t0, t6, #0 +addi t0, t6, #1 +addi t0, t6, #2 +addi t0, t6, #4 +addi t0, t6, #8 +addi t0, t6, #0x10 +addi t0, t6, #0x20 +addi t0, t6, #0x40 +addi t0, t6, #0x80 +addi t0, t6, #0x100 +addi t0, t6, #0x200 +addi t0, t6, #0x400 +addi t0, t6, #0x7ff +addi a0, zero, #0xfffff801 +addi a0, zero, #0xfffffc00 +addi a0, zero, #0xfffffe00 +addi a0, zero, #0xffffff00 +addi a0, zero, #0xffffff80 +addi a0, zero, #0xffffffc0 +addi a0, zero, #0xffffffe0 +addi a0, zero, #0xfffffff0 +addi a0, zero, #0xfffffff8 +addi a0, zero, #0xfffffffc +addi a0, zero, #0xfffffffe +addi a0, zero, #0xffffffff +addi a0, zero, #0 +addi a0, zero, #1 +addi a0, zero, #2 +addi a0, zero, #4 +addi a0, zero, #8 +addi a0, zero, #0x10 +addi a0, zero, #0x20 +addi a0, zero, #0x40 +addi a0, zero, #0x80 +addi a0, zero, #0x100 +addi a0, zero, #0x200 +addi a0, zero, #0x400 +addi a0, zero, #0x7ff +addi a0, ra, #0xfffff801 +addi a0, ra, #0xfffffc00 +addi a0, ra, #0xfffffe00 +addi a0, ra, #0xffffff00 +addi a0, ra, #0xffffff80 +addi a0, ra, #0xffffffc0 +addi a0, ra, #0xffffffe0 +addi a0, ra, #0xfffffff0 +addi a0, ra, #0xfffffff8 +addi a0, ra, #0xfffffffc +addi a0, ra, #0xfffffffe +addi a0, ra, #0xffffffff +addi a0, ra, #0 +addi a0, ra, #1 +addi a0, ra, #2 +addi a0, ra, #4 +addi a0, ra, #8 +addi a0, ra, #0x10 +addi a0, ra, #0x20 +addi a0, ra, #0x40 +addi a0, ra, #0x80 +addi a0, ra, #0x100 +addi a0, ra, #0x200 +addi a0, ra, #0x400 +addi a0, ra, #0x7ff +addi a0, t0, #0xfffff801 +addi a0, t0, #0xfffffc00 +addi a0, t0, #0xfffffe00 +addi a0, t0, #0xffffff00 +addi a0, t0, #0xffffff80 +addi a0, t0, #0xffffffc0 +addi a0, t0, #0xffffffe0 +addi a0, t0, #0xfffffff0 +addi a0, t0, #0xfffffff8 +addi a0, t0, #0xfffffffc +addi a0, t0, #0xfffffffe +addi a0, t0, #0xffffffff +addi a0, t0, #0 +addi a0, t0, #1 +addi a0, t0, #2 +addi a0, t0, #4 +addi a0, t0, #8 +addi a0, t0, #0x10 +addi a0, t0, #0x20 +addi a0, t0, #0x40 +addi a0, t0, #0x80 +addi a0, t0, #0x100 +addi a0, t0, #0x200 +addi a0, t0, #0x400 +addi a0, t0, #0x7ff +addi a0, a0, #0xfffff801 +addi a0, a0, #0xfffffc00 +addi a0, a0, #0xfffffe00 +addi a0, a0, #0xffffff00 +addi a0, a0, #0xffffff80 +addi a0, a0, #0xffffffc0 +addi a0, a0, #0xffffffe0 +addi a0, a0, #0xfffffff0 +addi a0, a0, #0xfffffff8 +addi a0, a0, #0xfffffffc +addi a0, a0, #0xfffffffe +addi a0, a0, #0xffffffff +addi a0, a0, #0 +addi a0, a0, #1 +addi a0, a0, #2 +addi a0, a0, #4 +addi a0, a0, #8 +addi a0, a0, #0x10 +addi a0, a0, #0x20 +addi a0, a0, #0x40 +addi a0, a0, #0x80 +addi a0, a0, #0x100 +addi a0, a0, #0x200 +addi a0, a0, #0x400 +addi a0, a0, #0x7ff +addi a0, a5, #0xfffff801 +addi a0, a5, #0xfffffc00 +addi a0, a5, #0xfffffe00 +addi a0, a5, #0xffffff00 +addi a0, a5, #0xffffff80 +addi a0, a5, #0xffffffc0 +addi a0, a5, #0xffffffe0 +addi a0, a5, #0xfffffff0 +addi a0, a5, #0xfffffff8 +addi a0, a5, #0xfffffffc +addi a0, a5, #0xfffffffe +addi a0, a5, #0xffffffff +addi a0, a5, #0 +addi a0, a5, #1 +addi a0, a5, #2 +addi a0, a5, #4 +addi a0, a5, #8 +addi a0, a5, #0x10 +addi a0, a5, #0x20 +addi a0, a5, #0x40 +addi a0, a5, #0x80 +addi a0, a5, #0x100 +addi a0, a5, #0x200 +addi a0, a5, #0x400 +addi a0, a5, #0x7ff +addi a0, s4, #0xfffff801 +addi a0, s4, #0xfffffc00 +addi a0, s4, #0xfffffe00 +addi a0, s4, #0xffffff00 +addi a0, s4, #0xffffff80 +addi a0, s4, #0xffffffc0 +addi a0, s4, #0xffffffe0 +addi a0, s4, #0xfffffff0 +addi a0, s4, #0xfffffff8 +addi a0, s4, #0xfffffffc +addi a0, s4, #0xfffffffe +addi a0, s4, #0xffffffff +addi a0, s4, #0 +addi a0, s4, #1 +addi a0, s4, #2 +addi a0, s4, #4 +addi a0, s4, #8 +addi a0, s4, #0x10 +addi a0, s4, #0x20 +addi a0, s4, #0x40 +addi a0, s4, #0x80 +addi a0, s4, #0x100 +addi a0, s4, #0x200 +addi a0, s4, #0x400 +addi a0, s4, #0x7ff +addi a0, s9, #0xfffff801 +addi a0, s9, #0xfffffc00 +addi a0, s9, #0xfffffe00 +addi a0, s9, #0xffffff00 +addi a0, s9, #0xffffff80 +addi a0, s9, #0xffffffc0 +addi a0, s9, #0xffffffe0 +addi a0, s9, #0xfffffff0 +addi a0, s9, #0xfffffff8 +addi a0, s9, #0xfffffffc +addi a0, s9, #0xfffffffe +addi a0, s9, #0xffffffff +addi a0, s9, #0 +addi a0, s9, #1 +addi a0, s9, #2 +addi a0, s9, #4 +addi a0, s9, #8 +addi a0, s9, #0x10 +addi a0, s9, #0x20 +addi a0, s9, #0x40 +addi a0, s9, #0x80 +addi a0, s9, #0x100 +addi a0, s9, #0x200 +addi a0, s9, #0x400 +addi a0, s9, #0x7ff +addi a0, t6, #0xfffff801 +addi a0, t6, #0xfffffc00 +addi a0, t6, #0xfffffe00 +addi a0, t6, #0xffffff00 +addi a0, t6, #0xffffff80 +addi a0, t6, #0xffffffc0 +addi a0, t6, #0xffffffe0 +addi a0, t6, #0xfffffff0 +addi a0, t6, #0xfffffff8 +addi a0, t6, #0xfffffffc +addi a0, t6, #0xfffffffe +addi a0, t6, #0xffffffff +addi a0, t6, #0 +addi a0, t6, #1 +addi a0, t6, #2 +addi a0, t6, #4 +addi a0, t6, #8 +addi a0, t6, #0x10 +addi a0, t6, #0x20 +addi a0, t6, #0x40 +addi a0, t6, #0x80 +addi a0, t6, #0x100 +addi a0, t6, #0x200 +addi a0, t6, #0x400 +addi a0, t6, #0x7ff +addi a5, zero, #0xfffff801 +addi a5, zero, #0xfffffc00 +addi a5, zero, #0xfffffe00 +addi a5, zero, #0xffffff00 +addi a5, zero, #0xffffff80 +addi a5, zero, #0xffffffc0 +addi a5, zero, #0xffffffe0 +addi a5, zero, #0xfffffff0 +addi a5, zero, #0xfffffff8 +addi a5, zero, #0xfffffffc +addi a5, zero, #0xfffffffe +addi a5, zero, #0xffffffff +addi a5, zero, #0 +addi a5, zero, #1 +addi a5, zero, #2 +addi a5, zero, #4 +addi a5, zero, #8 +addi a5, zero, #0x10 +addi a5, zero, #0x20 +addi a5, zero, #0x40 +addi a5, zero, #0x80 +addi a5, zero, #0x100 +addi a5, zero, #0x200 +addi a5, zero, #0x400 +addi a5, zero, #0x7ff +addi a5, ra, #0xfffff801 +addi a5, ra, #0xfffffc00 +addi a5, ra, #0xfffffe00 +addi a5, ra, #0xffffff00 +addi a5, ra, #0xffffff80 +addi a5, ra, #0xffffffc0 +addi a5, ra, #0xffffffe0 +addi a5, ra, #0xfffffff0 +addi a5, ra, #0xfffffff8 +addi a5, ra, #0xfffffffc +addi a5, ra, #0xfffffffe +addi a5, ra, #0xffffffff +addi a5, ra, #0 +addi a5, ra, #1 +addi a5, ra, #2 +addi a5, ra, #4 +addi a5, ra, #8 +addi a5, ra, #0x10 +addi a5, ra, #0x20 +addi a5, ra, #0x40 +addi a5, ra, #0x80 +addi a5, ra, #0x100 +addi a5, ra, #0x200 +addi a5, ra, #0x400 +addi a5, ra, #0x7ff +addi a5, t0, #0xfffff801 +addi a5, t0, #0xfffffc00 +addi a5, t0, #0xfffffe00 +addi a5, t0, #0xffffff00 +addi a5, t0, #0xffffff80 +addi a5, t0, #0xffffffc0 +addi a5, t0, #0xffffffe0 +addi a5, t0, #0xfffffff0 +addi a5, t0, #0xfffffff8 +addi a5, t0, #0xfffffffc +addi a5, t0, #0xfffffffe +addi a5, t0, #0xffffffff +addi a5, t0, #0 +addi a5, t0, #1 +addi a5, t0, #2 +addi a5, t0, #4 +addi a5, t0, #8 +addi a5, t0, #0x10 +addi a5, t0, #0x20 +addi a5, t0, #0x40 +addi a5, t0, #0x80 +addi a5, t0, #0x100 +addi a5, t0, #0x200 +addi a5, t0, #0x400 +addi a5, t0, #0x7ff +addi a5, a0, #0xfffff801 +addi a5, a0, #0xfffffc00 +addi a5, a0, #0xfffffe00 +addi a5, a0, #0xffffff00 +addi a5, a0, #0xffffff80 +addi a5, a0, #0xffffffc0 +addi a5, a0, #0xffffffe0 +addi a5, a0, #0xfffffff0 +addi a5, a0, #0xfffffff8 +addi a5, a0, #0xfffffffc +addi a5, a0, #0xfffffffe +addi a5, a0, #0xffffffff +addi a5, a0, #0 +addi a5, a0, #1 +addi a5, a0, #2 +addi a5, a0, #4 +addi a5, a0, #8 +addi a5, a0, #0x10 +addi a5, a0, #0x20 +addi a5, a0, #0x40 +addi a5, a0, #0x80 +addi a5, a0, #0x100 +addi a5, a0, #0x200 +addi a5, a0, #0x400 +addi a5, a0, #0x7ff +addi a5, a5, #0xfffff801 +addi a5, a5, #0xfffffc00 +addi a5, a5, #0xfffffe00 +addi a5, a5, #0xffffff00 +addi a5, a5, #0xffffff80 +addi a5, a5, #0xffffffc0 +addi a5, a5, #0xffffffe0 +addi a5, a5, #0xfffffff0 +addi a5, a5, #0xfffffff8 +addi a5, a5, #0xfffffffc +addi a5, a5, #0xfffffffe +addi a5, a5, #0xffffffff +addi a5, a5, #0 +addi a5, a5, #1 +addi a5, a5, #2 +addi a5, a5, #4 +addi a5, a5, #8 +addi a5, a5, #0x10 +addi a5, a5, #0x20 +addi a5, a5, #0x40 +addi a5, a5, #0x80 +addi a5, a5, #0x100 +addi a5, a5, #0x200 +addi a5, a5, #0x400 +addi a5, a5, #0x7ff +addi a5, s4, #0xfffff801 +addi a5, s4, #0xfffffc00 +addi a5, s4, #0xfffffe00 +addi a5, s4, #0xffffff00 +addi a5, s4, #0xffffff80 +addi a5, s4, #0xffffffc0 +addi a5, s4, #0xffffffe0 +addi a5, s4, #0xfffffff0 +addi a5, s4, #0xfffffff8 +addi a5, s4, #0xfffffffc +addi a5, s4, #0xfffffffe +addi a5, s4, #0xffffffff +addi a5, s4, #0 +addi a5, s4, #1 +addi a5, s4, #2 +addi a5, s4, #4 +addi a5, s4, #8 +addi a5, s4, #0x10 +addi a5, s4, #0x20 +addi a5, s4, #0x40 +addi a5, s4, #0x80 +addi a5, s4, #0x100 +addi a5, s4, #0x200 +addi a5, s4, #0x400 +addi a5, s4, #0x7ff +addi a5, s9, #0xfffff801 +addi a5, s9, #0xfffffc00 +addi a5, s9, #0xfffffe00 +addi a5, s9, #0xffffff00 +addi a5, s9, #0xffffff80 +addi a5, s9, #0xffffffc0 +addi a5, s9, #0xffffffe0 +addi a5, s9, #0xfffffff0 +addi a5, s9, #0xfffffff8 +addi a5, s9, #0xfffffffc +addi a5, s9, #0xfffffffe +addi a5, s9, #0xffffffff +addi a5, s9, #0 +addi a5, s9, #1 +addi a5, s9, #2 +addi a5, s9, #4 +addi a5, s9, #8 +addi a5, s9, #0x10 +addi a5, s9, #0x20 +addi a5, s9, #0x40 +addi a5, s9, #0x80 +addi a5, s9, #0x100 +addi a5, s9, #0x200 +addi a5, s9, #0x400 +addi a5, s9, #0x7ff +addi a5, t6, #0xfffff801 +addi a5, t6, #0xfffffc00 +addi a5, t6, #0xfffffe00 +addi a5, t6, #0xffffff00 +addi a5, t6, #0xffffff80 +addi a5, t6, #0xffffffc0 +addi a5, t6, #0xffffffe0 +addi a5, t6, #0xfffffff0 +addi a5, t6, #0xfffffff8 +addi a5, t6, #0xfffffffc +addi a5, t6, #0xfffffffe +addi a5, t6, #0xffffffff +addi a5, t6, #0 +addi a5, t6, #1 +addi a5, t6, #2 +addi a5, t6, #4 +addi a5, t6, #8 +addi a5, t6, #0x10 +addi a5, t6, #0x20 +addi a5, t6, #0x40 +addi a5, t6, #0x80 +addi a5, t6, #0x100 +addi a5, t6, #0x200 +addi a5, t6, #0x400 +addi a5, t6, #0x7ff +addi s4, zero, #0xfffff801 +addi s4, zero, #0xfffffc00 +addi s4, zero, #0xfffffe00 +addi s4, zero, #0xffffff00 +addi s4, zero, #0xffffff80 +addi s4, zero, #0xffffffc0 +addi s4, zero, #0xffffffe0 +addi s4, zero, #0xfffffff0 +addi s4, zero, #0xfffffff8 +addi s4, zero, #0xfffffffc +addi s4, zero, #0xfffffffe +addi s4, zero, #0xffffffff +addi s4, zero, #0 +addi s4, zero, #1 +addi s4, zero, #2 +addi s4, zero, #4 +addi s4, zero, #8 +addi s4, zero, #0x10 +addi s4, zero, #0x20 +addi s4, zero, #0x40 +addi s4, zero, #0x80 +addi s4, zero, #0x100 +addi s4, zero, #0x200 +addi s4, zero, #0x400 +addi s4, zero, #0x7ff +addi s4, ra, #0xfffff801 +addi s4, ra, #0xfffffc00 +addi s4, ra, #0xfffffe00 +addi s4, ra, #0xffffff00 +addi s4, ra, #0xffffff80 +addi s4, ra, #0xffffffc0 +addi s4, ra, #0xffffffe0 +addi s4, ra, #0xfffffff0 +addi s4, ra, #0xfffffff8 +addi s4, ra, #0xfffffffc +addi s4, ra, #0xfffffffe +addi s4, ra, #0xffffffff +addi s4, ra, #0 +addi s4, ra, #1 +addi s4, ra, #2 +addi s4, ra, #4 +addi s4, ra, #8 +addi s4, ra, #0x10 +addi s4, ra, #0x20 +addi s4, ra, #0x40 +addi s4, ra, #0x80 +addi s4, ra, #0x100 +addi s4, ra, #0x200 +addi s4, ra, #0x400 +addi s4, ra, #0x7ff +addi s4, t0, #0xfffff801 +addi s4, t0, #0xfffffc00 +addi s4, t0, #0xfffffe00 +addi s4, t0, #0xffffff00 +addi s4, t0, #0xffffff80 +addi s4, t0, #0xffffffc0 +addi s4, t0, #0xffffffe0 +addi s4, t0, #0xfffffff0 +addi s4, t0, #0xfffffff8 +addi s4, t0, #0xfffffffc +addi s4, t0, #0xfffffffe +addi s4, t0, #0xffffffff +addi s4, t0, #0 +addi s4, t0, #1 +addi s4, t0, #2 +addi s4, t0, #4 +addi s4, t0, #8 +addi s4, t0, #0x10 +addi s4, t0, #0x20 +addi s4, t0, #0x40 +addi s4, t0, #0x80 +addi s4, t0, #0x100 +addi s4, t0, #0x200 +addi s4, t0, #0x400 +addi s4, t0, #0x7ff +addi s4, a0, #0xfffff801 +addi s4, a0, #0xfffffc00 +addi s4, a0, #0xfffffe00 +addi s4, a0, #0xffffff00 +addi s4, a0, #0xffffff80 +addi s4, a0, #0xffffffc0 +addi s4, a0, #0xffffffe0 +addi s4, a0, #0xfffffff0 +addi s4, a0, #0xfffffff8 +addi s4, a0, #0xfffffffc +addi s4, a0, #0xfffffffe +addi s4, a0, #0xffffffff +addi s4, a0, #0 +addi s4, a0, #1 +addi s4, a0, #2 +addi s4, a0, #4 +addi s4, a0, #8 +addi s4, a0, #0x10 +addi s4, a0, #0x20 +addi s4, a0, #0x40 +addi s4, a0, #0x80 +addi s4, a0, #0x100 +addi s4, a0, #0x200 +addi s4, a0, #0x400 +addi s4, a0, #0x7ff +addi s4, a5, #0xfffff801 +addi s4, a5, #0xfffffc00 +addi s4, a5, #0xfffffe00 +addi s4, a5, #0xffffff00 +addi s4, a5, #0xffffff80 +addi s4, a5, #0xffffffc0 +addi s4, a5, #0xffffffe0 +addi s4, a5, #0xfffffff0 +addi s4, a5, #0xfffffff8 +addi s4, a5, #0xfffffffc +addi s4, a5, #0xfffffffe +addi s4, a5, #0xffffffff +addi s4, a5, #0 +addi s4, a5, #1 +addi s4, a5, #2 +addi s4, a5, #4 +addi s4, a5, #8 +addi s4, a5, #0x10 +addi s4, a5, #0x20 +addi s4, a5, #0x40 +addi s4, a5, #0x80 +addi s4, a5, #0x100 +addi s4, a5, #0x200 +addi s4, a5, #0x400 +addi s4, a5, #0x7ff +addi s4, s4, #0xfffff801 +addi s4, s4, #0xfffffc00 +addi s4, s4, #0xfffffe00 +addi s4, s4, #0xffffff00 +addi s4, s4, #0xffffff80 +addi s4, s4, #0xffffffc0 +addi s4, s4, #0xffffffe0 +addi s4, s4, #0xfffffff0 +addi s4, s4, #0xfffffff8 +addi s4, s4, #0xfffffffc +addi s4, s4, #0xfffffffe +addi s4, s4, #0xffffffff +addi s4, s4, #0 +addi s4, s4, #1 +addi s4, s4, #2 +addi s4, s4, #4 +addi s4, s4, #8 +addi s4, s4, #0x10 +addi s4, s4, #0x20 +addi s4, s4, #0x40 +addi s4, s4, #0x80 +addi s4, s4, #0x100 +addi s4, s4, #0x200 +addi s4, s4, #0x400 +addi s4, s4, #0x7ff +addi s4, s9, #0xfffff801 +addi s4, s9, #0xfffffc00 +addi s4, s9, #0xfffffe00 +addi s4, s9, #0xffffff00 +addi s4, s9, #0xffffff80 +addi s4, s9, #0xffffffc0 +addi s4, s9, #0xffffffe0 +addi s4, s9, #0xfffffff0 +addi s4, s9, #0xfffffff8 +addi s4, s9, #0xfffffffc +addi s4, s9, #0xfffffffe +addi s4, s9, #0xffffffff +addi s4, s9, #0 +addi s4, s9, #1 +addi s4, s9, #2 +addi s4, s9, #4 +addi s4, s9, #8 +addi s4, s9, #0x10 +addi s4, s9, #0x20 +addi s4, s9, #0x40 +addi s4, s9, #0x80 +addi s4, s9, #0x100 +addi s4, s9, #0x200 +addi s4, s9, #0x400 +addi s4, s9, #0x7ff +addi s4, t6, #0xfffff801 +addi s4, t6, #0xfffffc00 +addi s4, t6, #0xfffffe00 +addi s4, t6, #0xffffff00 +addi s4, t6, #0xffffff80 +addi s4, t6, #0xffffffc0 +addi s4, t6, #0xffffffe0 +addi s4, t6, #0xfffffff0 +addi s4, t6, #0xfffffff8 +addi s4, t6, #0xfffffffc +addi s4, t6, #0xfffffffe +addi s4, t6, #0xffffffff +addi s4, t6, #0 +addi s4, t6, #1 +addi s4, t6, #2 +addi s4, t6, #4 +addi s4, t6, #8 +addi s4, t6, #0x10 +addi s4, t6, #0x20 +addi s4, t6, #0x40 +addi s4, t6, #0x80 +addi s4, t6, #0x100 +addi s4, t6, #0x200 +addi s4, t6, #0x400 +addi s4, t6, #0x7ff +addi s9, zero, #0xfffff801 +addi s9, zero, #0xfffffc00 +addi s9, zero, #0xfffffe00 +addi s9, zero, #0xffffff00 +addi s9, zero, #0xffffff80 +addi s9, zero, #0xffffffc0 +addi s9, zero, #0xffffffe0 +addi s9, zero, #0xfffffff0 +addi s9, zero, #0xfffffff8 +addi s9, zero, #0xfffffffc +addi s9, zero, #0xfffffffe +addi s9, zero, #0xffffffff +addi s9, zero, #0 +addi s9, zero, #1 +addi s9, zero, #2 +addi s9, zero, #4 +addi s9, zero, #8 +addi s9, zero, #0x10 +addi s9, zero, #0x20 +addi s9, zero, #0x40 +addi s9, zero, #0x80 +addi s9, zero, #0x100 +addi s9, zero, #0x200 +addi s9, zero, #0x400 +addi s9, zero, #0x7ff +addi s9, ra, #0xfffff801 +addi s9, ra, #0xfffffc00 +addi s9, ra, #0xfffffe00 +addi s9, ra, #0xffffff00 +addi s9, ra, #0xffffff80 +addi s9, ra, #0xffffffc0 +addi s9, ra, #0xffffffe0 +addi s9, ra, #0xfffffff0 +addi s9, ra, #0xfffffff8 +addi s9, ra, #0xfffffffc +addi s9, ra, #0xfffffffe +addi s9, ra, #0xffffffff +addi s9, ra, #0 +addi s9, ra, #1 +addi s9, ra, #2 +addi s9, ra, #4 +addi s9, ra, #8 +addi s9, ra, #0x10 +addi s9, ra, #0x20 +addi s9, ra, #0x40 +addi s9, ra, #0x80 +addi s9, ra, #0x100 +addi s9, ra, #0x200 +addi s9, ra, #0x400 +addi s9, ra, #0x7ff +addi s9, t0, #0xfffff801 +addi s9, t0, #0xfffffc00 +addi s9, t0, #0xfffffe00 +addi s9, t0, #0xffffff00 +addi s9, t0, #0xffffff80 +addi s9, t0, #0xffffffc0 +addi s9, t0, #0xffffffe0 +addi s9, t0, #0xfffffff0 +addi s9, t0, #0xfffffff8 +addi s9, t0, #0xfffffffc +addi s9, t0, #0xfffffffe +addi s9, t0, #0xffffffff +addi s9, t0, #0 +addi s9, t0, #1 +addi s9, t0, #2 +addi s9, t0, #4 +addi s9, t0, #8 +addi s9, t0, #0x10 +addi s9, t0, #0x20 +addi s9, t0, #0x40 +addi s9, t0, #0x80 +addi s9, t0, #0x100 +addi s9, t0, #0x200 +addi s9, t0, #0x400 +addi s9, t0, #0x7ff +addi s9, a0, #0xfffff801 +addi s9, a0, #0xfffffc00 +addi s9, a0, #0xfffffe00 +addi s9, a0, #0xffffff00 +addi s9, a0, #0xffffff80 +addi s9, a0, #0xffffffc0 +addi s9, a0, #0xffffffe0 +addi s9, a0, #0xfffffff0 +addi s9, a0, #0xfffffff8 +addi s9, a0, #0xfffffffc +addi s9, a0, #0xfffffffe +addi s9, a0, #0xffffffff +addi s9, a0, #0 +addi s9, a0, #1 +addi s9, a0, #2 +addi s9, a0, #4 +addi s9, a0, #8 +addi s9, a0, #0x10 +addi s9, a0, #0x20 +addi s9, a0, #0x40 +addi s9, a0, #0x80 +addi s9, a0, #0x100 +addi s9, a0, #0x200 +addi s9, a0, #0x400 +addi s9, a0, #0x7ff +addi s9, a5, #0xfffff801 +addi s9, a5, #0xfffffc00 +addi s9, a5, #0xfffffe00 +addi s9, a5, #0xffffff00 +addi s9, a5, #0xffffff80 +addi s9, a5, #0xffffffc0 +addi s9, a5, #0xffffffe0 +addi s9, a5, #0xfffffff0 +addi s9, a5, #0xfffffff8 +addi s9, a5, #0xfffffffc +addi s9, a5, #0xfffffffe +addi s9, a5, #0xffffffff +addi s9, a5, #0 +addi s9, a5, #1 +addi s9, a5, #2 +addi s9, a5, #4 +addi s9, a5, #8 +addi s9, a5, #0x10 +addi s9, a5, #0x20 +addi s9, a5, #0x40 +addi s9, a5, #0x80 +addi s9, a5, #0x100 +addi s9, a5, #0x200 +addi s9, a5, #0x400 +addi s9, a5, #0x7ff +addi s9, s4, #0xfffff801 +addi s9, s4, #0xfffffc00 +addi s9, s4, #0xfffffe00 +addi s9, s4, #0xffffff00 +addi s9, s4, #0xffffff80 +addi s9, s4, #0xffffffc0 +addi s9, s4, #0xffffffe0 +addi s9, s4, #0xfffffff0 +addi s9, s4, #0xfffffff8 +addi s9, s4, #0xfffffffc +addi s9, s4, #0xfffffffe +addi s9, s4, #0xffffffff +addi s9, s4, #0 +addi s9, s4, #1 +addi s9, s4, #2 +addi s9, s4, #4 +addi s9, s4, #8 +addi s9, s4, #0x10 +addi s9, s4, #0x20 +addi s9, s4, #0x40 +addi s9, s4, #0x80 +addi s9, s4, #0x100 +addi s9, s4, #0x200 +addi s9, s4, #0x400 +addi s9, s4, #0x7ff +addi s9, s9, #0xfffff801 +addi s9, s9, #0xfffffc00 +addi s9, s9, #0xfffffe00 +addi s9, s9, #0xffffff00 +addi s9, s9, #0xffffff80 +addi s9, s9, #0xffffffc0 +addi s9, s9, #0xffffffe0 +addi s9, s9, #0xfffffff0 +addi s9, s9, #0xfffffff8 +addi s9, s9, #0xfffffffc +addi s9, s9, #0xfffffffe +addi s9, s9, #0xffffffff +addi s9, s9, #0 +addi s9, s9, #1 +addi s9, s9, #2 +addi s9, s9, #4 +addi s9, s9, #8 +addi s9, s9, #0x10 +addi s9, s9, #0x20 +addi s9, s9, #0x40 +addi s9, s9, #0x80 +addi s9, s9, #0x100 +addi s9, s9, #0x200 +addi s9, s9, #0x400 +addi s9, s9, #0x7ff +addi s9, t6, #0xfffff801 +addi s9, t6, #0xfffffc00 +addi s9, t6, #0xfffffe00 +addi s9, t6, #0xffffff00 +addi s9, t6, #0xffffff80 +addi s9, t6, #0xffffffc0 +addi s9, t6, #0xffffffe0 +addi s9, t6, #0xfffffff0 +addi s9, t6, #0xfffffff8 +addi s9, t6, #0xfffffffc +addi s9, t6, #0xfffffffe +addi s9, t6, #0xffffffff +addi s9, t6, #0 +addi s9, t6, #1 +addi s9, t6, #2 +addi s9, t6, #4 +addi s9, t6, #8 +addi s9, t6, #0x10 +addi s9, t6, #0x20 +addi s9, t6, #0x40 +addi s9, t6, #0x80 +addi s9, t6, #0x100 +addi s9, t6, #0x200 +addi s9, t6, #0x400 +addi s9, t6, #0x7ff +addi t6, zero, #0xfffff801 +addi t6, zero, #0xfffffc00 +addi t6, zero, #0xfffffe00 +addi t6, zero, #0xffffff00 +addi t6, zero, #0xffffff80 +addi t6, zero, #0xffffffc0 +addi t6, zero, #0xffffffe0 +addi t6, zero, #0xfffffff0 +addi t6, zero, #0xfffffff8 +addi t6, zero, #0xfffffffc +addi t6, zero, #0xfffffffe +addi t6, zero, #0xffffffff +addi t6, zero, #0 +addi t6, zero, #1 +addi t6, zero, #2 +addi t6, zero, #4 +addi t6, zero, #8 +addi t6, zero, #0x10 +addi t6, zero, #0x20 +addi t6, zero, #0x40 +addi t6, zero, #0x80 +addi t6, zero, #0x100 +addi t6, zero, #0x200 +addi t6, zero, #0x400 +addi t6, zero, #0x7ff +addi t6, ra, #0xfffff801 +addi t6, ra, #0xfffffc00 +addi t6, ra, #0xfffffe00 +addi t6, ra, #0xffffff00 +addi t6, ra, #0xffffff80 +addi t6, ra, #0xffffffc0 +addi t6, ra, #0xffffffe0 +addi t6, ra, #0xfffffff0 +addi t6, ra, #0xfffffff8 +addi t6, ra, #0xfffffffc +addi t6, ra, #0xfffffffe +addi t6, ra, #0xffffffff +addi t6, ra, #0 +addi t6, ra, #1 +addi t6, ra, #2 +addi t6, ra, #4 +addi t6, ra, #8 +addi t6, ra, #0x10 +addi t6, ra, #0x20 +addi t6, ra, #0x40 +addi t6, ra, #0x80 +addi t6, ra, #0x100 +addi t6, ra, #0x200 +addi t6, ra, #0x400 +addi t6, ra, #0x7ff +addi t6, t0, #0xfffff801 +addi t6, t0, #0xfffffc00 +addi t6, t0, #0xfffffe00 +addi t6, t0, #0xffffff00 +addi t6, t0, #0xffffff80 +addi t6, t0, #0xffffffc0 +addi t6, t0, #0xffffffe0 +addi t6, t0, #0xfffffff0 +addi t6, t0, #0xfffffff8 +addi t6, t0, #0xfffffffc +addi t6, t0, #0xfffffffe +addi t6, t0, #0xffffffff +addi t6, t0, #0 +addi t6, t0, #1 +addi t6, t0, #2 +addi t6, t0, #4 +addi t6, t0, #8 +addi t6, t0, #0x10 +addi t6, t0, #0x20 +addi t6, t0, #0x40 +addi t6, t0, #0x80 +addi t6, t0, #0x100 +addi t6, t0, #0x200 +addi t6, t0, #0x400 +addi t6, t0, #0x7ff +addi t6, a0, #0xfffff801 +addi t6, a0, #0xfffffc00 +addi t6, a0, #0xfffffe00 +addi t6, a0, #0xffffff00 +addi t6, a0, #0xffffff80 +addi t6, a0, #0xffffffc0 +addi t6, a0, #0xffffffe0 +addi t6, a0, #0xfffffff0 +addi t6, a0, #0xfffffff8 +addi t6, a0, #0xfffffffc +addi t6, a0, #0xfffffffe +addi t6, a0, #0xffffffff +addi t6, a0, #0 +addi t6, a0, #1 +addi t6, a0, #2 +addi t6, a0, #4 +addi t6, a0, #8 +addi t6, a0, #0x10 +addi t6, a0, #0x20 +addi t6, a0, #0x40 +addi t6, a0, #0x80 +addi t6, a0, #0x100 +addi t6, a0, #0x200 +addi t6, a0, #0x400 +addi t6, a0, #0x7ff +addi t6, a5, #0xfffff801 +addi t6, a5, #0xfffffc00 +addi t6, a5, #0xfffffe00 +addi t6, a5, #0xffffff00 +addi t6, a5, #0xffffff80 +addi t6, a5, #0xffffffc0 +addi t6, a5, #0xffffffe0 +addi t6, a5, #0xfffffff0 +addi t6, a5, #0xfffffff8 +addi t6, a5, #0xfffffffc +addi t6, a5, #0xfffffffe +addi t6, a5, #0xffffffff +addi t6, a5, #0 +addi t6, a5, #1 +addi t6, a5, #2 +addi t6, a5, #4 +addi t6, a5, #8 +addi t6, a5, #0x10 +addi t6, a5, #0x20 +addi t6, a5, #0x40 +addi t6, a5, #0x80 +addi t6, a5, #0x100 +addi t6, a5, #0x200 +addi t6, a5, #0x400 +addi t6, a5, #0x7ff +addi t6, s4, #0xfffff801 +addi t6, s4, #0xfffffc00 +addi t6, s4, #0xfffffe00 +addi t6, s4, #0xffffff00 +addi t6, s4, #0xffffff80 +addi t6, s4, #0xffffffc0 +addi t6, s4, #0xffffffe0 +addi t6, s4, #0xfffffff0 +addi t6, s4, #0xfffffff8 +addi t6, s4, #0xfffffffc +addi t6, s4, #0xfffffffe +addi t6, s4, #0xffffffff +addi t6, s4, #0 +addi t6, s4, #1 +addi t6, s4, #2 +addi t6, s4, #4 +addi t6, s4, #8 +addi t6, s4, #0x10 +addi t6, s4, #0x20 +addi t6, s4, #0x40 +addi t6, s4, #0x80 +addi t6, s4, #0x100 +addi t6, s4, #0x200 +addi t6, s4, #0x400 +addi t6, s4, #0x7ff +addi t6, s9, #0xfffff801 +addi t6, s9, #0xfffffc00 +addi t6, s9, #0xfffffe00 +addi t6, s9, #0xffffff00 +addi t6, s9, #0xffffff80 +addi t6, s9, #0xffffffc0 +addi t6, s9, #0xffffffe0 +addi t6, s9, #0xfffffff0 +addi t6, s9, #0xfffffff8 +addi t6, s9, #0xfffffffc +addi t6, s9, #0xfffffffe +addi t6, s9, #0xffffffff +addi t6, s9, #0 +addi t6, s9, #1 +addi t6, s9, #2 +addi t6, s9, #4 +addi t6, s9, #8 +addi t6, s9, #0x10 +addi t6, s9, #0x20 +addi t6, s9, #0x40 +addi t6, s9, #0x80 +addi t6, s9, #0x100 +addi t6, s9, #0x200 +addi t6, s9, #0x400 +addi t6, s9, #0x7ff +addi t6, t6, #0xfffff801 +addi t6, t6, #0xfffffc00 +addi t6, t6, #0xfffffe00 +addi t6, t6, #0xffffff00 +addi t6, t6, #0xffffff80 +addi t6, t6, #0xffffffc0 +addi t6, t6, #0xffffffe0 +addi t6, t6, #0xfffffff0 +addi t6, t6, #0xfffffff8 +addi t6, t6, #0xfffffffc +addi t6, t6, #0xfffffffe +addi t6, t6, #0xffffffff +addi t6, t6, #0 +addi t6, t6, #1 +addi t6, t6, #2 +addi t6, t6, #4 +addi t6, t6, #8 +addi t6, t6, #0x10 +addi t6, t6, #0x20 +addi t6, t6, #0x40 +addi t6, t6, #0x80 +addi t6, t6, #0x100 +addi t6, t6, #0x200 +addi t6, t6, #0x400 +addi t6, t6, #0x7ff diff --git a/tests/riscv/rv32i/and.asm b/tests/riscv/rv32i/and.asm new file mode 100644 index 0000000..9eda150 --- /dev/null +++ b/tests/riscv/rv32i/and.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +and zero, zero, zero +and zero, zero, ra +and zero, zero, t0 +and zero, zero, a0 +and zero, zero, a5 +and zero, zero, s4 +and zero, zero, s9 +and zero, zero, t6 +and zero, ra, zero +and zero, ra, ra +and zero, ra, t0 +and zero, ra, a0 +and zero, ra, a5 +and zero, ra, s4 +and zero, ra, s9 +and zero, ra, t6 +and zero, t0, zero +and zero, t0, ra +and zero, t0, t0 +and zero, t0, a0 +and zero, t0, a5 +and zero, t0, s4 +and zero, t0, s9 +and zero, t0, t6 +and zero, a0, zero +and zero, a0, ra +and zero, a0, t0 +and zero, a0, a0 +and zero, a0, a5 +and zero, a0, s4 +and zero, a0, s9 +and zero, a0, t6 +and zero, a5, zero +and zero, a5, ra +and zero, a5, t0 +and zero, a5, a0 +and zero, a5, a5 +and zero, a5, s4 +and zero, a5, s9 +and zero, a5, t6 +and zero, s4, zero +and zero, s4, ra +and zero, s4, t0 +and zero, s4, a0 +and zero, s4, a5 +and zero, s4, s4 +and zero, s4, s9 +and zero, s4, t6 +and zero, s9, zero +and zero, s9, ra +and zero, s9, t0 +and zero, s9, a0 +and zero, s9, a5 +and zero, s9, s4 +and zero, s9, s9 +and zero, s9, t6 +and zero, t6, zero +and zero, t6, ra +and zero, t6, t0 +and zero, t6, a0 +and zero, t6, a5 +and zero, t6, s4 +and zero, t6, s9 +and zero, t6, t6 +and ra, zero, zero +and ra, zero, ra +and ra, zero, t0 +and ra, zero, a0 +and ra, zero, a5 +and ra, zero, s4 +and ra, zero, s9 +and ra, zero, t6 +and ra, ra, zero +and ra, ra, ra +and ra, ra, t0 +and ra, ra, a0 +and ra, ra, a5 +and ra, ra, s4 +and ra, ra, s9 +and ra, ra, t6 +and ra, t0, zero +and ra, t0, ra +and ra, t0, t0 +and ra, t0, a0 +and ra, t0, a5 +and ra, t0, s4 +and ra, t0, s9 +and ra, t0, t6 +and ra, a0, zero +and ra, a0, ra +and ra, a0, t0 +and ra, a0, a0 +and ra, a0, a5 +and ra, a0, s4 +and ra, a0, s9 +and ra, a0, t6 +and ra, a5, zero +and ra, a5, ra +and ra, a5, t0 +and ra, a5, a0 +and ra, a5, a5 +and ra, a5, s4 +and ra, a5, s9 +and ra, a5, t6 +and ra, s4, zero +and ra, s4, ra +and ra, s4, t0 +and ra, s4, a0 +and ra, s4, a5 +and ra, s4, s4 +and ra, s4, s9 +and ra, s4, t6 +and ra, s9, zero +and ra, s9, ra +and ra, s9, t0 +and ra, s9, a0 +and ra, s9, a5 +and ra, s9, s4 +and ra, s9, s9 +and ra, s9, t6 +and ra, t6, zero +and ra, t6, ra +and ra, t6, t0 +and ra, t6, a0 +and ra, t6, a5 +and ra, t6, s4 +and ra, t6, s9 +and ra, t6, t6 +and t0, zero, zero +and t0, zero, ra +and t0, zero, t0 +and t0, zero, a0 +and t0, zero, a5 +and t0, zero, s4 +and t0, zero, s9 +and t0, zero, t6 +and t0, ra, zero +and t0, ra, ra +and t0, ra, t0 +and t0, ra, a0 +and t0, ra, a5 +and t0, ra, s4 +and t0, ra, s9 +and t0, ra, t6 +and t0, t0, zero +and t0, t0, ra +and t0, t0, t0 +and t0, t0, a0 +and t0, t0, a5 +and t0, t0, s4 +and t0, t0, s9 +and t0, t0, t6 +and t0, a0, zero +and t0, a0, ra +and t0, a0, t0 +and t0, a0, a0 +and t0, a0, a5 +and t0, a0, s4 +and t0, a0, s9 +and t0, a0, t6 +and t0, a5, zero +and t0, a5, ra +and t0, a5, t0 +and t0, a5, a0 +and t0, a5, a5 +and t0, a5, s4 +and t0, a5, s9 +and t0, a5, t6 +and t0, s4, zero +and t0, s4, ra +and t0, s4, t0 +and t0, s4, a0 +and t0, s4, a5 +and t0, s4, s4 +and t0, s4, s9 +and t0, s4, t6 +and t0, s9, zero +and t0, s9, ra +and t0, s9, t0 +and t0, s9, a0 +and t0, s9, a5 +and t0, s9, s4 +and t0, s9, s9 +and t0, s9, t6 +and t0, t6, zero +and t0, t6, ra +and t0, t6, t0 +and t0, t6, a0 +and t0, t6, a5 +and t0, t6, s4 +and t0, t6, s9 +and t0, t6, t6 +and a0, zero, zero +and a0, zero, ra +and a0, zero, t0 +and a0, zero, a0 +and a0, zero, a5 +and a0, zero, s4 +and a0, zero, s9 +and a0, zero, t6 +and a0, ra, zero +and a0, ra, ra +and a0, ra, t0 +and a0, ra, a0 +and a0, ra, a5 +and a0, ra, s4 +and a0, ra, s9 +and a0, ra, t6 +and a0, t0, zero +and a0, t0, ra +and a0, t0, t0 +and a0, t0, a0 +and a0, t0, a5 +and a0, t0, s4 +and a0, t0, s9 +and a0, t0, t6 +and a0, a0, zero +and a0, a0, ra +and a0, a0, t0 +and a0, a0, a0 +and a0, a0, a5 +and a0, a0, s4 +and a0, a0, s9 +and a0, a0, t6 +and a0, a5, zero +and a0, a5, ra +and a0, a5, t0 +and a0, a5, a0 +and a0, a5, a5 +and a0, a5, s4 +and a0, a5, s9 +and a0, a5, t6 +and a0, s4, zero +and a0, s4, ra +and a0, s4, t0 +and a0, s4, a0 +and a0, s4, a5 +and a0, s4, s4 +and a0, s4, s9 +and a0, s4, t6 +and a0, s9, zero +and a0, s9, ra +and a0, s9, t0 +and a0, s9, a0 +and a0, s9, a5 +and a0, s9, s4 +and a0, s9, s9 +and a0, s9, t6 +and a0, t6, zero +and a0, t6, ra +and a0, t6, t0 +and a0, t6, a0 +and a0, t6, a5 +and a0, t6, s4 +and a0, t6, s9 +and a0, t6, t6 +and a5, zero, zero +and a5, zero, ra +and a5, zero, t0 +and a5, zero, a0 +and a5, zero, a5 +and a5, zero, s4 +and a5, zero, s9 +and a5, zero, t6 +and a5, ra, zero +and a5, ra, ra +and a5, ra, t0 +and a5, ra, a0 +and a5, ra, a5 +and a5, ra, s4 +and a5, ra, s9 +and a5, ra, t6 +and a5, t0, zero +and a5, t0, ra +and a5, t0, t0 +and a5, t0, a0 +and a5, t0, a5 +and a5, t0, s4 +and a5, t0, s9 +and a5, t0, t6 +and a5, a0, zero +and a5, a0, ra +and a5, a0, t0 +and a5, a0, a0 +and a5, a0, a5 +and a5, a0, s4 +and a5, a0, s9 +and a5, a0, t6 +and a5, a5, zero +and a5, a5, ra +and a5, a5, t0 +and a5, a5, a0 +and a5, a5, a5 +and a5, a5, s4 +and a5, a5, s9 +and a5, a5, t6 +and a5, s4, zero +and a5, s4, ra +and a5, s4, t0 +and a5, s4, a0 +and a5, s4, a5 +and a5, s4, s4 +and a5, s4, s9 +and a5, s4, t6 +and a5, s9, zero +and a5, s9, ra +and a5, s9, t0 +and a5, s9, a0 +and a5, s9, a5 +and a5, s9, s4 +and a5, s9, s9 +and a5, s9, t6 +and a5, t6, zero +and a5, t6, ra +and a5, t6, t0 +and a5, t6, a0 +and a5, t6, a5 +and a5, t6, s4 +and a5, t6, s9 +and a5, t6, t6 +and s4, zero, zero +and s4, zero, ra +and s4, zero, t0 +and s4, zero, a0 +and s4, zero, a5 +and s4, zero, s4 +and s4, zero, s9 +and s4, zero, t6 +and s4, ra, zero +and s4, ra, ra +and s4, ra, t0 +and s4, ra, a0 +and s4, ra, a5 +and s4, ra, s4 +and s4, ra, s9 +and s4, ra, t6 +and s4, t0, zero +and s4, t0, ra +and s4, t0, t0 +and s4, t0, a0 +and s4, t0, a5 +and s4, t0, s4 +and s4, t0, s9 +and s4, t0, t6 +and s4, a0, zero +and s4, a0, ra +and s4, a0, t0 +and s4, a0, a0 +and s4, a0, a5 +and s4, a0, s4 +and s4, a0, s9 +and s4, a0, t6 +and s4, a5, zero +and s4, a5, ra +and s4, a5, t0 +and s4, a5, a0 +and s4, a5, a5 +and s4, a5, s4 +and s4, a5, s9 +and s4, a5, t6 +and s4, s4, zero +and s4, s4, ra +and s4, s4, t0 +and s4, s4, a0 +and s4, s4, a5 +and s4, s4, s4 +and s4, s4, s9 +and s4, s4, t6 +and s4, s9, zero +and s4, s9, ra +and s4, s9, t0 +and s4, s9, a0 +and s4, s9, a5 +and s4, s9, s4 +and s4, s9, s9 +and s4, s9, t6 +and s4, t6, zero +and s4, t6, ra +and s4, t6, t0 +and s4, t6, a0 +and s4, t6, a5 +and s4, t6, s4 +and s4, t6, s9 +and s4, t6, t6 +and s9, zero, zero +and s9, zero, ra +and s9, zero, t0 +and s9, zero, a0 +and s9, zero, a5 +and s9, zero, s4 +and s9, zero, s9 +and s9, zero, t6 +and s9, ra, zero +and s9, ra, ra +and s9, ra, t0 +and s9, ra, a0 +and s9, ra, a5 +and s9, ra, s4 +and s9, ra, s9 +and s9, ra, t6 +and s9, t0, zero +and s9, t0, ra +and s9, t0, t0 +and s9, t0, a0 +and s9, t0, a5 +and s9, t0, s4 +and s9, t0, s9 +and s9, t0, t6 +and s9, a0, zero +and s9, a0, ra +and s9, a0, t0 +and s9, a0, a0 +and s9, a0, a5 +and s9, a0, s4 +and s9, a0, s9 +and s9, a0, t6 +and s9, a5, zero +and s9, a5, ra +and s9, a5, t0 +and s9, a5, a0 +and s9, a5, a5 +and s9, a5, s4 +and s9, a5, s9 +and s9, a5, t6 +and s9, s4, zero +and s9, s4, ra +and s9, s4, t0 +and s9, s4, a0 +and s9, s4, a5 +and s9, s4, s4 +and s9, s4, s9 +and s9, s4, t6 +and s9, s9, zero +and s9, s9, ra +and s9, s9, t0 +and s9, s9, a0 +and s9, s9, a5 +and s9, s9, s4 +and s9, s9, s9 +and s9, s9, t6 +and s9, t6, zero +and s9, t6, ra +and s9, t6, t0 +and s9, t6, a0 +and s9, t6, a5 +and s9, t6, s4 +and s9, t6, s9 +and s9, t6, t6 +and t6, zero, zero +and t6, zero, ra +and t6, zero, t0 +and t6, zero, a0 +and t6, zero, a5 +and t6, zero, s4 +and t6, zero, s9 +and t6, zero, t6 +and t6, ra, zero +and t6, ra, ra +and t6, ra, t0 +and t6, ra, a0 +and t6, ra, a5 +and t6, ra, s4 +and t6, ra, s9 +and t6, ra, t6 +and t6, t0, zero +and t6, t0, ra +and t6, t0, t0 +and t6, t0, a0 +and t6, t0, a5 +and t6, t0, s4 +and t6, t0, s9 +and t6, t0, t6 +and t6, a0, zero +and t6, a0, ra +and t6, a0, t0 +and t6, a0, a0 +and t6, a0, a5 +and t6, a0, s4 +and t6, a0, s9 +and t6, a0, t6 +and t6, a5, zero +and t6, a5, ra +and t6, a5, t0 +and t6, a5, a0 +and t6, a5, a5 +and t6, a5, s4 +and t6, a5, s9 +and t6, a5, t6 +and t6, s4, zero +and t6, s4, ra +and t6, s4, t0 +and t6, s4, a0 +and t6, s4, a5 +and t6, s4, s4 +and t6, s4, s9 +and t6, s4, t6 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+andi zero, zero, #8 +andi zero, zero, #0x10 +andi zero, zero, #0x20 +andi zero, zero, #0x40 +andi zero, zero, #0x80 +andi zero, zero, #0x100 +andi zero, zero, #0x200 +andi zero, zero, #0x400 +andi zero, zero, #0x7ff +andi zero, ra, #0xfffff801 +andi zero, ra, #0xfffffc00 +andi zero, ra, #0xfffffe00 +andi zero, ra, #0xffffff00 +andi zero, ra, #0xffffff80 +andi zero, ra, #0xffffffc0 +andi zero, ra, #0xffffffe0 +andi zero, ra, #0xfffffff0 +andi zero, ra, #0xfffffff8 +andi zero, ra, #0xfffffffc +andi zero, ra, #0xfffffffe +andi zero, ra, #0xffffffff +andi zero, ra, #0 +andi zero, ra, #1 +andi zero, ra, #2 +andi zero, ra, #4 +andi zero, ra, #8 +andi zero, ra, #0x10 +andi zero, ra, #0x20 +andi zero, ra, #0x40 +andi zero, ra, #0x80 +andi zero, ra, #0x100 +andi zero, ra, #0x200 +andi zero, ra, #0x400 +andi zero, ra, #0x7ff +andi zero, t0, #0xfffff801 +andi zero, t0, #0xfffffc00 +andi zero, t0, #0xfffffe00 +andi zero, t0, #0xffffff00 +andi zero, t0, #0xffffff80 +andi zero, t0, #0xffffffc0 +andi zero, t0, #0xffffffe0 +andi zero, t0, #0xfffffff0 +andi zero, t0, #0xfffffff8 +andi zero, t0, #0xfffffffc +andi zero, t0, #0xfffffffe +andi zero, t0, #0xffffffff +andi zero, t0, #0 +andi zero, t0, #1 +andi zero, t0, #2 +andi zero, t0, #4 +andi zero, t0, #8 +andi zero, t0, #0x10 +andi zero, t0, #0x20 +andi zero, t0, #0x40 +andi zero, t0, #0x80 +andi zero, t0, #0x100 +andi zero, t0, #0x200 +andi zero, t0, #0x400 +andi zero, t0, #0x7ff +andi zero, a0, #0xfffff801 +andi zero, a0, #0xfffffc00 +andi zero, a0, #0xfffffe00 +andi zero, a0, #0xffffff00 +andi zero, a0, #0xffffff80 +andi zero, a0, #0xffffffc0 +andi zero, a0, #0xffffffe0 +andi zero, a0, #0xfffffff0 +andi zero, a0, #0xfffffff8 +andi zero, a0, #0xfffffffc +andi zero, a0, #0xfffffffe +andi zero, a0, #0xffffffff +andi zero, a0, #0 +andi zero, a0, #1 +andi zero, a0, #2 +andi zero, a0, #4 +andi zero, a0, #8 +andi zero, a0, #0x10 +andi zero, a0, #0x20 +andi zero, a0, #0x40 +andi zero, a0, #0x80 +andi zero, a0, #0x100 +andi zero, a0, #0x200 +andi zero, a0, #0x400 +andi zero, a0, #0x7ff +andi zero, a5, #0xfffff801 +andi zero, a5, #0xfffffc00 +andi zero, a5, #0xfffffe00 +andi zero, a5, #0xffffff00 +andi zero, a5, #0xffffff80 +andi zero, a5, #0xffffffc0 +andi zero, a5, #0xffffffe0 +andi zero, a5, #0xfffffff0 +andi zero, a5, #0xfffffff8 +andi zero, a5, #0xfffffffc +andi zero, a5, #0xfffffffe +andi zero, a5, #0xffffffff +andi zero, a5, #0 +andi zero, a5, #1 +andi zero, a5, #2 +andi zero, a5, #4 +andi zero, a5, #8 +andi zero, a5, #0x10 +andi zero, a5, #0x20 +andi zero, a5, #0x40 +andi zero, a5, #0x80 +andi zero, a5, #0x100 +andi zero, a5, #0x200 +andi zero, a5, #0x400 +andi zero, a5, #0x7ff +andi zero, s4, #0xfffff801 +andi zero, s4, #0xfffffc00 +andi zero, s4, #0xfffffe00 +andi zero, s4, #0xffffff00 +andi zero, s4, #0xffffff80 +andi zero, s4, #0xffffffc0 +andi zero, s4, #0xffffffe0 +andi zero, s4, #0xfffffff0 +andi zero, s4, #0xfffffff8 +andi zero, s4, #0xfffffffc +andi zero, s4, #0xfffffffe +andi zero, s4, #0xffffffff +andi zero, s4, #0 +andi zero, s4, #1 +andi zero, s4, #2 +andi zero, s4, #4 +andi zero, s4, #8 +andi zero, s4, #0x10 +andi zero, s4, #0x20 +andi zero, s4, #0x40 +andi zero, s4, #0x80 +andi zero, s4, #0x100 +andi zero, s4, #0x200 +andi zero, s4, #0x400 +andi zero, s4, #0x7ff +andi zero, s9, #0xfffff801 +andi zero, s9, #0xfffffc00 +andi zero, s9, #0xfffffe00 +andi zero, s9, #0xffffff00 +andi zero, s9, #0xffffff80 +andi zero, s9, #0xffffffc0 +andi zero, s9, #0xffffffe0 +andi zero, s9, #0xfffffff0 +andi zero, s9, #0xfffffff8 +andi zero, s9, #0xfffffffc +andi zero, s9, #0xfffffffe +andi zero, s9, #0xffffffff +andi zero, s9, #0 +andi zero, s9, #1 +andi zero, s9, #2 +andi zero, s9, #4 +andi zero, s9, #8 +andi zero, s9, #0x10 +andi zero, s9, #0x20 +andi zero, s9, #0x40 +andi zero, s9, #0x80 +andi zero, s9, #0x100 +andi zero, s9, #0x200 +andi zero, s9, #0x400 +andi zero, s9, #0x7ff +andi zero, t6, #0xfffff801 +andi zero, t6, #0xfffffc00 +andi zero, t6, #0xfffffe00 +andi zero, t6, #0xffffff00 +andi zero, t6, #0xffffff80 +andi zero, t6, #0xffffffc0 +andi zero, t6, #0xffffffe0 +andi zero, t6, #0xfffffff0 +andi zero, t6, #0xfffffff8 +andi zero, t6, #0xfffffffc +andi zero, t6, #0xfffffffe +andi zero, t6, #0xffffffff +andi zero, t6, #0 +andi zero, t6, #1 +andi zero, t6, #2 +andi zero, t6, #4 +andi zero, t6, #8 +andi zero, t6, #0x10 +andi zero, t6, #0x20 +andi zero, t6, #0x40 +andi zero, t6, #0x80 +andi zero, t6, #0x100 +andi zero, t6, #0x200 +andi zero, t6, #0x400 +andi zero, t6, #0x7ff +andi ra, zero, #0xfffff801 +andi ra, zero, #0xfffffc00 +andi ra, zero, #0xfffffe00 +andi ra, zero, #0xffffff00 +andi ra, zero, #0xffffff80 +andi ra, zero, #0xffffffc0 +andi ra, zero, #0xffffffe0 +andi ra, zero, #0xfffffff0 +andi ra, zero, #0xfffffff8 +andi ra, zero, #0xfffffffc +andi ra, zero, #0xfffffffe +andi ra, zero, #0xffffffff +andi ra, zero, #0 +andi ra, zero, #1 +andi ra, zero, #2 +andi ra, zero, #4 +andi ra, zero, #8 +andi ra, zero, #0x10 +andi ra, zero, #0x20 +andi ra, zero, #0x40 +andi ra, zero, #0x80 +andi ra, zero, #0x100 +andi ra, zero, #0x200 +andi ra, zero, #0x400 +andi ra, zero, #0x7ff +andi ra, ra, #0xfffff801 +andi ra, ra, #0xfffffc00 +andi ra, ra, #0xfffffe00 +andi ra, ra, #0xffffff00 +andi ra, ra, #0xffffff80 +andi ra, ra, #0xffffffc0 +andi ra, ra, #0xffffffe0 +andi ra, ra, #0xfffffff0 +andi ra, ra, #0xfffffff8 +andi ra, ra, #0xfffffffc +andi ra, ra, #0xfffffffe +andi ra, ra, #0xffffffff +andi ra, ra, #0 +andi ra, ra, #1 +andi ra, ra, #2 +andi ra, ra, #4 +andi ra, ra, #8 +andi ra, ra, #0x10 +andi ra, ra, #0x20 +andi ra, ra, #0x40 +andi ra, ra, #0x80 +andi ra, ra, #0x100 +andi ra, ra, #0x200 +andi ra, ra, #0x400 +andi ra, ra, #0x7ff +andi ra, t0, #0xfffff801 +andi ra, t0, #0xfffffc00 +andi ra, t0, #0xfffffe00 +andi ra, t0, #0xffffff00 +andi ra, t0, #0xffffff80 +andi ra, t0, #0xffffffc0 +andi ra, t0, #0xffffffe0 +andi ra, t0, #0xfffffff0 +andi ra, t0, #0xfffffff8 +andi ra, t0, #0xfffffffc +andi ra, t0, #0xfffffffe +andi ra, t0, #0xffffffff +andi ra, t0, #0 +andi ra, t0, #1 +andi ra, t0, #2 +andi ra, t0, #4 +andi ra, t0, #8 +andi ra, t0, #0x10 +andi ra, t0, #0x20 +andi ra, t0, #0x40 +andi ra, t0, #0x80 +andi ra, t0, #0x100 +andi ra, t0, #0x200 +andi ra, t0, #0x400 +andi ra, t0, #0x7ff +andi ra, a0, #0xfffff801 +andi ra, a0, #0xfffffc00 +andi ra, a0, #0xfffffe00 +andi ra, a0, #0xffffff00 +andi ra, a0, #0xffffff80 +andi ra, a0, #0xffffffc0 +andi ra, a0, #0xffffffe0 +andi ra, a0, #0xfffffff0 +andi ra, a0, #0xfffffff8 +andi ra, a0, #0xfffffffc +andi ra, a0, #0xfffffffe +andi ra, a0, #0xffffffff +andi ra, a0, #0 +andi ra, a0, #1 +andi ra, a0, #2 +andi ra, a0, #4 +andi ra, a0, #8 +andi ra, a0, #0x10 +andi ra, a0, #0x20 +andi ra, a0, #0x40 +andi ra, a0, #0x80 +andi ra, a0, #0x100 +andi ra, a0, #0x200 +andi ra, a0, #0x400 +andi ra, a0, #0x7ff +andi ra, a5, #0xfffff801 +andi ra, a5, #0xfffffc00 +andi ra, a5, #0xfffffe00 +andi ra, a5, #0xffffff00 +andi ra, a5, #0xffffff80 +andi ra, a5, #0xffffffc0 +andi ra, a5, #0xffffffe0 +andi ra, a5, #0xfffffff0 +andi ra, a5, #0xfffffff8 +andi ra, a5, #0xfffffffc +andi ra, a5, #0xfffffffe +andi ra, a5, #0xffffffff +andi ra, a5, #0 +andi ra, a5, #1 +andi ra, a5, #2 +andi ra, a5, #4 +andi ra, a5, #8 +andi ra, a5, #0x10 +andi ra, a5, #0x20 +andi ra, a5, #0x40 +andi ra, a5, #0x80 +andi ra, a5, #0x100 +andi ra, a5, #0x200 +andi ra, a5, #0x400 +andi ra, a5, #0x7ff +andi ra, s4, #0xfffff801 +andi ra, s4, #0xfffffc00 +andi ra, s4, #0xfffffe00 +andi ra, s4, #0xffffff00 +andi ra, s4, #0xffffff80 +andi ra, s4, #0xffffffc0 +andi ra, s4, #0xffffffe0 +andi ra, s4, #0xfffffff0 +andi ra, s4, #0xfffffff8 +andi ra, s4, #0xfffffffc +andi ra, s4, #0xfffffffe +andi ra, s4, #0xffffffff +andi ra, s4, #0 +andi ra, s4, #1 +andi ra, s4, #2 +andi ra, s4, #4 +andi ra, s4, #8 +andi ra, s4, #0x10 +andi ra, s4, #0x20 +andi ra, s4, #0x40 +andi ra, s4, #0x80 +andi ra, s4, #0x100 +andi ra, s4, #0x200 +andi ra, s4, #0x400 +andi ra, s4, #0x7ff +andi ra, s9, #0xfffff801 +andi ra, s9, #0xfffffc00 +andi ra, s9, #0xfffffe00 +andi ra, s9, #0xffffff00 +andi ra, s9, #0xffffff80 +andi ra, s9, #0xffffffc0 +andi ra, s9, #0xffffffe0 +andi ra, s9, #0xfffffff0 +andi ra, s9, #0xfffffff8 +andi ra, s9, #0xfffffffc +andi ra, s9, #0xfffffffe +andi ra, s9, #0xffffffff +andi ra, s9, #0 +andi ra, s9, #1 +andi ra, s9, #2 +andi ra, s9, #4 +andi ra, s9, #8 +andi ra, s9, #0x10 +andi ra, s9, #0x20 +andi ra, s9, #0x40 +andi ra, s9, #0x80 +andi ra, s9, #0x100 +andi ra, s9, #0x200 +andi ra, s9, #0x400 +andi ra, s9, #0x7ff +andi ra, t6, #0xfffff801 +andi ra, t6, #0xfffffc00 +andi ra, t6, #0xfffffe00 +andi ra, t6, #0xffffff00 +andi ra, t6, #0xffffff80 +andi ra, t6, #0xffffffc0 +andi ra, t6, #0xffffffe0 +andi ra, t6, #0xfffffff0 +andi ra, t6, #0xfffffff8 +andi ra, t6, #0xfffffffc +andi ra, t6, #0xfffffffe +andi ra, t6, #0xffffffff +andi ra, t6, #0 +andi ra, t6, #1 +andi ra, t6, #2 +andi ra, t6, #4 +andi ra, t6, #8 +andi ra, t6, #0x10 +andi ra, t6, #0x20 +andi ra, t6, #0x40 +andi ra, t6, #0x80 +andi ra, t6, #0x100 +andi ra, t6, #0x200 +andi ra, t6, #0x400 +andi ra, t6, #0x7ff +andi t0, zero, #0xfffff801 +andi t0, zero, #0xfffffc00 +andi t0, zero, #0xfffffe00 +andi t0, zero, #0xffffff00 +andi t0, zero, #0xffffff80 +andi t0, zero, #0xffffffc0 +andi t0, zero, #0xffffffe0 +andi t0, zero, #0xfffffff0 +andi t0, zero, #0xfffffff8 +andi t0, zero, #0xfffffffc +andi t0, zero, #0xfffffffe +andi t0, zero, #0xffffffff +andi t0, zero, #0 +andi t0, zero, #1 +andi t0, zero, #2 +andi t0, zero, #4 +andi t0, zero, #8 +andi t0, zero, #0x10 +andi t0, zero, #0x20 +andi t0, zero, #0x40 +andi t0, zero, #0x80 +andi t0, zero, #0x100 +andi t0, zero, #0x200 +andi t0, zero, #0x400 +andi t0, zero, #0x7ff +andi t0, ra, #0xfffff801 +andi t0, ra, #0xfffffc00 +andi t0, ra, #0xfffffe00 +andi t0, ra, #0xffffff00 +andi t0, ra, #0xffffff80 +andi t0, ra, #0xffffffc0 +andi t0, ra, #0xffffffe0 +andi t0, ra, #0xfffffff0 +andi t0, ra, #0xfffffff8 +andi t0, ra, #0xfffffffc +andi t0, ra, #0xfffffffe +andi t0, ra, #0xffffffff +andi t0, ra, #0 +andi t0, ra, #1 +andi t0, ra, #2 +andi t0, ra, #4 +andi t0, ra, #8 +andi t0, ra, #0x10 +andi t0, ra, #0x20 +andi t0, ra, #0x40 +andi t0, ra, #0x80 +andi t0, ra, #0x100 +andi t0, ra, #0x200 +andi t0, ra, #0x400 +andi t0, ra, #0x7ff +andi t0, t0, #0xfffff801 +andi t0, t0, #0xfffffc00 +andi t0, t0, #0xfffffe00 +andi t0, t0, #0xffffff00 +andi t0, t0, #0xffffff80 +andi t0, t0, #0xffffffc0 +andi t0, t0, #0xffffffe0 +andi t0, t0, #0xfffffff0 +andi t0, t0, #0xfffffff8 +andi t0, t0, #0xfffffffc +andi t0, t0, #0xfffffffe +andi t0, t0, #0xffffffff +andi t0, t0, #0 +andi t0, t0, #1 +andi t0, t0, #2 +andi t0, t0, #4 +andi t0, t0, #8 +andi t0, t0, #0x10 +andi t0, t0, #0x20 +andi t0, t0, #0x40 +andi t0, t0, #0x80 +andi t0, t0, #0x100 +andi t0, t0, #0x200 +andi t0, t0, #0x400 +andi t0, t0, #0x7ff +andi t0, a0, #0xfffff801 +andi t0, a0, #0xfffffc00 +andi t0, a0, #0xfffffe00 +andi t0, a0, #0xffffff00 +andi t0, a0, #0xffffff80 +andi t0, a0, #0xffffffc0 +andi t0, a0, #0xffffffe0 +andi t0, a0, #0xfffffff0 +andi t0, a0, #0xfffffff8 +andi t0, a0, #0xfffffffc +andi t0, a0, #0xfffffffe +andi t0, a0, #0xffffffff +andi t0, a0, #0 +andi t0, a0, #1 +andi t0, a0, #2 +andi t0, a0, #4 +andi t0, a0, #8 +andi t0, a0, #0x10 +andi t0, a0, #0x20 +andi t0, a0, #0x40 +andi t0, a0, #0x80 +andi t0, a0, #0x100 +andi t0, a0, #0x200 +andi t0, a0, #0x400 +andi t0, a0, #0x7ff +andi t0, a5, #0xfffff801 +andi t0, a5, #0xfffffc00 +andi t0, a5, #0xfffffe00 +andi t0, a5, #0xffffff00 +andi t0, a5, #0xffffff80 +andi t0, a5, #0xffffffc0 +andi t0, a5, #0xffffffe0 +andi t0, a5, #0xfffffff0 +andi t0, a5, #0xfffffff8 +andi t0, a5, #0xfffffffc +andi t0, a5, #0xfffffffe +andi t0, a5, #0xffffffff +andi t0, a5, #0 +andi t0, a5, #1 +andi t0, a5, #2 +andi t0, a5, #4 +andi t0, a5, #8 +andi t0, a5, #0x10 +andi t0, a5, #0x20 +andi t0, a5, #0x40 +andi t0, a5, #0x80 +andi t0, a5, #0x100 +andi t0, a5, #0x200 +andi t0, a5, #0x400 +andi t0, a5, #0x7ff +andi t0, s4, #0xfffff801 +andi t0, s4, #0xfffffc00 +andi t0, s4, #0xfffffe00 +andi t0, s4, #0xffffff00 +andi t0, s4, #0xffffff80 +andi t0, s4, #0xffffffc0 +andi t0, s4, #0xffffffe0 +andi t0, s4, #0xfffffff0 +andi t0, s4, #0xfffffff8 +andi t0, s4, #0xfffffffc +andi t0, s4, #0xfffffffe +andi t0, s4, #0xffffffff +andi t0, s4, #0 +andi t0, s4, #1 +andi t0, s4, #2 +andi t0, s4, #4 +andi t0, s4, #8 +andi t0, s4, #0x10 +andi t0, s4, #0x20 +andi t0, s4, #0x40 +andi t0, s4, #0x80 +andi t0, s4, #0x100 +andi t0, s4, #0x200 +andi t0, s4, #0x400 +andi t0, s4, #0x7ff +andi t0, s9, #0xfffff801 +andi t0, s9, #0xfffffc00 +andi t0, s9, #0xfffffe00 +andi t0, s9, #0xffffff00 +andi t0, s9, #0xffffff80 +andi t0, s9, #0xffffffc0 +andi t0, s9, #0xffffffe0 +andi t0, s9, #0xfffffff0 +andi t0, s9, #0xfffffff8 +andi t0, s9, #0xfffffffc +andi t0, s9, #0xfffffffe +andi t0, s9, #0xffffffff +andi t0, s9, #0 +andi t0, s9, #1 +andi t0, s9, #2 +andi t0, s9, #4 +andi t0, s9, #8 +andi t0, s9, #0x10 +andi t0, s9, #0x20 +andi t0, s9, #0x40 +andi t0, s9, #0x80 +andi t0, s9, #0x100 +andi t0, s9, #0x200 +andi t0, s9, #0x400 +andi t0, s9, #0x7ff +andi t0, t6, #0xfffff801 +andi t0, t6, #0xfffffc00 +andi t0, t6, #0xfffffe00 +andi t0, t6, #0xffffff00 +andi t0, t6, #0xffffff80 +andi t0, t6, #0xffffffc0 +andi t0, t6, #0xffffffe0 +andi t0, t6, #0xfffffff0 +andi t0, t6, #0xfffffff8 +andi t0, t6, #0xfffffffc +andi t0, t6, #0xfffffffe +andi t0, t6, #0xffffffff +andi t0, t6, #0 +andi t0, t6, #1 +andi t0, t6, #2 +andi t0, t6, #4 +andi t0, t6, #8 +andi t0, t6, #0x10 +andi t0, t6, #0x20 +andi t0, t6, #0x40 +andi t0, t6, #0x80 +andi t0, t6, #0x100 +andi t0, t6, #0x200 +andi t0, t6, #0x400 +andi t0, t6, #0x7ff +andi a0, zero, #0xfffff801 +andi a0, zero, #0xfffffc00 +andi a0, zero, #0xfffffe00 +andi a0, zero, #0xffffff00 +andi a0, zero, #0xffffff80 +andi a0, zero, #0xffffffc0 +andi a0, zero, #0xffffffe0 +andi a0, zero, #0xfffffff0 +andi a0, zero, #0xfffffff8 +andi a0, zero, #0xfffffffc +andi a0, zero, #0xfffffffe +andi a0, zero, #0xffffffff +andi a0, zero, #0 +andi a0, zero, #1 +andi a0, zero, #2 +andi a0, zero, #4 +andi a0, zero, #8 +andi a0, zero, #0x10 +andi a0, zero, #0x20 +andi a0, zero, #0x40 +andi a0, zero, #0x80 +andi a0, zero, #0x100 +andi a0, zero, #0x200 +andi a0, zero, #0x400 +andi a0, zero, #0x7ff +andi a0, ra, #0xfffff801 +andi a0, ra, #0xfffffc00 +andi a0, ra, #0xfffffe00 +andi a0, ra, #0xffffff00 +andi a0, ra, #0xffffff80 +andi a0, ra, #0xffffffc0 +andi a0, ra, #0xffffffe0 +andi a0, ra, #0xfffffff0 +andi a0, ra, #0xfffffff8 +andi a0, ra, #0xfffffffc +andi a0, ra, #0xfffffffe +andi a0, ra, #0xffffffff +andi a0, ra, #0 +andi a0, ra, #1 +andi a0, ra, #2 +andi a0, ra, #4 +andi a0, ra, #8 +andi a0, ra, #0x10 +andi a0, ra, #0x20 +andi a0, ra, #0x40 +andi a0, ra, #0x80 +andi a0, ra, #0x100 +andi a0, ra, #0x200 +andi a0, ra, #0x400 +andi a0, ra, #0x7ff +andi a0, t0, #0xfffff801 +andi a0, t0, #0xfffffc00 +andi a0, t0, #0xfffffe00 +andi a0, t0, #0xffffff00 +andi a0, t0, #0xffffff80 +andi a0, t0, #0xffffffc0 +andi a0, t0, #0xffffffe0 +andi a0, t0, #0xfffffff0 +andi a0, t0, #0xfffffff8 +andi a0, t0, #0xfffffffc +andi a0, t0, #0xfffffffe +andi a0, t0, #0xffffffff +andi a0, t0, #0 +andi a0, t0, #1 +andi a0, t0, #2 +andi a0, t0, #4 +andi a0, t0, #8 +andi a0, t0, #0x10 +andi a0, t0, #0x20 +andi a0, t0, #0x40 +andi a0, t0, #0x80 +andi a0, t0, #0x100 +andi a0, t0, #0x200 +andi a0, t0, #0x400 +andi a0, t0, #0x7ff +andi a0, a0, #0xfffff801 +andi a0, a0, #0xfffffc00 +andi a0, a0, #0xfffffe00 +andi a0, a0, #0xffffff00 +andi a0, a0, #0xffffff80 +andi a0, a0, #0xffffffc0 +andi a0, a0, #0xffffffe0 +andi a0, a0, #0xfffffff0 +andi a0, a0, #0xfffffff8 +andi a0, a0, #0xfffffffc +andi a0, a0, #0xfffffffe +andi a0, a0, #0xffffffff +andi a0, a0, #0 +andi a0, a0, #1 +andi a0, a0, #2 +andi a0, a0, #4 +andi a0, a0, #8 +andi a0, a0, #0x10 +andi a0, a0, #0x20 +andi a0, a0, #0x40 +andi a0, a0, #0x80 +andi a0, a0, #0x100 +andi a0, a0, #0x200 +andi a0, a0, #0x400 +andi a0, a0, #0x7ff +andi a0, a5, #0xfffff801 +andi a0, a5, #0xfffffc00 +andi a0, a5, #0xfffffe00 +andi a0, a5, #0xffffff00 +andi a0, a5, #0xffffff80 +andi a0, a5, #0xffffffc0 +andi a0, a5, #0xffffffe0 +andi a0, a5, #0xfffffff0 +andi a0, a5, #0xfffffff8 +andi a0, a5, #0xfffffffc +andi a0, a5, #0xfffffffe +andi a0, a5, #0xffffffff +andi a0, a5, #0 +andi a0, a5, #1 +andi a0, a5, #2 +andi a0, a5, #4 +andi a0, a5, #8 +andi a0, a5, #0x10 +andi a0, a5, #0x20 +andi a0, a5, #0x40 +andi a0, a5, #0x80 +andi a0, a5, #0x100 +andi a0, a5, #0x200 +andi a0, a5, #0x400 +andi a0, a5, #0x7ff +andi a0, s4, #0xfffff801 +andi a0, s4, #0xfffffc00 +andi a0, s4, #0xfffffe00 +andi a0, s4, #0xffffff00 +andi a0, s4, #0xffffff80 +andi a0, s4, #0xffffffc0 +andi a0, s4, #0xffffffe0 +andi a0, s4, #0xfffffff0 +andi a0, s4, #0xfffffff8 +andi a0, s4, #0xfffffffc +andi a0, s4, #0xfffffffe +andi a0, s4, #0xffffffff +andi a0, s4, #0 +andi a0, s4, #1 +andi a0, s4, #2 +andi a0, s4, #4 +andi a0, s4, #8 +andi a0, s4, #0x10 +andi a0, s4, #0x20 +andi a0, s4, #0x40 +andi a0, s4, #0x80 +andi a0, s4, #0x100 +andi a0, s4, #0x200 +andi a0, s4, #0x400 +andi a0, s4, #0x7ff +andi a0, s9, #0xfffff801 +andi a0, s9, #0xfffffc00 +andi a0, s9, #0xfffffe00 +andi a0, s9, #0xffffff00 +andi a0, s9, #0xffffff80 +andi a0, s9, #0xffffffc0 +andi a0, s9, #0xffffffe0 +andi a0, s9, #0xfffffff0 +andi a0, s9, #0xfffffff8 +andi a0, s9, #0xfffffffc +andi a0, s9, #0xfffffffe +andi a0, s9, #0xffffffff +andi a0, s9, #0 +andi a0, s9, #1 +andi a0, s9, #2 +andi a0, s9, #4 +andi a0, s9, #8 +andi a0, s9, #0x10 +andi a0, s9, #0x20 +andi a0, s9, #0x40 +andi a0, s9, #0x80 +andi a0, s9, #0x100 +andi a0, s9, #0x200 +andi a0, s9, #0x400 +andi a0, s9, #0x7ff +andi a0, t6, #0xfffff801 +andi a0, t6, #0xfffffc00 +andi a0, t6, #0xfffffe00 +andi a0, t6, #0xffffff00 +andi a0, t6, #0xffffff80 +andi a0, t6, #0xffffffc0 +andi a0, t6, #0xffffffe0 +andi a0, t6, #0xfffffff0 +andi a0, t6, #0xfffffff8 +andi a0, t6, #0xfffffffc +andi a0, t6, #0xfffffffe +andi a0, t6, #0xffffffff +andi a0, t6, #0 +andi a0, t6, #1 +andi a0, t6, #2 +andi a0, t6, #4 +andi a0, t6, #8 +andi a0, t6, #0x10 +andi a0, t6, #0x20 +andi a0, t6, #0x40 +andi a0, t6, #0x80 +andi a0, t6, #0x100 +andi a0, t6, #0x200 +andi a0, t6, #0x400 +andi a0, t6, #0x7ff +andi a5, zero, #0xfffff801 +andi a5, zero, #0xfffffc00 +andi a5, zero, #0xfffffe00 +andi a5, zero, #0xffffff00 +andi a5, zero, #0xffffff80 +andi a5, zero, #0xffffffc0 +andi a5, zero, #0xffffffe0 +andi a5, zero, #0xfffffff0 +andi a5, zero, #0xfffffff8 +andi a5, zero, #0xfffffffc +andi a5, zero, #0xfffffffe +andi a5, zero, #0xffffffff +andi a5, zero, #0 +andi a5, zero, #1 +andi a5, zero, #2 +andi a5, zero, #4 +andi a5, zero, #8 +andi a5, zero, #0x10 +andi a5, zero, #0x20 +andi a5, zero, #0x40 +andi a5, zero, #0x80 +andi a5, zero, #0x100 +andi a5, zero, #0x200 +andi a5, zero, #0x400 +andi a5, zero, #0x7ff +andi a5, ra, #0xfffff801 +andi a5, ra, #0xfffffc00 +andi a5, ra, #0xfffffe00 +andi a5, ra, #0xffffff00 +andi a5, ra, #0xffffff80 +andi a5, ra, #0xffffffc0 +andi a5, ra, #0xffffffe0 +andi a5, ra, #0xfffffff0 +andi a5, ra, #0xfffffff8 +andi a5, ra, #0xfffffffc +andi a5, ra, #0xfffffffe +andi a5, ra, #0xffffffff +andi a5, ra, #0 +andi a5, ra, #1 +andi a5, ra, #2 +andi a5, ra, #4 +andi a5, ra, #8 +andi a5, ra, #0x10 +andi a5, ra, #0x20 +andi a5, ra, #0x40 +andi a5, ra, #0x80 +andi a5, ra, #0x100 +andi a5, ra, #0x200 +andi a5, ra, #0x400 +andi a5, ra, #0x7ff +andi a5, t0, #0xfffff801 +andi a5, t0, #0xfffffc00 +andi a5, t0, #0xfffffe00 +andi a5, t0, #0xffffff00 +andi a5, t0, #0xffffff80 +andi a5, t0, #0xffffffc0 +andi a5, t0, #0xffffffe0 +andi a5, t0, #0xfffffff0 +andi a5, t0, #0xfffffff8 +andi a5, t0, #0xfffffffc +andi a5, t0, #0xfffffffe +andi a5, t0, #0xffffffff +andi a5, t0, #0 +andi a5, t0, #1 +andi a5, t0, #2 +andi a5, t0, #4 +andi a5, t0, #8 +andi a5, t0, #0x10 +andi a5, t0, #0x20 +andi a5, t0, #0x40 +andi a5, t0, #0x80 +andi a5, t0, #0x100 +andi a5, t0, #0x200 +andi a5, t0, #0x400 +andi a5, t0, #0x7ff +andi a5, a0, #0xfffff801 +andi a5, a0, #0xfffffc00 +andi a5, a0, #0xfffffe00 +andi a5, a0, #0xffffff00 +andi a5, a0, #0xffffff80 +andi a5, a0, #0xffffffc0 +andi a5, a0, #0xffffffe0 +andi a5, a0, #0xfffffff0 +andi a5, a0, #0xfffffff8 +andi a5, a0, #0xfffffffc +andi a5, a0, #0xfffffffe +andi a5, a0, #0xffffffff +andi a5, a0, #0 +andi a5, a0, #1 +andi a5, a0, #2 +andi a5, a0, #4 +andi a5, a0, #8 +andi a5, a0, #0x10 +andi a5, a0, #0x20 +andi a5, a0, #0x40 +andi a5, a0, #0x80 +andi a5, a0, #0x100 +andi a5, a0, #0x200 +andi a5, a0, #0x400 +andi a5, a0, #0x7ff +andi a5, a5, #0xfffff801 +andi a5, a5, #0xfffffc00 +andi a5, a5, #0xfffffe00 +andi a5, a5, #0xffffff00 +andi a5, a5, #0xffffff80 +andi a5, a5, #0xffffffc0 +andi a5, a5, #0xffffffe0 +andi a5, a5, #0xfffffff0 +andi a5, a5, #0xfffffff8 +andi a5, a5, #0xfffffffc +andi a5, a5, #0xfffffffe +andi a5, a5, #0xffffffff +andi a5, a5, #0 +andi a5, a5, #1 +andi a5, a5, #2 +andi a5, a5, #4 +andi a5, a5, #8 +andi a5, a5, #0x10 +andi a5, a5, #0x20 +andi a5, a5, #0x40 +andi a5, a5, #0x80 +andi a5, a5, #0x100 +andi a5, a5, #0x200 +andi a5, a5, #0x400 +andi a5, a5, #0x7ff +andi a5, s4, #0xfffff801 +andi a5, s4, #0xfffffc00 +andi a5, s4, #0xfffffe00 +andi a5, s4, #0xffffff00 +andi a5, s4, #0xffffff80 +andi a5, s4, #0xffffffc0 +andi a5, s4, #0xffffffe0 +andi a5, s4, #0xfffffff0 +andi a5, s4, #0xfffffff8 +andi a5, s4, #0xfffffffc +andi a5, s4, #0xfffffffe +andi a5, s4, #0xffffffff +andi a5, s4, #0 +andi a5, s4, #1 +andi a5, s4, #2 +andi a5, s4, #4 +andi a5, s4, #8 +andi a5, s4, #0x10 +andi a5, s4, #0x20 +andi a5, s4, #0x40 +andi a5, s4, #0x80 +andi a5, s4, #0x100 +andi a5, s4, #0x200 +andi a5, s4, #0x400 +andi a5, s4, #0x7ff +andi a5, s9, #0xfffff801 +andi a5, s9, #0xfffffc00 +andi a5, s9, #0xfffffe00 +andi a5, s9, #0xffffff00 +andi a5, s9, #0xffffff80 +andi a5, s9, #0xffffffc0 +andi a5, s9, #0xffffffe0 +andi a5, s9, #0xfffffff0 +andi a5, s9, #0xfffffff8 +andi a5, s9, #0xfffffffc +andi a5, s9, #0xfffffffe +andi a5, s9, #0xffffffff +andi a5, s9, #0 +andi a5, s9, #1 +andi a5, s9, #2 +andi a5, s9, #4 +andi a5, s9, #8 +andi a5, s9, #0x10 +andi a5, s9, #0x20 +andi a5, s9, #0x40 +andi a5, s9, #0x80 +andi a5, s9, #0x100 +andi a5, s9, #0x200 +andi a5, s9, #0x400 +andi a5, s9, #0x7ff +andi a5, t6, #0xfffff801 +andi a5, t6, #0xfffffc00 +andi a5, t6, #0xfffffe00 +andi a5, t6, #0xffffff00 +andi a5, t6, #0xffffff80 +andi a5, t6, #0xffffffc0 +andi a5, t6, #0xffffffe0 +andi a5, t6, #0xfffffff0 +andi a5, t6, #0xfffffff8 +andi a5, t6, #0xfffffffc +andi a5, t6, #0xfffffffe +andi a5, t6, #0xffffffff +andi a5, t6, #0 +andi a5, t6, #1 +andi a5, t6, #2 +andi a5, t6, #4 +andi a5, t6, #8 +andi a5, t6, #0x10 +andi a5, t6, #0x20 +andi a5, t6, #0x40 +andi a5, t6, #0x80 +andi a5, t6, #0x100 +andi a5, t6, #0x200 +andi a5, t6, #0x400 +andi a5, t6, #0x7ff +andi s4, zero, #0xfffff801 +andi s4, zero, #0xfffffc00 +andi s4, zero, #0xfffffe00 +andi s4, zero, #0xffffff00 +andi s4, zero, #0xffffff80 +andi s4, zero, #0xffffffc0 +andi s4, zero, #0xffffffe0 +andi s4, zero, #0xfffffff0 +andi s4, zero, #0xfffffff8 +andi s4, zero, #0xfffffffc +andi s4, zero, #0xfffffffe +andi s4, zero, #0xffffffff +andi s4, zero, #0 +andi s4, zero, #1 +andi s4, zero, #2 +andi s4, zero, #4 +andi s4, zero, #8 +andi s4, zero, #0x10 +andi s4, zero, #0x20 +andi s4, zero, #0x40 +andi s4, zero, #0x80 +andi s4, zero, #0x100 +andi s4, zero, #0x200 +andi s4, zero, #0x400 +andi s4, zero, #0x7ff +andi s4, ra, #0xfffff801 +andi s4, ra, #0xfffffc00 +andi s4, ra, #0xfffffe00 +andi s4, ra, #0xffffff00 +andi s4, ra, #0xffffff80 +andi s4, ra, #0xffffffc0 +andi s4, ra, #0xffffffe0 +andi s4, ra, #0xfffffff0 +andi s4, ra, #0xfffffff8 +andi s4, ra, #0xfffffffc +andi s4, ra, #0xfffffffe +andi s4, ra, #0xffffffff +andi s4, ra, #0 +andi s4, ra, #1 +andi s4, ra, #2 +andi s4, ra, #4 +andi s4, ra, #8 +andi s4, ra, #0x10 +andi s4, ra, #0x20 +andi s4, ra, #0x40 +andi s4, ra, #0x80 +andi s4, ra, #0x100 +andi s4, ra, #0x200 +andi s4, ra, #0x400 +andi s4, ra, #0x7ff +andi s4, t0, #0xfffff801 +andi s4, t0, #0xfffffc00 +andi s4, t0, #0xfffffe00 +andi s4, t0, #0xffffff00 +andi s4, t0, #0xffffff80 +andi s4, t0, #0xffffffc0 +andi s4, t0, #0xffffffe0 +andi s4, t0, #0xfffffff0 +andi s4, t0, #0xfffffff8 +andi s4, t0, #0xfffffffc +andi s4, t0, #0xfffffffe +andi s4, t0, #0xffffffff +andi s4, t0, #0 +andi s4, t0, #1 +andi s4, t0, #2 +andi s4, t0, #4 +andi s4, t0, #8 +andi s4, t0, #0x10 +andi s4, t0, #0x20 +andi s4, t0, #0x40 +andi s4, t0, #0x80 +andi s4, t0, #0x100 +andi s4, t0, #0x200 +andi s4, t0, #0x400 +andi s4, t0, #0x7ff +andi s4, a0, #0xfffff801 +andi s4, a0, #0xfffffc00 +andi s4, a0, #0xfffffe00 +andi s4, a0, #0xffffff00 +andi s4, a0, #0xffffff80 +andi s4, a0, #0xffffffc0 +andi s4, a0, #0xffffffe0 +andi s4, a0, #0xfffffff0 +andi s4, a0, #0xfffffff8 +andi s4, a0, #0xfffffffc +andi s4, a0, #0xfffffffe +andi s4, a0, #0xffffffff +andi s4, a0, #0 +andi s4, a0, #1 +andi s4, a0, #2 +andi s4, a0, #4 +andi s4, a0, #8 +andi s4, a0, #0x10 +andi s4, a0, #0x20 +andi s4, a0, #0x40 +andi s4, a0, #0x80 +andi s4, a0, #0x100 +andi s4, a0, #0x200 +andi s4, a0, #0x400 +andi s4, a0, #0x7ff +andi s4, a5, #0xfffff801 +andi s4, a5, #0xfffffc00 +andi s4, a5, #0xfffffe00 +andi s4, a5, #0xffffff00 +andi s4, a5, #0xffffff80 +andi s4, a5, #0xffffffc0 +andi s4, a5, #0xffffffe0 +andi s4, a5, #0xfffffff0 +andi s4, a5, #0xfffffff8 +andi s4, a5, #0xfffffffc +andi s4, a5, #0xfffffffe +andi s4, a5, #0xffffffff +andi s4, a5, #0 +andi s4, a5, #1 +andi s4, a5, #2 +andi s4, a5, #4 +andi s4, a5, #8 +andi s4, a5, #0x10 +andi s4, a5, #0x20 +andi s4, a5, #0x40 +andi s4, a5, #0x80 +andi s4, a5, #0x100 +andi s4, a5, #0x200 +andi s4, a5, #0x400 +andi s4, a5, #0x7ff +andi s4, s4, #0xfffff801 +andi s4, s4, #0xfffffc00 +andi s4, s4, #0xfffffe00 +andi s4, s4, #0xffffff00 +andi s4, s4, #0xffffff80 +andi s4, s4, #0xffffffc0 +andi s4, s4, #0xffffffe0 +andi s4, s4, #0xfffffff0 +andi s4, s4, #0xfffffff8 +andi s4, s4, #0xfffffffc +andi s4, s4, #0xfffffffe +andi s4, s4, #0xffffffff +andi s4, s4, #0 +andi s4, s4, #1 +andi s4, s4, #2 +andi s4, s4, #4 +andi s4, s4, #8 +andi s4, s4, #0x10 +andi s4, s4, #0x20 +andi s4, s4, #0x40 +andi s4, s4, #0x80 +andi s4, s4, #0x100 +andi s4, s4, #0x200 +andi s4, s4, #0x400 +andi s4, s4, #0x7ff +andi s4, s9, #0xfffff801 +andi s4, s9, #0xfffffc00 +andi s4, s9, #0xfffffe00 +andi s4, s9, #0xffffff00 +andi s4, s9, #0xffffff80 +andi s4, s9, #0xffffffc0 +andi s4, s9, #0xffffffe0 +andi s4, s9, #0xfffffff0 +andi s4, s9, #0xfffffff8 +andi s4, s9, #0xfffffffc +andi s4, s9, #0xfffffffe +andi s4, s9, #0xffffffff +andi s4, s9, #0 +andi s4, s9, #1 +andi s4, s9, #2 +andi s4, s9, #4 +andi s4, s9, #8 +andi s4, s9, #0x10 +andi s4, s9, #0x20 +andi s4, s9, #0x40 +andi s4, s9, #0x80 +andi s4, s9, #0x100 +andi s4, s9, #0x200 +andi s4, s9, #0x400 +andi s4, s9, #0x7ff +andi s4, t6, #0xfffff801 +andi s4, t6, #0xfffffc00 +andi s4, t6, #0xfffffe00 +andi s4, t6, #0xffffff00 +andi s4, t6, #0xffffff80 +andi s4, t6, #0xffffffc0 +andi s4, t6, #0xffffffe0 +andi s4, t6, #0xfffffff0 +andi s4, t6, #0xfffffff8 +andi s4, t6, #0xfffffffc +andi s4, t6, #0xfffffffe +andi s4, t6, #0xffffffff +andi s4, t6, #0 +andi s4, t6, #1 +andi s4, t6, #2 +andi s4, t6, #4 +andi s4, t6, #8 +andi s4, t6, #0x10 +andi s4, t6, #0x20 +andi s4, t6, #0x40 +andi s4, t6, #0x80 +andi s4, t6, #0x100 +andi s4, t6, #0x200 +andi s4, t6, #0x400 +andi s4, t6, #0x7ff +andi s9, zero, #0xfffff801 +andi s9, zero, #0xfffffc00 +andi s9, zero, #0xfffffe00 +andi s9, zero, #0xffffff00 +andi s9, zero, #0xffffff80 +andi s9, zero, #0xffffffc0 +andi s9, zero, #0xffffffe0 +andi s9, zero, #0xfffffff0 +andi s9, zero, #0xfffffff8 +andi s9, zero, #0xfffffffc +andi s9, zero, #0xfffffffe +andi s9, zero, #0xffffffff +andi s9, zero, #0 +andi s9, zero, #1 +andi s9, zero, #2 +andi s9, zero, #4 +andi s9, zero, #8 +andi s9, zero, #0x10 +andi s9, zero, #0x20 +andi s9, zero, #0x40 +andi s9, zero, #0x80 +andi s9, zero, #0x100 +andi s9, zero, #0x200 +andi s9, zero, #0x400 +andi s9, zero, #0x7ff +andi s9, ra, #0xfffff801 +andi s9, ra, #0xfffffc00 +andi s9, ra, #0xfffffe00 +andi s9, ra, #0xffffff00 +andi s9, ra, #0xffffff80 +andi s9, ra, #0xffffffc0 +andi s9, ra, #0xffffffe0 +andi s9, ra, #0xfffffff0 +andi s9, ra, #0xfffffff8 +andi s9, ra, #0xfffffffc +andi s9, ra, #0xfffffffe +andi s9, ra, #0xffffffff +andi s9, ra, #0 +andi s9, ra, #1 +andi s9, ra, #2 +andi s9, ra, #4 +andi s9, ra, #8 +andi s9, ra, #0x10 +andi s9, ra, #0x20 +andi s9, ra, #0x40 +andi s9, ra, #0x80 +andi s9, ra, #0x100 +andi s9, ra, #0x200 +andi s9, ra, #0x400 +andi s9, ra, #0x7ff +andi s9, t0, #0xfffff801 +andi s9, t0, #0xfffffc00 +andi s9, t0, #0xfffffe00 +andi s9, t0, #0xffffff00 +andi s9, t0, #0xffffff80 +andi s9, t0, #0xffffffc0 +andi s9, t0, #0xffffffe0 +andi s9, t0, #0xfffffff0 +andi s9, t0, #0xfffffff8 +andi s9, t0, #0xfffffffc +andi s9, t0, #0xfffffffe +andi s9, t0, #0xffffffff +andi s9, t0, #0 +andi s9, t0, #1 +andi s9, t0, #2 +andi s9, t0, #4 +andi s9, t0, #8 +andi s9, t0, #0x10 +andi s9, t0, #0x20 +andi s9, t0, #0x40 +andi s9, t0, #0x80 +andi s9, t0, #0x100 +andi s9, t0, #0x200 +andi s9, t0, #0x400 +andi s9, t0, #0x7ff +andi s9, a0, #0xfffff801 +andi s9, a0, #0xfffffc00 +andi s9, a0, #0xfffffe00 +andi s9, a0, #0xffffff00 +andi s9, a0, #0xffffff80 +andi s9, a0, #0xffffffc0 +andi s9, a0, #0xffffffe0 +andi s9, a0, #0xfffffff0 +andi s9, a0, #0xfffffff8 +andi s9, a0, #0xfffffffc +andi s9, a0, #0xfffffffe +andi s9, a0, #0xffffffff +andi s9, a0, #0 +andi s9, a0, #1 +andi s9, a0, #2 +andi s9, a0, #4 +andi s9, a0, #8 +andi s9, a0, #0x10 +andi s9, a0, #0x20 +andi s9, a0, #0x40 +andi s9, a0, #0x80 +andi s9, a0, #0x100 +andi s9, a0, #0x200 +andi s9, a0, #0x400 +andi s9, a0, #0x7ff +andi s9, a5, #0xfffff801 +andi s9, a5, #0xfffffc00 +andi s9, a5, #0xfffffe00 +andi s9, a5, #0xffffff00 +andi s9, a5, #0xffffff80 +andi s9, a5, #0xffffffc0 +andi s9, a5, #0xffffffe0 +andi s9, a5, #0xfffffff0 +andi s9, a5, #0xfffffff8 +andi s9, a5, #0xfffffffc +andi s9, a5, #0xfffffffe +andi s9, a5, #0xffffffff +andi s9, a5, #0 +andi s9, a5, #1 +andi s9, a5, #2 +andi s9, a5, #4 +andi s9, a5, #8 +andi s9, a5, #0x10 +andi s9, a5, #0x20 +andi s9, a5, #0x40 +andi s9, a5, #0x80 +andi s9, a5, #0x100 +andi s9, a5, #0x200 +andi s9, a5, #0x400 +andi s9, a5, #0x7ff +andi s9, s4, #0xfffff801 +andi s9, s4, #0xfffffc00 +andi s9, s4, #0xfffffe00 +andi s9, s4, #0xffffff00 +andi s9, s4, #0xffffff80 +andi s9, s4, #0xffffffc0 +andi s9, s4, #0xffffffe0 +andi s9, s4, #0xfffffff0 +andi s9, s4, #0xfffffff8 +andi s9, s4, #0xfffffffc +andi s9, s4, #0xfffffffe +andi s9, s4, #0xffffffff +andi s9, s4, #0 +andi s9, s4, #1 +andi s9, s4, #2 +andi s9, s4, #4 +andi s9, s4, #8 +andi s9, s4, #0x10 +andi s9, s4, #0x20 +andi s9, s4, #0x40 +andi s9, s4, #0x80 +andi s9, s4, #0x100 +andi s9, s4, #0x200 +andi s9, s4, #0x400 +andi s9, s4, #0x7ff +andi s9, s9, #0xfffff801 +andi s9, s9, #0xfffffc00 +andi s9, s9, #0xfffffe00 +andi s9, s9, #0xffffff00 +andi s9, s9, #0xffffff80 +andi s9, s9, #0xffffffc0 +andi s9, s9, #0xffffffe0 +andi s9, s9, #0xfffffff0 +andi s9, s9, #0xfffffff8 +andi s9, s9, #0xfffffffc +andi s9, s9, #0xfffffffe +andi s9, s9, #0xffffffff +andi s9, s9, #0 +andi s9, s9, #1 +andi s9, s9, #2 +andi s9, s9, #4 +andi s9, s9, #8 +andi s9, s9, #0x10 +andi s9, s9, #0x20 +andi s9, s9, #0x40 +andi s9, s9, #0x80 +andi s9, s9, #0x100 +andi s9, s9, #0x200 +andi s9, s9, #0x400 +andi s9, s9, #0x7ff +andi s9, t6, #0xfffff801 +andi s9, t6, #0xfffffc00 +andi s9, t6, #0xfffffe00 +andi s9, t6, #0xffffff00 +andi s9, t6, #0xffffff80 +andi s9, t6, #0xffffffc0 +andi s9, t6, #0xffffffe0 +andi s9, t6, #0xfffffff0 +andi s9, t6, #0xfffffff8 +andi s9, t6, #0xfffffffc +andi s9, t6, #0xfffffffe +andi s9, t6, #0xffffffff +andi s9, t6, #0 +andi s9, t6, #1 +andi s9, t6, #2 +andi s9, t6, #4 +andi s9, t6, #8 +andi s9, t6, #0x10 +andi s9, t6, #0x20 +andi s9, t6, #0x40 +andi s9, t6, #0x80 +andi s9, t6, #0x100 +andi s9, t6, #0x200 +andi s9, t6, #0x400 +andi s9, t6, #0x7ff +andi t6, zero, #0xfffff801 +andi t6, zero, #0xfffffc00 +andi t6, zero, #0xfffffe00 +andi t6, zero, #0xffffff00 +andi t6, zero, #0xffffff80 +andi t6, zero, #0xffffffc0 +andi t6, zero, #0xffffffe0 +andi t6, zero, #0xfffffff0 +andi t6, zero, #0xfffffff8 +andi t6, zero, #0xfffffffc +andi t6, zero, #0xfffffffe +andi t6, zero, #0xffffffff +andi t6, zero, #0 +andi t6, zero, #1 +andi t6, zero, #2 +andi t6, zero, #4 +andi t6, zero, #8 +andi t6, zero, #0x10 +andi t6, zero, #0x20 +andi t6, zero, #0x40 +andi t6, zero, #0x80 +andi t6, zero, #0x100 +andi t6, zero, #0x200 +andi t6, zero, #0x400 +andi t6, zero, #0x7ff +andi t6, ra, #0xfffff801 +andi t6, ra, #0xfffffc00 +andi t6, ra, #0xfffffe00 +andi t6, ra, #0xffffff00 +andi t6, ra, #0xffffff80 +andi t6, ra, #0xffffffc0 +andi t6, ra, #0xffffffe0 +andi t6, ra, #0xfffffff0 +andi t6, ra, #0xfffffff8 +andi t6, ra, #0xfffffffc +andi t6, ra, #0xfffffffe +andi t6, ra, #0xffffffff +andi t6, ra, #0 +andi t6, ra, #1 +andi t6, ra, #2 +andi t6, ra, #4 +andi t6, ra, #8 +andi t6, ra, #0x10 +andi t6, ra, #0x20 +andi t6, ra, #0x40 +andi t6, ra, #0x80 +andi t6, ra, #0x100 +andi t6, ra, #0x200 +andi t6, ra, #0x400 +andi t6, ra, #0x7ff +andi t6, t0, #0xfffff801 +andi t6, t0, #0xfffffc00 +andi t6, t0, #0xfffffe00 +andi t6, t0, #0xffffff00 +andi t6, t0, #0xffffff80 +andi t6, t0, #0xffffffc0 +andi t6, t0, #0xffffffe0 +andi t6, t0, #0xfffffff0 +andi t6, t0, #0xfffffff8 +andi t6, t0, #0xfffffffc +andi t6, t0, #0xfffffffe +andi t6, t0, #0xffffffff +andi t6, t0, #0 +andi t6, t0, #1 +andi t6, t0, #2 +andi t6, t0, #4 +andi t6, t0, #8 +andi t6, t0, #0x10 +andi t6, t0, #0x20 +andi t6, t0, #0x40 +andi t6, t0, #0x80 +andi t6, t0, #0x100 +andi t6, t0, #0x200 +andi t6, t0, #0x400 +andi t6, t0, #0x7ff +andi t6, a0, #0xfffff801 +andi t6, a0, #0xfffffc00 +andi t6, a0, #0xfffffe00 +andi t6, a0, #0xffffff00 +andi t6, a0, #0xffffff80 +andi t6, a0, #0xffffffc0 +andi t6, a0, #0xffffffe0 +andi t6, a0, #0xfffffff0 +andi t6, a0, #0xfffffff8 +andi t6, a0, #0xfffffffc +andi t6, a0, #0xfffffffe +andi t6, a0, #0xffffffff +andi t6, a0, #0 +andi t6, a0, #1 +andi t6, a0, #2 +andi t6, a0, #4 +andi t6, a0, #8 +andi t6, a0, #0x10 +andi t6, a0, #0x20 +andi t6, a0, #0x40 +andi t6, a0, #0x80 +andi t6, a0, #0x100 +andi t6, a0, #0x200 +andi t6, a0, #0x400 +andi t6, a0, #0x7ff +andi t6, a5, #0xfffff801 +andi t6, a5, #0xfffffc00 +andi t6, a5, #0xfffffe00 +andi t6, a5, #0xffffff00 +andi t6, a5, #0xffffff80 +andi t6, a5, #0xffffffc0 +andi t6, a5, #0xffffffe0 +andi t6, a5, #0xfffffff0 +andi t6, a5, #0xfffffff8 +andi t6, a5, #0xfffffffc +andi t6, a5, #0xfffffffe +andi t6, a5, #0xffffffff +andi t6, a5, #0 +andi t6, a5, #1 +andi t6, a5, #2 +andi t6, a5, #4 +andi t6, a5, #8 +andi t6, a5, #0x10 +andi t6, a5, #0x20 +andi t6, a5, #0x40 +andi t6, a5, #0x80 +andi t6, a5, #0x100 +andi t6, a5, #0x200 +andi t6, a5, #0x400 +andi t6, a5, #0x7ff +andi t6, s4, #0xfffff801 +andi t6, s4, #0xfffffc00 +andi t6, s4, #0xfffffe00 +andi t6, s4, #0xffffff00 +andi t6, s4, #0xffffff80 +andi t6, s4, #0xffffffc0 +andi t6, s4, #0xffffffe0 +andi t6, s4, #0xfffffff0 +andi t6, s4, #0xfffffff8 +andi t6, s4, #0xfffffffc +andi t6, s4, #0xfffffffe +andi t6, s4, #0xffffffff +andi t6, s4, #0 +andi t6, s4, #1 +andi t6, s4, #2 +andi t6, s4, #4 +andi t6, s4, #8 +andi t6, s4, #0x10 +andi t6, s4, #0x20 +andi t6, s4, #0x40 +andi t6, s4, #0x80 +andi t6, s4, #0x100 +andi t6, s4, #0x200 +andi t6, s4, #0x400 +andi t6, s4, #0x7ff +andi t6, s9, #0xfffff801 +andi t6, s9, #0xfffffc00 +andi t6, s9, #0xfffffe00 +andi t6, s9, #0xffffff00 +andi t6, s9, #0xffffff80 +andi t6, s9, #0xffffffc0 +andi t6, s9, #0xffffffe0 +andi t6, s9, #0xfffffff0 +andi t6, s9, #0xfffffff8 +andi t6, s9, #0xfffffffc +andi t6, s9, #0xfffffffe +andi t6, s9, #0xffffffff +andi t6, s9, #0 +andi t6, s9, #1 +andi t6, s9, #2 +andi t6, s9, #4 +andi t6, s9, #8 +andi t6, s9, #0x10 +andi t6, s9, #0x20 +andi t6, s9, #0x40 +andi t6, s9, #0x80 +andi t6, s9, #0x100 +andi t6, s9, #0x200 +andi t6, s9, #0x400 +andi t6, s9, #0x7ff +andi t6, t6, #0xfffff801 +andi t6, t6, #0xfffffc00 +andi t6, t6, #0xfffffe00 +andi t6, t6, #0xffffff00 +andi t6, t6, #0xffffff80 +andi t6, t6, #0xffffffc0 +andi t6, t6, #0xffffffe0 +andi t6, t6, #0xfffffff0 +andi t6, t6, #0xfffffff8 +andi t6, t6, #0xfffffffc +andi t6, t6, #0xfffffffe +andi t6, t6, #0xffffffff +andi t6, t6, #0 +andi t6, t6, #1 +andi t6, t6, #2 +andi t6, t6, #4 +andi t6, t6, #8 +andi t6, t6, #0x10 +andi t6, t6, #0x20 +andi t6, t6, #0x40 +andi t6, t6, #0x80 +andi t6, t6, #0x100 +andi t6, t6, #0x200 +andi t6, t6, #0x400 +andi t6, t6, #0x7ff diff --git a/tests/riscv/rv32i/auipc.asm b/tests/riscv/rv32i/auipc.asm new file mode 100644 index 0000000..82636c5 --- /dev/null +++ b/tests/riscv/rv32i/auipc.asm @@ -0,0 +1,44 @@ +.lang riscv32 +.org 0x0 + +auipc zero, #0x0 +auipc zero, #0x1000000 +auipc zero, #0x10000000 +auipc zero, #0x80000000 +auipc zero, #0xfffff000 +auipc ra, #0x0 +auipc ra, #0x1000000 +auipc ra, #0x10000000 +auipc ra, #0x80000000 +auipc ra, #0xfffff000 +auipc t0, #0x0 +auipc t0, #0x1000000 +auipc t0, #0x10000000 +auipc t0, #0x80000000 +auipc t0, #0xfffff000 +auipc a0, #0x0 +auipc a0, #0x1000000 +auipc a0, #0x10000000 +auipc a0, #0x80000000 +auipc a0, #0xfffff000 +auipc a5, #0x0 +auipc a5, #0x1000000 +auipc a5, #0x10000000 +auipc a5, #0x80000000 +auipc a5, #0xfffff000 +auipc s4, #0x0 +auipc s4, #0x1000000 +auipc s4, #0x10000000 +auipc s4, #0x80000000 +auipc s4, #0xfffff000 +auipc s9, #0x0 +auipc s9, #0x1000000 +auipc s9, #0x10000000 +auipc s9, #0x80000000 +auipc s9, #0xfffff000 +auipc t6, #0x0 +auipc t6, #0x1000000 +auipc t6, #0x10000000 +auipc t6, #0x80000000 +auipc t6, #0xfffff000 + diff --git a/tests/riscv/rv32i/auipc.bin b/tests/riscv/rv32i/auipc.bin new file mode 100644 index 0000000000000000000000000000000000000000..62b9a376370db8f1808d96cf1d407a9e26c5ba13 GIT binary patch literal 160 zcmWm5K?;O05Jb^75CS0(ce$>&@S1}lf(-P$S=8q9YDL6~*lf3BeKJqYHrwqu|E*|6 uD_YU6%vF7>Z}qLdH`lnvHLh_F*SXGhu5&LpxWNr>a9?d|Q=8h{#66!Ifk&1ArXm1tWr=nje zhVzv8oKmkcWU5g|8hxiRUmCmCxQh(`k|EYPO=bwkhW6gjeH;3XVYtkRuQ~OmKw67B zvFHbj`LWoo#a$Knw*s*(X`CaRI@(7^_v`3)j^Vl_zL(Uyil*{}Gf(^E>Ha+Z-ZR`( K#E*)4fA9}{vrmBl literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/beq.disasm b/tests/riscv/rv32i/beq.disasm new file mode 100644 index 0000000..2bcc667 --- /dev/null +++ b/tests/riscv/rv32i/beq.disasm @@ -0,0 +1,64 @@ +beq zero, zero, #4 +beq zero, ra, #8 +beq zero, t0, #12 +beq zero, a0, #16 +beq zero, a5, #20 +beq zero, s4, #24 +beq zero, s9, #28 +beq zero, t6, #32 +beq ra, zero, #36 +beq ra, ra, #40 +beq ra, t0, #44 +beq ra, a0, #48 +beq ra, a5, #52 +beq ra, s4, #56 +beq ra, s9, #60 +beq ra, t6, #64 +beq t0, zero, #68 +beq t0, ra, #72 +beq t0, t0, #76 +beq t0, a0, #80 +beq t0, a5, #84 +beq t0, s4, #88 +beq t0, s9, #92 +beq t0, t6, #96 +beq a0, zero, #100 +beq a0, ra, #104 +beq a0, t0, #108 +beq a0, a0, #112 +beq a0, a5, #116 +beq a0, s4, #120 +beq a0, s9, #124 +beq a0, t6, #128 +beq a5, zero, #132 +beq a5, ra, #136 +beq a5, t0, #140 +beq a5, a0, #144 +beq a5, a5, #148 +beq a5, s4, #152 +beq a5, s9, #156 +beq a5, t6, #160 +beq s4, zero, #164 +beq s4, ra, #168 +beq s4, t0, #172 +beq s4, a0, #176 +beq s4, a5, #180 +beq s4, s4, #184 +beq s4, s9, #188 +beq s4, t6, #192 +beq s9, zero, #196 +beq s9, ra, #200 +beq s9, t0, #204 +beq s9, a0, #208 +beq s9, a5, #212 +beq s9, s4, #216 +beq s9, s9, #220 +beq s9, t6, #224 +beq t6, zero, #228 +beq t6, ra, #232 +beq t6, t0, #236 +beq t6, a0, #240 +beq t6, a5, #244 +beq t6, s4, #248 +beq t6, s9, #252 +beq t6, t6, #256 diff --git a/tests/riscv/rv32i/bge.asm b/tests/riscv/rv32i/bge.asm new file mode 100644 index 0000000..e0594ba --- /dev/null +++ b/tests/riscv/rv32i/bge.asm @@ -0,0 +1,132 @@ +.lang riscv32 +.org 0x0 + +bge zero, zero, label_0 +label_0: +bge zero, ra, label_1 +label_1: +bge zero, t0, label_2 +label_2: +bge zero, a0, label_3 +label_3: +bge zero, a5, label_4 +label_4: +bge zero, s4, label_5 +label_5: +bge zero, s9, label_6 +label_6: +bge zero, t6, label_7 +label_7: +bge ra, zero, label_8 +label_8: +bge ra, ra, label_9 +label_9: +bge ra, t0, label_10 +label_10: +bge ra, a0, label_11 +label_11: +bge ra, a5, label_12 +label_12: +bge ra, s4, label_13 +label_13: +bge ra, s9, label_14 +label_14: +bge ra, t6, label_15 +label_15: +bge t0, zero, label_16 +label_16: +bge t0, ra, label_17 +label_17: +bge t0, t0, label_18 +label_18: +bge t0, a0, label_19 +label_19: +bge t0, a5, label_20 +label_20: +bge t0, s4, label_21 +label_21: +bge t0, s9, label_22 +label_22: +bge t0, t6, label_23 +label_23: +bge a0, zero, label_24 +label_24: +bge a0, ra, label_25 +label_25: +bge a0, t0, label_26 +label_26: +bge a0, a0, label_27 +label_27: +bge a0, a5, label_28 +label_28: +bge a0, s4, label_29 +label_29: +bge a0, s9, label_30 +label_30: +bge a0, t6, label_31 +label_31: +bge a5, zero, label_32 +label_32: +bge a5, ra, label_33 +label_33: +bge a5, t0, label_34 +label_34: +bge a5, a0, label_35 +label_35: +bge a5, a5, label_36 +label_36: +bge a5, s4, label_37 +label_37: +bge a5, s9, label_38 +label_38: +bge a5, t6, label_39 +label_39: +bge s4, zero, label_40 +label_40: +bge s4, ra, label_41 +label_41: +bge s4, t0, label_42 +label_42: +bge s4, a0, label_43 +label_43: +bge s4, a5, label_44 +label_44: +bge s4, s4, label_45 +label_45: +bge s4, s9, label_46 +label_46: +bge s4, t6, label_47 +label_47: +bge s9, zero, label_48 +label_48: +bge s9, ra, label_49 +label_49: +bge s9, t0, label_50 +label_50: +bge s9, a0, label_51 +label_51: +bge s9, a5, label_52 +label_52: +bge s9, s4, label_53 +label_53: +bge s9, s9, label_54 +label_54: +bge s9, t6, label_55 +label_55: +bge t6, zero, label_56 +label_56: +bge t6, ra, label_57 +label_57: +bge t6, t0, label_58 +label_58: +bge t6, a0, label_59 +label_59: +bge t6, a5, label_60 +label_60: +bge t6, s4, label_61 +label_61: +bge t6, s9, label_62 +label_62: +bge t6, t6, label_63 +label_63: + diff --git a/tests/riscv/rv32i/bge.bin b/tests/riscv/rv32i/bge.bin new file mode 100644 index 0000000000000000000000000000000000000000..e6f21e2fb50f825f9eb9fc4a0ea8024b58256726 GIT binary patch literal 256 zcmV~$e@Db%0KoC*p8bCI>xx98w{jwpXlA!&X8rMfLnji6P9ze&m6@5D*=v~N9Ot+` zA7UX$=7Ka5WNSe_35vyxay28GG-@Gf=8`s&bZbdJNrr{SxYDR5gIek|r#fw{(|zjn z8=c|WV0<>HHWsmAlAM{OOOx!&B;T48Hx}iKMYMIOEt}@trhT;OzHR!Q&2Z~5zB*Jp zmsly13q_hMvL8jhR}^wI R3+Rsl!$ZjU5mFsb{sECmV}Sqw literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/bge.disasm b/tests/riscv/rv32i/bge.disasm new file mode 100644 index 0000000..8786f00 --- /dev/null +++ b/tests/riscv/rv32i/bge.disasm @@ -0,0 +1,64 @@ +bge zero, zero, #4 +bge zero, ra, #8 +bge zero, t0, #12 +bge zero, a0, #16 +bge zero, a5, #20 +bge zero, s4, #24 +bge zero, s9, #28 +bge zero, t6, #32 +bge ra, zero, #36 +bge ra, ra, #40 +bge ra, t0, #44 +bge ra, a0, #48 +bge ra, a5, #52 +bge ra, s4, #56 +bge ra, s9, #60 +bge ra, t6, #64 +bge t0, zero, #68 +bge t0, ra, #72 +bge t0, t0, #76 +bge t0, a0, #80 +bge t0, a5, #84 +bge t0, s4, #88 +bge t0, s9, #92 +bge t0, t6, #96 +bge a0, zero, #100 +bge a0, ra, #104 +bge a0, t0, #108 +bge a0, a0, #112 +bge a0, a5, #116 +bge a0, s4, #120 +bge a0, s9, #124 +bge a0, t6, #128 +bge a5, zero, #132 +bge a5, ra, #136 +bge a5, t0, #140 +bge a5, a0, #144 +bge a5, a5, #148 +bge a5, s4, #152 +bge a5, s9, #156 +bge a5, t6, #160 +bge s4, zero, #164 +bge s4, ra, #168 +bge s4, t0, #172 +bge s4, a0, #176 +bge s4, a5, #180 +bge s4, s4, #184 +bge s4, s9, #188 +bge s4, t6, #192 +bge s9, zero, #196 +bge s9, ra, #200 +bge s9, t0, #204 +bge s9, a0, #208 +bge s9, a5, #212 +bge s9, s4, #216 +bge s9, s9, #220 +bge s9, t6, #224 +bge t6, zero, #228 +bge t6, ra, #232 +bge t6, t0, #236 +bge t6, a0, #240 +bge t6, a5, #244 +bge t6, s4, #248 +bge t6, s9, #252 +bge t6, t6, #256 diff --git a/tests/riscv/rv32i/bgeu.asm b/tests/riscv/rv32i/bgeu.asm new file mode 100644 index 0000000..e3601c3 --- /dev/null +++ b/tests/riscv/rv32i/bgeu.asm @@ -0,0 +1,132 @@ +.lang riscv32 +.org 0x0 + +bgeu zero, zero, label_0 +label_0: +bgeu zero, ra, label_1 +label_1: +bgeu zero, t0, label_2 +label_2: +bgeu zero, a0, label_3 +label_3: +bgeu zero, a5, label_4 +label_4: +bgeu zero, s4, label_5 +label_5: +bgeu zero, s9, label_6 +label_6: +bgeu zero, t6, label_7 +label_7: +bgeu ra, zero, label_8 +label_8: +bgeu ra, ra, label_9 +label_9: +bgeu ra, t0, label_10 +label_10: +bgeu ra, a0, label_11 +label_11: +bgeu ra, a5, label_12 +label_12: +bgeu ra, s4, label_13 +label_13: +bgeu ra, s9, label_14 +label_14: +bgeu ra, t6, label_15 +label_15: +bgeu t0, zero, label_16 +label_16: +bgeu t0, ra, label_17 +label_17: +bgeu t0, t0, label_18 +label_18: +bgeu t0, a0, label_19 +label_19: +bgeu t0, a5, label_20 +label_20: +bgeu t0, s4, label_21 +label_21: +bgeu t0, s9, label_22 +label_22: +bgeu t0, t6, label_23 +label_23: +bgeu a0, zero, label_24 +label_24: +bgeu a0, ra, label_25 +label_25: +bgeu a0, t0, label_26 +label_26: +bgeu a0, a0, label_27 +label_27: +bgeu a0, a5, label_28 +label_28: +bgeu a0, s4, label_29 +label_29: +bgeu a0, s9, label_30 +label_30: +bgeu a0, t6, label_31 +label_31: +bgeu a5, zero, label_32 +label_32: +bgeu a5, ra, label_33 +label_33: +bgeu a5, t0, label_34 +label_34: +bgeu a5, a0, label_35 +label_35: +bgeu a5, a5, label_36 +label_36: +bgeu a5, s4, label_37 +label_37: +bgeu a5, s9, label_38 +label_38: +bgeu a5, t6, label_39 +label_39: +bgeu s4, zero, label_40 +label_40: +bgeu s4, ra, label_41 +label_41: +bgeu s4, t0, label_42 +label_42: +bgeu s4, a0, label_43 +label_43: +bgeu s4, a5, label_44 +label_44: +bgeu s4, s4, label_45 +label_45: +bgeu s4, s9, label_46 +label_46: +bgeu s4, t6, label_47 +label_47: +bgeu s9, zero, label_48 +label_48: +bgeu s9, ra, label_49 +label_49: +bgeu s9, t0, label_50 +label_50: +bgeu s9, a0, label_51 +label_51: +bgeu s9, a5, label_52 +label_52: +bgeu s9, s4, label_53 +label_53: +bgeu s9, s9, label_54 +label_54: +bgeu s9, t6, label_55 +label_55: +bgeu t6, zero, label_56 +label_56: +bgeu t6, ra, label_57 +label_57: +bgeu t6, t0, label_58 +label_58: +bgeu t6, a0, label_59 +label_59: +bgeu t6, a5, label_60 +label_60: +bgeu t6, s4, label_61 +label_61: +bgeu t6, s9, label_62 +label_62: +bgeu t6, t6, label_63 +label_63: + diff --git a/tests/riscv/rv32i/bgeu.bin b/tests/riscv/rv32i/bgeu.bin new file mode 100644 index 0000000000000000000000000000000000000000..00b358c6e01beab226955021abf2e070b7e5a738 GIT binary patch literal 256 zcmV~$e@Db%0KoC*_ItbixFV70t(-_CI*~~9$M+4)%*@PQ!-+(q6NyA`?eW;{=JD9| z`A`T!xe!z_ z6j4NZ5>Y)w)ISl8j%csubZ>KVouJ~F{xoKIj2VApw23j-3DbLmG#M&O>CaMzrLWnT2bC literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/bgeu.disasm b/tests/riscv/rv32i/bgeu.disasm new file mode 100644 index 0000000..7b962ff --- /dev/null +++ b/tests/riscv/rv32i/bgeu.disasm @@ -0,0 +1,64 @@ +bgeu zero, zero, #4 +bgeu zero, ra, #8 +bgeu zero, t0, #12 +bgeu zero, a0, #16 +bgeu zero, a5, #20 +bgeu zero, s4, #24 +bgeu zero, s9, #28 +bgeu zero, t6, #32 +bgeu ra, zero, #36 +bgeu ra, ra, #40 +bgeu ra, t0, #44 +bgeu ra, a0, #48 +bgeu ra, a5, #52 +bgeu ra, s4, #56 +bgeu ra, s9, #60 +bgeu ra, t6, #64 +bgeu t0, zero, #68 +bgeu t0, ra, #72 +bgeu t0, t0, #76 +bgeu t0, a0, #80 +bgeu t0, a5, #84 +bgeu t0, s4, #88 +bgeu t0, s9, #92 +bgeu t0, t6, #96 +bgeu a0, zero, #100 +bgeu a0, ra, #104 +bgeu a0, t0, #108 +bgeu a0, a0, #112 +bgeu a0, a5, #116 +bgeu a0, s4, #120 +bgeu a0, s9, #124 +bgeu a0, t6, #128 +bgeu a5, zero, #132 +bgeu a5, ra, #136 +bgeu a5, t0, #140 +bgeu a5, a0, #144 +bgeu a5, a5, #148 +bgeu a5, s4, #152 +bgeu a5, s9, #156 +bgeu a5, t6, #160 +bgeu s4, zero, #164 +bgeu s4, ra, #168 +bgeu s4, t0, #172 +bgeu s4, a0, #176 +bgeu s4, a5, #180 +bgeu s4, s4, #184 +bgeu s4, s9, #188 +bgeu s4, t6, #192 +bgeu s9, zero, #196 +bgeu s9, ra, #200 +bgeu s9, t0, #204 +bgeu s9, a0, #208 +bgeu s9, a5, #212 +bgeu s9, s4, #216 +bgeu s9, s9, #220 +bgeu s9, t6, #224 +bgeu t6, zero, #228 +bgeu t6, ra, #232 +bgeu t6, t0, #236 +bgeu t6, a0, #240 +bgeu t6, a5, #244 +bgeu t6, s4, #248 +bgeu t6, s9, #252 +bgeu t6, t6, #256 diff --git a/tests/riscv/rv32i/blt.asm b/tests/riscv/rv32i/blt.asm new file mode 100644 index 0000000..012b63f --- /dev/null +++ b/tests/riscv/rv32i/blt.asm @@ -0,0 +1,132 @@ +.lang riscv32 +.org 0x0 + +blt zero, zero, label_0 +label_0: +blt zero, ra, label_1 +label_1: +blt zero, t0, label_2 +label_2: +blt zero, a0, label_3 +label_3: +blt zero, a5, label_4 +label_4: +blt zero, s4, label_5 +label_5: +blt zero, s9, label_6 +label_6: +blt zero, t6, label_7 +label_7: +blt ra, zero, label_8 +label_8: +blt ra, ra, label_9 +label_9: +blt ra, t0, label_10 +label_10: +blt ra, a0, label_11 +label_11: +blt ra, a5, label_12 +label_12: +blt ra, s4, label_13 +label_13: +blt ra, s9, label_14 +label_14: +blt ra, t6, label_15 +label_15: +blt t0, zero, label_16 +label_16: +blt t0, ra, label_17 +label_17: +blt t0, t0, label_18 +label_18: +blt t0, a0, label_19 +label_19: +blt t0, a5, label_20 +label_20: +blt t0, s4, label_21 +label_21: +blt t0, s9, label_22 +label_22: +blt t0, t6, label_23 +label_23: +blt a0, zero, label_24 +label_24: +blt a0, ra, label_25 +label_25: +blt a0, t0, label_26 +label_26: +blt a0, a0, label_27 +label_27: +blt a0, a5, label_28 +label_28: +blt a0, s4, label_29 +label_29: +blt a0, s9, label_30 +label_30: +blt a0, t6, label_31 +label_31: +blt a5, zero, label_32 +label_32: +blt a5, ra, label_33 +label_33: +blt a5, t0, label_34 +label_34: +blt a5, a0, label_35 +label_35: +blt a5, a5, label_36 +label_36: +blt a5, s4, label_37 +label_37: +blt a5, s9, label_38 +label_38: +blt a5, t6, label_39 +label_39: +blt s4, zero, label_40 +label_40: +blt s4, ra, label_41 +label_41: +blt s4, t0, label_42 +label_42: +blt s4, a0, label_43 +label_43: +blt s4, a5, label_44 +label_44: +blt s4, s4, label_45 +label_45: +blt s4, s9, label_46 +label_46: +blt s4, t6, label_47 +label_47: +blt s9, zero, label_48 +label_48: +blt s9, ra, label_49 +label_49: +blt s9, t0, label_50 +label_50: +blt s9, a0, label_51 +label_51: +blt s9, a5, label_52 +label_52: +blt s9, s4, label_53 +label_53: +blt s9, s9, label_54 +label_54: +blt s9, t6, label_55 +label_55: +blt t6, zero, label_56 +label_56: +blt t6, ra, label_57 +label_57: +blt t6, t0, label_58 +label_58: +blt t6, a0, label_59 +label_59: +blt t6, a5, label_60 +label_60: +blt t6, s4, label_61 +label_61: +blt t6, s9, label_62 +label_62: +blt t6, t6, label_63 +label_63: + diff --git a/tests/riscv/rv32i/blt.bin b/tests/riscv/rv32i/blt.bin new file mode 100644 index 0000000000000000000000000000000000000000..0c75c9bdaa80e34c36d91e9cbde5d4bae7f620e8 GIT binary patch literal 256 zcmV~$e@Db%0KoC*_IuBsZC4}`y_K1@W@dLHk?4=_8#<9lbRv=HEzHc!%wEeJ=Qzjp z`49_1G8d#vLADm;lc0!Zl&cxhq*DuxX0FjLHM+G%KWPk+&bZR4CX-q-Xig2L{8PnB+^ z(w}P#&l=^*AkuW=Bc0?W7Ujkv zvTfoMo8-YJ{jtfmHu;r9@#YY2Ju26wK6PmxUD{ulZs*cpdkpU$EP?N(MK60Jxi`tjb-aZJ-V#oZ zE~wUmdLw9NLAzS8R15OiLJLWkOZv5B*htJQ8CMpQvQV>wmNs2s(?8e@pEhP|GhR7N z+CgnS3df~9cc~s->MxgO=h9w#EZ;oxU4Zs{x(lEF$!GZXF?*l!CSZCGQ2U4?3@MwC z>N%wT326=??QO);MC6AA9mjNSO#c!y{KlAL%y^eDjS1?Qp|h0kGNpe_8U9ktDP_FR Km_9Pp>FghX(Nlo{ literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/bne.disasm b/tests/riscv/rv32i/bne.disasm new file mode 100644 index 0000000..9c4fbef --- /dev/null +++ b/tests/riscv/rv32i/bne.disasm @@ -0,0 +1,64 @@ +bne zero, zero, #4 +bne zero, ra, #8 +bne zero, t0, #12 +bne zero, a0, #16 +bne zero, a5, #20 +bne zero, s4, #24 +bne zero, s9, #28 +bne zero, t6, #32 +bne ra, zero, #36 +bne ra, ra, #40 +bne ra, t0, #44 +bne ra, a0, #48 +bne ra, a5, #52 +bne ra, s4, #56 +bne ra, s9, #60 +bne ra, t6, #64 +bne t0, zero, #68 +bne t0, ra, #72 +bne t0, t0, #76 +bne t0, a0, #80 +bne t0, a5, #84 +bne t0, s4, #88 +bne t0, s9, #92 +bne t0, t6, #96 +bne a0, zero, #100 +bne a0, ra, #104 +bne a0, t0, #108 +bne a0, a0, #112 +bne a0, a5, #116 +bne a0, s4, #120 +bne a0, s9, #124 +bne a0, t6, #128 +bne a5, zero, #132 +bne a5, ra, #136 +bne a5, t0, #140 +bne a5, a0, #144 +bne a5, a5, #148 +bne a5, s4, #152 +bne a5, s9, #156 +bne a5, t6, #160 +bne s4, zero, #164 +bne s4, ra, #168 +bne s4, t0, #172 +bne s4, a0, #176 +bne s4, a5, #180 +bne s4, s4, #184 +bne s4, s9, #188 +bne s4, t6, #192 +bne s9, zero, #196 +bne s9, ra, #200 +bne s9, t0, #204 +bne s9, a0, #208 +bne s9, a5, #212 +bne s9, s4, #216 +bne s9, s9, #220 +bne s9, t6, #224 +bne t6, zero, #228 +bne t6, ra, #232 +bne t6, t0, #236 +bne t6, a0, #240 +bne t6, a5, #244 +bne t6, s4, #248 +bne t6, s9, #252 +bne t6, t6, #256 diff --git a/tests/riscv/rv32i/ebreak.asm b/tests/riscv/rv32i/ebreak.asm new file mode 100644 index 0000000..83b3e1c --- /dev/null +++ b/tests/riscv/rv32i/ebreak.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +ebreak + diff --git a/tests/riscv/rv32i/ebreak.bin b/tests/riscv/rv32i/ebreak.bin new file mode 100644 index 0000000000000000000000000000000000000000..0e95dc7cbd5167539f689e046340cb7a73993bfa GIT binary patch literal 4 LcmXSB5MTfR0q_8X literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/ebreak.disasm b/tests/riscv/rv32i/ebreak.disasm new file mode 100644 index 0000000..92b8ac6 --- /dev/null +++ b/tests/riscv/rv32i/ebreak.disasm @@ -0,0 +1 @@ +ebreak diff --git a/tests/riscv/rv32i/ecall.asm b/tests/riscv/rv32i/ecall.asm new file mode 100644 index 0000000..5ff9cca --- /dev/null +++ b/tests/riscv/rv32i/ecall.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +ecall + diff --git a/tests/riscv/rv32i/ecall.bin b/tests/riscv/rv32i/ecall.bin new file mode 100644 index 0000000000000000000000000000000000000000..807d9be3b2b7d936eb933c2aa06c9dc7c2d654cd GIT binary patch literal 4 LcmXSBU|;|M0nh++ literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/ecall.disasm b/tests/riscv/rv32i/ecall.disasm new file mode 100644 index 0000000..45a1522 --- /dev/null +++ b/tests/riscv/rv32i/ecall.disasm @@ -0,0 +1 @@ +ecall diff --git a/tests/riscv/rv32i/fence.asm b/tests/riscv/rv32i/fence.asm new file mode 100644 index 0000000..4ae0ac1 --- /dev/null +++ b/tests/riscv/rv32i/fence.asm @@ -0,0 +1,7 @@ +.lang riscv32 +.org 0x0 + +fence #0x00, zero, zero +fence #0x0F, zero, zero +fence + diff --git a/tests/riscv/rv32i/fence.bin b/tests/riscv/rv32i/fence.bin new file mode 100644 index 0000000000000000000000000000000000000000..c9ec50937c800a3d3cf4a708068aae8e552df49e GIT binary patch literal 12 Qcmd;QU|`^9_yEHE00{#E9RL6T literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/fence.disasm b/tests/riscv/rv32i/fence.disasm new file mode 100644 index 0000000..63ed775 --- /dev/null +++ b/tests/riscv/rv32i/fence.disasm @@ -0,0 +1,6 @@ +Colliding matches: "fence fence " +1: "fence" +2: "fence #0xFF, zero, zero" +fence #0x00, zero, zero +fence #0x0F, zero, zero +fence diff --git a/tests/riscv/rv32i/fence.i.asm b/tests/riscv/rv32i/fence.i.asm new file mode 100644 index 0000000..0db42c3 --- /dev/null +++ b/tests/riscv/rv32i/fence.i.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fence.i + diff --git a/tests/riscv/rv32i/fence.i.bin b/tests/riscv/rv32i/fence.i.bin new file mode 100644 index 0000000000000000000000000000000000000000..0b75e9966626aa2fe87c7d20dbdd17c9dfceeac6 GIT binary patch literal 4 Lcmd-VU|;|M0B`^x literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/fence.i.disasm b/tests/riscv/rv32i/fence.i.disasm new file mode 100644 index 0000000..500e5f7 --- /dev/null +++ b/tests/riscv/rv32i/fence.i.disasm @@ -0,0 +1 @@ +fence.i diff --git a/tests/riscv/rv32i/fence_i.asm b/tests/riscv/rv32i/fence_i.asm new file mode 100644 index 0000000..0db42c3 --- /dev/null +++ b/tests/riscv/rv32i/fence_i.asm @@ -0,0 +1,5 @@ +.lang riscv32 +.org 0x0 + +fence.i + diff --git a/tests/riscv/rv32i/fence_i.bin b/tests/riscv/rv32i/fence_i.bin new file mode 100644 index 0000000000000000000000000000000000000000..0b75e9966626aa2fe87c7d20dbdd17c9dfceeac6 GIT binary patch literal 4 Lcmd-VU|;|M0B`^x literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/fence_i.disasm b/tests/riscv/rv32i/fence_i.disasm new file mode 100644 index 0000000..500e5f7 --- /dev/null +++ b/tests/riscv/rv32i/fence_i.disasm @@ -0,0 +1 @@ +fence.i diff --git a/tests/riscv/rv32i/jal.asm b/tests/riscv/rv32i/jal.asm new file mode 100644 index 0000000..1d60e2e --- /dev/null +++ b/tests/riscv/rv32i/jal.asm @@ -0,0 +1,164 @@ +.lang riscv32 +.org 0x0 + +jal zero, label_0 +label_0: +jal zero, label_1 +label_1: +jal zero, label_2 +label_2: +jal zero, label_3 +label_3: +jal zero, label_4 +label_4: +jal zero, label_5 +label_5: +jal zero, label_6 +label_6: +jal zero, label_7 +label_7: +jal zero, label_8 +label_8: +jal zero, label_9 +label_9: +jal ra, label_0 +label_0: +jal ra, label_1 +label_1: +jal ra, label_2 +label_2: +jal ra, label_3 +label_3: +jal ra, label_4 +label_4: +jal ra, label_5 +label_5: +jal ra, label_6 +label_6: +jal ra, label_7 +label_7: +jal ra, label_8 +label_8: +jal ra, label_9 +label_9: +jal t0, label_0 +label_0: +jal t0, label_1 +label_1: +jal t0, label_2 +label_2: +jal t0, label_3 +label_3: +jal t0, label_4 +label_4: +jal t0, label_5 +label_5: +jal t0, label_6 +label_6: +jal t0, label_7 +label_7: +jal t0, label_8 +label_8: +jal t0, label_9 +label_9: +jal a0, label_0 +label_0: +jal a0, label_1 +label_1: +jal a0, label_2 +label_2: +jal a0, label_3 +label_3: +jal a0, label_4 +label_4: +jal a0, label_5 +label_5: +jal a0, label_6 +label_6: +jal a0, label_7 +label_7: +jal a0, label_8 +label_8: +jal a0, label_9 +label_9: +jal a5, label_0 +label_0: +jal a5, label_1 +label_1: +jal a5, label_2 +label_2: +jal a5, label_3 +label_3: +jal a5, label_4 +label_4: +jal a5, label_5 +label_5: +jal a5, label_6 +label_6: +jal a5, label_7 +label_7: +jal a5, label_8 +label_8: +jal a5, label_9 +label_9: +jal s4, label_0 +label_0: +jal s4, label_1 +label_1: +jal s4, label_2 +label_2: +jal s4, label_3 +label_3: +jal s4, label_4 +label_4: +jal s4, label_5 +label_5: +jal s4, label_6 +label_6: +jal s4, label_7 +label_7: +jal s4, label_8 +label_8: +jal s4, label_9 +label_9: +jal s9, label_0 +label_0: +jal s9, label_1 +label_1: +jal s9, label_2 +label_2: +jal s9, label_3 +label_3: +jal s9, label_4 +label_4: +jal s9, label_5 +label_5: +jal s9, label_6 +label_6: +jal s9, label_7 +label_7: +jal s9, label_8 +label_8: +jal s9, label_9 +label_9: +jal t6, label_0 +label_0: +jal t6, label_1 +label_1: +jal t6, label_2 +label_2: +jal t6, label_3 +label_3: +jal t6, label_4 +label_4: +jal t6, label_5 +label_5: +jal t6, label_6 +label_6: +jal t6, label_7 +label_7: +jal t6, label_8 +label_8: +jal t6, label_9 +label_9: + diff --git a/tests/riscv/rv32i/jal.bin b/tests/riscv/rv32i/jal.bin new file mode 100644 index 0000000000000000000000000000000000000000..98671f6cb0e2d4b169829568931f2c5b9588dcf3 GIT binary patch literal 320 zcmWN=fks1N7y!`EwboqMHZwCb^UEYjk|arzBr{1SNs=Tn2b2xRRb{(l} z&%OhPjvPBN<%q(DOhg6x*Kk~<+eNSy63(Jc{vU} z^4JqkJ#*&Vb1&*LE?s!#wKv{+=e-X;<|>|i_QhAXf`0>}j+(}_!!=^1u FtAFkpP@ez* literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/jal.disasm b/tests/riscv/rv32i/jal.disasm new file mode 100644 index 0000000..830c2db --- /dev/null +++ b/tests/riscv/rv32i/jal.disasm @@ -0,0 +1,80 @@ +jal zero, #284 +jal zero, #288 +jal zero, #292 +jal zero, #296 +jal zero, #300 +jal zero, #304 +jal zero, #308 +jal zero, #312 +jal zero, #316 +jal zero, #320 +jal ra, #4 +jal ra, #8 +jal ra, #12 +jal ra, #16 +jal ra, #20 +jal ra, #24 +jal ra, #28 +jal ra, #32 +jal ra, #36 +jal ra, #40 +jal t0, #44 +jal t0, #48 +jal t0, #52 +jal t0, #56 +jal t0, #60 +jal t0, #64 +jal t0, #68 +jal t0, #72 +jal t0, #76 +jal t0, #80 +jal a0, #84 +jal a0, #88 +jal a0, #92 +jal a0, #96 +jal a0, #100 +jal a0, #104 +jal a0, #108 +jal a0, #112 +jal a0, #116 +jal a0, #120 +jal a5, #124 +jal a5, #128 +jal a5, #132 +jal a5, #136 +jal a5, #140 +jal a5, #144 +jal a5, #148 +jal a5, #152 +jal a5, #156 +jal a5, #160 +jal s4, #164 +jal s4, #168 +jal s4, #172 +jal s4, #176 +jal s4, #180 +jal s4, #184 +jal s4, #188 +jal s4, #192 +jal s4, #196 +jal s4, #200 +jal s9, #204 +jal s9, #208 +jal s9, #212 +jal s9, #216 +jal s9, #220 +jal s9, #224 +jal s9, #228 +jal s9, #232 +jal s9, #236 +jal s9, #240 +jal t6, #244 +jal t6, #248 +jal t6, #252 +jal t6, #256 +jal t6, #260 +jal t6, #264 +jal t6, #268 +jal t6, #272 +jal t6, #276 +jal t6, #280 diff --git a/tests/riscv/rv32i/jalr.asm b/tests/riscv/rv32i/jalr.asm new file mode 100644 index 0000000..56cad99 --- /dev/null +++ b/tests/riscv/rv32i/jalr.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +jalr zero, zero, #-2047 +jalr zero, zero, #-1024 +jalr zero, zero, #-512 +jalr zero, zero, #-256 +jalr zero, zero, #-128 +jalr zero, zero, #-64 +jalr zero, zero, #-32 +jalr zero, zero, #-16 +jalr zero, zero, #-8 +jalr zero, zero, #-4 +jalr zero, zero, #-2 +jalr zero, zero, #-1 +jalr zero, zero, #0 +jalr zero, zero, #1 +jalr zero, zero, #2 +jalr zero, zero, #4 +jalr zero, zero, #8 +jalr zero, zero, #16 +jalr zero, zero, #32 +jalr zero, zero, #64 +jalr zero, zero, #128 +jalr zero, zero, #256 +jalr zero, zero, #512 +jalr zero, zero, #1024 +jalr zero, zero, #2047 +jalr zero, ra, #-2047 +jalr zero, ra, #-1024 +jalr zero, ra, #-512 +jalr zero, ra, #-256 +jalr zero, ra, #-128 +jalr zero, ra, #-64 +jalr zero, ra, #-32 +jalr zero, ra, #-16 +jalr zero, ra, #-8 +jalr zero, ra, #-4 +jalr zero, ra, #-2 +jalr zero, ra, #-1 +jalr zero, ra, #0 +jalr zero, ra, #1 +jalr zero, ra, #2 +jalr zero, ra, #4 +jalr zero, ra, #8 +jalr zero, ra, #16 +jalr zero, ra, #32 +jalr zero, ra, #64 +jalr zero, ra, #128 +jalr zero, ra, #256 +jalr zero, ra, #512 +jalr zero, ra, #1024 +jalr zero, ra, #2047 +jalr zero, t0, #-2047 +jalr zero, t0, #-1024 +jalr zero, t0, #-512 +jalr zero, t0, #-256 +jalr zero, t0, #-128 +jalr zero, t0, #-64 +jalr zero, t0, #-32 +jalr zero, t0, #-16 +jalr zero, t0, #-8 +jalr zero, t0, #-4 +jalr zero, t0, #-2 +jalr zero, t0, #-1 +jalr zero, t0, #0 +jalr zero, t0, #1 +jalr zero, t0, #2 +jalr zero, t0, #4 +jalr zero, t0, #8 +jalr zero, t0, #16 +jalr zero, t0, #32 +jalr zero, t0, #64 +jalr zero, t0, #128 +jalr zero, t0, #256 +jalr zero, t0, #512 +jalr zero, t0, #1024 +jalr zero, t0, #2047 +jalr zero, a0, #-2047 +jalr zero, a0, #-1024 +jalr zero, a0, #-512 +jalr zero, a0, #-256 +jalr zero, a0, #-128 +jalr zero, a0, #-64 +jalr zero, a0, #-32 +jalr zero, a0, #-16 +jalr zero, a0, #-8 +jalr zero, a0, #-4 +jalr zero, a0, #-2 +jalr zero, a0, #-1 +jalr zero, a0, #0 +jalr zero, a0, #1 +jalr zero, a0, #2 +jalr zero, a0, #4 +jalr zero, a0, #8 +jalr zero, a0, #16 +jalr zero, a0, #32 +jalr zero, a0, #64 +jalr zero, a0, #128 +jalr zero, a0, #256 +jalr zero, a0, #512 +jalr zero, a0, #1024 +jalr zero, a0, #2047 +jalr zero, a5, #-2047 +jalr zero, a5, #-1024 +jalr zero, a5, #-512 +jalr zero, a5, #-256 +jalr zero, a5, #-128 +jalr zero, a5, #-64 +jalr zero, a5, #-32 +jalr zero, a5, #-16 +jalr zero, a5, #-8 +jalr zero, a5, #-4 +jalr zero, a5, #-2 +jalr zero, a5, #-1 +jalr zero, a5, #0 +jalr zero, a5, #1 +jalr zero, a5, #2 +jalr zero, a5, #4 +jalr zero, a5, #8 +jalr zero, a5, #16 +jalr zero, a5, #32 +jalr zero, a5, #64 +jalr zero, a5, #128 +jalr zero, a5, #256 +jalr zero, a5, #512 +jalr zero, a5, #1024 +jalr zero, a5, #2047 +jalr zero, s4, #-2047 +jalr zero, s4, #-1024 +jalr zero, s4, #-512 +jalr zero, s4, #-256 +jalr zero, s4, #-128 +jalr zero, s4, #-64 +jalr zero, s4, #-32 +jalr zero, s4, #-16 +jalr zero, s4, #-8 +jalr zero, s4, #-4 +jalr zero, s4, #-2 +jalr zero, s4, #-1 +jalr zero, s4, #0 +jalr zero, s4, #1 +jalr zero, s4, #2 +jalr zero, s4, #4 +jalr zero, s4, #8 +jalr zero, s4, #16 +jalr zero, s4, #32 +jalr zero, s4, #64 +jalr zero, s4, #128 +jalr zero, s4, #256 +jalr zero, s4, #512 +jalr zero, s4, #1024 +jalr zero, s4, #2047 +jalr zero, s9, #-2047 +jalr zero, s9, #-1024 +jalr zero, s9, #-512 +jalr zero, s9, #-256 +jalr zero, s9, #-128 +jalr zero, s9, #-64 +jalr zero, s9, #-32 +jalr zero, s9, #-16 +jalr zero, s9, #-8 +jalr zero, s9, #-4 +jalr zero, s9, #-2 +jalr zero, s9, #-1 +jalr zero, s9, #0 +jalr zero, s9, #1 +jalr zero, s9, #2 +jalr zero, s9, #4 +jalr zero, s9, #8 +jalr zero, s9, #16 +jalr zero, s9, #32 +jalr zero, s9, #64 +jalr zero, s9, #128 +jalr zero, s9, #256 +jalr zero, s9, #512 +jalr zero, s9, #1024 +jalr zero, s9, #2047 +jalr zero, t6, #-2047 +jalr zero, t6, #-1024 +jalr zero, t6, #-512 +jalr zero, t6, #-256 +jalr zero, t6, #-128 +jalr zero, t6, #-64 +jalr zero, t6, #-32 +jalr zero, t6, #-16 +jalr zero, t6, #-8 +jalr zero, t6, #-4 +jalr zero, t6, #-2 +jalr zero, t6, #-1 +jalr zero, t6, #0 +jalr zero, t6, #1 +jalr zero, t6, #2 +jalr zero, t6, #4 +jalr zero, t6, #8 +jalr zero, t6, #16 +jalr zero, t6, #32 +jalr zero, t6, #64 +jalr zero, t6, #128 +jalr zero, t6, #256 +jalr zero, t6, #512 +jalr zero, t6, #1024 +jalr zero, t6, #2047 +jalr ra, zero, #-2047 +jalr ra, zero, #-1024 +jalr ra, zero, #-512 +jalr ra, zero, #-256 +jalr ra, zero, #-128 +jalr ra, zero, #-64 +jalr ra, zero, #-32 +jalr ra, zero, #-16 +jalr ra, zero, #-8 +jalr ra, zero, #-4 +jalr ra, zero, #-2 +jalr ra, zero, #-1 +jalr ra, zero, #0 +jalr ra, zero, #1 +jalr ra, zero, #2 +jalr ra, zero, #4 +jalr ra, zero, #8 +jalr ra, zero, #16 +jalr ra, zero, #32 +jalr ra, zero, #64 +jalr ra, zero, #128 +jalr ra, zero, #256 +jalr ra, zero, #512 +jalr ra, zero, #1024 +jalr ra, zero, #2047 +jalr ra, ra, #-2047 +jalr ra, ra, #-1024 +jalr ra, ra, #-512 +jalr ra, ra, #-256 +jalr ra, ra, #-128 +jalr ra, ra, #-64 +jalr ra, ra, #-32 +jalr ra, ra, #-16 +jalr ra, ra, #-8 +jalr ra, ra, #-4 +jalr ra, ra, #-2 +jalr ra, ra, #-1 +jalr ra, ra, #0 +jalr ra, ra, #1 +jalr ra, ra, #2 +jalr ra, ra, #4 +jalr ra, ra, #8 +jalr ra, ra, #16 +jalr ra, ra, #32 +jalr ra, ra, #64 +jalr ra, ra, #128 +jalr ra, ra, #256 +jalr ra, ra, #512 +jalr ra, ra, #1024 +jalr ra, ra, #2047 +jalr ra, t0, #-2047 +jalr ra, t0, #-1024 +jalr ra, t0, #-512 +jalr ra, t0, #-256 +jalr ra, t0, #-128 +jalr ra, t0, #-64 +jalr ra, t0, #-32 +jalr ra, t0, #-16 +jalr ra, t0, #-8 +jalr ra, t0, #-4 +jalr ra, t0, #-2 +jalr ra, t0, #-1 +jalr ra, t0, #0 +jalr ra, t0, #1 +jalr ra, t0, #2 +jalr ra, t0, #4 +jalr ra, t0, #8 +jalr ra, t0, #16 +jalr ra, t0, #32 +jalr ra, t0, #64 +jalr ra, t0, #128 +jalr ra, t0, #256 +jalr ra, t0, #512 +jalr ra, t0, #1024 +jalr ra, t0, #2047 +jalr ra, a0, #-2047 +jalr ra, a0, #-1024 +jalr ra, a0, #-512 +jalr ra, a0, #-256 +jalr ra, a0, #-128 +jalr ra, a0, #-64 +jalr ra, a0, #-32 +jalr ra, a0, #-16 +jalr ra, a0, #-8 +jalr ra, a0, #-4 +jalr ra, a0, #-2 +jalr ra, a0, #-1 +jalr ra, a0, #0 +jalr ra, a0, #1 +jalr ra, a0, #2 +jalr ra, a0, #4 +jalr ra, a0, #8 +jalr ra, a0, #16 +jalr ra, a0, #32 +jalr ra, a0, #64 +jalr ra, a0, #128 +jalr ra, a0, #256 +jalr ra, a0, #512 +jalr ra, a0, #1024 +jalr ra, a0, #2047 +jalr ra, a5, #-2047 +jalr ra, a5, #-1024 +jalr ra, a5, #-512 +jalr ra, a5, #-256 +jalr ra, a5, #-128 +jalr ra, a5, #-64 +jalr ra, a5, #-32 +jalr ra, a5, #-16 +jalr ra, a5, #-8 +jalr ra, a5, #-4 +jalr ra, a5, #-2 +jalr ra, a5, #-1 +jalr ra, a5, #0 +jalr ra, a5, #1 +jalr ra, a5, #2 +jalr ra, a5, #4 +jalr ra, a5, #8 +jalr ra, a5, #16 +jalr ra, a5, #32 +jalr ra, a5, #64 +jalr ra, a5, #128 +jalr ra, a5, #256 +jalr ra, a5, #512 +jalr ra, a5, #1024 +jalr ra, a5, #2047 +jalr ra, s4, #-2047 +jalr ra, s4, #-1024 +jalr ra, s4, #-512 +jalr ra, s4, #-256 +jalr ra, s4, #-128 +jalr ra, s4, #-64 +jalr ra, s4, #-32 +jalr ra, s4, #-16 +jalr ra, s4, #-8 +jalr ra, s4, #-4 +jalr ra, s4, #-2 +jalr ra, s4, #-1 +jalr ra, s4, #0 +jalr ra, s4, #1 +jalr ra, s4, #2 +jalr ra, s4, #4 +jalr ra, s4, #8 +jalr ra, s4, #16 +jalr ra, s4, #32 +jalr ra, s4, #64 +jalr ra, s4, #128 +jalr ra, s4, #256 +jalr ra, s4, #512 +jalr ra, s4, #1024 +jalr ra, s4, #2047 +jalr ra, s9, #-2047 +jalr ra, s9, #-1024 +jalr ra, s9, #-512 +jalr ra, s9, #-256 +jalr ra, s9, #-128 +jalr ra, s9, #-64 +jalr ra, s9, #-32 +jalr ra, s9, #-16 +jalr ra, s9, #-8 +jalr ra, s9, #-4 +jalr ra, s9, #-2 +jalr ra, s9, #-1 +jalr ra, s9, #0 +jalr ra, s9, #1 +jalr ra, s9, #2 +jalr ra, s9, #4 +jalr ra, s9, #8 +jalr ra, s9, #16 +jalr ra, s9, #32 +jalr ra, s9, #64 +jalr ra, s9, #128 +jalr ra, s9, #256 +jalr ra, s9, #512 +jalr ra, s9, #1024 +jalr ra, s9, #2047 +jalr ra, t6, #-2047 +jalr ra, t6, #-1024 +jalr ra, t6, #-512 +jalr ra, t6, #-256 +jalr ra, t6, #-128 +jalr ra, t6, #-64 +jalr ra, t6, #-32 +jalr ra, t6, #-16 +jalr ra, t6, #-8 +jalr ra, t6, #-4 +jalr ra, t6, #-2 +jalr ra, t6, #-1 +jalr ra, t6, #0 +jalr ra, t6, #1 +jalr ra, t6, #2 +jalr ra, t6, #4 +jalr ra, t6, #8 +jalr ra, t6, #16 +jalr ra, t6, #32 +jalr ra, t6, #64 +jalr ra, t6, #128 +jalr ra, t6, #256 +jalr ra, t6, #512 +jalr ra, t6, #1024 +jalr ra, t6, #2047 +jalr t0, zero, #-2047 +jalr t0, zero, #-1024 +jalr t0, zero, #-512 +jalr t0, zero, #-256 +jalr t0, zero, #-128 +jalr t0, zero, #-64 +jalr t0, zero, #-32 +jalr t0, zero, #-16 +jalr t0, zero, #-8 +jalr t0, zero, #-4 +jalr t0, zero, #-2 +jalr t0, zero, #-1 +jalr t0, zero, #0 +jalr t0, zero, #1 +jalr t0, zero, #2 +jalr t0, zero, #4 +jalr t0, zero, #8 +jalr t0, zero, #16 +jalr t0, zero, #32 +jalr t0, zero, #64 +jalr t0, zero, #128 +jalr t0, zero, #256 +jalr t0, zero, #512 +jalr t0, zero, #1024 +jalr t0, zero, #2047 +jalr t0, ra, #-2047 +jalr t0, ra, #-1024 +jalr t0, ra, #-512 +jalr t0, ra, #-256 +jalr t0, ra, #-128 +jalr t0, ra, #-64 +jalr t0, ra, #-32 +jalr t0, ra, #-16 +jalr t0, ra, #-8 +jalr t0, ra, #-4 +jalr t0, ra, #-2 +jalr t0, ra, #-1 +jalr t0, ra, #0 +jalr t0, ra, #1 +jalr t0, ra, #2 +jalr t0, ra, #4 +jalr t0, ra, #8 +jalr t0, ra, #16 +jalr t0, ra, #32 +jalr t0, ra, #64 +jalr t0, ra, #128 +jalr t0, ra, #256 +jalr t0, ra, #512 +jalr t0, ra, #1024 +jalr t0, ra, #2047 +jalr t0, t0, #-2047 +jalr t0, t0, #-1024 +jalr t0, t0, #-512 +jalr t0, t0, #-256 +jalr t0, t0, #-128 +jalr t0, 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t6, zero, #-32 +jalr t6, zero, #-16 +jalr t6, zero, #-8 +jalr t6, zero, #-4 +jalr t6, zero, #-2 +jalr t6, zero, #-1 +jalr t6, zero, #0 +jalr t6, zero, #1 +jalr t6, zero, #2 +jalr t6, zero, #4 +jalr t6, zero, #8 +jalr t6, zero, #16 +jalr t6, zero, #32 +jalr t6, zero, #64 +jalr t6, zero, #128 +jalr t6, zero, #256 +jalr t6, zero, #512 +jalr t6, zero, #1024 +jalr t6, zero, #2047 +jalr t6, ra, #-2047 +jalr t6, ra, #-1024 +jalr t6, ra, #-512 +jalr t6, ra, #-256 +jalr t6, ra, #-128 +jalr t6, ra, #-64 +jalr t6, ra, #-32 +jalr t6, ra, #-16 +jalr t6, ra, #-8 +jalr t6, ra, #-4 +jalr t6, ra, #-2 +jalr t6, ra, #-1 +jalr t6, ra, #0 +jalr t6, ra, #1 +jalr t6, ra, #2 +jalr t6, ra, #4 +jalr t6, ra, #8 +jalr t6, ra, #16 +jalr t6, ra, #32 +jalr t6, ra, #64 +jalr t6, ra, #128 +jalr t6, ra, #256 +jalr t6, ra, #512 +jalr t6, ra, #1024 +jalr t6, ra, #2047 +jalr t6, t0, #-2047 +jalr t6, t0, #-1024 +jalr t6, t0, #-512 +jalr t6, t0, #-256 +jalr t6, t0, #-128 +jalr t6, t0, #-64 +jalr t6, t0, #-32 +jalr t6, t0, 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t6, a5, #-1 +jalr t6, a5, #0 +jalr t6, a5, #1 +jalr t6, a5, #2 +jalr t6, a5, #4 +jalr t6, a5, #8 +jalr t6, a5, #16 +jalr t6, a5, #32 +jalr t6, a5, #64 +jalr t6, a5, #128 +jalr t6, a5, #256 +jalr t6, a5, #512 +jalr t6, a5, #1024 +jalr t6, a5, #2047 +jalr t6, s4, #-2047 +jalr t6, s4, #-1024 +jalr t6, s4, #-512 +jalr t6, s4, #-256 +jalr t6, s4, #-128 +jalr t6, s4, #-64 +jalr t6, s4, #-32 +jalr t6, s4, #-16 +jalr t6, s4, #-8 +jalr t6, s4, #-4 +jalr t6, s4, #-2 +jalr t6, s4, #-1 +jalr t6, s4, #0 +jalr t6, s4, #1 +jalr t6, s4, #2 +jalr t6, s4, #4 +jalr t6, s4, #8 +jalr t6, s4, #16 +jalr t6, s4, #32 +jalr t6, s4, #64 +jalr t6, s4, #128 +jalr t6, s4, #256 +jalr t6, s4, #512 +jalr t6, s4, #1024 +jalr t6, s4, #2047 +jalr t6, s9, #-2047 +jalr t6, s9, #-1024 +jalr t6, s9, #-512 +jalr t6, s9, #-256 +jalr t6, s9, #-128 +jalr t6, s9, #-64 +jalr t6, s9, #-32 +jalr t6, s9, #-16 +jalr t6, s9, #-8 +jalr t6, s9, #-4 +jalr t6, s9, #-2 +jalr t6, s9, #-1 +jalr t6, s9, #0 +jalr t6, s9, #1 +jalr t6, s9, #2 +jalr t6, s9, #4 +jalr t6, s9, #8 +jalr t6, s9, #16 +jalr t6, s9, #32 +jalr t6, s9, #64 +jalr t6, s9, #128 +jalr t6, s9, #256 +jalr t6, s9, #512 +jalr t6, s9, #1024 +jalr t6, s9, #2047 +jalr t6, t6, #-2047 +jalr t6, t6, #-1024 +jalr t6, t6, #-512 +jalr t6, t6, #-256 +jalr t6, t6, #-128 +jalr t6, t6, #-64 +jalr t6, t6, #-32 +jalr t6, t6, #-16 +jalr t6, t6, #-8 +jalr t6, t6, #-4 +jalr t6, t6, #-2 +jalr t6, t6, #-1 +jalr t6, t6, #0 +jalr t6, t6, #1 +jalr t6, t6, #2 +jalr t6, t6, #4 +jalr t6, t6, #8 +jalr t6, t6, #16 +jalr t6, t6, #32 +jalr t6, t6, #64 +jalr t6, t6, #128 +jalr t6, t6, #256 +jalr t6, t6, #512 +jalr t6, t6, #1024 +jalr t6, t6, #2047 + diff --git a/tests/riscv/rv32i/jalr.bin b/tests/riscv/rv32i/jalr.bin new file mode 100644 index 0000000000000000000000000000000000000000..25dd636734f4a20a19c2614fd91f56350757dbb4 GIT binary patch literal 6400 zcmWmG@unT$8OHJHl4ZphCQ6n1(Je%XkXslbLWEq#zKlH<%VJrqTiQyMD!qkKYN*nq zRF68&=_h}D|4F>(+3%QVzVCHdbe-Pdf(<*SUm@TX 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#0x10 +jalr zero, zero, #0x20 +jalr zero, zero, #0x40 +jalr zero, zero, #0x80 +jalr zero, zero, #0x100 +jalr zero, zero, #0x200 +jalr zero, zero, #0x400 +jalr zero, zero, #0x7ff +jalr zero, ra, #0xfffff801 +jalr zero, ra, #0xfffffc00 +jalr zero, ra, #0xfffffe00 +jalr zero, ra, #0xffffff00 +jalr zero, ra, #0xffffff80 +jalr zero, ra, #0xffffffc0 +jalr zero, ra, #0xffffffe0 +jalr zero, ra, #0xfffffff0 +jalr zero, ra, #0xfffffff8 +jalr zero, ra, #0xfffffffc +jalr zero, ra, #0xfffffffe +jalr zero, ra, #0xffffffff +jalr zero, ra, #0 +jalr zero, ra, #1 +jalr zero, ra, #2 +jalr zero, ra, #4 +jalr zero, ra, #8 +jalr zero, ra, #0x10 +jalr zero, ra, #0x20 +jalr zero, ra, #0x40 +jalr zero, ra, #0x80 +jalr zero, ra, #0x100 +jalr zero, ra, #0x200 +jalr zero, ra, #0x400 +jalr zero, ra, #0x7ff +jalr zero, t0, #0xfffff801 +jalr zero, t0, #0xfffffc00 +jalr zero, t0, #0xfffffe00 +jalr zero, t0, #0xffffff00 +jalr zero, t0, #0xffffff80 +jalr zero, t0, #0xffffffc0 +jalr zero, t0, #0xffffffe0 +jalr zero, t0, #0xfffffff0 +jalr zero, t0, #0xfffffff8 +jalr zero, t0, #0xfffffffc +jalr zero, t0, #0xfffffffe +jalr zero, t0, #0xffffffff +jalr zero, t0, #0 +jalr zero, t0, #1 +jalr zero, t0, #2 +jalr zero, t0, #4 +jalr zero, t0, #8 +jalr zero, t0, #0x10 +jalr zero, t0, #0x20 +jalr zero, t0, #0x40 +jalr zero, t0, #0x80 +jalr zero, t0, #0x100 +jalr zero, t0, #0x200 +jalr zero, t0, #0x400 +jalr zero, t0, #0x7ff +jalr zero, a0, #0xfffff801 +jalr zero, a0, #0xfffffc00 +jalr zero, a0, #0xfffffe00 +jalr zero, a0, #0xffffff00 +jalr zero, a0, #0xffffff80 +jalr zero, a0, #0xffffffc0 +jalr zero, a0, #0xffffffe0 +jalr zero, a0, #0xfffffff0 +jalr zero, a0, #0xfffffff8 +jalr zero, a0, #0xfffffffc +jalr zero, a0, #0xfffffffe +jalr zero, a0, #0xffffffff +jalr zero, a0, #0 +jalr zero, a0, #1 +jalr zero, a0, #2 +jalr zero, a0, #4 +jalr zero, a0, #8 +jalr zero, a0, #0x10 +jalr zero, a0, #0x20 +jalr zero, a0, #0x40 +jalr zero, a0, #0x80 +jalr zero, a0, #0x100 +jalr zero, a0, #0x200 +jalr zero, a0, #0x400 +jalr zero, a0, #0x7ff +jalr zero, a5, #0xfffff801 +jalr zero, a5, #0xfffffc00 +jalr zero, a5, #0xfffffe00 +jalr zero, a5, #0xffffff00 +jalr zero, a5, #0xffffff80 +jalr zero, a5, #0xffffffc0 +jalr zero, a5, #0xffffffe0 +jalr zero, a5, #0xfffffff0 +jalr zero, a5, #0xfffffff8 +jalr zero, a5, #0xfffffffc +jalr zero, a5, #0xfffffffe +jalr zero, a5, #0xffffffff +jalr zero, a5, #0 +jalr zero, a5, #1 +jalr zero, a5, #2 +jalr zero, a5, #4 +jalr zero, a5, #8 +jalr zero, a5, #0x10 +jalr zero, a5, #0x20 +jalr zero, a5, #0x40 +jalr zero, a5, #0x80 +jalr zero, a5, #0x100 +jalr zero, a5, #0x200 +jalr zero, a5, #0x400 +jalr zero, a5, #0x7ff +jalr zero, s4, #0xfffff801 +jalr zero, s4, #0xfffffc00 +jalr zero, s4, #0xfffffe00 +jalr zero, s4, #0xffffff00 +jalr zero, s4, #0xffffff80 +jalr zero, s4, #0xffffffc0 +jalr zero, s4, #0xffffffe0 +jalr zero, s4, #0xfffffff0 +jalr zero, s4, #0xfffffff8 +jalr zero, s4, #0xfffffffc +jalr zero, s4, #0xfffffffe +jalr zero, s4, #0xffffffff +jalr zero, s4, #0 +jalr zero, s4, #1 +jalr zero, s4, #2 +jalr zero, s4, #4 +jalr zero, s4, #8 +jalr zero, s4, #0x10 +jalr zero, s4, #0x20 +jalr zero, s4, #0x40 +jalr zero, s4, #0x80 +jalr zero, s4, #0x100 +jalr zero, s4, #0x200 +jalr zero, s4, #0x400 +jalr zero, s4, #0x7ff +jalr zero, s9, #0xfffff801 +jalr zero, s9, #0xfffffc00 +jalr zero, s9, #0xfffffe00 +jalr zero, s9, #0xffffff00 +jalr zero, s9, #0xffffff80 +jalr zero, s9, #0xffffffc0 +jalr zero, s9, #0xffffffe0 +jalr zero, s9, #0xfffffff0 +jalr zero, s9, #0xfffffff8 +jalr zero, s9, #0xfffffffc +jalr zero, s9, #0xfffffffe +jalr zero, s9, #0xffffffff +jalr zero, s9, #0 +jalr zero, s9, #1 +jalr zero, s9, #2 +jalr zero, s9, #4 +jalr zero, s9, #8 +jalr zero, s9, #0x10 +jalr zero, s9, #0x20 +jalr zero, s9, #0x40 +jalr zero, s9, #0x80 +jalr zero, s9, #0x100 +jalr zero, s9, #0x200 +jalr zero, s9, #0x400 +jalr zero, s9, #0x7ff +jalr zero, t6, #0xfffff801 +jalr zero, t6, #0xfffffc00 +jalr zero, t6, #0xfffffe00 +jalr zero, t6, #0xffffff00 +jalr zero, t6, #0xffffff80 +jalr zero, t6, #0xffffffc0 +jalr zero, t6, #0xffffffe0 +jalr zero, t6, #0xfffffff0 +jalr zero, t6, #0xfffffff8 +jalr zero, t6, #0xfffffffc +jalr zero, t6, #0xfffffffe +jalr zero, t6, #0xffffffff +jalr zero, t6, #0 +jalr zero, t6, #1 +jalr zero, t6, #2 +jalr zero, t6, #4 +jalr zero, t6, #8 +jalr zero, t6, #0x10 +jalr zero, t6, #0x20 +jalr zero, t6, #0x40 +jalr zero, t6, #0x80 +jalr zero, t6, #0x100 +jalr zero, t6, #0x200 +jalr zero, t6, #0x400 +jalr zero, t6, #0x7ff +jalr ra, zero, #0xfffff801 +jalr ra, zero, #0xfffffc00 +jalr ra, zero, #0xfffffe00 +jalr ra, zero, #0xffffff00 +jalr ra, zero, #0xffffff80 +jalr ra, zero, #0xffffffc0 +jalr ra, zero, #0xffffffe0 +jalr ra, zero, #0xfffffff0 +jalr ra, zero, #0xfffffff8 +jalr ra, zero, #0xfffffffc +jalr ra, zero, #0xfffffffe +jalr ra, zero, #0xffffffff +jalr ra, zero, #0 +jalr ra, zero, #1 +jalr ra, zero, #2 +jalr ra, zero, #4 +jalr ra, zero, #8 +jalr ra, zero, #0x10 +jalr ra, zero, #0x20 +jalr ra, zero, #0x40 +jalr ra, zero, #0x80 +jalr ra, zero, #0x100 +jalr ra, zero, #0x200 +jalr ra, zero, #0x400 +jalr ra, zero, #0x7ff +jalr ra, ra, #0xfffff801 +jalr ra, ra, #0xfffffc00 +jalr ra, ra, #0xfffffe00 +jalr ra, ra, #0xffffff00 +jalr ra, ra, #0xffffff80 +jalr ra, ra, #0xffffffc0 +jalr ra, ra, #0xffffffe0 +jalr ra, ra, #0xfffffff0 +jalr ra, ra, #0xfffffff8 +jalr ra, ra, #0xfffffffc +jalr ra, ra, #0xfffffffe +jalr ra, ra, #0xffffffff +jalr ra, ra, #0 +jalr ra, ra, #1 +jalr ra, ra, #2 +jalr ra, ra, #4 +jalr ra, ra, #8 +jalr ra, ra, #0x10 +jalr ra, ra, #0x20 +jalr ra, ra, #0x40 +jalr ra, ra, #0x80 +jalr ra, ra, #0x100 +jalr ra, ra, #0x200 +jalr ra, ra, #0x400 +jalr ra, ra, #0x7ff +jalr ra, t0, #0xfffff801 +jalr ra, t0, #0xfffffc00 +jalr ra, t0, #0xfffffe00 +jalr ra, t0, #0xffffff00 +jalr ra, t0, #0xffffff80 +jalr ra, t0, #0xffffffc0 +jalr ra, t0, #0xffffffe0 +jalr ra, t0, #0xfffffff0 +jalr ra, t0, #0xfffffff8 +jalr ra, t0, #0xfffffffc +jalr ra, t0, #0xfffffffe +jalr ra, t0, #0xffffffff +jalr ra, t0, #0 +jalr ra, t0, #1 +jalr ra, t0, #2 +jalr ra, t0, #4 +jalr ra, t0, #8 +jalr ra, t0, #0x10 +jalr ra, t0, #0x20 +jalr ra, t0, #0x40 +jalr ra, t0, #0x80 +jalr ra, t0, #0x100 +jalr ra, t0, #0x200 +jalr ra, t0, #0x400 +jalr ra, t0, #0x7ff +jalr ra, a0, #0xfffff801 +jalr ra, a0, #0xfffffc00 +jalr ra, a0, #0xfffffe00 +jalr ra, a0, #0xffffff00 +jalr ra, a0, #0xffffff80 +jalr ra, a0, #0xffffffc0 +jalr ra, a0, #0xffffffe0 +jalr ra, a0, #0xfffffff0 +jalr ra, a0, #0xfffffff8 +jalr ra, a0, #0xfffffffc +jalr ra, a0, #0xfffffffe +jalr ra, a0, #0xffffffff +jalr ra, a0, #0 +jalr ra, a0, #1 +jalr ra, a0, #2 +jalr ra, a0, #4 +jalr ra, a0, #8 +jalr ra, a0, #0x10 +jalr ra, a0, #0x20 +jalr ra, a0, #0x40 +jalr ra, a0, #0x80 +jalr ra, a0, #0x100 +jalr ra, a0, #0x200 +jalr ra, a0, #0x400 +jalr ra, a0, #0x7ff +jalr ra, a5, #0xfffff801 +jalr ra, a5, #0xfffffc00 +jalr ra, a5, #0xfffffe00 +jalr ra, a5, #0xffffff00 +jalr ra, a5, #0xffffff80 +jalr ra, a5, #0xffffffc0 +jalr ra, a5, #0xffffffe0 +jalr ra, a5, #0xfffffff0 +jalr ra, a5, #0xfffffff8 +jalr ra, a5, #0xfffffffc +jalr ra, a5, #0xfffffffe +jalr ra, a5, #0xffffffff +jalr ra, a5, #0 +jalr ra, a5, #1 +jalr ra, a5, #2 +jalr ra, a5, #4 +jalr ra, a5, #8 +jalr ra, a5, #0x10 +jalr ra, a5, #0x20 +jalr ra, a5, #0x40 +jalr ra, a5, #0x80 +jalr ra, a5, #0x100 +jalr ra, a5, #0x200 +jalr ra, a5, #0x400 +jalr ra, a5, #0x7ff +jalr ra, s4, #0xfffff801 +jalr ra, s4, #0xfffffc00 +jalr ra, s4, #0xfffffe00 +jalr ra, s4, #0xffffff00 +jalr ra, s4, #0xffffff80 +jalr ra, s4, #0xffffffc0 +jalr ra, s4, #0xffffffe0 +jalr ra, s4, #0xfffffff0 +jalr ra, s4, #0xfffffff8 +jalr ra, s4, #0xfffffffc +jalr ra, s4, #0xfffffffe +jalr ra, s4, #0xffffffff +jalr ra, s4, #0 +jalr ra, s4, #1 +jalr ra, s4, #2 +jalr ra, s4, #4 +jalr ra, s4, #8 +jalr ra, s4, #0x10 +jalr ra, s4, #0x20 +jalr ra, s4, #0x40 +jalr ra, s4, #0x80 +jalr ra, s4, #0x100 +jalr ra, s4, #0x200 +jalr ra, s4, #0x400 +jalr ra, s4, #0x7ff +jalr ra, s9, #0xfffff801 +jalr ra, s9, #0xfffffc00 +jalr ra, s9, #0xfffffe00 +jalr ra, s9, #0xffffff00 +jalr ra, s9, #0xffffff80 +jalr ra, s9, #0xffffffc0 +jalr ra, s9, #0xffffffe0 +jalr ra, s9, #0xfffffff0 +jalr ra, s9, #0xfffffff8 +jalr ra, s9, #0xfffffffc +jalr ra, s9, #0xfffffffe +jalr ra, s9, #0xffffffff +jalr ra, s9, #0 +jalr ra, s9, #1 +jalr ra, s9, #2 +jalr ra, s9, #4 +jalr ra, s9, #8 +jalr ra, s9, #0x10 +jalr ra, s9, #0x20 +jalr ra, s9, #0x40 +jalr ra, s9, #0x80 +jalr ra, s9, #0x100 +jalr ra, s9, #0x200 +jalr ra, s9, #0x400 +jalr ra, s9, #0x7ff +jalr ra, t6, #0xfffff801 +jalr ra, t6, #0xfffffc00 +jalr ra, t6, #0xfffffe00 +jalr ra, t6, #0xffffff00 +jalr ra, t6, #0xffffff80 +jalr ra, t6, #0xffffffc0 +jalr ra, t6, #0xffffffe0 +jalr ra, t6, #0xfffffff0 +jalr ra, t6, #0xfffffff8 +jalr ra, t6, #0xfffffffc +jalr ra, t6, #0xfffffffe +jalr ra, t6, #0xffffffff +jalr ra, t6, #0 +jalr ra, t6, #1 +jalr ra, t6, #2 +jalr ra, t6, #4 +jalr ra, t6, #8 +jalr ra, t6, #0x10 +jalr ra, t6, #0x20 +jalr ra, t6, #0x40 +jalr ra, t6, #0x80 +jalr ra, t6, #0x100 +jalr ra, t6, #0x200 +jalr ra, t6, #0x400 +jalr ra, t6, #0x7ff +jalr t0, zero, #0xfffff801 +jalr t0, zero, #0xfffffc00 +jalr t0, zero, #0xfffffe00 +jalr t0, zero, #0xffffff00 +jalr t0, zero, #0xffffff80 +jalr t0, zero, #0xffffffc0 +jalr t0, zero, #0xffffffe0 +jalr t0, zero, #0xfffffff0 +jalr t0, zero, #0xfffffff8 +jalr t0, zero, #0xfffffffc +jalr t0, zero, #0xfffffffe +jalr t0, zero, #0xffffffff +jalr t0, zero, #0 +jalr t0, zero, #1 +jalr t0, zero, #2 +jalr t0, zero, #4 +jalr t0, zero, #8 +jalr t0, zero, #0x10 +jalr t0, zero, #0x20 +jalr t0, zero, #0x40 +jalr t0, zero, #0x80 +jalr t0, zero, #0x100 +jalr t0, zero, #0x200 +jalr t0, zero, #0x400 +jalr t0, zero, #0x7ff +jalr t0, ra, #0xfffff801 +jalr t0, ra, #0xfffffc00 +jalr t0, ra, #0xfffffe00 +jalr t0, ra, #0xffffff00 +jalr t0, ra, #0xffffff80 +jalr t0, ra, #0xffffffc0 +jalr t0, ra, #0xffffffe0 +jalr t0, ra, #0xfffffff0 +jalr t0, ra, #0xfffffff8 +jalr t0, ra, #0xfffffffc +jalr t0, ra, #0xfffffffe +jalr t0, ra, #0xffffffff +jalr t0, ra, #0 +jalr t0, ra, #1 +jalr t0, ra, #2 +jalr t0, ra, #4 +jalr t0, ra, #8 +jalr t0, ra, #0x10 +jalr t0, ra, #0x20 +jalr t0, ra, #0x40 +jalr t0, ra, #0x80 +jalr t0, ra, #0x100 +jalr t0, ra, #0x200 +jalr t0, ra, #0x400 +jalr t0, ra, #0x7ff +jalr t0, t0, #0xfffff801 +jalr t0, t0, #0xfffffc00 +jalr t0, t0, #0xfffffe00 +jalr t0, t0, #0xffffff00 +jalr t0, t0, #0xffffff80 +jalr t0, t0, #0xffffffc0 +jalr t0, t0, #0xffffffe0 +jalr t0, t0, #0xfffffff0 +jalr t0, t0, #0xfffffff8 +jalr t0, t0, #0xfffffffc +jalr t0, t0, #0xfffffffe +jalr t0, t0, #0xffffffff +jalr t0, t0, #0 +jalr t0, t0, #1 +jalr t0, t0, #2 +jalr t0, t0, #4 +jalr t0, t0, #8 +jalr t0, t0, #0x10 +jalr t0, t0, #0x20 +jalr t0, t0, #0x40 +jalr t0, t0, #0x80 +jalr t0, t0, #0x100 +jalr t0, t0, #0x200 +jalr t0, t0, #0x400 +jalr t0, t0, #0x7ff +jalr t0, a0, #0xfffff801 +jalr t0, a0, #0xfffffc00 +jalr t0, a0, #0xfffffe00 +jalr t0, a0, #0xffffff00 +jalr t0, a0, #0xffffff80 +jalr t0, a0, #0xffffffc0 +jalr t0, a0, #0xffffffe0 +jalr t0, a0, #0xfffffff0 +jalr t0, a0, #0xfffffff8 +jalr t0, a0, #0xfffffffc +jalr t0, a0, #0xfffffffe +jalr t0, a0, #0xffffffff +jalr t0, a0, #0 +jalr t0, a0, #1 +jalr t0, a0, #2 +jalr t0, a0, #4 +jalr t0, a0, #8 +jalr t0, a0, #0x10 +jalr t0, a0, #0x20 +jalr t0, a0, #0x40 +jalr t0, a0, #0x80 +jalr t0, a0, #0x100 +jalr t0, a0, #0x200 +jalr t0, a0, #0x400 +jalr t0, a0, #0x7ff +jalr t0, a5, #0xfffff801 +jalr t0, a5, #0xfffffc00 +jalr t0, a5, #0xfffffe00 +jalr t0, a5, #0xffffff00 +jalr t0, a5, #0xffffff80 +jalr t0, a5, #0xffffffc0 +jalr t0, a5, #0xffffffe0 +jalr t0, a5, #0xfffffff0 +jalr t0, a5, #0xfffffff8 +jalr t0, a5, #0xfffffffc +jalr t0, a5, #0xfffffffe +jalr t0, a5, #0xffffffff +jalr t0, a5, #0 +jalr t0, a5, #1 +jalr t0, a5, #2 +jalr t0, a5, #4 +jalr t0, a5, #8 +jalr t0, a5, #0x10 +jalr t0, a5, #0x20 +jalr t0, a5, #0x40 +jalr t0, a5, #0x80 +jalr t0, a5, #0x100 +jalr t0, a5, #0x200 +jalr t0, a5, #0x400 +jalr t0, a5, #0x7ff +jalr t0, s4, #0xfffff801 +jalr t0, s4, #0xfffffc00 +jalr t0, s4, #0xfffffe00 +jalr t0, s4, #0xffffff00 +jalr t0, s4, #0xffffff80 +jalr t0, s4, #0xffffffc0 +jalr t0, s4, #0xffffffe0 +jalr t0, s4, #0xfffffff0 +jalr t0, s4, #0xfffffff8 +jalr t0, s4, #0xfffffffc +jalr t0, s4, #0xfffffffe +jalr t0, s4, #0xffffffff +jalr t0, s4, #0 +jalr t0, s4, #1 +jalr t0, s4, #2 +jalr t0, s4, #4 +jalr t0, s4, #8 +jalr t0, s4, #0x10 +jalr t0, s4, #0x20 +jalr t0, s4, #0x40 +jalr t0, s4, #0x80 +jalr t0, s4, #0x100 +jalr t0, s4, #0x200 +jalr t0, s4, #0x400 +jalr t0, s4, #0x7ff +jalr t0, s9, #0xfffff801 +jalr t0, s9, #0xfffffc00 +jalr t0, s9, #0xfffffe00 +jalr t0, s9, #0xffffff00 +jalr t0, s9, #0xffffff80 +jalr t0, s9, #0xffffffc0 +jalr t0, s9, #0xffffffe0 +jalr t0, s9, #0xfffffff0 +jalr t0, s9, #0xfffffff8 +jalr t0, s9, #0xfffffffc +jalr t0, s9, #0xfffffffe +jalr t0, s9, #0xffffffff +jalr t0, s9, #0 +jalr t0, s9, #1 +jalr t0, s9, #2 +jalr t0, s9, #4 +jalr t0, s9, #8 +jalr t0, s9, #0x10 +jalr t0, s9, #0x20 +jalr t0, s9, #0x40 +jalr t0, s9, #0x80 +jalr t0, s9, #0x100 +jalr t0, s9, #0x200 +jalr t0, s9, #0x400 +jalr t0, s9, #0x7ff +jalr t0, t6, #0xfffff801 +jalr t0, t6, #0xfffffc00 +jalr t0, t6, #0xfffffe00 +jalr t0, t6, #0xffffff00 +jalr t0, t6, #0xffffff80 +jalr t0, t6, #0xffffffc0 +jalr t0, t6, #0xffffffe0 +jalr t0, t6, #0xfffffff0 +jalr t0, t6, #0xfffffff8 +jalr t0, t6, #0xfffffffc +jalr t0, t6, #0xfffffffe +jalr t0, t6, #0xffffffff +jalr t0, t6, #0 +jalr t0, t6, #1 +jalr t0, t6, #2 +jalr t0, t6, #4 +jalr t0, t6, #8 +jalr t0, t6, #0x10 +jalr t0, t6, #0x20 +jalr t0, t6, #0x40 +jalr t0, t6, #0x80 +jalr t0, t6, #0x100 +jalr t0, t6, #0x200 +jalr t0, t6, #0x400 +jalr t0, t6, #0x7ff +jalr a0, zero, #0xfffff801 +jalr a0, zero, #0xfffffc00 +jalr a0, zero, #0xfffffe00 +jalr a0, zero, #0xffffff00 +jalr a0, zero, #0xffffff80 +jalr a0, zero, #0xffffffc0 +jalr a0, zero, #0xffffffe0 +jalr a0, zero, #0xfffffff0 +jalr a0, zero, #0xfffffff8 +jalr a0, zero, #0xfffffffc +jalr a0, zero, #0xfffffffe +jalr a0, zero, #0xffffffff +jalr a0, zero, #0 +jalr a0, zero, #1 +jalr a0, zero, #2 +jalr a0, zero, #4 +jalr a0, zero, #8 +jalr a0, zero, #0x10 +jalr a0, zero, #0x20 +jalr a0, zero, #0x40 +jalr a0, zero, #0x80 +jalr a0, zero, #0x100 +jalr a0, zero, #0x200 +jalr a0, zero, #0x400 +jalr a0, zero, #0x7ff +jalr a0, ra, #0xfffff801 +jalr a0, ra, #0xfffffc00 +jalr a0, ra, #0xfffffe00 +jalr a0, ra, #0xffffff00 +jalr a0, ra, #0xffffff80 +jalr a0, ra, #0xffffffc0 +jalr a0, ra, #0xffffffe0 +jalr a0, ra, #0xfffffff0 +jalr a0, ra, #0xfffffff8 +jalr a0, ra, #0xfffffffc +jalr a0, ra, #0xfffffffe +jalr a0, ra, #0xffffffff +jalr a0, ra, #0 +jalr a0, ra, #1 +jalr a0, ra, #2 +jalr a0, ra, #4 +jalr a0, ra, #8 +jalr a0, ra, #0x10 +jalr a0, ra, #0x20 +jalr a0, ra, #0x40 +jalr a0, ra, #0x80 +jalr a0, ra, #0x100 +jalr a0, ra, #0x200 +jalr a0, ra, #0x400 +jalr a0, ra, #0x7ff +jalr a0, t0, #0xfffff801 +jalr a0, t0, #0xfffffc00 +jalr a0, t0, #0xfffffe00 +jalr a0, t0, #0xffffff00 +jalr a0, t0, #0xffffff80 +jalr a0, t0, #0xffffffc0 +jalr a0, t0, #0xffffffe0 +jalr a0, t0, #0xfffffff0 +jalr a0, t0, #0xfffffff8 +jalr a0, t0, #0xfffffffc +jalr a0, t0, #0xfffffffe +jalr a0, t0, #0xffffffff +jalr a0, t0, #0 +jalr a0, t0, #1 +jalr a0, t0, #2 +jalr a0, t0, #4 +jalr a0, t0, #8 +jalr a0, t0, #0x10 +jalr a0, t0, #0x20 +jalr a0, t0, #0x40 +jalr a0, t0, #0x80 +jalr a0, t0, #0x100 +jalr a0, t0, #0x200 +jalr a0, t0, #0x400 +jalr a0, t0, #0x7ff +jalr a0, a0, #0xfffff801 +jalr a0, a0, #0xfffffc00 +jalr a0, a0, #0xfffffe00 +jalr a0, a0, #0xffffff00 +jalr a0, a0, #0xffffff80 +jalr a0, a0, #0xffffffc0 +jalr a0, a0, #0xffffffe0 +jalr a0, a0, #0xfffffff0 +jalr a0, a0, #0xfffffff8 +jalr a0, a0, #0xfffffffc +jalr a0, a0, #0xfffffffe +jalr a0, a0, #0xffffffff +jalr a0, a0, #0 +jalr a0, a0, #1 +jalr a0, a0, #2 +jalr a0, a0, #4 +jalr a0, a0, #8 +jalr a0, a0, #0x10 +jalr a0, a0, #0x20 +jalr a0, a0, #0x40 +jalr a0, a0, #0x80 +jalr a0, a0, #0x100 +jalr a0, a0, #0x200 +jalr a0, a0, #0x400 +jalr a0, a0, #0x7ff +jalr a0, a5, #0xfffff801 +jalr a0, a5, #0xfffffc00 +jalr a0, a5, #0xfffffe00 +jalr a0, a5, #0xffffff00 +jalr a0, a5, #0xffffff80 +jalr a0, a5, #0xffffffc0 +jalr a0, a5, #0xffffffe0 +jalr a0, a5, #0xfffffff0 +jalr a0, a5, #0xfffffff8 +jalr a0, a5, #0xfffffffc +jalr a0, a5, #0xfffffffe +jalr a0, a5, #0xffffffff +jalr a0, a5, #0 +jalr a0, a5, #1 +jalr a0, a5, #2 +jalr a0, a5, #4 +jalr a0, a5, #8 +jalr a0, a5, #0x10 +jalr a0, a5, #0x20 +jalr a0, a5, #0x40 +jalr a0, a5, #0x80 +jalr a0, a5, #0x100 +jalr a0, a5, #0x200 +jalr a0, a5, #0x400 +jalr a0, a5, #0x7ff +jalr a0, s4, #0xfffff801 +jalr a0, s4, #0xfffffc00 +jalr a0, s4, #0xfffffe00 +jalr a0, s4, #0xffffff00 +jalr a0, s4, #0xffffff80 +jalr a0, s4, #0xffffffc0 +jalr a0, s4, #0xffffffe0 +jalr a0, s4, #0xfffffff0 +jalr a0, s4, #0xfffffff8 +jalr a0, s4, #0xfffffffc +jalr a0, s4, #0xfffffffe +jalr a0, s4, #0xffffffff +jalr a0, s4, #0 +jalr a0, s4, #1 +jalr a0, s4, #2 +jalr a0, s4, #4 +jalr a0, s4, #8 +jalr a0, s4, #0x10 +jalr a0, s4, #0x20 +jalr a0, s4, #0x40 +jalr a0, s4, #0x80 +jalr a0, s4, #0x100 +jalr a0, s4, #0x200 +jalr a0, s4, #0x400 +jalr a0, s4, #0x7ff +jalr a0, s9, #0xfffff801 +jalr a0, s9, #0xfffffc00 +jalr a0, s9, #0xfffffe00 +jalr a0, s9, #0xffffff00 +jalr a0, s9, #0xffffff80 +jalr a0, s9, #0xffffffc0 +jalr a0, s9, #0xffffffe0 +jalr a0, s9, #0xfffffff0 +jalr a0, s9, #0xfffffff8 +jalr a0, s9, #0xfffffffc +jalr a0, s9, #0xfffffffe +jalr a0, s9, #0xffffffff +jalr a0, s9, #0 +jalr a0, s9, #1 +jalr a0, s9, #2 +jalr a0, s9, #4 +jalr a0, s9, #8 +jalr a0, s9, #0x10 +jalr a0, s9, #0x20 +jalr a0, s9, #0x40 +jalr a0, s9, #0x80 +jalr a0, s9, #0x100 +jalr a0, s9, #0x200 +jalr a0, s9, #0x400 +jalr a0, s9, #0x7ff +jalr a0, t6, #0xfffff801 +jalr a0, t6, #0xfffffc00 +jalr a0, t6, #0xfffffe00 +jalr a0, t6, #0xffffff00 +jalr a0, t6, #0xffffff80 +jalr a0, t6, #0xffffffc0 +jalr a0, t6, #0xffffffe0 +jalr a0, t6, #0xfffffff0 +jalr a0, t6, #0xfffffff8 +jalr a0, t6, #0xfffffffc +jalr a0, t6, #0xfffffffe +jalr a0, t6, #0xffffffff +jalr a0, t6, #0 +jalr a0, t6, #1 +jalr a0, t6, #2 +jalr a0, t6, #4 +jalr a0, t6, #8 +jalr a0, t6, #0x10 +jalr a0, t6, #0x20 +jalr a0, t6, #0x40 +jalr a0, t6, #0x80 +jalr a0, t6, #0x100 +jalr a0, t6, #0x200 +jalr a0, t6, #0x400 +jalr a0, t6, #0x7ff +jalr a5, zero, #0xfffff801 +jalr a5, zero, #0xfffffc00 +jalr a5, zero, #0xfffffe00 +jalr a5, zero, #0xffffff00 +jalr a5, zero, #0xffffff80 +jalr a5, zero, #0xffffffc0 +jalr a5, zero, #0xffffffe0 +jalr a5, zero, #0xfffffff0 +jalr a5, zero, #0xfffffff8 +jalr a5, zero, #0xfffffffc +jalr a5, zero, #0xfffffffe +jalr a5, zero, #0xffffffff +jalr a5, zero, #0 +jalr a5, zero, #1 +jalr a5, zero, #2 +jalr a5, zero, #4 +jalr a5, zero, #8 +jalr a5, zero, #0x10 +jalr a5, zero, #0x20 +jalr a5, zero, #0x40 +jalr a5, zero, #0x80 +jalr a5, zero, #0x100 +jalr a5, zero, #0x200 +jalr a5, zero, #0x400 +jalr a5, zero, #0x7ff +jalr a5, ra, #0xfffff801 +jalr a5, ra, #0xfffffc00 +jalr a5, ra, #0xfffffe00 +jalr a5, ra, #0xffffff00 +jalr a5, ra, #0xffffff80 +jalr a5, ra, #0xffffffc0 +jalr a5, ra, #0xffffffe0 +jalr a5, ra, #0xfffffff0 +jalr a5, ra, #0xfffffff8 +jalr a5, ra, #0xfffffffc +jalr a5, ra, #0xfffffffe +jalr a5, ra, #0xffffffff +jalr a5, ra, #0 +jalr a5, ra, #1 +jalr a5, ra, #2 +jalr a5, ra, #4 +jalr a5, ra, #8 +jalr a5, ra, #0x10 +jalr a5, ra, #0x20 +jalr a5, ra, #0x40 +jalr a5, ra, #0x80 +jalr a5, ra, #0x100 +jalr a5, ra, #0x200 +jalr a5, ra, #0x400 +jalr a5, ra, #0x7ff +jalr a5, t0, #0xfffff801 +jalr a5, t0, #0xfffffc00 +jalr a5, t0, #0xfffffe00 +jalr a5, t0, #0xffffff00 +jalr a5, t0, #0xffffff80 +jalr a5, t0, #0xffffffc0 +jalr a5, t0, #0xffffffe0 +jalr a5, t0, #0xfffffff0 +jalr a5, t0, #0xfffffff8 +jalr a5, t0, #0xfffffffc +jalr a5, t0, #0xfffffffe +jalr a5, t0, #0xffffffff +jalr a5, t0, #0 +jalr a5, t0, #1 +jalr a5, t0, #2 +jalr a5, t0, #4 +jalr a5, t0, #8 +jalr a5, t0, #0x10 +jalr a5, t0, #0x20 +jalr a5, t0, #0x40 +jalr a5, t0, #0x80 +jalr a5, t0, #0x100 +jalr a5, t0, #0x200 +jalr a5, t0, #0x400 +jalr a5, t0, #0x7ff +jalr a5, a0, #0xfffff801 +jalr a5, a0, #0xfffffc00 +jalr a5, a0, #0xfffffe00 +jalr a5, a0, #0xffffff00 +jalr a5, a0, #0xffffff80 +jalr a5, a0, #0xffffffc0 +jalr a5, a0, #0xffffffe0 +jalr a5, a0, #0xfffffff0 +jalr a5, a0, #0xfffffff8 +jalr a5, a0, #0xfffffffc +jalr a5, a0, #0xfffffffe +jalr a5, a0, #0xffffffff +jalr a5, a0, #0 +jalr a5, a0, #1 +jalr a5, a0, #2 +jalr a5, a0, #4 +jalr a5, a0, #8 +jalr a5, a0, #0x10 +jalr a5, a0, #0x20 +jalr a5, a0, #0x40 +jalr a5, a0, #0x80 +jalr a5, a0, #0x100 +jalr a5, a0, #0x200 +jalr a5, a0, #0x400 +jalr a5, a0, #0x7ff +jalr a5, a5, #0xfffff801 +jalr a5, a5, #0xfffffc00 +jalr a5, a5, #0xfffffe00 +jalr a5, a5, #0xffffff00 +jalr a5, a5, #0xffffff80 +jalr a5, a5, #0xffffffc0 +jalr a5, a5, #0xffffffe0 +jalr a5, a5, #0xfffffff0 +jalr a5, a5, #0xfffffff8 +jalr a5, a5, #0xfffffffc +jalr a5, a5, #0xfffffffe +jalr a5, a5, #0xffffffff +jalr a5, a5, #0 +jalr a5, a5, #1 +jalr a5, a5, #2 +jalr a5, a5, #4 +jalr a5, a5, #8 +jalr a5, a5, #0x10 +jalr a5, a5, #0x20 +jalr a5, a5, #0x40 +jalr a5, a5, #0x80 +jalr a5, a5, #0x100 +jalr a5, a5, #0x200 +jalr a5, a5, #0x400 +jalr a5, a5, #0x7ff +jalr a5, s4, #0xfffff801 +jalr a5, s4, #0xfffffc00 +jalr a5, s4, #0xfffffe00 +jalr a5, s4, #0xffffff00 +jalr a5, s4, #0xffffff80 +jalr a5, s4, #0xffffffc0 +jalr a5, s4, #0xffffffe0 +jalr a5, s4, #0xfffffff0 +jalr a5, s4, #0xfffffff8 +jalr a5, s4, #0xfffffffc +jalr a5, s4, #0xfffffffe +jalr a5, s4, #0xffffffff +jalr a5, s4, #0 +jalr a5, s4, #1 +jalr a5, s4, #2 +jalr a5, s4, #4 +jalr a5, s4, #8 +jalr a5, s4, #0x10 +jalr a5, s4, #0x20 +jalr a5, s4, #0x40 +jalr a5, s4, #0x80 +jalr a5, s4, #0x100 +jalr a5, s4, #0x200 +jalr a5, s4, #0x400 +jalr a5, s4, #0x7ff +jalr a5, s9, #0xfffff801 +jalr a5, s9, #0xfffffc00 +jalr a5, s9, #0xfffffe00 +jalr a5, s9, #0xffffff00 +jalr a5, s9, #0xffffff80 +jalr a5, s9, #0xffffffc0 +jalr a5, s9, #0xffffffe0 +jalr a5, s9, #0xfffffff0 +jalr a5, s9, #0xfffffff8 +jalr a5, s9, #0xfffffffc +jalr a5, s9, #0xfffffffe +jalr a5, s9, #0xffffffff +jalr a5, s9, #0 +jalr a5, s9, #1 +jalr a5, s9, #2 +jalr a5, s9, #4 +jalr a5, s9, #8 +jalr a5, s9, #0x10 +jalr a5, s9, #0x20 +jalr a5, s9, #0x40 +jalr a5, s9, #0x80 +jalr a5, s9, #0x100 +jalr a5, s9, #0x200 +jalr a5, s9, #0x400 +jalr a5, s9, #0x7ff +jalr a5, t6, #0xfffff801 +jalr a5, t6, #0xfffffc00 +jalr a5, t6, #0xfffffe00 +jalr a5, t6, #0xffffff00 +jalr a5, t6, #0xffffff80 +jalr a5, t6, #0xffffffc0 +jalr a5, t6, #0xffffffe0 +jalr a5, t6, #0xfffffff0 +jalr a5, t6, #0xfffffff8 +jalr a5, t6, #0xfffffffc +jalr a5, t6, #0xfffffffe +jalr a5, t6, #0xffffffff +jalr a5, t6, #0 +jalr a5, t6, #1 +jalr a5, t6, #2 +jalr a5, t6, #4 +jalr a5, t6, #8 +jalr a5, t6, #0x10 +jalr a5, t6, #0x20 +jalr a5, t6, #0x40 +jalr a5, t6, #0x80 +jalr a5, t6, #0x100 +jalr a5, t6, #0x200 +jalr a5, t6, #0x400 +jalr a5, t6, #0x7ff +jalr s4, zero, #0xfffff801 +jalr s4, zero, #0xfffffc00 +jalr s4, zero, #0xfffffe00 +jalr s4, zero, #0xffffff00 +jalr s4, zero, #0xffffff80 +jalr s4, zero, #0xffffffc0 +jalr s4, zero, #0xffffffe0 +jalr s4, zero, #0xfffffff0 +jalr s4, zero, #0xfffffff8 +jalr s4, zero, #0xfffffffc +jalr s4, zero, #0xfffffffe +jalr s4, zero, #0xffffffff +jalr s4, zero, #0 +jalr s4, zero, #1 +jalr s4, zero, #2 +jalr s4, zero, #4 +jalr s4, zero, #8 +jalr s4, zero, #0x10 +jalr s4, zero, #0x20 +jalr s4, zero, #0x40 +jalr s4, zero, #0x80 +jalr s4, zero, #0x100 +jalr s4, zero, #0x200 +jalr s4, zero, #0x400 +jalr s4, zero, #0x7ff +jalr s4, ra, #0xfffff801 +jalr s4, ra, #0xfffffc00 +jalr s4, ra, #0xfffffe00 +jalr s4, ra, #0xffffff00 +jalr s4, ra, #0xffffff80 +jalr s4, ra, #0xffffffc0 +jalr s4, ra, #0xffffffe0 +jalr s4, ra, #0xfffffff0 +jalr s4, ra, #0xfffffff8 +jalr s4, ra, #0xfffffffc +jalr s4, ra, #0xfffffffe +jalr s4, ra, #0xffffffff +jalr s4, ra, #0 +jalr s4, ra, #1 +jalr s4, ra, #2 +jalr s4, ra, #4 +jalr s4, ra, #8 +jalr s4, ra, #0x10 +jalr s4, ra, #0x20 +jalr s4, ra, #0x40 +jalr s4, ra, #0x80 +jalr s4, ra, #0x100 +jalr s4, ra, #0x200 +jalr s4, ra, #0x400 +jalr s4, ra, #0x7ff +jalr s4, t0, #0xfffff801 +jalr s4, t0, #0xfffffc00 +jalr s4, t0, #0xfffffe00 +jalr s4, t0, #0xffffff00 +jalr s4, t0, #0xffffff80 +jalr s4, t0, #0xffffffc0 +jalr s4, t0, #0xffffffe0 +jalr s4, t0, #0xfffffff0 +jalr s4, t0, #0xfffffff8 +jalr s4, t0, #0xfffffffc +jalr s4, t0, #0xfffffffe +jalr s4, t0, #0xffffffff +jalr s4, t0, #0 +jalr s4, t0, #1 +jalr s4, t0, #2 +jalr s4, t0, #4 +jalr s4, t0, #8 +jalr s4, t0, #0x10 +jalr s4, t0, #0x20 +jalr s4, t0, #0x40 +jalr s4, t0, #0x80 +jalr s4, t0, #0x100 +jalr s4, t0, #0x200 +jalr s4, t0, #0x400 +jalr s4, t0, #0x7ff +jalr s4, a0, #0xfffff801 +jalr s4, a0, #0xfffffc00 +jalr s4, a0, #0xfffffe00 +jalr s4, a0, #0xffffff00 +jalr s4, a0, #0xffffff80 +jalr s4, a0, #0xffffffc0 +jalr s4, a0, #0xffffffe0 +jalr s4, a0, #0xfffffff0 +jalr s4, a0, #0xfffffff8 +jalr s4, a0, #0xfffffffc +jalr s4, a0, #0xfffffffe +jalr s4, a0, #0xffffffff +jalr s4, a0, #0 +jalr s4, a0, #1 +jalr s4, a0, #2 +jalr s4, a0, #4 +jalr s4, a0, #8 +jalr s4, a0, #0x10 +jalr s4, a0, #0x20 +jalr s4, a0, #0x40 +jalr s4, a0, #0x80 +jalr s4, a0, #0x100 +jalr s4, a0, #0x200 +jalr s4, a0, #0x400 +jalr s4, a0, #0x7ff +jalr s4, a5, #0xfffff801 +jalr s4, a5, #0xfffffc00 +jalr s4, a5, #0xfffffe00 +jalr s4, a5, #0xffffff00 +jalr s4, a5, #0xffffff80 +jalr s4, a5, #0xffffffc0 +jalr s4, a5, #0xffffffe0 +jalr s4, a5, #0xfffffff0 +jalr s4, a5, #0xfffffff8 +jalr s4, a5, #0xfffffffc +jalr s4, a5, #0xfffffffe +jalr s4, a5, #0xffffffff +jalr s4, a5, #0 +jalr s4, a5, #1 +jalr s4, a5, #2 +jalr s4, a5, #4 +jalr s4, a5, #8 +jalr s4, a5, #0x10 +jalr s4, a5, #0x20 +jalr s4, a5, #0x40 +jalr s4, a5, #0x80 +jalr s4, a5, #0x100 +jalr s4, a5, #0x200 +jalr s4, a5, #0x400 +jalr s4, a5, #0x7ff +jalr s4, s4, #0xfffff801 +jalr s4, s4, #0xfffffc00 +jalr s4, s4, #0xfffffe00 +jalr s4, s4, #0xffffff00 +jalr s4, s4, #0xffffff80 +jalr s4, s4, #0xffffffc0 +jalr s4, s4, #0xffffffe0 +jalr s4, s4, #0xfffffff0 +jalr s4, s4, #0xfffffff8 +jalr s4, s4, #0xfffffffc +jalr s4, s4, #0xfffffffe +jalr s4, s4, #0xffffffff +jalr s4, s4, #0 +jalr s4, s4, #1 +jalr s4, s4, #2 +jalr s4, s4, #4 +jalr s4, s4, #8 +jalr s4, s4, #0x10 +jalr s4, s4, #0x20 +jalr s4, s4, #0x40 +jalr s4, s4, #0x80 +jalr s4, s4, #0x100 +jalr s4, s4, #0x200 +jalr s4, s4, #0x400 +jalr s4, s4, #0x7ff +jalr s4, s9, #0xfffff801 +jalr s4, s9, #0xfffffc00 +jalr s4, s9, #0xfffffe00 +jalr s4, s9, #0xffffff00 +jalr s4, s9, #0xffffff80 +jalr s4, s9, #0xffffffc0 +jalr s4, s9, #0xffffffe0 +jalr s4, s9, #0xfffffff0 +jalr s4, s9, #0xfffffff8 +jalr s4, s9, #0xfffffffc +jalr s4, s9, #0xfffffffe +jalr s4, s9, #0xffffffff +jalr s4, s9, #0 +jalr s4, s9, #1 +jalr s4, s9, #2 +jalr s4, s9, #4 +jalr s4, s9, #8 +jalr s4, s9, #0x10 +jalr s4, s9, #0x20 +jalr s4, s9, #0x40 +jalr s4, s9, #0x80 +jalr s4, s9, #0x100 +jalr s4, s9, #0x200 +jalr s4, s9, #0x400 +jalr s4, s9, #0x7ff +jalr s4, t6, #0xfffff801 +jalr s4, t6, #0xfffffc00 +jalr s4, t6, #0xfffffe00 +jalr s4, t6, #0xffffff00 +jalr s4, t6, #0xffffff80 +jalr s4, t6, #0xffffffc0 +jalr s4, t6, #0xffffffe0 +jalr s4, t6, #0xfffffff0 +jalr s4, t6, #0xfffffff8 +jalr s4, t6, #0xfffffffc +jalr s4, t6, #0xfffffffe +jalr s4, t6, #0xffffffff +jalr s4, t6, #0 +jalr s4, t6, #1 +jalr s4, t6, #2 +jalr s4, t6, #4 +jalr s4, t6, #8 +jalr s4, t6, #0x10 +jalr s4, t6, #0x20 +jalr s4, t6, #0x40 +jalr s4, t6, #0x80 +jalr s4, t6, #0x100 +jalr s4, t6, #0x200 +jalr s4, t6, #0x400 +jalr s4, t6, #0x7ff +jalr s9, zero, #0xfffff801 +jalr s9, zero, #0xfffffc00 +jalr s9, zero, #0xfffffe00 +jalr s9, zero, #0xffffff00 +jalr s9, zero, #0xffffff80 +jalr s9, zero, #0xffffffc0 +jalr s9, zero, #0xffffffe0 +jalr s9, zero, #0xfffffff0 +jalr s9, zero, #0xfffffff8 +jalr s9, zero, #0xfffffffc +jalr s9, zero, #0xfffffffe +jalr s9, zero, #0xffffffff +jalr s9, zero, #0 +jalr s9, zero, #1 +jalr s9, zero, #2 +jalr s9, zero, #4 +jalr s9, zero, #8 +jalr s9, zero, #0x10 +jalr s9, zero, #0x20 +jalr s9, zero, #0x40 +jalr s9, zero, #0x80 +jalr s9, zero, #0x100 +jalr s9, zero, #0x200 +jalr s9, zero, #0x400 +jalr s9, zero, #0x7ff +jalr s9, ra, #0xfffff801 +jalr s9, ra, #0xfffffc00 +jalr s9, ra, #0xfffffe00 +jalr s9, ra, #0xffffff00 +jalr s9, ra, #0xffffff80 +jalr s9, ra, #0xffffffc0 +jalr s9, ra, #0xffffffe0 +jalr s9, ra, #0xfffffff0 +jalr s9, ra, #0xfffffff8 +jalr s9, ra, #0xfffffffc +jalr s9, ra, #0xfffffffe +jalr s9, ra, #0xffffffff +jalr s9, ra, #0 +jalr s9, ra, #1 +jalr s9, ra, #2 +jalr s9, ra, #4 +jalr s9, ra, #8 +jalr s9, ra, #0x10 +jalr s9, ra, #0x20 +jalr s9, ra, #0x40 +jalr s9, ra, #0x80 +jalr s9, ra, #0x100 +jalr s9, ra, #0x200 +jalr s9, ra, #0x400 +jalr s9, ra, #0x7ff +jalr s9, t0, #0xfffff801 +jalr s9, t0, #0xfffffc00 +jalr s9, t0, #0xfffffe00 +jalr s9, t0, #0xffffff00 +jalr s9, t0, #0xffffff80 +jalr s9, t0, #0xffffffc0 +jalr s9, t0, #0xffffffe0 +jalr s9, t0, #0xfffffff0 +jalr s9, t0, #0xfffffff8 +jalr s9, t0, #0xfffffffc +jalr s9, t0, #0xfffffffe +jalr s9, t0, #0xffffffff +jalr s9, t0, #0 +jalr s9, t0, #1 +jalr s9, t0, #2 +jalr s9, t0, #4 +jalr s9, t0, #8 +jalr s9, t0, #0x10 +jalr s9, t0, #0x20 +jalr s9, t0, #0x40 +jalr s9, t0, #0x80 +jalr s9, t0, #0x100 +jalr s9, t0, #0x200 +jalr s9, t0, #0x400 +jalr s9, t0, #0x7ff +jalr s9, a0, #0xfffff801 +jalr s9, a0, #0xfffffc00 +jalr s9, a0, #0xfffffe00 +jalr s9, a0, #0xffffff00 +jalr s9, a0, #0xffffff80 +jalr s9, a0, #0xffffffc0 +jalr s9, a0, #0xffffffe0 +jalr s9, a0, #0xfffffff0 +jalr s9, a0, #0xfffffff8 +jalr s9, a0, #0xfffffffc +jalr s9, a0, #0xfffffffe +jalr s9, a0, #0xffffffff +jalr s9, a0, #0 +jalr s9, a0, #1 +jalr s9, a0, #2 +jalr s9, a0, #4 +jalr s9, a0, #8 +jalr s9, a0, #0x10 +jalr s9, a0, #0x20 +jalr s9, a0, #0x40 +jalr s9, a0, #0x80 +jalr s9, a0, #0x100 +jalr s9, a0, #0x200 +jalr s9, a0, #0x400 +jalr s9, a0, #0x7ff +jalr s9, a5, #0xfffff801 +jalr s9, a5, #0xfffffc00 +jalr s9, a5, #0xfffffe00 +jalr s9, a5, #0xffffff00 +jalr s9, a5, #0xffffff80 +jalr s9, a5, #0xffffffc0 +jalr s9, a5, #0xffffffe0 +jalr s9, a5, #0xfffffff0 +jalr s9, a5, #0xfffffff8 +jalr s9, a5, #0xfffffffc +jalr s9, a5, #0xfffffffe +jalr s9, a5, #0xffffffff +jalr s9, a5, #0 +jalr s9, a5, #1 +jalr s9, a5, #2 +jalr s9, a5, #4 +jalr s9, a5, #8 +jalr s9, a5, #0x10 +jalr s9, a5, #0x20 +jalr s9, a5, #0x40 +jalr s9, a5, #0x80 +jalr s9, a5, #0x100 +jalr s9, a5, #0x200 +jalr s9, a5, #0x400 +jalr s9, a5, #0x7ff +jalr s9, s4, #0xfffff801 +jalr s9, s4, #0xfffffc00 +jalr s9, s4, #0xfffffe00 +jalr s9, s4, #0xffffff00 +jalr s9, s4, #0xffffff80 +jalr s9, s4, #0xffffffc0 +jalr s9, s4, #0xffffffe0 +jalr s9, s4, #0xfffffff0 +jalr s9, s4, #0xfffffff8 +jalr s9, s4, #0xfffffffc +jalr s9, s4, #0xfffffffe +jalr s9, s4, #0xffffffff +jalr s9, s4, #0 +jalr s9, s4, #1 +jalr s9, s4, #2 +jalr s9, s4, #4 +jalr s9, s4, #8 +jalr s9, s4, #0x10 +jalr s9, s4, #0x20 +jalr s9, s4, #0x40 +jalr s9, s4, #0x80 +jalr s9, s4, #0x100 +jalr s9, s4, #0x200 +jalr s9, s4, #0x400 +jalr s9, s4, #0x7ff +jalr s9, s9, #0xfffff801 +jalr s9, s9, #0xfffffc00 +jalr s9, s9, #0xfffffe00 +jalr s9, s9, #0xffffff00 +jalr s9, s9, #0xffffff80 +jalr s9, s9, #0xffffffc0 +jalr s9, s9, #0xffffffe0 +jalr s9, s9, #0xfffffff0 +jalr s9, s9, #0xfffffff8 +jalr s9, s9, #0xfffffffc +jalr s9, s9, #0xfffffffe +jalr s9, s9, #0xffffffff +jalr s9, s9, #0 +jalr s9, s9, #1 +jalr s9, s9, #2 +jalr s9, s9, #4 +jalr s9, s9, #8 +jalr s9, s9, #0x10 +jalr s9, s9, #0x20 +jalr s9, s9, #0x40 +jalr s9, s9, #0x80 +jalr s9, s9, #0x100 +jalr s9, s9, #0x200 +jalr s9, s9, #0x400 +jalr s9, s9, #0x7ff +jalr s9, t6, #0xfffff801 +jalr s9, t6, #0xfffffc00 +jalr s9, t6, #0xfffffe00 +jalr s9, t6, #0xffffff00 +jalr s9, t6, #0xffffff80 +jalr s9, t6, #0xffffffc0 +jalr s9, t6, #0xffffffe0 +jalr s9, t6, #0xfffffff0 +jalr s9, t6, #0xfffffff8 +jalr s9, t6, #0xfffffffc +jalr s9, t6, #0xfffffffe +jalr s9, t6, #0xffffffff +jalr s9, t6, #0 +jalr s9, t6, #1 +jalr s9, t6, #2 +jalr s9, t6, #4 +jalr s9, t6, #8 +jalr s9, t6, #0x10 +jalr s9, t6, #0x20 +jalr s9, t6, #0x40 +jalr s9, t6, #0x80 +jalr s9, t6, #0x100 +jalr s9, t6, #0x200 +jalr s9, t6, #0x400 +jalr s9, t6, #0x7ff +jalr t6, zero, #0xfffff801 +jalr t6, zero, #0xfffffc00 +jalr t6, zero, #0xfffffe00 +jalr t6, zero, #0xffffff00 +jalr t6, zero, #0xffffff80 +jalr t6, zero, #0xffffffc0 +jalr t6, zero, #0xffffffe0 +jalr t6, zero, #0xfffffff0 +jalr t6, zero, #0xfffffff8 +jalr t6, zero, #0xfffffffc +jalr t6, zero, #0xfffffffe +jalr t6, zero, #0xffffffff +jalr t6, zero, #0 +jalr t6, zero, #1 +jalr t6, zero, #2 +jalr t6, zero, #4 +jalr t6, zero, #8 +jalr t6, zero, #0x10 +jalr t6, zero, #0x20 +jalr t6, zero, #0x40 +jalr t6, zero, #0x80 +jalr t6, zero, #0x100 +jalr t6, zero, #0x200 +jalr t6, zero, #0x400 +jalr t6, zero, #0x7ff +jalr t6, ra, #0xfffff801 +jalr t6, ra, #0xfffffc00 +jalr t6, ra, #0xfffffe00 +jalr t6, ra, #0xffffff00 +jalr t6, ra, #0xffffff80 +jalr t6, ra, #0xffffffc0 +jalr t6, ra, #0xffffffe0 +jalr t6, ra, #0xfffffff0 +jalr t6, ra, #0xfffffff8 +jalr t6, ra, #0xfffffffc +jalr t6, ra, #0xfffffffe +jalr t6, ra, #0xffffffff +jalr t6, ra, #0 +jalr t6, ra, #1 +jalr t6, ra, #2 +jalr t6, ra, #4 +jalr t6, ra, #8 +jalr t6, ra, #0x10 +jalr t6, ra, #0x20 +jalr t6, ra, #0x40 +jalr t6, ra, #0x80 +jalr t6, ra, #0x100 +jalr t6, ra, #0x200 +jalr t6, ra, #0x400 +jalr t6, ra, #0x7ff +jalr t6, t0, #0xfffff801 +jalr t6, t0, #0xfffffc00 +jalr t6, t0, #0xfffffe00 +jalr t6, t0, #0xffffff00 +jalr t6, t0, #0xffffff80 +jalr t6, t0, #0xffffffc0 +jalr t6, t0, #0xffffffe0 +jalr t6, t0, #0xfffffff0 +jalr t6, t0, #0xfffffff8 +jalr t6, t0, #0xfffffffc +jalr t6, t0, #0xfffffffe +jalr t6, t0, #0xffffffff +jalr t6, t0, #0 +jalr t6, t0, #1 +jalr t6, t0, #2 +jalr t6, t0, #4 +jalr t6, t0, #8 +jalr t6, t0, #0x10 +jalr t6, t0, #0x20 +jalr t6, t0, #0x40 +jalr t6, t0, #0x80 +jalr t6, t0, #0x100 +jalr t6, t0, #0x200 +jalr t6, t0, #0x400 +jalr t6, t0, #0x7ff +jalr t6, a0, #0xfffff801 +jalr t6, a0, #0xfffffc00 +jalr t6, a0, #0xfffffe00 +jalr t6, a0, #0xffffff00 +jalr t6, a0, #0xffffff80 +jalr t6, a0, #0xffffffc0 +jalr t6, a0, #0xffffffe0 +jalr t6, a0, #0xfffffff0 +jalr t6, a0, #0xfffffff8 +jalr t6, a0, #0xfffffffc +jalr t6, a0, #0xfffffffe +jalr t6, a0, #0xffffffff +jalr t6, a0, #0 +jalr t6, a0, #1 +jalr t6, a0, #2 +jalr t6, a0, #4 +jalr t6, a0, #8 +jalr t6, a0, #0x10 +jalr t6, a0, #0x20 +jalr t6, a0, #0x40 +jalr t6, a0, #0x80 +jalr t6, a0, #0x100 +jalr t6, a0, #0x200 +jalr t6, a0, #0x400 +jalr t6, a0, #0x7ff +jalr t6, a5, #0xfffff801 +jalr t6, a5, #0xfffffc00 +jalr t6, a5, #0xfffffe00 +jalr t6, a5, #0xffffff00 +jalr t6, a5, #0xffffff80 +jalr t6, a5, #0xffffffc0 +jalr t6, a5, #0xffffffe0 +jalr t6, a5, #0xfffffff0 +jalr t6, a5, #0xfffffff8 +jalr t6, a5, #0xfffffffc +jalr t6, a5, #0xfffffffe +jalr t6, a5, #0xffffffff +jalr t6, a5, #0 +jalr t6, a5, #1 +jalr t6, a5, #2 +jalr t6, a5, #4 +jalr t6, a5, #8 +jalr t6, a5, #0x10 +jalr t6, a5, #0x20 +jalr t6, a5, #0x40 +jalr t6, a5, #0x80 +jalr t6, a5, #0x100 +jalr t6, a5, #0x200 +jalr t6, a5, #0x400 +jalr t6, a5, #0x7ff +jalr t6, s4, #0xfffff801 +jalr t6, s4, #0xfffffc00 +jalr t6, s4, #0xfffffe00 +jalr t6, s4, #0xffffff00 +jalr t6, s4, #0xffffff80 +jalr t6, s4, #0xffffffc0 +jalr t6, s4, #0xffffffe0 +jalr t6, s4, #0xfffffff0 +jalr t6, s4, #0xfffffff8 +jalr t6, s4, #0xfffffffc +jalr t6, s4, #0xfffffffe +jalr t6, s4, #0xffffffff +jalr t6, s4, #0 +jalr t6, s4, #1 +jalr t6, s4, #2 +jalr t6, s4, #4 +jalr t6, s4, #8 +jalr t6, s4, #0x10 +jalr t6, s4, #0x20 +jalr t6, s4, #0x40 +jalr t6, s4, #0x80 +jalr t6, s4, #0x100 +jalr t6, s4, #0x200 +jalr t6, s4, #0x400 +jalr t6, s4, #0x7ff +jalr t6, s9, #0xfffff801 +jalr t6, s9, #0xfffffc00 +jalr t6, s9, #0xfffffe00 +jalr t6, s9, #0xffffff00 +jalr t6, s9, #0xffffff80 +jalr t6, s9, #0xffffffc0 +jalr t6, s9, #0xffffffe0 +jalr t6, s9, #0xfffffff0 +jalr t6, s9, #0xfffffff8 +jalr t6, s9, #0xfffffffc +jalr t6, s9, #0xfffffffe +jalr t6, s9, #0xffffffff +jalr t6, s9, #0 +jalr t6, s9, #1 +jalr t6, s9, #2 +jalr t6, s9, #4 +jalr t6, s9, #8 +jalr t6, s9, #0x10 +jalr t6, s9, #0x20 +jalr t6, s9, #0x40 +jalr t6, s9, #0x80 +jalr t6, s9, #0x100 +jalr t6, s9, #0x200 +jalr t6, s9, #0x400 +jalr t6, s9, #0x7ff +jalr t6, t6, #0xfffff801 +jalr t6, t6, #0xfffffc00 +jalr t6, t6, #0xfffffe00 +jalr t6, t6, #0xffffff00 +jalr t6, t6, #0xffffff80 +jalr t6, t6, #0xffffffc0 +jalr t6, t6, #0xffffffe0 +jalr t6, t6, #0xfffffff0 +jalr t6, t6, #0xfffffff8 +jalr t6, t6, #0xfffffffc +jalr t6, t6, #0xfffffffe +jalr t6, t6, #0xffffffff +jalr t6, t6, #0 +jalr t6, t6, #1 +jalr t6, t6, #2 +jalr t6, t6, #4 +jalr t6, t6, #8 +jalr t6, t6, #0x10 +jalr t6, t6, #0x20 +jalr t6, t6, #0x40 +jalr t6, t6, #0x80 +jalr t6, t6, #0x100 +jalr t6, t6, #0x200 +jalr t6, t6, #0x400 +jalr t6, t6, #0x7ff diff --git a/tests/riscv/rv32i/lb.asm b/tests/riscv/rv32i/lb.asm new file mode 100644 index 0000000..ac9b630 --- /dev/null +++ b/tests/riscv/rv32i/lb.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +lb zero, (#-2047, zero) +lb zero, (#-1024, zero) +lb zero, (#-512, zero) +lb zero, (#-256, zero) +lb zero, (#-128, zero) +lb zero, (#-64, zero) +lb zero, (#-32, zero) +lb zero, (#-16, zero) +lb zero, (#-8, zero) +lb zero, (#-4, zero) +lb zero, (#-2, zero) +lb zero, (#-1, zero) +lb zero, (#0, zero) +lb zero, (#1, zero) +lb zero, (#2, zero) +lb zero, (#4, zero) +lb zero, (#8, zero) +lb zero, (#16, zero) +lb zero, (#32, zero) +lb zero, (#64, zero) +lb zero, (#128, zero) +lb zero, (#256, zero) +lb zero, (#512, zero) +lb zero, (#1024, zero) +lb zero, (#2047, zero) +lb zero, (#-2047, ra) +lb zero, (#-1024, ra) +lb zero, (#-512, ra) +lb zero, (#-256, ra) +lb zero, (#-128, ra) +lb zero, (#-64, ra) +lb zero, (#-32, ra) +lb zero, (#-16, ra) +lb zero, (#-8, ra) +lb zero, (#-4, ra) +lb zero, (#-2, ra) +lb zero, (#-1, ra) +lb zero, (#0, ra) +lb zero, (#1, ra) +lb zero, (#2, ra) +lb zero, (#4, ra) +lb zero, (#8, ra) +lb zero, (#16, ra) +lb zero, (#32, ra) +lb zero, (#64, ra) +lb zero, (#128, ra) +lb zero, (#256, ra) +lb zero, (#512, ra) +lb zero, (#1024, ra) +lb zero, (#2047, ra) +lb zero, (#-2047, t0) +lb zero, (#-1024, t0) +lb zero, (#-512, t0) +lb zero, (#-256, t0) +lb zero, (#-128, t0) +lb zero, (#-64, t0) +lb zero, (#-32, t0) +lb zero, (#-16, t0) +lb zero, (#-8, t0) +lb zero, (#-4, t0) +lb zero, (#-2, t0) +lb zero, (#-1, t0) +lb zero, (#0, t0) +lb zero, (#1, t0) +lb zero, (#2, t0) +lb zero, (#4, t0) +lb zero, (#8, t0) +lb zero, (#16, t0) +lb zero, (#32, t0) +lb zero, (#64, t0) +lb zero, (#128, t0) +lb zero, (#256, t0) +lb zero, (#512, t0) +lb zero, (#1024, t0) +lb zero, (#2047, t0) +lb zero, (#-2047, a0) +lb zero, (#-1024, a0) +lb zero, (#-512, a0) +lb zero, (#-256, a0) +lb zero, (#-128, a0) +lb zero, (#-64, a0) +lb zero, (#-32, a0) +lb zero, (#-16, a0) +lb zero, (#-8, a0) +lb zero, (#-4, a0) +lb zero, (#-2, a0) +lb zero, (#-1, a0) +lb zero, (#0, a0) +lb zero, (#1, a0) +lb zero, (#2, a0) +lb zero, (#4, a0) +lb zero, (#8, a0) +lb zero, (#16, a0) +lb zero, (#32, a0) +lb zero, (#64, a0) +lb zero, (#128, a0) +lb zero, (#256, a0) +lb zero, (#512, a0) +lb zero, (#1024, a0) +lb zero, (#2047, a0) +lb zero, (#-2047, a5) +lb zero, (#-1024, a5) +lb zero, (#-512, a5) +lb zero, (#-256, a5) +lb zero, (#-128, a5) +lb zero, (#-64, a5) +lb zero, (#-32, a5) +lb zero, (#-16, a5) +lb zero, (#-8, a5) +lb zero, (#-4, a5) +lb zero, (#-2, a5) +lb zero, (#-1, a5) +lb zero, (#0, a5) +lb zero, (#1, a5) +lb zero, (#2, a5) +lb zero, (#4, a5) +lb zero, (#8, a5) +lb zero, (#16, a5) +lb zero, (#32, a5) +lb zero, (#64, a5) +lb zero, (#128, a5) +lb zero, (#256, a5) +lb zero, (#512, a5) +lb zero, (#1024, a5) +lb zero, (#2047, a5) +lb zero, (#-2047, s4) +lb zero, (#-1024, s4) +lb zero, (#-512, s4) +lb zero, (#-256, s4) +lb zero, (#-128, s4) +lb zero, (#-64, s4) +lb zero, (#-32, s4) +lb zero, (#-16, s4) +lb zero, (#-8, s4) +lb zero, (#-4, s4) +lb zero, (#-2, s4) +lb zero, (#-1, s4) +lb zero, (#0, s4) +lb zero, (#1, s4) +lb zero, (#2, s4) +lb zero, (#4, s4) +lb zero, (#8, s4) +lb zero, (#16, s4) +lb zero, (#32, s4) +lb zero, (#64, s4) +lb zero, (#128, s4) +lb zero, (#256, s4) +lb zero, (#512, s4) +lb zero, (#1024, s4) +lb zero, (#2047, s4) +lb zero, (#-2047, s9) +lb zero, (#-1024, s9) +lb zero, (#-512, s9) +lb zero, (#-256, s9) +lb zero, (#-128, s9) +lb zero, (#-64, s9) +lb zero, (#-32, s9) +lb zero, (#-16, s9) +lb zero, (#-8, s9) +lb zero, (#-4, s9) +lb zero, (#-2, s9) +lb zero, (#-1, s9) +lb zero, (#0, s9) +lb zero, (#1, s9) +lb zero, (#2, s9) +lb zero, (#4, s9) +lb zero, (#8, s9) +lb zero, (#16, s9) +lb zero, (#32, s9) +lb zero, (#64, s9) +lb zero, (#128, s9) +lb zero, (#256, s9) +lb zero, (#512, s9) +lb zero, (#1024, s9) +lb zero, (#2047, s9) +lb zero, (#-2047, t6) +lb zero, (#-1024, t6) +lb zero, (#-512, t6) +lb zero, (#-256, t6) +lb zero, (#-128, t6) +lb zero, (#-64, t6) +lb zero, (#-32, t6) +lb zero, (#-16, t6) +lb zero, (#-8, t6) +lb zero, (#-4, t6) +lb zero, (#-2, t6) +lb zero, (#-1, t6) +lb zero, (#0, t6) +lb zero, (#1, t6) +lb zero, (#2, t6) +lb zero, (#4, t6) +lb zero, (#8, t6) +lb zero, (#16, t6) +lb zero, (#32, t6) +lb zero, (#64, t6) +lb zero, (#128, t6) +lb zero, (#256, t6) +lb zero, (#512, t6) +lb zero, (#1024, t6) +lb zero, (#2047, t6) +lb ra, (#-2047, zero) +lb ra, (#-1024, zero) +lb ra, (#-512, zero) +lb ra, (#-256, zero) +lb ra, (#-128, zero) +lb ra, (#-64, zero) +lb ra, (#-32, zero) +lb ra, (#-16, zero) +lb ra, (#-8, zero) +lb ra, (#-4, zero) +lb ra, (#-2, zero) +lb ra, (#-1, zero) +lb ra, (#0, zero) +lb ra, (#1, zero) +lb ra, (#2, zero) +lb ra, (#4, zero) +lb ra, (#8, zero) +lb ra, (#16, zero) +lb ra, (#32, zero) +lb ra, (#64, zero) +lb ra, (#128, zero) +lb ra, (#256, zero) +lb ra, (#512, zero) +lb ra, (#1024, zero) +lb ra, (#2047, zero) +lb ra, (#-2047, ra) +lb ra, (#-1024, ra) +lb ra, (#-512, ra) +lb ra, (#-256, ra) +lb ra, (#-128, ra) +lb ra, (#-64, ra) +lb ra, (#-32, ra) +lb ra, (#-16, ra) +lb ra, (#-8, ra) +lb ra, (#-4, ra) +lb ra, (#-2, ra) +lb ra, (#-1, ra) +lb ra, (#0, ra) +lb ra, (#1, ra) +lb ra, (#2, ra) +lb ra, (#4, ra) +lb ra, (#8, ra) +lb ra, (#16, ra) +lb ra, (#32, ra) +lb ra, (#64, ra) +lb ra, (#128, ra) +lb ra, (#256, ra) +lb ra, (#512, ra) +lb ra, (#1024, ra) +lb ra, (#2047, ra) +lb ra, (#-2047, t0) +lb ra, (#-1024, t0) +lb ra, (#-512, t0) +lb ra, (#-256, t0) +lb ra, (#-128, t0) +lb ra, (#-64, t0) +lb ra, (#-32, t0) +lb ra, (#-16, t0) +lb ra, (#-8, t0) +lb ra, (#-4, t0) +lb ra, (#-2, t0) +lb ra, (#-1, t0) +lb ra, (#0, t0) +lb ra, (#1, t0) +lb ra, (#2, t0) +lb ra, (#4, t0) +lb ra, (#8, t0) +lb ra, (#16, t0) +lb ra, (#32, t0) +lb ra, (#64, t0) +lb ra, (#128, t0) +lb ra, (#256, t0) +lb ra, (#512, t0) +lb ra, (#1024, t0) +lb ra, (#2047, t0) +lb ra, (#-2047, a0) +lb ra, (#-1024, a0) +lb ra, (#-512, a0) +lb ra, (#-256, a0) +lb ra, (#-128, a0) +lb ra, (#-64, a0) +lb ra, (#-32, a0) +lb ra, (#-16, a0) +lb ra, (#-8, a0) +lb ra, (#-4, a0) +lb ra, (#-2, a0) +lb ra, (#-1, a0) +lb ra, (#0, a0) +lb ra, (#1, a0) +lb ra, (#2, a0) +lb ra, (#4, a0) +lb ra, (#8, a0) +lb ra, (#16, a0) +lb ra, (#32, a0) +lb ra, (#64, a0) +lb ra, (#128, a0) +lb ra, (#256, a0) +lb ra, (#512, a0) +lb ra, (#1024, a0) +lb ra, (#2047, a0) +lb ra, (#-2047, a5) +lb ra, (#-1024, a5) +lb ra, (#-512, a5) +lb ra, (#-256, a5) +lb ra, (#-128, a5) +lb ra, (#-64, a5) +lb ra, (#-32, a5) +lb ra, (#-16, a5) +lb ra, (#-8, a5) +lb ra, (#-4, a5) +lb ra, (#-2, a5) +lb ra, (#-1, a5) +lb ra, (#0, a5) +lb ra, (#1, a5) +lb ra, (#2, a5) +lb ra, (#4, a5) +lb ra, (#8, a5) +lb ra, (#16, a5) +lb ra, (#32, a5) +lb ra, (#64, a5) +lb ra, (#128, a5) +lb ra, (#256, a5) +lb ra, (#512, a5) +lb ra, (#1024, a5) +lb ra, (#2047, a5) +lb ra, (#-2047, s4) +lb ra, (#-1024, s4) +lb ra, (#-512, s4) +lb ra, (#-256, s4) +lb ra, (#-128, s4) +lb ra, (#-64, s4) +lb ra, (#-32, s4) +lb ra, (#-16, s4) +lb ra, (#-8, s4) +lb ra, (#-4, s4) +lb ra, (#-2, s4) +lb ra, (#-1, s4) +lb ra, (#0, s4) +lb ra, (#1, s4) +lb ra, (#2, s4) +lb ra, (#4, s4) +lb ra, (#8, s4) +lb ra, (#16, s4) +lb ra, (#32, s4) +lb ra, (#64, s4) +lb ra, (#128, s4) +lb ra, (#256, s4) +lb ra, (#512, s4) +lb ra, (#1024, s4) +lb ra, (#2047, s4) +lb ra, (#-2047, s9) +lb ra, (#-1024, s9) +lb ra, (#-512, s9) +lb ra, (#-256, s9) +lb ra, (#-128, s9) +lb ra, (#-64, s9) +lb ra, (#-32, s9) +lb ra, (#-16, s9) +lb ra, (#-8, s9) +lb ra, (#-4, s9) +lb ra, (#-2, s9) +lb ra, (#-1, s9) +lb ra, (#0, s9) +lb ra, (#1, s9) +lb ra, (#2, s9) +lb ra, (#4, s9) +lb ra, (#8, s9) +lb ra, (#16, s9) +lb ra, (#32, s9) +lb ra, (#64, s9) +lb ra, (#128, s9) +lb ra, (#256, s9) +lb ra, (#512, s9) +lb ra, (#1024, s9) +lb ra, (#2047, s9) +lb ra, (#-2047, t6) +lb ra, (#-1024, t6) +lb ra, (#-512, t6) +lb ra, (#-256, t6) +lb ra, (#-128, t6) +lb ra, (#-64, t6) +lb ra, (#-32, t6) +lb ra, (#-16, t6) +lb ra, (#-8, t6) +lb ra, (#-4, t6) +lb ra, (#-2, t6) +lb ra, (#-1, t6) +lb ra, (#0, t6) +lb ra, (#1, t6) +lb ra, (#2, t6) +lb ra, (#4, t6) +lb ra, (#8, t6) +lb ra, (#16, t6) +lb ra, (#32, t6) +lb ra, (#64, t6) +lb ra, (#128, t6) +lb ra, (#256, t6) +lb ra, (#512, t6) +lb ra, (#1024, t6) +lb ra, (#2047, t6) +lb t0, (#-2047, zero) +lb t0, (#-1024, zero) +lb t0, (#-512, zero) +lb t0, (#-256, zero) +lb t0, (#-128, zero) +lb t0, (#-64, zero) +lb t0, (#-32, zero) +lb t0, (#-16, zero) +lb t0, (#-8, zero) +lb t0, (#-4, zero) +lb t0, (#-2, zero) +lb t0, (#-1, zero) +lb t0, (#0, zero) +lb t0, (#1, zero) +lb t0, (#2, zero) +lb t0, (#4, zero) +lb t0, (#8, zero) +lb t0, (#16, zero) +lb t0, (#32, zero) +lb t0, (#64, zero) +lb t0, (#128, zero) +lb t0, (#256, zero) +lb t0, (#512, zero) +lb t0, (#1024, zero) +lb t0, (#2047, zero) +lb t0, (#-2047, ra) +lb t0, (#-1024, ra) +lb t0, (#-512, ra) +lb t0, (#-256, ra) +lb t0, (#-128, ra) +lb t0, (#-64, ra) +lb t0, (#-32, ra) +lb t0, (#-16, ra) +lb t0, (#-8, ra) +lb t0, (#-4, ra) +lb t0, (#-2, ra) +lb t0, (#-1, ra) +lb t0, (#0, ra) +lb t0, (#1, ra) +lb t0, (#2, ra) +lb t0, (#4, ra) +lb t0, (#8, ra) +lb t0, (#16, ra) +lb t0, (#32, ra) +lb t0, (#64, ra) +lb t0, (#128, ra) +lb t0, (#256, ra) +lb t0, (#512, ra) +lb t0, (#1024, ra) +lb t0, (#2047, ra) +lb t0, (#-2047, t0) +lb t0, (#-1024, t0) +lb t0, (#-512, t0) +lb t0, (#-256, t0) +lb t0, (#-128, t0) +lb t0, (#-64, t0) +lb t0, (#-32, t0) +lb t0, (#-16, t0) +lb t0, (#-8, t0) +lb t0, (#-4, t0) +lb t0, (#-2, t0) +lb t0, (#-1, t0) +lb t0, (#0, t0) +lb t0, (#1, t0) +lb t0, (#2, t0) +lb t0, (#4, t0) +lb t0, (#8, t0) +lb t0, (#16, t0) +lb t0, (#32, t0) +lb t0, (#64, t0) +lb t0, (#128, t0) +lb t0, (#256, t0) +lb t0, (#512, t0) +lb t0, (#1024, t0) +lb t0, (#2047, t0) +lb t0, (#-2047, a0) +lb t0, (#-1024, a0) +lb t0, (#-512, a0) +lb t0, (#-256, a0) +lb t0, (#-128, a0) +lb t0, (#-64, a0) +lb t0, (#-32, a0) +lb t0, (#-16, a0) +lb t0, (#-8, a0) +lb t0, (#-4, a0) +lb t0, (#-2, a0) +lb t0, (#-1, a0) +lb t0, (#0, a0) +lb t0, (#1, a0) +lb t0, (#2, a0) +lb t0, (#4, a0) +lb t0, (#8, a0) +lb t0, (#16, a0) +lb t0, (#32, a0) +lb t0, (#64, a0) +lb t0, (#128, a0) +lb t0, (#256, a0) +lb t0, (#512, a0) +lb t0, (#1024, a0) +lb t0, (#2047, a0) +lb t0, (#-2047, a5) +lb t0, (#-1024, a5) +lb t0, (#-512, a5) +lb t0, (#-256, a5) +lb t0, (#-128, a5) +lb t0, (#-64, a5) +lb t0, (#-32, a5) +lb t0, (#-16, a5) +lb t0, (#-8, a5) +lb t0, (#-4, a5) +lb t0, (#-2, a5) +lb t0, (#-1, a5) +lb t0, (#0, a5) +lb t0, (#1, a5) +lb t0, (#2, a5) +lb t0, (#4, a5) +lb t0, (#8, a5) +lb t0, (#16, a5) +lb t0, (#32, a5) +lb t0, (#64, a5) +lb t0, (#128, a5) +lb t0, (#256, a5) +lb t0, (#512, a5) +lb t0, (#1024, a5) +lb t0, (#2047, a5) +lb t0, (#-2047, s4) +lb t0, (#-1024, s4) +lb t0, (#-512, s4) +lb t0, (#-256, s4) +lb t0, (#-128, s4) +lb t0, (#-64, s4) +lb t0, (#-32, s4) +lb t0, (#-16, s4) +lb t0, (#-8, s4) +lb t0, (#-4, s4) +lb t0, (#-2, s4) +lb t0, (#-1, s4) +lb t0, (#0, s4) +lb t0, (#1, s4) +lb t0, (#2, s4) +lb t0, (#4, s4) +lb t0, (#8, s4) +lb t0, (#16, s4) +lb t0, (#32, s4) +lb t0, (#64, s4) +lb t0, (#128, s4) +lb t0, (#256, s4) +lb t0, (#512, s4) +lb t0, (#1024, s4) +lb t0, (#2047, s4) +lb t0, (#-2047, s9) +lb t0, (#-1024, s9) +lb t0, (#-512, s9) +lb t0, (#-256, s9) +lb t0, (#-128, s9) +lb t0, (#-64, s9) +lb t0, (#-32, s9) +lb t0, (#-16, s9) +lb t0, (#-8, s9) +lb t0, (#-4, s9) +lb t0, (#-2, s9) +lb t0, (#-1, s9) +lb t0, (#0, s9) +lb t0, (#1, s9) +lb t0, (#2, s9) +lb t0, (#4, s9) +lb t0, (#8, s9) +lb t0, (#16, s9) +lb t0, (#32, s9) +lb t0, (#64, s9) +lb t0, (#128, s9) +lb t0, (#256, s9) +lb t0, (#512, s9) +lb t0, (#1024, s9) +lb t0, (#2047, s9) +lb t0, (#-2047, t6) +lb t0, (#-1024, t6) +lb t0, (#-512, t6) +lb t0, (#-256, t6) +lb t0, (#-128, t6) +lb t0, (#-64, t6) +lb t0, (#-32, t6) +lb t0, (#-16, t6) +lb t0, (#-8, t6) +lb t0, (#-4, t6) +lb t0, (#-2, t6) +lb t0, (#-1, t6) +lb t0, (#0, t6) +lb t0, (#1, t6) +lb t0, (#2, t6) +lb t0, (#4, t6) +lb t0, (#8, t6) +lb t0, (#16, t6) +lb t0, (#32, t6) +lb t0, (#64, t6) +lb t0, (#128, t6) +lb t0, (#256, t6) +lb t0, (#512, t6) +lb t0, (#1024, t6) +lb t0, (#2047, t6) +lb a0, (#-2047, zero) +lb a0, (#-1024, zero) +lb a0, (#-512, zero) +lb a0, (#-256, zero) +lb a0, (#-128, zero) +lb a0, (#-64, zero) +lb a0, (#-32, zero) +lb a0, (#-16, zero) +lb a0, (#-8, zero) +lb a0, (#-4, zero) +lb a0, (#-2, zero) +lb a0, (#-1, zero) +lb a0, (#0, zero) +lb a0, (#1, zero) +lb a0, (#2, zero) +lb a0, (#4, zero) +lb a0, (#8, zero) +lb a0, (#16, zero) +lb a0, (#32, zero) +lb a0, (#64, zero) +lb a0, (#128, zero) +lb a0, (#256, zero) +lb a0, (#512, zero) +lb a0, (#1024, zero) +lb a0, (#2047, zero) +lb a0, (#-2047, ra) +lb a0, (#-1024, ra) +lb a0, (#-512, ra) +lb a0, (#-256, ra) +lb a0, (#-128, ra) +lb a0, (#-64, ra) +lb a0, (#-32, ra) +lb a0, (#-16, ra) +lb a0, (#-8, ra) +lb a0, (#-4, ra) +lb a0, (#-2, ra) +lb a0, (#-1, ra) +lb a0, (#0, ra) +lb a0, (#1, ra) +lb a0, (#2, ra) +lb a0, (#4, ra) +lb a0, (#8, ra) +lb a0, (#16, ra) +lb a0, (#32, ra) +lb a0, (#64, ra) +lb a0, (#128, ra) +lb a0, (#256, ra) +lb a0, (#512, ra) +lb a0, (#1024, ra) +lb a0, (#2047, ra) +lb a0, (#-2047, t0) +lb a0, (#-1024, t0) +lb a0, (#-512, t0) +lb a0, (#-256, t0) +lb a0, (#-128, t0) +lb a0, (#-64, t0) +lb a0, (#-32, t0) +lb a0, (#-16, t0) +lb a0, (#-8, t0) +lb a0, (#-4, t0) +lb a0, (#-2, t0) +lb a0, (#-1, t0) +lb a0, (#0, t0) +lb a0, (#1, t0) +lb a0, (#2, t0) +lb a0, (#4, t0) +lb a0, (#8, t0) +lb a0, (#16, t0) +lb a0, (#32, t0) +lb a0, (#64, t0) +lb a0, (#128, t0) +lb a0, (#256, t0) +lb a0, (#512, t0) +lb a0, (#1024, t0) +lb a0, (#2047, t0) +lb a0, (#-2047, a0) +lb a0, (#-1024, a0) +lb a0, (#-512, a0) +lb a0, (#-256, a0) +lb a0, (#-128, a0) +lb a0, (#-64, a0) +lb a0, (#-32, a0) +lb a0, (#-16, a0) +lb a0, (#-8, a0) +lb a0, (#-4, a0) +lb a0, (#-2, a0) +lb a0, (#-1, a0) +lb a0, (#0, a0) +lb a0, (#1, a0) +lb a0, (#2, a0) +lb a0, (#4, a0) +lb a0, (#8, a0) +lb a0, (#16, a0) +lb a0, (#32, a0) +lb a0, (#64, a0) +lb a0, (#128, a0) +lb a0, (#256, a0) +lb a0, (#512, a0) +lb a0, (#1024, a0) +lb a0, (#2047, a0) +lb a0, (#-2047, a5) +lb a0, (#-1024, a5) +lb a0, (#-512, a5) +lb a0, (#-256, a5) +lb a0, (#-128, a5) +lb a0, (#-64, a5) +lb a0, (#-32, a5) +lb a0, (#-16, a5) +lb a0, (#-8, a5) +lb a0, (#-4, a5) +lb a0, (#-2, a5) +lb a0, (#-1, a5) +lb a0, (#0, a5) +lb a0, (#1, a5) +lb a0, (#2, a5) +lb a0, (#4, a5) +lb a0, (#8, a5) +lb a0, (#16, a5) +lb a0, (#32, a5) +lb a0, (#64, a5) +lb a0, (#128, a5) +lb a0, (#256, a5) +lb a0, (#512, a5) +lb a0, (#1024, a5) +lb a0, (#2047, a5) +lb a0, (#-2047, s4) +lb a0, (#-1024, s4) +lb a0, (#-512, s4) +lb a0, (#-256, s4) +lb a0, (#-128, s4) +lb a0, (#-64, s4) +lb a0, (#-32, s4) +lb a0, (#-16, s4) +lb a0, (#-8, s4) +lb a0, (#-4, s4) +lb a0, (#-2, s4) +lb a0, (#-1, s4) +lb a0, (#0, s4) +lb a0, (#1, s4) +lb a0, (#2, s4) +lb a0, (#4, s4) +lb a0, (#8, s4) +lb a0, (#16, s4) +lb a0, (#32, s4) +lb a0, (#64, s4) +lb a0, (#128, s4) +lb a0, (#256, s4) +lb a0, (#512, s4) +lb a0, (#1024, s4) +lb a0, (#2047, s4) +lb a0, (#-2047, s9) +lb a0, (#-1024, s9) +lb a0, (#-512, s9) +lb a0, (#-256, s9) +lb a0, (#-128, s9) +lb a0, (#-64, s9) +lb a0, (#-32, s9) +lb a0, (#-16, s9) +lb a0, (#-8, s9) +lb a0, (#-4, s9) +lb a0, (#-2, s9) +lb a0, (#-1, s9) +lb a0, (#0, s9) +lb a0, (#1, s9) +lb a0, (#2, s9) +lb a0, (#4, s9) +lb a0, (#8, s9) +lb a0, (#16, s9) +lb a0, (#32, s9) +lb a0, (#64, s9) +lb a0, (#128, s9) +lb a0, (#256, s9) +lb a0, (#512, s9) +lb a0, (#1024, s9) +lb a0, (#2047, s9) +lb a0, (#-2047, t6) +lb a0, (#-1024, t6) +lb a0, (#-512, t6) +lb a0, (#-256, t6) +lb a0, (#-128, t6) +lb a0, (#-64, t6) +lb a0, (#-32, t6) +lb a0, (#-16, t6) +lb a0, (#-8, t6) +lb a0, (#-4, t6) +lb a0, (#-2, t6) +lb a0, (#-1, t6) +lb a0, (#0, t6) +lb a0, (#1, t6) +lb a0, (#2, t6) +lb a0, (#4, t6) +lb a0, (#8, t6) +lb a0, (#16, t6) +lb a0, (#32, t6) +lb a0, (#64, t6) +lb a0, (#128, t6) +lb a0, (#256, t6) +lb a0, (#512, t6) +lb a0, (#1024, t6) +lb a0, (#2047, t6) +lb a5, (#-2047, zero) +lb a5, (#-1024, zero) +lb a5, (#-512, zero) +lb a5, (#-256, zero) +lb a5, (#-128, zero) +lb a5, (#-64, zero) +lb a5, (#-32, zero) +lb a5, (#-16, zero) +lb a5, (#-8, zero) +lb a5, (#-4, zero) +lb a5, (#-2, zero) +lb a5, (#-1, zero) +lb a5, (#0, zero) +lb a5, (#1, zero) +lb a5, (#2, zero) +lb a5, (#4, zero) +lb a5, (#8, zero) +lb a5, (#16, zero) +lb a5, (#32, zero) +lb a5, (#64, zero) +lb a5, (#128, zero) +lb a5, (#256, zero) +lb a5, (#512, zero) +lb a5, (#1024, zero) +lb a5, (#2047, zero) +lb a5, (#-2047, ra) +lb a5, (#-1024, ra) +lb a5, (#-512, ra) +lb a5, (#-256, ra) +lb a5, (#-128, ra) +lb a5, (#-64, ra) +lb a5, (#-32, ra) +lb a5, (#-16, ra) +lb a5, (#-8, ra) +lb a5, (#-4, ra) +lb a5, (#-2, ra) +lb a5, (#-1, ra) +lb a5, (#0, ra) +lb a5, (#1, ra) +lb a5, (#2, ra) +lb a5, (#4, ra) +lb a5, (#8, ra) +lb a5, (#16, ra) +lb a5, (#32, ra) +lb a5, (#64, ra) +lb a5, (#128, ra) +lb a5, (#256, ra) +lb a5, (#512, ra) +lb a5, (#1024, ra) +lb a5, (#2047, ra) +lb a5, (#-2047, t0) +lb a5, (#-1024, t0) +lb a5, (#-512, t0) +lb a5, (#-256, t0) +lb a5, (#-128, t0) +lb a5, (#-64, t0) +lb a5, (#-32, t0) +lb a5, (#-16, t0) +lb a5, (#-8, t0) +lb a5, (#-4, t0) +lb a5, (#-2, t0) +lb a5, (#-1, t0) +lb a5, (#0, t0) +lb a5, (#1, t0) +lb a5, (#2, t0) +lb a5, (#4, t0) +lb a5, (#8, t0) +lb a5, (#16, t0) +lb a5, (#32, t0) +lb a5, (#64, t0) +lb a5, (#128, t0) +lb a5, (#256, t0) +lb a5, (#512, t0) +lb a5, (#1024, t0) +lb a5, (#2047, t0) +lb a5, (#-2047, a0) +lb a5, (#-1024, a0) +lb a5, (#-512, a0) +lb a5, (#-256, a0) +lb a5, (#-128, a0) +lb a5, (#-64, a0) +lb a5, (#-32, a0) +lb a5, (#-16, a0) +lb a5, (#-8, a0) +lb a5, (#-4, a0) +lb a5, (#-2, a0) +lb a5, (#-1, a0) +lb a5, (#0, a0) +lb a5, (#1, a0) +lb a5, (#2, a0) +lb a5, (#4, a0) +lb a5, (#8, a0) +lb a5, (#16, a0) +lb a5, (#32, a0) +lb a5, (#64, a0) +lb a5, (#128, a0) +lb a5, (#256, a0) +lb a5, (#512, a0) +lb a5, (#1024, a0) +lb a5, (#2047, a0) +lb a5, (#-2047, a5) +lb a5, (#-1024, a5) +lb a5, (#-512, a5) +lb a5, (#-256, a5) +lb a5, (#-128, a5) +lb a5, (#-64, a5) +lb a5, (#-32, a5) +lb a5, (#-16, a5) +lb a5, (#-8, a5) +lb a5, (#-4, a5) +lb a5, (#-2, a5) +lb a5, (#-1, a5) +lb a5, (#0, a5) +lb a5, (#1, a5) +lb a5, (#2, a5) +lb a5, (#4, a5) +lb a5, (#8, a5) +lb a5, (#16, a5) +lb a5, (#32, a5) +lb a5, (#64, a5) +lb a5, (#128, a5) +lb a5, (#256, a5) +lb a5, (#512, a5) +lb a5, (#1024, a5) +lb a5, (#2047, a5) +lb a5, (#-2047, s4) +lb a5, (#-1024, s4) +lb a5, (#-512, s4) +lb a5, (#-256, s4) +lb a5, (#-128, s4) +lb a5, (#-64, s4) +lb a5, (#-32, s4) +lb a5, (#-16, s4) +lb a5, (#-8, s4) +lb a5, (#-4, s4) +lb a5, (#-2, s4) +lb a5, (#-1, s4) +lb a5, (#0, s4) +lb a5, (#1, s4) +lb a5, (#2, s4) +lb a5, (#4, s4) +lb a5, (#8, s4) +lb a5, (#16, s4) +lb a5, (#32, s4) +lb a5, (#64, s4) +lb a5, (#128, s4) +lb a5, (#256, s4) +lb a5, (#512, s4) +lb a5, (#1024, s4) +lb a5, (#2047, s4) +lb a5, (#-2047, s9) +lb a5, (#-1024, s9) +lb a5, (#-512, s9) +lb a5, (#-256, s9) +lb a5, (#-128, s9) +lb a5, (#-64, s9) +lb a5, (#-32, s9) +lb a5, (#-16, s9) +lb a5, (#-8, s9) +lb a5, (#-4, s9) +lb a5, (#-2, s9) +lb a5, (#-1, s9) +lb a5, (#0, s9) +lb a5, (#1, s9) +lb a5, (#2, s9) +lb a5, (#4, s9) +lb a5, (#8, s9) +lb a5, (#16, s9) +lb a5, (#32, s9) +lb a5, (#64, s9) +lb a5, (#128, s9) +lb a5, (#256, s9) +lb a5, (#512, s9) +lb a5, (#1024, s9) +lb a5, (#2047, s9) +lb a5, (#-2047, t6) +lb a5, (#-1024, t6) +lb a5, (#-512, t6) +lb a5, (#-256, t6) +lb a5, (#-128, t6) +lb a5, (#-64, t6) +lb a5, (#-32, t6) +lb a5, (#-16, t6) +lb a5, (#-8, t6) +lb a5, (#-4, t6) +lb a5, (#-2, t6) +lb a5, (#-1, t6) +lb a5, (#0, t6) +lb a5, (#1, t6) +lb a5, (#2, t6) +lb a5, (#4, t6) +lb a5, (#8, t6) +lb a5, (#16, t6) +lb a5, (#32, t6) +lb a5, (#64, t6) +lb a5, (#128, t6) +lb a5, (#256, t6) +lb a5, (#512, t6) +lb a5, (#1024, t6) +lb a5, (#2047, t6) +lb s4, (#-2047, zero) +lb s4, (#-1024, zero) +lb s4, (#-512, zero) +lb s4, (#-256, zero) +lb s4, (#-128, zero) +lb s4, (#-64, zero) +lb s4, (#-32, zero) +lb s4, (#-16, zero) +lb s4, (#-8, zero) +lb s4, (#-4, zero) +lb s4, (#-2, zero) +lb s4, (#-1, zero) +lb s4, (#0, zero) +lb s4, (#1, zero) +lb s4, (#2, zero) +lb s4, (#4, zero) +lb s4, (#8, zero) +lb s4, (#16, zero) +lb s4, (#32, zero) +lb s4, (#64, zero) +lb s4, (#128, zero) +lb s4, (#256, zero) +lb s4, (#512, zero) +lb s4, (#1024, zero) +lb s4, (#2047, zero) +lb s4, (#-2047, ra) +lb s4, (#-1024, ra) +lb s4, (#-512, ra) +lb s4, (#-256, ra) +lb s4, (#-128, ra) +lb s4, (#-64, ra) +lb s4, (#-32, ra) +lb s4, (#-16, ra) +lb s4, (#-8, ra) +lb s4, (#-4, ra) +lb s4, (#-2, ra) +lb s4, (#-1, ra) +lb s4, (#0, ra) +lb s4, (#1, ra) +lb s4, (#2, ra) +lb s4, (#4, ra) +lb s4, (#8, ra) +lb s4, (#16, ra) +lb s4, (#32, ra) +lb s4, (#64, ra) +lb s4, (#128, ra) +lb s4, (#256, ra) +lb s4, (#512, ra) +lb s4, (#1024, ra) +lb s4, (#2047, ra) +lb s4, (#-2047, t0) +lb s4, (#-1024, t0) +lb s4, (#-512, t0) +lb s4, (#-256, t0) +lb s4, (#-128, t0) +lb s4, (#-64, t0) +lb s4, (#-32, t0) +lb s4, (#-16, t0) +lb s4, (#-8, t0) +lb s4, (#-4, t0) +lb s4, (#-2, t0) +lb s4, (#-1, t0) +lb s4, (#0, t0) +lb s4, (#1, t0) +lb s4, (#2, t0) +lb s4, (#4, t0) +lb s4, (#8, t0) +lb s4, (#16, t0) +lb s4, (#32, t0) +lb s4, (#64, t0) +lb s4, (#128, t0) +lb s4, (#256, t0) +lb s4, (#512, t0) +lb s4, (#1024, t0) +lb s4, (#2047, t0) +lb s4, (#-2047, a0) +lb s4, (#-1024, a0) +lb s4, (#-512, a0) +lb s4, (#-256, a0) +lb s4, (#-128, a0) +lb s4, (#-64, a0) +lb s4, (#-32, a0) +lb s4, (#-16, a0) +lb s4, (#-8, a0) +lb s4, (#-4, a0) +lb s4, (#-2, a0) +lb s4, (#-1, a0) +lb s4, (#0, a0) +lb s4, (#1, a0) +lb s4, (#2, a0) +lb s4, (#4, a0) +lb s4, (#8, a0) +lb s4, (#16, a0) +lb s4, (#32, a0) +lb s4, (#64, a0) +lb s4, (#128, a0) +lb s4, (#256, a0) +lb s4, (#512, a0) +lb s4, (#1024, a0) +lb s4, (#2047, a0) +lb s4, (#-2047, a5) +lb s4, (#-1024, a5) +lb s4, (#-512, a5) +lb s4, (#-256, a5) +lb s4, (#-128, a5) +lb s4, (#-64, a5) +lb s4, (#-32, a5) +lb s4, (#-16, a5) +lb s4, (#-8, a5) +lb s4, (#-4, a5) +lb s4, (#-2, a5) +lb s4, (#-1, a5) +lb s4, (#0, a5) +lb s4, (#1, a5) +lb s4, (#2, a5) +lb s4, (#4, a5) +lb s4, (#8, a5) +lb s4, (#16, a5) +lb s4, (#32, a5) +lb s4, (#64, a5) +lb s4, (#128, a5) +lb s4, (#256, a5) +lb s4, (#512, a5) +lb s4, (#1024, a5) +lb s4, (#2047, a5) +lb s4, (#-2047, s4) +lb s4, (#-1024, s4) +lb s4, (#-512, s4) +lb s4, (#-256, s4) +lb s4, (#-128, s4) +lb s4, (#-64, s4) +lb s4, (#-32, s4) +lb s4, (#-16, s4) +lb s4, (#-8, s4) +lb s4, (#-4, s4) +lb s4, (#-2, s4) +lb s4, (#-1, s4) +lb s4, (#0, s4) +lb s4, (#1, s4) +lb s4, (#2, s4) +lb s4, (#4, s4) +lb s4, (#8, s4) +lb s4, (#16, s4) +lb s4, (#32, s4) +lb s4, (#64, s4) +lb s4, (#128, s4) +lb s4, (#256, s4) +lb s4, (#512, s4) +lb s4, (#1024, s4) +lb s4, (#2047, s4) +lb s4, (#-2047, s9) +lb s4, (#-1024, s9) +lb s4, (#-512, s9) +lb s4, (#-256, s9) +lb s4, (#-128, s9) +lb s4, (#-64, s9) +lb s4, (#-32, s9) +lb s4, (#-16, s9) +lb s4, (#-8, s9) +lb s4, (#-4, s9) +lb s4, (#-2, s9) +lb s4, (#-1, s9) +lb s4, (#0, s9) +lb s4, (#1, s9) +lb s4, (#2, s9) +lb s4, (#4, s9) +lb s4, (#8, s9) +lb s4, (#16, s9) +lb s4, (#32, s9) +lb s4, (#64, s9) +lb s4, (#128, s9) +lb s4, (#256, s9) +lb s4, (#512, s9) +lb s4, (#1024, s9) +lb s4, (#2047, s9) +lb s4, (#-2047, t6) +lb s4, (#-1024, t6) +lb s4, (#-512, t6) +lb s4, (#-256, t6) +lb s4, (#-128, t6) +lb s4, (#-64, t6) +lb s4, (#-32, t6) +lb s4, (#-16, t6) +lb s4, (#-8, t6) +lb s4, (#-4, t6) +lb s4, (#-2, t6) +lb s4, (#-1, t6) +lb s4, (#0, t6) +lb s4, (#1, t6) +lb s4, (#2, t6) +lb s4, (#4, t6) +lb s4, (#8, t6) +lb s4, (#16, t6) +lb s4, (#32, t6) +lb s4, (#64, t6) +lb s4, (#128, t6) +lb s4, (#256, t6) +lb s4, (#512, t6) +lb s4, (#1024, t6) +lb s4, (#2047, t6) +lb s9, (#-2047, zero) +lb s9, (#-1024, zero) +lb s9, (#-512, zero) +lb s9, (#-256, zero) +lb s9, (#-128, zero) +lb s9, (#-64, zero) +lb s9, (#-32, zero) +lb s9, (#-16, zero) +lb s9, (#-8, zero) +lb s9, (#-4, zero) +lb s9, (#-2, zero) +lb s9, (#-1, zero) +lb s9, (#0, zero) +lb s9, (#1, zero) +lb s9, (#2, zero) +lb s9, (#4, zero) +lb s9, (#8, zero) +lb s9, (#16, zero) +lb s9, (#32, zero) +lb s9, (#64, zero) +lb s9, (#128, zero) +lb s9, (#256, zero) +lb s9, (#512, zero) +lb s9, (#1024, zero) +lb s9, (#2047, zero) +lb s9, (#-2047, ra) +lb s9, (#-1024, ra) +lb s9, (#-512, ra) +lb s9, (#-256, ra) +lb s9, (#-128, ra) +lb s9, (#-64, ra) +lb s9, (#-32, ra) +lb s9, (#-16, ra) +lb s9, (#-8, ra) +lb s9, (#-4, ra) +lb s9, (#-2, ra) +lb s9, (#-1, ra) +lb s9, (#0, ra) +lb s9, (#1, ra) +lb s9, (#2, ra) +lb s9, (#4, ra) +lb s9, (#8, ra) +lb s9, (#16, ra) +lb s9, (#32, ra) +lb s9, (#64, ra) +lb s9, (#128, ra) +lb s9, (#256, ra) +lb s9, (#512, ra) +lb s9, (#1024, ra) +lb s9, (#2047, ra) +lb s9, (#-2047, t0) +lb s9, (#-1024, t0) +lb s9, (#-512, t0) +lb s9, (#-256, t0) +lb s9, (#-128, t0) +lb s9, (#-64, t0) +lb s9, (#-32, t0) +lb s9, (#-16, t0) +lb s9, (#-8, t0) +lb s9, (#-4, t0) +lb s9, (#-2, t0) +lb s9, (#-1, t0) +lb s9, (#0, t0) +lb s9, (#1, t0) +lb s9, (#2, t0) +lb s9, (#4, t0) +lb s9, (#8, t0) +lb s9, (#16, t0) +lb s9, (#32, t0) +lb s9, (#64, t0) +lb s9, (#128, t0) +lb s9, (#256, t0) +lb s9, (#512, t0) +lb s9, (#1024, t0) +lb s9, (#2047, t0) +lb s9, (#-2047, a0) +lb s9, (#-1024, a0) +lb s9, (#-512, a0) +lb s9, (#-256, a0) +lb s9, (#-128, a0) +lb s9, (#-64, a0) +lb s9, (#-32, a0) +lb s9, (#-16, a0) +lb s9, (#-8, a0) +lb s9, (#-4, a0) +lb s9, (#-2, a0) +lb s9, (#-1, a0) +lb s9, (#0, a0) +lb s9, (#1, a0) +lb s9, (#2, a0) +lb s9, (#4, a0) +lb s9, (#8, a0) +lb s9, (#16, a0) +lb s9, (#32, a0) +lb s9, (#64, a0) +lb s9, (#128, a0) +lb s9, (#256, a0) +lb s9, (#512, a0) +lb s9, (#1024, a0) +lb s9, (#2047, a0) +lb s9, (#-2047, a5) +lb s9, (#-1024, a5) +lb s9, (#-512, a5) +lb s9, (#-256, a5) +lb s9, (#-128, a5) +lb s9, (#-64, a5) +lb s9, (#-32, a5) +lb s9, (#-16, a5) +lb s9, (#-8, a5) +lb s9, (#-4, a5) +lb s9, (#-2, a5) +lb s9, (#-1, a5) +lb s9, (#0, a5) +lb s9, (#1, a5) +lb s9, (#2, a5) +lb s9, (#4, a5) +lb s9, (#8, a5) +lb s9, (#16, a5) +lb s9, (#32, a5) +lb s9, (#64, a5) +lb s9, (#128, a5) +lb s9, (#256, a5) +lb s9, (#512, a5) +lb s9, (#1024, a5) +lb s9, (#2047, a5) +lb s9, (#-2047, s4) +lb s9, (#-1024, s4) +lb s9, (#-512, s4) +lb s9, (#-256, s4) +lb s9, (#-128, s4) +lb s9, (#-64, s4) +lb s9, (#-32, s4) +lb s9, (#-16, s4) +lb s9, (#-8, s4) +lb s9, (#-4, s4) +lb s9, (#-2, s4) +lb s9, (#-1, s4) +lb s9, (#0, s4) +lb s9, (#1, s4) +lb s9, (#2, s4) +lb s9, (#4, s4) +lb s9, (#8, s4) +lb s9, (#16, s4) +lb s9, (#32, s4) +lb s9, (#64, s4) +lb s9, (#128, s4) +lb s9, (#256, s4) +lb s9, (#512, s4) +lb s9, (#1024, s4) +lb s9, (#2047, s4) +lb s9, (#-2047, s9) +lb s9, (#-1024, s9) +lb s9, (#-512, s9) +lb s9, (#-256, s9) +lb s9, (#-128, s9) +lb s9, (#-64, s9) +lb s9, (#-32, s9) +lb s9, (#-16, s9) +lb s9, (#-8, s9) +lb s9, (#-4, s9) +lb s9, (#-2, s9) +lb s9, (#-1, s9) +lb s9, (#0, s9) +lb s9, (#1, s9) +lb s9, (#2, s9) +lb s9, (#4, s9) +lb s9, (#8, s9) +lb s9, (#16, s9) +lb s9, (#32, s9) +lb s9, (#64, s9) +lb s9, (#128, s9) +lb s9, (#256, s9) +lb s9, (#512, s9) +lb s9, (#1024, s9) +lb s9, (#2047, s9) +lb s9, (#-2047, t6) +lb s9, (#-1024, t6) +lb s9, (#-512, t6) +lb s9, (#-256, t6) +lb s9, (#-128, t6) +lb s9, (#-64, t6) +lb s9, (#-32, t6) +lb s9, (#-16, t6) +lb s9, (#-8, t6) +lb s9, (#-4, t6) +lb s9, (#-2, t6) +lb s9, (#-1, t6) +lb s9, (#0, t6) +lb s9, (#1, t6) +lb s9, (#2, t6) +lb s9, (#4, t6) +lb s9, (#8, t6) +lb s9, (#16, t6) +lb s9, (#32, t6) +lb s9, (#64, t6) +lb s9, (#128, t6) +lb s9, (#256, t6) +lb s9, (#512, t6) +lb s9, (#1024, t6) +lb s9, (#2047, t6) +lb t6, (#-2047, zero) +lb t6, (#-1024, zero) +lb t6, (#-512, zero) +lb t6, (#-256, zero) +lb t6, (#-128, zero) +lb t6, (#-64, zero) +lb t6, (#-32, zero) +lb t6, (#-16, zero) +lb t6, (#-8, zero) +lb t6, (#-4, zero) +lb t6, (#-2, zero) +lb t6, (#-1, zero) +lb t6, (#0, zero) +lb t6, (#1, zero) +lb t6, (#2, zero) +lb t6, (#4, zero) +lb t6, (#8, zero) +lb t6, (#16, zero) +lb t6, (#32, zero) +lb t6, (#64, zero) +lb t6, (#128, zero) +lb t6, (#256, zero) +lb t6, (#512, zero) +lb t6, (#1024, zero) +lb t6, (#2047, zero) +lb t6, (#-2047, ra) +lb t6, (#-1024, ra) +lb t6, (#-512, ra) +lb t6, (#-256, ra) +lb t6, (#-128, ra) +lb t6, (#-64, ra) +lb t6, (#-32, ra) +lb t6, (#-16, ra) +lb t6, (#-8, ra) +lb t6, (#-4, ra) +lb t6, (#-2, ra) +lb t6, (#-1, ra) +lb t6, (#0, ra) +lb t6, (#1, ra) +lb t6, (#2, ra) +lb t6, (#4, ra) +lb t6, (#8, ra) +lb t6, (#16, ra) +lb t6, (#32, ra) +lb t6, (#64, ra) +lb t6, (#128, ra) +lb t6, (#256, ra) +lb t6, (#512, ra) +lb t6, (#1024, ra) +lb t6, (#2047, ra) +lb t6, (#-2047, t0) +lb t6, (#-1024, t0) +lb t6, (#-512, t0) +lb t6, (#-256, t0) +lb t6, (#-128, t0) +lb t6, (#-64, t0) +lb t6, (#-32, t0) +lb t6, (#-16, t0) +lb t6, (#-8, t0) +lb t6, (#-4, t0) +lb t6, (#-2, t0) +lb t6, (#-1, t0) +lb t6, (#0, t0) +lb t6, (#1, t0) +lb t6, (#2, t0) +lb t6, (#4, t0) +lb t6, (#8, t0) +lb t6, (#16, t0) +lb t6, (#32, t0) +lb t6, (#64, t0) +lb t6, (#128, t0) +lb t6, (#256, t0) +lb t6, (#512, t0) +lb t6, (#1024, t0) +lb t6, (#2047, t0) +lb t6, (#-2047, a0) +lb t6, (#-1024, a0) +lb t6, (#-512, a0) +lb t6, (#-256, a0) +lb t6, (#-128, a0) +lb t6, (#-64, a0) +lb t6, (#-32, a0) +lb t6, (#-16, a0) +lb t6, (#-8, a0) +lb t6, (#-4, a0) +lb t6, (#-2, a0) +lb t6, (#-1, a0) +lb t6, (#0, a0) +lb t6, (#1, a0) +lb t6, (#2, a0) +lb t6, (#4, a0) +lb t6, (#8, a0) +lb t6, (#16, a0) +lb t6, (#32, a0) +lb t6, (#64, a0) +lb t6, (#128, a0) +lb t6, (#256, a0) +lb t6, (#512, a0) +lb t6, (#1024, a0) +lb t6, (#2047, a0) +lb t6, (#-2047, a5) +lb t6, (#-1024, a5) +lb t6, (#-512, a5) +lb t6, (#-256, a5) +lb t6, (#-128, a5) +lb t6, (#-64, a5) +lb t6, (#-32, a5) +lb t6, (#-16, a5) +lb t6, (#-8, a5) +lb t6, (#-4, a5) +lb t6, (#-2, a5) +lb t6, (#-1, a5) +lb t6, (#0, a5) +lb t6, (#1, a5) +lb t6, (#2, a5) +lb t6, (#4, a5) +lb t6, (#8, a5) +lb t6, (#16, a5) +lb t6, (#32, a5) +lb t6, (#64, a5) +lb t6, (#128, a5) +lb t6, (#256, a5) +lb t6, (#512, a5) +lb t6, (#1024, a5) +lb t6, (#2047, a5) +lb t6, (#-2047, s4) +lb t6, (#-1024, s4) +lb t6, (#-512, s4) +lb t6, (#-256, s4) +lb t6, (#-128, s4) +lb t6, (#-64, s4) +lb t6, (#-32, s4) +lb t6, (#-16, s4) +lb t6, (#-8, s4) +lb t6, (#-4, s4) +lb t6, (#-2, s4) +lb t6, (#-1, s4) +lb t6, (#0, s4) +lb t6, (#1, s4) +lb t6, (#2, s4) +lb t6, (#4, s4) +lb t6, (#8, s4) +lb t6, (#16, s4) +lb t6, (#32, s4) +lb t6, (#64, s4) +lb t6, (#128, s4) +lb t6, (#256, s4) +lb t6, (#512, s4) +lb t6, (#1024, s4) +lb t6, (#2047, s4) +lb t6, (#-2047, s9) +lb t6, (#-1024, s9) +lb t6, (#-512, s9) +lb t6, (#-256, s9) +lb t6, (#-128, s9) +lb t6, (#-64, s9) +lb t6, (#-32, s9) +lb t6, (#-16, s9) +lb t6, (#-8, s9) +lb t6, (#-4, s9) +lb t6, (#-2, s9) +lb t6, (#-1, s9) +lb t6, (#0, s9) +lb t6, (#1, s9) +lb t6, (#2, s9) +lb t6, (#4, s9) +lb t6, (#8, s9) +lb t6, (#16, s9) +lb t6, (#32, s9) +lb t6, (#64, s9) +lb t6, (#128, s9) +lb t6, (#256, s9) +lb t6, (#512, s9) +lb t6, (#1024, s9) +lb t6, (#2047, s9) +lb t6, (#-2047, t6) +lb t6, (#-1024, t6) +lb t6, (#-512, t6) +lb t6, (#-256, t6) +lb t6, (#-128, t6) +lb t6, (#-64, t6) +lb t6, (#-32, t6) +lb t6, (#-16, t6) +lb t6, (#-8, t6) +lb t6, (#-4, t6) +lb t6, (#-2, t6) +lb t6, (#-1, t6) +lb t6, (#0, t6) +lb t6, (#1, t6) +lb t6, (#2, t6) +lb t6, (#4, t6) +lb t6, (#8, t6) +lb t6, (#16, t6) +lb t6, (#32, t6) +lb t6, (#64, t6) +lb t6, (#128, t6) +lb t6, (#256, t6) +lb t6, (#512, t6) +lb t6, (#1024, t6) +lb t6, (#2047, t6) + diff --git a/tests/riscv/rv32i/lb.bin b/tests/riscv/rv32i/lb.bin new file mode 100644 index 0000000000000000000000000000000000000000..15fc82eb323bae2e5f4e8e64c0b2ab03ea46bff0 GIT binary patch literal 6400 zcmWmG;l>?Jy2kOES}7H+>DX+WZL^mUA;NnKEkua$9@1*nN>PeBrN=OaG0Z8nVGLuK z7{)v7$T(yiG7cGsj6=pDbZFEch+{jDI2qGkA>;D2Otmj3^_@h%(|GyP3x={O55C z=?ND+tK?ZF&nkIV$+M~W9sYuUAq6vdgO8|4o>lU!l4q4XtK?awJ9aaV+wot=?Z{8K zV2^B%Y>#Y@>~}Z(9)HEZk%Jk$#V0gmdt`fLdt`fLd*nNIGml&N@8cGhCtR?{Vvofh zi#-;IW{^Bikd}BikeU z-3`CTU-56`Ukf z!3^HvGddP~EcRIJvDjm=$8yJR=5gxBsUNstkJTQlJyv_He)qs1@ppX38qDB5zF=Ur z$7+w&9;-c8d#rctW*(=0oce(aGBz2Tj7`SoZ%+IP|G+c0UE@D<yq8}w+u!nvW z{V4iT^rPrU(T}1ZML$XoX7CoD(4ZehKZ<@7{V4iT^rPh6%;Svu5tk=iu!nv`{fPPz z^&{#>)Q_kiQ9t4m%-|h9qeDNUenkC<`VsXb>POU%s2@c?%KC&0_Rx=_A4NZkeiZ#E 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(#0xfffff801, zero) +lb zero, (#0xfffffc00, zero) +lb zero, (#0xfffffe00, zero) +lb zero, (#0xffffff00, zero) +lb zero, (#0xffffff80, zero) +lb zero, (#0xffffffc0, zero) +lb zero, (#0xffffffe0, zero) +lb zero, (#0xfffffff0, zero) +lb zero, (#0xfffffff8, zero) +lb zero, (#0xfffffffc, zero) +lb zero, (#0xfffffffe, zero) +lb zero, (#0xffffffff, zero) +lb zero, (#0, zero) +lb zero, (#1, zero) +lb zero, (#2, zero) +lb zero, (#4, zero) +lb zero, (#8, zero) +lb zero, (#0x10, zero) +lb zero, (#0x20, zero) +lb zero, (#0x40, zero) +lb zero, (#0x80, zero) +lb zero, (#0x100, zero) +lb zero, (#0x200, zero) +lb zero, (#0x400, zero) +lb zero, (#0x7ff, zero) +lb zero, (#0xfffff801, ra) +lb zero, (#0xfffffc00, ra) +lb zero, (#0xfffffe00, ra) +lb zero, (#0xffffff00, ra) +lb zero, (#0xffffff80, ra) +lb zero, (#0xffffffc0, ra) +lb zero, (#0xffffffe0, ra) +lb zero, (#0xfffffff0, ra) +lb zero, (#0xfffffff8, ra) +lb zero, (#0xfffffffc, ra) +lb zero, (#0xfffffffe, ra) +lb zero, (#0xffffffff, ra) +lb zero, (#0, ra) +lb zero, (#1, ra) +lb zero, (#2, ra) +lb zero, (#4, ra) +lb zero, (#8, ra) +lb zero, (#0x10, ra) +lb zero, (#0x20, ra) +lb zero, (#0x40, ra) +lb zero, (#0x80, ra) +lb zero, (#0x100, ra) +lb zero, (#0x200, ra) +lb zero, (#0x400, ra) +lb zero, (#0x7ff, ra) +lb zero, (#0xfffff801, t0) +lb zero, (#0xfffffc00, t0) +lb zero, (#0xfffffe00, t0) +lb zero, (#0xffffff00, t0) +lb zero, (#0xffffff80, t0) +lb zero, (#0xffffffc0, t0) +lb zero, (#0xffffffe0, t0) +lb zero, (#0xfffffff0, t0) +lb zero, (#0xfffffff8, t0) +lb zero, (#0xfffffffc, t0) +lb zero, (#0xfffffffe, t0) +lb zero, (#0xffffffff, t0) +lb zero, (#0, t0) +lb zero, (#1, t0) +lb zero, (#2, t0) +lb zero, (#4, t0) +lb zero, (#8, t0) +lb zero, (#0x10, t0) +lb zero, (#0x20, t0) +lb zero, (#0x40, t0) +lb zero, (#0x80, t0) +lb zero, (#0x100, t0) +lb zero, (#0x200, t0) +lb zero, (#0x400, t0) +lb zero, (#0x7ff, t0) +lb zero, (#0xfffff801, a0) +lb zero, (#0xfffffc00, a0) +lb zero, (#0xfffffe00, a0) +lb zero, (#0xffffff00, a0) +lb zero, (#0xffffff80, a0) +lb zero, (#0xffffffc0, a0) +lb zero, (#0xffffffe0, a0) +lb zero, (#0xfffffff0, a0) +lb zero, (#0xfffffff8, a0) +lb zero, (#0xfffffffc, a0) +lb zero, (#0xfffffffe, a0) +lb zero, (#0xffffffff, a0) +lb zero, (#0, a0) +lb zero, (#1, a0) +lb zero, (#2, a0) +lb zero, (#4, a0) +lb zero, (#8, a0) +lb zero, (#0x10, a0) +lb zero, (#0x20, a0) +lb zero, (#0x40, a0) +lb zero, (#0x80, a0) +lb zero, (#0x100, a0) +lb zero, (#0x200, a0) +lb zero, (#0x400, a0) +lb zero, (#0x7ff, a0) +lb zero, (#0xfffff801, a5) +lb zero, (#0xfffffc00, a5) +lb zero, (#0xfffffe00, a5) +lb zero, (#0xffffff00, a5) +lb zero, (#0xffffff80, a5) +lb zero, (#0xffffffc0, a5) +lb zero, (#0xffffffe0, a5) +lb zero, (#0xfffffff0, a5) +lb zero, (#0xfffffff8, a5) +lb zero, (#0xfffffffc, a5) +lb zero, (#0xfffffffe, a5) +lb zero, (#0xffffffff, a5) +lb zero, (#0, a5) +lb zero, (#1, a5) +lb zero, (#2, a5) +lb zero, (#4, a5) +lb zero, (#8, a5) +lb zero, (#0x10, a5) +lb zero, (#0x20, a5) +lb zero, (#0x40, a5) +lb zero, (#0x80, a5) +lb zero, (#0x100, a5) +lb zero, (#0x200, a5) +lb zero, (#0x400, a5) +lb zero, (#0x7ff, a5) +lb zero, (#0xfffff801, s4) +lb zero, (#0xfffffc00, s4) +lb zero, (#0xfffffe00, s4) +lb zero, (#0xffffff00, s4) +lb zero, (#0xffffff80, s4) +lb zero, (#0xffffffc0, s4) +lb zero, (#0xffffffe0, s4) +lb zero, (#0xfffffff0, s4) +lb zero, (#0xfffffff8, s4) +lb zero, (#0xfffffffc, s4) +lb zero, (#0xfffffffe, s4) +lb zero, (#0xffffffff, s4) +lb zero, (#0, s4) +lb zero, (#1, s4) +lb zero, (#2, s4) +lb zero, (#4, s4) +lb zero, (#8, s4) +lb zero, (#0x10, s4) +lb zero, (#0x20, s4) +lb zero, (#0x40, s4) +lb zero, (#0x80, s4) +lb zero, (#0x100, s4) +lb zero, (#0x200, s4) +lb zero, (#0x400, s4) +lb zero, (#0x7ff, s4) +lb zero, (#0xfffff801, s9) +lb zero, (#0xfffffc00, s9) +lb zero, (#0xfffffe00, s9) +lb zero, (#0xffffff00, s9) +lb zero, (#0xffffff80, s9) +lb zero, (#0xffffffc0, s9) +lb zero, (#0xffffffe0, s9) +lb zero, (#0xfffffff0, s9) +lb zero, (#0xfffffff8, s9) +lb zero, (#0xfffffffc, s9) +lb zero, (#0xfffffffe, s9) +lb zero, (#0xffffffff, s9) +lb zero, (#0, s9) +lb zero, (#1, s9) +lb zero, (#2, s9) +lb zero, (#4, s9) +lb zero, (#8, s9) +lb zero, (#0x10, s9) +lb zero, (#0x20, s9) +lb zero, (#0x40, s9) +lb zero, (#0x80, s9) +lb zero, (#0x100, s9) +lb zero, (#0x200, s9) +lb zero, (#0x400, s9) +lb zero, (#0x7ff, s9) +lb zero, (#0xfffff801, t6) +lb zero, (#0xfffffc00, t6) +lb zero, (#0xfffffe00, t6) +lb zero, (#0xffffff00, t6) +lb zero, (#0xffffff80, t6) +lb zero, (#0xffffffc0, t6) +lb zero, (#0xffffffe0, t6) +lb zero, (#0xfffffff0, t6) +lb zero, (#0xfffffff8, t6) +lb zero, (#0xfffffffc, t6) +lb zero, (#0xfffffffe, t6) +lb zero, (#0xffffffff, t6) +lb zero, (#0, t6) +lb zero, (#1, t6) +lb zero, (#2, t6) +lb zero, (#4, t6) +lb zero, (#8, t6) +lb zero, (#0x10, t6) +lb zero, (#0x20, t6) +lb zero, (#0x40, t6) +lb zero, (#0x80, t6) +lb zero, (#0x100, t6) +lb zero, (#0x200, t6) +lb zero, (#0x400, t6) +lb zero, (#0x7ff, t6) +lb ra, (#0xfffff801, zero) +lb ra, (#0xfffffc00, zero) +lb ra, (#0xfffffe00, zero) +lb ra, (#0xffffff00, zero) +lb ra, (#0xffffff80, zero) +lb ra, (#0xffffffc0, zero) +lb ra, (#0xffffffe0, zero) +lb ra, (#0xfffffff0, zero) +lb ra, (#0xfffffff8, zero) +lb ra, (#0xfffffffc, zero) +lb ra, (#0xfffffffe, zero) +lb ra, (#0xffffffff, zero) +lb ra, (#0, zero) +lb ra, (#1, zero) +lb ra, (#2, zero) +lb ra, (#4, zero) +lb ra, (#8, zero) +lb ra, (#0x10, zero) +lb ra, (#0x20, zero) +lb ra, (#0x40, zero) +lb ra, (#0x80, zero) +lb ra, (#0x100, zero) +lb ra, (#0x200, zero) +lb ra, (#0x400, zero) +lb ra, (#0x7ff, zero) +lb ra, (#0xfffff801, ra) +lb ra, (#0xfffffc00, ra) +lb ra, (#0xfffffe00, ra) +lb ra, (#0xffffff00, ra) +lb ra, (#0xffffff80, ra) +lb ra, (#0xffffffc0, ra) +lb ra, (#0xffffffe0, ra) +lb ra, (#0xfffffff0, ra) +lb ra, (#0xfffffff8, ra) +lb ra, (#0xfffffffc, ra) +lb ra, (#0xfffffffe, ra) +lb ra, (#0xffffffff, ra) +lb ra, (#0, ra) +lb ra, (#1, ra) +lb ra, (#2, ra) +lb ra, (#4, ra) +lb ra, (#8, ra) +lb ra, (#0x10, ra) +lb ra, (#0x20, ra) +lb ra, (#0x40, ra) +lb ra, (#0x80, ra) +lb ra, (#0x100, ra) +lb ra, (#0x200, ra) +lb ra, (#0x400, ra) +lb ra, (#0x7ff, ra) +lb ra, (#0xfffff801, t0) +lb ra, (#0xfffffc00, t0) +lb ra, (#0xfffffe00, t0) +lb ra, (#0xffffff00, t0) +lb ra, (#0xffffff80, t0) +lb ra, (#0xffffffc0, t0) +lb ra, (#0xffffffe0, t0) +lb ra, (#0xfffffff0, t0) +lb ra, (#0xfffffff8, t0) +lb ra, (#0xfffffffc, t0) +lb ra, (#0xfffffffe, t0) +lb ra, (#0xffffffff, t0) +lb ra, (#0, t0) +lb ra, (#1, t0) +lb ra, (#2, t0) +lb ra, (#4, t0) +lb ra, (#8, t0) +lb ra, (#0x10, t0) +lb ra, (#0x20, t0) +lb ra, (#0x40, t0) +lb ra, (#0x80, t0) +lb ra, (#0x100, t0) +lb ra, (#0x200, t0) +lb ra, (#0x400, t0) +lb ra, (#0x7ff, t0) +lb ra, (#0xfffff801, a0) +lb ra, (#0xfffffc00, a0) +lb ra, (#0xfffffe00, a0) +lb ra, (#0xffffff00, a0) +lb ra, (#0xffffff80, a0) +lb ra, (#0xffffffc0, a0) +lb ra, (#0xffffffe0, a0) +lb ra, (#0xfffffff0, a0) +lb ra, (#0xfffffff8, a0) +lb ra, (#0xfffffffc, a0) +lb ra, (#0xfffffffe, a0) +lb ra, (#0xffffffff, a0) +lb ra, (#0, a0) +lb ra, (#1, a0) +lb ra, (#2, a0) +lb ra, (#4, a0) +lb ra, (#8, a0) +lb ra, (#0x10, a0) +lb ra, (#0x20, a0) +lb ra, (#0x40, a0) +lb ra, (#0x80, a0) +lb ra, (#0x100, a0) +lb ra, (#0x200, a0) +lb ra, (#0x400, a0) +lb ra, (#0x7ff, a0) +lb ra, (#0xfffff801, a5) +lb ra, (#0xfffffc00, a5) +lb ra, (#0xfffffe00, a5) +lb ra, (#0xffffff00, a5) +lb ra, (#0xffffff80, a5) +lb ra, (#0xffffffc0, a5) +lb ra, (#0xffffffe0, a5) +lb ra, (#0xfffffff0, a5) +lb ra, (#0xfffffff8, a5) +lb ra, (#0xfffffffc, a5) +lb ra, (#0xfffffffe, a5) +lb ra, (#0xffffffff, a5) +lb ra, (#0, a5) +lb ra, (#1, a5) +lb ra, (#2, a5) +lb ra, (#4, a5) +lb ra, (#8, a5) +lb ra, (#0x10, a5) +lb ra, (#0x20, a5) +lb ra, (#0x40, a5) +lb ra, (#0x80, a5) +lb ra, (#0x100, a5) +lb ra, (#0x200, a5) +lb ra, (#0x400, a5) +lb ra, (#0x7ff, a5) +lb ra, (#0xfffff801, s4) +lb ra, (#0xfffffc00, s4) +lb ra, (#0xfffffe00, s4) +lb ra, (#0xffffff00, s4) +lb ra, (#0xffffff80, s4) +lb ra, (#0xffffffc0, s4) +lb ra, (#0xffffffe0, s4) +lb ra, (#0xfffffff0, s4) +lb ra, (#0xfffffff8, s4) +lb ra, (#0xfffffffc, s4) +lb ra, (#0xfffffffe, s4) +lb ra, (#0xffffffff, s4) +lb ra, (#0, s4) +lb ra, (#1, s4) +lb ra, (#2, s4) +lb ra, (#4, s4) +lb ra, (#8, s4) +lb ra, (#0x10, s4) +lb ra, (#0x20, s4) +lb ra, (#0x40, s4) +lb ra, (#0x80, s4) +lb ra, (#0x100, s4) +lb ra, (#0x200, s4) +lb ra, (#0x400, s4) +lb ra, (#0x7ff, s4) +lb ra, (#0xfffff801, s9) +lb ra, (#0xfffffc00, s9) +lb ra, (#0xfffffe00, s9) +lb ra, (#0xffffff00, s9) +lb ra, (#0xffffff80, s9) +lb ra, (#0xffffffc0, s9) +lb ra, (#0xffffffe0, s9) +lb ra, (#0xfffffff0, s9) +lb ra, (#0xfffffff8, s9) +lb ra, (#0xfffffffc, s9) +lb ra, (#0xfffffffe, s9) +lb ra, (#0xffffffff, s9) +lb ra, (#0, s9) +lb ra, (#1, s9) +lb ra, (#2, s9) +lb ra, (#4, s9) +lb ra, (#8, s9) +lb ra, (#0x10, s9) +lb ra, (#0x20, s9) +lb ra, (#0x40, s9) +lb ra, (#0x80, s9) +lb ra, (#0x100, s9) +lb ra, (#0x200, s9) +lb ra, (#0x400, s9) +lb ra, (#0x7ff, s9) +lb ra, (#0xfffff801, t6) +lb ra, (#0xfffffc00, t6) +lb ra, (#0xfffffe00, t6) +lb ra, (#0xffffff00, t6) +lb ra, (#0xffffff80, t6) +lb ra, (#0xffffffc0, t6) +lb ra, (#0xffffffe0, t6) +lb ra, (#0xfffffff0, t6) +lb ra, (#0xfffffff8, t6) +lb ra, (#0xfffffffc, t6) +lb ra, (#0xfffffffe, t6) +lb ra, (#0xffffffff, t6) +lb ra, (#0, t6) +lb ra, (#1, t6) +lb ra, (#2, t6) +lb ra, (#4, t6) +lb ra, (#8, t6) +lb ra, (#0x10, t6) +lb ra, (#0x20, t6) +lb ra, (#0x40, t6) +lb ra, (#0x80, t6) +lb ra, (#0x100, t6) +lb ra, (#0x200, t6) +lb ra, (#0x400, t6) +lb ra, (#0x7ff, t6) +lb t0, (#0xfffff801, zero) +lb t0, (#0xfffffc00, zero) +lb t0, (#0xfffffe00, zero) +lb t0, (#0xffffff00, zero) +lb t0, (#0xffffff80, zero) +lb t0, (#0xffffffc0, zero) +lb t0, (#0xffffffe0, zero) +lb t0, (#0xfffffff0, zero) +lb t0, (#0xfffffff8, zero) +lb t0, (#0xfffffffc, zero) +lb t0, (#0xfffffffe, zero) +lb t0, (#0xffffffff, zero) +lb t0, (#0, zero) +lb t0, (#1, zero) +lb t0, (#2, zero) +lb t0, (#4, zero) +lb t0, (#8, zero) +lb t0, (#0x10, zero) +lb t0, (#0x20, zero) +lb t0, (#0x40, zero) +lb t0, (#0x80, zero) +lb t0, (#0x100, zero) +lb t0, (#0x200, zero) +lb t0, (#0x400, zero) +lb t0, (#0x7ff, zero) +lb t0, (#0xfffff801, ra) +lb t0, (#0xfffffc00, ra) +lb t0, (#0xfffffe00, ra) +lb t0, (#0xffffff00, ra) +lb t0, (#0xffffff80, ra) +lb t0, (#0xffffffc0, ra) +lb t0, (#0xffffffe0, ra) +lb t0, (#0xfffffff0, ra) +lb t0, (#0xfffffff8, ra) +lb t0, (#0xfffffffc, ra) +lb t0, (#0xfffffffe, ra) +lb t0, (#0xffffffff, ra) +lb t0, (#0, ra) +lb t0, (#1, ra) +lb t0, (#2, ra) +lb t0, (#4, ra) +lb t0, (#8, ra) +lb t0, (#0x10, ra) +lb t0, (#0x20, ra) +lb t0, (#0x40, ra) +lb t0, (#0x80, ra) +lb t0, (#0x100, ra) +lb t0, (#0x200, ra) +lb t0, (#0x400, ra) +lb t0, (#0x7ff, ra) +lb t0, (#0xfffff801, t0) +lb t0, (#0xfffffc00, t0) +lb t0, (#0xfffffe00, t0) +lb t0, (#0xffffff00, t0) +lb t0, (#0xffffff80, t0) +lb t0, (#0xffffffc0, t0) +lb t0, (#0xffffffe0, t0) +lb t0, (#0xfffffff0, t0) +lb t0, (#0xfffffff8, t0) +lb t0, (#0xfffffffc, t0) +lb t0, (#0xfffffffe, t0) +lb t0, (#0xffffffff, t0) +lb t0, (#0, t0) +lb t0, (#1, t0) +lb t0, (#2, t0) +lb t0, (#4, t0) +lb t0, (#8, t0) +lb t0, (#0x10, t0) +lb t0, (#0x20, t0) +lb t0, (#0x40, t0) +lb t0, (#0x80, t0) +lb t0, (#0x100, t0) +lb t0, (#0x200, t0) +lb t0, (#0x400, t0) +lb t0, (#0x7ff, t0) +lb t0, (#0xfffff801, a0) +lb t0, (#0xfffffc00, a0) +lb t0, (#0xfffffe00, a0) +lb t0, (#0xffffff00, a0) +lb t0, (#0xffffff80, a0) +lb t0, (#0xffffffc0, a0) +lb t0, (#0xffffffe0, a0) +lb t0, (#0xfffffff0, a0) +lb t0, (#0xfffffff8, a0) +lb t0, (#0xfffffffc, a0) +lb t0, (#0xfffffffe, a0) +lb t0, (#0xffffffff, a0) +lb t0, (#0, a0) +lb t0, (#1, a0) +lb t0, (#2, a0) +lb t0, (#4, a0) +lb t0, (#8, a0) +lb t0, (#0x10, a0) +lb t0, (#0x20, a0) +lb t0, (#0x40, a0) +lb t0, (#0x80, a0) +lb t0, (#0x100, a0) +lb t0, (#0x200, a0) +lb t0, (#0x400, a0) +lb t0, (#0x7ff, a0) +lb t0, (#0xfffff801, a5) +lb t0, (#0xfffffc00, a5) +lb t0, (#0xfffffe00, a5) +lb t0, (#0xffffff00, a5) +lb t0, (#0xffffff80, a5) +lb t0, (#0xffffffc0, a5) +lb t0, (#0xffffffe0, a5) +lb t0, (#0xfffffff0, a5) +lb t0, (#0xfffffff8, a5) +lb t0, (#0xfffffffc, a5) +lb t0, (#0xfffffffe, a5) +lb t0, (#0xffffffff, a5) +lb t0, (#0, a5) +lb t0, (#1, a5) +lb t0, (#2, a5) +lb t0, (#4, a5) +lb t0, (#8, a5) +lb t0, (#0x10, a5) +lb t0, (#0x20, a5) +lb t0, (#0x40, a5) +lb t0, (#0x80, a5) +lb t0, (#0x100, a5) +lb t0, (#0x200, a5) +lb t0, (#0x400, a5) +lb t0, (#0x7ff, a5) +lb t0, (#0xfffff801, s4) +lb t0, (#0xfffffc00, s4) +lb t0, (#0xfffffe00, s4) +lb t0, (#0xffffff00, s4) +lb t0, (#0xffffff80, s4) +lb t0, (#0xffffffc0, s4) +lb t0, (#0xffffffe0, s4) +lb t0, (#0xfffffff0, s4) +lb t0, (#0xfffffff8, s4) +lb t0, (#0xfffffffc, s4) +lb t0, (#0xfffffffe, s4) +lb t0, (#0xffffffff, s4) +lb t0, (#0, s4) +lb t0, (#1, s4) +lb t0, (#2, s4) +lb t0, (#4, s4) +lb t0, (#8, s4) +lb t0, (#0x10, s4) +lb t0, (#0x20, s4) +lb t0, (#0x40, s4) +lb t0, (#0x80, s4) +lb t0, (#0x100, s4) +lb t0, (#0x200, s4) +lb t0, (#0x400, s4) +lb t0, (#0x7ff, s4) +lb t0, (#0xfffff801, s9) +lb t0, (#0xfffffc00, s9) +lb t0, (#0xfffffe00, s9) +lb t0, (#0xffffff00, s9) +lb t0, (#0xffffff80, s9) +lb t0, (#0xffffffc0, s9) +lb t0, (#0xffffffe0, s9) +lb t0, (#0xfffffff0, s9) +lb t0, (#0xfffffff8, s9) +lb t0, (#0xfffffffc, s9) +lb t0, (#0xfffffffe, s9) +lb t0, (#0xffffffff, s9) +lb t0, (#0, s9) +lb t0, (#1, s9) +lb t0, (#2, s9) +lb t0, (#4, s9) +lb t0, (#8, s9) +lb t0, (#0x10, s9) +lb t0, (#0x20, s9) +lb t0, (#0x40, s9) +lb t0, (#0x80, s9) +lb t0, (#0x100, s9) +lb t0, (#0x200, s9) +lb t0, (#0x400, s9) +lb t0, (#0x7ff, s9) +lb t0, (#0xfffff801, t6) +lb t0, (#0xfffffc00, t6) +lb t0, (#0xfffffe00, t6) +lb t0, (#0xffffff00, t6) +lb t0, (#0xffffff80, t6) +lb t0, (#0xffffffc0, t6) +lb t0, (#0xffffffe0, t6) +lb t0, (#0xfffffff0, t6) +lb t0, (#0xfffffff8, t6) +lb t0, (#0xfffffffc, t6) +lb t0, (#0xfffffffe, t6) +lb t0, (#0xffffffff, t6) +lb t0, (#0, t6) +lb t0, (#1, t6) +lb t0, (#2, t6) +lb t0, (#4, t6) +lb t0, (#8, t6) +lb t0, (#0x10, t6) +lb t0, (#0x20, t6) +lb t0, (#0x40, t6) +lb t0, (#0x80, t6) +lb t0, (#0x100, t6) +lb t0, (#0x200, t6) +lb t0, (#0x400, t6) +lb t0, (#0x7ff, t6) +lb a0, (#0xfffff801, zero) +lb a0, (#0xfffffc00, zero) +lb a0, (#0xfffffe00, zero) +lb a0, (#0xffffff00, zero) +lb a0, (#0xffffff80, zero) +lb a0, (#0xffffffc0, zero) +lb a0, (#0xffffffe0, zero) +lb a0, (#0xfffffff0, zero) +lb a0, (#0xfffffff8, zero) +lb a0, (#0xfffffffc, zero) +lb a0, (#0xfffffffe, zero) +lb a0, (#0xffffffff, zero) +lb a0, (#0, zero) +lb a0, (#1, zero) +lb a0, (#2, zero) +lb a0, (#4, zero) +lb a0, (#8, zero) +lb a0, (#0x10, zero) +lb a0, (#0x20, zero) +lb a0, (#0x40, zero) +lb a0, (#0x80, zero) +lb a0, (#0x100, zero) +lb a0, (#0x200, zero) +lb a0, (#0x400, zero) +lb a0, (#0x7ff, zero) +lb a0, (#0xfffff801, ra) +lb a0, (#0xfffffc00, ra) +lb a0, (#0xfffffe00, ra) +lb a0, (#0xffffff00, ra) +lb a0, (#0xffffff80, ra) +lb a0, (#0xffffffc0, ra) +lb a0, (#0xffffffe0, ra) +lb a0, (#0xfffffff0, ra) +lb a0, (#0xfffffff8, ra) +lb a0, (#0xfffffffc, ra) +lb a0, (#0xfffffffe, ra) +lb a0, (#0xffffffff, ra) +lb a0, (#0, ra) +lb a0, (#1, ra) +lb a0, (#2, ra) +lb a0, (#4, ra) +lb a0, (#8, ra) +lb a0, (#0x10, ra) +lb a0, (#0x20, ra) +lb a0, (#0x40, ra) +lb a0, (#0x80, ra) +lb a0, (#0x100, ra) +lb a0, (#0x200, ra) +lb a0, (#0x400, ra) +lb a0, (#0x7ff, ra) +lb a0, (#0xfffff801, t0) +lb a0, (#0xfffffc00, t0) +lb a0, (#0xfffffe00, t0) +lb a0, (#0xffffff00, t0) +lb a0, (#0xffffff80, t0) +lb a0, (#0xffffffc0, t0) +lb a0, (#0xffffffe0, t0) +lb a0, (#0xfffffff0, t0) +lb a0, (#0xfffffff8, t0) +lb a0, (#0xfffffffc, t0) +lb a0, (#0xfffffffe, t0) +lb a0, (#0xffffffff, t0) +lb a0, (#0, t0) +lb a0, (#1, t0) +lb a0, (#2, t0) +lb a0, (#4, t0) +lb a0, (#8, t0) +lb a0, (#0x10, t0) +lb a0, (#0x20, t0) +lb a0, (#0x40, t0) +lb a0, (#0x80, t0) +lb a0, (#0x100, t0) +lb a0, (#0x200, t0) +lb a0, (#0x400, t0) +lb a0, (#0x7ff, t0) +lb a0, (#0xfffff801, a0) +lb a0, (#0xfffffc00, a0) +lb a0, (#0xfffffe00, a0) +lb a0, (#0xffffff00, a0) +lb a0, (#0xffffff80, a0) +lb a0, (#0xffffffc0, a0) +lb a0, (#0xffffffe0, a0) +lb a0, (#0xfffffff0, a0) +lb a0, (#0xfffffff8, a0) +lb a0, (#0xfffffffc, a0) +lb a0, (#0xfffffffe, a0) +lb a0, (#0xffffffff, a0) +lb a0, (#0, a0) +lb a0, (#1, a0) +lb a0, (#2, a0) +lb a0, (#4, a0) +lb a0, (#8, a0) +lb a0, (#0x10, a0) +lb a0, (#0x20, a0) +lb a0, (#0x40, a0) +lb a0, (#0x80, a0) +lb a0, (#0x100, a0) +lb a0, (#0x200, a0) +lb a0, (#0x400, a0) +lb a0, (#0x7ff, a0) +lb a0, (#0xfffff801, a5) +lb a0, (#0xfffffc00, a5) +lb a0, (#0xfffffe00, a5) +lb a0, (#0xffffff00, a5) +lb a0, (#0xffffff80, a5) +lb a0, (#0xffffffc0, a5) +lb a0, (#0xffffffe0, a5) +lb a0, (#0xfffffff0, a5) +lb a0, (#0xfffffff8, a5) +lb a0, (#0xfffffffc, a5) +lb a0, (#0xfffffffe, a5) +lb a0, (#0xffffffff, a5) +lb a0, (#0, a5) +lb a0, (#1, a5) +lb a0, (#2, a5) +lb a0, (#4, a5) +lb a0, (#8, a5) +lb a0, (#0x10, a5) +lb a0, (#0x20, a5) +lb a0, (#0x40, a5) +lb a0, (#0x80, a5) +lb a0, (#0x100, a5) +lb a0, (#0x200, a5) +lb a0, (#0x400, a5) +lb a0, (#0x7ff, a5) +lb a0, (#0xfffff801, s4) +lb a0, (#0xfffffc00, s4) +lb a0, (#0xfffffe00, s4) +lb a0, (#0xffffff00, s4) +lb a0, (#0xffffff80, s4) +lb a0, (#0xffffffc0, s4) +lb a0, (#0xffffffe0, s4) +lb a0, (#0xfffffff0, s4) +lb a0, (#0xfffffff8, s4) +lb a0, (#0xfffffffc, s4) +lb a0, (#0xfffffffe, s4) +lb a0, (#0xffffffff, s4) +lb a0, (#0, s4) +lb a0, (#1, s4) +lb a0, (#2, s4) +lb a0, (#4, s4) +lb a0, (#8, s4) +lb a0, (#0x10, s4) +lb a0, (#0x20, s4) +lb a0, (#0x40, s4) +lb a0, (#0x80, s4) +lb a0, (#0x100, s4) +lb a0, (#0x200, s4) +lb a0, (#0x400, s4) +lb a0, (#0x7ff, s4) +lb a0, (#0xfffff801, s9) +lb a0, (#0xfffffc00, s9) +lb a0, (#0xfffffe00, s9) +lb a0, (#0xffffff00, s9) +lb a0, (#0xffffff80, s9) +lb a0, (#0xffffffc0, s9) +lb a0, (#0xffffffe0, s9) +lb a0, (#0xfffffff0, s9) +lb a0, (#0xfffffff8, s9) +lb a0, (#0xfffffffc, s9) +lb a0, (#0xfffffffe, s9) +lb a0, (#0xffffffff, s9) +lb a0, (#0, s9) +lb a0, (#1, s9) +lb a0, (#2, s9) +lb a0, (#4, s9) +lb a0, (#8, s9) +lb a0, (#0x10, s9) +lb a0, (#0x20, s9) +lb a0, (#0x40, s9) +lb a0, (#0x80, s9) +lb a0, (#0x100, s9) +lb a0, (#0x200, s9) +lb a0, (#0x400, s9) +lb a0, (#0x7ff, s9) +lb a0, (#0xfffff801, t6) +lb a0, (#0xfffffc00, t6) +lb a0, (#0xfffffe00, t6) +lb a0, (#0xffffff00, t6) +lb a0, (#0xffffff80, t6) +lb a0, (#0xffffffc0, t6) +lb a0, (#0xffffffe0, t6) +lb a0, (#0xfffffff0, t6) +lb a0, (#0xfffffff8, t6) +lb a0, (#0xfffffffc, t6) +lb a0, (#0xfffffffe, t6) +lb a0, (#0xffffffff, t6) +lb a0, (#0, t6) +lb a0, (#1, t6) +lb a0, (#2, t6) +lb a0, (#4, t6) +lb a0, (#8, t6) +lb a0, (#0x10, t6) +lb a0, (#0x20, t6) +lb a0, (#0x40, t6) +lb a0, (#0x80, t6) +lb a0, (#0x100, t6) +lb a0, (#0x200, t6) +lb a0, (#0x400, t6) +lb a0, (#0x7ff, t6) +lb a5, (#0xfffff801, zero) +lb a5, (#0xfffffc00, zero) +lb a5, (#0xfffffe00, zero) +lb a5, (#0xffffff00, zero) +lb a5, (#0xffffff80, zero) +lb a5, (#0xffffffc0, zero) +lb a5, (#0xffffffe0, zero) +lb a5, (#0xfffffff0, zero) +lb a5, (#0xfffffff8, zero) +lb a5, (#0xfffffffc, zero) +lb a5, (#0xfffffffe, zero) +lb a5, (#0xffffffff, zero) +lb a5, (#0, zero) +lb a5, (#1, zero) +lb a5, (#2, zero) +lb a5, (#4, zero) +lb a5, (#8, zero) +lb a5, (#0x10, zero) +lb a5, (#0x20, zero) +lb a5, (#0x40, zero) +lb a5, (#0x80, zero) +lb a5, (#0x100, zero) +lb a5, (#0x200, zero) +lb a5, (#0x400, zero) +lb a5, (#0x7ff, zero) +lb a5, (#0xfffff801, ra) +lb a5, (#0xfffffc00, ra) +lb a5, (#0xfffffe00, ra) +lb a5, (#0xffffff00, ra) +lb a5, (#0xffffff80, ra) +lb a5, (#0xffffffc0, ra) +lb a5, (#0xffffffe0, ra) +lb a5, (#0xfffffff0, ra) +lb a5, (#0xfffffff8, ra) +lb a5, (#0xfffffffc, ra) +lb a5, (#0xfffffffe, ra) +lb a5, (#0xffffffff, ra) +lb a5, (#0, ra) +lb a5, (#1, ra) +lb a5, (#2, ra) +lb a5, (#4, ra) +lb a5, (#8, ra) +lb a5, (#0x10, ra) +lb a5, (#0x20, ra) +lb a5, (#0x40, ra) +lb a5, (#0x80, ra) +lb a5, (#0x100, ra) +lb a5, (#0x200, ra) +lb a5, (#0x400, ra) +lb a5, (#0x7ff, ra) +lb a5, (#0xfffff801, t0) +lb a5, (#0xfffffc00, t0) +lb a5, (#0xfffffe00, t0) +lb a5, (#0xffffff00, t0) +lb a5, (#0xffffff80, t0) +lb a5, (#0xffffffc0, t0) +lb a5, (#0xffffffe0, t0) +lb a5, (#0xfffffff0, t0) +lb a5, (#0xfffffff8, t0) +lb a5, (#0xfffffffc, t0) +lb a5, (#0xfffffffe, t0) +lb a5, (#0xffffffff, t0) +lb a5, (#0, t0) +lb a5, (#1, t0) +lb a5, (#2, t0) +lb a5, (#4, t0) +lb a5, (#8, t0) +lb a5, (#0x10, t0) +lb a5, (#0x20, t0) +lb a5, (#0x40, t0) +lb a5, (#0x80, t0) +lb a5, (#0x100, t0) +lb a5, (#0x200, t0) +lb a5, (#0x400, t0) +lb a5, (#0x7ff, t0) +lb a5, (#0xfffff801, a0) +lb a5, (#0xfffffc00, a0) +lb a5, (#0xfffffe00, a0) +lb a5, (#0xffffff00, a0) +lb a5, (#0xffffff80, a0) +lb a5, (#0xffffffc0, a0) +lb a5, (#0xffffffe0, a0) +lb a5, (#0xfffffff0, a0) +lb a5, (#0xfffffff8, a0) +lb a5, (#0xfffffffc, a0) +lb a5, (#0xfffffffe, a0) +lb a5, (#0xffffffff, a0) +lb a5, (#0, a0) +lb a5, (#1, a0) +lb a5, (#2, a0) +lb a5, (#4, a0) +lb a5, (#8, a0) +lb a5, (#0x10, a0) +lb a5, (#0x20, a0) +lb a5, (#0x40, a0) +lb a5, (#0x80, a0) +lb a5, (#0x100, a0) +lb a5, (#0x200, a0) +lb a5, (#0x400, a0) +lb a5, (#0x7ff, a0) +lb a5, (#0xfffff801, a5) +lb a5, (#0xfffffc00, a5) +lb a5, (#0xfffffe00, a5) +lb a5, (#0xffffff00, a5) +lb a5, (#0xffffff80, a5) +lb a5, (#0xffffffc0, a5) +lb a5, (#0xffffffe0, a5) +lb a5, (#0xfffffff0, a5) +lb a5, (#0xfffffff8, a5) +lb a5, (#0xfffffffc, a5) +lb a5, (#0xfffffffe, a5) +lb a5, (#0xffffffff, a5) +lb a5, (#0, a5) +lb a5, (#1, a5) +lb a5, (#2, a5) +lb a5, (#4, a5) +lb a5, (#8, a5) +lb a5, (#0x10, a5) +lb a5, (#0x20, a5) +lb a5, (#0x40, a5) +lb a5, (#0x80, a5) +lb a5, (#0x100, a5) +lb a5, (#0x200, a5) +lb a5, (#0x400, a5) +lb a5, (#0x7ff, a5) +lb a5, (#0xfffff801, s4) +lb a5, (#0xfffffc00, s4) +lb a5, (#0xfffffe00, s4) +lb a5, (#0xffffff00, s4) +lb a5, (#0xffffff80, s4) +lb a5, (#0xffffffc0, s4) +lb a5, (#0xffffffe0, s4) +lb a5, (#0xfffffff0, s4) +lb a5, (#0xfffffff8, s4) +lb a5, (#0xfffffffc, s4) +lb a5, (#0xfffffffe, s4) +lb a5, (#0xffffffff, s4) +lb a5, (#0, s4) +lb a5, (#1, s4) +lb a5, (#2, s4) +lb a5, (#4, s4) +lb a5, (#8, s4) +lb a5, (#0x10, s4) +lb a5, (#0x20, s4) +lb a5, (#0x40, s4) +lb a5, (#0x80, s4) +lb a5, (#0x100, s4) +lb a5, (#0x200, s4) +lb a5, (#0x400, s4) +lb a5, (#0x7ff, s4) +lb a5, (#0xfffff801, s9) +lb a5, (#0xfffffc00, s9) +lb a5, (#0xfffffe00, s9) +lb a5, (#0xffffff00, s9) +lb a5, (#0xffffff80, s9) +lb a5, (#0xffffffc0, s9) +lb a5, (#0xffffffe0, s9) +lb a5, (#0xfffffff0, s9) +lb a5, (#0xfffffff8, s9) +lb a5, (#0xfffffffc, s9) +lb a5, (#0xfffffffe, s9) +lb a5, (#0xffffffff, s9) +lb a5, (#0, s9) +lb a5, (#1, s9) +lb a5, (#2, s9) +lb a5, (#4, s9) +lb a5, (#8, s9) +lb a5, (#0x10, s9) +lb a5, (#0x20, s9) +lb a5, (#0x40, s9) +lb a5, (#0x80, s9) +lb a5, (#0x100, s9) +lb a5, (#0x200, s9) +lb a5, (#0x400, s9) +lb a5, (#0x7ff, s9) +lb a5, (#0xfffff801, t6) +lb a5, (#0xfffffc00, t6) +lb a5, (#0xfffffe00, t6) +lb a5, (#0xffffff00, t6) +lb a5, (#0xffffff80, t6) +lb a5, (#0xffffffc0, t6) +lb a5, (#0xffffffe0, t6) +lb a5, (#0xfffffff0, t6) +lb a5, (#0xfffffff8, t6) +lb a5, (#0xfffffffc, t6) +lb a5, (#0xfffffffe, t6) +lb a5, (#0xffffffff, t6) +lb a5, (#0, t6) +lb a5, (#1, t6) +lb a5, (#2, t6) +lb a5, (#4, t6) +lb a5, (#8, t6) +lb a5, (#0x10, t6) +lb a5, (#0x20, t6) +lb a5, (#0x40, t6) +lb a5, (#0x80, t6) +lb a5, (#0x100, t6) +lb a5, (#0x200, t6) +lb a5, (#0x400, t6) +lb a5, (#0x7ff, t6) +lb s4, (#0xfffff801, zero) +lb s4, (#0xfffffc00, zero) +lb s4, (#0xfffffe00, zero) +lb s4, (#0xffffff00, zero) +lb s4, (#0xffffff80, zero) +lb s4, (#0xffffffc0, zero) +lb s4, (#0xffffffe0, zero) +lb s4, (#0xfffffff0, zero) +lb s4, (#0xfffffff8, zero) +lb s4, (#0xfffffffc, zero) +lb s4, (#0xfffffffe, zero) +lb s4, (#0xffffffff, zero) +lb s4, (#0, zero) +lb s4, (#1, zero) +lb s4, (#2, zero) +lb s4, (#4, zero) +lb s4, (#8, zero) +lb s4, (#0x10, zero) +lb s4, (#0x20, zero) +lb s4, (#0x40, zero) +lb s4, (#0x80, zero) +lb s4, (#0x100, zero) +lb s4, (#0x200, zero) +lb s4, (#0x400, zero) +lb s4, (#0x7ff, zero) +lb s4, (#0xfffff801, ra) +lb s4, (#0xfffffc00, ra) +lb s4, (#0xfffffe00, ra) +lb s4, (#0xffffff00, ra) +lb s4, (#0xffffff80, ra) +lb s4, (#0xffffffc0, ra) +lb s4, (#0xffffffe0, ra) +lb s4, (#0xfffffff0, ra) +lb s4, (#0xfffffff8, ra) +lb s4, (#0xfffffffc, ra) +lb s4, (#0xfffffffe, ra) +lb s4, (#0xffffffff, ra) +lb s4, (#0, ra) +lb s4, (#1, ra) +lb s4, (#2, ra) +lb s4, (#4, ra) +lb s4, (#8, ra) +lb s4, (#0x10, ra) +lb s4, (#0x20, ra) +lb s4, (#0x40, ra) +lb s4, (#0x80, ra) +lb s4, (#0x100, ra) +lb s4, (#0x200, ra) +lb s4, (#0x400, ra) +lb s4, (#0x7ff, ra) +lb s4, (#0xfffff801, t0) +lb s4, (#0xfffffc00, t0) +lb s4, (#0xfffffe00, t0) +lb s4, (#0xffffff00, t0) +lb s4, (#0xffffff80, t0) +lb s4, (#0xffffffc0, t0) +lb s4, (#0xffffffe0, t0) +lb s4, (#0xfffffff0, t0) +lb s4, (#0xfffffff8, t0) +lb s4, (#0xfffffffc, t0) +lb s4, (#0xfffffffe, t0) +lb s4, (#0xffffffff, t0) +lb s4, (#0, t0) +lb s4, (#1, t0) +lb s4, (#2, t0) +lb s4, (#4, t0) +lb s4, (#8, t0) +lb s4, (#0x10, t0) +lb s4, (#0x20, t0) +lb s4, (#0x40, t0) +lb s4, (#0x80, t0) +lb s4, (#0x100, t0) +lb s4, (#0x200, t0) +lb s4, (#0x400, t0) +lb s4, (#0x7ff, t0) +lb s4, (#0xfffff801, a0) +lb s4, (#0xfffffc00, a0) +lb s4, (#0xfffffe00, a0) +lb s4, (#0xffffff00, a0) +lb s4, (#0xffffff80, a0) +lb s4, (#0xffffffc0, a0) +lb s4, (#0xffffffe0, a0) +lb s4, (#0xfffffff0, a0) +lb s4, (#0xfffffff8, a0) +lb s4, (#0xfffffffc, a0) +lb s4, (#0xfffffffe, a0) +lb s4, (#0xffffffff, a0) +lb s4, (#0, a0) +lb s4, (#1, a0) +lb s4, (#2, a0) +lb s4, (#4, a0) +lb s4, (#8, a0) +lb s4, (#0x10, a0) +lb s4, (#0x20, a0) +lb s4, (#0x40, a0) +lb s4, (#0x80, a0) +lb s4, (#0x100, a0) +lb s4, (#0x200, a0) +lb s4, (#0x400, a0) +lb s4, (#0x7ff, a0) +lb s4, (#0xfffff801, a5) +lb s4, (#0xfffffc00, a5) +lb s4, (#0xfffffe00, a5) +lb s4, (#0xffffff00, a5) +lb s4, (#0xffffff80, a5) +lb s4, (#0xffffffc0, a5) +lb s4, (#0xffffffe0, a5) +lb s4, (#0xfffffff0, a5) +lb s4, (#0xfffffff8, a5) +lb s4, (#0xfffffffc, a5) +lb s4, (#0xfffffffe, a5) +lb s4, (#0xffffffff, a5) +lb s4, (#0, a5) +lb s4, (#1, a5) +lb s4, (#2, a5) +lb s4, (#4, a5) +lb s4, (#8, a5) +lb s4, (#0x10, a5) +lb s4, (#0x20, a5) +lb s4, (#0x40, a5) +lb s4, (#0x80, a5) +lb s4, (#0x100, a5) +lb s4, (#0x200, a5) +lb s4, (#0x400, a5) +lb s4, (#0x7ff, a5) +lb s4, (#0xfffff801, s4) +lb s4, (#0xfffffc00, s4) +lb s4, (#0xfffffe00, s4) +lb s4, (#0xffffff00, s4) +lb s4, (#0xffffff80, s4) +lb s4, (#0xffffffc0, s4) +lb s4, (#0xffffffe0, s4) +lb s4, (#0xfffffff0, s4) +lb s4, (#0xfffffff8, s4) +lb s4, (#0xfffffffc, s4) +lb s4, (#0xfffffffe, s4) +lb s4, (#0xffffffff, s4) +lb s4, (#0, s4) +lb s4, (#1, s4) +lb s4, (#2, s4) +lb s4, (#4, s4) +lb s4, (#8, s4) +lb s4, (#0x10, s4) +lb s4, (#0x20, s4) +lb s4, (#0x40, s4) +lb s4, (#0x80, s4) +lb s4, (#0x100, s4) +lb s4, (#0x200, s4) +lb s4, (#0x400, s4) +lb s4, (#0x7ff, s4) +lb s4, (#0xfffff801, s9) +lb s4, (#0xfffffc00, s9) +lb s4, (#0xfffffe00, s9) +lb s4, (#0xffffff00, s9) +lb s4, (#0xffffff80, s9) +lb s4, (#0xffffffc0, s9) +lb s4, (#0xffffffe0, s9) +lb s4, (#0xfffffff0, s9) +lb s4, (#0xfffffff8, s9) +lb s4, (#0xfffffffc, s9) +lb s4, (#0xfffffffe, s9) +lb s4, (#0xffffffff, s9) +lb s4, (#0, s9) +lb s4, (#1, s9) +lb s4, (#2, s9) +lb s4, (#4, s9) +lb s4, (#8, s9) +lb s4, (#0x10, s9) +lb s4, (#0x20, s9) +lb s4, (#0x40, s9) +lb s4, (#0x80, s9) +lb s4, (#0x100, s9) +lb s4, (#0x200, s9) +lb s4, (#0x400, s9) +lb s4, (#0x7ff, s9) +lb s4, (#0xfffff801, t6) +lb s4, (#0xfffffc00, t6) +lb s4, (#0xfffffe00, t6) +lb s4, (#0xffffff00, t6) +lb s4, (#0xffffff80, t6) +lb s4, (#0xffffffc0, t6) +lb s4, (#0xffffffe0, t6) +lb s4, (#0xfffffff0, t6) +lb s4, (#0xfffffff8, t6) +lb s4, (#0xfffffffc, t6) +lb s4, (#0xfffffffe, t6) +lb s4, (#0xffffffff, t6) +lb s4, (#0, t6) +lb s4, (#1, t6) +lb s4, (#2, t6) +lb s4, (#4, t6) +lb s4, (#8, t6) +lb s4, (#0x10, t6) +lb s4, (#0x20, t6) +lb s4, (#0x40, t6) +lb s4, (#0x80, t6) +lb s4, (#0x100, t6) +lb s4, (#0x200, t6) +lb s4, (#0x400, t6) +lb s4, (#0x7ff, t6) +lb s9, (#0xfffff801, zero) +lb s9, (#0xfffffc00, zero) +lb s9, (#0xfffffe00, zero) +lb s9, (#0xffffff00, zero) +lb s9, (#0xffffff80, zero) +lb s9, (#0xffffffc0, zero) +lb s9, (#0xffffffe0, zero) +lb s9, (#0xfffffff0, zero) +lb s9, (#0xfffffff8, zero) +lb s9, (#0xfffffffc, zero) +lb s9, (#0xfffffffe, zero) +lb s9, (#0xffffffff, zero) +lb s9, (#0, zero) +lb s9, (#1, zero) +lb s9, (#2, zero) +lb s9, (#4, zero) +lb s9, (#8, zero) +lb s9, (#0x10, zero) +lb s9, (#0x20, zero) +lb s9, (#0x40, zero) +lb s9, (#0x80, zero) +lb s9, (#0x100, zero) +lb s9, (#0x200, zero) +lb s9, (#0x400, zero) +lb s9, (#0x7ff, zero) +lb s9, (#0xfffff801, ra) +lb s9, (#0xfffffc00, ra) +lb s9, (#0xfffffe00, ra) +lb s9, (#0xffffff00, ra) +lb s9, (#0xffffff80, ra) +lb s9, (#0xffffffc0, ra) +lb s9, (#0xffffffe0, ra) +lb s9, (#0xfffffff0, ra) +lb s9, (#0xfffffff8, ra) +lb s9, (#0xfffffffc, ra) +lb s9, (#0xfffffffe, ra) +lb s9, (#0xffffffff, ra) +lb s9, (#0, ra) +lb s9, (#1, ra) +lb s9, (#2, ra) +lb s9, (#4, ra) +lb s9, (#8, ra) +lb s9, (#0x10, ra) +lb s9, (#0x20, ra) +lb s9, (#0x40, ra) +lb s9, (#0x80, ra) +lb s9, (#0x100, ra) +lb s9, (#0x200, ra) +lb s9, (#0x400, ra) +lb s9, (#0x7ff, ra) +lb s9, (#0xfffff801, t0) +lb s9, (#0xfffffc00, t0) +lb s9, (#0xfffffe00, t0) +lb s9, (#0xffffff00, t0) +lb s9, (#0xffffff80, t0) +lb s9, (#0xffffffc0, t0) +lb s9, (#0xffffffe0, t0) +lb s9, (#0xfffffff0, t0) +lb s9, (#0xfffffff8, t0) +lb s9, (#0xfffffffc, t0) +lb s9, (#0xfffffffe, t0) +lb s9, (#0xffffffff, t0) +lb s9, (#0, t0) +lb s9, (#1, t0) +lb s9, (#2, t0) +lb s9, (#4, t0) +lb s9, (#8, t0) +lb s9, (#0x10, t0) +lb s9, (#0x20, t0) +lb s9, (#0x40, t0) +lb s9, (#0x80, t0) +lb s9, (#0x100, t0) +lb s9, (#0x200, t0) +lb s9, (#0x400, t0) +lb s9, (#0x7ff, t0) +lb s9, (#0xfffff801, a0) +lb s9, (#0xfffffc00, a0) +lb s9, (#0xfffffe00, a0) +lb s9, (#0xffffff00, a0) +lb s9, (#0xffffff80, a0) +lb s9, (#0xffffffc0, a0) +lb s9, (#0xffffffe0, a0) +lb s9, (#0xfffffff0, a0) +lb s9, (#0xfffffff8, a0) +lb s9, (#0xfffffffc, a0) +lb s9, (#0xfffffffe, a0) +lb s9, (#0xffffffff, a0) +lb s9, (#0, a0) +lb s9, (#1, a0) +lb s9, (#2, a0) +lb s9, (#4, a0) +lb s9, (#8, a0) +lb s9, (#0x10, a0) +lb s9, (#0x20, a0) +lb s9, (#0x40, a0) +lb s9, (#0x80, a0) +lb s9, (#0x100, a0) +lb s9, (#0x200, a0) +lb s9, (#0x400, a0) +lb s9, (#0x7ff, a0) +lb s9, (#0xfffff801, a5) +lb s9, (#0xfffffc00, a5) +lb s9, (#0xfffffe00, a5) +lb s9, (#0xffffff00, a5) +lb s9, (#0xffffff80, a5) +lb s9, (#0xffffffc0, a5) +lb s9, (#0xffffffe0, a5) +lb s9, (#0xfffffff0, a5) +lb s9, (#0xfffffff8, a5) +lb s9, (#0xfffffffc, a5) +lb s9, (#0xfffffffe, a5) +lb s9, (#0xffffffff, a5) +lb s9, (#0, a5) +lb s9, (#1, a5) +lb s9, (#2, a5) +lb s9, (#4, a5) +lb s9, (#8, a5) +lb s9, (#0x10, a5) +lb s9, (#0x20, a5) +lb s9, (#0x40, a5) +lb s9, (#0x80, a5) +lb s9, (#0x100, a5) +lb s9, (#0x200, a5) +lb s9, (#0x400, a5) +lb s9, (#0x7ff, a5) +lb s9, (#0xfffff801, s4) +lb s9, (#0xfffffc00, s4) +lb s9, (#0xfffffe00, s4) +lb s9, (#0xffffff00, s4) +lb s9, (#0xffffff80, s4) +lb s9, (#0xffffffc0, s4) +lb s9, (#0xffffffe0, s4) +lb s9, (#0xfffffff0, s4) +lb s9, (#0xfffffff8, s4) +lb s9, (#0xfffffffc, s4) +lb s9, (#0xfffffffe, s4) +lb s9, (#0xffffffff, s4) +lb s9, (#0, s4) +lb s9, (#1, s4) +lb s9, (#2, s4) +lb s9, (#4, s4) +lb s9, (#8, s4) +lb s9, (#0x10, s4) +lb s9, (#0x20, s4) +lb s9, (#0x40, s4) +lb s9, (#0x80, s4) +lb s9, (#0x100, s4) +lb s9, (#0x200, s4) +lb s9, (#0x400, s4) +lb s9, (#0x7ff, s4) +lb s9, (#0xfffff801, s9) +lb s9, (#0xfffffc00, s9) +lb s9, (#0xfffffe00, s9) +lb s9, (#0xffffff00, s9) +lb s9, (#0xffffff80, s9) +lb s9, (#0xffffffc0, s9) +lb s9, (#0xffffffe0, s9) +lb s9, (#0xfffffff0, s9) +lb s9, (#0xfffffff8, s9) +lb s9, (#0xfffffffc, s9) +lb s9, (#0xfffffffe, s9) +lb s9, (#0xffffffff, s9) +lb s9, (#0, s9) +lb s9, (#1, s9) +lb s9, (#2, s9) +lb s9, (#4, s9) +lb s9, (#8, s9) +lb s9, (#0x10, s9) +lb s9, (#0x20, s9) +lb s9, (#0x40, s9) +lb s9, (#0x80, s9) +lb s9, (#0x100, s9) +lb s9, (#0x200, s9) +lb s9, (#0x400, s9) +lb s9, (#0x7ff, s9) +lb s9, (#0xfffff801, t6) +lb s9, (#0xfffffc00, t6) +lb s9, (#0xfffffe00, t6) +lb s9, (#0xffffff00, t6) +lb s9, (#0xffffff80, t6) +lb s9, (#0xffffffc0, t6) +lb s9, (#0xffffffe0, t6) +lb s9, (#0xfffffff0, t6) +lb s9, (#0xfffffff8, t6) +lb s9, (#0xfffffffc, t6) +lb s9, (#0xfffffffe, t6) +lb s9, (#0xffffffff, t6) +lb s9, (#0, t6) +lb s9, (#1, t6) +lb s9, (#2, t6) +lb s9, (#4, t6) +lb s9, (#8, t6) +lb s9, (#0x10, t6) +lb s9, (#0x20, t6) +lb s9, (#0x40, t6) +lb s9, (#0x80, t6) +lb s9, (#0x100, t6) +lb s9, (#0x200, t6) +lb s9, (#0x400, t6) +lb s9, (#0x7ff, t6) +lb t6, (#0xfffff801, zero) +lb t6, (#0xfffffc00, zero) +lb t6, (#0xfffffe00, zero) +lb t6, (#0xffffff00, zero) +lb t6, (#0xffffff80, zero) +lb t6, (#0xffffffc0, zero) +lb t6, (#0xffffffe0, zero) +lb t6, (#0xfffffff0, zero) +lb t6, (#0xfffffff8, zero) +lb t6, (#0xfffffffc, zero) +lb t6, (#0xfffffffe, zero) +lb t6, (#0xffffffff, zero) +lb t6, (#0, zero) +lb t6, (#1, zero) +lb t6, (#2, zero) +lb t6, (#4, zero) +lb t6, (#8, zero) +lb t6, (#0x10, zero) +lb t6, (#0x20, zero) +lb t6, (#0x40, zero) +lb t6, (#0x80, zero) +lb t6, (#0x100, zero) +lb t6, (#0x200, zero) +lb t6, (#0x400, zero) +lb t6, (#0x7ff, zero) +lb t6, (#0xfffff801, ra) +lb t6, (#0xfffffc00, ra) +lb t6, (#0xfffffe00, ra) +lb t6, (#0xffffff00, ra) +lb t6, (#0xffffff80, ra) +lb t6, (#0xffffffc0, ra) +lb t6, (#0xffffffe0, ra) +lb t6, (#0xfffffff0, ra) +lb t6, (#0xfffffff8, ra) +lb t6, (#0xfffffffc, ra) +lb t6, (#0xfffffffe, ra) +lb t6, (#0xffffffff, ra) +lb t6, (#0, ra) +lb t6, (#1, ra) +lb t6, (#2, ra) +lb t6, (#4, ra) +lb t6, (#8, ra) +lb t6, (#0x10, ra) +lb t6, (#0x20, ra) +lb t6, (#0x40, ra) +lb t6, (#0x80, ra) +lb t6, (#0x100, ra) +lb t6, (#0x200, ra) +lb t6, (#0x400, ra) +lb t6, (#0x7ff, ra) +lb t6, (#0xfffff801, t0) +lb t6, (#0xfffffc00, t0) +lb t6, (#0xfffffe00, t0) +lb t6, (#0xffffff00, t0) +lb t6, (#0xffffff80, t0) +lb t6, (#0xffffffc0, t0) +lb t6, (#0xffffffe0, t0) +lb t6, (#0xfffffff0, t0) +lb t6, (#0xfffffff8, t0) +lb t6, (#0xfffffffc, t0) +lb t6, (#0xfffffffe, t0) +lb t6, (#0xffffffff, t0) +lb t6, (#0, t0) +lb t6, (#1, t0) +lb t6, (#2, t0) +lb t6, (#4, t0) +lb t6, (#8, t0) +lb t6, (#0x10, t0) +lb t6, (#0x20, t0) +lb t6, (#0x40, t0) +lb t6, (#0x80, t0) +lb t6, (#0x100, t0) +lb t6, (#0x200, t0) +lb t6, (#0x400, t0) +lb t6, (#0x7ff, t0) +lb t6, (#0xfffff801, a0) +lb t6, (#0xfffffc00, a0) +lb t6, (#0xfffffe00, a0) +lb t6, (#0xffffff00, a0) +lb t6, (#0xffffff80, a0) +lb t6, (#0xffffffc0, a0) +lb t6, (#0xffffffe0, a0) +lb t6, (#0xfffffff0, a0) +lb t6, (#0xfffffff8, a0) +lb t6, (#0xfffffffc, a0) +lb t6, (#0xfffffffe, a0) +lb t6, (#0xffffffff, a0) +lb t6, (#0, a0) +lb t6, (#1, a0) +lb t6, (#2, a0) +lb t6, (#4, a0) +lb t6, (#8, a0) +lb t6, (#0x10, a0) +lb t6, (#0x20, a0) +lb t6, (#0x40, a0) +lb t6, (#0x80, a0) +lb t6, (#0x100, a0) +lb t6, (#0x200, a0) +lb t6, (#0x400, a0) +lb t6, (#0x7ff, a0) +lb t6, (#0xfffff801, a5) +lb t6, (#0xfffffc00, a5) +lb t6, (#0xfffffe00, a5) +lb t6, (#0xffffff00, a5) +lb t6, (#0xffffff80, a5) +lb t6, (#0xffffffc0, a5) +lb t6, (#0xffffffe0, a5) +lb t6, (#0xfffffff0, a5) +lb t6, (#0xfffffff8, a5) +lb t6, (#0xfffffffc, a5) +lb t6, (#0xfffffffe, a5) +lb t6, (#0xffffffff, a5) +lb t6, (#0, a5) +lb t6, (#1, a5) +lb t6, (#2, a5) +lb t6, (#4, a5) +lb t6, (#8, a5) +lb t6, (#0x10, a5) +lb t6, (#0x20, a5) +lb t6, (#0x40, a5) +lb t6, (#0x80, a5) +lb t6, (#0x100, a5) +lb t6, (#0x200, a5) +lb t6, (#0x400, a5) +lb t6, (#0x7ff, a5) +lb t6, (#0xfffff801, s4) +lb t6, (#0xfffffc00, s4) +lb t6, (#0xfffffe00, s4) +lb t6, (#0xffffff00, s4) +lb t6, (#0xffffff80, s4) +lb t6, (#0xffffffc0, s4) +lb t6, (#0xffffffe0, s4) +lb t6, (#0xfffffff0, s4) +lb t6, (#0xfffffff8, s4) +lb t6, (#0xfffffffc, s4) +lb t6, (#0xfffffffe, s4) +lb t6, (#0xffffffff, s4) +lb t6, (#0, s4) +lb t6, (#1, s4) +lb t6, (#2, s4) +lb t6, (#4, s4) +lb t6, (#8, s4) +lb t6, (#0x10, s4) +lb t6, (#0x20, s4) +lb t6, (#0x40, s4) +lb t6, (#0x80, s4) +lb t6, (#0x100, s4) +lb t6, (#0x200, s4) +lb t6, (#0x400, s4) +lb t6, (#0x7ff, s4) +lb t6, (#0xfffff801, s9) +lb t6, (#0xfffffc00, s9) +lb t6, (#0xfffffe00, s9) +lb t6, (#0xffffff00, s9) +lb t6, (#0xffffff80, s9) +lb t6, (#0xffffffc0, s9) +lb t6, (#0xffffffe0, s9) +lb t6, (#0xfffffff0, s9) +lb t6, (#0xfffffff8, s9) +lb t6, (#0xfffffffc, s9) +lb t6, (#0xfffffffe, s9) +lb t6, (#0xffffffff, s9) +lb t6, (#0, s9) +lb t6, (#1, s9) +lb t6, (#2, s9) +lb t6, (#4, s9) +lb t6, (#8, s9) +lb t6, (#0x10, s9) +lb t6, (#0x20, s9) +lb t6, (#0x40, s9) +lb t6, (#0x80, s9) +lb t6, (#0x100, s9) +lb t6, (#0x200, s9) +lb t6, (#0x400, s9) +lb t6, (#0x7ff, s9) +lb t6, (#0xfffff801, t6) +lb t6, (#0xfffffc00, t6) +lb t6, (#0xfffffe00, t6) +lb t6, (#0xffffff00, t6) +lb t6, (#0xffffff80, t6) +lb t6, (#0xffffffc0, t6) +lb t6, (#0xffffffe0, t6) +lb t6, (#0xfffffff0, t6) +lb t6, (#0xfffffff8, t6) +lb t6, (#0xfffffffc, t6) +lb t6, (#0xfffffffe, t6) +lb t6, (#0xffffffff, t6) +lb t6, (#0, t6) +lb t6, (#1, t6) +lb t6, (#2, t6) +lb t6, (#4, t6) +lb t6, (#8, t6) +lb t6, (#0x10, t6) +lb t6, (#0x20, t6) +lb t6, (#0x40, t6) +lb t6, (#0x80, t6) +lb t6, (#0x100, t6) +lb t6, (#0x200, t6) +lb t6, (#0x400, t6) +lb t6, (#0x7ff, t6) diff --git a/tests/riscv/rv32i/lbu.asm b/tests/riscv/rv32i/lbu.asm new file mode 100644 index 0000000..1ce3ddc --- /dev/null +++ b/tests/riscv/rv32i/lbu.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +lbu zero, (#-2047, zero) +lbu zero, (#-1024, zero) +lbu zero, (#-512, zero) +lbu zero, (#-256, zero) +lbu zero, (#-128, zero) +lbu zero, (#-64, zero) +lbu zero, (#-32, zero) +lbu zero, (#-16, zero) +lbu zero, (#-8, zero) +lbu zero, (#-4, zero) +lbu zero, (#-2, zero) +lbu zero, (#-1, zero) +lbu zero, (#0, zero) +lbu zero, (#1, zero) +lbu zero, (#2, zero) +lbu zero, (#4, zero) +lbu zero, (#8, zero) +lbu zero, (#16, zero) +lbu zero, (#32, zero) +lbu zero, (#64, zero) +lbu zero, (#128, zero) +lbu zero, (#256, zero) +lbu zero, (#512, zero) +lbu zero, (#1024, zero) +lbu zero, (#2047, zero) +lbu zero, (#-2047, ra) +lbu zero, (#-1024, ra) +lbu zero, (#-512, ra) +lbu zero, (#-256, ra) +lbu zero, (#-128, ra) +lbu zero, (#-64, ra) +lbu zero, (#-32, ra) +lbu zero, (#-16, ra) +lbu zero, (#-8, ra) +lbu zero, (#-4, ra) +lbu zero, (#-2, ra) +lbu zero, (#-1, ra) +lbu zero, (#0, ra) +lbu zero, (#1, ra) +lbu zero, (#2, ra) +lbu zero, (#4, ra) +lbu zero, (#8, ra) +lbu zero, (#16, ra) +lbu zero, (#32, ra) +lbu zero, (#64, ra) +lbu zero, (#128, ra) +lbu zero, (#256, ra) +lbu zero, (#512, ra) +lbu zero, (#1024, ra) +lbu zero, (#2047, ra) +lbu zero, (#-2047, t0) +lbu zero, (#-1024, t0) +lbu zero, (#-512, t0) +lbu zero, (#-256, t0) +lbu zero, (#-128, t0) +lbu zero, (#-64, t0) +lbu zero, (#-32, t0) +lbu zero, (#-16, t0) +lbu zero, (#-8, t0) +lbu zero, (#-4, t0) +lbu zero, (#-2, t0) +lbu zero, (#-1, t0) +lbu zero, (#0, t0) +lbu zero, (#1, t0) +lbu zero, (#2, t0) +lbu zero, (#4, t0) +lbu zero, (#8, t0) +lbu zero, (#16, t0) +lbu zero, (#32, t0) +lbu zero, (#64, t0) +lbu zero, (#128, t0) +lbu zero, (#256, t0) +lbu zero, (#512, t0) +lbu zero, (#1024, t0) +lbu zero, (#2047, t0) +lbu zero, (#-2047, a0) +lbu zero, (#-1024, a0) +lbu zero, (#-512, a0) +lbu zero, (#-256, a0) +lbu zero, (#-128, a0) +lbu zero, (#-64, a0) +lbu zero, (#-32, a0) +lbu zero, (#-16, a0) +lbu zero, (#-8, a0) +lbu zero, (#-4, a0) +lbu zero, (#-2, a0) +lbu zero, (#-1, a0) +lbu zero, (#0, a0) +lbu zero, (#1, a0) +lbu zero, (#2, a0) +lbu zero, (#4, a0) +lbu zero, (#8, a0) +lbu zero, (#16, a0) +lbu zero, (#32, a0) +lbu zero, (#64, a0) +lbu zero, (#128, a0) +lbu zero, (#256, a0) +lbu zero, (#512, a0) +lbu zero, (#1024, a0) +lbu zero, (#2047, a0) +lbu zero, (#-2047, a5) +lbu zero, (#-1024, a5) +lbu zero, (#-512, a5) +lbu zero, (#-256, a5) +lbu zero, (#-128, a5) +lbu zero, (#-64, a5) +lbu zero, (#-32, a5) +lbu zero, (#-16, a5) +lbu zero, (#-8, a5) +lbu zero, (#-4, a5) +lbu zero, (#-2, a5) +lbu zero, (#-1, a5) +lbu zero, (#0, a5) +lbu zero, (#1, a5) +lbu zero, (#2, a5) +lbu zero, (#4, a5) +lbu zero, (#8, a5) +lbu zero, (#16, a5) +lbu zero, (#32, a5) +lbu zero, (#64, a5) +lbu zero, (#128, a5) +lbu zero, (#256, a5) +lbu zero, (#512, a5) +lbu zero, (#1024, a5) +lbu zero, (#2047, a5) +lbu zero, (#-2047, s4) +lbu zero, (#-1024, s4) +lbu zero, (#-512, s4) +lbu zero, (#-256, s4) +lbu zero, (#-128, s4) +lbu zero, (#-64, s4) +lbu zero, (#-32, s4) +lbu zero, (#-16, s4) +lbu zero, (#-8, s4) +lbu zero, (#-4, s4) +lbu zero, (#-2, s4) +lbu zero, (#-1, s4) +lbu zero, (#0, s4) +lbu zero, (#1, s4) +lbu zero, (#2, s4) +lbu zero, (#4, s4) +lbu zero, (#8, s4) +lbu zero, (#16, s4) +lbu zero, (#32, s4) +lbu zero, (#64, s4) +lbu zero, (#128, s4) +lbu zero, (#256, s4) +lbu zero, (#512, s4) +lbu zero, (#1024, s4) +lbu zero, (#2047, s4) +lbu zero, (#-2047, s9) +lbu zero, (#-1024, s9) +lbu zero, (#-512, s9) +lbu zero, (#-256, s9) +lbu zero, (#-128, s9) +lbu zero, (#-64, s9) +lbu zero, (#-32, s9) +lbu zero, (#-16, s9) +lbu zero, (#-8, s9) +lbu zero, (#-4, s9) +lbu zero, (#-2, s9) +lbu zero, (#-1, s9) +lbu zero, (#0, s9) +lbu zero, (#1, s9) +lbu zero, (#2, s9) +lbu zero, (#4, s9) +lbu zero, (#8, s9) +lbu zero, (#16, s9) +lbu zero, (#32, s9) +lbu zero, (#64, s9) +lbu zero, (#128, s9) +lbu zero, (#256, s9) +lbu zero, (#512, s9) +lbu zero, (#1024, s9) +lbu zero, (#2047, s9) +lbu zero, (#-2047, t6) +lbu zero, (#-1024, t6) +lbu zero, (#-512, t6) +lbu zero, (#-256, t6) +lbu zero, (#-128, t6) +lbu zero, (#-64, t6) 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ra) +lbu a0, (#-128, ra) +lbu a0, (#-64, ra) +lbu a0, (#-32, ra) +lbu a0, (#-16, ra) +lbu a0, (#-8, ra) +lbu a0, (#-4, ra) +lbu a0, (#-2, ra) +lbu a0, (#-1, ra) +lbu a0, (#0, ra) +lbu a0, (#1, ra) +lbu a0, (#2, ra) +lbu a0, (#4, ra) +lbu a0, (#8, ra) +lbu a0, (#16, ra) +lbu a0, (#32, ra) +lbu a0, (#64, ra) +lbu a0, (#128, ra) +lbu a0, (#256, ra) +lbu a0, (#512, ra) +lbu a0, (#1024, ra) +lbu a0, (#2047, ra) +lbu a0, (#-2047, t0) +lbu a0, (#-1024, t0) +lbu a0, (#-512, t0) +lbu a0, (#-256, t0) +lbu a0, (#-128, t0) +lbu a0, (#-64, t0) +lbu a0, (#-32, t0) +lbu a0, (#-16, t0) +lbu a0, (#-8, t0) +lbu a0, (#-4, t0) +lbu a0, (#-2, t0) +lbu a0, (#-1, t0) +lbu a0, (#0, t0) +lbu a0, (#1, t0) +lbu a0, (#2, t0) +lbu a0, (#4, t0) +lbu a0, (#8, t0) +lbu a0, (#16, t0) +lbu a0, (#32, t0) +lbu a0, (#64, t0) +lbu a0, (#128, t0) +lbu a0, (#256, t0) +lbu a0, (#512, t0) +lbu a0, (#1024, t0) +lbu a0, (#2047, t0) +lbu a0, (#-2047, a0) +lbu a0, (#-1024, a0) +lbu a0, (#-512, a0) +lbu a0, (#-256, a0) +lbu a0, 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a0, (#-64, s4) +lbu a0, (#-32, s4) +lbu a0, (#-16, s4) +lbu a0, (#-8, s4) +lbu a0, (#-4, s4) +lbu a0, (#-2, s4) +lbu a0, (#-1, s4) +lbu a0, (#0, s4) +lbu a0, (#1, s4) +lbu a0, (#2, s4) +lbu a0, (#4, s4) +lbu a0, (#8, s4) +lbu a0, (#16, s4) +lbu a0, (#32, s4) +lbu a0, (#64, s4) +lbu a0, (#128, s4) +lbu a0, (#256, s4) +lbu a0, (#512, s4) +lbu a0, (#1024, s4) +lbu a0, (#2047, s4) +lbu a0, (#-2047, s9) +lbu a0, (#-1024, s9) +lbu a0, (#-512, s9) +lbu a0, (#-256, s9) +lbu a0, (#-128, s9) +lbu a0, (#-64, s9) +lbu a0, (#-32, s9) +lbu a0, (#-16, s9) +lbu a0, (#-8, s9) +lbu a0, (#-4, s9) +lbu a0, (#-2, s9) +lbu a0, (#-1, s9) +lbu a0, (#0, s9) +lbu a0, (#1, s9) +lbu a0, (#2, s9) +lbu a0, (#4, s9) +lbu a0, (#8, s9) +lbu a0, (#16, s9) +lbu a0, (#32, s9) +lbu a0, (#64, s9) +lbu a0, (#128, s9) +lbu a0, (#256, s9) +lbu a0, (#512, s9) +lbu a0, (#1024, s9) +lbu a0, (#2047, s9) +lbu a0, (#-2047, t6) +lbu a0, (#-1024, t6) +lbu a0, (#-512, t6) +lbu a0, (#-256, t6) +lbu a0, (#-128, t6) +lbu a0, (#-64, t6) +lbu a0, (#-32, t6) +lbu a0, (#-16, t6) +lbu a0, (#-8, t6) +lbu a0, (#-4, t6) +lbu a0, (#-2, t6) +lbu a0, (#-1, t6) +lbu a0, (#0, t6) +lbu a0, (#1, t6) +lbu a0, (#2, t6) +lbu a0, (#4, t6) +lbu a0, (#8, t6) +lbu a0, (#16, t6) +lbu a0, (#32, t6) +lbu a0, (#64, t6) +lbu a0, (#128, t6) +lbu a0, (#256, t6) +lbu a0, (#512, t6) +lbu a0, (#1024, t6) +lbu a0, (#2047, t6) +lbu a5, (#-2047, zero) +lbu a5, (#-1024, zero) +lbu a5, (#-512, zero) +lbu a5, (#-256, zero) +lbu a5, (#-128, zero) +lbu a5, (#-64, zero) +lbu a5, (#-32, zero) +lbu a5, (#-16, zero) +lbu a5, (#-8, zero) +lbu a5, (#-4, zero) +lbu a5, (#-2, zero) +lbu a5, (#-1, zero) +lbu a5, (#0, zero) +lbu a5, (#1, zero) +lbu a5, (#2, zero) +lbu a5, (#4, zero) +lbu a5, (#8, zero) +lbu a5, (#16, zero) +lbu a5, (#32, zero) +lbu a5, (#64, zero) +lbu a5, (#128, zero) +lbu a5, (#256, zero) +lbu a5, (#512, zero) +lbu a5, (#1024, zero) +lbu a5, (#2047, zero) +lbu a5, (#-2047, ra) +lbu a5, (#-1024, ra) +lbu a5, (#-512, ra) +lbu a5, (#-256, ra) +lbu a5, (#-128, ra) +lbu a5, (#-64, ra) +lbu a5, (#-32, ra) +lbu a5, (#-16, ra) +lbu a5, (#-8, ra) +lbu a5, (#-4, ra) +lbu a5, (#-2, ra) +lbu a5, (#-1, ra) +lbu a5, (#0, ra) +lbu a5, (#1, ra) +lbu a5, (#2, ra) +lbu a5, (#4, ra) +lbu a5, (#8, ra) +lbu a5, (#16, ra) +lbu a5, (#32, ra) +lbu a5, (#64, ra) +lbu a5, (#128, ra) +lbu a5, (#256, ra) +lbu a5, (#512, ra) +lbu a5, (#1024, ra) +lbu a5, (#2047, ra) +lbu a5, (#-2047, t0) +lbu a5, (#-1024, t0) +lbu a5, (#-512, t0) +lbu a5, (#-256, t0) +lbu a5, (#-128, t0) +lbu a5, (#-64, t0) +lbu a5, (#-32, t0) +lbu a5, (#-16, t0) +lbu a5, (#-8, t0) +lbu a5, (#-4, t0) +lbu a5, (#-2, t0) +lbu a5, (#-1, t0) +lbu a5, (#0, t0) +lbu a5, (#1, t0) +lbu a5, (#2, t0) +lbu a5, (#4, t0) +lbu a5, (#8, t0) +lbu a5, (#16, t0) +lbu a5, (#32, t0) +lbu a5, (#64, t0) +lbu a5, (#128, t0) +lbu a5, (#256, t0) +lbu a5, (#512, t0) +lbu a5, (#1024, t0) +lbu a5, (#2047, t0) +lbu a5, (#-2047, a0) +lbu a5, (#-1024, a0) +lbu a5, (#-512, a0) +lbu a5, (#-256, a0) +lbu a5, (#-128, a0) +lbu a5, (#-64, a0) +lbu a5, (#-32, a0) +lbu a5, (#-16, a0) +lbu a5, (#-8, a0) +lbu a5, (#-4, a0) +lbu a5, (#-2, a0) +lbu a5, (#-1, a0) +lbu a5, (#0, a0) +lbu a5, (#1, a0) +lbu a5, (#2, a0) +lbu a5, (#4, a0) +lbu a5, (#8, a0) +lbu a5, (#16, a0) +lbu a5, (#32, a0) +lbu a5, (#64, a0) +lbu a5, (#128, a0) +lbu a5, (#256, a0) +lbu a5, (#512, a0) +lbu a5, (#1024, a0) +lbu a5, (#2047, a0) +lbu a5, (#-2047, a5) +lbu a5, (#-1024, a5) +lbu a5, (#-512, a5) +lbu a5, (#-256, a5) +lbu a5, (#-128, a5) +lbu a5, (#-64, a5) +lbu a5, (#-32, a5) +lbu a5, (#-16, a5) +lbu a5, (#-8, a5) +lbu a5, (#-4, a5) +lbu a5, (#-2, a5) +lbu a5, (#-1, a5) +lbu a5, (#0, a5) +lbu a5, (#1, a5) +lbu a5, (#2, a5) +lbu a5, (#4, a5) +lbu a5, (#8, a5) +lbu a5, (#16, a5) +lbu a5, (#32, a5) +lbu a5, (#64, a5) +lbu a5, (#128, a5) +lbu a5, (#256, a5) +lbu a5, (#512, a5) +lbu a5, (#1024, a5) +lbu a5, (#2047, a5) +lbu a5, (#-2047, s4) +lbu a5, (#-1024, s4) +lbu a5, (#-512, s4) +lbu a5, (#-256, s4) +lbu a5, (#-128, s4) +lbu a5, (#-64, s4) +lbu a5, (#-32, s4) +lbu a5, (#-16, s4) +lbu a5, (#-8, s4) +lbu a5, (#-4, s4) +lbu a5, (#-2, s4) +lbu a5, (#-1, s4) +lbu a5, (#0, s4) +lbu a5, (#1, s4) +lbu a5, (#2, s4) +lbu a5, (#4, s4) +lbu a5, (#8, s4) +lbu a5, (#16, s4) +lbu a5, (#32, s4) +lbu a5, (#64, s4) +lbu a5, (#128, s4) +lbu a5, (#256, s4) +lbu a5, (#512, s4) +lbu a5, (#1024, s4) +lbu a5, (#2047, s4) +lbu a5, (#-2047, s9) +lbu a5, (#-1024, s9) +lbu a5, (#-512, s9) +lbu a5, (#-256, s9) +lbu a5, (#-128, s9) +lbu a5, (#-64, s9) +lbu a5, (#-32, s9) +lbu a5, (#-16, s9) +lbu a5, (#-8, s9) +lbu a5, (#-4, s9) +lbu a5, (#-2, s9) +lbu a5, (#-1, s9) +lbu a5, (#0, s9) +lbu a5, (#1, s9) +lbu a5, (#2, s9) +lbu a5, (#4, s9) +lbu a5, (#8, s9) +lbu a5, (#16, s9) +lbu a5, (#32, s9) +lbu a5, (#64, s9) +lbu a5, (#128, s9) +lbu a5, (#256, s9) +lbu a5, (#512, s9) +lbu a5, (#1024, s9) +lbu a5, (#2047, s9) +lbu a5, (#-2047, t6) +lbu a5, (#-1024, t6) +lbu a5, (#-512, t6) +lbu a5, (#-256, t6) +lbu a5, (#-128, t6) +lbu a5, (#-64, t6) +lbu a5, (#-32, t6) +lbu a5, (#-16, t6) +lbu a5, (#-8, t6) +lbu a5, (#-4, t6) +lbu a5, (#-2, t6) +lbu a5, (#-1, t6) +lbu a5, (#0, t6) +lbu a5, (#1, t6) +lbu a5, (#2, t6) +lbu a5, (#4, t6) +lbu a5, (#8, t6) +lbu a5, (#16, t6) +lbu a5, (#32, t6) +lbu a5, (#64, t6) +lbu a5, (#128, t6) +lbu a5, (#256, t6) +lbu a5, (#512, t6) +lbu a5, (#1024, t6) +lbu a5, (#2047, t6) +lbu s4, (#-2047, zero) +lbu s4, (#-1024, zero) +lbu s4, (#-512, zero) +lbu s4, (#-256, zero) +lbu s4, (#-128, zero) +lbu s4, (#-64, zero) +lbu s4, (#-32, zero) +lbu s4, (#-16, zero) +lbu s4, (#-8, zero) +lbu s4, (#-4, zero) +lbu s4, (#-2, zero) +lbu s4, (#-1, zero) +lbu s4, (#0, zero) +lbu s4, (#1, zero) +lbu s4, (#2, zero) +lbu s4, (#4, zero) +lbu s4, (#8, zero) +lbu s4, (#16, zero) +lbu s4, (#32, zero) +lbu s4, (#64, zero) +lbu s4, (#128, zero) +lbu s4, (#256, zero) +lbu s4, (#512, zero) +lbu s4, (#1024, zero) +lbu s4, (#2047, zero) +lbu s4, (#-2047, ra) +lbu s4, (#-1024, ra) +lbu s4, (#-512, ra) +lbu s4, (#-256, ra) +lbu s4, (#-128, ra) +lbu s4, (#-64, ra) +lbu s4, (#-32, ra) +lbu s4, (#-16, ra) +lbu s4, (#-8, ra) +lbu s4, (#-4, ra) +lbu s4, (#-2, ra) +lbu s4, (#-1, ra) +lbu s4, (#0, ra) +lbu s4, (#1, ra) +lbu s4, (#2, ra) +lbu s4, (#4, ra) +lbu s4, (#8, ra) +lbu s4, (#16, ra) +lbu s4, (#32, ra) +lbu s4, (#64, ra) +lbu s4, (#128, ra) +lbu s4, (#256, ra) +lbu s4, (#512, ra) +lbu s4, (#1024, ra) +lbu s4, (#2047, ra) +lbu s4, (#-2047, t0) +lbu s4, (#-1024, t0) +lbu s4, (#-512, t0) +lbu s4, (#-256, t0) +lbu s4, (#-128, t0) +lbu s4, (#-64, t0) +lbu s4, (#-32, t0) +lbu s4, (#-16, t0) +lbu s4, (#-8, t0) +lbu s4, (#-4, t0) +lbu s4, (#-2, t0) +lbu s4, (#-1, t0) +lbu s4, (#0, t0) +lbu s4, (#1, t0) +lbu s4, (#2, t0) +lbu s4, (#4, t0) +lbu s4, (#8, t0) +lbu s4, (#16, t0) +lbu s4, (#32, t0) +lbu s4, (#64, t0) +lbu s4, (#128, t0) +lbu s4, (#256, t0) +lbu s4, (#512, t0) +lbu s4, (#1024, t0) +lbu s4, (#2047, t0) +lbu s4, (#-2047, a0) +lbu s4, (#-1024, a0) +lbu s4, (#-512, a0) +lbu s4, (#-256, a0) +lbu s4, (#-128, a0) +lbu s4, (#-64, a0) +lbu s4, (#-32, a0) +lbu s4, (#-16, a0) +lbu s4, (#-8, a0) +lbu s4, (#-4, a0) +lbu s4, (#-2, a0) +lbu s4, (#-1, a0) +lbu s4, (#0, a0) +lbu s4, (#1, a0) +lbu s4, (#2, a0) +lbu s4, (#4, a0) +lbu s4, (#8, a0) +lbu s4, (#16, a0) +lbu s4, (#32, a0) +lbu s4, (#64, a0) +lbu s4, (#128, a0) +lbu s4, (#256, a0) +lbu s4, (#512, a0) +lbu s4, (#1024, a0) +lbu s4, (#2047, a0) +lbu s4, (#-2047, a5) +lbu s4, (#-1024, a5) +lbu s4, (#-512, a5) +lbu s4, (#-256, a5) +lbu s4, (#-128, a5) +lbu s4, (#-64, a5) +lbu s4, (#-32, a5) +lbu s4, (#-16, a5) +lbu s4, (#-8, a5) +lbu s4, (#-4, a5) +lbu s4, (#-2, a5) +lbu s4, (#-1, a5) +lbu s4, (#0, a5) +lbu s4, (#1, a5) +lbu s4, (#2, a5) +lbu s4, (#4, a5) +lbu s4, (#8, a5) +lbu s4, (#16, a5) +lbu s4, (#32, a5) +lbu s4, (#64, a5) +lbu s4, (#128, a5) +lbu s4, (#256, a5) +lbu s4, (#512, a5) +lbu s4, (#1024, a5) +lbu s4, (#2047, a5) +lbu s4, (#-2047, s4) +lbu s4, (#-1024, s4) +lbu s4, (#-512, s4) +lbu s4, (#-256, s4) +lbu s4, (#-128, s4) +lbu s4, (#-64, s4) +lbu s4, (#-32, s4) +lbu s4, (#-16, s4) +lbu s4, (#-8, s4) +lbu s4, (#-4, s4) +lbu s4, (#-2, s4) +lbu s4, (#-1, s4) +lbu s4, (#0, s4) +lbu s4, (#1, s4) +lbu s4, (#2, s4) +lbu s4, (#4, s4) +lbu s4, (#8, s4) +lbu s4, (#16, s4) +lbu s4, (#32, s4) +lbu s4, (#64, s4) +lbu s4, (#128, s4) +lbu s4, (#256, s4) +lbu s4, (#512, s4) +lbu s4, (#1024, s4) +lbu s4, (#2047, s4) +lbu s4, (#-2047, s9) +lbu s4, (#-1024, s9) +lbu s4, (#-512, s9) +lbu s4, (#-256, s9) +lbu s4, (#-128, s9) +lbu s4, (#-64, s9) +lbu s4, (#-32, s9) +lbu s4, (#-16, s9) +lbu s4, (#-8, s9) +lbu s4, (#-4, s9) +lbu s4, (#-2, s9) +lbu s4, (#-1, s9) +lbu s4, (#0, s9) +lbu s4, (#1, s9) +lbu s4, (#2, s9) +lbu s4, (#4, s9) +lbu s4, (#8, s9) +lbu s4, (#16, s9) +lbu s4, (#32, s9) +lbu s4, (#64, s9) +lbu s4, (#128, s9) +lbu s4, (#256, s9) +lbu s4, (#512, s9) +lbu s4, (#1024, s9) +lbu s4, (#2047, s9) +lbu s4, (#-2047, t6) +lbu s4, (#-1024, t6) +lbu s4, (#-512, t6) +lbu s4, (#-256, t6) +lbu s4, (#-128, t6) +lbu s4, (#-64, t6) +lbu s4, (#-32, t6) +lbu s4, (#-16, t6) +lbu s4, (#-8, t6) +lbu s4, (#-4, t6) +lbu s4, (#-2, t6) +lbu s4, (#-1, t6) +lbu s4, (#0, t6) +lbu s4, (#1, t6) +lbu s4, (#2, t6) +lbu s4, (#4, t6) +lbu s4, (#8, t6) +lbu s4, (#16, t6) +lbu s4, (#32, t6) +lbu s4, (#64, t6) +lbu s4, (#128, t6) +lbu s4, (#256, t6) +lbu s4, (#512, t6) +lbu s4, (#1024, t6) +lbu s4, (#2047, t6) +lbu s9, (#-2047, zero) +lbu s9, (#-1024, zero) +lbu s9, (#-512, zero) +lbu s9, (#-256, zero) +lbu s9, (#-128, zero) +lbu s9, (#-64, zero) +lbu s9, (#-32, zero) +lbu s9, (#-16, zero) +lbu s9, (#-8, zero) +lbu s9, (#-4, zero) +lbu s9, (#-2, zero) +lbu s9, (#-1, zero) +lbu s9, (#0, zero) +lbu s9, (#1, zero) +lbu s9, (#2, zero) +lbu s9, (#4, zero) +lbu s9, (#8, zero) +lbu s9, (#16, zero) +lbu s9, (#32, zero) +lbu s9, (#64, zero) +lbu s9, (#128, zero) +lbu s9, (#256, zero) +lbu s9, (#512, zero) +lbu s9, (#1024, zero) +lbu s9, (#2047, zero) +lbu s9, (#-2047, ra) +lbu s9, (#-1024, ra) +lbu s9, (#-512, ra) +lbu s9, (#-256, ra) +lbu s9, (#-128, ra) +lbu s9, (#-64, ra) +lbu s9, (#-32, ra) +lbu s9, (#-16, ra) +lbu s9, (#-8, ra) +lbu s9, (#-4, ra) +lbu s9, (#-2, ra) +lbu s9, (#-1, ra) +lbu s9, (#0, ra) +lbu s9, (#1, ra) +lbu s9, (#2, ra) +lbu s9, (#4, ra) +lbu s9, (#8, ra) +lbu s9, (#16, ra) +lbu s9, (#32, ra) +lbu s9, (#64, ra) +lbu s9, (#128, ra) +lbu s9, (#256, ra) +lbu s9, (#512, ra) +lbu s9, (#1024, ra) +lbu s9, (#2047, ra) +lbu s9, (#-2047, t0) +lbu s9, (#-1024, t0) +lbu s9, (#-512, t0) +lbu s9, (#-256, t0) +lbu s9, (#-128, t0) +lbu s9, (#-64, t0) +lbu s9, (#-32, t0) +lbu s9, (#-16, t0) +lbu s9, (#-8, t0) +lbu s9, (#-4, t0) +lbu s9, (#-2, t0) +lbu s9, (#-1, t0) +lbu s9, (#0, t0) +lbu s9, (#1, t0) +lbu s9, (#2, t0) +lbu s9, (#4, t0) +lbu s9, (#8, t0) +lbu s9, (#16, t0) +lbu s9, (#32, t0) +lbu s9, (#64, t0) +lbu s9, (#128, t0) +lbu s9, (#256, t0) +lbu s9, (#512, t0) +lbu s9, (#1024, t0) +lbu s9, (#2047, t0) +lbu s9, (#-2047, a0) +lbu s9, (#-1024, a0) +lbu s9, (#-512, a0) +lbu s9, (#-256, a0) +lbu s9, (#-128, a0) +lbu s9, (#-64, a0) +lbu s9, (#-32, a0) +lbu s9, (#-16, a0) +lbu s9, (#-8, a0) +lbu s9, (#-4, a0) +lbu s9, (#-2, a0) +lbu s9, (#-1, a0) +lbu s9, (#0, a0) +lbu s9, (#1, a0) +lbu s9, (#2, a0) +lbu s9, (#4, a0) +lbu s9, (#8, a0) +lbu s9, (#16, a0) +lbu s9, (#32, a0) +lbu s9, (#64, a0) +lbu s9, (#128, a0) +lbu s9, (#256, a0) +lbu s9, (#512, a0) +lbu s9, (#1024, a0) +lbu s9, (#2047, a0) +lbu s9, (#-2047, a5) +lbu s9, (#-1024, a5) +lbu s9, (#-512, a5) +lbu s9, (#-256, a5) +lbu s9, (#-128, a5) +lbu s9, (#-64, a5) +lbu s9, (#-32, a5) +lbu s9, (#-16, a5) +lbu s9, (#-8, a5) +lbu s9, (#-4, a5) +lbu s9, (#-2, a5) +lbu s9, (#-1, a5) +lbu s9, (#0, a5) +lbu s9, (#1, a5) +lbu s9, (#2, a5) +lbu s9, (#4, a5) +lbu s9, (#8, a5) +lbu s9, (#16, a5) +lbu s9, (#32, a5) +lbu s9, (#64, a5) +lbu s9, (#128, a5) +lbu s9, (#256, a5) +lbu s9, (#512, a5) +lbu s9, (#1024, a5) +lbu s9, (#2047, a5) +lbu s9, (#-2047, s4) +lbu s9, (#-1024, s4) +lbu s9, (#-512, s4) +lbu s9, (#-256, s4) +lbu s9, (#-128, s4) +lbu s9, (#-64, s4) +lbu s9, (#-32, s4) +lbu s9, (#-16, s4) +lbu s9, (#-8, s4) +lbu s9, (#-4, s4) +lbu s9, (#-2, s4) +lbu s9, (#-1, s4) +lbu s9, (#0, s4) +lbu s9, (#1, s4) +lbu s9, (#2, s4) +lbu s9, (#4, s4) +lbu s9, (#8, s4) +lbu s9, (#16, s4) +lbu s9, (#32, s4) +lbu s9, (#64, s4) +lbu s9, (#128, s4) +lbu s9, (#256, s4) +lbu s9, (#512, s4) +lbu s9, (#1024, s4) +lbu s9, (#2047, s4) +lbu s9, (#-2047, s9) +lbu s9, (#-1024, s9) +lbu s9, (#-512, s9) +lbu s9, (#-256, s9) +lbu s9, (#-128, s9) +lbu s9, (#-64, s9) +lbu s9, (#-32, s9) +lbu s9, (#-16, s9) +lbu s9, (#-8, s9) +lbu s9, (#-4, s9) +lbu s9, (#-2, s9) +lbu s9, (#-1, s9) +lbu s9, (#0, s9) +lbu s9, (#1, s9) +lbu s9, (#2, s9) +lbu s9, (#4, s9) +lbu s9, (#8, s9) +lbu s9, (#16, s9) +lbu s9, (#32, s9) +lbu s9, (#64, s9) +lbu s9, (#128, s9) +lbu s9, (#256, s9) +lbu s9, (#512, s9) +lbu s9, (#1024, s9) +lbu s9, (#2047, s9) +lbu s9, (#-2047, t6) +lbu s9, (#-1024, t6) +lbu s9, (#-512, t6) +lbu s9, (#-256, t6) +lbu s9, (#-128, t6) +lbu s9, (#-64, t6) +lbu s9, (#-32, t6) +lbu s9, (#-16, t6) +lbu s9, (#-8, t6) +lbu s9, (#-4, t6) +lbu s9, (#-2, t6) +lbu s9, (#-1, t6) +lbu s9, (#0, t6) +lbu s9, (#1, t6) +lbu s9, (#2, t6) +lbu s9, (#4, t6) +lbu s9, (#8, t6) +lbu s9, (#16, t6) +lbu s9, (#32, t6) +lbu s9, (#64, t6) +lbu s9, (#128, t6) +lbu s9, (#256, t6) +lbu s9, (#512, t6) +lbu s9, (#1024, t6) +lbu s9, (#2047, t6) +lbu t6, (#-2047, zero) +lbu t6, (#-1024, zero) +lbu t6, (#-512, zero) +lbu t6, (#-256, zero) +lbu t6, (#-128, zero) +lbu t6, (#-64, zero) +lbu t6, (#-32, zero) +lbu t6, (#-16, zero) +lbu t6, (#-8, zero) +lbu t6, (#-4, zero) +lbu t6, (#-2, zero) +lbu t6, (#-1, zero) +lbu t6, (#0, zero) +lbu t6, (#1, zero) +lbu t6, (#2, zero) +lbu t6, (#4, zero) +lbu t6, (#8, zero) +lbu t6, (#16, zero) +lbu t6, (#32, zero) +lbu t6, (#64, zero) +lbu t6, (#128, zero) +lbu t6, (#256, zero) +lbu t6, (#512, zero) +lbu t6, (#1024, zero) +lbu t6, (#2047, zero) +lbu t6, (#-2047, ra) +lbu t6, (#-1024, ra) +lbu t6, (#-512, ra) +lbu t6, (#-256, ra) +lbu t6, (#-128, ra) +lbu t6, (#-64, ra) +lbu t6, (#-32, ra) +lbu t6, (#-16, ra) +lbu t6, (#-8, ra) +lbu t6, (#-4, ra) +lbu t6, (#-2, ra) +lbu t6, (#-1, ra) +lbu t6, (#0, ra) +lbu t6, (#1, ra) +lbu t6, (#2, ra) +lbu t6, (#4, ra) +lbu t6, (#8, ra) +lbu t6, (#16, ra) +lbu t6, (#32, ra) +lbu t6, (#64, ra) +lbu t6, (#128, ra) +lbu t6, (#256, ra) +lbu t6, (#512, ra) +lbu t6, (#1024, ra) +lbu t6, (#2047, ra) +lbu t6, (#-2047, t0) +lbu t6, (#-1024, t0) +lbu t6, (#-512, t0) +lbu t6, (#-256, t0) +lbu t6, (#-128, t0) +lbu t6, (#-64, t0) +lbu t6, (#-32, t0) +lbu t6, (#-16, t0) +lbu t6, (#-8, t0) +lbu t6, (#-4, t0) +lbu t6, (#-2, t0) +lbu t6, (#-1, t0) +lbu t6, (#0, t0) +lbu t6, (#1, t0) +lbu t6, (#2, t0) +lbu t6, (#4, t0) +lbu t6, (#8, t0) +lbu t6, (#16, t0) +lbu t6, (#32, t0) +lbu t6, (#64, t0) +lbu t6, (#128, t0) +lbu t6, (#256, t0) +lbu t6, (#512, t0) +lbu t6, (#1024, t0) +lbu t6, (#2047, t0) +lbu t6, (#-2047, a0) +lbu t6, (#-1024, a0) +lbu t6, (#-512, a0) +lbu t6, (#-256, a0) +lbu t6, (#-128, a0) +lbu t6, (#-64, a0) +lbu t6, (#-32, a0) +lbu t6, (#-16, a0) +lbu t6, (#-8, a0) +lbu t6, (#-4, a0) +lbu t6, (#-2, a0) +lbu t6, (#-1, a0) +lbu t6, (#0, a0) +lbu t6, (#1, a0) +lbu t6, (#2, a0) +lbu t6, (#4, a0) +lbu t6, (#8, a0) +lbu t6, (#16, a0) +lbu t6, (#32, a0) +lbu t6, (#64, a0) +lbu t6, (#128, a0) +lbu t6, (#256, a0) +lbu t6, (#512, a0) +lbu t6, (#1024, a0) +lbu t6, (#2047, a0) +lbu t6, (#-2047, a5) +lbu t6, (#-1024, a5) +lbu t6, (#-512, a5) +lbu t6, (#-256, a5) +lbu t6, (#-128, a5) +lbu t6, (#-64, a5) +lbu t6, (#-32, a5) +lbu t6, (#-16, a5) +lbu t6, (#-8, a5) +lbu t6, (#-4, a5) +lbu t6, (#-2, a5) +lbu t6, (#-1, a5) +lbu t6, (#0, a5) +lbu t6, (#1, a5) +lbu t6, (#2, a5) +lbu t6, (#4, a5) +lbu t6, (#8, a5) +lbu t6, (#16, a5) +lbu t6, (#32, a5) +lbu t6, (#64, a5) +lbu t6, (#128, a5) +lbu t6, (#256, a5) +lbu t6, (#512, a5) +lbu t6, (#1024, a5) +lbu t6, (#2047, a5) +lbu t6, (#-2047, s4) +lbu t6, (#-1024, s4) +lbu t6, (#-512, s4) +lbu t6, (#-256, s4) +lbu t6, (#-128, s4) +lbu t6, (#-64, s4) +lbu t6, (#-32, s4) +lbu t6, (#-16, s4) +lbu t6, (#-8, s4) +lbu t6, (#-4, s4) +lbu t6, (#-2, s4) +lbu t6, (#-1, s4) +lbu t6, (#0, s4) +lbu t6, (#1, s4) +lbu t6, (#2, s4) +lbu t6, (#4, s4) +lbu t6, (#8, s4) +lbu t6, (#16, s4) +lbu t6, (#32, s4) +lbu t6, (#64, s4) +lbu t6, (#128, s4) +lbu t6, (#256, s4) +lbu t6, (#512, s4) +lbu t6, (#1024, s4) +lbu t6, (#2047, s4) +lbu t6, (#-2047, s9) +lbu t6, (#-1024, s9) +lbu t6, (#-512, s9) +lbu t6, (#-256, s9) +lbu t6, (#-128, s9) +lbu t6, (#-64, s9) +lbu t6, (#-32, s9) +lbu t6, (#-16, s9) +lbu t6, (#-8, s9) +lbu t6, (#-4, s9) +lbu t6, (#-2, s9) +lbu t6, (#-1, s9) +lbu t6, (#0, s9) +lbu t6, (#1, s9) +lbu t6, (#2, s9) +lbu t6, (#4, s9) +lbu t6, (#8, s9) +lbu t6, (#16, s9) +lbu t6, (#32, s9) +lbu t6, (#64, s9) +lbu t6, (#128, s9) +lbu t6, (#256, s9) +lbu t6, (#512, s9) +lbu t6, (#1024, s9) +lbu t6, (#2047, s9) +lbu t6, (#-2047, t6) +lbu t6, (#-1024, t6) +lbu t6, (#-512, t6) +lbu t6, (#-256, t6) +lbu t6, (#-128, t6) +lbu t6, (#-64, t6) +lbu t6, (#-32, t6) +lbu t6, (#-16, t6) +lbu t6, (#-8, t6) +lbu t6, (#-4, t6) +lbu t6, (#-2, t6) +lbu t6, (#-1, t6) +lbu t6, (#0, t6) +lbu t6, (#1, t6) +lbu t6, (#2, t6) +lbu t6, (#4, t6) +lbu t6, (#8, t6) +lbu t6, (#16, t6) +lbu t6, (#32, t6) +lbu t6, (#64, t6) +lbu t6, (#128, t6) +lbu t6, (#256, t6) +lbu t6, (#512, t6) +lbu t6, (#1024, t6) +lbu t6, (#2047, t6) + diff --git a/tests/riscv/rv32i/lbu.bin b/tests/riscv/rv32i/lbu.bin new file mode 100644 index 0000000000000000000000000000000000000000..ef50dd7d6a0874bab9bde00b21d35208d3cb0c5b GIT binary patch literal 6400 zcmWmGVaMH2y2kNLcDK~F*)<%8<1kyPQl(!ZLWBtUNc+*KQl(!h7RzE;tgjHm7{)L) zjHyw5=GPbhH?8}*_8qzMzfb+Er&HhTIPe`m@DsoAeCnUDyX_v9f*k$Z8b{V^jUB)hBm$A#(W$ZF`8M};K#x7%*vCG(H>@s#4yNq4N zE@S_l@yDmr-tIUcqm|LhXl1ni=0^nl8UIAvn89ld_=r|UE2EXs%4lV@cl2f+r~ZGQ zPW^eu0nh5}S)DzrvuAboY(634FZdVEjTyYbh)+0sR%g%Z>{*>XtFvcyzN0tuIPL%Y zblSTe2kg<=qq9e6kIwJ@jD)}9-{=}Mc#8?2(b=Q3M`w@D9-Te9J9;yZQ~!TYr~b0z zfITkuxY*-jkBi^^1sQ+Ce{gBc;2mas!NndIdtB^svB$+8mpghhkJJADPpAF5FKoJb{vp#lW~)A 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z`myTAsvoO`myTAsvoOPOX&dTq?$Jr;b0epLOa`cd_x>POX&svlK9s(w`csQOX$qv}W1kE$P4 qKdOFI{iym;^`q)X)sLzlRX?hJRQ;&>QT3zhN7aw2A5}l<^W(n-RT;+s literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/lbu.disasm b/tests/riscv/rv32i/lbu.disasm new file mode 100644 index 0000000..7e9a46d --- /dev/null +++ b/tests/riscv/rv32i/lbu.disasm @@ -0,0 +1,1600 @@ +lbu zero, (#0xfffff801, zero) +lbu zero, (#0xfffffc00, zero) +lbu zero, (#0xfffffe00, zero) +lbu zero, (#0xffffff00, zero) +lbu zero, (#0xffffff80, zero) +lbu zero, (#0xffffffc0, zero) +lbu zero, (#0xffffffe0, zero) +lbu zero, (#0xfffffff0, zero) +lbu zero, (#0xfffffff8, zero) +lbu zero, (#0xfffffffc, zero) +lbu zero, (#0xfffffffe, zero) +lbu zero, (#0xffffffff, zero) +lbu zero, (#0, zero) +lbu zero, (#1, zero) +lbu zero, (#2, zero) +lbu zero, (#4, zero) +lbu zero, (#8, zero) +lbu zero, (#0x10, zero) +lbu zero, (#0x20, zero) +lbu zero, (#0x40, zero) +lbu zero, (#0x80, zero) +lbu zero, (#0x100, zero) +lbu zero, (#0x200, zero) +lbu zero, (#0x400, zero) +lbu zero, (#0x7ff, zero) +lbu zero, (#0xfffff801, ra) +lbu zero, (#0xfffffc00, ra) +lbu zero, (#0xfffffe00, ra) +lbu zero, (#0xffffff00, ra) +lbu zero, (#0xffffff80, ra) +lbu zero, (#0xffffffc0, ra) +lbu zero, (#0xffffffe0, ra) +lbu zero, (#0xfffffff0, ra) +lbu zero, (#0xfffffff8, ra) +lbu zero, (#0xfffffffc, ra) +lbu zero, (#0xfffffffe, ra) +lbu zero, (#0xffffffff, ra) +lbu zero, (#0, ra) +lbu zero, (#1, ra) +lbu zero, (#2, ra) +lbu zero, (#4, ra) +lbu zero, (#8, ra) +lbu zero, (#0x10, ra) +lbu zero, (#0x20, ra) +lbu zero, (#0x40, ra) +lbu zero, (#0x80, ra) +lbu zero, (#0x100, ra) +lbu zero, (#0x200, ra) +lbu zero, (#0x400, ra) +lbu zero, (#0x7ff, ra) +lbu zero, (#0xfffff801, t0) +lbu zero, (#0xfffffc00, t0) +lbu zero, (#0xfffffe00, t0) +lbu zero, (#0xffffff00, t0) +lbu zero, (#0xffffff80, t0) +lbu zero, (#0xffffffc0, t0) +lbu zero, (#0xffffffe0, t0) +lbu zero, (#0xfffffff0, t0) +lbu zero, (#0xfffffff8, t0) +lbu zero, (#0xfffffffc, t0) +lbu zero, (#0xfffffffe, t0) +lbu zero, (#0xffffffff, t0) +lbu zero, (#0, t0) +lbu zero, (#1, t0) +lbu zero, (#2, t0) +lbu zero, (#4, t0) +lbu zero, (#8, t0) +lbu zero, (#0x10, t0) +lbu zero, (#0x20, t0) +lbu zero, (#0x40, t0) +lbu zero, (#0x80, t0) +lbu zero, (#0x100, t0) +lbu zero, (#0x200, t0) +lbu zero, (#0x400, t0) +lbu zero, (#0x7ff, t0) +lbu zero, (#0xfffff801, a0) +lbu zero, (#0xfffffc00, a0) +lbu zero, (#0xfffffe00, a0) +lbu zero, (#0xffffff00, a0) +lbu zero, (#0xffffff80, a0) +lbu zero, (#0xffffffc0, a0) +lbu zero, (#0xffffffe0, a0) +lbu zero, (#0xfffffff0, a0) +lbu zero, (#0xfffffff8, a0) +lbu zero, (#0xfffffffc, a0) +lbu zero, (#0xfffffffe, a0) +lbu zero, (#0xffffffff, a0) +lbu zero, (#0, a0) +lbu zero, (#1, a0) +lbu zero, (#2, a0) +lbu zero, (#4, a0) +lbu zero, (#8, a0) +lbu zero, (#0x10, a0) +lbu zero, (#0x20, a0) +lbu zero, (#0x40, a0) +lbu zero, (#0x80, a0) +lbu zero, (#0x100, a0) +lbu zero, (#0x200, a0) +lbu zero, (#0x400, a0) +lbu zero, (#0x7ff, a0) +lbu zero, (#0xfffff801, a5) +lbu zero, (#0xfffffc00, a5) +lbu zero, (#0xfffffe00, a5) +lbu zero, (#0xffffff00, a5) +lbu zero, (#0xffffff80, a5) +lbu zero, (#0xffffffc0, a5) +lbu zero, (#0xffffffe0, a5) +lbu zero, (#0xfffffff0, a5) +lbu zero, (#0xfffffff8, a5) +lbu zero, (#0xfffffffc, a5) +lbu zero, (#0xfffffffe, a5) +lbu zero, (#0xffffffff, a5) +lbu zero, (#0, a5) +lbu zero, (#1, a5) +lbu zero, (#2, a5) +lbu zero, (#4, a5) +lbu zero, (#8, a5) +lbu zero, (#0x10, a5) +lbu zero, (#0x20, a5) +lbu zero, (#0x40, a5) +lbu zero, (#0x80, a5) +lbu zero, (#0x100, a5) +lbu zero, (#0x200, a5) +lbu zero, (#0x400, a5) +lbu zero, (#0x7ff, a5) +lbu zero, (#0xfffff801, s4) +lbu zero, (#0xfffffc00, s4) +lbu zero, (#0xfffffe00, s4) +lbu zero, (#0xffffff00, s4) +lbu zero, (#0xffffff80, s4) +lbu zero, (#0xffffffc0, s4) +lbu zero, (#0xffffffe0, s4) +lbu zero, (#0xfffffff0, s4) +lbu zero, (#0xfffffff8, s4) +lbu zero, (#0xfffffffc, s4) +lbu zero, (#0xfffffffe, s4) +lbu zero, (#0xffffffff, s4) +lbu zero, (#0, s4) +lbu zero, (#1, s4) +lbu zero, (#2, s4) +lbu zero, (#4, s4) +lbu zero, (#8, s4) +lbu zero, (#0x10, s4) +lbu zero, (#0x20, s4) +lbu zero, (#0x40, s4) +lbu zero, (#0x80, s4) +lbu zero, (#0x100, s4) +lbu zero, (#0x200, s4) +lbu zero, (#0x400, s4) +lbu zero, (#0x7ff, s4) +lbu zero, (#0xfffff801, s9) +lbu zero, (#0xfffffc00, s9) +lbu zero, (#0xfffffe00, s9) +lbu zero, (#0xffffff00, s9) +lbu zero, (#0xffffff80, s9) +lbu zero, (#0xffffffc0, s9) +lbu zero, (#0xffffffe0, s9) +lbu zero, (#0xfffffff0, s9) +lbu zero, (#0xfffffff8, s9) +lbu zero, (#0xfffffffc, s9) +lbu zero, (#0xfffffffe, s9) +lbu zero, (#0xffffffff, s9) +lbu zero, (#0, s9) +lbu zero, (#1, s9) +lbu zero, (#2, s9) +lbu zero, (#4, s9) +lbu zero, (#8, s9) +lbu zero, (#0x10, s9) +lbu zero, (#0x20, s9) +lbu zero, (#0x40, s9) +lbu zero, (#0x80, s9) +lbu zero, (#0x100, s9) +lbu zero, (#0x200, s9) +lbu zero, (#0x400, s9) +lbu zero, (#0x7ff, s9) +lbu zero, (#0xfffff801, t6) +lbu zero, (#0xfffffc00, t6) +lbu zero, (#0xfffffe00, t6) +lbu zero, (#0xffffff00, t6) +lbu zero, (#0xffffff80, t6) +lbu zero, (#0xffffffc0, t6) +lbu zero, (#0xffffffe0, t6) +lbu zero, (#0xfffffff0, t6) +lbu zero, (#0xfffffff8, t6) +lbu zero, (#0xfffffffc, t6) +lbu zero, (#0xfffffffe, t6) +lbu zero, (#0xffffffff, t6) +lbu zero, (#0, t6) +lbu zero, (#1, t6) +lbu zero, (#2, t6) +lbu zero, (#4, t6) +lbu zero, (#8, t6) +lbu zero, (#0x10, t6) +lbu zero, (#0x20, t6) +lbu zero, (#0x40, t6) +lbu zero, (#0x80, t6) +lbu zero, (#0x100, t6) +lbu zero, (#0x200, t6) +lbu zero, (#0x400, t6) +lbu zero, (#0x7ff, t6) +lbu ra, (#0xfffff801, zero) +lbu ra, (#0xfffffc00, zero) +lbu ra, (#0xfffffe00, zero) +lbu ra, (#0xffffff00, zero) +lbu ra, (#0xffffff80, zero) +lbu ra, (#0xffffffc0, zero) +lbu ra, (#0xffffffe0, zero) +lbu ra, (#0xfffffff0, zero) +lbu ra, (#0xfffffff8, zero) +lbu ra, (#0xfffffffc, zero) +lbu ra, (#0xfffffffe, zero) +lbu ra, (#0xffffffff, zero) +lbu ra, (#0, zero) +lbu ra, (#1, zero) +lbu ra, (#2, zero) +lbu ra, (#4, zero) +lbu ra, (#8, zero) +lbu ra, (#0x10, zero) +lbu ra, (#0x20, zero) +lbu ra, (#0x40, zero) +lbu ra, (#0x80, zero) +lbu ra, (#0x100, zero) +lbu ra, (#0x200, zero) +lbu ra, (#0x400, zero) +lbu ra, (#0x7ff, zero) +lbu ra, (#0xfffff801, ra) +lbu ra, (#0xfffffc00, ra) +lbu ra, (#0xfffffe00, ra) +lbu ra, (#0xffffff00, ra) +lbu ra, (#0xffffff80, ra) +lbu ra, (#0xffffffc0, ra) +lbu ra, (#0xffffffe0, ra) +lbu ra, (#0xfffffff0, ra) +lbu ra, (#0xfffffff8, ra) +lbu ra, (#0xfffffffc, ra) +lbu ra, (#0xfffffffe, ra) +lbu ra, (#0xffffffff, ra) +lbu ra, (#0, ra) +lbu ra, (#1, ra) +lbu ra, (#2, ra) +lbu ra, (#4, ra) +lbu ra, (#8, ra) +lbu ra, (#0x10, ra) +lbu ra, (#0x20, ra) +lbu ra, (#0x40, ra) +lbu ra, (#0x80, ra) +lbu ra, (#0x100, ra) +lbu ra, (#0x200, ra) +lbu ra, (#0x400, ra) +lbu ra, (#0x7ff, ra) +lbu ra, (#0xfffff801, t0) +lbu ra, (#0xfffffc00, t0) +lbu ra, (#0xfffffe00, t0) +lbu ra, (#0xffffff00, t0) +lbu ra, (#0xffffff80, t0) +lbu ra, (#0xffffffc0, t0) +lbu ra, (#0xffffffe0, t0) +lbu ra, (#0xfffffff0, t0) +lbu ra, (#0xfffffff8, t0) +lbu ra, (#0xfffffffc, t0) +lbu ra, (#0xfffffffe, t0) +lbu ra, (#0xffffffff, t0) +lbu ra, (#0, t0) +lbu ra, (#1, t0) +lbu ra, (#2, t0) +lbu ra, (#4, t0) +lbu ra, (#8, t0) +lbu ra, (#0x10, t0) +lbu ra, (#0x20, t0) +lbu ra, (#0x40, t0) +lbu ra, (#0x80, t0) +lbu ra, (#0x100, t0) +lbu ra, (#0x200, t0) +lbu ra, (#0x400, t0) +lbu ra, (#0x7ff, t0) +lbu ra, (#0xfffff801, a0) +lbu ra, (#0xfffffc00, a0) +lbu ra, (#0xfffffe00, a0) +lbu ra, (#0xffffff00, a0) +lbu ra, (#0xffffff80, a0) +lbu ra, (#0xffffffc0, a0) +lbu ra, (#0xffffffe0, a0) +lbu ra, (#0xfffffff0, a0) +lbu ra, (#0xfffffff8, a0) +lbu ra, (#0xfffffffc, a0) +lbu ra, (#0xfffffffe, a0) +lbu ra, (#0xffffffff, a0) +lbu ra, (#0, a0) +lbu ra, (#1, a0) +lbu ra, (#2, a0) +lbu ra, (#4, a0) +lbu ra, (#8, a0) +lbu ra, (#0x10, a0) +lbu ra, (#0x20, a0) +lbu ra, (#0x40, a0) +lbu ra, (#0x80, a0) +lbu ra, (#0x100, a0) +lbu ra, (#0x200, a0) +lbu ra, (#0x400, a0) +lbu ra, (#0x7ff, a0) +lbu ra, (#0xfffff801, a5) +lbu ra, (#0xfffffc00, a5) +lbu ra, (#0xfffffe00, a5) +lbu ra, (#0xffffff00, a5) +lbu ra, (#0xffffff80, a5) +lbu ra, (#0xffffffc0, a5) +lbu ra, (#0xffffffe0, a5) +lbu ra, (#0xfffffff0, a5) +lbu ra, (#0xfffffff8, a5) +lbu ra, (#0xfffffffc, a5) +lbu ra, (#0xfffffffe, a5) +lbu ra, (#0xffffffff, a5) +lbu ra, (#0, a5) +lbu ra, (#1, a5) +lbu ra, (#2, a5) +lbu ra, (#4, a5) +lbu ra, (#8, a5) +lbu ra, (#0x10, a5) +lbu ra, (#0x20, a5) +lbu ra, (#0x40, a5) +lbu ra, (#0x80, a5) +lbu ra, (#0x100, a5) +lbu ra, (#0x200, a5) +lbu ra, (#0x400, a5) +lbu ra, (#0x7ff, a5) +lbu ra, (#0xfffff801, s4) +lbu ra, (#0xfffffc00, s4) +lbu ra, (#0xfffffe00, s4) +lbu ra, (#0xffffff00, s4) +lbu ra, (#0xffffff80, s4) +lbu ra, (#0xffffffc0, s4) +lbu ra, (#0xffffffe0, s4) +lbu ra, (#0xfffffff0, s4) +lbu ra, (#0xfffffff8, s4) +lbu ra, (#0xfffffffc, s4) +lbu ra, (#0xfffffffe, s4) +lbu ra, (#0xffffffff, s4) +lbu ra, (#0, s4) +lbu ra, (#1, s4) +lbu ra, (#2, s4) +lbu ra, (#4, s4) +lbu ra, (#8, s4) +lbu ra, (#0x10, s4) +lbu ra, (#0x20, s4) +lbu ra, (#0x40, s4) +lbu ra, (#0x80, s4) +lbu ra, (#0x100, s4) +lbu ra, (#0x200, s4) +lbu ra, (#0x400, s4) +lbu ra, (#0x7ff, s4) +lbu ra, (#0xfffff801, s9) +lbu ra, (#0xfffffc00, s9) +lbu ra, (#0xfffffe00, s9) +lbu ra, (#0xffffff00, s9) +lbu ra, (#0xffffff80, s9) +lbu ra, (#0xffffffc0, s9) +lbu ra, (#0xffffffe0, s9) +lbu ra, (#0xfffffff0, s9) +lbu ra, (#0xfffffff8, s9) +lbu ra, (#0xfffffffc, s9) +lbu ra, (#0xfffffffe, s9) +lbu ra, (#0xffffffff, s9) +lbu ra, (#0, s9) +lbu ra, (#1, s9) +lbu ra, (#2, s9) +lbu ra, (#4, s9) +lbu ra, (#8, s9) +lbu ra, (#0x10, s9) +lbu ra, (#0x20, s9) +lbu ra, (#0x40, s9) +lbu ra, (#0x80, s9) +lbu ra, (#0x100, s9) +lbu ra, (#0x200, s9) +lbu ra, (#0x400, s9) +lbu ra, (#0x7ff, s9) +lbu ra, (#0xfffff801, t6) +lbu ra, (#0xfffffc00, t6) +lbu ra, (#0xfffffe00, t6) +lbu ra, (#0xffffff00, t6) +lbu ra, (#0xffffff80, t6) +lbu ra, (#0xffffffc0, t6) +lbu ra, (#0xffffffe0, t6) +lbu ra, (#0xfffffff0, t6) +lbu ra, (#0xfffffff8, t6) +lbu ra, (#0xfffffffc, t6) +lbu ra, (#0xfffffffe, t6) +lbu ra, (#0xffffffff, t6) +lbu ra, (#0, t6) +lbu ra, (#1, t6) +lbu ra, (#2, t6) +lbu ra, (#4, t6) +lbu ra, (#8, t6) +lbu ra, (#0x10, t6) +lbu ra, (#0x20, t6) +lbu ra, (#0x40, t6) +lbu ra, (#0x80, t6) +lbu ra, (#0x100, t6) +lbu ra, (#0x200, t6) +lbu ra, (#0x400, t6) +lbu ra, (#0x7ff, t6) +lbu t0, (#0xfffff801, zero) +lbu t0, (#0xfffffc00, zero) +lbu t0, (#0xfffffe00, zero) +lbu t0, (#0xffffff00, zero) +lbu t0, (#0xffffff80, zero) +lbu t0, (#0xffffffc0, zero) +lbu t0, (#0xffffffe0, zero) +lbu t0, (#0xfffffff0, zero) +lbu t0, (#0xfffffff8, zero) +lbu t0, (#0xfffffffc, zero) +lbu t0, (#0xfffffffe, zero) +lbu t0, (#0xffffffff, zero) +lbu t0, (#0, zero) +lbu t0, (#1, zero) +lbu t0, (#2, zero) +lbu t0, (#4, zero) +lbu t0, (#8, zero) +lbu t0, (#0x10, zero) +lbu t0, (#0x20, zero) +lbu t0, (#0x40, zero) +lbu t0, (#0x80, zero) +lbu t0, (#0x100, zero) +lbu t0, (#0x200, zero) +lbu t0, (#0x400, zero) +lbu t0, (#0x7ff, zero) +lbu t0, (#0xfffff801, ra) +lbu t0, (#0xfffffc00, ra) +lbu t0, (#0xfffffe00, ra) +lbu t0, (#0xffffff00, ra) +lbu t0, (#0xffffff80, ra) +lbu t0, (#0xffffffc0, ra) +lbu t0, (#0xffffffe0, ra) +lbu t0, (#0xfffffff0, ra) +lbu t0, (#0xfffffff8, ra) +lbu t0, (#0xfffffffc, ra) +lbu t0, (#0xfffffffe, ra) +lbu t0, (#0xffffffff, ra) +lbu t0, (#0, ra) +lbu t0, (#1, ra) +lbu t0, (#2, ra) +lbu t0, (#4, ra) +lbu t0, (#8, ra) +lbu t0, (#0x10, ra) +lbu t0, (#0x20, ra) +lbu t0, (#0x40, ra) +lbu t0, (#0x80, ra) +lbu t0, (#0x100, ra) +lbu t0, (#0x200, ra) +lbu t0, (#0x400, ra) +lbu t0, (#0x7ff, ra) +lbu t0, (#0xfffff801, t0) +lbu t0, (#0xfffffc00, t0) +lbu t0, (#0xfffffe00, t0) +lbu t0, (#0xffffff00, t0) +lbu t0, (#0xffffff80, t0) +lbu t0, (#0xffffffc0, t0) +lbu t0, (#0xffffffe0, t0) +lbu t0, (#0xfffffff0, t0) +lbu t0, (#0xfffffff8, t0) +lbu t0, (#0xfffffffc, t0) +lbu t0, (#0xfffffffe, t0) +lbu t0, (#0xffffffff, t0) +lbu t0, (#0, t0) +lbu t0, (#1, t0) +lbu t0, (#2, t0) +lbu t0, (#4, t0) +lbu t0, (#8, t0) +lbu t0, (#0x10, t0) +lbu t0, (#0x20, t0) +lbu t0, (#0x40, t0) +lbu t0, (#0x80, t0) +lbu t0, (#0x100, t0) +lbu t0, (#0x200, t0) +lbu t0, (#0x400, t0) +lbu t0, (#0x7ff, t0) +lbu t0, (#0xfffff801, a0) +lbu t0, (#0xfffffc00, a0) +lbu t0, (#0xfffffe00, a0) +lbu t0, (#0xffffff00, a0) +lbu t0, (#0xffffff80, a0) +lbu t0, (#0xffffffc0, a0) +lbu t0, (#0xffffffe0, a0) +lbu t0, (#0xfffffff0, a0) +lbu t0, (#0xfffffff8, a0) +lbu t0, (#0xfffffffc, a0) +lbu t0, (#0xfffffffe, a0) +lbu t0, (#0xffffffff, a0) +lbu t0, (#0, a0) +lbu t0, (#1, a0) +lbu t0, (#2, a0) +lbu t0, (#4, a0) +lbu t0, (#8, a0) +lbu t0, (#0x10, a0) +lbu t0, (#0x20, a0) +lbu t0, (#0x40, a0) +lbu t0, (#0x80, a0) +lbu t0, (#0x100, a0) +lbu t0, (#0x200, a0) +lbu t0, (#0x400, a0) +lbu t0, (#0x7ff, a0) +lbu t0, (#0xfffff801, a5) +lbu t0, (#0xfffffc00, a5) +lbu t0, (#0xfffffe00, a5) +lbu t0, (#0xffffff00, a5) +lbu t0, (#0xffffff80, a5) +lbu t0, (#0xffffffc0, a5) +lbu t0, (#0xffffffe0, a5) +lbu t0, (#0xfffffff0, a5) +lbu t0, (#0xfffffff8, a5) +lbu t0, (#0xfffffffc, a5) +lbu t0, (#0xfffffffe, a5) +lbu t0, (#0xffffffff, a5) +lbu t0, (#0, a5) +lbu t0, (#1, a5) +lbu t0, (#2, a5) +lbu t0, (#4, a5) +lbu t0, (#8, a5) +lbu t0, (#0x10, a5) +lbu t0, (#0x20, a5) +lbu t0, (#0x40, a5) +lbu t0, (#0x80, a5) +lbu t0, (#0x100, a5) +lbu t0, (#0x200, a5) +lbu t0, (#0x400, a5) +lbu t0, (#0x7ff, a5) +lbu t0, (#0xfffff801, s4) +lbu t0, (#0xfffffc00, s4) +lbu t0, (#0xfffffe00, s4) +lbu t0, (#0xffffff00, s4) +lbu t0, (#0xffffff80, s4) +lbu t0, (#0xffffffc0, s4) +lbu t0, (#0xffffffe0, s4) +lbu t0, (#0xfffffff0, s4) +lbu t0, (#0xfffffff8, s4) +lbu t0, (#0xfffffffc, s4) +lbu t0, (#0xfffffffe, s4) +lbu t0, (#0xffffffff, s4) +lbu t0, (#0, s4) +lbu t0, (#1, s4) +lbu t0, (#2, s4) +lbu t0, (#4, s4) +lbu t0, (#8, s4) +lbu t0, (#0x10, s4) +lbu t0, (#0x20, s4) +lbu t0, (#0x40, s4) +lbu t0, (#0x80, s4) +lbu t0, (#0x100, s4) +lbu t0, (#0x200, s4) +lbu t0, (#0x400, s4) +lbu t0, (#0x7ff, s4) +lbu t0, (#0xfffff801, s9) +lbu t0, (#0xfffffc00, s9) +lbu t0, (#0xfffffe00, s9) +lbu t0, (#0xffffff00, s9) +lbu t0, (#0xffffff80, s9) +lbu t0, (#0xffffffc0, s9) +lbu t0, (#0xffffffe0, s9) +lbu t0, (#0xfffffff0, s9) +lbu t0, (#0xfffffff8, s9) +lbu t0, (#0xfffffffc, s9) +lbu t0, (#0xfffffffe, s9) +lbu t0, (#0xffffffff, s9) +lbu t0, (#0, s9) +lbu t0, (#1, s9) +lbu t0, (#2, s9) +lbu t0, (#4, s9) +lbu t0, (#8, s9) +lbu t0, (#0x10, s9) +lbu t0, (#0x20, s9) +lbu t0, (#0x40, s9) +lbu t0, (#0x80, s9) +lbu t0, (#0x100, s9) +lbu t0, (#0x200, s9) +lbu t0, (#0x400, s9) +lbu t0, (#0x7ff, s9) +lbu t0, (#0xfffff801, t6) +lbu t0, (#0xfffffc00, t6) +lbu t0, (#0xfffffe00, t6) +lbu t0, (#0xffffff00, t6) +lbu t0, (#0xffffff80, t6) +lbu t0, (#0xffffffc0, t6) +lbu t0, (#0xffffffe0, t6) +lbu t0, (#0xfffffff0, t6) +lbu t0, (#0xfffffff8, t6) +lbu t0, (#0xfffffffc, t6) +lbu t0, (#0xfffffffe, t6) +lbu t0, (#0xffffffff, t6) +lbu t0, (#0, t6) +lbu t0, (#1, t6) +lbu t0, (#2, t6) +lbu t0, (#4, t6) +lbu t0, (#8, t6) +lbu t0, (#0x10, t6) +lbu t0, (#0x20, t6) +lbu t0, (#0x40, t6) +lbu t0, (#0x80, t6) +lbu t0, (#0x100, t6) +lbu t0, (#0x200, t6) +lbu t0, (#0x400, t6) +lbu t0, (#0x7ff, t6) +lbu a0, (#0xfffff801, zero) +lbu a0, (#0xfffffc00, zero) +lbu a0, (#0xfffffe00, zero) +lbu a0, (#0xffffff00, zero) +lbu a0, (#0xffffff80, zero) +lbu a0, (#0xffffffc0, zero) +lbu a0, (#0xffffffe0, zero) +lbu a0, (#0xfffffff0, zero) +lbu a0, (#0xfffffff8, zero) +lbu a0, (#0xfffffffc, zero) +lbu a0, (#0xfffffffe, zero) +lbu a0, (#0xffffffff, zero) +lbu a0, (#0, zero) +lbu a0, (#1, zero) +lbu a0, (#2, zero) +lbu a0, (#4, zero) +lbu a0, (#8, zero) +lbu a0, (#0x10, zero) +lbu a0, (#0x20, zero) +lbu a0, (#0x40, zero) +lbu a0, (#0x80, zero) +lbu a0, (#0x100, zero) +lbu a0, (#0x200, zero) +lbu a0, (#0x400, zero) +lbu a0, (#0x7ff, zero) +lbu a0, (#0xfffff801, ra) +lbu a0, (#0xfffffc00, ra) +lbu a0, (#0xfffffe00, ra) +lbu a0, (#0xffffff00, ra) +lbu a0, (#0xffffff80, ra) +lbu a0, (#0xffffffc0, ra) +lbu a0, (#0xffffffe0, ra) +lbu a0, (#0xfffffff0, ra) +lbu a0, (#0xfffffff8, ra) +lbu a0, (#0xfffffffc, ra) +lbu a0, (#0xfffffffe, ra) +lbu a0, (#0xffffffff, ra) +lbu a0, (#0, ra) +lbu a0, (#1, ra) +lbu a0, (#2, ra) +lbu a0, (#4, ra) +lbu a0, (#8, ra) +lbu a0, (#0x10, ra) +lbu a0, (#0x20, ra) +lbu a0, (#0x40, ra) +lbu a0, (#0x80, ra) +lbu a0, (#0x100, ra) +lbu a0, (#0x200, ra) +lbu a0, (#0x400, ra) +lbu a0, (#0x7ff, ra) +lbu a0, (#0xfffff801, t0) +lbu a0, (#0xfffffc00, t0) +lbu a0, (#0xfffffe00, t0) +lbu a0, (#0xffffff00, t0) +lbu a0, (#0xffffff80, t0) +lbu a0, (#0xffffffc0, t0) +lbu a0, (#0xffffffe0, t0) +lbu a0, (#0xfffffff0, t0) +lbu a0, (#0xfffffff8, t0) +lbu a0, (#0xfffffffc, t0) +lbu a0, (#0xfffffffe, t0) +lbu a0, (#0xffffffff, t0) +lbu a0, (#0, t0) +lbu a0, (#1, t0) +lbu a0, (#2, t0) +lbu a0, (#4, t0) +lbu a0, (#8, t0) +lbu a0, (#0x10, t0) +lbu a0, (#0x20, t0) +lbu a0, (#0x40, t0) +lbu a0, (#0x80, t0) +lbu a0, (#0x100, t0) +lbu a0, (#0x200, t0) +lbu a0, (#0x400, t0) +lbu a0, (#0x7ff, t0) +lbu a0, (#0xfffff801, a0) +lbu a0, (#0xfffffc00, a0) +lbu a0, (#0xfffffe00, a0) +lbu a0, (#0xffffff00, a0) +lbu a0, (#0xffffff80, a0) +lbu a0, (#0xffffffc0, a0) +lbu a0, (#0xffffffe0, a0) +lbu a0, (#0xfffffff0, a0) +lbu a0, (#0xfffffff8, a0) +lbu a0, (#0xfffffffc, a0) +lbu a0, (#0xfffffffe, a0) +lbu a0, (#0xffffffff, a0) +lbu a0, (#0, a0) +lbu a0, (#1, a0) +lbu a0, (#2, a0) +lbu a0, (#4, a0) +lbu a0, (#8, a0) +lbu a0, (#0x10, a0) +lbu a0, (#0x20, a0) +lbu a0, (#0x40, a0) +lbu a0, (#0x80, a0) +lbu a0, (#0x100, a0) +lbu a0, (#0x200, a0) +lbu a0, (#0x400, a0) +lbu a0, (#0x7ff, a0) +lbu a0, (#0xfffff801, a5) +lbu a0, (#0xfffffc00, a5) +lbu a0, (#0xfffffe00, a5) +lbu a0, (#0xffffff00, a5) +lbu a0, (#0xffffff80, a5) +lbu a0, (#0xffffffc0, a5) +lbu a0, (#0xffffffe0, a5) +lbu a0, (#0xfffffff0, a5) +lbu a0, (#0xfffffff8, a5) +lbu a0, (#0xfffffffc, a5) +lbu a0, (#0xfffffffe, a5) +lbu a0, (#0xffffffff, a5) +lbu a0, (#0, a5) +lbu a0, (#1, a5) +lbu a0, (#2, a5) +lbu a0, (#4, a5) +lbu a0, (#8, a5) +lbu a0, (#0x10, a5) +lbu a0, (#0x20, a5) +lbu a0, (#0x40, a5) +lbu a0, (#0x80, a5) +lbu a0, (#0x100, a5) +lbu a0, (#0x200, a5) +lbu a0, (#0x400, a5) +lbu a0, (#0x7ff, a5) +lbu a0, (#0xfffff801, s4) +lbu a0, (#0xfffffc00, s4) +lbu a0, (#0xfffffe00, s4) +lbu a0, (#0xffffff00, s4) +lbu a0, (#0xffffff80, s4) +lbu a0, (#0xffffffc0, s4) +lbu a0, (#0xffffffe0, s4) +lbu a0, (#0xfffffff0, s4) +lbu a0, (#0xfffffff8, s4) +lbu a0, (#0xfffffffc, s4) +lbu a0, (#0xfffffffe, s4) +lbu a0, (#0xffffffff, s4) +lbu a0, (#0, s4) +lbu a0, (#1, s4) +lbu a0, (#2, s4) +lbu a0, (#4, s4) +lbu a0, (#8, s4) +lbu a0, (#0x10, s4) +lbu a0, (#0x20, s4) +lbu a0, (#0x40, s4) +lbu a0, (#0x80, s4) +lbu a0, (#0x100, s4) +lbu a0, (#0x200, s4) +lbu a0, (#0x400, s4) +lbu a0, (#0x7ff, s4) +lbu a0, (#0xfffff801, s9) +lbu a0, (#0xfffffc00, s9) +lbu a0, (#0xfffffe00, s9) +lbu a0, (#0xffffff00, s9) +lbu a0, (#0xffffff80, s9) +lbu a0, (#0xffffffc0, s9) +lbu a0, (#0xffffffe0, s9) +lbu a0, (#0xfffffff0, s9) +lbu a0, (#0xfffffff8, s9) +lbu a0, (#0xfffffffc, s9) +lbu a0, (#0xfffffffe, s9) +lbu a0, (#0xffffffff, s9) +lbu a0, (#0, s9) +lbu a0, (#1, s9) +lbu a0, (#2, s9) +lbu a0, (#4, s9) +lbu a0, (#8, s9) +lbu a0, (#0x10, s9) +lbu a0, (#0x20, s9) +lbu a0, (#0x40, s9) +lbu a0, (#0x80, s9) +lbu a0, (#0x100, s9) +lbu a0, (#0x200, s9) +lbu a0, (#0x400, s9) +lbu a0, (#0x7ff, s9) +lbu a0, (#0xfffff801, t6) +lbu a0, (#0xfffffc00, t6) +lbu a0, (#0xfffffe00, t6) +lbu a0, (#0xffffff00, t6) +lbu a0, (#0xffffff80, t6) +lbu a0, (#0xffffffc0, t6) +lbu a0, (#0xffffffe0, t6) +lbu a0, (#0xfffffff0, t6) +lbu a0, (#0xfffffff8, t6) +lbu a0, (#0xfffffffc, t6) +lbu a0, (#0xfffffffe, t6) +lbu a0, (#0xffffffff, t6) +lbu a0, (#0, t6) +lbu a0, (#1, t6) +lbu a0, (#2, t6) +lbu a0, (#4, t6) +lbu a0, (#8, t6) +lbu a0, (#0x10, t6) +lbu a0, (#0x20, t6) +lbu a0, (#0x40, t6) +lbu a0, (#0x80, t6) +lbu a0, (#0x100, t6) +lbu a0, (#0x200, t6) +lbu a0, (#0x400, t6) +lbu a0, (#0x7ff, t6) +lbu a5, (#0xfffff801, zero) +lbu a5, (#0xfffffc00, zero) +lbu a5, (#0xfffffe00, zero) +lbu a5, (#0xffffff00, zero) +lbu a5, (#0xffffff80, zero) +lbu a5, (#0xffffffc0, zero) +lbu a5, (#0xffffffe0, zero) +lbu a5, (#0xfffffff0, zero) +lbu a5, (#0xfffffff8, zero) +lbu a5, (#0xfffffffc, zero) +lbu a5, (#0xfffffffe, zero) +lbu a5, (#0xffffffff, zero) +lbu a5, (#0, zero) +lbu a5, (#1, zero) +lbu a5, (#2, zero) +lbu a5, (#4, zero) +lbu a5, (#8, zero) +lbu a5, (#0x10, zero) +lbu a5, (#0x20, zero) +lbu a5, (#0x40, zero) +lbu a5, (#0x80, zero) +lbu a5, (#0x100, zero) +lbu a5, (#0x200, zero) +lbu a5, (#0x400, zero) +lbu a5, (#0x7ff, zero) +lbu a5, (#0xfffff801, ra) +lbu a5, (#0xfffffc00, ra) +lbu a5, (#0xfffffe00, ra) +lbu a5, (#0xffffff00, ra) +lbu a5, (#0xffffff80, ra) +lbu a5, (#0xffffffc0, ra) +lbu a5, (#0xffffffe0, ra) +lbu a5, (#0xfffffff0, ra) +lbu a5, (#0xfffffff8, ra) +lbu a5, (#0xfffffffc, ra) +lbu a5, (#0xfffffffe, ra) +lbu a5, (#0xffffffff, ra) +lbu a5, (#0, ra) +lbu a5, (#1, ra) +lbu a5, (#2, ra) +lbu a5, (#4, ra) +lbu a5, (#8, ra) +lbu a5, (#0x10, ra) +lbu a5, (#0x20, ra) +lbu a5, (#0x40, ra) +lbu a5, (#0x80, ra) +lbu a5, (#0x100, ra) +lbu a5, (#0x200, ra) +lbu a5, (#0x400, ra) +lbu a5, (#0x7ff, ra) +lbu a5, (#0xfffff801, t0) +lbu a5, (#0xfffffc00, t0) +lbu a5, (#0xfffffe00, t0) +lbu a5, (#0xffffff00, t0) +lbu a5, (#0xffffff80, t0) +lbu a5, (#0xffffffc0, t0) +lbu a5, (#0xffffffe0, t0) +lbu a5, (#0xfffffff0, t0) +lbu a5, (#0xfffffff8, t0) +lbu a5, (#0xfffffffc, t0) +lbu a5, (#0xfffffffe, t0) +lbu a5, (#0xffffffff, t0) +lbu a5, (#0, t0) +lbu a5, (#1, t0) +lbu a5, (#2, t0) +lbu a5, (#4, t0) +lbu a5, (#8, t0) +lbu a5, (#0x10, t0) +lbu a5, (#0x20, t0) +lbu a5, (#0x40, t0) +lbu a5, (#0x80, t0) +lbu a5, (#0x100, t0) +lbu a5, (#0x200, t0) +lbu a5, (#0x400, t0) +lbu a5, (#0x7ff, t0) +lbu a5, (#0xfffff801, a0) +lbu a5, (#0xfffffc00, a0) +lbu a5, (#0xfffffe00, a0) +lbu a5, (#0xffffff00, a0) +lbu a5, (#0xffffff80, a0) +lbu a5, (#0xffffffc0, a0) +lbu a5, (#0xffffffe0, a0) +lbu a5, (#0xfffffff0, a0) +lbu a5, (#0xfffffff8, a0) +lbu a5, (#0xfffffffc, a0) +lbu a5, (#0xfffffffe, a0) +lbu a5, (#0xffffffff, a0) +lbu a5, (#0, a0) +lbu a5, (#1, a0) +lbu a5, (#2, a0) +lbu a5, (#4, a0) +lbu a5, (#8, a0) +lbu a5, (#0x10, a0) +lbu a5, (#0x20, a0) +lbu a5, (#0x40, a0) +lbu a5, (#0x80, a0) +lbu a5, (#0x100, a0) +lbu a5, (#0x200, a0) +lbu a5, (#0x400, a0) +lbu a5, (#0x7ff, a0) +lbu a5, (#0xfffff801, a5) +lbu a5, (#0xfffffc00, a5) +lbu a5, (#0xfffffe00, a5) +lbu a5, (#0xffffff00, a5) +lbu a5, (#0xffffff80, a5) +lbu a5, (#0xffffffc0, a5) +lbu a5, (#0xffffffe0, a5) +lbu a5, (#0xfffffff0, a5) +lbu a5, (#0xfffffff8, a5) +lbu a5, (#0xfffffffc, a5) +lbu a5, (#0xfffffffe, a5) +lbu a5, (#0xffffffff, a5) +lbu a5, (#0, a5) +lbu a5, (#1, a5) +lbu a5, (#2, a5) +lbu a5, (#4, a5) +lbu a5, (#8, a5) +lbu a5, (#0x10, a5) +lbu a5, (#0x20, a5) +lbu a5, (#0x40, a5) +lbu a5, (#0x80, a5) +lbu a5, (#0x100, a5) +lbu a5, (#0x200, a5) +lbu a5, (#0x400, a5) +lbu a5, (#0x7ff, a5) +lbu a5, (#0xfffff801, s4) +lbu a5, (#0xfffffc00, s4) +lbu a5, (#0xfffffe00, s4) +lbu a5, (#0xffffff00, s4) +lbu a5, (#0xffffff80, s4) +lbu a5, (#0xffffffc0, s4) +lbu a5, (#0xffffffe0, s4) +lbu a5, (#0xfffffff0, s4) +lbu a5, (#0xfffffff8, s4) +lbu a5, (#0xfffffffc, s4) +lbu a5, (#0xfffffffe, s4) +lbu a5, (#0xffffffff, s4) +lbu a5, (#0, s4) +lbu a5, (#1, s4) +lbu a5, (#2, s4) +lbu a5, (#4, s4) +lbu a5, (#8, s4) +lbu a5, (#0x10, s4) +lbu a5, (#0x20, s4) +lbu a5, (#0x40, s4) +lbu a5, (#0x80, s4) +lbu a5, (#0x100, s4) +lbu a5, (#0x200, s4) +lbu a5, (#0x400, s4) +lbu a5, (#0x7ff, s4) +lbu a5, (#0xfffff801, s9) +lbu a5, (#0xfffffc00, s9) +lbu a5, (#0xfffffe00, s9) +lbu a5, (#0xffffff00, s9) +lbu a5, (#0xffffff80, s9) +lbu a5, (#0xffffffc0, s9) +lbu a5, (#0xffffffe0, s9) +lbu a5, (#0xfffffff0, s9) +lbu a5, (#0xfffffff8, s9) +lbu a5, (#0xfffffffc, s9) +lbu a5, (#0xfffffffe, s9) +lbu a5, (#0xffffffff, s9) +lbu a5, (#0, s9) +lbu a5, (#1, s9) +lbu a5, (#2, s9) +lbu a5, (#4, s9) +lbu a5, (#8, s9) +lbu a5, (#0x10, s9) +lbu a5, (#0x20, s9) +lbu a5, (#0x40, s9) +lbu a5, (#0x80, s9) +lbu a5, (#0x100, s9) +lbu a5, (#0x200, s9) +lbu a5, (#0x400, s9) +lbu a5, (#0x7ff, s9) +lbu a5, (#0xfffff801, t6) +lbu a5, (#0xfffffc00, t6) +lbu a5, (#0xfffffe00, t6) +lbu a5, (#0xffffff00, t6) +lbu a5, (#0xffffff80, t6) +lbu a5, (#0xffffffc0, t6) +lbu a5, (#0xffffffe0, t6) +lbu a5, (#0xfffffff0, t6) +lbu a5, (#0xfffffff8, t6) +lbu a5, (#0xfffffffc, t6) +lbu a5, (#0xfffffffe, t6) +lbu a5, (#0xffffffff, t6) +lbu a5, (#0, t6) +lbu a5, (#1, t6) +lbu a5, (#2, t6) +lbu a5, (#4, t6) +lbu a5, (#8, t6) +lbu a5, (#0x10, t6) +lbu a5, (#0x20, t6) +lbu a5, (#0x40, t6) +lbu a5, (#0x80, t6) +lbu a5, (#0x100, t6) +lbu a5, (#0x200, t6) +lbu a5, (#0x400, t6) +lbu a5, (#0x7ff, t6) +lbu s4, (#0xfffff801, zero) +lbu s4, (#0xfffffc00, zero) +lbu s4, (#0xfffffe00, zero) +lbu s4, (#0xffffff00, zero) +lbu s4, (#0xffffff80, zero) +lbu s4, (#0xffffffc0, zero) +lbu s4, (#0xffffffe0, zero) +lbu s4, (#0xfffffff0, zero) +lbu s4, (#0xfffffff8, zero) +lbu s4, (#0xfffffffc, zero) +lbu s4, (#0xfffffffe, zero) +lbu s4, (#0xffffffff, zero) +lbu s4, (#0, zero) +lbu s4, (#1, zero) +lbu s4, (#2, zero) +lbu s4, (#4, zero) +lbu s4, (#8, zero) +lbu s4, (#0x10, zero) +lbu s4, (#0x20, zero) +lbu s4, (#0x40, zero) +lbu s4, (#0x80, zero) +lbu s4, (#0x100, zero) +lbu s4, (#0x200, zero) +lbu s4, (#0x400, zero) +lbu s4, (#0x7ff, zero) +lbu s4, (#0xfffff801, ra) +lbu s4, (#0xfffffc00, ra) +lbu s4, (#0xfffffe00, ra) +lbu s4, (#0xffffff00, ra) +lbu s4, (#0xffffff80, ra) +lbu s4, (#0xffffffc0, ra) +lbu s4, (#0xffffffe0, ra) +lbu s4, (#0xfffffff0, ra) +lbu s4, (#0xfffffff8, ra) +lbu s4, (#0xfffffffc, ra) +lbu s4, (#0xfffffffe, ra) +lbu s4, (#0xffffffff, ra) +lbu s4, (#0, ra) +lbu s4, (#1, ra) +lbu s4, (#2, ra) +lbu s4, (#4, ra) +lbu s4, (#8, ra) +lbu s4, (#0x10, ra) +lbu s4, (#0x20, ra) +lbu s4, (#0x40, ra) +lbu s4, (#0x80, ra) +lbu s4, (#0x100, ra) +lbu s4, (#0x200, ra) +lbu s4, (#0x400, ra) +lbu s4, (#0x7ff, ra) +lbu s4, (#0xfffff801, t0) +lbu s4, (#0xfffffc00, t0) +lbu s4, (#0xfffffe00, t0) +lbu s4, (#0xffffff00, t0) +lbu s4, (#0xffffff80, t0) +lbu s4, (#0xffffffc0, t0) +lbu s4, (#0xffffffe0, t0) +lbu s4, (#0xfffffff0, t0) +lbu s4, (#0xfffffff8, t0) +lbu s4, (#0xfffffffc, t0) +lbu s4, (#0xfffffffe, t0) +lbu s4, (#0xffffffff, t0) +lbu s4, (#0, t0) +lbu s4, (#1, t0) +lbu s4, (#2, t0) +lbu s4, (#4, t0) +lbu s4, (#8, t0) +lbu s4, (#0x10, t0) +lbu s4, (#0x20, t0) +lbu s4, (#0x40, t0) +lbu s4, (#0x80, t0) +lbu s4, (#0x100, t0) +lbu s4, (#0x200, t0) +lbu s4, (#0x400, t0) +lbu s4, (#0x7ff, t0) +lbu s4, (#0xfffff801, a0) +lbu s4, (#0xfffffc00, a0) +lbu s4, (#0xfffffe00, a0) +lbu s4, (#0xffffff00, a0) +lbu s4, (#0xffffff80, a0) +lbu s4, (#0xffffffc0, a0) +lbu s4, (#0xffffffe0, a0) +lbu s4, (#0xfffffff0, a0) +lbu s4, (#0xfffffff8, a0) +lbu s4, (#0xfffffffc, a0) +lbu s4, (#0xfffffffe, a0) +lbu s4, (#0xffffffff, a0) +lbu s4, (#0, a0) +lbu s4, (#1, a0) +lbu s4, (#2, a0) +lbu s4, (#4, a0) +lbu s4, (#8, a0) +lbu s4, (#0x10, a0) +lbu s4, (#0x20, a0) +lbu s4, (#0x40, a0) +lbu s4, (#0x80, a0) +lbu s4, (#0x100, a0) +lbu s4, (#0x200, a0) +lbu s4, (#0x400, a0) +lbu s4, (#0x7ff, a0) +lbu s4, (#0xfffff801, a5) +lbu s4, (#0xfffffc00, a5) +lbu s4, (#0xfffffe00, a5) +lbu s4, (#0xffffff00, a5) +lbu s4, (#0xffffff80, a5) +lbu s4, (#0xffffffc0, a5) +lbu s4, (#0xffffffe0, a5) +lbu s4, (#0xfffffff0, a5) +lbu s4, (#0xfffffff8, a5) +lbu s4, (#0xfffffffc, a5) +lbu s4, (#0xfffffffe, a5) +lbu s4, (#0xffffffff, a5) +lbu s4, (#0, a5) +lbu s4, (#1, a5) +lbu s4, (#2, a5) +lbu s4, (#4, a5) +lbu s4, (#8, a5) +lbu s4, (#0x10, a5) +lbu s4, (#0x20, a5) +lbu s4, (#0x40, a5) +lbu s4, (#0x80, a5) +lbu s4, (#0x100, a5) +lbu s4, (#0x200, a5) +lbu s4, (#0x400, a5) +lbu s4, (#0x7ff, a5) +lbu s4, (#0xfffff801, s4) +lbu s4, (#0xfffffc00, s4) +lbu s4, (#0xfffffe00, s4) +lbu s4, (#0xffffff00, s4) +lbu s4, (#0xffffff80, s4) +lbu s4, (#0xffffffc0, s4) +lbu s4, (#0xffffffe0, s4) +lbu s4, (#0xfffffff0, s4) +lbu s4, (#0xfffffff8, s4) +lbu s4, (#0xfffffffc, s4) +lbu s4, (#0xfffffffe, s4) +lbu s4, (#0xffffffff, s4) +lbu s4, (#0, s4) +lbu s4, (#1, s4) +lbu s4, (#2, s4) +lbu s4, (#4, s4) +lbu s4, (#8, s4) +lbu s4, (#0x10, s4) +lbu s4, (#0x20, s4) +lbu s4, (#0x40, s4) +lbu s4, (#0x80, s4) +lbu s4, (#0x100, s4) +lbu s4, (#0x200, s4) +lbu s4, (#0x400, s4) +lbu s4, (#0x7ff, s4) +lbu s4, (#0xfffff801, s9) +lbu s4, (#0xfffffc00, s9) +lbu s4, (#0xfffffe00, s9) +lbu s4, (#0xffffff00, s9) +lbu s4, (#0xffffff80, s9) +lbu s4, (#0xffffffc0, s9) +lbu s4, (#0xffffffe0, s9) +lbu s4, (#0xfffffff0, s9) +lbu s4, (#0xfffffff8, s9) +lbu s4, (#0xfffffffc, s9) +lbu s4, (#0xfffffffe, s9) +lbu s4, (#0xffffffff, s9) +lbu s4, (#0, s9) +lbu s4, (#1, s9) +lbu s4, (#2, s9) +lbu s4, (#4, s9) +lbu s4, (#8, s9) +lbu s4, (#0x10, s9) +lbu s4, (#0x20, s9) +lbu s4, (#0x40, s9) +lbu s4, (#0x80, s9) +lbu s4, (#0x100, s9) +lbu s4, (#0x200, s9) +lbu s4, (#0x400, s9) +lbu s4, (#0x7ff, s9) +lbu s4, (#0xfffff801, t6) +lbu s4, (#0xfffffc00, t6) +lbu s4, (#0xfffffe00, t6) +lbu s4, (#0xffffff00, t6) +lbu s4, (#0xffffff80, t6) +lbu s4, (#0xffffffc0, t6) +lbu s4, (#0xffffffe0, t6) +lbu s4, (#0xfffffff0, t6) +lbu s4, (#0xfffffff8, t6) +lbu s4, (#0xfffffffc, t6) +lbu s4, (#0xfffffffe, t6) +lbu s4, (#0xffffffff, t6) +lbu s4, (#0, t6) +lbu s4, (#1, t6) +lbu s4, (#2, t6) +lbu s4, (#4, t6) +lbu s4, (#8, t6) +lbu s4, (#0x10, t6) +lbu s4, (#0x20, t6) +lbu s4, (#0x40, t6) +lbu s4, (#0x80, t6) +lbu s4, (#0x100, t6) +lbu s4, (#0x200, t6) +lbu s4, (#0x400, t6) +lbu s4, (#0x7ff, t6) +lbu s9, (#0xfffff801, zero) +lbu s9, (#0xfffffc00, zero) +lbu s9, (#0xfffffe00, zero) +lbu s9, (#0xffffff00, zero) +lbu s9, (#0xffffff80, zero) +lbu s9, (#0xffffffc0, zero) +lbu s9, (#0xffffffe0, zero) +lbu s9, (#0xfffffff0, zero) +lbu s9, (#0xfffffff8, zero) +lbu s9, (#0xfffffffc, zero) +lbu s9, (#0xfffffffe, zero) +lbu s9, (#0xffffffff, zero) +lbu s9, (#0, zero) +lbu s9, (#1, zero) +lbu s9, (#2, zero) +lbu s9, (#4, zero) +lbu s9, (#8, zero) +lbu s9, (#0x10, zero) +lbu s9, (#0x20, zero) +lbu s9, (#0x40, zero) +lbu s9, (#0x80, zero) +lbu s9, (#0x100, zero) +lbu s9, (#0x200, zero) +lbu s9, (#0x400, zero) +lbu s9, (#0x7ff, zero) +lbu s9, (#0xfffff801, ra) +lbu s9, (#0xfffffc00, ra) +lbu s9, (#0xfffffe00, ra) +lbu s9, (#0xffffff00, ra) +lbu s9, (#0xffffff80, ra) +lbu s9, (#0xffffffc0, ra) +lbu s9, (#0xffffffe0, ra) +lbu s9, (#0xfffffff0, ra) +lbu s9, (#0xfffffff8, ra) +lbu s9, (#0xfffffffc, ra) +lbu s9, (#0xfffffffe, ra) +lbu s9, (#0xffffffff, ra) +lbu s9, (#0, ra) +lbu s9, (#1, ra) +lbu s9, (#2, ra) +lbu s9, (#4, ra) +lbu s9, (#8, ra) +lbu s9, (#0x10, ra) +lbu s9, (#0x20, ra) +lbu s9, (#0x40, ra) +lbu s9, (#0x80, ra) +lbu s9, (#0x100, ra) +lbu s9, (#0x200, ra) +lbu s9, (#0x400, ra) +lbu s9, (#0x7ff, ra) +lbu s9, (#0xfffff801, t0) +lbu s9, (#0xfffffc00, t0) +lbu s9, (#0xfffffe00, t0) +lbu s9, (#0xffffff00, t0) +lbu s9, (#0xffffff80, t0) +lbu s9, (#0xffffffc0, t0) +lbu s9, (#0xffffffe0, t0) +lbu s9, (#0xfffffff0, t0) +lbu s9, (#0xfffffff8, t0) +lbu s9, (#0xfffffffc, t0) +lbu s9, (#0xfffffffe, t0) +lbu s9, (#0xffffffff, t0) +lbu s9, (#0, t0) +lbu s9, (#1, t0) +lbu s9, (#2, t0) +lbu s9, (#4, t0) +lbu s9, (#8, t0) +lbu s9, (#0x10, t0) +lbu s9, (#0x20, t0) +lbu s9, (#0x40, t0) +lbu s9, (#0x80, t0) +lbu s9, (#0x100, t0) +lbu s9, (#0x200, t0) +lbu s9, (#0x400, t0) +lbu s9, (#0x7ff, t0) +lbu s9, (#0xfffff801, a0) +lbu s9, (#0xfffffc00, a0) +lbu s9, (#0xfffffe00, a0) +lbu s9, (#0xffffff00, a0) +lbu s9, (#0xffffff80, a0) +lbu s9, (#0xffffffc0, a0) +lbu s9, (#0xffffffe0, a0) +lbu s9, (#0xfffffff0, a0) +lbu s9, (#0xfffffff8, a0) +lbu s9, (#0xfffffffc, a0) +lbu s9, (#0xfffffffe, a0) +lbu s9, (#0xffffffff, a0) +lbu s9, (#0, a0) +lbu s9, (#1, a0) +lbu s9, (#2, a0) +lbu s9, (#4, a0) +lbu s9, (#8, a0) +lbu s9, (#0x10, a0) +lbu s9, (#0x20, a0) +lbu s9, (#0x40, a0) +lbu s9, (#0x80, a0) +lbu s9, (#0x100, a0) +lbu s9, (#0x200, a0) +lbu s9, (#0x400, a0) +lbu s9, (#0x7ff, a0) +lbu s9, (#0xfffff801, a5) +lbu s9, (#0xfffffc00, a5) +lbu s9, (#0xfffffe00, a5) +lbu s9, (#0xffffff00, a5) +lbu s9, (#0xffffff80, a5) +lbu s9, (#0xffffffc0, a5) +lbu s9, (#0xffffffe0, a5) +lbu s9, (#0xfffffff0, a5) +lbu s9, (#0xfffffff8, a5) +lbu s9, (#0xfffffffc, a5) +lbu s9, (#0xfffffffe, a5) +lbu s9, (#0xffffffff, a5) +lbu s9, (#0, a5) +lbu s9, (#1, a5) +lbu s9, (#2, a5) +lbu s9, (#4, a5) +lbu s9, (#8, a5) +lbu s9, (#0x10, a5) +lbu s9, (#0x20, a5) +lbu s9, (#0x40, a5) +lbu s9, (#0x80, a5) +lbu s9, (#0x100, a5) +lbu s9, (#0x200, a5) +lbu s9, (#0x400, a5) +lbu s9, (#0x7ff, a5) +lbu s9, (#0xfffff801, s4) +lbu s9, (#0xfffffc00, s4) +lbu s9, (#0xfffffe00, s4) +lbu s9, (#0xffffff00, s4) +lbu s9, (#0xffffff80, s4) +lbu s9, (#0xffffffc0, s4) +lbu s9, (#0xffffffe0, s4) +lbu s9, (#0xfffffff0, s4) +lbu s9, (#0xfffffff8, s4) +lbu s9, (#0xfffffffc, s4) +lbu s9, (#0xfffffffe, s4) +lbu s9, (#0xffffffff, s4) +lbu s9, (#0, s4) +lbu s9, (#1, s4) +lbu s9, (#2, s4) +lbu s9, (#4, s4) +lbu s9, (#8, s4) +lbu s9, (#0x10, s4) +lbu s9, (#0x20, s4) +lbu s9, (#0x40, s4) +lbu s9, (#0x80, s4) +lbu s9, (#0x100, s4) +lbu s9, (#0x200, s4) +lbu s9, (#0x400, s4) +lbu s9, (#0x7ff, s4) +lbu s9, (#0xfffff801, s9) +lbu s9, (#0xfffffc00, s9) +lbu s9, (#0xfffffe00, s9) +lbu s9, (#0xffffff00, s9) +lbu s9, (#0xffffff80, s9) +lbu s9, (#0xffffffc0, s9) +lbu s9, (#0xffffffe0, s9) +lbu s9, (#0xfffffff0, s9) +lbu s9, (#0xfffffff8, s9) +lbu s9, (#0xfffffffc, s9) +lbu s9, (#0xfffffffe, s9) +lbu s9, (#0xffffffff, s9) +lbu s9, (#0, s9) +lbu s9, (#1, s9) +lbu s9, (#2, s9) +lbu s9, (#4, s9) +lbu s9, (#8, s9) +lbu s9, (#0x10, s9) +lbu s9, (#0x20, s9) +lbu s9, (#0x40, s9) +lbu s9, (#0x80, s9) +lbu s9, (#0x100, s9) +lbu s9, (#0x200, s9) +lbu s9, (#0x400, s9) +lbu s9, (#0x7ff, s9) +lbu s9, (#0xfffff801, t6) +lbu s9, (#0xfffffc00, t6) +lbu s9, (#0xfffffe00, t6) +lbu s9, (#0xffffff00, t6) +lbu s9, (#0xffffff80, t6) +lbu s9, (#0xffffffc0, t6) +lbu s9, (#0xffffffe0, t6) +lbu s9, (#0xfffffff0, t6) +lbu s9, (#0xfffffff8, t6) +lbu s9, (#0xfffffffc, t6) +lbu s9, (#0xfffffffe, t6) +lbu s9, (#0xffffffff, t6) +lbu s9, (#0, t6) +lbu s9, (#1, t6) +lbu s9, (#2, t6) +lbu s9, (#4, t6) +lbu s9, (#8, t6) +lbu s9, (#0x10, t6) +lbu s9, (#0x20, t6) +lbu s9, (#0x40, t6) +lbu s9, (#0x80, t6) +lbu s9, (#0x100, t6) +lbu s9, (#0x200, t6) +lbu s9, (#0x400, t6) +lbu s9, (#0x7ff, t6) +lbu t6, (#0xfffff801, zero) +lbu t6, (#0xfffffc00, zero) +lbu t6, (#0xfffffe00, zero) +lbu t6, (#0xffffff00, zero) +lbu t6, (#0xffffff80, zero) +lbu t6, (#0xffffffc0, zero) +lbu t6, (#0xffffffe0, zero) +lbu t6, (#0xfffffff0, zero) +lbu t6, (#0xfffffff8, zero) +lbu t6, (#0xfffffffc, zero) +lbu t6, (#0xfffffffe, zero) +lbu t6, (#0xffffffff, zero) +lbu t6, (#0, zero) +lbu t6, (#1, zero) +lbu t6, (#2, zero) +lbu t6, (#4, zero) +lbu t6, (#8, zero) +lbu t6, (#0x10, zero) +lbu t6, (#0x20, zero) +lbu t6, (#0x40, zero) +lbu t6, (#0x80, zero) +lbu t6, (#0x100, zero) +lbu t6, (#0x200, zero) +lbu t6, (#0x400, zero) +lbu t6, (#0x7ff, zero) +lbu t6, (#0xfffff801, ra) +lbu t6, (#0xfffffc00, ra) +lbu t6, (#0xfffffe00, ra) +lbu t6, (#0xffffff00, ra) +lbu t6, (#0xffffff80, ra) +lbu t6, (#0xffffffc0, ra) +lbu t6, (#0xffffffe0, ra) +lbu t6, (#0xfffffff0, ra) +lbu t6, (#0xfffffff8, ra) +lbu t6, (#0xfffffffc, ra) +lbu t6, (#0xfffffffe, ra) +lbu t6, (#0xffffffff, ra) +lbu t6, (#0, ra) +lbu t6, (#1, ra) +lbu t6, (#2, ra) +lbu t6, (#4, ra) +lbu t6, (#8, ra) +lbu t6, (#0x10, ra) +lbu t6, (#0x20, ra) +lbu t6, (#0x40, ra) +lbu t6, (#0x80, ra) +lbu t6, (#0x100, ra) +lbu t6, (#0x200, ra) +lbu t6, (#0x400, ra) +lbu t6, (#0x7ff, ra) +lbu t6, (#0xfffff801, t0) +lbu t6, (#0xfffffc00, t0) +lbu t6, (#0xfffffe00, t0) +lbu t6, (#0xffffff00, t0) +lbu t6, (#0xffffff80, t0) +lbu t6, (#0xffffffc0, t0) +lbu t6, (#0xffffffe0, t0) +lbu t6, (#0xfffffff0, t0) +lbu t6, (#0xfffffff8, t0) +lbu t6, (#0xfffffffc, t0) +lbu t6, (#0xfffffffe, t0) +lbu t6, (#0xffffffff, t0) +lbu t6, (#0, t0) +lbu t6, (#1, t0) +lbu t6, (#2, t0) +lbu t6, (#4, t0) +lbu t6, (#8, t0) +lbu t6, (#0x10, t0) +lbu t6, (#0x20, t0) +lbu t6, (#0x40, t0) +lbu t6, (#0x80, t0) +lbu t6, (#0x100, t0) +lbu t6, (#0x200, t0) +lbu t6, (#0x400, t0) +lbu t6, (#0x7ff, t0) +lbu t6, (#0xfffff801, a0) +lbu t6, (#0xfffffc00, a0) +lbu t6, (#0xfffffe00, a0) +lbu t6, (#0xffffff00, a0) +lbu t6, (#0xffffff80, a0) +lbu t6, (#0xffffffc0, a0) +lbu t6, (#0xffffffe0, a0) +lbu t6, (#0xfffffff0, a0) +lbu t6, (#0xfffffff8, a0) +lbu t6, (#0xfffffffc, a0) +lbu t6, (#0xfffffffe, a0) +lbu t6, (#0xffffffff, a0) +lbu t6, (#0, a0) +lbu t6, (#1, a0) +lbu t6, (#2, a0) +lbu t6, (#4, a0) +lbu t6, (#8, a0) +lbu t6, (#0x10, a0) +lbu t6, (#0x20, a0) +lbu t6, (#0x40, a0) +lbu t6, (#0x80, a0) +lbu t6, (#0x100, a0) +lbu t6, (#0x200, a0) +lbu t6, (#0x400, a0) +lbu t6, (#0x7ff, a0) +lbu t6, (#0xfffff801, a5) +lbu t6, (#0xfffffc00, a5) +lbu t6, (#0xfffffe00, a5) +lbu t6, (#0xffffff00, a5) +lbu t6, (#0xffffff80, a5) +lbu t6, (#0xffffffc0, a5) +lbu t6, (#0xffffffe0, a5) +lbu t6, (#0xfffffff0, a5) +lbu t6, (#0xfffffff8, a5) +lbu t6, (#0xfffffffc, a5) +lbu t6, (#0xfffffffe, a5) +lbu t6, (#0xffffffff, a5) +lbu t6, (#0, a5) +lbu t6, (#1, a5) +lbu t6, (#2, a5) +lbu t6, (#4, a5) +lbu t6, (#8, a5) +lbu t6, (#0x10, a5) +lbu t6, (#0x20, a5) +lbu t6, (#0x40, a5) +lbu t6, (#0x80, a5) +lbu t6, (#0x100, a5) +lbu t6, (#0x200, a5) +lbu t6, (#0x400, a5) +lbu t6, (#0x7ff, a5) +lbu t6, (#0xfffff801, s4) +lbu t6, (#0xfffffc00, s4) +lbu t6, (#0xfffffe00, s4) +lbu t6, (#0xffffff00, s4) +lbu t6, (#0xffffff80, s4) +lbu t6, (#0xffffffc0, s4) +lbu t6, (#0xffffffe0, s4) +lbu t6, (#0xfffffff0, s4) +lbu t6, (#0xfffffff8, s4) +lbu t6, (#0xfffffffc, s4) +lbu t6, (#0xfffffffe, s4) +lbu t6, (#0xffffffff, s4) +lbu t6, (#0, s4) +lbu t6, (#1, s4) +lbu t6, (#2, s4) +lbu t6, (#4, s4) +lbu t6, (#8, s4) +lbu t6, (#0x10, s4) +lbu t6, (#0x20, s4) +lbu t6, (#0x40, s4) +lbu t6, (#0x80, s4) +lbu t6, (#0x100, s4) +lbu t6, (#0x200, s4) +lbu t6, (#0x400, s4) +lbu t6, (#0x7ff, s4) +lbu t6, (#0xfffff801, s9) +lbu t6, (#0xfffffc00, s9) +lbu t6, (#0xfffffe00, s9) +lbu t6, (#0xffffff00, s9) +lbu t6, (#0xffffff80, s9) +lbu t6, (#0xffffffc0, s9) +lbu t6, (#0xffffffe0, s9) +lbu t6, (#0xfffffff0, s9) +lbu t6, (#0xfffffff8, s9) +lbu t6, (#0xfffffffc, s9) +lbu t6, (#0xfffffffe, s9) +lbu t6, (#0xffffffff, s9) +lbu t6, (#0, s9) +lbu t6, (#1, s9) +lbu t6, (#2, s9) +lbu t6, (#4, s9) +lbu t6, (#8, s9) +lbu t6, (#0x10, s9) +lbu t6, (#0x20, s9) +lbu t6, (#0x40, s9) +lbu t6, (#0x80, s9) +lbu t6, (#0x100, s9) +lbu t6, (#0x200, s9) +lbu t6, (#0x400, s9) +lbu t6, (#0x7ff, s9) +lbu t6, (#0xfffff801, t6) +lbu t6, (#0xfffffc00, t6) +lbu t6, (#0xfffffe00, t6) +lbu t6, (#0xffffff00, t6) +lbu t6, (#0xffffff80, t6) +lbu t6, (#0xffffffc0, t6) +lbu t6, (#0xffffffe0, t6) +lbu t6, (#0xfffffff0, t6) +lbu t6, (#0xfffffff8, t6) +lbu t6, (#0xfffffffc, t6) +lbu t6, (#0xfffffffe, t6) +lbu t6, (#0xffffffff, t6) +lbu t6, (#0, t6) +lbu t6, (#1, t6) +lbu t6, (#2, t6) +lbu t6, (#4, t6) +lbu t6, (#8, t6) +lbu t6, (#0x10, t6) +lbu t6, (#0x20, t6) +lbu t6, (#0x40, t6) +lbu t6, (#0x80, t6) +lbu t6, (#0x100, t6) +lbu t6, (#0x200, t6) +lbu t6, (#0x400, t6) +lbu t6, (#0x7ff, t6) diff --git a/tests/riscv/rv32i/lh.asm b/tests/riscv/rv32i/lh.asm new file mode 100644 index 0000000..8493058 --- /dev/null +++ b/tests/riscv/rv32i/lh.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +lh zero, (#-2047, zero) +lh zero, (#-1024, zero) +lh zero, (#-512, zero) +lh zero, (#-256, zero) +lh zero, (#-128, zero) +lh zero, (#-64, zero) +lh zero, (#-32, zero) +lh zero, (#-16, zero) +lh zero, (#-8, zero) +lh zero, (#-4, zero) +lh zero, (#-2, zero) +lh zero, (#-1, zero) +lh zero, (#0, zero) +lh zero, (#1, zero) +lh zero, (#2, zero) +lh zero, (#4, zero) +lh zero, (#8, zero) +lh zero, (#16, zero) +lh zero, (#32, zero) +lh zero, (#64, zero) +lh zero, (#128, zero) +lh zero, (#256, zero) +lh zero, (#512, zero) +lh zero, (#1024, zero) +lh zero, (#2047, zero) +lh zero, (#-2047, ra) +lh zero, (#-1024, ra) +lh zero, (#-512, ra) +lh zero, (#-256, ra) +lh zero, (#-128, ra) +lh zero, (#-64, ra) +lh zero, (#-32, ra) +lh zero, (#-16, ra) +lh zero, (#-8, ra) +lh zero, (#-4, ra) +lh zero, (#-2, ra) +lh zero, (#-1, ra) +lh zero, (#0, ra) +lh zero, (#1, ra) +lh zero, (#2, ra) +lh zero, (#4, ra) +lh zero, (#8, ra) +lh zero, (#16, ra) +lh zero, (#32, ra) +lh zero, (#64, ra) +lh zero, (#128, ra) +lh zero, (#256, ra) +lh zero, (#512, ra) +lh zero, (#1024, ra) +lh zero, (#2047, ra) +lh zero, (#-2047, t0) +lh zero, (#-1024, t0) +lh zero, (#-512, t0) +lh zero, (#-256, t0) +lh zero, (#-128, t0) +lh zero, (#-64, t0) +lh zero, (#-32, t0) +lh zero, (#-16, t0) +lh zero, (#-8, t0) +lh zero, (#-4, t0) +lh zero, (#-2, t0) +lh zero, (#-1, t0) +lh zero, (#0, t0) +lh zero, (#1, t0) +lh zero, (#2, t0) +lh zero, (#4, t0) +lh zero, (#8, t0) +lh zero, (#16, t0) +lh zero, (#32, t0) +lh zero, (#64, t0) +lh zero, (#128, t0) +lh zero, (#256, t0) +lh zero, (#512, t0) +lh zero, (#1024, t0) +lh zero, (#2047, t0) +lh zero, (#-2047, a0) +lh zero, (#-1024, a0) +lh zero, (#-512, a0) +lh zero, (#-256, a0) +lh zero, (#-128, a0) +lh zero, (#-64, a0) +lh zero, (#-32, a0) +lh zero, (#-16, a0) +lh zero, (#-8, a0) +lh zero, (#-4, a0) +lh zero, (#-2, a0) +lh zero, (#-1, a0) +lh zero, (#0, a0) +lh zero, (#1, a0) +lh zero, (#2, a0) +lh zero, (#4, a0) +lh zero, (#8, a0) +lh zero, (#16, a0) +lh zero, (#32, a0) +lh zero, (#64, a0) +lh zero, (#128, a0) +lh zero, (#256, a0) +lh zero, (#512, a0) +lh zero, (#1024, a0) +lh zero, (#2047, a0) +lh zero, (#-2047, a5) +lh zero, (#-1024, a5) +lh zero, (#-512, a5) +lh zero, (#-256, a5) +lh zero, (#-128, a5) +lh zero, (#-64, a5) +lh zero, (#-32, a5) +lh zero, (#-16, a5) +lh zero, (#-8, a5) +lh zero, (#-4, a5) +lh zero, (#-2, a5) +lh zero, (#-1, a5) +lh zero, (#0, a5) +lh zero, (#1, a5) +lh zero, (#2, a5) +lh zero, (#4, a5) +lh zero, (#8, a5) +lh zero, (#16, a5) +lh zero, (#32, a5) +lh zero, (#64, a5) +lh zero, (#128, a5) +lh zero, (#256, a5) +lh zero, (#512, a5) +lh zero, (#1024, a5) +lh zero, (#2047, a5) +lh zero, (#-2047, s4) +lh zero, (#-1024, s4) +lh zero, (#-512, s4) +lh zero, (#-256, s4) +lh zero, (#-128, s4) +lh zero, (#-64, s4) +lh zero, (#-32, s4) +lh zero, (#-16, s4) +lh zero, (#-8, s4) +lh zero, (#-4, s4) +lh zero, (#-2, s4) +lh zero, (#-1, s4) +lh zero, (#0, s4) +lh zero, (#1, s4) +lh zero, (#2, s4) +lh zero, (#4, s4) +lh zero, (#8, s4) +lh zero, (#16, s4) +lh zero, (#32, s4) +lh zero, (#64, s4) +lh zero, (#128, s4) +lh zero, (#256, s4) +lh zero, (#512, s4) +lh zero, (#1024, s4) +lh zero, (#2047, s4) +lh zero, (#-2047, s9) +lh zero, (#-1024, s9) +lh zero, (#-512, s9) +lh zero, (#-256, s9) +lh zero, (#-128, s9) +lh zero, (#-64, s9) +lh zero, (#-32, s9) +lh zero, (#-16, s9) +lh zero, (#-8, s9) +lh zero, (#-4, s9) +lh zero, (#-2, s9) +lh zero, (#-1, s9) +lh zero, (#0, s9) +lh zero, (#1, s9) +lh zero, (#2, s9) +lh zero, (#4, s9) +lh zero, (#8, s9) +lh zero, (#16, s9) +lh zero, (#32, s9) +lh zero, (#64, s9) +lh zero, (#128, s9) +lh zero, (#256, s9) +lh zero, (#512, s9) +lh zero, (#1024, s9) +lh zero, (#2047, s9) +lh zero, (#-2047, t6) +lh zero, (#-1024, t6) +lh zero, (#-512, t6) +lh zero, (#-256, t6) +lh zero, (#-128, t6) +lh zero, (#-64, t6) +lh zero, (#-32, t6) +lh zero, (#-16, t6) +lh zero, (#-8, t6) +lh zero, (#-4, t6) +lh zero, (#-2, t6) +lh zero, (#-1, t6) +lh zero, (#0, t6) +lh zero, (#1, t6) +lh zero, (#2, t6) +lh zero, (#4, t6) +lh zero, (#8, t6) +lh zero, (#16, t6) +lh zero, (#32, t6) +lh zero, (#64, t6) +lh zero, (#128, t6) +lh zero, (#256, t6) +lh zero, (#512, t6) +lh zero, (#1024, t6) +lh zero, (#2047, t6) +lh ra, (#-2047, zero) +lh ra, (#-1024, zero) +lh ra, (#-512, zero) +lh ra, (#-256, zero) +lh ra, (#-128, zero) +lh ra, (#-64, zero) +lh ra, (#-32, zero) +lh ra, (#-16, zero) +lh ra, (#-8, zero) +lh ra, (#-4, zero) +lh ra, (#-2, zero) +lh ra, (#-1, zero) +lh ra, (#0, zero) +lh ra, (#1, zero) +lh ra, (#2, zero) +lh ra, (#4, zero) +lh ra, (#8, zero) +lh ra, (#16, zero) +lh ra, (#32, zero) +lh ra, (#64, zero) +lh ra, (#128, zero) +lh ra, (#256, zero) +lh ra, (#512, zero) +lh ra, (#1024, zero) +lh ra, (#2047, zero) +lh ra, (#-2047, ra) +lh ra, (#-1024, ra) +lh ra, (#-512, ra) +lh ra, (#-256, ra) +lh ra, (#-128, ra) +lh ra, (#-64, ra) +lh ra, (#-32, ra) +lh ra, (#-16, ra) +lh ra, (#-8, ra) +lh ra, (#-4, ra) +lh ra, (#-2, ra) +lh ra, (#-1, ra) +lh ra, (#0, ra) +lh ra, (#1, ra) +lh ra, (#2, ra) +lh ra, (#4, ra) +lh ra, (#8, ra) +lh ra, (#16, ra) +lh ra, (#32, ra) +lh ra, (#64, ra) +lh ra, (#128, ra) +lh ra, (#256, ra) +lh ra, (#512, ra) +lh ra, (#1024, ra) +lh ra, (#2047, ra) +lh ra, (#-2047, t0) +lh ra, (#-1024, t0) +lh ra, (#-512, t0) +lh ra, (#-256, t0) +lh ra, (#-128, t0) +lh ra, (#-64, t0) +lh ra, (#-32, t0) +lh ra, (#-16, t0) +lh ra, (#-8, t0) +lh ra, (#-4, t0) +lh ra, (#-2, t0) +lh ra, (#-1, t0) +lh ra, (#0, t0) +lh ra, (#1, t0) +lh ra, (#2, t0) +lh ra, (#4, t0) +lh ra, (#8, t0) +lh ra, (#16, t0) +lh ra, (#32, t0) +lh ra, (#64, t0) +lh ra, (#128, t0) +lh ra, (#256, t0) +lh ra, (#512, t0) +lh ra, (#1024, t0) +lh ra, (#2047, t0) +lh ra, (#-2047, a0) +lh ra, (#-1024, a0) +lh ra, (#-512, a0) +lh ra, (#-256, a0) +lh ra, (#-128, a0) +lh ra, (#-64, a0) +lh ra, (#-32, a0) +lh ra, (#-16, a0) +lh ra, (#-8, a0) +lh ra, (#-4, a0) +lh ra, (#-2, a0) +lh ra, (#-1, a0) +lh ra, (#0, a0) +lh ra, (#1, a0) +lh ra, (#2, a0) +lh ra, (#4, a0) +lh ra, (#8, a0) +lh ra, (#16, a0) +lh ra, (#32, a0) +lh ra, (#64, a0) +lh ra, (#128, a0) +lh ra, (#256, a0) +lh ra, (#512, a0) +lh ra, (#1024, a0) +lh ra, (#2047, a0) +lh ra, (#-2047, a5) +lh ra, (#-1024, a5) +lh ra, (#-512, a5) +lh ra, (#-256, a5) +lh ra, (#-128, a5) +lh ra, (#-64, a5) +lh ra, (#-32, a5) +lh ra, (#-16, a5) +lh ra, (#-8, a5) +lh ra, (#-4, a5) +lh ra, (#-2, a5) +lh ra, (#-1, a5) +lh ra, (#0, a5) +lh ra, (#1, a5) +lh ra, (#2, a5) +lh ra, (#4, a5) +lh ra, (#8, a5) +lh ra, (#16, a5) +lh ra, (#32, a5) +lh ra, (#64, a5) +lh ra, (#128, a5) +lh ra, (#256, a5) +lh ra, (#512, a5) +lh ra, (#1024, a5) +lh ra, (#2047, a5) +lh ra, (#-2047, s4) +lh ra, (#-1024, s4) +lh ra, (#-512, s4) +lh ra, (#-256, s4) +lh ra, (#-128, s4) +lh ra, (#-64, s4) +lh ra, (#-32, s4) +lh ra, (#-16, s4) +lh ra, (#-8, s4) +lh ra, (#-4, s4) +lh ra, (#-2, s4) +lh ra, (#-1, s4) +lh ra, (#0, s4) +lh ra, (#1, s4) +lh ra, (#2, s4) +lh ra, (#4, s4) +lh ra, (#8, s4) +lh ra, (#16, s4) +lh ra, (#32, s4) +lh ra, (#64, s4) +lh ra, (#128, s4) +lh ra, (#256, s4) +lh ra, (#512, s4) +lh ra, (#1024, s4) +lh ra, (#2047, s4) +lh ra, (#-2047, s9) +lh ra, (#-1024, s9) +lh ra, (#-512, s9) +lh ra, (#-256, s9) +lh ra, (#-128, s9) +lh ra, (#-64, s9) +lh ra, (#-32, s9) +lh ra, (#-16, s9) +lh ra, (#-8, s9) +lh ra, (#-4, s9) +lh ra, (#-2, s9) +lh ra, (#-1, s9) +lh ra, (#0, s9) +lh ra, (#1, s9) +lh ra, (#2, s9) +lh ra, (#4, s9) +lh ra, (#8, s9) +lh ra, (#16, s9) +lh ra, (#32, s9) +lh ra, (#64, s9) +lh ra, (#128, s9) +lh ra, (#256, s9) +lh ra, (#512, s9) +lh ra, (#1024, s9) +lh ra, (#2047, s9) +lh ra, (#-2047, t6) +lh ra, (#-1024, t6) +lh ra, (#-512, t6) +lh ra, (#-256, t6) +lh ra, (#-128, t6) +lh ra, (#-64, t6) +lh ra, (#-32, t6) +lh ra, (#-16, t6) +lh ra, (#-8, t6) +lh ra, (#-4, t6) +lh ra, (#-2, t6) +lh ra, (#-1, t6) +lh ra, (#0, t6) +lh ra, (#1, t6) +lh ra, (#2, t6) +lh ra, (#4, t6) +lh ra, (#8, t6) +lh ra, (#16, t6) +lh ra, (#32, t6) +lh ra, (#64, t6) +lh ra, (#128, t6) +lh ra, (#256, t6) +lh ra, (#512, t6) +lh ra, (#1024, t6) +lh ra, (#2047, t6) +lh t0, (#-2047, zero) +lh t0, (#-1024, zero) +lh t0, (#-512, zero) +lh t0, (#-256, zero) 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t0, (#-64, t0) +lh t0, (#-32, t0) +lh t0, (#-16, t0) +lh t0, (#-8, t0) +lh t0, (#-4, t0) +lh t0, (#-2, t0) +lh t0, (#-1, t0) +lh t0, (#0, t0) +lh t0, (#1, t0) +lh t0, (#2, t0) +lh t0, (#4, t0) +lh t0, (#8, t0) +lh t0, (#16, t0) +lh t0, (#32, t0) +lh t0, (#64, t0) +lh t0, (#128, t0) +lh t0, (#256, t0) +lh t0, (#512, t0) +lh t0, (#1024, t0) +lh t0, (#2047, t0) +lh t0, (#-2047, a0) +lh t0, (#-1024, a0) +lh t0, (#-512, a0) +lh t0, (#-256, a0) +lh t0, (#-128, a0) +lh t0, (#-64, a0) +lh t0, (#-32, a0) +lh t0, (#-16, a0) +lh t0, (#-8, a0) +lh t0, (#-4, a0) +lh t0, (#-2, a0) +lh t0, (#-1, a0) +lh t0, (#0, a0) +lh t0, (#1, a0) +lh t0, (#2, a0) +lh t0, (#4, a0) +lh t0, (#8, a0) +lh t0, (#16, a0) +lh t0, (#32, a0) +lh t0, (#64, a0) +lh t0, (#128, a0) +lh t0, (#256, a0) +lh t0, (#512, a0) +lh t0, (#1024, a0) +lh t0, (#2047, a0) +lh t0, (#-2047, a5) +lh t0, (#-1024, a5) +lh t0, (#-512, a5) +lh t0, (#-256, a5) +lh t0, (#-128, a5) +lh t0, (#-64, a5) +lh t0, (#-32, a5) +lh t0, (#-16, a5) +lh t0, (#-8, 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s9) +lh t6, (#4, s9) +lh t6, (#8, s9) +lh t6, (#16, s9) +lh t6, (#32, s9) +lh t6, (#64, s9) +lh t6, (#128, s9) +lh t6, (#256, s9) +lh t6, (#512, s9) +lh t6, (#1024, s9) +lh t6, (#2047, s9) +lh t6, (#-2047, t6) +lh t6, (#-1024, t6) +lh t6, (#-512, t6) +lh t6, (#-256, t6) +lh t6, (#-128, t6) +lh t6, (#-64, t6) +lh t6, (#-32, t6) +lh t6, (#-16, t6) +lh t6, (#-8, t6) +lh t6, (#-4, t6) +lh t6, (#-2, t6) +lh t6, (#-1, t6) +lh t6, (#0, t6) +lh t6, (#1, t6) +lh t6, (#2, t6) +lh t6, (#4, t6) +lh t6, (#8, t6) +lh t6, (#16, t6) +lh t6, (#32, t6) +lh t6, (#64, t6) +lh t6, (#128, t6) +lh t6, (#256, t6) +lh t6, (#512, t6) +lh t6, (#1024, t6) +lh t6, (#2047, t6) + diff --git a/tests/riscv/rv32i/lh.bin b/tests/riscv/rv32i/lh.bin new file mode 100644 index 0000000000000000000000000000000000000000..bfaf3b5b69b80b292f5214f2caaef011d10b98f7 GIT binary patch literal 6400 zcmWmG;iep28iwKes#7Xj(_7Js)>I1-BIFcGh!7!%)LY6HBBU*r#j;qZvVDwU408%) z7{eGQhA}a=?78ye{*!q3({HJ#?ss!@bGx}|?y=%Ke&7K=@wmCU#XVMhN7HO>Zg9qo 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(#0xfffff801, zero) +lh zero, (#0xfffffc00, zero) +lh zero, (#0xfffffe00, zero) +lh zero, (#0xffffff00, zero) +lh zero, (#0xffffff80, zero) +lh zero, (#0xffffffc0, zero) +lh zero, (#0xffffffe0, zero) +lh zero, (#0xfffffff0, zero) +lh zero, (#0xfffffff8, zero) +lh zero, (#0xfffffffc, zero) +lh zero, (#0xfffffffe, zero) +lh zero, (#0xffffffff, zero) +lh zero, (#0, zero) +lh zero, (#1, zero) +lh zero, (#2, zero) +lh zero, (#4, zero) +lh zero, (#8, zero) +lh zero, (#0x10, zero) +lh zero, (#0x20, zero) +lh zero, (#0x40, zero) +lh zero, (#0x80, zero) +lh zero, (#0x100, zero) +lh zero, (#0x200, zero) +lh zero, (#0x400, zero) +lh zero, (#0x7ff, zero) +lh zero, (#0xfffff801, ra) +lh zero, (#0xfffffc00, ra) +lh zero, (#0xfffffe00, ra) +lh zero, (#0xffffff00, ra) +lh zero, (#0xffffff80, ra) +lh zero, (#0xffffffc0, ra) +lh zero, (#0xffffffe0, ra) +lh zero, (#0xfffffff0, ra) +lh zero, (#0xfffffff8, ra) +lh zero, (#0xfffffffc, ra) +lh zero, (#0xfffffffe, ra) +lh zero, (#0xffffffff, ra) +lh zero, (#0, ra) +lh zero, (#1, ra) +lh zero, (#2, ra) +lh zero, (#4, ra) +lh zero, (#8, ra) +lh zero, (#0x10, ra) +lh zero, (#0x20, ra) +lh zero, (#0x40, ra) +lh zero, (#0x80, ra) +lh zero, (#0x100, ra) +lh zero, (#0x200, ra) +lh zero, (#0x400, ra) +lh zero, (#0x7ff, ra) +lh zero, (#0xfffff801, t0) +lh zero, (#0xfffffc00, t0) +lh zero, (#0xfffffe00, t0) +lh zero, (#0xffffff00, t0) +lh zero, (#0xffffff80, t0) +lh zero, (#0xffffffc0, t0) +lh zero, (#0xffffffe0, t0) +lh zero, (#0xfffffff0, t0) +lh zero, (#0xfffffff8, t0) +lh zero, (#0xfffffffc, t0) +lh zero, (#0xfffffffe, t0) +lh zero, (#0xffffffff, t0) +lh zero, (#0, t0) +lh zero, (#1, t0) +lh zero, (#2, t0) +lh zero, (#4, t0) +lh zero, (#8, t0) +lh zero, (#0x10, t0) +lh zero, (#0x20, t0) +lh zero, (#0x40, t0) +lh zero, (#0x80, t0) +lh zero, (#0x100, t0) +lh zero, (#0x200, t0) +lh zero, (#0x400, t0) +lh zero, (#0x7ff, t0) +lh zero, (#0xfffff801, a0) +lh zero, (#0xfffffc00, a0) +lh zero, (#0xfffffe00, a0) +lh zero, (#0xffffff00, a0) +lh zero, (#0xffffff80, a0) +lh zero, (#0xffffffc0, a0) +lh zero, (#0xffffffe0, a0) +lh zero, (#0xfffffff0, a0) +lh zero, (#0xfffffff8, a0) +lh zero, (#0xfffffffc, a0) +lh zero, (#0xfffffffe, a0) +lh zero, (#0xffffffff, a0) +lh zero, (#0, a0) +lh zero, (#1, a0) +lh zero, (#2, a0) +lh zero, (#4, a0) +lh zero, (#8, a0) +lh zero, (#0x10, a0) +lh zero, (#0x20, a0) +lh zero, (#0x40, a0) +lh zero, (#0x80, a0) +lh zero, (#0x100, a0) +lh zero, (#0x200, a0) +lh zero, (#0x400, a0) +lh zero, (#0x7ff, a0) +lh zero, (#0xfffff801, a5) +lh zero, (#0xfffffc00, a5) +lh zero, (#0xfffffe00, a5) +lh zero, (#0xffffff00, a5) +lh zero, (#0xffffff80, a5) +lh zero, (#0xffffffc0, a5) +lh zero, (#0xffffffe0, a5) +lh zero, (#0xfffffff0, a5) +lh zero, (#0xfffffff8, a5) +lh zero, (#0xfffffffc, a5) +lh zero, (#0xfffffffe, a5) +lh zero, (#0xffffffff, a5) +lh zero, (#0, a5) +lh zero, (#1, a5) +lh zero, (#2, a5) +lh zero, (#4, a5) +lh zero, (#8, a5) +lh zero, (#0x10, a5) +lh zero, (#0x20, a5) +lh zero, (#0x40, a5) +lh zero, (#0x80, a5) +lh zero, (#0x100, a5) +lh zero, (#0x200, a5) +lh zero, (#0x400, a5) +lh zero, (#0x7ff, a5) +lh zero, (#0xfffff801, s4) +lh zero, (#0xfffffc00, s4) +lh zero, (#0xfffffe00, s4) +lh zero, (#0xffffff00, s4) +lh zero, (#0xffffff80, s4) +lh zero, (#0xffffffc0, s4) +lh zero, (#0xffffffe0, s4) +lh zero, (#0xfffffff0, s4) +lh zero, (#0xfffffff8, s4) +lh zero, (#0xfffffffc, s4) +lh zero, (#0xfffffffe, s4) +lh zero, (#0xffffffff, s4) +lh zero, (#0, s4) +lh zero, (#1, s4) +lh zero, (#2, s4) +lh zero, (#4, s4) +lh zero, (#8, s4) +lh zero, (#0x10, s4) +lh zero, (#0x20, s4) +lh zero, (#0x40, s4) +lh zero, (#0x80, s4) +lh zero, (#0x100, s4) +lh zero, (#0x200, s4) +lh zero, (#0x400, s4) +lh zero, (#0x7ff, s4) +lh zero, (#0xfffff801, s9) +lh zero, (#0xfffffc00, s9) +lh zero, (#0xfffffe00, s9) +lh zero, (#0xffffff00, s9) +lh zero, (#0xffffff80, s9) +lh zero, (#0xffffffc0, s9) +lh zero, (#0xffffffe0, s9) +lh zero, (#0xfffffff0, s9) +lh zero, (#0xfffffff8, s9) +lh zero, (#0xfffffffc, s9) +lh zero, (#0xfffffffe, s9) +lh zero, (#0xffffffff, s9) +lh zero, (#0, s9) +lh zero, (#1, s9) +lh zero, (#2, s9) +lh zero, (#4, s9) +lh zero, (#8, s9) +lh zero, (#0x10, s9) +lh zero, (#0x20, s9) +lh zero, (#0x40, s9) +lh zero, (#0x80, s9) +lh zero, (#0x100, s9) +lh zero, (#0x200, s9) +lh zero, (#0x400, s9) +lh zero, (#0x7ff, s9) +lh zero, (#0xfffff801, t6) +lh zero, (#0xfffffc00, t6) +lh zero, (#0xfffffe00, t6) +lh zero, (#0xffffff00, t6) +lh zero, (#0xffffff80, t6) +lh zero, (#0xffffffc0, t6) +lh zero, (#0xffffffe0, t6) +lh zero, (#0xfffffff0, t6) +lh zero, (#0xfffffff8, t6) +lh zero, (#0xfffffffc, t6) +lh zero, (#0xfffffffe, t6) +lh zero, (#0xffffffff, t6) +lh zero, (#0, t6) +lh zero, (#1, t6) +lh zero, (#2, t6) +lh zero, (#4, t6) +lh zero, (#8, t6) +lh zero, (#0x10, t6) +lh zero, (#0x20, t6) +lh zero, (#0x40, t6) +lh zero, (#0x80, t6) +lh zero, (#0x100, t6) +lh zero, (#0x200, t6) +lh zero, (#0x400, t6) +lh zero, (#0x7ff, t6) +lh ra, (#0xfffff801, zero) +lh ra, (#0xfffffc00, zero) +lh ra, (#0xfffffe00, zero) +lh ra, (#0xffffff00, zero) +lh ra, (#0xffffff80, zero) +lh ra, (#0xffffffc0, zero) +lh ra, (#0xffffffe0, zero) +lh ra, (#0xfffffff0, zero) +lh ra, (#0xfffffff8, zero) +lh ra, (#0xfffffffc, zero) +lh ra, (#0xfffffffe, zero) +lh ra, (#0xffffffff, zero) +lh ra, (#0, zero) +lh ra, (#1, zero) +lh ra, (#2, zero) +lh ra, (#4, zero) +lh ra, (#8, zero) +lh ra, (#0x10, zero) +lh ra, (#0x20, zero) +lh ra, (#0x40, zero) +lh ra, (#0x80, zero) +lh ra, (#0x100, zero) +lh ra, (#0x200, zero) +lh ra, (#0x400, zero) +lh ra, (#0x7ff, zero) +lh ra, (#0xfffff801, ra) +lh ra, (#0xfffffc00, ra) +lh ra, (#0xfffffe00, ra) +lh ra, (#0xffffff00, ra) +lh ra, (#0xffffff80, ra) +lh ra, (#0xffffffc0, ra) +lh ra, (#0xffffffe0, ra) +lh ra, (#0xfffffff0, ra) +lh ra, (#0xfffffff8, ra) +lh ra, (#0xfffffffc, ra) +lh ra, (#0xfffffffe, ra) +lh ra, (#0xffffffff, ra) +lh ra, (#0, ra) +lh ra, (#1, ra) +lh ra, (#2, ra) +lh ra, (#4, ra) +lh ra, (#8, ra) +lh ra, (#0x10, ra) +lh ra, (#0x20, ra) +lh ra, (#0x40, ra) +lh ra, (#0x80, ra) +lh ra, (#0x100, ra) +lh ra, (#0x200, ra) +lh ra, (#0x400, ra) +lh ra, (#0x7ff, ra) +lh ra, (#0xfffff801, t0) +lh ra, (#0xfffffc00, t0) +lh ra, (#0xfffffe00, t0) +lh ra, (#0xffffff00, t0) +lh ra, (#0xffffff80, t0) +lh ra, (#0xffffffc0, t0) +lh ra, (#0xffffffe0, t0) +lh ra, (#0xfffffff0, t0) +lh ra, (#0xfffffff8, t0) +lh ra, (#0xfffffffc, t0) +lh ra, (#0xfffffffe, t0) +lh ra, (#0xffffffff, t0) +lh ra, (#0, t0) +lh ra, (#1, t0) +lh ra, (#2, t0) +lh ra, (#4, t0) +lh ra, (#8, t0) +lh ra, (#0x10, t0) +lh ra, (#0x20, t0) +lh ra, (#0x40, t0) +lh ra, (#0x80, t0) +lh ra, (#0x100, t0) +lh ra, (#0x200, t0) +lh ra, (#0x400, t0) +lh ra, (#0x7ff, t0) +lh ra, (#0xfffff801, a0) +lh ra, (#0xfffffc00, a0) +lh ra, (#0xfffffe00, a0) +lh ra, (#0xffffff00, a0) +lh ra, (#0xffffff80, a0) +lh ra, (#0xffffffc0, a0) +lh ra, (#0xffffffe0, a0) +lh ra, (#0xfffffff0, a0) +lh ra, (#0xfffffff8, a0) +lh ra, (#0xfffffffc, a0) +lh ra, (#0xfffffffe, a0) +lh ra, (#0xffffffff, a0) +lh ra, (#0, a0) +lh ra, (#1, a0) +lh ra, (#2, a0) +lh ra, (#4, a0) +lh ra, (#8, a0) +lh ra, (#0x10, a0) +lh ra, (#0x20, a0) +lh ra, (#0x40, a0) +lh ra, (#0x80, a0) +lh ra, (#0x100, a0) +lh ra, (#0x200, a0) +lh ra, (#0x400, a0) +lh ra, (#0x7ff, a0) +lh ra, (#0xfffff801, a5) +lh ra, (#0xfffffc00, a5) +lh ra, (#0xfffffe00, a5) +lh ra, (#0xffffff00, a5) +lh ra, (#0xffffff80, a5) +lh ra, (#0xffffffc0, a5) +lh ra, (#0xffffffe0, a5) +lh ra, (#0xfffffff0, a5) +lh ra, (#0xfffffff8, a5) +lh ra, (#0xfffffffc, a5) +lh ra, (#0xfffffffe, a5) +lh ra, (#0xffffffff, a5) +lh ra, (#0, a5) +lh ra, (#1, a5) +lh ra, (#2, a5) +lh ra, (#4, a5) +lh ra, (#8, a5) +lh ra, (#0x10, a5) +lh ra, (#0x20, a5) +lh ra, (#0x40, a5) +lh ra, (#0x80, a5) +lh ra, (#0x100, a5) +lh ra, (#0x200, a5) +lh ra, (#0x400, a5) +lh ra, (#0x7ff, a5) +lh ra, (#0xfffff801, s4) +lh ra, (#0xfffffc00, s4) +lh ra, (#0xfffffe00, s4) +lh ra, (#0xffffff00, s4) +lh ra, (#0xffffff80, s4) +lh ra, (#0xffffffc0, s4) +lh ra, (#0xffffffe0, s4) +lh ra, (#0xfffffff0, s4) +lh ra, (#0xfffffff8, s4) +lh ra, (#0xfffffffc, s4) +lh ra, (#0xfffffffe, s4) +lh ra, (#0xffffffff, s4) +lh ra, (#0, s4) +lh ra, (#1, s4) +lh ra, (#2, s4) +lh ra, (#4, s4) +lh ra, (#8, s4) +lh ra, (#0x10, s4) +lh ra, (#0x20, s4) +lh ra, (#0x40, s4) +lh ra, (#0x80, s4) +lh ra, (#0x100, s4) +lh ra, (#0x200, s4) +lh ra, (#0x400, s4) +lh ra, (#0x7ff, s4) +lh ra, (#0xfffff801, s9) +lh ra, (#0xfffffc00, s9) +lh ra, (#0xfffffe00, s9) +lh ra, (#0xffffff00, s9) +lh ra, (#0xffffff80, s9) +lh ra, (#0xffffffc0, s9) +lh ra, (#0xffffffe0, s9) +lh ra, (#0xfffffff0, s9) +lh ra, (#0xfffffff8, s9) +lh ra, (#0xfffffffc, s9) +lh ra, (#0xfffffffe, s9) +lh ra, (#0xffffffff, s9) +lh ra, (#0, s9) +lh ra, (#1, s9) +lh ra, (#2, s9) +lh ra, (#4, s9) +lh ra, (#8, s9) +lh ra, (#0x10, s9) +lh ra, (#0x20, s9) +lh ra, (#0x40, s9) +lh ra, (#0x80, s9) +lh ra, (#0x100, s9) +lh ra, (#0x200, s9) +lh ra, (#0x400, s9) +lh ra, (#0x7ff, s9) +lh ra, (#0xfffff801, t6) +lh ra, (#0xfffffc00, t6) +lh ra, (#0xfffffe00, t6) +lh ra, (#0xffffff00, t6) +lh ra, (#0xffffff80, t6) +lh ra, (#0xffffffc0, t6) +lh ra, (#0xffffffe0, t6) +lh ra, (#0xfffffff0, t6) +lh ra, (#0xfffffff8, t6) +lh ra, (#0xfffffffc, t6) +lh ra, (#0xfffffffe, t6) +lh ra, (#0xffffffff, t6) +lh ra, (#0, t6) +lh ra, (#1, t6) +lh ra, (#2, t6) +lh ra, (#4, t6) +lh ra, (#8, t6) +lh ra, (#0x10, t6) +lh ra, (#0x20, t6) +lh ra, (#0x40, t6) +lh ra, (#0x80, t6) +lh ra, (#0x100, t6) +lh ra, (#0x200, t6) +lh ra, (#0x400, t6) +lh ra, (#0x7ff, t6) +lh t0, (#0xfffff801, zero) +lh t0, (#0xfffffc00, zero) +lh t0, (#0xfffffe00, zero) +lh t0, (#0xffffff00, zero) +lh t0, (#0xffffff80, zero) +lh t0, (#0xffffffc0, zero) +lh t0, (#0xffffffe0, zero) +lh t0, (#0xfffffff0, zero) +lh t0, (#0xfffffff8, zero) +lh t0, (#0xfffffffc, zero) +lh t0, (#0xfffffffe, zero) +lh t0, (#0xffffffff, zero) +lh t0, (#0, zero) +lh t0, (#1, zero) +lh t0, (#2, zero) +lh t0, (#4, zero) +lh t0, (#8, zero) +lh t0, (#0x10, zero) +lh t0, (#0x20, zero) +lh t0, (#0x40, zero) +lh t0, (#0x80, zero) +lh t0, (#0x100, zero) +lh t0, (#0x200, zero) +lh t0, (#0x400, zero) +lh t0, (#0x7ff, zero) +lh t0, (#0xfffff801, ra) +lh t0, (#0xfffffc00, ra) +lh t0, (#0xfffffe00, ra) +lh t0, (#0xffffff00, ra) +lh t0, (#0xffffff80, ra) +lh t0, (#0xffffffc0, ra) +lh t0, (#0xffffffe0, ra) +lh t0, (#0xfffffff0, ra) +lh t0, (#0xfffffff8, ra) +lh t0, (#0xfffffffc, ra) +lh t0, (#0xfffffffe, ra) +lh t0, (#0xffffffff, ra) +lh t0, (#0, ra) +lh t0, (#1, ra) +lh t0, (#2, ra) +lh t0, (#4, ra) +lh t0, (#8, ra) +lh t0, (#0x10, ra) +lh t0, (#0x20, ra) +lh t0, (#0x40, ra) +lh t0, (#0x80, ra) +lh t0, (#0x100, ra) +lh t0, (#0x200, ra) +lh t0, (#0x400, ra) +lh t0, (#0x7ff, ra) +lh t0, (#0xfffff801, t0) +lh t0, (#0xfffffc00, t0) +lh t0, (#0xfffffe00, t0) +lh t0, (#0xffffff00, t0) +lh t0, (#0xffffff80, t0) +lh t0, (#0xffffffc0, t0) +lh t0, (#0xffffffe0, t0) +lh t0, (#0xfffffff0, t0) +lh t0, (#0xfffffff8, t0) +lh t0, (#0xfffffffc, t0) +lh t0, (#0xfffffffe, t0) +lh t0, (#0xffffffff, t0) +lh t0, (#0, t0) +lh t0, (#1, t0) +lh t0, (#2, t0) +lh t0, (#4, t0) +lh t0, (#8, t0) +lh t0, (#0x10, t0) +lh t0, (#0x20, t0) +lh t0, (#0x40, t0) +lh t0, (#0x80, t0) +lh t0, (#0x100, t0) +lh t0, (#0x200, t0) +lh t0, (#0x400, t0) +lh t0, (#0x7ff, t0) +lh t0, (#0xfffff801, a0) +lh t0, (#0xfffffc00, a0) +lh t0, (#0xfffffe00, a0) +lh t0, (#0xffffff00, a0) +lh t0, (#0xffffff80, a0) +lh t0, (#0xffffffc0, a0) +lh t0, (#0xffffffe0, a0) +lh t0, (#0xfffffff0, a0) +lh t0, (#0xfffffff8, a0) +lh t0, (#0xfffffffc, a0) +lh t0, (#0xfffffffe, a0) +lh t0, (#0xffffffff, a0) +lh t0, (#0, a0) +lh t0, (#1, a0) +lh t0, (#2, a0) +lh t0, (#4, a0) +lh t0, (#8, a0) +lh t0, (#0x10, a0) +lh t0, (#0x20, a0) +lh t0, (#0x40, a0) +lh t0, (#0x80, a0) +lh t0, (#0x100, a0) +lh t0, (#0x200, a0) +lh t0, (#0x400, a0) +lh t0, (#0x7ff, a0) +lh t0, (#0xfffff801, a5) +lh t0, (#0xfffffc00, a5) +lh t0, (#0xfffffe00, a5) +lh t0, (#0xffffff00, a5) +lh t0, (#0xffffff80, a5) +lh t0, (#0xffffffc0, a5) +lh t0, (#0xffffffe0, a5) +lh t0, (#0xfffffff0, a5) +lh t0, (#0xfffffff8, a5) +lh t0, (#0xfffffffc, a5) +lh t0, (#0xfffffffe, a5) +lh t0, (#0xffffffff, a5) +lh t0, (#0, a5) +lh t0, (#1, a5) +lh t0, (#2, a5) +lh t0, (#4, a5) +lh t0, (#8, a5) +lh t0, (#0x10, a5) +lh t0, (#0x20, a5) +lh t0, (#0x40, a5) +lh t0, (#0x80, a5) +lh t0, (#0x100, a5) +lh t0, (#0x200, a5) +lh t0, (#0x400, a5) +lh t0, (#0x7ff, a5) +lh t0, (#0xfffff801, s4) +lh t0, (#0xfffffc00, s4) +lh t0, (#0xfffffe00, s4) +lh t0, (#0xffffff00, s4) +lh t0, (#0xffffff80, s4) +lh t0, (#0xffffffc0, s4) +lh t0, (#0xffffffe0, s4) +lh t0, (#0xfffffff0, s4) +lh t0, (#0xfffffff8, s4) +lh t0, (#0xfffffffc, s4) +lh t0, (#0xfffffffe, s4) +lh t0, (#0xffffffff, s4) +lh t0, (#0, s4) +lh t0, (#1, s4) +lh t0, (#2, s4) +lh t0, (#4, s4) +lh t0, (#8, s4) +lh t0, (#0x10, s4) +lh t0, (#0x20, s4) +lh t0, (#0x40, s4) +lh t0, (#0x80, s4) +lh t0, (#0x100, s4) +lh t0, (#0x200, s4) +lh t0, (#0x400, s4) +lh t0, (#0x7ff, s4) +lh t0, (#0xfffff801, s9) +lh t0, (#0xfffffc00, s9) +lh t0, (#0xfffffe00, s9) +lh t0, (#0xffffff00, s9) +lh t0, (#0xffffff80, s9) +lh t0, (#0xffffffc0, s9) +lh t0, (#0xffffffe0, s9) +lh t0, (#0xfffffff0, s9) +lh t0, (#0xfffffff8, s9) +lh t0, (#0xfffffffc, s9) +lh t0, (#0xfffffffe, s9) +lh t0, (#0xffffffff, s9) +lh t0, (#0, s9) +lh t0, (#1, s9) +lh t0, (#2, s9) +lh t0, (#4, s9) +lh t0, (#8, s9) +lh t0, (#0x10, s9) +lh t0, (#0x20, s9) +lh t0, (#0x40, s9) +lh t0, (#0x80, s9) +lh t0, (#0x100, s9) +lh t0, (#0x200, s9) +lh t0, (#0x400, s9) +lh t0, (#0x7ff, s9) +lh t0, (#0xfffff801, t6) +lh t0, (#0xfffffc00, t6) +lh t0, (#0xfffffe00, t6) +lh t0, (#0xffffff00, t6) +lh t0, (#0xffffff80, t6) +lh t0, (#0xffffffc0, t6) +lh t0, (#0xffffffe0, t6) +lh t0, (#0xfffffff0, t6) +lh t0, (#0xfffffff8, t6) +lh t0, (#0xfffffffc, t6) +lh t0, (#0xfffffffe, t6) +lh t0, (#0xffffffff, t6) +lh t0, (#0, t6) +lh t0, (#1, t6) +lh t0, (#2, t6) +lh t0, (#4, t6) +lh t0, (#8, t6) +lh t0, (#0x10, t6) +lh t0, (#0x20, t6) +lh t0, (#0x40, t6) +lh t0, (#0x80, t6) +lh t0, (#0x100, t6) +lh t0, (#0x200, t6) +lh t0, (#0x400, t6) +lh t0, (#0x7ff, t6) +lh a0, (#0xfffff801, zero) +lh a0, (#0xfffffc00, zero) +lh a0, (#0xfffffe00, zero) +lh a0, (#0xffffff00, zero) +lh a0, (#0xffffff80, zero) +lh a0, (#0xffffffc0, zero) +lh a0, (#0xffffffe0, zero) +lh a0, (#0xfffffff0, zero) +lh a0, (#0xfffffff8, zero) +lh a0, (#0xfffffffc, zero) +lh a0, (#0xfffffffe, zero) +lh a0, (#0xffffffff, zero) +lh a0, (#0, zero) +lh a0, (#1, zero) +lh a0, (#2, zero) +lh a0, (#4, zero) +lh a0, (#8, zero) +lh a0, (#0x10, zero) +lh a0, (#0x20, zero) +lh a0, (#0x40, zero) +lh a0, (#0x80, zero) +lh a0, (#0x100, zero) +lh a0, (#0x200, zero) +lh a0, (#0x400, zero) +lh a0, (#0x7ff, zero) +lh a0, (#0xfffff801, ra) +lh a0, (#0xfffffc00, ra) +lh a0, (#0xfffffe00, ra) +lh a0, (#0xffffff00, ra) +lh a0, (#0xffffff80, ra) +lh a0, (#0xffffffc0, ra) +lh a0, (#0xffffffe0, ra) +lh a0, (#0xfffffff0, ra) +lh a0, (#0xfffffff8, ra) +lh a0, (#0xfffffffc, ra) +lh a0, (#0xfffffffe, ra) +lh a0, (#0xffffffff, ra) +lh a0, (#0, ra) +lh a0, (#1, ra) +lh a0, (#2, ra) +lh a0, (#4, ra) +lh a0, (#8, ra) +lh a0, (#0x10, ra) +lh a0, (#0x20, ra) +lh a0, (#0x40, ra) +lh a0, (#0x80, ra) +lh a0, (#0x100, ra) +lh a0, (#0x200, ra) +lh a0, (#0x400, ra) +lh a0, (#0x7ff, ra) +lh a0, (#0xfffff801, t0) +lh a0, (#0xfffffc00, t0) +lh a0, (#0xfffffe00, t0) +lh a0, (#0xffffff00, t0) +lh a0, (#0xffffff80, t0) +lh a0, (#0xffffffc0, t0) +lh a0, (#0xffffffe0, t0) +lh a0, (#0xfffffff0, t0) +lh a0, (#0xfffffff8, t0) +lh a0, (#0xfffffffc, t0) +lh a0, (#0xfffffffe, t0) +lh a0, (#0xffffffff, t0) +lh a0, (#0, t0) +lh a0, (#1, t0) +lh a0, (#2, t0) +lh a0, (#4, t0) +lh a0, (#8, t0) +lh a0, (#0x10, t0) +lh a0, (#0x20, t0) +lh a0, (#0x40, t0) +lh a0, (#0x80, t0) +lh a0, (#0x100, t0) +lh a0, (#0x200, t0) +lh a0, (#0x400, t0) +lh a0, (#0x7ff, t0) +lh a0, (#0xfffff801, a0) +lh a0, (#0xfffffc00, a0) +lh a0, (#0xfffffe00, a0) +lh a0, (#0xffffff00, a0) +lh a0, (#0xffffff80, a0) +lh a0, (#0xffffffc0, a0) +lh a0, (#0xffffffe0, a0) +lh a0, (#0xfffffff0, a0) +lh a0, (#0xfffffff8, a0) +lh a0, (#0xfffffffc, a0) +lh a0, (#0xfffffffe, a0) +lh a0, (#0xffffffff, a0) +lh a0, (#0, a0) +lh a0, (#1, a0) +lh a0, (#2, a0) +lh a0, (#4, a0) +lh a0, (#8, a0) +lh a0, (#0x10, a0) +lh a0, (#0x20, a0) +lh a0, (#0x40, a0) +lh a0, (#0x80, a0) +lh a0, (#0x100, a0) +lh a0, (#0x200, a0) +lh a0, (#0x400, a0) +lh a0, (#0x7ff, a0) +lh a0, (#0xfffff801, a5) +lh a0, (#0xfffffc00, a5) +lh a0, (#0xfffffe00, a5) +lh a0, (#0xffffff00, a5) +lh a0, (#0xffffff80, a5) +lh a0, (#0xffffffc0, a5) +lh a0, (#0xffffffe0, a5) +lh a0, (#0xfffffff0, a5) +lh a0, (#0xfffffff8, a5) +lh a0, (#0xfffffffc, a5) +lh a0, (#0xfffffffe, a5) +lh a0, (#0xffffffff, a5) +lh a0, (#0, a5) +lh a0, (#1, a5) +lh a0, (#2, a5) +lh a0, (#4, a5) +lh a0, (#8, a5) +lh a0, (#0x10, a5) +lh a0, (#0x20, a5) +lh a0, (#0x40, a5) +lh a0, (#0x80, a5) +lh a0, (#0x100, a5) +lh a0, (#0x200, a5) +lh a0, (#0x400, a5) +lh a0, (#0x7ff, a5) +lh a0, (#0xfffff801, s4) +lh a0, (#0xfffffc00, s4) +lh a0, (#0xfffffe00, s4) +lh a0, (#0xffffff00, s4) +lh a0, (#0xffffff80, s4) +lh a0, (#0xffffffc0, s4) +lh a0, (#0xffffffe0, s4) +lh a0, (#0xfffffff0, s4) +lh a0, (#0xfffffff8, s4) +lh a0, (#0xfffffffc, s4) +lh a0, (#0xfffffffe, s4) +lh a0, (#0xffffffff, s4) +lh a0, (#0, s4) +lh a0, (#1, s4) +lh a0, (#2, s4) +lh a0, (#4, s4) +lh a0, (#8, s4) +lh a0, (#0x10, s4) +lh a0, (#0x20, s4) +lh a0, (#0x40, s4) +lh a0, (#0x80, s4) +lh a0, (#0x100, s4) +lh a0, (#0x200, s4) +lh a0, (#0x400, s4) +lh a0, (#0x7ff, s4) +lh a0, (#0xfffff801, s9) +lh a0, (#0xfffffc00, s9) +lh a0, (#0xfffffe00, s9) +lh a0, (#0xffffff00, s9) +lh a0, (#0xffffff80, s9) +lh a0, (#0xffffffc0, s9) +lh a0, (#0xffffffe0, s9) +lh a0, (#0xfffffff0, s9) +lh a0, (#0xfffffff8, s9) +lh a0, (#0xfffffffc, s9) +lh a0, (#0xfffffffe, s9) +lh a0, (#0xffffffff, s9) +lh a0, (#0, s9) +lh a0, (#1, s9) +lh a0, (#2, s9) +lh a0, (#4, s9) +lh a0, (#8, s9) +lh a0, (#0x10, s9) +lh a0, (#0x20, s9) +lh a0, (#0x40, s9) +lh a0, (#0x80, s9) +lh a0, (#0x100, s9) +lh a0, (#0x200, s9) +lh a0, (#0x400, s9) +lh a0, (#0x7ff, s9) +lh a0, (#0xfffff801, t6) +lh a0, (#0xfffffc00, t6) +lh a0, (#0xfffffe00, t6) +lh a0, (#0xffffff00, t6) +lh a0, (#0xffffff80, t6) +lh a0, (#0xffffffc0, t6) +lh a0, (#0xffffffe0, t6) +lh a0, (#0xfffffff0, t6) +lh a0, (#0xfffffff8, t6) +lh a0, (#0xfffffffc, t6) +lh a0, (#0xfffffffe, t6) +lh a0, (#0xffffffff, t6) +lh a0, (#0, t6) +lh a0, (#1, t6) +lh a0, (#2, t6) +lh a0, (#4, t6) +lh a0, (#8, t6) +lh a0, (#0x10, t6) +lh a0, (#0x20, t6) +lh a0, (#0x40, t6) +lh a0, (#0x80, t6) +lh a0, (#0x100, t6) +lh a0, (#0x200, t6) +lh a0, (#0x400, t6) +lh a0, (#0x7ff, t6) +lh a5, (#0xfffff801, zero) +lh a5, (#0xfffffc00, zero) +lh a5, (#0xfffffe00, zero) +lh a5, (#0xffffff00, zero) +lh a5, (#0xffffff80, zero) +lh a5, (#0xffffffc0, zero) +lh a5, (#0xffffffe0, zero) +lh a5, (#0xfffffff0, zero) +lh a5, (#0xfffffff8, zero) +lh a5, (#0xfffffffc, zero) +lh a5, (#0xfffffffe, zero) +lh a5, (#0xffffffff, zero) +lh a5, (#0, zero) +lh a5, (#1, zero) +lh a5, (#2, zero) +lh a5, (#4, zero) +lh a5, (#8, zero) +lh a5, (#0x10, zero) +lh a5, (#0x20, zero) +lh a5, (#0x40, zero) +lh a5, (#0x80, zero) +lh a5, (#0x100, zero) +lh a5, (#0x200, zero) +lh a5, (#0x400, zero) +lh a5, (#0x7ff, zero) +lh a5, (#0xfffff801, ra) +lh a5, (#0xfffffc00, ra) +lh a5, (#0xfffffe00, ra) +lh a5, (#0xffffff00, ra) +lh a5, (#0xffffff80, ra) +lh a5, (#0xffffffc0, ra) +lh a5, (#0xffffffe0, ra) +lh a5, (#0xfffffff0, ra) +lh a5, (#0xfffffff8, ra) +lh a5, (#0xfffffffc, ra) +lh a5, (#0xfffffffe, ra) +lh a5, (#0xffffffff, ra) +lh a5, (#0, ra) +lh a5, (#1, ra) +lh a5, (#2, ra) +lh a5, (#4, ra) +lh a5, (#8, ra) +lh a5, (#0x10, ra) +lh a5, (#0x20, ra) +lh a5, (#0x40, ra) +lh a5, (#0x80, ra) +lh a5, (#0x100, ra) +lh a5, (#0x200, ra) +lh a5, (#0x400, ra) +lh a5, (#0x7ff, ra) +lh a5, (#0xfffff801, t0) +lh a5, (#0xfffffc00, t0) +lh a5, (#0xfffffe00, t0) +lh a5, (#0xffffff00, t0) +lh a5, (#0xffffff80, t0) +lh a5, (#0xffffffc0, t0) +lh a5, (#0xffffffe0, t0) +lh a5, (#0xfffffff0, t0) +lh a5, (#0xfffffff8, t0) +lh a5, (#0xfffffffc, t0) +lh a5, (#0xfffffffe, t0) +lh a5, (#0xffffffff, t0) +lh a5, (#0, t0) +lh a5, (#1, t0) +lh a5, (#2, t0) +lh a5, (#4, t0) +lh a5, (#8, t0) +lh a5, (#0x10, t0) +lh a5, (#0x20, t0) +lh a5, (#0x40, t0) +lh a5, (#0x80, t0) +lh a5, (#0x100, t0) +lh a5, (#0x200, t0) +lh a5, (#0x400, t0) +lh a5, (#0x7ff, t0) +lh a5, (#0xfffff801, a0) +lh a5, (#0xfffffc00, a0) +lh a5, (#0xfffffe00, a0) +lh a5, (#0xffffff00, a0) +lh a5, (#0xffffff80, a0) +lh a5, (#0xffffffc0, a0) +lh a5, (#0xffffffe0, a0) +lh a5, (#0xfffffff0, a0) +lh a5, (#0xfffffff8, a0) +lh a5, (#0xfffffffc, a0) +lh a5, (#0xfffffffe, a0) +lh a5, (#0xffffffff, a0) +lh a5, (#0, a0) +lh a5, (#1, a0) +lh a5, (#2, a0) +lh a5, (#4, a0) +lh a5, (#8, a0) +lh a5, (#0x10, a0) +lh a5, (#0x20, a0) +lh a5, (#0x40, a0) +lh a5, (#0x80, a0) +lh a5, (#0x100, a0) +lh a5, (#0x200, a0) +lh a5, (#0x400, a0) +lh a5, (#0x7ff, a0) +lh a5, (#0xfffff801, a5) +lh a5, (#0xfffffc00, a5) +lh a5, (#0xfffffe00, a5) +lh a5, (#0xffffff00, a5) +lh a5, (#0xffffff80, a5) +lh a5, (#0xffffffc0, a5) +lh a5, (#0xffffffe0, a5) +lh a5, (#0xfffffff0, a5) +lh a5, (#0xfffffff8, a5) +lh a5, (#0xfffffffc, a5) +lh a5, (#0xfffffffe, a5) +lh a5, (#0xffffffff, a5) +lh a5, (#0, a5) +lh a5, (#1, a5) +lh a5, (#2, a5) +lh a5, (#4, a5) +lh a5, (#8, a5) +lh a5, (#0x10, a5) +lh a5, (#0x20, a5) +lh a5, (#0x40, a5) +lh a5, (#0x80, a5) +lh a5, (#0x100, a5) +lh a5, (#0x200, a5) +lh a5, (#0x400, a5) +lh a5, (#0x7ff, a5) +lh a5, (#0xfffff801, s4) +lh a5, (#0xfffffc00, s4) +lh a5, (#0xfffffe00, s4) +lh a5, (#0xffffff00, s4) +lh a5, (#0xffffff80, s4) +lh a5, (#0xffffffc0, s4) +lh a5, (#0xffffffe0, s4) +lh a5, (#0xfffffff0, s4) +lh a5, (#0xfffffff8, s4) +lh a5, (#0xfffffffc, s4) +lh a5, (#0xfffffffe, s4) +lh a5, (#0xffffffff, s4) +lh a5, (#0, s4) +lh a5, (#1, s4) +lh a5, (#2, s4) +lh a5, (#4, s4) +lh a5, (#8, s4) +lh a5, (#0x10, s4) +lh a5, (#0x20, s4) +lh a5, (#0x40, s4) +lh a5, (#0x80, s4) +lh a5, (#0x100, s4) +lh a5, (#0x200, s4) +lh a5, (#0x400, s4) +lh a5, (#0x7ff, s4) +lh a5, (#0xfffff801, s9) +lh a5, (#0xfffffc00, s9) +lh a5, (#0xfffffe00, s9) +lh a5, (#0xffffff00, s9) +lh a5, (#0xffffff80, s9) +lh a5, (#0xffffffc0, s9) +lh a5, (#0xffffffe0, s9) +lh a5, (#0xfffffff0, s9) +lh a5, (#0xfffffff8, s9) +lh a5, (#0xfffffffc, s9) +lh a5, (#0xfffffffe, s9) +lh a5, (#0xffffffff, s9) +lh a5, (#0, s9) +lh a5, (#1, s9) +lh a5, (#2, s9) +lh a5, (#4, s9) +lh a5, (#8, s9) +lh a5, (#0x10, s9) +lh a5, (#0x20, s9) +lh a5, (#0x40, s9) +lh a5, (#0x80, s9) +lh a5, (#0x100, s9) +lh a5, (#0x200, s9) +lh a5, (#0x400, s9) +lh a5, (#0x7ff, s9) +lh a5, (#0xfffff801, t6) +lh a5, (#0xfffffc00, t6) +lh a5, (#0xfffffe00, t6) +lh a5, (#0xffffff00, t6) +lh a5, (#0xffffff80, t6) +lh a5, (#0xffffffc0, t6) +lh a5, (#0xffffffe0, t6) +lh a5, (#0xfffffff0, t6) +lh a5, (#0xfffffff8, t6) +lh a5, (#0xfffffffc, t6) +lh a5, (#0xfffffffe, t6) +lh a5, (#0xffffffff, t6) +lh a5, (#0, t6) +lh a5, (#1, t6) +lh a5, (#2, t6) +lh a5, (#4, t6) +lh a5, (#8, t6) +lh a5, (#0x10, t6) +lh a5, (#0x20, t6) +lh a5, (#0x40, t6) +lh a5, (#0x80, t6) +lh a5, (#0x100, t6) +lh a5, (#0x200, t6) +lh a5, (#0x400, t6) +lh a5, (#0x7ff, t6) +lh s4, (#0xfffff801, zero) +lh s4, (#0xfffffc00, zero) +lh s4, (#0xfffffe00, zero) +lh s4, (#0xffffff00, zero) +lh s4, (#0xffffff80, zero) +lh s4, (#0xffffffc0, zero) +lh s4, (#0xffffffe0, zero) +lh s4, (#0xfffffff0, zero) +lh s4, (#0xfffffff8, zero) +lh s4, (#0xfffffffc, zero) +lh s4, (#0xfffffffe, zero) +lh s4, (#0xffffffff, zero) +lh s4, (#0, zero) +lh s4, (#1, zero) +lh s4, (#2, zero) +lh s4, (#4, zero) +lh s4, (#8, zero) +lh s4, (#0x10, zero) +lh s4, (#0x20, zero) +lh s4, (#0x40, zero) +lh s4, (#0x80, zero) +lh s4, (#0x100, zero) +lh s4, (#0x200, zero) +lh s4, (#0x400, zero) +lh s4, (#0x7ff, zero) +lh s4, (#0xfffff801, ra) +lh s4, (#0xfffffc00, ra) +lh s4, (#0xfffffe00, ra) +lh s4, (#0xffffff00, ra) +lh s4, (#0xffffff80, ra) +lh s4, (#0xffffffc0, ra) +lh s4, (#0xffffffe0, ra) +lh s4, (#0xfffffff0, ra) +lh s4, (#0xfffffff8, ra) +lh s4, (#0xfffffffc, ra) +lh s4, (#0xfffffffe, ra) +lh s4, (#0xffffffff, ra) +lh s4, (#0, ra) +lh s4, (#1, ra) +lh s4, (#2, ra) +lh s4, (#4, ra) +lh s4, (#8, ra) +lh s4, (#0x10, ra) +lh s4, (#0x20, ra) +lh s4, (#0x40, ra) +lh s4, (#0x80, ra) +lh s4, (#0x100, ra) +lh s4, (#0x200, ra) +lh s4, (#0x400, ra) +lh s4, (#0x7ff, ra) +lh s4, (#0xfffff801, t0) +lh s4, (#0xfffffc00, t0) +lh s4, (#0xfffffe00, t0) +lh s4, (#0xffffff00, t0) +lh s4, (#0xffffff80, t0) +lh s4, (#0xffffffc0, t0) +lh s4, (#0xffffffe0, t0) +lh s4, (#0xfffffff0, t0) +lh s4, (#0xfffffff8, t0) +lh s4, (#0xfffffffc, t0) +lh s4, (#0xfffffffe, t0) +lh s4, (#0xffffffff, t0) +lh s4, (#0, t0) +lh s4, (#1, t0) +lh s4, (#2, t0) +lh s4, (#4, t0) +lh s4, (#8, t0) +lh s4, (#0x10, t0) +lh s4, (#0x20, t0) +lh s4, (#0x40, t0) +lh s4, (#0x80, t0) +lh s4, (#0x100, t0) +lh s4, (#0x200, t0) +lh s4, (#0x400, t0) +lh s4, (#0x7ff, t0) +lh s4, (#0xfffff801, a0) +lh s4, (#0xfffffc00, a0) +lh s4, (#0xfffffe00, a0) +lh s4, (#0xffffff00, a0) +lh s4, (#0xffffff80, a0) +lh s4, (#0xffffffc0, a0) +lh s4, (#0xffffffe0, a0) +lh s4, (#0xfffffff0, a0) +lh s4, (#0xfffffff8, a0) +lh s4, (#0xfffffffc, a0) +lh s4, (#0xfffffffe, a0) +lh s4, (#0xffffffff, a0) +lh s4, (#0, a0) +lh s4, (#1, a0) +lh s4, (#2, a0) +lh s4, (#4, a0) +lh s4, (#8, a0) +lh s4, (#0x10, a0) +lh s4, (#0x20, a0) +lh s4, (#0x40, a0) +lh s4, (#0x80, a0) +lh s4, (#0x100, a0) +lh s4, (#0x200, a0) +lh s4, (#0x400, a0) +lh s4, (#0x7ff, a0) +lh s4, (#0xfffff801, a5) +lh s4, (#0xfffffc00, a5) +lh s4, (#0xfffffe00, a5) +lh s4, (#0xffffff00, a5) +lh s4, (#0xffffff80, a5) +lh s4, (#0xffffffc0, a5) +lh s4, (#0xffffffe0, a5) +lh s4, (#0xfffffff0, a5) +lh s4, (#0xfffffff8, a5) +lh s4, (#0xfffffffc, a5) +lh s4, (#0xfffffffe, a5) +lh s4, (#0xffffffff, a5) +lh s4, (#0, a5) +lh s4, (#1, a5) +lh s4, (#2, a5) +lh s4, (#4, a5) +lh s4, (#8, a5) +lh s4, (#0x10, a5) +lh s4, (#0x20, a5) +lh s4, (#0x40, a5) +lh s4, (#0x80, a5) +lh s4, (#0x100, a5) +lh s4, (#0x200, a5) +lh s4, (#0x400, a5) +lh s4, (#0x7ff, a5) +lh s4, (#0xfffff801, s4) +lh s4, (#0xfffffc00, s4) +lh s4, (#0xfffffe00, s4) +lh s4, (#0xffffff00, s4) +lh s4, (#0xffffff80, s4) +lh s4, (#0xffffffc0, s4) +lh s4, (#0xffffffe0, s4) +lh s4, (#0xfffffff0, s4) +lh s4, (#0xfffffff8, s4) +lh s4, (#0xfffffffc, s4) +lh s4, (#0xfffffffe, s4) +lh s4, (#0xffffffff, s4) +lh s4, (#0, s4) +lh s4, (#1, s4) +lh s4, (#2, s4) +lh s4, (#4, s4) +lh s4, (#8, s4) +lh s4, (#0x10, s4) +lh s4, (#0x20, s4) +lh s4, (#0x40, s4) +lh s4, (#0x80, s4) +lh s4, (#0x100, s4) +lh s4, (#0x200, s4) +lh s4, (#0x400, s4) +lh s4, (#0x7ff, s4) +lh s4, (#0xfffff801, s9) +lh s4, (#0xfffffc00, s9) +lh s4, (#0xfffffe00, s9) +lh s4, (#0xffffff00, s9) +lh s4, (#0xffffff80, s9) +lh s4, (#0xffffffc0, s9) +lh s4, (#0xffffffe0, s9) +lh s4, (#0xfffffff0, s9) +lh s4, (#0xfffffff8, s9) +lh s4, (#0xfffffffc, s9) +lh s4, (#0xfffffffe, s9) +lh s4, (#0xffffffff, s9) +lh s4, (#0, s9) +lh s4, (#1, s9) +lh s4, (#2, s9) +lh s4, (#4, s9) +lh s4, (#8, s9) +lh s4, (#0x10, s9) +lh s4, (#0x20, s9) +lh s4, (#0x40, s9) +lh s4, (#0x80, s9) +lh s4, (#0x100, s9) +lh s4, (#0x200, s9) +lh s4, (#0x400, s9) +lh s4, (#0x7ff, s9) +lh s4, (#0xfffff801, t6) +lh s4, (#0xfffffc00, t6) +lh s4, (#0xfffffe00, t6) +lh s4, (#0xffffff00, t6) +lh s4, (#0xffffff80, t6) +lh s4, (#0xffffffc0, t6) +lh s4, (#0xffffffe0, t6) +lh s4, (#0xfffffff0, t6) +lh s4, (#0xfffffff8, t6) +lh s4, (#0xfffffffc, t6) +lh s4, (#0xfffffffe, t6) +lh s4, (#0xffffffff, t6) +lh s4, (#0, t6) +lh s4, (#1, t6) +lh s4, (#2, t6) +lh s4, (#4, t6) +lh s4, (#8, t6) +lh s4, (#0x10, t6) +lh s4, (#0x20, t6) +lh s4, (#0x40, t6) +lh s4, (#0x80, t6) +lh s4, (#0x100, t6) +lh s4, (#0x200, t6) +lh s4, (#0x400, t6) +lh s4, (#0x7ff, t6) +lh s9, (#0xfffff801, zero) +lh s9, (#0xfffffc00, zero) +lh s9, (#0xfffffe00, zero) +lh s9, (#0xffffff00, zero) +lh s9, (#0xffffff80, zero) +lh s9, (#0xffffffc0, zero) +lh s9, (#0xffffffe0, zero) +lh s9, (#0xfffffff0, zero) +lh s9, (#0xfffffff8, zero) +lh s9, (#0xfffffffc, zero) +lh s9, (#0xfffffffe, zero) +lh s9, (#0xffffffff, zero) +lh s9, (#0, zero) +lh s9, (#1, zero) +lh s9, (#2, zero) +lh s9, (#4, zero) +lh s9, (#8, zero) +lh s9, (#0x10, zero) +lh s9, (#0x20, zero) +lh s9, (#0x40, zero) +lh s9, (#0x80, zero) +lh s9, (#0x100, zero) +lh s9, (#0x200, zero) +lh s9, (#0x400, zero) +lh s9, (#0x7ff, zero) +lh s9, (#0xfffff801, ra) +lh s9, (#0xfffffc00, ra) +lh s9, (#0xfffffe00, ra) +lh s9, (#0xffffff00, ra) +lh s9, (#0xffffff80, ra) +lh s9, (#0xffffffc0, ra) +lh s9, (#0xffffffe0, ra) +lh s9, (#0xfffffff0, ra) +lh s9, (#0xfffffff8, ra) +lh s9, (#0xfffffffc, ra) +lh s9, (#0xfffffffe, ra) +lh s9, (#0xffffffff, ra) +lh s9, (#0, ra) +lh s9, (#1, ra) +lh s9, (#2, ra) +lh s9, (#4, ra) +lh s9, (#8, ra) +lh s9, (#0x10, ra) +lh s9, (#0x20, ra) +lh s9, (#0x40, ra) +lh s9, (#0x80, ra) +lh s9, (#0x100, ra) +lh s9, (#0x200, ra) +lh s9, (#0x400, ra) +lh s9, (#0x7ff, ra) +lh s9, (#0xfffff801, t0) +lh s9, (#0xfffffc00, t0) +lh s9, (#0xfffffe00, t0) +lh s9, (#0xffffff00, t0) +lh s9, (#0xffffff80, t0) +lh s9, (#0xffffffc0, t0) +lh s9, (#0xffffffe0, t0) +lh s9, (#0xfffffff0, t0) +lh s9, (#0xfffffff8, t0) +lh s9, (#0xfffffffc, t0) +lh s9, (#0xfffffffe, t0) +lh s9, (#0xffffffff, t0) +lh s9, (#0, t0) +lh s9, (#1, t0) +lh s9, (#2, t0) +lh s9, (#4, t0) +lh s9, (#8, t0) +lh s9, (#0x10, t0) +lh s9, (#0x20, t0) +lh s9, (#0x40, t0) +lh s9, (#0x80, t0) +lh s9, (#0x100, t0) +lh s9, (#0x200, t0) +lh s9, (#0x400, t0) +lh s9, (#0x7ff, t0) +lh s9, (#0xfffff801, a0) +lh s9, (#0xfffffc00, a0) +lh s9, (#0xfffffe00, a0) +lh s9, (#0xffffff00, a0) +lh s9, (#0xffffff80, a0) +lh s9, (#0xffffffc0, a0) +lh s9, (#0xffffffe0, a0) +lh s9, (#0xfffffff0, a0) +lh s9, (#0xfffffff8, a0) +lh s9, (#0xfffffffc, a0) +lh s9, (#0xfffffffe, a0) +lh s9, (#0xffffffff, a0) +lh s9, (#0, a0) +lh s9, (#1, a0) +lh s9, (#2, a0) +lh s9, (#4, a0) +lh s9, (#8, a0) +lh s9, (#0x10, a0) +lh s9, (#0x20, a0) +lh s9, (#0x40, a0) +lh s9, (#0x80, a0) +lh s9, (#0x100, a0) +lh s9, (#0x200, a0) +lh s9, (#0x400, a0) +lh s9, (#0x7ff, a0) +lh s9, (#0xfffff801, a5) +lh s9, (#0xfffffc00, a5) +lh s9, (#0xfffffe00, a5) +lh s9, (#0xffffff00, a5) +lh s9, (#0xffffff80, a5) +lh s9, (#0xffffffc0, a5) +lh s9, (#0xffffffe0, a5) +lh s9, (#0xfffffff0, a5) +lh s9, (#0xfffffff8, a5) +lh s9, (#0xfffffffc, a5) +lh s9, (#0xfffffffe, a5) +lh s9, (#0xffffffff, a5) +lh s9, (#0, a5) +lh s9, (#1, a5) +lh s9, (#2, a5) +lh s9, (#4, a5) +lh s9, (#8, a5) +lh s9, (#0x10, a5) +lh s9, (#0x20, a5) +lh s9, (#0x40, a5) +lh s9, (#0x80, a5) +lh s9, (#0x100, a5) +lh s9, (#0x200, a5) +lh s9, (#0x400, a5) +lh s9, (#0x7ff, a5) +lh s9, (#0xfffff801, s4) +lh s9, (#0xfffffc00, s4) +lh s9, (#0xfffffe00, s4) +lh s9, (#0xffffff00, s4) +lh s9, (#0xffffff80, s4) +lh s9, (#0xffffffc0, s4) +lh s9, (#0xffffffe0, s4) +lh s9, (#0xfffffff0, s4) +lh s9, (#0xfffffff8, s4) +lh s9, (#0xfffffffc, s4) +lh s9, (#0xfffffffe, s4) +lh s9, (#0xffffffff, s4) +lh s9, (#0, s4) +lh s9, (#1, s4) +lh s9, (#2, s4) +lh s9, (#4, s4) +lh s9, (#8, s4) +lh s9, (#0x10, s4) +lh s9, (#0x20, s4) +lh s9, (#0x40, s4) +lh s9, (#0x80, s4) +lh s9, (#0x100, s4) +lh s9, (#0x200, s4) +lh s9, (#0x400, s4) +lh s9, (#0x7ff, s4) +lh s9, (#0xfffff801, s9) +lh s9, (#0xfffffc00, s9) +lh s9, (#0xfffffe00, s9) +lh s9, (#0xffffff00, s9) +lh s9, (#0xffffff80, s9) +lh s9, (#0xffffffc0, s9) +lh s9, (#0xffffffe0, s9) +lh s9, (#0xfffffff0, s9) +lh s9, (#0xfffffff8, s9) +lh s9, (#0xfffffffc, s9) +lh s9, (#0xfffffffe, s9) +lh s9, (#0xffffffff, s9) +lh s9, (#0, s9) +lh s9, (#1, s9) +lh s9, (#2, s9) +lh s9, (#4, s9) +lh s9, (#8, s9) +lh s9, (#0x10, s9) +lh s9, (#0x20, s9) +lh s9, (#0x40, s9) +lh s9, (#0x80, s9) +lh s9, (#0x100, s9) +lh s9, (#0x200, s9) +lh s9, (#0x400, s9) +lh s9, (#0x7ff, s9) +lh s9, (#0xfffff801, t6) +lh s9, (#0xfffffc00, t6) +lh s9, (#0xfffffe00, t6) +lh s9, (#0xffffff00, t6) +lh s9, (#0xffffff80, t6) +lh s9, (#0xffffffc0, t6) +lh s9, (#0xffffffe0, t6) +lh s9, (#0xfffffff0, t6) +lh s9, (#0xfffffff8, t6) +lh s9, (#0xfffffffc, t6) +lh s9, (#0xfffffffe, t6) +lh s9, (#0xffffffff, t6) +lh s9, (#0, t6) +lh s9, (#1, t6) +lh s9, (#2, t6) +lh s9, (#4, t6) +lh s9, (#8, t6) +lh s9, (#0x10, t6) +lh s9, (#0x20, t6) +lh s9, (#0x40, t6) +lh s9, (#0x80, t6) +lh s9, (#0x100, t6) +lh s9, (#0x200, t6) +lh s9, (#0x400, t6) +lh s9, (#0x7ff, t6) +lh t6, (#0xfffff801, zero) +lh t6, (#0xfffffc00, zero) +lh t6, (#0xfffffe00, zero) +lh t6, (#0xffffff00, zero) +lh t6, (#0xffffff80, zero) +lh t6, (#0xffffffc0, zero) +lh t6, (#0xffffffe0, zero) +lh t6, (#0xfffffff0, zero) +lh t6, (#0xfffffff8, zero) +lh t6, (#0xfffffffc, zero) +lh t6, (#0xfffffffe, zero) +lh t6, (#0xffffffff, zero) +lh t6, (#0, zero) +lh t6, (#1, zero) +lh t6, (#2, zero) +lh t6, (#4, zero) +lh t6, (#8, zero) +lh t6, (#0x10, zero) +lh t6, (#0x20, zero) +lh t6, (#0x40, zero) +lh t6, (#0x80, zero) +lh t6, (#0x100, zero) +lh t6, (#0x200, zero) +lh t6, (#0x400, zero) +lh t6, (#0x7ff, zero) +lh t6, (#0xfffff801, ra) +lh t6, (#0xfffffc00, ra) +lh t6, (#0xfffffe00, ra) +lh t6, (#0xffffff00, ra) +lh t6, (#0xffffff80, ra) +lh t6, (#0xffffffc0, ra) +lh t6, (#0xffffffe0, ra) +lh t6, (#0xfffffff0, ra) +lh t6, (#0xfffffff8, ra) +lh t6, (#0xfffffffc, ra) +lh t6, (#0xfffffffe, ra) +lh t6, (#0xffffffff, ra) +lh t6, (#0, ra) +lh t6, (#1, ra) +lh t6, (#2, ra) +lh t6, (#4, ra) +lh t6, (#8, ra) +lh t6, (#0x10, ra) +lh t6, (#0x20, ra) +lh t6, (#0x40, ra) +lh t6, (#0x80, ra) +lh t6, (#0x100, ra) +lh t6, (#0x200, ra) +lh t6, (#0x400, ra) +lh t6, (#0x7ff, ra) +lh t6, (#0xfffff801, t0) +lh t6, (#0xfffffc00, t0) +lh t6, (#0xfffffe00, t0) +lh t6, (#0xffffff00, t0) +lh t6, (#0xffffff80, t0) +lh t6, (#0xffffffc0, t0) +lh t6, (#0xffffffe0, t0) +lh t6, (#0xfffffff0, t0) +lh t6, (#0xfffffff8, t0) +lh t6, (#0xfffffffc, t0) +lh t6, (#0xfffffffe, t0) +lh t6, (#0xffffffff, t0) +lh t6, (#0, t0) +lh t6, (#1, t0) +lh t6, (#2, t0) +lh t6, (#4, t0) +lh t6, (#8, t0) +lh t6, (#0x10, t0) +lh t6, (#0x20, t0) +lh t6, (#0x40, t0) +lh t6, (#0x80, t0) +lh t6, (#0x100, t0) +lh t6, (#0x200, t0) +lh t6, (#0x400, t0) +lh t6, (#0x7ff, t0) +lh t6, (#0xfffff801, a0) +lh t6, (#0xfffffc00, a0) +lh t6, (#0xfffffe00, a0) +lh t6, (#0xffffff00, a0) +lh t6, (#0xffffff80, a0) +lh t6, (#0xffffffc0, a0) +lh t6, (#0xffffffe0, a0) +lh t6, (#0xfffffff0, a0) +lh t6, (#0xfffffff8, a0) +lh t6, (#0xfffffffc, a0) +lh t6, (#0xfffffffe, a0) +lh t6, (#0xffffffff, a0) +lh t6, (#0, a0) +lh t6, (#1, a0) +lh t6, (#2, a0) +lh t6, (#4, a0) +lh t6, (#8, a0) +lh t6, (#0x10, a0) +lh t6, (#0x20, a0) +lh t6, (#0x40, a0) +lh t6, (#0x80, a0) +lh t6, (#0x100, a0) +lh t6, (#0x200, a0) +lh t6, (#0x400, a0) +lh t6, (#0x7ff, a0) +lh t6, (#0xfffff801, a5) +lh t6, (#0xfffffc00, a5) +lh t6, (#0xfffffe00, a5) +lh t6, (#0xffffff00, a5) +lh t6, (#0xffffff80, a5) +lh t6, (#0xffffffc0, a5) +lh t6, (#0xffffffe0, a5) +lh t6, (#0xfffffff0, a5) +lh t6, (#0xfffffff8, a5) +lh t6, (#0xfffffffc, a5) +lh t6, (#0xfffffffe, a5) +lh t6, (#0xffffffff, a5) +lh t6, (#0, a5) +lh t6, (#1, a5) +lh t6, (#2, a5) +lh t6, (#4, a5) +lh t6, (#8, a5) +lh t6, (#0x10, a5) +lh t6, (#0x20, a5) +lh t6, (#0x40, a5) +lh t6, (#0x80, a5) +lh t6, (#0x100, a5) +lh t6, (#0x200, a5) +lh t6, (#0x400, a5) +lh t6, (#0x7ff, a5) +lh t6, (#0xfffff801, s4) +lh t6, (#0xfffffc00, s4) +lh t6, (#0xfffffe00, s4) +lh t6, (#0xffffff00, s4) +lh t6, (#0xffffff80, s4) +lh t6, (#0xffffffc0, s4) +lh t6, (#0xffffffe0, s4) +lh t6, (#0xfffffff0, s4) +lh t6, (#0xfffffff8, s4) +lh t6, (#0xfffffffc, s4) +lh t6, (#0xfffffffe, s4) +lh t6, (#0xffffffff, s4) +lh t6, (#0, s4) +lh t6, (#1, s4) +lh t6, (#2, s4) +lh t6, (#4, s4) +lh t6, (#8, s4) +lh t6, (#0x10, s4) +lh t6, (#0x20, s4) +lh t6, (#0x40, s4) +lh t6, (#0x80, s4) +lh t6, (#0x100, s4) +lh t6, (#0x200, s4) +lh t6, (#0x400, s4) +lh t6, (#0x7ff, s4) +lh t6, (#0xfffff801, s9) +lh t6, (#0xfffffc00, s9) +lh t6, (#0xfffffe00, s9) +lh t6, (#0xffffff00, s9) +lh t6, (#0xffffff80, s9) +lh t6, (#0xffffffc0, s9) +lh t6, (#0xffffffe0, s9) +lh t6, (#0xfffffff0, s9) +lh t6, (#0xfffffff8, s9) +lh t6, (#0xfffffffc, s9) +lh t6, (#0xfffffffe, s9) +lh t6, (#0xffffffff, s9) +lh t6, (#0, s9) +lh t6, (#1, s9) +lh t6, (#2, s9) +lh t6, (#4, s9) +lh t6, (#8, s9) +lh t6, (#0x10, s9) +lh t6, (#0x20, s9) +lh t6, (#0x40, s9) +lh t6, (#0x80, s9) +lh t6, (#0x100, s9) +lh t6, (#0x200, s9) +lh t6, (#0x400, s9) +lh t6, (#0x7ff, s9) +lh t6, (#0xfffff801, t6) +lh t6, (#0xfffffc00, t6) +lh t6, (#0xfffffe00, t6) +lh t6, (#0xffffff00, t6) +lh t6, (#0xffffff80, t6) +lh t6, (#0xffffffc0, t6) +lh t6, (#0xffffffe0, t6) +lh t6, (#0xfffffff0, t6) +lh t6, (#0xfffffff8, t6) +lh t6, (#0xfffffffc, t6) +lh t6, (#0xfffffffe, t6) +lh t6, (#0xffffffff, t6) +lh t6, (#0, t6) +lh t6, (#1, t6) +lh t6, (#2, t6) +lh t6, (#4, t6) +lh t6, (#8, t6) +lh t6, (#0x10, t6) +lh t6, (#0x20, t6) +lh t6, (#0x40, t6) +lh t6, (#0x80, t6) +lh t6, (#0x100, t6) +lh t6, (#0x200, t6) +lh t6, (#0x400, t6) +lh t6, (#0x7ff, t6) diff --git a/tests/riscv/rv32i/lhu.asm b/tests/riscv/rv32i/lhu.asm new file mode 100644 index 0000000..816ca9f --- /dev/null +++ b/tests/riscv/rv32i/lhu.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +lhu zero, (#-2047, zero) +lhu zero, (#-1024, zero) +lhu zero, (#-512, zero) +lhu zero, (#-256, zero) +lhu zero, (#-128, zero) +lhu zero, (#-64, zero) +lhu zero, (#-32, zero) +lhu zero, (#-16, zero) +lhu zero, (#-8, zero) +lhu zero, (#-4, zero) +lhu zero, (#-2, zero) +lhu zero, (#-1, zero) +lhu zero, (#0, zero) +lhu zero, (#1, zero) +lhu zero, (#2, zero) +lhu zero, (#4, zero) +lhu zero, (#8, zero) +lhu zero, (#16, zero) +lhu zero, (#32, zero) +lhu zero, (#64, zero) +lhu zero, (#128, zero) +lhu zero, (#256, zero) +lhu zero, (#512, zero) +lhu zero, (#1024, zero) +lhu zero, (#2047, zero) +lhu zero, (#-2047, ra) +lhu zero, (#-1024, ra) +lhu zero, (#-512, ra) +lhu zero, (#-256, ra) +lhu zero, (#-128, ra) +lhu zero, (#-64, ra) +lhu zero, (#-32, ra) +lhu zero, (#-16, ra) +lhu zero, (#-8, ra) +lhu zero, (#-4, ra) +lhu zero, (#-2, ra) +lhu zero, (#-1, ra) +lhu zero, (#0, ra) +lhu zero, (#1, ra) +lhu zero, (#2, ra) +lhu zero, (#4, ra) +lhu zero, (#8, ra) +lhu zero, (#16, ra) +lhu zero, (#32, ra) +lhu zero, (#64, ra) +lhu zero, (#128, ra) +lhu zero, (#256, ra) +lhu zero, (#512, ra) +lhu zero, (#1024, ra) +lhu zero, (#2047, ra) +lhu zero, (#-2047, t0) +lhu zero, (#-1024, t0) +lhu zero, (#-512, t0) +lhu zero, (#-256, t0) +lhu zero, (#-128, t0) +lhu zero, (#-64, t0) +lhu zero, (#-32, t0) +lhu zero, (#-16, t0) +lhu zero, (#-8, t0) +lhu zero, (#-4, t0) +lhu zero, (#-2, t0) +lhu zero, (#-1, t0) +lhu zero, (#0, t0) +lhu zero, (#1, t0) +lhu zero, (#2, t0) +lhu zero, (#4, t0) +lhu zero, (#8, t0) +lhu zero, (#16, t0) +lhu zero, (#32, t0) +lhu zero, (#64, t0) +lhu zero, (#128, t0) +lhu zero, (#256, t0) +lhu zero, (#512, t0) +lhu zero, (#1024, t0) +lhu zero, (#2047, t0) +lhu zero, (#-2047, a0) +lhu zero, (#-1024, a0) +lhu zero, (#-512, a0) +lhu zero, (#-256, a0) +lhu zero, (#-128, a0) +lhu zero, (#-64, a0) +lhu zero, (#-32, a0) +lhu zero, (#-16, a0) +lhu zero, (#-8, a0) +lhu zero, (#-4, a0) +lhu zero, (#-2, a0) +lhu zero, (#-1, a0) +lhu zero, (#0, a0) +lhu zero, (#1, a0) +lhu zero, (#2, a0) +lhu zero, (#4, a0) +lhu zero, (#8, a0) +lhu zero, (#16, a0) +lhu zero, (#32, a0) +lhu zero, (#64, a0) +lhu zero, (#128, a0) +lhu zero, (#256, a0) +lhu zero, (#512, a0) +lhu zero, (#1024, a0) +lhu zero, (#2047, a0) +lhu zero, (#-2047, a5) +lhu zero, (#-1024, a5) +lhu zero, (#-512, a5) +lhu zero, (#-256, a5) +lhu zero, (#-128, a5) +lhu zero, (#-64, a5) +lhu zero, (#-32, a5) +lhu zero, (#-16, a5) +lhu zero, (#-8, a5) +lhu zero, (#-4, a5) +lhu zero, (#-2, a5) +lhu zero, (#-1, a5) +lhu zero, (#0, a5) +lhu zero, (#1, a5) +lhu zero, (#2, a5) +lhu zero, (#4, a5) +lhu zero, (#8, a5) +lhu zero, (#16, a5) +lhu zero, (#32, a5) +lhu zero, (#64, a5) +lhu zero, (#128, a5) +lhu zero, (#256, a5) +lhu zero, (#512, a5) +lhu zero, (#1024, a5) +lhu zero, (#2047, a5) +lhu zero, (#-2047, s4) +lhu zero, (#-1024, s4) +lhu zero, (#-512, s4) +lhu zero, (#-256, s4) +lhu zero, (#-128, s4) +lhu zero, (#-64, s4) +lhu zero, (#-32, s4) +lhu zero, (#-16, s4) +lhu zero, (#-8, s4) +lhu zero, (#-4, s4) +lhu zero, (#-2, s4) +lhu zero, (#-1, s4) +lhu zero, (#0, s4) +lhu zero, (#1, s4) +lhu zero, (#2, s4) +lhu zero, (#4, s4) +lhu zero, (#8, s4) +lhu zero, (#16, s4) +lhu zero, (#32, s4) +lhu zero, (#64, s4) +lhu zero, (#128, s4) +lhu zero, (#256, s4) +lhu zero, (#512, s4) +lhu zero, (#1024, s4) +lhu zero, (#2047, s4) +lhu zero, (#-2047, s9) +lhu zero, (#-1024, s9) +lhu zero, (#-512, s9) +lhu zero, (#-256, s9) +lhu zero, (#-128, s9) +lhu zero, (#-64, s9) +lhu zero, (#-32, s9) +lhu zero, (#-16, s9) +lhu zero, (#-8, s9) +lhu zero, (#-4, s9) +lhu zero, (#-2, s9) +lhu zero, (#-1, s9) +lhu zero, (#0, s9) +lhu zero, (#1, s9) +lhu zero, (#2, s9) +lhu zero, (#4, s9) +lhu zero, (#8, s9) +lhu zero, (#16, s9) +lhu zero, (#32, s9) +lhu zero, (#64, s9) +lhu zero, (#128, s9) +lhu zero, (#256, s9) +lhu zero, (#512, s9) +lhu zero, (#1024, s9) +lhu zero, (#2047, s9) +lhu zero, (#-2047, t6) +lhu zero, (#-1024, t6) +lhu zero, (#-512, t6) +lhu zero, (#-256, t6) +lhu zero, (#-128, t6) +lhu zero, (#-64, t6) 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a0, (#-64, s4) +lhu a0, (#-32, s4) +lhu a0, (#-16, s4) +lhu a0, (#-8, s4) +lhu a0, (#-4, s4) +lhu a0, (#-2, s4) +lhu a0, (#-1, s4) +lhu a0, (#0, s4) +lhu a0, (#1, s4) +lhu a0, (#2, s4) +lhu a0, (#4, s4) +lhu a0, (#8, s4) +lhu a0, (#16, s4) +lhu a0, (#32, s4) +lhu a0, (#64, s4) +lhu a0, (#128, s4) +lhu a0, (#256, s4) +lhu a0, (#512, s4) +lhu a0, (#1024, s4) +lhu a0, (#2047, s4) +lhu a0, (#-2047, s9) +lhu a0, (#-1024, s9) +lhu a0, (#-512, s9) +lhu a0, (#-256, s9) +lhu a0, (#-128, s9) +lhu a0, (#-64, s9) +lhu a0, (#-32, s9) +lhu a0, (#-16, s9) +lhu a0, (#-8, s9) +lhu a0, (#-4, s9) +lhu a0, (#-2, s9) +lhu a0, (#-1, s9) +lhu a0, (#0, s9) +lhu a0, (#1, s9) +lhu a0, (#2, s9) +lhu a0, (#4, s9) +lhu a0, (#8, s9) +lhu a0, (#16, s9) +lhu a0, (#32, s9) +lhu a0, (#64, s9) +lhu a0, (#128, s9) +lhu a0, (#256, s9) +lhu a0, (#512, s9) +lhu a0, (#1024, s9) +lhu a0, (#2047, s9) +lhu a0, (#-2047, t6) +lhu a0, (#-1024, t6) +lhu a0, (#-512, t6) +lhu a0, (#-256, t6) +lhu a0, (#-128, t6) +lhu a0, (#-64, t6) +lhu a0, (#-32, t6) +lhu a0, (#-16, t6) +lhu a0, (#-8, t6) +lhu a0, (#-4, t6) +lhu a0, (#-2, t6) +lhu a0, (#-1, t6) +lhu a0, (#0, t6) +lhu a0, (#1, t6) +lhu a0, (#2, t6) +lhu a0, (#4, t6) +lhu a0, (#8, t6) +lhu a0, (#16, t6) +lhu a0, (#32, t6) +lhu a0, (#64, t6) +lhu a0, (#128, t6) +lhu a0, (#256, t6) +lhu a0, (#512, t6) +lhu a0, (#1024, t6) +lhu a0, (#2047, t6) +lhu a5, (#-2047, zero) +lhu a5, (#-1024, zero) +lhu a5, (#-512, zero) +lhu a5, (#-256, zero) +lhu a5, (#-128, zero) +lhu a5, (#-64, zero) +lhu a5, (#-32, zero) +lhu a5, (#-16, zero) +lhu a5, (#-8, zero) +lhu a5, (#-4, zero) +lhu a5, (#-2, zero) +lhu a5, (#-1, zero) +lhu a5, (#0, zero) +lhu a5, (#1, zero) +lhu a5, (#2, zero) +lhu a5, (#4, zero) +lhu a5, (#8, zero) +lhu a5, (#16, zero) +lhu a5, (#32, zero) +lhu a5, (#64, zero) +lhu a5, (#128, zero) +lhu a5, (#256, zero) +lhu a5, (#512, zero) +lhu a5, (#1024, zero) +lhu a5, (#2047, zero) +lhu a5, (#-2047, ra) +lhu a5, (#-1024, ra) +lhu a5, (#-512, ra) +lhu a5, (#-256, ra) +lhu a5, (#-128, ra) +lhu a5, (#-64, ra) +lhu a5, (#-32, ra) +lhu a5, (#-16, ra) +lhu a5, (#-8, ra) +lhu a5, (#-4, ra) +lhu a5, (#-2, ra) +lhu a5, (#-1, ra) +lhu a5, (#0, ra) +lhu a5, (#1, ra) +lhu a5, (#2, ra) +lhu a5, (#4, ra) +lhu a5, (#8, ra) +lhu a5, (#16, ra) +lhu a5, (#32, ra) +lhu a5, (#64, ra) +lhu a5, (#128, ra) +lhu a5, (#256, ra) +lhu a5, (#512, ra) +lhu a5, (#1024, ra) +lhu a5, (#2047, ra) +lhu a5, (#-2047, t0) +lhu a5, (#-1024, t0) +lhu a5, (#-512, t0) +lhu a5, (#-256, t0) +lhu a5, (#-128, t0) +lhu a5, (#-64, t0) +lhu a5, (#-32, t0) +lhu a5, (#-16, t0) +lhu a5, (#-8, t0) +lhu a5, (#-4, t0) +lhu a5, (#-2, t0) +lhu a5, (#-1, t0) +lhu a5, (#0, t0) +lhu a5, (#1, t0) +lhu a5, (#2, t0) +lhu a5, (#4, t0) +lhu a5, (#8, t0) +lhu a5, (#16, t0) +lhu a5, (#32, t0) +lhu a5, (#64, t0) +lhu a5, (#128, t0) +lhu a5, (#256, t0) +lhu a5, (#512, t0) +lhu a5, (#1024, t0) +lhu a5, (#2047, t0) +lhu a5, (#-2047, a0) +lhu a5, (#-1024, a0) +lhu a5, (#-512, a0) +lhu a5, (#-256, a0) +lhu a5, (#-128, a0) +lhu a5, (#-64, a0) +lhu a5, (#-32, a0) +lhu a5, (#-16, a0) +lhu a5, (#-8, a0) +lhu a5, (#-4, a0) +lhu a5, (#-2, a0) +lhu a5, (#-1, a0) +lhu a5, (#0, a0) +lhu a5, (#1, a0) +lhu a5, (#2, a0) +lhu a5, (#4, a0) +lhu a5, (#8, a0) +lhu a5, (#16, a0) +lhu a5, (#32, a0) +lhu a5, (#64, a0) +lhu a5, (#128, a0) +lhu a5, (#256, a0) +lhu a5, (#512, a0) +lhu a5, (#1024, a0) +lhu a5, (#2047, a0) +lhu a5, (#-2047, a5) +lhu a5, (#-1024, a5) +lhu a5, (#-512, a5) +lhu a5, (#-256, a5) +lhu a5, (#-128, a5) +lhu a5, (#-64, a5) +lhu a5, (#-32, a5) +lhu a5, (#-16, a5) +lhu a5, (#-8, a5) +lhu a5, (#-4, a5) +lhu a5, (#-2, a5) +lhu a5, (#-1, a5) +lhu a5, (#0, a5) +lhu a5, (#1, a5) +lhu a5, (#2, a5) +lhu a5, (#4, a5) +lhu a5, (#8, a5) +lhu a5, (#16, a5) +lhu a5, (#32, a5) +lhu a5, (#64, a5) +lhu a5, (#128, a5) +lhu a5, (#256, a5) +lhu a5, (#512, a5) +lhu a5, (#1024, a5) +lhu a5, (#2047, a5) +lhu a5, (#-2047, s4) +lhu a5, (#-1024, s4) +lhu a5, (#-512, s4) +lhu a5, (#-256, s4) +lhu a5, (#-128, s4) +lhu a5, (#-64, s4) +lhu a5, (#-32, s4) +lhu a5, (#-16, s4) +lhu a5, (#-8, s4) +lhu a5, (#-4, s4) +lhu a5, (#-2, s4) +lhu a5, (#-1, s4) +lhu a5, (#0, s4) +lhu a5, (#1, s4) +lhu a5, (#2, s4) +lhu a5, (#4, s4) +lhu a5, (#8, s4) +lhu a5, (#16, s4) +lhu a5, (#32, s4) +lhu a5, (#64, s4) +lhu a5, (#128, s4) +lhu a5, (#256, s4) +lhu a5, (#512, s4) +lhu a5, (#1024, s4) +lhu a5, (#2047, s4) +lhu a5, (#-2047, s9) +lhu a5, (#-1024, s9) +lhu a5, (#-512, s9) +lhu a5, (#-256, s9) +lhu a5, (#-128, s9) +lhu a5, (#-64, s9) +lhu a5, (#-32, s9) +lhu a5, (#-16, s9) +lhu a5, (#-8, s9) +lhu a5, (#-4, s9) +lhu a5, (#-2, s9) +lhu a5, (#-1, s9) +lhu a5, (#0, s9) +lhu a5, (#1, s9) +lhu a5, (#2, s9) +lhu a5, (#4, s9) +lhu a5, (#8, s9) +lhu a5, (#16, s9) +lhu a5, (#32, s9) +lhu a5, (#64, s9) +lhu a5, (#128, s9) +lhu a5, (#256, s9) +lhu a5, (#512, s9) +lhu a5, (#1024, s9) +lhu a5, (#2047, s9) +lhu a5, (#-2047, t6) +lhu a5, (#-1024, t6) +lhu a5, (#-512, t6) +lhu a5, (#-256, t6) +lhu a5, (#-128, t6) +lhu a5, (#-64, t6) +lhu a5, (#-32, t6) +lhu a5, (#-16, t6) +lhu a5, (#-8, t6) +lhu a5, (#-4, t6) +lhu a5, (#-2, t6) +lhu a5, (#-1, t6) +lhu a5, (#0, t6) +lhu a5, (#1, t6) +lhu a5, (#2, t6) +lhu a5, (#4, t6) +lhu a5, (#8, t6) +lhu a5, (#16, t6) +lhu a5, (#32, t6) +lhu a5, (#64, t6) +lhu a5, (#128, t6) +lhu a5, (#256, t6) +lhu a5, (#512, t6) +lhu a5, (#1024, t6) +lhu a5, (#2047, t6) +lhu s4, (#-2047, zero) +lhu s4, (#-1024, zero) +lhu s4, (#-512, zero) +lhu s4, (#-256, zero) +lhu s4, (#-128, zero) +lhu s4, (#-64, zero) +lhu s4, (#-32, zero) +lhu s4, (#-16, zero) +lhu s4, (#-8, zero) +lhu s4, (#-4, zero) +lhu s4, (#-2, zero) +lhu s4, (#-1, zero) +lhu s4, (#0, zero) +lhu s4, (#1, zero) +lhu s4, (#2, zero) +lhu s4, (#4, zero) +lhu s4, (#8, zero) +lhu s4, (#16, zero) +lhu s4, (#32, zero) +lhu s4, (#64, zero) +lhu s4, (#128, zero) +lhu s4, (#256, zero) +lhu s4, (#512, zero) +lhu s4, (#1024, zero) +lhu s4, (#2047, zero) +lhu s4, (#-2047, ra) +lhu s4, (#-1024, ra) +lhu s4, (#-512, ra) +lhu s4, (#-256, ra) +lhu s4, (#-128, ra) +lhu s4, (#-64, ra) +lhu s4, (#-32, ra) +lhu s4, (#-16, ra) +lhu s4, (#-8, ra) +lhu s4, (#-4, ra) +lhu s4, (#-2, ra) +lhu s4, (#-1, ra) +lhu s4, (#0, ra) +lhu s4, (#1, ra) +lhu s4, (#2, ra) +lhu s4, (#4, ra) +lhu s4, (#8, ra) +lhu s4, (#16, ra) +lhu s4, (#32, ra) +lhu s4, (#64, ra) +lhu s4, (#128, ra) +lhu s4, (#256, ra) +lhu s4, (#512, ra) +lhu s4, (#1024, ra) +lhu s4, (#2047, ra) +lhu s4, (#-2047, t0) +lhu s4, (#-1024, t0) +lhu s4, (#-512, t0) +lhu s4, (#-256, t0) +lhu s4, (#-128, t0) +lhu s4, (#-64, t0) +lhu s4, (#-32, t0) +lhu s4, (#-16, t0) +lhu s4, (#-8, t0) +lhu s4, (#-4, t0) +lhu s4, (#-2, t0) +lhu s4, (#-1, t0) +lhu s4, (#0, t0) +lhu s4, (#1, t0) +lhu s4, (#2, t0) +lhu s4, (#4, t0) +lhu s4, (#8, t0) +lhu s4, (#16, t0) +lhu s4, (#32, t0) +lhu s4, (#64, t0) +lhu s4, (#128, t0) +lhu s4, (#256, t0) +lhu s4, (#512, t0) +lhu s4, (#1024, t0) +lhu s4, (#2047, t0) +lhu s4, (#-2047, a0) +lhu s4, (#-1024, a0) +lhu s4, (#-512, a0) +lhu s4, (#-256, a0) +lhu s4, (#-128, a0) +lhu s4, (#-64, a0) +lhu s4, (#-32, a0) +lhu s4, (#-16, a0) +lhu s4, (#-8, a0) +lhu s4, (#-4, a0) +lhu s4, (#-2, a0) +lhu s4, (#-1, a0) +lhu s4, (#0, a0) +lhu s4, (#1, a0) +lhu s4, (#2, a0) +lhu s4, (#4, a0) +lhu s4, (#8, a0) +lhu s4, (#16, a0) +lhu s4, (#32, a0) +lhu s4, (#64, a0) +lhu s4, (#128, a0) +lhu s4, (#256, a0) +lhu s4, (#512, a0) +lhu s4, (#1024, a0) +lhu s4, (#2047, a0) +lhu s4, (#-2047, a5) +lhu s4, (#-1024, a5) +lhu s4, (#-512, a5) +lhu s4, (#-256, a5) +lhu s4, (#-128, a5) +lhu s4, (#-64, a5) +lhu s4, (#-32, a5) +lhu s4, (#-16, a5) +lhu s4, (#-8, a5) +lhu s4, (#-4, a5) +lhu s4, (#-2, a5) +lhu s4, (#-1, a5) +lhu s4, (#0, a5) +lhu s4, (#1, a5) +lhu s4, (#2, a5) +lhu s4, (#4, a5) +lhu s4, (#8, a5) +lhu s4, (#16, a5) +lhu s4, (#32, a5) +lhu s4, (#64, a5) +lhu s4, (#128, a5) +lhu s4, (#256, a5) +lhu s4, (#512, a5) +lhu s4, (#1024, a5) +lhu s4, (#2047, a5) +lhu s4, (#-2047, s4) +lhu s4, (#-1024, s4) +lhu s4, (#-512, s4) +lhu s4, (#-256, s4) +lhu s4, (#-128, s4) +lhu s4, (#-64, s4) +lhu s4, (#-32, s4) +lhu s4, (#-16, s4) +lhu s4, (#-8, s4) +lhu s4, (#-4, s4) +lhu s4, (#-2, s4) +lhu s4, (#-1, s4) +lhu s4, (#0, s4) +lhu s4, (#1, s4) +lhu s4, (#2, s4) +lhu s4, (#4, s4) +lhu s4, (#8, s4) +lhu s4, (#16, s4) +lhu s4, (#32, s4) +lhu s4, (#64, s4) +lhu s4, (#128, s4) +lhu s4, (#256, s4) +lhu s4, (#512, s4) +lhu s4, (#1024, s4) +lhu s4, (#2047, s4) +lhu s4, (#-2047, s9) +lhu s4, (#-1024, s9) +lhu s4, (#-512, s9) +lhu s4, (#-256, s9) +lhu s4, (#-128, s9) +lhu s4, (#-64, s9) +lhu s4, (#-32, s9) +lhu s4, (#-16, s9) +lhu s4, (#-8, s9) +lhu s4, (#-4, s9) +lhu s4, (#-2, s9) +lhu s4, (#-1, s9) +lhu s4, (#0, s9) +lhu s4, (#1, s9) +lhu s4, (#2, s9) +lhu s4, (#4, s9) +lhu s4, (#8, s9) +lhu s4, (#16, s9) +lhu s4, (#32, s9) +lhu s4, (#64, s9) +lhu s4, (#128, s9) +lhu s4, (#256, s9) +lhu s4, (#512, s9) +lhu s4, (#1024, s9) +lhu s4, (#2047, s9) +lhu s4, (#-2047, t6) +lhu s4, (#-1024, t6) +lhu s4, (#-512, t6) +lhu s4, (#-256, t6) +lhu s4, (#-128, t6) +lhu s4, (#-64, t6) +lhu s4, (#-32, t6) +lhu s4, (#-16, t6) +lhu s4, (#-8, t6) +lhu s4, (#-4, t6) +lhu s4, (#-2, t6) +lhu s4, (#-1, t6) +lhu s4, (#0, t6) +lhu s4, (#1, t6) +lhu s4, (#2, t6) +lhu s4, (#4, t6) +lhu s4, (#8, t6) +lhu s4, (#16, t6) +lhu s4, (#32, t6) +lhu s4, (#64, t6) +lhu s4, (#128, t6) +lhu s4, (#256, t6) +lhu s4, (#512, t6) +lhu s4, (#1024, t6) +lhu s4, (#2047, t6) +lhu s9, (#-2047, zero) +lhu s9, (#-1024, zero) +lhu s9, (#-512, zero) +lhu s9, (#-256, zero) +lhu s9, (#-128, zero) +lhu s9, (#-64, zero) +lhu s9, (#-32, zero) +lhu s9, (#-16, zero) +lhu s9, (#-8, zero) +lhu s9, (#-4, zero) +lhu s9, (#-2, zero) +lhu s9, (#-1, zero) +lhu s9, (#0, zero) +lhu s9, (#1, zero) +lhu s9, (#2, zero) +lhu s9, (#4, zero) +lhu s9, (#8, zero) +lhu s9, (#16, zero) +lhu s9, (#32, zero) +lhu s9, (#64, zero) +lhu s9, (#128, zero) +lhu s9, (#256, zero) +lhu s9, (#512, zero) +lhu s9, (#1024, zero) +lhu s9, (#2047, zero) +lhu s9, (#-2047, ra) +lhu s9, (#-1024, ra) +lhu s9, (#-512, ra) +lhu s9, (#-256, ra) +lhu s9, (#-128, ra) +lhu s9, (#-64, ra) +lhu s9, (#-32, ra) +lhu s9, (#-16, ra) +lhu s9, (#-8, ra) +lhu s9, (#-4, ra) +lhu s9, (#-2, ra) +lhu s9, (#-1, ra) +lhu s9, (#0, ra) +lhu s9, (#1, ra) +lhu s9, (#2, ra) +lhu s9, (#4, ra) +lhu s9, (#8, ra) +lhu s9, (#16, ra) +lhu s9, (#32, ra) +lhu s9, (#64, ra) +lhu s9, (#128, ra) +lhu s9, (#256, ra) +lhu s9, (#512, ra) +lhu s9, (#1024, ra) +lhu s9, (#2047, ra) +lhu s9, (#-2047, t0) +lhu s9, (#-1024, t0) +lhu s9, (#-512, t0) +lhu s9, (#-256, t0) +lhu s9, (#-128, t0) +lhu s9, (#-64, t0) +lhu s9, (#-32, t0) +lhu s9, (#-16, t0) +lhu s9, (#-8, t0) +lhu s9, (#-4, t0) +lhu s9, (#-2, t0) +lhu s9, (#-1, t0) +lhu s9, (#0, t0) +lhu s9, (#1, t0) +lhu s9, (#2, t0) +lhu s9, (#4, t0) +lhu s9, (#8, t0) +lhu s9, (#16, t0) +lhu s9, (#32, t0) +lhu s9, (#64, t0) +lhu s9, (#128, t0) +lhu s9, (#256, t0) +lhu s9, (#512, t0) +lhu s9, (#1024, t0) +lhu s9, (#2047, t0) +lhu s9, (#-2047, a0) +lhu s9, (#-1024, a0) +lhu s9, (#-512, a0) +lhu s9, (#-256, a0) +lhu s9, (#-128, a0) +lhu s9, (#-64, a0) +lhu s9, (#-32, a0) +lhu s9, (#-16, a0) +lhu s9, (#-8, a0) +lhu s9, (#-4, a0) +lhu s9, (#-2, a0) +lhu s9, (#-1, a0) +lhu s9, (#0, a0) +lhu s9, (#1, a0) +lhu s9, (#2, a0) +lhu s9, (#4, a0) +lhu s9, (#8, a0) +lhu s9, (#16, a0) +lhu s9, (#32, a0) +lhu s9, (#64, a0) +lhu s9, (#128, a0) +lhu s9, (#256, a0) +lhu s9, (#512, a0) +lhu s9, (#1024, a0) +lhu s9, (#2047, a0) +lhu s9, (#-2047, a5) +lhu s9, (#-1024, a5) +lhu s9, (#-512, a5) +lhu s9, (#-256, a5) +lhu s9, (#-128, a5) +lhu s9, (#-64, a5) +lhu s9, (#-32, a5) +lhu s9, (#-16, a5) +lhu s9, (#-8, a5) +lhu s9, (#-4, a5) +lhu s9, (#-2, a5) +lhu s9, (#-1, a5) +lhu s9, (#0, a5) +lhu s9, (#1, a5) +lhu s9, (#2, a5) +lhu s9, (#4, a5) +lhu s9, (#8, a5) +lhu s9, (#16, a5) +lhu s9, (#32, a5) +lhu s9, (#64, a5) +lhu s9, (#128, a5) +lhu s9, (#256, a5) +lhu s9, (#512, a5) +lhu s9, (#1024, a5) +lhu s9, (#2047, a5) +lhu s9, (#-2047, s4) +lhu s9, (#-1024, s4) +lhu s9, (#-512, s4) +lhu s9, (#-256, s4) +lhu s9, (#-128, s4) +lhu s9, (#-64, s4) +lhu s9, (#-32, s4) +lhu s9, (#-16, s4) +lhu s9, (#-8, s4) +lhu s9, (#-4, s4) +lhu s9, (#-2, s4) +lhu s9, (#-1, s4) +lhu s9, (#0, s4) +lhu s9, (#1, s4) +lhu s9, (#2, s4) +lhu s9, (#4, s4) +lhu s9, (#8, s4) +lhu s9, (#16, s4) +lhu s9, (#32, s4) +lhu s9, (#64, s4) +lhu s9, (#128, s4) +lhu s9, (#256, s4) +lhu s9, (#512, s4) +lhu s9, (#1024, s4) +lhu s9, (#2047, s4) +lhu s9, (#-2047, s9) +lhu s9, (#-1024, s9) +lhu s9, (#-512, s9) +lhu s9, (#-256, s9) +lhu s9, (#-128, s9) +lhu s9, (#-64, s9) +lhu s9, (#-32, s9) +lhu s9, (#-16, s9) +lhu s9, (#-8, s9) +lhu s9, (#-4, s9) +lhu s9, (#-2, s9) +lhu s9, (#-1, s9) +lhu s9, (#0, s9) +lhu s9, (#1, s9) +lhu s9, (#2, s9) +lhu s9, (#4, s9) +lhu s9, (#8, s9) +lhu s9, (#16, s9) +lhu s9, (#32, s9) +lhu s9, (#64, s9) +lhu s9, (#128, s9) +lhu s9, (#256, s9) +lhu s9, (#512, s9) +lhu s9, (#1024, s9) +lhu s9, (#2047, s9) +lhu s9, (#-2047, t6) +lhu s9, (#-1024, t6) +lhu s9, (#-512, t6) +lhu s9, (#-256, t6) +lhu s9, (#-128, t6) +lhu s9, (#-64, t6) +lhu s9, (#-32, t6) +lhu s9, (#-16, t6) +lhu s9, (#-8, t6) +lhu s9, (#-4, t6) +lhu s9, (#-2, t6) +lhu s9, (#-1, t6) +lhu s9, (#0, t6) +lhu s9, (#1, t6) +lhu s9, (#2, t6) +lhu s9, (#4, t6) +lhu s9, (#8, t6) +lhu s9, (#16, t6) +lhu s9, (#32, t6) +lhu s9, (#64, t6) +lhu s9, (#128, t6) +lhu s9, (#256, t6) +lhu s9, (#512, t6) +lhu s9, (#1024, t6) +lhu s9, (#2047, t6) +lhu t6, (#-2047, zero) +lhu t6, (#-1024, zero) +lhu t6, (#-512, zero) +lhu t6, (#-256, zero) +lhu t6, (#-128, zero) +lhu t6, (#-64, zero) +lhu t6, (#-32, zero) +lhu t6, (#-16, zero) +lhu t6, (#-8, zero) +lhu t6, (#-4, zero) +lhu t6, (#-2, zero) +lhu t6, (#-1, zero) +lhu t6, (#0, zero) +lhu t6, (#1, zero) +lhu t6, (#2, zero) +lhu t6, (#4, zero) +lhu t6, (#8, zero) +lhu t6, (#16, zero) +lhu t6, (#32, zero) +lhu t6, (#64, zero) +lhu t6, (#128, zero) +lhu t6, (#256, zero) +lhu t6, (#512, zero) +lhu t6, (#1024, zero) +lhu t6, (#2047, zero) +lhu t6, (#-2047, ra) +lhu t6, (#-1024, ra) +lhu t6, (#-512, ra) +lhu t6, (#-256, ra) +lhu t6, (#-128, ra) +lhu t6, (#-64, ra) +lhu t6, (#-32, ra) +lhu t6, (#-16, ra) +lhu t6, (#-8, ra) +lhu t6, (#-4, ra) +lhu t6, (#-2, ra) +lhu t6, (#-1, ra) +lhu t6, (#0, ra) +lhu t6, (#1, ra) +lhu t6, (#2, ra) +lhu t6, (#4, ra) +lhu t6, (#8, ra) +lhu t6, (#16, ra) +lhu t6, (#32, ra) +lhu t6, (#64, ra) +lhu t6, (#128, ra) +lhu t6, (#256, ra) +lhu t6, (#512, ra) +lhu t6, (#1024, ra) +lhu t6, (#2047, ra) +lhu t6, (#-2047, t0) +lhu t6, (#-1024, t0) +lhu t6, (#-512, t0) +lhu t6, (#-256, t0) +lhu t6, (#-128, t0) +lhu t6, (#-64, t0) +lhu t6, (#-32, t0) +lhu t6, (#-16, t0) +lhu t6, (#-8, t0) +lhu t6, (#-4, t0) +lhu t6, (#-2, t0) +lhu t6, (#-1, t0) +lhu t6, (#0, t0) +lhu t6, (#1, t0) +lhu t6, (#2, t0) +lhu t6, (#4, t0) +lhu t6, (#8, t0) +lhu t6, (#16, t0) +lhu t6, (#32, t0) +lhu t6, (#64, t0) +lhu t6, (#128, t0) +lhu t6, (#256, t0) +lhu t6, (#512, t0) +lhu t6, (#1024, t0) +lhu t6, (#2047, t0) +lhu t6, (#-2047, a0) +lhu t6, (#-1024, a0) +lhu t6, (#-512, a0) +lhu t6, (#-256, a0) +lhu t6, (#-128, a0) +lhu t6, (#-64, a0) +lhu t6, (#-32, a0) +lhu t6, (#-16, a0) +lhu t6, (#-8, a0) +lhu t6, (#-4, a0) +lhu t6, (#-2, a0) +lhu t6, (#-1, a0) +lhu t6, (#0, a0) +lhu t6, (#1, a0) +lhu t6, (#2, a0) +lhu t6, (#4, a0) +lhu t6, (#8, a0) +lhu t6, (#16, a0) +lhu t6, (#32, a0) +lhu t6, (#64, a0) +lhu t6, (#128, a0) +lhu t6, (#256, a0) +lhu t6, (#512, a0) +lhu t6, (#1024, a0) +lhu t6, (#2047, a0) +lhu t6, (#-2047, a5) +lhu t6, (#-1024, a5) +lhu t6, (#-512, a5) +lhu t6, (#-256, a5) +lhu t6, (#-128, a5) +lhu t6, (#-64, a5) +lhu t6, (#-32, a5) +lhu t6, (#-16, a5) +lhu t6, (#-8, a5) +lhu t6, (#-4, a5) +lhu t6, (#-2, a5) +lhu t6, (#-1, a5) +lhu t6, (#0, a5) +lhu t6, (#1, a5) +lhu t6, (#2, a5) +lhu t6, (#4, a5) +lhu t6, (#8, a5) +lhu t6, (#16, a5) +lhu t6, (#32, a5) +lhu t6, (#64, a5) +lhu t6, (#128, a5) +lhu t6, (#256, a5) +lhu t6, (#512, a5) +lhu t6, (#1024, a5) +lhu t6, (#2047, a5) +lhu t6, (#-2047, s4) +lhu t6, (#-1024, s4) +lhu t6, (#-512, s4) +lhu t6, (#-256, s4) +lhu t6, (#-128, s4) +lhu t6, (#-64, s4) +lhu t6, (#-32, s4) +lhu t6, (#-16, s4) +lhu t6, (#-8, s4) +lhu t6, (#-4, s4) +lhu t6, (#-2, s4) +lhu t6, (#-1, s4) +lhu t6, (#0, s4) +lhu t6, (#1, s4) +lhu t6, (#2, s4) +lhu t6, (#4, s4) +lhu t6, (#8, s4) +lhu t6, (#16, s4) +lhu t6, (#32, s4) +lhu t6, (#64, s4) +lhu t6, (#128, s4) +lhu t6, (#256, s4) +lhu t6, (#512, s4) +lhu t6, (#1024, s4) +lhu t6, (#2047, s4) +lhu t6, (#-2047, s9) +lhu t6, (#-1024, s9) +lhu t6, (#-512, s9) +lhu t6, (#-256, s9) +lhu t6, (#-128, s9) +lhu t6, (#-64, s9) +lhu t6, (#-32, s9) +lhu t6, (#-16, s9) +lhu t6, (#-8, s9) +lhu t6, (#-4, s9) +lhu t6, (#-2, s9) +lhu t6, (#-1, s9) +lhu t6, (#0, s9) +lhu t6, (#1, s9) +lhu t6, (#2, s9) +lhu t6, (#4, s9) +lhu t6, (#8, s9) +lhu t6, (#16, s9) +lhu t6, (#32, s9) +lhu t6, (#64, s9) +lhu t6, (#128, s9) +lhu t6, (#256, s9) +lhu t6, (#512, s9) +lhu t6, (#1024, s9) +lhu t6, (#2047, s9) +lhu t6, (#-2047, t6) +lhu t6, (#-1024, t6) +lhu t6, (#-512, t6) +lhu t6, (#-256, t6) +lhu t6, (#-128, t6) +lhu t6, (#-64, t6) +lhu t6, (#-32, t6) +lhu t6, (#-16, t6) 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zy04=9D!Q+t`zpGxqWdbkucG@Zy04=9D!Q+t`zr1mGkAp$_zw3~bYI224EI%ZUq$y- zbYDgOIQh1peA`dWiaY$kJ$~Y0Ir+AqeA`dH?I+*%Q`4Bi0RwK}+kWzGKQ)i=7*BA( zVCJ$U8A(Qxkz^zpNk)>9WF#3$Mv{?aBpFFYl96O28A(Qxkz^zpNk)>9WTami{E_%0 zwJT)sN8*pfABjH_eqVJk@zF=N8*pfA8FT^!ArcyH}FT|kF>J~e^wolE9JN&>s ze&S&>`L<8K?UQf&#J;*W_xCjOYZ!OUfo`6Kg3?pN4@KQe!0{>c21`6Kg3=8w!D zxo^ziIo{$6_#^X2?(M-JnLjdrc21`6Kg3-Zf_M z67TU1{E_)1@9e=JnLjdrWd6wfk@+L@N9K>rADKTge`Nm1{E_)1^GD{7%pZB*n87Q2 zz<2OR=8wFW!5^7FGJjj3T4RC^CwSBBRJCGK!2MqsS;Sii{$o$S5+3j3T4R zC^CwSBBRJCzcTov@JDG^$l#B{AB8^(e-!>G{89L$@JDGIGkA*E_yqna{83sN{89L$ z@JDF}GneJeA7}nJcPl(A{y6i;nLp0_apsRRf1LT_%pd2jF@tA#gU{fPGk=^r&x$|J z{Bh=wb2pf|EQLP`f0TZOJ@}*WN8yjcAB8^(e-!>G{89SG44&gHzJNapf0W)H{89L$ z@JHzfGneJeALs2YR@j3-&irxak28Oq`QywVXZ|?z$9dbB!3(^@SMbM~Kh9fw@W+`y z&irxak28N1{wTX!tgr`v6#gjuQTU_qN8yjcAB8{4t}%m`c#m)3kHQ~iXAk};{89L$ z@JHc~!XJe{3V#&-DEv|Qqwq)JkHQ~?KMH>o{wVv#3|`>_zJossf0Vrp{wVxW_@nSg z(T~}?J9~HMX2l(T;2uBmu*}}w*}FS?cW3YJ+%#rzz8C6D=QDsyaRYsLjWz=68`cd_x zwku@lN7aw2A5}l9epLOa`cd_xwv8D)#cOPOX&+74ze%d8)>e$3qp z&q_aL{h0M*){j{~X8oA;W7dzkYs}yo-rzIzW7dyZKW6=y^<&nLxf{$}mZ~3BKWe|i z9{N%Bqv}W1kE$P4KdOFI{iuCo2G8*pU!WgVKdOFI{iym;^`rKKnaeWk$GpA83VZ0s ztRJ&}%=$6w$E+W-e$4tYZyPgsfp_={{h0M*){j{~X8oA;W7dyZKdOGz-7QwwLqDp1 zRQ;&>QT3zhN7aw2A9dH5!ArcyH|R&zkE$P4KdOFI{iym;^`q)X)sLzlRX?hJRQ;&> sQT3zhN7aw2A5}l9epLOa`cd_x>POX&svlK9s(w`csQOX$qdr{zAF`8u#{d8T literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/lhu.disasm b/tests/riscv/rv32i/lhu.disasm new file mode 100644 index 0000000..8312321 --- /dev/null +++ b/tests/riscv/rv32i/lhu.disasm @@ -0,0 +1,1600 @@ +lhu zero, (#0xfffff801, zero) +lhu zero, (#0xfffffc00, zero) +lhu zero, (#0xfffffe00, zero) +lhu zero, (#0xffffff00, zero) +lhu zero, (#0xffffff80, zero) +lhu zero, (#0xffffffc0, zero) +lhu zero, (#0xffffffe0, zero) +lhu zero, (#0xfffffff0, zero) +lhu zero, (#0xfffffff8, zero) +lhu zero, (#0xfffffffc, zero) +lhu zero, (#0xfffffffe, zero) +lhu zero, (#0xffffffff, zero) +lhu zero, (#0, zero) +lhu zero, (#1, zero) +lhu zero, (#2, zero) +lhu zero, (#4, zero) +lhu zero, (#8, zero) +lhu zero, (#0x10, zero) +lhu zero, (#0x20, zero) +lhu zero, (#0x40, zero) +lhu zero, (#0x80, zero) +lhu zero, (#0x100, zero) +lhu zero, (#0x200, zero) +lhu zero, (#0x400, zero) +lhu zero, (#0x7ff, zero) +lhu zero, (#0xfffff801, ra) +lhu zero, (#0xfffffc00, ra) +lhu zero, (#0xfffffe00, ra) +lhu zero, (#0xffffff00, ra) +lhu zero, (#0xffffff80, ra) +lhu zero, (#0xffffffc0, ra) +lhu zero, (#0xffffffe0, ra) +lhu zero, (#0xfffffff0, ra) +lhu zero, (#0xfffffff8, ra) +lhu zero, (#0xfffffffc, ra) +lhu zero, (#0xfffffffe, ra) +lhu zero, (#0xffffffff, ra) +lhu zero, (#0, ra) +lhu zero, (#1, ra) +lhu zero, (#2, ra) +lhu zero, (#4, ra) +lhu zero, (#8, ra) +lhu zero, (#0x10, ra) +lhu zero, (#0x20, ra) +lhu zero, (#0x40, ra) +lhu zero, (#0x80, ra) +lhu zero, (#0x100, ra) +lhu zero, (#0x200, ra) +lhu zero, (#0x400, ra) +lhu zero, (#0x7ff, ra) +lhu zero, (#0xfffff801, t0) +lhu zero, (#0xfffffc00, t0) +lhu zero, (#0xfffffe00, t0) +lhu zero, (#0xffffff00, t0) +lhu zero, (#0xffffff80, t0) +lhu zero, (#0xffffffc0, t0) +lhu zero, (#0xffffffe0, t0) +lhu zero, (#0xfffffff0, t0) +lhu zero, (#0xfffffff8, t0) +lhu zero, (#0xfffffffc, t0) +lhu zero, (#0xfffffffe, t0) +lhu zero, (#0xffffffff, t0) +lhu zero, (#0, t0) +lhu zero, (#1, t0) +lhu zero, (#2, t0) +lhu zero, (#4, t0) +lhu zero, (#8, t0) +lhu zero, (#0x10, t0) +lhu zero, (#0x20, t0) +lhu zero, (#0x40, t0) +lhu zero, (#0x80, t0) +lhu zero, (#0x100, t0) +lhu zero, (#0x200, t0) +lhu zero, (#0x400, t0) +lhu zero, (#0x7ff, t0) +lhu zero, (#0xfffff801, a0) +lhu zero, (#0xfffffc00, a0) +lhu zero, (#0xfffffe00, a0) +lhu zero, (#0xffffff00, a0) +lhu zero, (#0xffffff80, a0) +lhu zero, (#0xffffffc0, a0) +lhu zero, (#0xffffffe0, a0) +lhu zero, (#0xfffffff0, a0) +lhu zero, (#0xfffffff8, a0) +lhu zero, (#0xfffffffc, a0) +lhu zero, (#0xfffffffe, a0) +lhu zero, (#0xffffffff, a0) +lhu zero, (#0, a0) +lhu zero, (#1, a0) +lhu zero, (#2, a0) +lhu zero, (#4, a0) +lhu zero, (#8, a0) +lhu zero, (#0x10, a0) +lhu zero, (#0x20, a0) +lhu zero, (#0x40, a0) +lhu zero, (#0x80, a0) +lhu zero, (#0x100, a0) +lhu zero, (#0x200, a0) +lhu zero, (#0x400, a0) +lhu zero, (#0x7ff, a0) +lhu zero, (#0xfffff801, a5) +lhu zero, (#0xfffffc00, a5) +lhu zero, (#0xfffffe00, a5) +lhu zero, (#0xffffff00, a5) +lhu zero, (#0xffffff80, a5) +lhu zero, (#0xffffffc0, a5) +lhu zero, (#0xffffffe0, a5) +lhu zero, (#0xfffffff0, a5) +lhu zero, (#0xfffffff8, a5) +lhu zero, (#0xfffffffc, a5) +lhu zero, (#0xfffffffe, a5) +lhu zero, (#0xffffffff, a5) +lhu zero, (#0, a5) +lhu zero, (#1, a5) +lhu zero, (#2, a5) +lhu zero, (#4, a5) +lhu zero, (#8, a5) +lhu zero, (#0x10, a5) +lhu zero, (#0x20, a5) +lhu zero, (#0x40, a5) +lhu zero, (#0x80, a5) +lhu zero, (#0x100, a5) +lhu zero, (#0x200, a5) +lhu zero, (#0x400, a5) +lhu zero, (#0x7ff, a5) +lhu zero, (#0xfffff801, s4) +lhu zero, (#0xfffffc00, s4) +lhu zero, (#0xfffffe00, s4) +lhu zero, (#0xffffff00, s4) +lhu zero, (#0xffffff80, s4) +lhu zero, (#0xffffffc0, s4) +lhu zero, (#0xffffffe0, s4) +lhu zero, (#0xfffffff0, s4) +lhu zero, (#0xfffffff8, s4) +lhu zero, (#0xfffffffc, s4) +lhu zero, (#0xfffffffe, s4) +lhu zero, (#0xffffffff, s4) +lhu zero, (#0, s4) +lhu zero, (#1, s4) +lhu zero, (#2, s4) +lhu zero, (#4, s4) +lhu zero, (#8, s4) +lhu zero, (#0x10, s4) +lhu zero, (#0x20, s4) +lhu zero, (#0x40, s4) +lhu zero, (#0x80, s4) +lhu zero, (#0x100, s4) +lhu zero, (#0x200, s4) +lhu zero, (#0x400, s4) +lhu zero, (#0x7ff, s4) +lhu zero, (#0xfffff801, s9) +lhu zero, (#0xfffffc00, s9) +lhu zero, (#0xfffffe00, s9) +lhu zero, (#0xffffff00, s9) +lhu zero, (#0xffffff80, s9) +lhu zero, (#0xffffffc0, s9) +lhu zero, (#0xffffffe0, s9) +lhu zero, (#0xfffffff0, s9) +lhu zero, (#0xfffffff8, s9) +lhu zero, (#0xfffffffc, s9) +lhu zero, (#0xfffffffe, s9) +lhu zero, (#0xffffffff, s9) +lhu zero, (#0, s9) +lhu zero, (#1, s9) +lhu zero, (#2, s9) +lhu zero, (#4, s9) +lhu zero, (#8, s9) +lhu zero, (#0x10, s9) +lhu zero, (#0x20, s9) +lhu zero, (#0x40, s9) +lhu zero, (#0x80, s9) +lhu zero, (#0x100, s9) +lhu zero, (#0x200, s9) +lhu zero, (#0x400, s9) +lhu zero, (#0x7ff, s9) +lhu zero, (#0xfffff801, t6) +lhu zero, (#0xfffffc00, t6) +lhu zero, (#0xfffffe00, t6) +lhu zero, (#0xffffff00, t6) +lhu zero, (#0xffffff80, t6) +lhu zero, (#0xffffffc0, t6) +lhu zero, (#0xffffffe0, t6) +lhu zero, (#0xfffffff0, t6) +lhu zero, (#0xfffffff8, t6) +lhu zero, (#0xfffffffc, t6) +lhu zero, (#0xfffffffe, t6) +lhu zero, (#0xffffffff, t6) +lhu zero, (#0, t6) +lhu zero, (#1, t6) +lhu zero, (#2, t6) +lhu zero, (#4, t6) +lhu zero, (#8, t6) +lhu zero, (#0x10, t6) +lhu zero, (#0x20, t6) +lhu zero, (#0x40, t6) +lhu zero, (#0x80, t6) +lhu zero, (#0x100, t6) +lhu zero, (#0x200, t6) +lhu zero, (#0x400, t6) +lhu zero, (#0x7ff, t6) +lhu ra, (#0xfffff801, zero) +lhu ra, (#0xfffffc00, zero) +lhu ra, (#0xfffffe00, zero) +lhu ra, (#0xffffff00, zero) +lhu ra, (#0xffffff80, zero) +lhu ra, (#0xffffffc0, zero) +lhu ra, (#0xffffffe0, zero) +lhu ra, (#0xfffffff0, zero) +lhu ra, (#0xfffffff8, zero) +lhu ra, (#0xfffffffc, zero) +lhu ra, (#0xfffffffe, zero) +lhu ra, (#0xffffffff, zero) +lhu ra, (#0, zero) +lhu ra, (#1, zero) +lhu ra, (#2, zero) +lhu ra, (#4, zero) +lhu ra, (#8, zero) +lhu ra, (#0x10, zero) +lhu ra, (#0x20, zero) +lhu ra, (#0x40, zero) +lhu ra, (#0x80, zero) +lhu ra, (#0x100, zero) +lhu ra, (#0x200, zero) +lhu ra, (#0x400, zero) +lhu ra, (#0x7ff, zero) +lhu ra, (#0xfffff801, ra) +lhu ra, (#0xfffffc00, ra) +lhu ra, (#0xfffffe00, ra) +lhu ra, (#0xffffff00, ra) +lhu ra, (#0xffffff80, ra) +lhu ra, (#0xffffffc0, ra) +lhu ra, (#0xffffffe0, ra) +lhu ra, (#0xfffffff0, ra) +lhu ra, (#0xfffffff8, ra) +lhu ra, (#0xfffffffc, ra) +lhu ra, (#0xfffffffe, ra) +lhu ra, (#0xffffffff, ra) +lhu ra, (#0, ra) +lhu ra, (#1, ra) +lhu ra, (#2, ra) +lhu ra, (#4, ra) +lhu ra, (#8, ra) +lhu ra, (#0x10, ra) +lhu ra, (#0x20, ra) +lhu ra, (#0x40, ra) +lhu ra, (#0x80, ra) +lhu ra, (#0x100, ra) +lhu ra, (#0x200, ra) +lhu ra, (#0x400, ra) +lhu ra, (#0x7ff, ra) +lhu ra, (#0xfffff801, t0) +lhu ra, (#0xfffffc00, t0) +lhu ra, (#0xfffffe00, t0) +lhu ra, (#0xffffff00, t0) +lhu ra, (#0xffffff80, t0) +lhu ra, (#0xffffffc0, t0) +lhu ra, (#0xffffffe0, t0) +lhu ra, (#0xfffffff0, t0) +lhu ra, (#0xfffffff8, t0) +lhu ra, (#0xfffffffc, t0) +lhu ra, (#0xfffffffe, t0) +lhu ra, (#0xffffffff, t0) +lhu ra, (#0, t0) +lhu ra, (#1, t0) +lhu ra, (#2, t0) +lhu ra, (#4, t0) +lhu ra, (#8, t0) +lhu ra, (#0x10, t0) +lhu ra, (#0x20, t0) +lhu ra, (#0x40, t0) +lhu ra, (#0x80, t0) +lhu ra, (#0x100, t0) +lhu ra, (#0x200, t0) +lhu ra, (#0x400, t0) +lhu ra, (#0x7ff, t0) +lhu ra, (#0xfffff801, a0) +lhu ra, (#0xfffffc00, a0) +lhu ra, (#0xfffffe00, a0) +lhu ra, (#0xffffff00, a0) +lhu ra, (#0xffffff80, a0) +lhu ra, (#0xffffffc0, a0) +lhu ra, (#0xffffffe0, a0) +lhu ra, (#0xfffffff0, a0) +lhu ra, (#0xfffffff8, a0) +lhu ra, (#0xfffffffc, a0) +lhu ra, (#0xfffffffe, a0) +lhu ra, (#0xffffffff, a0) +lhu ra, (#0, a0) +lhu ra, (#1, a0) +lhu ra, (#2, a0) +lhu ra, (#4, a0) +lhu ra, (#8, a0) +lhu ra, (#0x10, a0) +lhu ra, (#0x20, a0) +lhu ra, (#0x40, a0) +lhu ra, (#0x80, a0) +lhu ra, (#0x100, a0) +lhu ra, (#0x200, a0) +lhu ra, (#0x400, a0) +lhu ra, (#0x7ff, a0) +lhu ra, (#0xfffff801, a5) +lhu ra, (#0xfffffc00, a5) +lhu ra, (#0xfffffe00, a5) +lhu ra, (#0xffffff00, a5) +lhu ra, (#0xffffff80, a5) +lhu ra, (#0xffffffc0, a5) +lhu ra, (#0xffffffe0, a5) +lhu ra, (#0xfffffff0, a5) +lhu ra, (#0xfffffff8, a5) +lhu ra, (#0xfffffffc, a5) +lhu ra, (#0xfffffffe, a5) +lhu ra, (#0xffffffff, a5) +lhu ra, (#0, a5) +lhu ra, (#1, a5) +lhu ra, (#2, a5) +lhu ra, (#4, a5) +lhu ra, (#8, a5) +lhu ra, (#0x10, a5) +lhu ra, (#0x20, a5) +lhu ra, (#0x40, a5) +lhu ra, (#0x80, a5) +lhu ra, (#0x100, a5) +lhu ra, (#0x200, a5) +lhu ra, (#0x400, a5) +lhu ra, (#0x7ff, a5) +lhu ra, (#0xfffff801, s4) +lhu ra, (#0xfffffc00, s4) +lhu ra, (#0xfffffe00, s4) +lhu ra, (#0xffffff00, s4) +lhu ra, (#0xffffff80, s4) +lhu ra, (#0xffffffc0, s4) +lhu ra, (#0xffffffe0, s4) +lhu ra, (#0xfffffff0, s4) +lhu ra, (#0xfffffff8, s4) +lhu ra, (#0xfffffffc, s4) +lhu ra, (#0xfffffffe, s4) +lhu ra, (#0xffffffff, s4) +lhu ra, (#0, s4) +lhu ra, (#1, s4) +lhu ra, (#2, s4) +lhu ra, (#4, s4) +lhu ra, (#8, s4) +lhu ra, (#0x10, s4) +lhu ra, (#0x20, s4) +lhu ra, (#0x40, s4) +lhu ra, (#0x80, s4) +lhu ra, (#0x100, s4) +lhu ra, (#0x200, s4) +lhu ra, (#0x400, s4) +lhu ra, (#0x7ff, s4) +lhu ra, (#0xfffff801, s9) +lhu ra, (#0xfffffc00, s9) +lhu ra, (#0xfffffe00, s9) +lhu ra, (#0xffffff00, s9) +lhu ra, (#0xffffff80, s9) +lhu ra, (#0xffffffc0, s9) +lhu ra, (#0xffffffe0, s9) +lhu ra, (#0xfffffff0, s9) +lhu ra, (#0xfffffff8, s9) +lhu ra, (#0xfffffffc, s9) +lhu ra, (#0xfffffffe, s9) +lhu ra, (#0xffffffff, s9) +lhu ra, (#0, s9) +lhu ra, (#1, s9) +lhu ra, (#2, s9) +lhu ra, (#4, s9) +lhu ra, (#8, s9) +lhu ra, (#0x10, s9) +lhu ra, (#0x20, s9) +lhu ra, (#0x40, s9) +lhu ra, (#0x80, s9) +lhu ra, (#0x100, s9) +lhu ra, (#0x200, s9) +lhu ra, (#0x400, s9) +lhu ra, (#0x7ff, s9) +lhu ra, (#0xfffff801, t6) +lhu ra, (#0xfffffc00, t6) +lhu ra, (#0xfffffe00, t6) +lhu ra, (#0xffffff00, t6) +lhu ra, (#0xffffff80, t6) +lhu ra, (#0xffffffc0, t6) +lhu ra, (#0xffffffe0, t6) +lhu ra, (#0xfffffff0, t6) +lhu ra, (#0xfffffff8, t6) +lhu ra, (#0xfffffffc, t6) +lhu ra, (#0xfffffffe, t6) +lhu ra, (#0xffffffff, t6) +lhu ra, (#0, t6) +lhu ra, (#1, t6) +lhu ra, (#2, t6) +lhu ra, (#4, t6) +lhu ra, (#8, t6) +lhu ra, (#0x10, t6) +lhu ra, (#0x20, t6) +lhu ra, (#0x40, t6) +lhu ra, (#0x80, t6) +lhu ra, (#0x100, t6) +lhu ra, (#0x200, t6) +lhu ra, (#0x400, t6) +lhu ra, (#0x7ff, t6) +lhu t0, (#0xfffff801, zero) +lhu t0, (#0xfffffc00, zero) +lhu t0, (#0xfffffe00, zero) +lhu t0, (#0xffffff00, zero) +lhu t0, (#0xffffff80, zero) +lhu t0, (#0xffffffc0, zero) +lhu t0, (#0xffffffe0, zero) +lhu t0, (#0xfffffff0, zero) +lhu t0, (#0xfffffff8, zero) +lhu t0, (#0xfffffffc, zero) +lhu t0, (#0xfffffffe, zero) +lhu t0, (#0xffffffff, zero) +lhu t0, (#0, zero) +lhu t0, (#1, zero) +lhu t0, (#2, zero) +lhu t0, (#4, zero) +lhu t0, (#8, zero) +lhu t0, (#0x10, zero) +lhu t0, (#0x20, zero) +lhu t0, (#0x40, zero) +lhu t0, (#0x80, zero) +lhu t0, (#0x100, zero) +lhu t0, (#0x200, zero) +lhu t0, (#0x400, zero) +lhu t0, (#0x7ff, zero) +lhu t0, (#0xfffff801, ra) +lhu t0, (#0xfffffc00, ra) +lhu t0, (#0xfffffe00, ra) +lhu t0, (#0xffffff00, ra) +lhu t0, (#0xffffff80, ra) +lhu t0, (#0xffffffc0, ra) +lhu t0, (#0xffffffe0, ra) +lhu t0, (#0xfffffff0, ra) +lhu t0, (#0xfffffff8, ra) +lhu t0, (#0xfffffffc, ra) +lhu t0, (#0xfffffffe, ra) +lhu t0, (#0xffffffff, ra) +lhu t0, (#0, ra) +lhu t0, (#1, ra) +lhu t0, (#2, ra) +lhu t0, (#4, ra) +lhu t0, (#8, ra) +lhu t0, (#0x10, ra) +lhu t0, (#0x20, ra) +lhu t0, (#0x40, ra) +lhu t0, (#0x80, ra) +lhu t0, (#0x100, ra) +lhu t0, (#0x200, ra) +lhu t0, (#0x400, ra) +lhu t0, (#0x7ff, ra) +lhu t0, (#0xfffff801, t0) +lhu t0, (#0xfffffc00, t0) +lhu t0, (#0xfffffe00, t0) +lhu t0, (#0xffffff00, t0) +lhu t0, (#0xffffff80, t0) +lhu t0, (#0xffffffc0, t0) +lhu t0, (#0xffffffe0, t0) +lhu t0, (#0xfffffff0, t0) +lhu t0, (#0xfffffff8, t0) +lhu t0, (#0xfffffffc, t0) +lhu t0, (#0xfffffffe, t0) +lhu t0, (#0xffffffff, t0) +lhu t0, (#0, t0) +lhu t0, (#1, t0) +lhu t0, (#2, t0) +lhu t0, (#4, t0) +lhu t0, (#8, t0) +lhu t0, (#0x10, t0) +lhu t0, (#0x20, t0) +lhu t0, (#0x40, t0) +lhu t0, (#0x80, t0) +lhu t0, (#0x100, t0) +lhu t0, (#0x200, t0) +lhu t0, (#0x400, t0) +lhu t0, (#0x7ff, t0) +lhu t0, (#0xfffff801, a0) +lhu t0, (#0xfffffc00, a0) +lhu t0, (#0xfffffe00, a0) +lhu t0, (#0xffffff00, a0) +lhu t0, (#0xffffff80, a0) +lhu t0, (#0xffffffc0, a0) +lhu t0, (#0xffffffe0, a0) +lhu t0, (#0xfffffff0, a0) +lhu t0, (#0xfffffff8, a0) +lhu t0, (#0xfffffffc, a0) +lhu t0, (#0xfffffffe, a0) +lhu t0, (#0xffffffff, a0) +lhu t0, (#0, a0) +lhu t0, (#1, a0) +lhu t0, (#2, a0) +lhu t0, (#4, a0) +lhu t0, (#8, a0) +lhu t0, (#0x10, a0) +lhu t0, (#0x20, a0) +lhu t0, (#0x40, a0) +lhu t0, (#0x80, a0) +lhu t0, (#0x100, a0) +lhu t0, (#0x200, a0) +lhu t0, (#0x400, a0) +lhu t0, (#0x7ff, a0) +lhu t0, (#0xfffff801, a5) +lhu t0, (#0xfffffc00, a5) +lhu t0, (#0xfffffe00, a5) +lhu t0, (#0xffffff00, a5) +lhu t0, (#0xffffff80, a5) +lhu t0, (#0xffffffc0, a5) +lhu t0, (#0xffffffe0, a5) +lhu t0, (#0xfffffff0, a5) +lhu t0, (#0xfffffff8, a5) +lhu t0, (#0xfffffffc, a5) +lhu t0, (#0xfffffffe, a5) +lhu t0, (#0xffffffff, a5) +lhu t0, (#0, a5) +lhu t0, (#1, a5) +lhu t0, (#2, a5) +lhu t0, (#4, a5) +lhu t0, (#8, a5) +lhu t0, (#0x10, a5) +lhu t0, (#0x20, a5) +lhu t0, (#0x40, a5) +lhu t0, (#0x80, a5) +lhu t0, (#0x100, a5) +lhu t0, (#0x200, a5) +lhu t0, (#0x400, a5) +lhu t0, (#0x7ff, a5) +lhu t0, (#0xfffff801, s4) +lhu t0, (#0xfffffc00, s4) +lhu t0, (#0xfffffe00, s4) +lhu t0, (#0xffffff00, s4) +lhu t0, (#0xffffff80, s4) +lhu t0, (#0xffffffc0, s4) +lhu t0, (#0xffffffe0, s4) +lhu t0, (#0xfffffff0, s4) +lhu t0, (#0xfffffff8, s4) +lhu t0, (#0xfffffffc, s4) +lhu t0, (#0xfffffffe, s4) +lhu t0, (#0xffffffff, s4) +lhu t0, (#0, s4) +lhu t0, (#1, s4) +lhu t0, (#2, s4) +lhu t0, (#4, s4) +lhu t0, (#8, s4) +lhu t0, (#0x10, s4) +lhu t0, (#0x20, s4) +lhu t0, (#0x40, s4) +lhu t0, (#0x80, s4) +lhu t0, (#0x100, s4) +lhu t0, (#0x200, s4) +lhu t0, (#0x400, s4) +lhu t0, (#0x7ff, s4) +lhu t0, (#0xfffff801, s9) +lhu t0, (#0xfffffc00, s9) +lhu t0, (#0xfffffe00, s9) +lhu t0, (#0xffffff00, s9) +lhu t0, (#0xffffff80, s9) +lhu t0, (#0xffffffc0, s9) +lhu t0, (#0xffffffe0, s9) +lhu t0, (#0xfffffff0, s9) +lhu t0, (#0xfffffff8, s9) +lhu t0, (#0xfffffffc, s9) +lhu t0, (#0xfffffffe, s9) +lhu t0, (#0xffffffff, s9) +lhu t0, (#0, s9) +lhu t0, (#1, s9) +lhu t0, (#2, s9) +lhu t0, (#4, s9) +lhu t0, (#8, s9) +lhu t0, (#0x10, s9) +lhu t0, (#0x20, s9) +lhu t0, (#0x40, s9) +lhu t0, (#0x80, s9) +lhu t0, (#0x100, s9) +lhu t0, (#0x200, s9) +lhu t0, (#0x400, s9) +lhu t0, (#0x7ff, s9) +lhu t0, (#0xfffff801, t6) +lhu t0, (#0xfffffc00, t6) +lhu t0, (#0xfffffe00, t6) +lhu t0, (#0xffffff00, t6) +lhu t0, (#0xffffff80, t6) +lhu t0, (#0xffffffc0, t6) +lhu t0, (#0xffffffe0, t6) +lhu t0, (#0xfffffff0, t6) +lhu t0, (#0xfffffff8, t6) +lhu t0, (#0xfffffffc, t6) +lhu t0, (#0xfffffffe, t6) +lhu t0, (#0xffffffff, t6) +lhu t0, (#0, t6) +lhu t0, (#1, t6) +lhu t0, (#2, t6) +lhu t0, (#4, t6) +lhu t0, (#8, t6) +lhu t0, (#0x10, t6) +lhu t0, (#0x20, t6) +lhu t0, (#0x40, t6) +lhu t0, (#0x80, t6) +lhu t0, (#0x100, t6) +lhu t0, (#0x200, t6) +lhu t0, (#0x400, t6) +lhu t0, (#0x7ff, t6) +lhu a0, (#0xfffff801, zero) +lhu a0, (#0xfffffc00, zero) +lhu a0, (#0xfffffe00, zero) +lhu a0, (#0xffffff00, zero) +lhu a0, (#0xffffff80, zero) +lhu a0, (#0xffffffc0, zero) +lhu a0, (#0xffffffe0, zero) +lhu a0, (#0xfffffff0, zero) +lhu a0, (#0xfffffff8, zero) +lhu a0, (#0xfffffffc, zero) +lhu a0, (#0xfffffffe, zero) +lhu a0, (#0xffffffff, zero) +lhu a0, (#0, zero) +lhu a0, (#1, zero) +lhu a0, (#2, zero) +lhu a0, (#4, zero) +lhu a0, (#8, zero) +lhu a0, (#0x10, zero) +lhu a0, (#0x20, zero) +lhu a0, (#0x40, zero) +lhu a0, (#0x80, zero) +lhu a0, (#0x100, zero) +lhu a0, (#0x200, zero) +lhu a0, (#0x400, zero) +lhu a0, (#0x7ff, zero) +lhu a0, (#0xfffff801, ra) +lhu a0, (#0xfffffc00, ra) +lhu a0, (#0xfffffe00, ra) +lhu a0, (#0xffffff00, ra) +lhu a0, (#0xffffff80, ra) +lhu a0, (#0xffffffc0, ra) +lhu a0, (#0xffffffe0, ra) +lhu a0, (#0xfffffff0, ra) +lhu a0, (#0xfffffff8, ra) +lhu a0, (#0xfffffffc, ra) +lhu a0, (#0xfffffffe, ra) +lhu a0, (#0xffffffff, ra) +lhu a0, (#0, ra) +lhu a0, (#1, ra) +lhu a0, (#2, ra) +lhu a0, (#4, ra) +lhu a0, (#8, ra) +lhu a0, (#0x10, ra) +lhu a0, (#0x20, ra) +lhu a0, (#0x40, ra) +lhu a0, (#0x80, ra) +lhu a0, (#0x100, ra) +lhu a0, (#0x200, ra) +lhu a0, (#0x400, ra) +lhu a0, (#0x7ff, ra) +lhu a0, (#0xfffff801, t0) +lhu a0, (#0xfffffc00, t0) +lhu a0, (#0xfffffe00, t0) +lhu a0, (#0xffffff00, t0) +lhu a0, (#0xffffff80, t0) +lhu a0, (#0xffffffc0, t0) +lhu a0, (#0xffffffe0, t0) +lhu a0, (#0xfffffff0, t0) +lhu a0, (#0xfffffff8, t0) +lhu a0, (#0xfffffffc, t0) +lhu a0, (#0xfffffffe, t0) +lhu a0, (#0xffffffff, t0) +lhu a0, (#0, t0) +lhu a0, (#1, t0) +lhu a0, (#2, t0) +lhu a0, (#4, t0) +lhu a0, (#8, t0) +lhu a0, (#0x10, t0) +lhu a0, (#0x20, t0) +lhu a0, (#0x40, t0) +lhu a0, (#0x80, t0) +lhu a0, (#0x100, t0) +lhu a0, (#0x200, t0) +lhu a0, (#0x400, t0) +lhu a0, (#0x7ff, t0) +lhu a0, (#0xfffff801, a0) +lhu a0, (#0xfffffc00, a0) +lhu a0, (#0xfffffe00, a0) +lhu a0, (#0xffffff00, a0) +lhu a0, (#0xffffff80, a0) +lhu a0, (#0xffffffc0, a0) +lhu a0, (#0xffffffe0, a0) +lhu a0, (#0xfffffff0, a0) +lhu a0, (#0xfffffff8, a0) +lhu a0, (#0xfffffffc, a0) +lhu a0, (#0xfffffffe, a0) +lhu a0, (#0xffffffff, a0) +lhu a0, (#0, a0) +lhu a0, (#1, a0) +lhu a0, (#2, a0) +lhu a0, (#4, a0) +lhu a0, (#8, a0) +lhu a0, (#0x10, a0) +lhu a0, (#0x20, a0) +lhu a0, (#0x40, a0) +lhu a0, (#0x80, a0) +lhu a0, (#0x100, a0) +lhu a0, (#0x200, a0) +lhu a0, (#0x400, a0) +lhu a0, (#0x7ff, a0) +lhu a0, (#0xfffff801, a5) +lhu a0, (#0xfffffc00, a5) +lhu a0, (#0xfffffe00, a5) +lhu a0, (#0xffffff00, a5) +lhu a0, (#0xffffff80, a5) +lhu a0, (#0xffffffc0, a5) +lhu a0, (#0xffffffe0, a5) +lhu a0, (#0xfffffff0, a5) +lhu a0, (#0xfffffff8, a5) +lhu a0, (#0xfffffffc, a5) +lhu a0, (#0xfffffffe, a5) +lhu a0, (#0xffffffff, a5) +lhu a0, (#0, a5) +lhu a0, (#1, a5) +lhu a0, (#2, a5) +lhu a0, (#4, a5) +lhu a0, (#8, a5) +lhu a0, (#0x10, a5) +lhu a0, (#0x20, a5) +lhu a0, (#0x40, a5) +lhu a0, (#0x80, a5) +lhu a0, (#0x100, a5) +lhu a0, (#0x200, a5) +lhu a0, (#0x400, a5) +lhu a0, (#0x7ff, a5) +lhu a0, (#0xfffff801, s4) +lhu a0, (#0xfffffc00, s4) +lhu a0, (#0xfffffe00, s4) +lhu a0, (#0xffffff00, s4) +lhu a0, (#0xffffff80, s4) +lhu a0, (#0xffffffc0, s4) +lhu a0, (#0xffffffe0, s4) +lhu a0, (#0xfffffff0, s4) +lhu a0, (#0xfffffff8, s4) +lhu a0, (#0xfffffffc, s4) +lhu a0, (#0xfffffffe, s4) +lhu a0, (#0xffffffff, s4) +lhu a0, (#0, s4) +lhu a0, (#1, s4) +lhu a0, (#2, s4) +lhu a0, (#4, s4) +lhu a0, (#8, s4) +lhu a0, (#0x10, s4) +lhu a0, (#0x20, s4) +lhu a0, (#0x40, s4) +lhu a0, (#0x80, s4) +lhu a0, (#0x100, s4) +lhu a0, (#0x200, s4) +lhu a0, (#0x400, s4) +lhu a0, (#0x7ff, s4) +lhu a0, (#0xfffff801, s9) +lhu a0, (#0xfffffc00, s9) +lhu a0, (#0xfffffe00, s9) +lhu a0, (#0xffffff00, s9) +lhu a0, (#0xffffff80, s9) +lhu a0, (#0xffffffc0, s9) +lhu a0, (#0xffffffe0, s9) +lhu a0, (#0xfffffff0, s9) +lhu a0, (#0xfffffff8, s9) +lhu a0, (#0xfffffffc, s9) +lhu a0, (#0xfffffffe, s9) +lhu a0, (#0xffffffff, s9) +lhu a0, (#0, s9) +lhu a0, (#1, s9) +lhu a0, (#2, s9) +lhu a0, (#4, s9) +lhu a0, (#8, s9) +lhu a0, (#0x10, s9) +lhu a0, (#0x20, s9) +lhu a0, (#0x40, s9) +lhu a0, (#0x80, s9) +lhu a0, (#0x100, s9) +lhu a0, (#0x200, s9) +lhu a0, (#0x400, s9) +lhu a0, (#0x7ff, s9) +lhu a0, (#0xfffff801, t6) +lhu a0, (#0xfffffc00, t6) +lhu a0, (#0xfffffe00, t6) +lhu a0, (#0xffffff00, t6) +lhu a0, (#0xffffff80, t6) +lhu a0, (#0xffffffc0, t6) +lhu a0, (#0xffffffe0, t6) +lhu a0, (#0xfffffff0, t6) +lhu a0, (#0xfffffff8, t6) +lhu a0, (#0xfffffffc, t6) +lhu a0, (#0xfffffffe, t6) +lhu a0, (#0xffffffff, t6) +lhu a0, (#0, t6) +lhu a0, (#1, t6) +lhu a0, (#2, t6) +lhu a0, (#4, t6) +lhu a0, (#8, t6) +lhu a0, (#0x10, t6) +lhu a0, (#0x20, t6) +lhu a0, (#0x40, t6) +lhu a0, (#0x80, t6) +lhu a0, (#0x100, t6) +lhu a0, (#0x200, t6) +lhu a0, (#0x400, t6) +lhu a0, (#0x7ff, t6) +lhu a5, (#0xfffff801, zero) +lhu a5, (#0xfffffc00, zero) +lhu a5, (#0xfffffe00, zero) +lhu a5, (#0xffffff00, zero) +lhu a5, (#0xffffff80, zero) +lhu a5, (#0xffffffc0, zero) +lhu a5, (#0xffffffe0, zero) +lhu a5, (#0xfffffff0, zero) +lhu a5, (#0xfffffff8, zero) +lhu a5, (#0xfffffffc, zero) +lhu a5, (#0xfffffffe, zero) +lhu a5, (#0xffffffff, zero) +lhu a5, (#0, zero) +lhu a5, (#1, zero) +lhu a5, (#2, zero) +lhu a5, (#4, zero) +lhu a5, (#8, zero) +lhu a5, (#0x10, zero) +lhu a5, (#0x20, zero) +lhu a5, (#0x40, zero) +lhu a5, (#0x80, zero) +lhu a5, (#0x100, zero) +lhu a5, (#0x200, zero) +lhu a5, (#0x400, zero) +lhu a5, (#0x7ff, zero) +lhu a5, (#0xfffff801, ra) +lhu a5, (#0xfffffc00, ra) +lhu a5, (#0xfffffe00, ra) +lhu a5, (#0xffffff00, ra) +lhu a5, (#0xffffff80, ra) +lhu a5, (#0xffffffc0, ra) +lhu a5, (#0xffffffe0, ra) +lhu a5, (#0xfffffff0, ra) +lhu a5, (#0xfffffff8, ra) +lhu a5, (#0xfffffffc, ra) +lhu a5, (#0xfffffffe, ra) +lhu a5, (#0xffffffff, ra) +lhu a5, (#0, ra) +lhu a5, (#1, ra) +lhu a5, (#2, ra) +lhu a5, (#4, ra) +lhu a5, (#8, ra) +lhu a5, (#0x10, ra) +lhu a5, (#0x20, ra) +lhu a5, (#0x40, ra) +lhu a5, (#0x80, ra) +lhu a5, (#0x100, ra) +lhu a5, (#0x200, ra) +lhu a5, (#0x400, ra) +lhu a5, (#0x7ff, ra) +lhu a5, (#0xfffff801, t0) +lhu a5, (#0xfffffc00, t0) +lhu a5, (#0xfffffe00, t0) +lhu a5, (#0xffffff00, t0) +lhu a5, (#0xffffff80, t0) +lhu a5, (#0xffffffc0, t0) +lhu a5, (#0xffffffe0, t0) +lhu a5, (#0xfffffff0, t0) +lhu a5, (#0xfffffff8, t0) +lhu a5, (#0xfffffffc, t0) +lhu a5, (#0xfffffffe, t0) +lhu a5, (#0xffffffff, t0) +lhu a5, (#0, t0) +lhu a5, (#1, t0) +lhu a5, (#2, t0) +lhu a5, (#4, t0) +lhu a5, (#8, t0) +lhu a5, (#0x10, t0) +lhu a5, (#0x20, t0) +lhu a5, (#0x40, t0) +lhu a5, (#0x80, t0) +lhu a5, (#0x100, t0) +lhu a5, (#0x200, t0) +lhu a5, (#0x400, t0) +lhu a5, (#0x7ff, t0) +lhu a5, (#0xfffff801, a0) +lhu a5, (#0xfffffc00, a0) +lhu a5, (#0xfffffe00, a0) +lhu a5, (#0xffffff00, a0) +lhu a5, (#0xffffff80, a0) +lhu a5, (#0xffffffc0, a0) +lhu a5, (#0xffffffe0, a0) +lhu a5, (#0xfffffff0, a0) +lhu a5, (#0xfffffff8, a0) +lhu a5, (#0xfffffffc, a0) +lhu a5, (#0xfffffffe, a0) +lhu a5, (#0xffffffff, a0) +lhu a5, (#0, a0) +lhu a5, (#1, a0) +lhu a5, (#2, a0) +lhu a5, (#4, a0) +lhu a5, (#8, a0) +lhu a5, (#0x10, a0) +lhu a5, (#0x20, a0) +lhu a5, (#0x40, a0) +lhu a5, (#0x80, a0) +lhu a5, (#0x100, a0) +lhu a5, (#0x200, a0) +lhu a5, (#0x400, a0) +lhu a5, (#0x7ff, a0) +lhu a5, (#0xfffff801, a5) +lhu a5, (#0xfffffc00, a5) +lhu a5, (#0xfffffe00, a5) +lhu a5, (#0xffffff00, a5) +lhu a5, (#0xffffff80, a5) +lhu a5, (#0xffffffc0, a5) +lhu a5, (#0xffffffe0, a5) +lhu a5, (#0xfffffff0, a5) +lhu a5, (#0xfffffff8, a5) +lhu a5, (#0xfffffffc, a5) +lhu a5, (#0xfffffffe, a5) +lhu a5, (#0xffffffff, a5) +lhu a5, (#0, a5) +lhu a5, (#1, a5) +lhu a5, (#2, a5) +lhu a5, (#4, a5) +lhu a5, (#8, a5) +lhu a5, (#0x10, a5) +lhu a5, (#0x20, a5) +lhu a5, (#0x40, a5) +lhu a5, (#0x80, a5) +lhu a5, (#0x100, a5) +lhu a5, (#0x200, a5) +lhu a5, (#0x400, a5) +lhu a5, (#0x7ff, a5) +lhu a5, (#0xfffff801, s4) +lhu a5, (#0xfffffc00, s4) +lhu a5, (#0xfffffe00, s4) +lhu a5, (#0xffffff00, s4) +lhu a5, (#0xffffff80, s4) +lhu a5, (#0xffffffc0, s4) +lhu a5, (#0xffffffe0, s4) +lhu a5, (#0xfffffff0, s4) +lhu a5, (#0xfffffff8, s4) +lhu a5, (#0xfffffffc, s4) +lhu a5, (#0xfffffffe, s4) +lhu a5, (#0xffffffff, s4) +lhu a5, (#0, s4) +lhu a5, (#1, s4) +lhu a5, (#2, s4) +lhu a5, (#4, s4) +lhu a5, (#8, s4) +lhu a5, (#0x10, s4) +lhu a5, (#0x20, s4) +lhu a5, (#0x40, s4) +lhu a5, (#0x80, s4) +lhu a5, (#0x100, s4) +lhu a5, (#0x200, s4) +lhu a5, (#0x400, s4) +lhu a5, (#0x7ff, s4) +lhu a5, (#0xfffff801, s9) +lhu a5, (#0xfffffc00, s9) +lhu a5, (#0xfffffe00, s9) +lhu a5, (#0xffffff00, s9) +lhu a5, (#0xffffff80, s9) +lhu a5, (#0xffffffc0, s9) +lhu a5, (#0xffffffe0, s9) +lhu a5, (#0xfffffff0, s9) +lhu a5, (#0xfffffff8, s9) +lhu a5, (#0xfffffffc, s9) +lhu a5, (#0xfffffffe, s9) +lhu a5, (#0xffffffff, s9) +lhu a5, (#0, s9) +lhu a5, (#1, s9) +lhu a5, (#2, s9) +lhu a5, (#4, s9) +lhu a5, (#8, s9) +lhu a5, (#0x10, s9) +lhu a5, (#0x20, s9) +lhu a5, (#0x40, s9) +lhu a5, (#0x80, s9) +lhu a5, (#0x100, s9) +lhu a5, (#0x200, s9) +lhu a5, (#0x400, s9) +lhu a5, (#0x7ff, s9) +lhu a5, (#0xfffff801, t6) +lhu a5, (#0xfffffc00, t6) +lhu a5, (#0xfffffe00, t6) +lhu a5, (#0xffffff00, t6) +lhu a5, (#0xffffff80, t6) +lhu a5, (#0xffffffc0, t6) +lhu a5, (#0xffffffe0, t6) +lhu a5, (#0xfffffff0, t6) +lhu a5, (#0xfffffff8, t6) +lhu a5, (#0xfffffffc, t6) +lhu a5, (#0xfffffffe, t6) +lhu a5, (#0xffffffff, t6) +lhu a5, (#0, t6) +lhu a5, (#1, t6) +lhu a5, (#2, t6) +lhu a5, (#4, t6) +lhu a5, (#8, t6) +lhu a5, (#0x10, t6) +lhu a5, (#0x20, t6) +lhu a5, (#0x40, t6) +lhu a5, (#0x80, t6) +lhu a5, (#0x100, t6) +lhu a5, (#0x200, t6) +lhu a5, (#0x400, t6) +lhu a5, (#0x7ff, t6) +lhu s4, (#0xfffff801, zero) +lhu s4, (#0xfffffc00, zero) +lhu s4, (#0xfffffe00, zero) +lhu s4, (#0xffffff00, zero) +lhu s4, (#0xffffff80, zero) +lhu s4, (#0xffffffc0, zero) +lhu s4, (#0xffffffe0, zero) +lhu s4, (#0xfffffff0, zero) +lhu s4, (#0xfffffff8, zero) +lhu s4, (#0xfffffffc, zero) +lhu s4, (#0xfffffffe, zero) +lhu s4, (#0xffffffff, zero) +lhu s4, (#0, zero) +lhu s4, (#1, zero) +lhu s4, (#2, zero) +lhu s4, (#4, zero) +lhu s4, (#8, zero) +lhu s4, (#0x10, zero) +lhu s4, (#0x20, zero) +lhu s4, (#0x40, zero) +lhu s4, (#0x80, zero) +lhu s4, (#0x100, zero) +lhu s4, (#0x200, zero) +lhu s4, (#0x400, zero) +lhu s4, (#0x7ff, zero) +lhu s4, (#0xfffff801, ra) +lhu s4, (#0xfffffc00, ra) +lhu s4, (#0xfffffe00, ra) +lhu s4, (#0xffffff00, ra) +lhu s4, (#0xffffff80, ra) +lhu s4, (#0xffffffc0, ra) +lhu s4, (#0xffffffe0, ra) +lhu s4, (#0xfffffff0, ra) +lhu s4, (#0xfffffff8, ra) +lhu s4, (#0xfffffffc, ra) +lhu s4, (#0xfffffffe, ra) +lhu s4, (#0xffffffff, ra) +lhu s4, (#0, ra) +lhu s4, (#1, ra) +lhu s4, (#2, ra) +lhu s4, (#4, ra) +lhu s4, (#8, ra) +lhu s4, (#0x10, ra) +lhu s4, (#0x20, ra) +lhu s4, (#0x40, ra) +lhu s4, (#0x80, ra) +lhu s4, (#0x100, ra) +lhu s4, (#0x200, ra) +lhu s4, (#0x400, ra) +lhu s4, (#0x7ff, ra) +lhu s4, (#0xfffff801, t0) +lhu s4, (#0xfffffc00, t0) +lhu s4, (#0xfffffe00, t0) +lhu s4, (#0xffffff00, t0) +lhu s4, (#0xffffff80, t0) +lhu s4, (#0xffffffc0, t0) +lhu s4, (#0xffffffe0, t0) +lhu s4, (#0xfffffff0, t0) +lhu s4, (#0xfffffff8, t0) +lhu s4, (#0xfffffffc, t0) +lhu s4, (#0xfffffffe, t0) +lhu s4, (#0xffffffff, t0) +lhu s4, (#0, t0) +lhu s4, (#1, t0) +lhu s4, (#2, t0) +lhu s4, (#4, t0) +lhu s4, (#8, t0) +lhu s4, (#0x10, t0) +lhu s4, (#0x20, t0) +lhu s4, (#0x40, t0) +lhu s4, (#0x80, t0) +lhu s4, (#0x100, t0) +lhu s4, (#0x200, t0) +lhu s4, (#0x400, t0) +lhu s4, (#0x7ff, t0) +lhu s4, (#0xfffff801, a0) +lhu s4, (#0xfffffc00, a0) +lhu s4, (#0xfffffe00, a0) +lhu s4, (#0xffffff00, a0) +lhu s4, (#0xffffff80, a0) +lhu s4, (#0xffffffc0, a0) +lhu s4, (#0xffffffe0, a0) +lhu s4, (#0xfffffff0, a0) +lhu s4, (#0xfffffff8, a0) +lhu s4, (#0xfffffffc, a0) +lhu s4, (#0xfffffffe, a0) +lhu s4, (#0xffffffff, a0) +lhu s4, (#0, a0) +lhu s4, (#1, a0) +lhu s4, (#2, a0) +lhu s4, (#4, a0) +lhu s4, (#8, a0) +lhu s4, (#0x10, a0) +lhu s4, (#0x20, a0) +lhu s4, (#0x40, a0) +lhu s4, (#0x80, a0) +lhu s4, (#0x100, a0) +lhu s4, (#0x200, a0) +lhu s4, (#0x400, a0) +lhu s4, (#0x7ff, a0) +lhu s4, (#0xfffff801, a5) +lhu s4, (#0xfffffc00, a5) +lhu s4, (#0xfffffe00, a5) +lhu s4, (#0xffffff00, a5) +lhu s4, (#0xffffff80, a5) +lhu s4, (#0xffffffc0, a5) +lhu s4, (#0xffffffe0, a5) +lhu s4, (#0xfffffff0, a5) +lhu s4, (#0xfffffff8, a5) +lhu s4, (#0xfffffffc, a5) +lhu s4, (#0xfffffffe, a5) +lhu s4, (#0xffffffff, a5) +lhu s4, (#0, a5) +lhu s4, (#1, a5) +lhu s4, (#2, a5) +lhu s4, (#4, a5) +lhu s4, (#8, a5) +lhu s4, (#0x10, a5) +lhu s4, (#0x20, a5) +lhu s4, (#0x40, a5) +lhu s4, (#0x80, a5) +lhu s4, (#0x100, a5) +lhu s4, (#0x200, a5) +lhu s4, (#0x400, a5) +lhu s4, (#0x7ff, a5) +lhu s4, (#0xfffff801, s4) +lhu s4, (#0xfffffc00, s4) +lhu s4, (#0xfffffe00, s4) +lhu s4, (#0xffffff00, s4) +lhu s4, (#0xffffff80, s4) +lhu s4, (#0xffffffc0, s4) +lhu s4, (#0xffffffe0, s4) +lhu s4, (#0xfffffff0, s4) +lhu s4, (#0xfffffff8, s4) +lhu s4, (#0xfffffffc, s4) +lhu s4, (#0xfffffffe, s4) +lhu s4, (#0xffffffff, s4) +lhu s4, (#0, s4) +lhu s4, (#1, s4) +lhu s4, (#2, s4) +lhu s4, (#4, s4) +lhu s4, (#8, s4) +lhu s4, (#0x10, s4) +lhu s4, (#0x20, s4) +lhu s4, (#0x40, s4) +lhu s4, (#0x80, s4) +lhu s4, (#0x100, s4) +lhu s4, (#0x200, s4) +lhu s4, (#0x400, s4) +lhu s4, (#0x7ff, s4) +lhu s4, (#0xfffff801, s9) +lhu s4, (#0xfffffc00, s9) +lhu s4, (#0xfffffe00, s9) +lhu s4, (#0xffffff00, s9) +lhu s4, (#0xffffff80, s9) +lhu s4, (#0xffffffc0, s9) +lhu s4, (#0xffffffe0, s9) +lhu s4, (#0xfffffff0, s9) +lhu s4, (#0xfffffff8, s9) +lhu s4, (#0xfffffffc, s9) +lhu s4, (#0xfffffffe, s9) +lhu s4, (#0xffffffff, s9) +lhu s4, (#0, s9) +lhu s4, (#1, s9) +lhu s4, (#2, s9) +lhu s4, (#4, s9) +lhu s4, (#8, s9) +lhu s4, (#0x10, s9) +lhu s4, (#0x20, s9) +lhu s4, (#0x40, s9) +lhu s4, (#0x80, s9) +lhu s4, (#0x100, s9) +lhu s4, (#0x200, s9) +lhu s4, (#0x400, s9) +lhu s4, (#0x7ff, s9) +lhu s4, (#0xfffff801, t6) +lhu s4, (#0xfffffc00, t6) +lhu s4, (#0xfffffe00, t6) +lhu s4, (#0xffffff00, t6) +lhu s4, (#0xffffff80, t6) +lhu s4, (#0xffffffc0, t6) +lhu s4, (#0xffffffe0, t6) +lhu s4, (#0xfffffff0, t6) +lhu s4, (#0xfffffff8, t6) +lhu s4, (#0xfffffffc, t6) +lhu s4, (#0xfffffffe, t6) +lhu s4, (#0xffffffff, t6) +lhu s4, (#0, t6) +lhu s4, (#1, t6) +lhu s4, (#2, t6) +lhu s4, (#4, t6) +lhu s4, (#8, t6) +lhu s4, (#0x10, t6) +lhu s4, (#0x20, t6) +lhu s4, (#0x40, t6) +lhu s4, (#0x80, t6) +lhu s4, (#0x100, t6) +lhu s4, (#0x200, t6) +lhu s4, (#0x400, t6) +lhu s4, (#0x7ff, t6) +lhu s9, (#0xfffff801, zero) +lhu s9, (#0xfffffc00, zero) +lhu s9, (#0xfffffe00, zero) +lhu s9, (#0xffffff00, zero) +lhu s9, (#0xffffff80, zero) +lhu s9, (#0xffffffc0, zero) +lhu s9, (#0xffffffe0, zero) +lhu s9, (#0xfffffff0, zero) +lhu s9, (#0xfffffff8, zero) +lhu s9, (#0xfffffffc, zero) +lhu s9, (#0xfffffffe, zero) +lhu s9, (#0xffffffff, zero) +lhu s9, (#0, zero) +lhu s9, (#1, zero) +lhu s9, (#2, zero) +lhu s9, (#4, zero) +lhu s9, (#8, zero) +lhu s9, (#0x10, zero) +lhu s9, (#0x20, zero) +lhu s9, (#0x40, zero) +lhu s9, (#0x80, zero) +lhu s9, (#0x100, zero) +lhu s9, (#0x200, zero) +lhu s9, (#0x400, zero) +lhu s9, (#0x7ff, zero) +lhu s9, (#0xfffff801, ra) +lhu s9, (#0xfffffc00, ra) +lhu s9, (#0xfffffe00, ra) +lhu s9, (#0xffffff00, ra) +lhu s9, (#0xffffff80, ra) +lhu s9, (#0xffffffc0, ra) +lhu s9, (#0xffffffe0, ra) +lhu s9, (#0xfffffff0, ra) +lhu s9, (#0xfffffff8, ra) +lhu s9, (#0xfffffffc, ra) +lhu s9, (#0xfffffffe, ra) +lhu s9, (#0xffffffff, ra) +lhu s9, (#0, ra) +lhu s9, (#1, ra) +lhu s9, (#2, ra) +lhu s9, (#4, ra) +lhu s9, (#8, ra) +lhu s9, (#0x10, ra) +lhu s9, (#0x20, ra) +lhu s9, (#0x40, ra) +lhu s9, (#0x80, ra) +lhu s9, (#0x100, ra) +lhu s9, (#0x200, ra) +lhu s9, (#0x400, ra) +lhu s9, (#0x7ff, ra) +lhu s9, (#0xfffff801, t0) +lhu s9, (#0xfffffc00, t0) +lhu s9, (#0xfffffe00, t0) +lhu s9, (#0xffffff00, t0) +lhu s9, (#0xffffff80, t0) +lhu s9, (#0xffffffc0, t0) +lhu s9, (#0xffffffe0, t0) +lhu s9, (#0xfffffff0, t0) +lhu s9, (#0xfffffff8, t0) +lhu s9, (#0xfffffffc, t0) +lhu s9, (#0xfffffffe, t0) +lhu s9, (#0xffffffff, t0) +lhu s9, (#0, t0) +lhu s9, (#1, t0) +lhu s9, (#2, t0) +lhu s9, (#4, t0) +lhu s9, (#8, t0) +lhu s9, (#0x10, t0) +lhu s9, (#0x20, t0) +lhu s9, (#0x40, t0) +lhu s9, (#0x80, t0) +lhu s9, (#0x100, t0) +lhu s9, (#0x200, t0) +lhu s9, (#0x400, t0) +lhu s9, (#0x7ff, t0) +lhu s9, (#0xfffff801, a0) +lhu s9, (#0xfffffc00, a0) +lhu s9, (#0xfffffe00, a0) +lhu s9, (#0xffffff00, a0) +lhu s9, (#0xffffff80, a0) +lhu s9, (#0xffffffc0, a0) +lhu s9, (#0xffffffe0, a0) +lhu s9, (#0xfffffff0, a0) +lhu s9, (#0xfffffff8, a0) +lhu s9, (#0xfffffffc, a0) +lhu s9, (#0xfffffffe, a0) +lhu s9, (#0xffffffff, a0) +lhu s9, (#0, a0) +lhu s9, (#1, a0) +lhu s9, (#2, a0) +lhu s9, (#4, a0) +lhu s9, (#8, a0) +lhu s9, (#0x10, a0) +lhu s9, (#0x20, a0) +lhu s9, (#0x40, a0) +lhu s9, (#0x80, a0) +lhu s9, (#0x100, a0) +lhu s9, (#0x200, a0) +lhu s9, (#0x400, a0) +lhu s9, (#0x7ff, a0) +lhu s9, (#0xfffff801, a5) +lhu s9, (#0xfffffc00, a5) +lhu s9, (#0xfffffe00, a5) +lhu s9, (#0xffffff00, a5) +lhu s9, (#0xffffff80, a5) +lhu s9, (#0xffffffc0, a5) +lhu s9, (#0xffffffe0, a5) +lhu s9, (#0xfffffff0, a5) +lhu s9, (#0xfffffff8, a5) +lhu s9, (#0xfffffffc, a5) +lhu s9, (#0xfffffffe, a5) +lhu s9, (#0xffffffff, a5) +lhu s9, (#0, a5) +lhu s9, (#1, a5) +lhu s9, (#2, a5) +lhu s9, (#4, a5) +lhu s9, (#8, a5) +lhu s9, (#0x10, a5) +lhu s9, (#0x20, a5) +lhu s9, (#0x40, a5) +lhu s9, (#0x80, a5) +lhu s9, (#0x100, a5) +lhu s9, (#0x200, a5) +lhu s9, (#0x400, a5) +lhu s9, (#0x7ff, a5) +lhu s9, (#0xfffff801, s4) +lhu s9, (#0xfffffc00, s4) +lhu s9, (#0xfffffe00, s4) +lhu s9, (#0xffffff00, s4) +lhu s9, (#0xffffff80, s4) +lhu s9, (#0xffffffc0, s4) +lhu s9, (#0xffffffe0, s4) +lhu s9, (#0xfffffff0, s4) +lhu s9, (#0xfffffff8, s4) +lhu s9, (#0xfffffffc, s4) +lhu s9, (#0xfffffffe, s4) +lhu s9, (#0xffffffff, s4) +lhu s9, (#0, s4) +lhu s9, (#1, s4) +lhu s9, (#2, s4) +lhu s9, (#4, s4) +lhu s9, (#8, s4) +lhu s9, (#0x10, s4) +lhu s9, (#0x20, s4) +lhu s9, (#0x40, s4) +lhu s9, (#0x80, s4) +lhu s9, (#0x100, s4) +lhu s9, (#0x200, s4) +lhu s9, (#0x400, s4) +lhu s9, (#0x7ff, s4) +lhu s9, (#0xfffff801, s9) +lhu s9, (#0xfffffc00, s9) +lhu s9, (#0xfffffe00, s9) +lhu s9, (#0xffffff00, s9) +lhu s9, (#0xffffff80, s9) +lhu s9, (#0xffffffc0, s9) +lhu s9, (#0xffffffe0, s9) +lhu s9, (#0xfffffff0, s9) +lhu s9, (#0xfffffff8, s9) +lhu s9, (#0xfffffffc, s9) +lhu s9, (#0xfffffffe, s9) +lhu s9, (#0xffffffff, s9) +lhu s9, (#0, s9) +lhu s9, (#1, s9) +lhu s9, (#2, s9) +lhu s9, (#4, s9) +lhu s9, (#8, s9) +lhu s9, (#0x10, s9) +lhu s9, (#0x20, s9) +lhu s9, (#0x40, s9) +lhu s9, (#0x80, s9) +lhu s9, (#0x100, s9) +lhu s9, (#0x200, s9) +lhu s9, (#0x400, s9) +lhu s9, (#0x7ff, s9) +lhu s9, (#0xfffff801, t6) +lhu s9, (#0xfffffc00, t6) +lhu s9, (#0xfffffe00, t6) +lhu s9, (#0xffffff00, t6) +lhu s9, (#0xffffff80, t6) +lhu s9, (#0xffffffc0, t6) +lhu s9, (#0xffffffe0, t6) +lhu s9, (#0xfffffff0, t6) +lhu s9, (#0xfffffff8, t6) +lhu s9, (#0xfffffffc, t6) +lhu s9, (#0xfffffffe, t6) +lhu s9, (#0xffffffff, t6) +lhu s9, (#0, t6) +lhu s9, (#1, t6) +lhu s9, (#2, t6) +lhu s9, (#4, t6) +lhu s9, (#8, t6) +lhu s9, (#0x10, t6) +lhu s9, (#0x20, t6) +lhu s9, (#0x40, t6) +lhu s9, (#0x80, t6) +lhu s9, (#0x100, t6) +lhu s9, (#0x200, t6) +lhu s9, (#0x400, t6) +lhu s9, (#0x7ff, t6) +lhu t6, (#0xfffff801, zero) +lhu t6, (#0xfffffc00, zero) +lhu t6, (#0xfffffe00, zero) +lhu t6, (#0xffffff00, zero) +lhu t6, (#0xffffff80, zero) +lhu t6, (#0xffffffc0, zero) +lhu t6, (#0xffffffe0, zero) +lhu t6, (#0xfffffff0, zero) +lhu t6, (#0xfffffff8, zero) +lhu t6, (#0xfffffffc, zero) +lhu t6, (#0xfffffffe, zero) +lhu t6, (#0xffffffff, zero) +lhu t6, (#0, zero) +lhu t6, (#1, zero) +lhu t6, (#2, zero) +lhu t6, (#4, zero) +lhu t6, (#8, zero) +lhu t6, (#0x10, zero) +lhu t6, (#0x20, zero) +lhu t6, (#0x40, zero) +lhu t6, (#0x80, zero) +lhu t6, (#0x100, zero) +lhu t6, (#0x200, zero) +lhu t6, (#0x400, zero) +lhu t6, (#0x7ff, zero) +lhu t6, (#0xfffff801, ra) +lhu t6, (#0xfffffc00, ra) +lhu t6, (#0xfffffe00, ra) +lhu t6, (#0xffffff00, ra) +lhu t6, (#0xffffff80, ra) +lhu t6, (#0xffffffc0, ra) +lhu t6, (#0xffffffe0, ra) +lhu t6, (#0xfffffff0, ra) +lhu t6, (#0xfffffff8, ra) +lhu t6, (#0xfffffffc, ra) +lhu t6, (#0xfffffffe, ra) +lhu t6, (#0xffffffff, ra) +lhu t6, (#0, ra) +lhu t6, (#1, ra) +lhu t6, (#2, ra) +lhu t6, (#4, ra) +lhu t6, (#8, ra) +lhu t6, (#0x10, ra) +lhu t6, (#0x20, ra) +lhu t6, (#0x40, ra) +lhu t6, (#0x80, ra) +lhu t6, (#0x100, ra) +lhu t6, (#0x200, ra) +lhu t6, (#0x400, ra) +lhu t6, (#0x7ff, ra) +lhu t6, (#0xfffff801, t0) +lhu t6, (#0xfffffc00, t0) +lhu t6, (#0xfffffe00, t0) +lhu t6, (#0xffffff00, t0) +lhu t6, (#0xffffff80, t0) +lhu t6, (#0xffffffc0, t0) +lhu t6, (#0xffffffe0, t0) +lhu t6, (#0xfffffff0, t0) +lhu t6, (#0xfffffff8, t0) +lhu t6, (#0xfffffffc, t0) +lhu t6, (#0xfffffffe, t0) +lhu t6, (#0xffffffff, t0) +lhu t6, (#0, t0) +lhu t6, (#1, t0) +lhu t6, (#2, t0) +lhu t6, (#4, t0) +lhu t6, (#8, t0) +lhu t6, (#0x10, t0) +lhu t6, (#0x20, t0) +lhu t6, (#0x40, t0) +lhu t6, (#0x80, t0) +lhu t6, (#0x100, t0) +lhu t6, (#0x200, t0) +lhu t6, (#0x400, t0) +lhu t6, (#0x7ff, t0) +lhu t6, (#0xfffff801, a0) +lhu t6, (#0xfffffc00, a0) +lhu t6, (#0xfffffe00, a0) +lhu t6, (#0xffffff00, a0) +lhu t6, (#0xffffff80, a0) +lhu t6, (#0xffffffc0, a0) +lhu t6, (#0xffffffe0, a0) +lhu t6, (#0xfffffff0, a0) +lhu t6, (#0xfffffff8, a0) +lhu t6, (#0xfffffffc, a0) +lhu t6, (#0xfffffffe, a0) +lhu t6, (#0xffffffff, a0) +lhu t6, (#0, a0) +lhu t6, (#1, a0) +lhu t6, (#2, a0) +lhu t6, (#4, a0) +lhu t6, (#8, a0) +lhu t6, (#0x10, a0) +lhu t6, (#0x20, a0) +lhu t6, (#0x40, a0) +lhu t6, (#0x80, a0) +lhu t6, (#0x100, a0) +lhu t6, (#0x200, a0) +lhu t6, (#0x400, a0) +lhu t6, (#0x7ff, a0) +lhu t6, (#0xfffff801, a5) +lhu t6, (#0xfffffc00, a5) +lhu t6, (#0xfffffe00, a5) +lhu t6, (#0xffffff00, a5) +lhu t6, (#0xffffff80, a5) +lhu t6, (#0xffffffc0, a5) +lhu t6, (#0xffffffe0, a5) +lhu t6, (#0xfffffff0, a5) +lhu t6, (#0xfffffff8, a5) +lhu t6, (#0xfffffffc, a5) +lhu t6, (#0xfffffffe, a5) +lhu t6, (#0xffffffff, a5) +lhu t6, (#0, a5) +lhu t6, (#1, a5) +lhu t6, (#2, a5) +lhu t6, (#4, a5) +lhu t6, (#8, a5) +lhu t6, (#0x10, a5) +lhu t6, (#0x20, a5) +lhu t6, (#0x40, a5) +lhu t6, (#0x80, a5) +lhu t6, (#0x100, a5) +lhu t6, (#0x200, a5) +lhu t6, (#0x400, a5) +lhu t6, (#0x7ff, a5) +lhu t6, (#0xfffff801, s4) +lhu t6, (#0xfffffc00, s4) +lhu t6, (#0xfffffe00, s4) +lhu t6, (#0xffffff00, s4) +lhu t6, (#0xffffff80, s4) +lhu t6, (#0xffffffc0, s4) +lhu t6, (#0xffffffe0, s4) +lhu t6, (#0xfffffff0, s4) +lhu t6, (#0xfffffff8, s4) +lhu t6, (#0xfffffffc, s4) +lhu t6, (#0xfffffffe, s4) +lhu t6, (#0xffffffff, s4) +lhu t6, (#0, s4) +lhu t6, (#1, s4) +lhu t6, (#2, s4) +lhu t6, (#4, s4) +lhu t6, (#8, s4) +lhu t6, (#0x10, s4) +lhu t6, (#0x20, s4) +lhu t6, (#0x40, s4) +lhu t6, (#0x80, s4) +lhu t6, (#0x100, s4) +lhu t6, (#0x200, s4) +lhu t6, (#0x400, s4) +lhu t6, (#0x7ff, s4) +lhu t6, (#0xfffff801, s9) +lhu t6, (#0xfffffc00, s9) +lhu t6, (#0xfffffe00, s9) +lhu t6, (#0xffffff00, s9) +lhu t6, (#0xffffff80, s9) +lhu t6, (#0xffffffc0, s9) +lhu t6, (#0xffffffe0, s9) +lhu t6, (#0xfffffff0, s9) +lhu t6, (#0xfffffff8, s9) +lhu t6, (#0xfffffffc, s9) +lhu t6, (#0xfffffffe, s9) +lhu t6, (#0xffffffff, s9) +lhu t6, (#0, s9) +lhu t6, (#1, s9) +lhu t6, (#2, s9) +lhu t6, (#4, s9) +lhu t6, (#8, s9) +lhu t6, (#0x10, s9) +lhu t6, (#0x20, s9) +lhu t6, (#0x40, s9) +lhu t6, (#0x80, s9) +lhu t6, (#0x100, s9) +lhu t6, (#0x200, s9) +lhu t6, (#0x400, s9) +lhu t6, (#0x7ff, s9) +lhu t6, (#0xfffff801, t6) +lhu t6, (#0xfffffc00, t6) +lhu t6, (#0xfffffe00, t6) +lhu t6, (#0xffffff00, t6) +lhu t6, (#0xffffff80, t6) +lhu t6, (#0xffffffc0, t6) +lhu t6, (#0xffffffe0, t6) +lhu t6, (#0xfffffff0, t6) +lhu t6, (#0xfffffff8, t6) +lhu t6, (#0xfffffffc, t6) +lhu t6, (#0xfffffffe, t6) +lhu t6, (#0xffffffff, t6) +lhu t6, (#0, t6) +lhu t6, (#1, t6) +lhu t6, (#2, t6) +lhu t6, (#4, t6) +lhu t6, (#8, t6) +lhu t6, (#0x10, t6) +lhu t6, (#0x20, t6) +lhu t6, (#0x40, t6) +lhu t6, (#0x80, t6) +lhu t6, (#0x100, t6) +lhu t6, (#0x200, t6) +lhu t6, (#0x400, t6) +lhu t6, (#0x7ff, t6) diff --git a/tests/riscv/rv32i/lui.asm b/tests/riscv/rv32i/lui.asm new file mode 100644 index 0000000..c652043 --- /dev/null +++ b/tests/riscv/rv32i/lui.asm @@ -0,0 +1,44 @@ +.lang riscv32 +.org 0x0 + +lui zero, #0x0 +lui zero, #0x1000000 +lui zero, #0x10000000 +lui zero, #0x80000000 +lui zero, #0xfffff000 +lui ra, #0x0 +lui ra, #0x1000000 +lui ra, #0x10000000 +lui ra, #0x80000000 +lui ra, #0xfffff000 +lui t0, #0x0 +lui t0, #0x1000000 +lui t0, #0x10000000 +lui t0, #0x80000000 +lui t0, #0xfffff000 +lui a0, #0x0 +lui a0, #0x1000000 +lui a0, #0x10000000 +lui a0, #0x80000000 +lui a0, #0xfffff000 +lui a5, #0x0 +lui a5, #0x1000000 +lui a5, #0x10000000 +lui a5, #0x80000000 +lui a5, #0xfffff000 +lui s4, #0x0 +lui s4, #0x1000000 +lui s4, #0x10000000 +lui s4, #0x80000000 +lui s4, #0xfffff000 +lui s9, #0x0 +lui s9, #0x1000000 +lui s9, #0x10000000 +lui s9, #0x80000000 +lui s9, #0xfffff000 +lui t6, #0x0 +lui t6, #0x1000000 +lui t6, #0x10000000 +lui t6, #0x80000000 +lui t6, #0xfffff000 + diff --git a/tests/riscv/rv32i/lui.bin b/tests/riscv/rv32i/lui.bin new file mode 100644 index 0000000000000000000000000000000000000000..d01b7277546717a29e1c99c48ed9b3538ff6e6b9 GIT binary patch literal 160 zcmWm5Q3k{?6ouj25FtXkn{2PU>b6FyQp25Z9?r|}J1Zhq#Adr4>yvqEw%KmS`ENxl uTG5JjWv=R5eXDQvy}8CUu5pcfxXyL1bDev+!3}P3gZpYzo7&W-mYF|ZqcRWx literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/lui.disasm b/tests/riscv/rv32i/lui.disasm new file mode 100644 index 0000000..2f90ccb --- /dev/null +++ b/tests/riscv/rv32i/lui.disasm @@ -0,0 +1,40 @@ +lui zero, #0x0 +lui zero, #0x1000000 +lui zero, #0x10000000 +lui zero, #0x80000000 +lui zero, #0xfffff000 +lui ra, #0x0 +lui ra, #0x1000000 +lui ra, #0x10000000 +lui ra, #0x80000000 +lui ra, #0xfffff000 +lui t0, #0x0 +lui t0, #0x1000000 +lui t0, #0x10000000 +lui t0, #0x80000000 +lui t0, #0xfffff000 +lui a0, #0x0 +lui a0, #0x1000000 +lui a0, #0x10000000 +lui a0, #0x80000000 +lui a0, #0xfffff000 +lui a5, #0x0 +lui a5, #0x1000000 +lui a5, #0x10000000 +lui a5, #0x80000000 +lui a5, #0xfffff000 +lui s4, #0x0 +lui s4, #0x1000000 +lui s4, #0x10000000 +lui s4, #0x80000000 +lui s4, #0xfffff000 +lui s9, #0x0 +lui s9, #0x1000000 +lui s9, #0x10000000 +lui s9, #0x80000000 +lui s9, #0xfffff000 +lui t6, #0x0 +lui t6, #0x1000000 +lui t6, #0x10000000 +lui t6, #0x80000000 +lui t6, #0xfffff000 diff --git a/tests/riscv/rv32i/lw.asm b/tests/riscv/rv32i/lw.asm new file mode 100644 index 0000000..1377eb0 --- /dev/null +++ b/tests/riscv/rv32i/lw.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +lw zero, (#-2047, zero) +lw zero, (#-1024, zero) +lw zero, (#-512, zero) +lw zero, (#-256, zero) +lw zero, (#-128, zero) +lw zero, (#-64, zero) +lw zero, (#-32, zero) +lw zero, (#-16, zero) +lw zero, (#-8, zero) +lw zero, (#-4, zero) +lw zero, (#-2, zero) +lw zero, (#-1, zero) +lw zero, (#0, zero) +lw zero, (#1, zero) +lw zero, (#2, zero) +lw zero, (#4, zero) +lw zero, (#8, zero) +lw zero, (#16, zero) +lw zero, (#32, zero) +lw zero, (#64, zero) +lw zero, (#128, zero) +lw zero, (#256, zero) +lw zero, (#512, zero) +lw zero, (#1024, zero) +lw zero, (#2047, zero) +lw zero, (#-2047, ra) +lw zero, (#-1024, ra) +lw zero, (#-512, ra) +lw zero, (#-256, ra) +lw zero, (#-128, ra) +lw zero, (#-64, ra) +lw zero, (#-32, ra) +lw zero, (#-16, ra) +lw zero, (#-8, ra) +lw zero, (#-4, ra) +lw zero, (#-2, ra) +lw zero, (#-1, ra) +lw zero, (#0, ra) +lw zero, (#1, ra) +lw zero, (#2, ra) +lw zero, (#4, ra) +lw zero, (#8, ra) +lw zero, (#16, ra) +lw zero, (#32, ra) +lw zero, (#64, ra) +lw zero, (#128, ra) +lw zero, (#256, ra) +lw zero, (#512, ra) +lw zero, (#1024, ra) +lw zero, (#2047, ra) +lw zero, (#-2047, t0) +lw zero, (#-1024, t0) +lw zero, (#-512, t0) +lw zero, (#-256, t0) +lw zero, (#-128, t0) +lw zero, (#-64, t0) +lw zero, (#-32, t0) +lw zero, (#-16, t0) +lw zero, (#-8, t0) +lw zero, (#-4, t0) +lw zero, (#-2, t0) +lw zero, (#-1, t0) +lw zero, (#0, t0) +lw zero, (#1, t0) +lw zero, (#2, t0) +lw zero, (#4, t0) +lw zero, (#8, t0) +lw zero, (#16, t0) +lw zero, (#32, t0) +lw zero, (#64, t0) +lw zero, (#128, t0) +lw zero, (#256, t0) +lw zero, (#512, t0) +lw zero, (#1024, t0) +lw zero, (#2047, t0) +lw zero, (#-2047, a0) +lw zero, (#-1024, a0) +lw zero, (#-512, a0) +lw zero, (#-256, a0) +lw zero, (#-128, a0) +lw zero, (#-64, a0) +lw zero, (#-32, a0) +lw zero, (#-16, a0) +lw zero, (#-8, a0) +lw zero, (#-4, a0) +lw zero, (#-2, a0) +lw zero, (#-1, a0) +lw zero, (#0, a0) +lw zero, (#1, a0) +lw zero, (#2, a0) +lw zero, (#4, a0) +lw zero, (#8, a0) +lw zero, (#16, a0) +lw zero, (#32, a0) +lw zero, (#64, a0) +lw zero, (#128, a0) +lw zero, (#256, a0) +lw zero, (#512, a0) +lw zero, (#1024, a0) +lw zero, (#2047, a0) +lw zero, (#-2047, a5) +lw zero, (#-1024, a5) +lw zero, (#-512, a5) +lw zero, (#-256, a5) +lw zero, (#-128, a5) +lw zero, (#-64, a5) +lw zero, (#-32, a5) +lw zero, (#-16, a5) +lw zero, (#-8, a5) +lw zero, (#-4, a5) +lw zero, (#-2, a5) +lw zero, (#-1, a5) +lw zero, (#0, a5) +lw zero, (#1, a5) +lw zero, (#2, a5) +lw zero, (#4, a5) +lw zero, (#8, a5) +lw zero, (#16, a5) +lw zero, (#32, a5) +lw zero, (#64, a5) +lw zero, (#128, a5) +lw zero, (#256, a5) +lw zero, (#512, a5) +lw zero, (#1024, a5) +lw zero, (#2047, a5) +lw zero, (#-2047, s4) +lw zero, (#-1024, s4) +lw zero, (#-512, s4) +lw zero, (#-256, s4) +lw zero, (#-128, s4) +lw zero, (#-64, s4) +lw zero, (#-32, s4) +lw zero, (#-16, s4) +lw zero, (#-8, s4) +lw zero, (#-4, s4) +lw zero, (#-2, s4) +lw zero, (#-1, s4) +lw zero, (#0, s4) +lw zero, (#1, s4) +lw zero, (#2, s4) +lw zero, (#4, s4) +lw zero, (#8, s4) +lw zero, (#16, s4) +lw zero, (#32, s4) +lw zero, (#64, s4) +lw zero, (#128, s4) +lw zero, (#256, s4) +lw zero, (#512, s4) +lw zero, (#1024, s4) +lw zero, (#2047, s4) +lw zero, (#-2047, s9) +lw zero, (#-1024, s9) +lw zero, (#-512, s9) +lw zero, (#-256, s9) +lw zero, (#-128, s9) +lw zero, (#-64, s9) +lw zero, (#-32, s9) +lw zero, (#-16, s9) +lw zero, (#-8, s9) +lw zero, (#-4, s9) +lw zero, (#-2, s9) +lw zero, (#-1, s9) +lw zero, (#0, s9) +lw zero, (#1, s9) +lw zero, (#2, s9) +lw zero, (#4, s9) +lw zero, (#8, s9) +lw zero, (#16, s9) +lw zero, (#32, s9) +lw zero, (#64, s9) +lw zero, (#128, s9) +lw zero, (#256, s9) +lw zero, (#512, s9) +lw zero, (#1024, s9) +lw zero, (#2047, s9) +lw zero, (#-2047, t6) +lw zero, (#-1024, t6) +lw zero, (#-512, t6) +lw zero, (#-256, t6) +lw zero, (#-128, t6) +lw zero, (#-64, t6) +lw zero, (#-32, t6) +lw zero, (#-16, t6) +lw zero, (#-8, t6) +lw zero, (#-4, t6) +lw zero, (#-2, t6) +lw zero, (#-1, t6) +lw zero, (#0, t6) +lw zero, (#1, t6) +lw zero, (#2, t6) +lw zero, (#4, t6) +lw zero, (#8, t6) +lw zero, (#16, t6) +lw zero, (#32, t6) +lw zero, (#64, t6) +lw zero, (#128, t6) +lw zero, (#256, t6) +lw zero, (#512, t6) +lw zero, (#1024, t6) +lw zero, (#2047, t6) +lw ra, (#-2047, zero) +lw ra, (#-1024, zero) +lw ra, (#-512, zero) +lw ra, (#-256, zero) +lw ra, (#-128, zero) +lw ra, (#-64, zero) +lw ra, (#-32, zero) +lw ra, (#-16, zero) +lw ra, (#-8, zero) +lw ra, (#-4, zero) +lw ra, (#-2, zero) +lw ra, (#-1, zero) +lw ra, (#0, zero) +lw ra, (#1, zero) +lw ra, (#2, zero) +lw ra, (#4, zero) +lw ra, (#8, zero) +lw ra, (#16, zero) +lw ra, (#32, zero) +lw ra, (#64, zero) +lw ra, (#128, zero) +lw ra, (#256, zero) +lw ra, (#512, zero) +lw ra, (#1024, zero) +lw ra, (#2047, zero) +lw ra, (#-2047, ra) +lw ra, (#-1024, ra) +lw ra, (#-512, ra) +lw ra, (#-256, ra) +lw ra, (#-128, ra) +lw ra, (#-64, ra) +lw ra, (#-32, ra) +lw ra, (#-16, ra) +lw ra, (#-8, ra) +lw ra, (#-4, ra) +lw ra, (#-2, ra) +lw ra, (#-1, ra) +lw ra, (#0, ra) +lw ra, (#1, ra) +lw ra, (#2, ra) +lw ra, (#4, ra) +lw ra, (#8, ra) +lw ra, (#16, ra) +lw ra, (#32, ra) +lw ra, (#64, ra) +lw ra, (#128, ra) +lw ra, (#256, ra) +lw ra, (#512, ra) +lw ra, (#1024, ra) +lw ra, (#2047, ra) +lw ra, (#-2047, t0) +lw ra, (#-1024, t0) +lw ra, (#-512, t0) +lw ra, (#-256, t0) +lw ra, (#-128, t0) +lw ra, (#-64, t0) +lw ra, (#-32, t0) +lw ra, (#-16, t0) +lw ra, (#-8, t0) +lw ra, (#-4, t0) +lw ra, (#-2, t0) +lw ra, (#-1, t0) +lw ra, (#0, t0) +lw ra, (#1, t0) +lw ra, (#2, t0) +lw ra, (#4, t0) +lw ra, (#8, t0) +lw ra, (#16, t0) +lw ra, (#32, t0) +lw ra, (#64, t0) +lw ra, (#128, t0) +lw ra, (#256, t0) +lw ra, (#512, t0) +lw ra, (#1024, t0) +lw ra, (#2047, t0) +lw ra, (#-2047, a0) +lw ra, (#-1024, a0) +lw ra, (#-512, a0) +lw ra, (#-256, a0) +lw ra, (#-128, a0) +lw ra, (#-64, a0) +lw ra, (#-32, a0) +lw ra, (#-16, a0) +lw ra, (#-8, a0) +lw ra, (#-4, a0) +lw ra, (#-2, a0) +lw ra, (#-1, a0) +lw ra, (#0, a0) +lw ra, (#1, a0) +lw ra, (#2, a0) +lw ra, (#4, a0) +lw ra, (#8, a0) +lw ra, (#16, a0) +lw ra, (#32, a0) +lw ra, (#64, a0) +lw ra, (#128, a0) +lw ra, (#256, a0) +lw ra, (#512, a0) +lw ra, (#1024, a0) +lw ra, (#2047, a0) +lw ra, (#-2047, a5) +lw ra, (#-1024, a5) +lw ra, (#-512, a5) +lw ra, (#-256, a5) +lw ra, (#-128, a5) +lw ra, (#-64, a5) +lw ra, (#-32, a5) +lw ra, (#-16, a5) +lw ra, (#-8, a5) +lw ra, (#-4, a5) +lw ra, (#-2, a5) +lw ra, (#-1, a5) +lw ra, (#0, a5) +lw ra, (#1, a5) +lw ra, (#2, a5) +lw ra, (#4, a5) +lw ra, (#8, a5) +lw ra, (#16, a5) +lw ra, (#32, a5) +lw ra, (#64, a5) +lw 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(#0xffffff80, zero) +lw zero, (#0xffffffc0, zero) +lw zero, (#0xffffffe0, zero) +lw zero, (#0xfffffff0, zero) +lw zero, (#0xfffffff8, zero) +lw zero, (#0xfffffffc, zero) +lw zero, (#0xfffffffe, zero) +lw zero, (#0xffffffff, zero) +lw zero, (#0, zero) +lw zero, (#1, zero) +lw zero, (#2, zero) +lw zero, (#4, zero) +lw zero, (#8, zero) +lw zero, (#0x10, zero) +lw zero, (#0x20, zero) +lw zero, (#0x40, zero) +lw zero, (#0x80, zero) +lw zero, (#0x100, zero) +lw zero, (#0x200, zero) +lw zero, (#0x400, zero) +lw zero, (#0x7ff, zero) +lw zero, (#0xfffff801, ra) +lw zero, (#0xfffffc00, ra) +lw zero, (#0xfffffe00, ra) +lw zero, (#0xffffff00, ra) +lw zero, (#0xffffff80, ra) +lw zero, (#0xffffffc0, ra) +lw zero, (#0xffffffe0, ra) +lw zero, (#0xfffffff0, ra) +lw zero, (#0xfffffff8, ra) +lw zero, (#0xfffffffc, ra) +lw zero, (#0xfffffffe, ra) +lw zero, (#0xffffffff, ra) +lw zero, (#0, ra) +lw zero, (#1, ra) +lw zero, (#2, ra) +lw zero, (#4, ra) +lw zero, (#8, ra) +lw zero, (#0x10, ra) +lw zero, (#0x20, ra) +lw zero, (#0x40, ra) +lw zero, (#0x80, ra) +lw zero, (#0x100, ra) +lw zero, (#0x200, ra) +lw zero, (#0x400, ra) +lw zero, (#0x7ff, ra) +lw zero, (#0xfffff801, t0) +lw zero, (#0xfffffc00, t0) +lw zero, (#0xfffffe00, t0) +lw zero, (#0xffffff00, t0) +lw zero, (#0xffffff80, t0) +lw zero, (#0xffffffc0, t0) +lw zero, (#0xffffffe0, t0) +lw zero, (#0xfffffff0, t0) +lw zero, (#0xfffffff8, t0) +lw zero, (#0xfffffffc, t0) +lw zero, (#0xfffffffe, t0) +lw zero, (#0xffffffff, t0) +lw zero, (#0, t0) +lw zero, (#1, t0) +lw zero, (#2, t0) +lw zero, (#4, t0) +lw zero, (#8, t0) +lw zero, (#0x10, t0) +lw zero, (#0x20, t0) +lw zero, (#0x40, t0) +lw zero, (#0x80, t0) +lw zero, (#0x100, t0) +lw zero, (#0x200, t0) +lw zero, (#0x400, t0) +lw zero, (#0x7ff, t0) +lw zero, (#0xfffff801, a0) +lw zero, (#0xfffffc00, a0) +lw zero, (#0xfffffe00, a0) +lw zero, (#0xffffff00, a0) +lw zero, (#0xffffff80, a0) +lw zero, (#0xffffffc0, a0) +lw zero, (#0xffffffe0, a0) +lw zero, (#0xfffffff0, a0) +lw zero, (#0xfffffff8, a0) +lw zero, (#0xfffffffc, a0) +lw zero, (#0xfffffffe, a0) +lw zero, (#0xffffffff, a0) +lw zero, (#0, a0) +lw zero, (#1, a0) +lw zero, (#2, a0) +lw zero, (#4, a0) +lw zero, (#8, a0) +lw zero, (#0x10, a0) +lw zero, (#0x20, a0) +lw zero, (#0x40, a0) +lw zero, (#0x80, a0) +lw zero, (#0x100, a0) +lw zero, (#0x200, a0) +lw zero, (#0x400, a0) +lw zero, (#0x7ff, a0) +lw zero, (#0xfffff801, a5) +lw zero, (#0xfffffc00, a5) +lw zero, (#0xfffffe00, a5) +lw zero, (#0xffffff00, a5) +lw zero, (#0xffffff80, a5) +lw zero, (#0xffffffc0, a5) +lw zero, (#0xffffffe0, a5) +lw zero, (#0xfffffff0, a5) +lw zero, (#0xfffffff8, a5) +lw zero, (#0xfffffffc, a5) +lw zero, (#0xfffffffe, a5) +lw zero, (#0xffffffff, a5) +lw zero, (#0, a5) +lw zero, (#1, a5) +lw zero, (#2, a5) +lw zero, (#4, a5) +lw zero, (#8, a5) +lw zero, (#0x10, a5) +lw zero, (#0x20, a5) +lw zero, (#0x40, a5) +lw zero, (#0x80, a5) +lw zero, (#0x100, a5) +lw zero, (#0x200, a5) +lw zero, (#0x400, a5) +lw zero, (#0x7ff, a5) +lw zero, (#0xfffff801, s4) +lw zero, (#0xfffffc00, s4) +lw zero, (#0xfffffe00, s4) +lw zero, (#0xffffff00, s4) +lw zero, (#0xffffff80, s4) +lw zero, (#0xffffffc0, s4) +lw zero, (#0xffffffe0, s4) +lw zero, (#0xfffffff0, s4) +lw zero, (#0xfffffff8, s4) +lw zero, (#0xfffffffc, s4) +lw zero, (#0xfffffffe, s4) +lw zero, (#0xffffffff, s4) +lw zero, (#0, s4) +lw zero, (#1, s4) +lw zero, (#2, s4) +lw zero, (#4, s4) +lw zero, (#8, s4) +lw zero, (#0x10, s4) +lw zero, (#0x20, s4) +lw zero, (#0x40, s4) +lw zero, (#0x80, s4) +lw zero, (#0x100, s4) +lw zero, (#0x200, s4) +lw zero, (#0x400, s4) +lw zero, (#0x7ff, s4) +lw zero, (#0xfffff801, s9) +lw zero, (#0xfffffc00, s9) +lw zero, (#0xfffffe00, s9) +lw zero, (#0xffffff00, s9) +lw zero, (#0xffffff80, s9) +lw zero, (#0xffffffc0, s9) +lw zero, (#0xffffffe0, s9) +lw zero, (#0xfffffff0, s9) +lw zero, (#0xfffffff8, s9) +lw zero, (#0xfffffffc, s9) +lw zero, (#0xfffffffe, s9) +lw zero, (#0xffffffff, s9) +lw zero, (#0, s9) +lw zero, (#1, s9) +lw zero, (#2, s9) +lw zero, (#4, s9) +lw zero, (#8, s9) +lw zero, (#0x10, s9) +lw zero, (#0x20, s9) +lw zero, (#0x40, s9) +lw zero, (#0x80, s9) +lw zero, (#0x100, s9) +lw zero, (#0x200, s9) +lw zero, (#0x400, s9) +lw zero, (#0x7ff, s9) +lw zero, (#0xfffff801, t6) +lw zero, (#0xfffffc00, t6) +lw zero, (#0xfffffe00, t6) +lw zero, (#0xffffff00, t6) +lw zero, (#0xffffff80, t6) +lw zero, (#0xffffffc0, t6) +lw zero, (#0xffffffe0, t6) +lw zero, (#0xfffffff0, t6) +lw zero, (#0xfffffff8, t6) +lw zero, (#0xfffffffc, t6) +lw zero, (#0xfffffffe, t6) +lw zero, (#0xffffffff, t6) +lw zero, (#0, t6) +lw zero, (#1, t6) +lw zero, (#2, t6) +lw zero, (#4, t6) +lw zero, (#8, t6) +lw zero, (#0x10, t6) +lw zero, (#0x20, t6) +lw zero, (#0x40, t6) +lw zero, (#0x80, t6) +lw zero, (#0x100, t6) +lw zero, (#0x200, t6) +lw zero, (#0x400, t6) +lw zero, (#0x7ff, t6) +lw ra, (#0xfffff801, zero) +lw ra, (#0xfffffc00, zero) +lw ra, (#0xfffffe00, zero) +lw ra, (#0xffffff00, zero) +lw ra, (#0xffffff80, zero) +lw ra, (#0xffffffc0, zero) +lw ra, (#0xffffffe0, zero) +lw ra, (#0xfffffff0, zero) +lw ra, (#0xfffffff8, zero) +lw ra, (#0xfffffffc, zero) +lw ra, (#0xfffffffe, zero) +lw ra, (#0xffffffff, zero) +lw ra, (#0, zero) +lw ra, (#1, zero) +lw ra, (#2, zero) +lw ra, (#4, zero) +lw ra, (#8, zero) +lw ra, (#0x10, zero) +lw ra, (#0x20, zero) +lw ra, (#0x40, zero) +lw ra, (#0x80, zero) +lw ra, (#0x100, zero) +lw ra, (#0x200, zero) +lw ra, (#0x400, zero) +lw ra, (#0x7ff, zero) +lw ra, (#0xfffff801, ra) +lw ra, (#0xfffffc00, ra) +lw ra, (#0xfffffe00, ra) +lw ra, (#0xffffff00, ra) +lw ra, (#0xffffff80, ra) +lw ra, (#0xffffffc0, ra) +lw ra, (#0xffffffe0, ra) +lw ra, (#0xfffffff0, ra) +lw ra, (#0xfffffff8, ra) +lw ra, (#0xfffffffc, ra) +lw ra, (#0xfffffffe, ra) +lw ra, (#0xffffffff, ra) +lw ra, (#0, ra) +lw ra, (#1, ra) +lw ra, (#2, ra) +lw ra, (#4, ra) +lw ra, (#8, ra) +lw ra, (#0x10, ra) +lw ra, (#0x20, ra) +lw ra, (#0x40, ra) +lw ra, (#0x80, ra) +lw ra, (#0x100, ra) +lw ra, (#0x200, ra) +lw ra, (#0x400, ra) +lw ra, (#0x7ff, ra) +lw ra, (#0xfffff801, t0) +lw ra, (#0xfffffc00, t0) +lw ra, (#0xfffffe00, t0) +lw ra, (#0xffffff00, t0) +lw ra, (#0xffffff80, t0) +lw ra, (#0xffffffc0, t0) +lw ra, (#0xffffffe0, t0) +lw ra, (#0xfffffff0, t0) +lw ra, (#0xfffffff8, t0) +lw ra, (#0xfffffffc, t0) +lw ra, (#0xfffffffe, t0) +lw ra, (#0xffffffff, t0) +lw ra, (#0, t0) +lw ra, (#1, t0) +lw ra, (#2, t0) +lw ra, (#4, t0) +lw ra, (#8, t0) +lw ra, (#0x10, t0) +lw ra, (#0x20, t0) +lw ra, (#0x40, t0) +lw ra, (#0x80, t0) +lw ra, (#0x100, t0) +lw ra, (#0x200, t0) +lw ra, (#0x400, t0) +lw ra, (#0x7ff, t0) +lw ra, (#0xfffff801, a0) +lw ra, (#0xfffffc00, a0) +lw ra, (#0xfffffe00, a0) +lw ra, (#0xffffff00, a0) +lw ra, (#0xffffff80, a0) +lw ra, (#0xffffffc0, a0) +lw ra, (#0xffffffe0, a0) +lw ra, (#0xfffffff0, a0) +lw ra, (#0xfffffff8, a0) +lw ra, (#0xfffffffc, a0) +lw ra, (#0xfffffffe, a0) +lw ra, (#0xffffffff, a0) +lw ra, (#0, a0) +lw ra, (#1, a0) +lw ra, (#2, a0) +lw ra, (#4, a0) +lw ra, (#8, a0) +lw ra, (#0x10, a0) +lw ra, (#0x20, a0) +lw ra, (#0x40, a0) +lw ra, (#0x80, a0) +lw ra, (#0x100, a0) +lw ra, (#0x200, a0) +lw ra, (#0x400, a0) +lw ra, (#0x7ff, a0) +lw ra, (#0xfffff801, a5) +lw ra, (#0xfffffc00, a5) +lw ra, (#0xfffffe00, a5) +lw ra, (#0xffffff00, a5) +lw ra, (#0xffffff80, a5) +lw ra, (#0xffffffc0, a5) +lw ra, (#0xffffffe0, a5) +lw ra, (#0xfffffff0, a5) +lw ra, (#0xfffffff8, a5) +lw ra, (#0xfffffffc, a5) +lw ra, (#0xfffffffe, a5) +lw ra, (#0xffffffff, a5) +lw ra, (#0, a5) +lw ra, (#1, a5) +lw ra, (#2, a5) +lw ra, (#4, a5) +lw ra, (#8, a5) +lw ra, (#0x10, a5) +lw ra, (#0x20, a5) +lw ra, (#0x40, a5) +lw ra, (#0x80, a5) +lw ra, (#0x100, a5) +lw ra, (#0x200, a5) +lw ra, (#0x400, a5) +lw ra, (#0x7ff, a5) +lw ra, (#0xfffff801, s4) +lw ra, (#0xfffffc00, s4) +lw ra, (#0xfffffe00, s4) +lw ra, (#0xffffff00, s4) +lw ra, (#0xffffff80, s4) +lw ra, (#0xffffffc0, s4) +lw ra, (#0xffffffe0, s4) +lw ra, (#0xfffffff0, s4) +lw ra, (#0xfffffff8, s4) +lw ra, (#0xfffffffc, s4) +lw ra, (#0xfffffffe, s4) +lw ra, (#0xffffffff, s4) +lw ra, (#0, s4) +lw ra, (#1, s4) +lw ra, (#2, s4) +lw ra, (#4, s4) +lw ra, (#8, s4) +lw ra, (#0x10, s4) +lw ra, (#0x20, s4) +lw ra, (#0x40, s4) +lw ra, (#0x80, s4) +lw ra, (#0x100, s4) +lw ra, (#0x200, s4) +lw ra, (#0x400, s4) +lw ra, (#0x7ff, s4) +lw ra, (#0xfffff801, s9) +lw ra, (#0xfffffc00, s9) +lw ra, (#0xfffffe00, s9) +lw ra, (#0xffffff00, s9) +lw ra, (#0xffffff80, s9) +lw ra, (#0xffffffc0, s9) +lw ra, (#0xffffffe0, s9) +lw ra, (#0xfffffff0, s9) +lw ra, (#0xfffffff8, s9) +lw ra, (#0xfffffffc, s9) +lw ra, (#0xfffffffe, s9) +lw ra, (#0xffffffff, s9) +lw ra, (#0, s9) +lw ra, (#1, s9) +lw ra, (#2, s9) +lw ra, (#4, s9) +lw ra, (#8, s9) +lw ra, (#0x10, s9) +lw ra, (#0x20, s9) +lw ra, (#0x40, s9) +lw ra, (#0x80, s9) +lw ra, (#0x100, s9) +lw ra, (#0x200, s9) +lw ra, (#0x400, s9) +lw ra, (#0x7ff, s9) +lw ra, (#0xfffff801, t6) +lw ra, (#0xfffffc00, t6) +lw ra, (#0xfffffe00, t6) +lw ra, (#0xffffff00, t6) +lw ra, (#0xffffff80, t6) +lw ra, (#0xffffffc0, t6) +lw ra, (#0xffffffe0, t6) +lw ra, (#0xfffffff0, t6) +lw ra, (#0xfffffff8, t6) +lw ra, (#0xfffffffc, t6) +lw ra, (#0xfffffffe, t6) +lw ra, (#0xffffffff, t6) +lw ra, (#0, t6) +lw ra, (#1, t6) +lw ra, (#2, t6) +lw ra, (#4, t6) +lw ra, (#8, t6) +lw ra, (#0x10, t6) +lw ra, (#0x20, t6) +lw ra, (#0x40, t6) +lw ra, (#0x80, t6) +lw ra, (#0x100, t6) +lw ra, (#0x200, t6) +lw ra, (#0x400, t6) +lw ra, (#0x7ff, t6) +lw t0, (#0xfffff801, zero) +lw t0, (#0xfffffc00, zero) +lw t0, (#0xfffffe00, zero) +lw t0, (#0xffffff00, zero) +lw t0, (#0xffffff80, zero) +lw t0, (#0xffffffc0, zero) +lw t0, (#0xffffffe0, zero) +lw t0, (#0xfffffff0, zero) +lw t0, (#0xfffffff8, zero) +lw t0, (#0xfffffffc, zero) +lw t0, (#0xfffffffe, zero) +lw t0, (#0xffffffff, zero) +lw t0, (#0, zero) +lw t0, (#1, zero) +lw t0, (#2, zero) +lw t0, (#4, zero) +lw t0, (#8, zero) +lw t0, (#0x10, zero) +lw t0, (#0x20, zero) +lw t0, (#0x40, zero) +lw t0, (#0x80, zero) +lw t0, (#0x100, zero) +lw t0, (#0x200, zero) +lw t0, (#0x400, zero) +lw t0, (#0x7ff, zero) +lw t0, (#0xfffff801, ra) +lw t0, (#0xfffffc00, ra) +lw t0, (#0xfffffe00, ra) +lw t0, (#0xffffff00, ra) +lw t0, (#0xffffff80, ra) +lw t0, (#0xffffffc0, ra) +lw t0, (#0xffffffe0, ra) +lw t0, (#0xfffffff0, ra) +lw t0, (#0xfffffff8, ra) +lw t0, (#0xfffffffc, ra) +lw t0, (#0xfffffffe, ra) +lw t0, (#0xffffffff, ra) +lw t0, (#0, ra) +lw t0, (#1, ra) +lw t0, (#2, ra) +lw t0, (#4, ra) +lw t0, (#8, ra) +lw t0, (#0x10, ra) +lw t0, (#0x20, ra) +lw t0, (#0x40, ra) +lw t0, (#0x80, ra) +lw t0, (#0x100, ra) +lw t0, (#0x200, ra) +lw t0, (#0x400, ra) +lw t0, (#0x7ff, ra) +lw t0, (#0xfffff801, t0) +lw t0, (#0xfffffc00, t0) +lw t0, (#0xfffffe00, t0) +lw t0, (#0xffffff00, t0) +lw t0, (#0xffffff80, t0) +lw t0, (#0xffffffc0, t0) +lw t0, (#0xffffffe0, t0) +lw t0, (#0xfffffff0, t0) +lw t0, (#0xfffffff8, t0) +lw t0, (#0xfffffffc, t0) +lw t0, (#0xfffffffe, t0) +lw t0, (#0xffffffff, t0) +lw t0, (#0, t0) +lw t0, (#1, t0) +lw t0, (#2, t0) +lw t0, (#4, t0) +lw t0, (#8, t0) +lw t0, (#0x10, t0) +lw t0, (#0x20, t0) +lw t0, (#0x40, t0) +lw t0, (#0x80, t0) +lw t0, (#0x100, t0) +lw t0, (#0x200, t0) +lw t0, (#0x400, t0) +lw t0, (#0x7ff, t0) +lw t0, (#0xfffff801, a0) +lw t0, (#0xfffffc00, a0) +lw t0, (#0xfffffe00, a0) +lw t0, (#0xffffff00, a0) +lw t0, (#0xffffff80, a0) +lw t0, (#0xffffffc0, a0) +lw t0, (#0xffffffe0, a0) +lw t0, (#0xfffffff0, a0) +lw t0, (#0xfffffff8, a0) +lw t0, (#0xfffffffc, a0) +lw t0, (#0xfffffffe, a0) +lw t0, (#0xffffffff, a0) +lw t0, (#0, a0) +lw t0, (#1, a0) +lw t0, (#2, a0) +lw t0, (#4, a0) +lw t0, (#8, a0) +lw t0, (#0x10, a0) +lw t0, (#0x20, a0) +lw t0, (#0x40, a0) +lw t0, (#0x80, a0) +lw t0, (#0x100, a0) +lw t0, (#0x200, a0) +lw t0, (#0x400, a0) +lw t0, (#0x7ff, a0) +lw t0, (#0xfffff801, a5) +lw t0, (#0xfffffc00, a5) +lw t0, (#0xfffffe00, a5) +lw t0, (#0xffffff00, a5) +lw t0, (#0xffffff80, a5) +lw t0, (#0xffffffc0, a5) +lw t0, (#0xffffffe0, a5) +lw t0, (#0xfffffff0, a5) +lw t0, (#0xfffffff8, a5) +lw t0, (#0xfffffffc, a5) +lw t0, (#0xfffffffe, a5) +lw t0, (#0xffffffff, a5) +lw t0, (#0, a5) +lw t0, (#1, a5) +lw t0, (#2, a5) +lw t0, (#4, a5) +lw t0, (#8, a5) +lw t0, (#0x10, a5) +lw t0, (#0x20, a5) +lw t0, (#0x40, a5) +lw t0, (#0x80, a5) +lw t0, (#0x100, a5) +lw t0, (#0x200, a5) +lw t0, (#0x400, a5) +lw t0, (#0x7ff, a5) +lw t0, (#0xfffff801, s4) +lw t0, (#0xfffffc00, s4) +lw t0, (#0xfffffe00, s4) +lw t0, (#0xffffff00, s4) +lw t0, (#0xffffff80, s4) +lw t0, (#0xffffffc0, s4) +lw t0, (#0xffffffe0, s4) +lw t0, (#0xfffffff0, s4) +lw t0, (#0xfffffff8, s4) +lw t0, (#0xfffffffc, s4) +lw t0, (#0xfffffffe, s4) +lw t0, (#0xffffffff, s4) +lw t0, (#0, s4) +lw t0, (#1, s4) +lw t0, (#2, s4) +lw t0, (#4, s4) +lw t0, (#8, s4) +lw t0, (#0x10, s4) +lw t0, (#0x20, s4) +lw t0, (#0x40, s4) +lw t0, (#0x80, s4) +lw t0, (#0x100, s4) +lw t0, (#0x200, s4) +lw t0, (#0x400, s4) +lw t0, (#0x7ff, s4) +lw t0, (#0xfffff801, s9) +lw t0, (#0xfffffc00, s9) +lw t0, (#0xfffffe00, s9) +lw t0, (#0xffffff00, s9) +lw t0, (#0xffffff80, s9) +lw t0, (#0xffffffc0, s9) +lw t0, (#0xffffffe0, s9) +lw t0, (#0xfffffff0, s9) +lw t0, (#0xfffffff8, s9) +lw t0, (#0xfffffffc, s9) +lw t0, (#0xfffffffe, s9) +lw t0, (#0xffffffff, s9) +lw t0, (#0, s9) +lw t0, (#1, s9) +lw t0, (#2, s9) +lw t0, (#4, s9) +lw t0, (#8, s9) +lw t0, (#0x10, s9) +lw t0, (#0x20, s9) +lw t0, (#0x40, s9) +lw t0, (#0x80, s9) +lw t0, (#0x100, s9) +lw t0, (#0x200, s9) +lw t0, (#0x400, s9) +lw t0, (#0x7ff, s9) +lw t0, (#0xfffff801, t6) +lw t0, (#0xfffffc00, t6) +lw t0, (#0xfffffe00, t6) +lw t0, (#0xffffff00, t6) +lw t0, (#0xffffff80, t6) +lw t0, (#0xffffffc0, t6) +lw t0, (#0xffffffe0, t6) +lw t0, (#0xfffffff0, t6) +lw t0, (#0xfffffff8, t6) +lw t0, (#0xfffffffc, t6) +lw t0, (#0xfffffffe, t6) +lw t0, (#0xffffffff, t6) +lw t0, (#0, t6) +lw t0, (#1, t6) +lw t0, (#2, t6) +lw t0, (#4, t6) +lw t0, (#8, t6) +lw t0, (#0x10, t6) +lw t0, (#0x20, t6) +lw t0, (#0x40, t6) +lw t0, (#0x80, t6) +lw t0, (#0x100, t6) +lw t0, (#0x200, t6) +lw t0, (#0x400, t6) +lw t0, (#0x7ff, t6) +lw a0, (#0xfffff801, zero) +lw a0, (#0xfffffc00, zero) +lw a0, (#0xfffffe00, zero) +lw a0, (#0xffffff00, zero) +lw a0, (#0xffffff80, zero) +lw a0, (#0xffffffc0, zero) +lw a0, (#0xffffffe0, zero) +lw a0, (#0xfffffff0, zero) +lw a0, (#0xfffffff8, zero) +lw a0, (#0xfffffffc, zero) +lw a0, (#0xfffffffe, zero) +lw a0, (#0xffffffff, zero) +lw a0, (#0, zero) +lw a0, (#1, zero) +lw a0, (#2, zero) +lw a0, (#4, zero) +lw a0, (#8, zero) +lw a0, (#0x10, zero) +lw a0, (#0x20, zero) +lw a0, (#0x40, zero) +lw a0, (#0x80, zero) +lw a0, (#0x100, zero) +lw a0, (#0x200, zero) +lw a0, (#0x400, zero) +lw a0, (#0x7ff, zero) +lw a0, (#0xfffff801, ra) +lw a0, (#0xfffffc00, ra) +lw a0, (#0xfffffe00, ra) +lw a0, (#0xffffff00, ra) +lw a0, (#0xffffff80, ra) +lw a0, (#0xffffffc0, ra) +lw a0, (#0xffffffe0, ra) +lw a0, (#0xfffffff0, ra) +lw a0, (#0xfffffff8, ra) +lw a0, (#0xfffffffc, ra) +lw a0, (#0xfffffffe, ra) +lw a0, (#0xffffffff, ra) +lw a0, (#0, ra) +lw a0, (#1, ra) +lw a0, (#2, ra) +lw a0, (#4, ra) +lw a0, (#8, ra) +lw a0, (#0x10, ra) +lw a0, (#0x20, ra) +lw a0, (#0x40, ra) +lw a0, (#0x80, ra) +lw a0, (#0x100, ra) +lw a0, (#0x200, ra) +lw a0, (#0x400, ra) +lw a0, (#0x7ff, ra) +lw a0, (#0xfffff801, t0) +lw a0, (#0xfffffc00, t0) +lw a0, (#0xfffffe00, t0) +lw a0, (#0xffffff00, t0) +lw a0, (#0xffffff80, t0) +lw a0, (#0xffffffc0, t0) +lw a0, (#0xffffffe0, t0) +lw a0, (#0xfffffff0, t0) +lw a0, (#0xfffffff8, t0) +lw a0, (#0xfffffffc, t0) +lw a0, (#0xfffffffe, t0) +lw a0, (#0xffffffff, t0) +lw a0, (#0, t0) +lw a0, (#1, t0) +lw a0, (#2, t0) +lw a0, (#4, t0) +lw a0, (#8, t0) +lw a0, (#0x10, t0) +lw a0, (#0x20, t0) +lw a0, (#0x40, t0) +lw a0, (#0x80, t0) +lw a0, (#0x100, t0) +lw a0, (#0x200, t0) +lw a0, (#0x400, t0) +lw a0, (#0x7ff, t0) +lw a0, (#0xfffff801, a0) +lw a0, (#0xfffffc00, a0) +lw a0, (#0xfffffe00, a0) +lw a0, (#0xffffff00, a0) +lw a0, (#0xffffff80, a0) +lw a0, (#0xffffffc0, a0) +lw a0, (#0xffffffe0, a0) +lw a0, (#0xfffffff0, a0) +lw a0, (#0xfffffff8, a0) +lw a0, (#0xfffffffc, a0) +lw a0, (#0xfffffffe, a0) +lw a0, (#0xffffffff, a0) +lw a0, (#0, a0) +lw a0, (#1, a0) +lw a0, (#2, a0) +lw a0, (#4, a0) +lw a0, (#8, a0) +lw a0, (#0x10, a0) +lw a0, (#0x20, a0) +lw a0, (#0x40, a0) +lw a0, (#0x80, a0) +lw a0, (#0x100, a0) +lw a0, (#0x200, a0) +lw a0, (#0x400, a0) +lw a0, (#0x7ff, a0) +lw a0, (#0xfffff801, a5) +lw a0, (#0xfffffc00, a5) +lw a0, (#0xfffffe00, a5) +lw a0, (#0xffffff00, a5) +lw a0, (#0xffffff80, a5) +lw a0, (#0xffffffc0, a5) +lw a0, (#0xffffffe0, a5) +lw a0, (#0xfffffff0, a5) +lw a0, (#0xfffffff8, a5) +lw a0, (#0xfffffffc, a5) +lw a0, (#0xfffffffe, a5) +lw a0, (#0xffffffff, a5) +lw a0, (#0, a5) +lw a0, (#1, a5) +lw a0, (#2, a5) +lw a0, (#4, a5) +lw a0, (#8, a5) +lw a0, (#0x10, a5) +lw a0, (#0x20, a5) +lw a0, (#0x40, a5) +lw a0, (#0x80, a5) +lw a0, (#0x100, a5) +lw a0, (#0x200, a5) +lw a0, (#0x400, a5) +lw a0, (#0x7ff, a5) +lw a0, (#0xfffff801, s4) +lw a0, (#0xfffffc00, s4) +lw a0, (#0xfffffe00, s4) +lw a0, (#0xffffff00, s4) +lw a0, (#0xffffff80, s4) +lw a0, (#0xffffffc0, s4) +lw a0, (#0xffffffe0, s4) +lw a0, (#0xfffffff0, s4) +lw a0, (#0xfffffff8, s4) +lw a0, (#0xfffffffc, s4) +lw a0, (#0xfffffffe, s4) +lw a0, (#0xffffffff, s4) +lw a0, (#0, s4) +lw a0, (#1, s4) +lw a0, (#2, s4) +lw a0, (#4, s4) +lw a0, (#8, s4) +lw a0, (#0x10, s4) +lw a0, (#0x20, s4) +lw a0, (#0x40, s4) +lw a0, (#0x80, s4) +lw a0, (#0x100, s4) +lw a0, (#0x200, s4) +lw a0, (#0x400, s4) +lw a0, (#0x7ff, s4) +lw a0, (#0xfffff801, s9) +lw a0, (#0xfffffc00, s9) +lw a0, (#0xfffffe00, s9) +lw a0, (#0xffffff00, s9) +lw a0, (#0xffffff80, s9) +lw a0, (#0xffffffc0, s9) +lw a0, (#0xffffffe0, s9) +lw a0, (#0xfffffff0, s9) +lw a0, (#0xfffffff8, s9) +lw a0, (#0xfffffffc, s9) +lw a0, (#0xfffffffe, s9) +lw a0, (#0xffffffff, s9) +lw a0, (#0, s9) +lw a0, (#1, s9) +lw a0, (#2, s9) +lw a0, (#4, s9) +lw a0, (#8, s9) +lw a0, (#0x10, s9) +lw a0, (#0x20, s9) +lw a0, (#0x40, s9) +lw a0, (#0x80, s9) +lw a0, (#0x100, s9) +lw a0, (#0x200, s9) +lw a0, (#0x400, s9) +lw a0, (#0x7ff, s9) +lw a0, (#0xfffff801, t6) +lw a0, (#0xfffffc00, t6) +lw a0, (#0xfffffe00, t6) +lw a0, (#0xffffff00, t6) +lw a0, (#0xffffff80, t6) +lw a0, (#0xffffffc0, t6) +lw a0, (#0xffffffe0, t6) +lw a0, (#0xfffffff0, t6) +lw a0, (#0xfffffff8, t6) +lw a0, (#0xfffffffc, t6) +lw a0, (#0xfffffffe, t6) +lw a0, (#0xffffffff, t6) +lw a0, (#0, t6) +lw a0, (#1, t6) +lw a0, (#2, t6) +lw a0, (#4, t6) +lw a0, (#8, t6) +lw a0, (#0x10, t6) +lw a0, (#0x20, t6) +lw a0, (#0x40, t6) +lw a0, (#0x80, t6) +lw a0, (#0x100, t6) +lw a0, (#0x200, t6) +lw a0, (#0x400, t6) +lw a0, (#0x7ff, t6) +lw a5, (#0xfffff801, zero) +lw a5, (#0xfffffc00, zero) +lw a5, (#0xfffffe00, zero) +lw a5, (#0xffffff00, zero) +lw a5, (#0xffffff80, zero) +lw a5, (#0xffffffc0, zero) +lw a5, (#0xffffffe0, zero) +lw a5, (#0xfffffff0, zero) +lw a5, (#0xfffffff8, zero) +lw a5, (#0xfffffffc, zero) +lw a5, (#0xfffffffe, zero) +lw a5, (#0xffffffff, zero) +lw a5, (#0, zero) +lw a5, (#1, zero) +lw a5, (#2, zero) +lw a5, (#4, zero) +lw a5, (#8, zero) +lw a5, (#0x10, zero) +lw a5, (#0x20, zero) +lw a5, (#0x40, zero) +lw a5, (#0x80, zero) +lw a5, (#0x100, zero) +lw a5, (#0x200, zero) +lw a5, (#0x400, zero) +lw a5, (#0x7ff, zero) +lw a5, (#0xfffff801, ra) +lw a5, (#0xfffffc00, ra) +lw a5, (#0xfffffe00, ra) +lw a5, (#0xffffff00, ra) +lw a5, (#0xffffff80, ra) +lw a5, (#0xffffffc0, ra) +lw a5, (#0xffffffe0, ra) +lw a5, (#0xfffffff0, ra) +lw a5, (#0xfffffff8, ra) +lw a5, (#0xfffffffc, ra) +lw a5, (#0xfffffffe, ra) +lw a5, (#0xffffffff, ra) +lw a5, (#0, ra) +lw a5, (#1, ra) +lw a5, (#2, ra) +lw a5, (#4, ra) +lw a5, (#8, ra) +lw a5, (#0x10, ra) +lw a5, (#0x20, ra) +lw a5, (#0x40, ra) +lw a5, (#0x80, ra) +lw a5, (#0x100, ra) +lw a5, (#0x200, ra) +lw a5, (#0x400, ra) +lw a5, (#0x7ff, ra) +lw a5, (#0xfffff801, t0) +lw a5, (#0xfffffc00, t0) +lw a5, (#0xfffffe00, t0) +lw a5, (#0xffffff00, t0) +lw a5, (#0xffffff80, t0) +lw a5, (#0xffffffc0, t0) +lw a5, (#0xffffffe0, t0) +lw a5, (#0xfffffff0, t0) +lw a5, (#0xfffffff8, t0) +lw a5, (#0xfffffffc, t0) +lw a5, (#0xfffffffe, t0) +lw a5, (#0xffffffff, t0) +lw a5, (#0, t0) +lw a5, (#1, t0) +lw a5, (#2, t0) +lw a5, (#4, t0) +lw a5, (#8, t0) +lw a5, (#0x10, t0) +lw a5, (#0x20, t0) +lw a5, (#0x40, t0) +lw a5, (#0x80, t0) +lw a5, (#0x100, t0) +lw a5, (#0x200, t0) +lw a5, (#0x400, t0) +lw a5, (#0x7ff, t0) +lw a5, (#0xfffff801, a0) +lw a5, (#0xfffffc00, a0) +lw a5, (#0xfffffe00, a0) +lw a5, (#0xffffff00, a0) +lw a5, (#0xffffff80, a0) +lw a5, (#0xffffffc0, a0) +lw a5, (#0xffffffe0, a0) +lw a5, (#0xfffffff0, a0) +lw a5, (#0xfffffff8, a0) +lw a5, (#0xfffffffc, a0) +lw a5, (#0xfffffffe, a0) +lw a5, (#0xffffffff, a0) +lw a5, (#0, a0) +lw a5, (#1, a0) +lw a5, (#2, a0) +lw a5, (#4, a0) +lw a5, (#8, a0) +lw a5, (#0x10, a0) +lw a5, (#0x20, a0) +lw a5, (#0x40, a0) +lw a5, (#0x80, a0) +lw a5, (#0x100, a0) +lw a5, (#0x200, a0) +lw a5, (#0x400, a0) +lw a5, (#0x7ff, a0) +lw a5, (#0xfffff801, a5) +lw a5, (#0xfffffc00, a5) +lw a5, (#0xfffffe00, a5) +lw a5, (#0xffffff00, a5) +lw a5, (#0xffffff80, a5) +lw a5, (#0xffffffc0, a5) +lw a5, (#0xffffffe0, a5) +lw a5, (#0xfffffff0, a5) +lw a5, (#0xfffffff8, a5) +lw a5, (#0xfffffffc, a5) +lw a5, (#0xfffffffe, a5) +lw a5, (#0xffffffff, a5) +lw a5, (#0, a5) +lw a5, (#1, a5) +lw a5, (#2, a5) +lw a5, (#4, a5) +lw a5, (#8, a5) +lw a5, (#0x10, a5) +lw a5, (#0x20, a5) +lw a5, (#0x40, a5) +lw a5, (#0x80, a5) +lw a5, (#0x100, a5) +lw a5, (#0x200, a5) +lw a5, (#0x400, a5) +lw a5, (#0x7ff, a5) +lw a5, (#0xfffff801, s4) +lw a5, (#0xfffffc00, s4) +lw a5, (#0xfffffe00, s4) +lw a5, (#0xffffff00, s4) +lw a5, (#0xffffff80, s4) +lw a5, (#0xffffffc0, s4) +lw a5, (#0xffffffe0, s4) +lw a5, (#0xfffffff0, s4) +lw a5, (#0xfffffff8, s4) +lw a5, (#0xfffffffc, s4) +lw a5, (#0xfffffffe, s4) +lw a5, (#0xffffffff, s4) +lw a5, (#0, s4) +lw a5, (#1, s4) +lw a5, (#2, s4) +lw a5, (#4, s4) +lw a5, (#8, s4) +lw a5, (#0x10, s4) +lw a5, (#0x20, s4) +lw a5, (#0x40, s4) +lw a5, (#0x80, s4) +lw a5, (#0x100, s4) +lw a5, (#0x200, s4) +lw a5, (#0x400, s4) +lw a5, (#0x7ff, s4) +lw a5, (#0xfffff801, s9) +lw a5, (#0xfffffc00, s9) +lw a5, (#0xfffffe00, s9) +lw a5, (#0xffffff00, s9) +lw a5, (#0xffffff80, s9) +lw a5, (#0xffffffc0, s9) +lw a5, (#0xffffffe0, s9) +lw a5, (#0xfffffff0, s9) +lw a5, (#0xfffffff8, s9) +lw a5, (#0xfffffffc, s9) +lw a5, (#0xfffffffe, s9) +lw a5, (#0xffffffff, s9) +lw a5, (#0, s9) +lw a5, (#1, s9) +lw a5, (#2, s9) +lw a5, (#4, s9) +lw a5, (#8, s9) +lw a5, (#0x10, s9) +lw a5, (#0x20, s9) +lw a5, (#0x40, s9) +lw a5, (#0x80, s9) +lw a5, (#0x100, s9) +lw a5, (#0x200, s9) +lw a5, (#0x400, s9) +lw a5, (#0x7ff, s9) +lw a5, (#0xfffff801, t6) +lw a5, (#0xfffffc00, t6) +lw a5, (#0xfffffe00, t6) +lw a5, (#0xffffff00, t6) +lw a5, (#0xffffff80, t6) +lw a5, (#0xffffffc0, t6) +lw a5, (#0xffffffe0, t6) +lw a5, (#0xfffffff0, t6) +lw a5, (#0xfffffff8, t6) +lw a5, (#0xfffffffc, t6) +lw a5, (#0xfffffffe, t6) +lw a5, (#0xffffffff, t6) +lw a5, (#0, t6) +lw a5, (#1, t6) +lw a5, (#2, t6) +lw a5, (#4, t6) +lw a5, (#8, t6) +lw a5, (#0x10, t6) +lw a5, (#0x20, t6) +lw a5, (#0x40, t6) +lw a5, (#0x80, t6) +lw a5, (#0x100, t6) +lw a5, (#0x200, t6) +lw a5, (#0x400, t6) +lw a5, (#0x7ff, t6) +lw s4, (#0xfffff801, zero) +lw s4, (#0xfffffc00, zero) +lw s4, (#0xfffffe00, zero) +lw s4, (#0xffffff00, zero) +lw s4, (#0xffffff80, zero) +lw s4, (#0xffffffc0, zero) +lw s4, (#0xffffffe0, zero) +lw s4, (#0xfffffff0, zero) +lw s4, (#0xfffffff8, zero) +lw s4, (#0xfffffffc, zero) +lw s4, (#0xfffffffe, zero) +lw s4, (#0xffffffff, zero) +lw s4, (#0, zero) +lw s4, (#1, zero) +lw s4, (#2, zero) +lw s4, (#4, zero) +lw s4, (#8, zero) +lw s4, (#0x10, zero) +lw s4, (#0x20, zero) +lw s4, (#0x40, zero) +lw s4, (#0x80, zero) +lw s4, (#0x100, zero) +lw s4, (#0x200, zero) +lw s4, (#0x400, zero) +lw s4, (#0x7ff, zero) +lw s4, (#0xfffff801, ra) +lw s4, (#0xfffffc00, ra) +lw s4, (#0xfffffe00, ra) +lw s4, (#0xffffff00, ra) +lw s4, (#0xffffff80, ra) +lw s4, (#0xffffffc0, ra) +lw s4, (#0xffffffe0, ra) +lw s4, (#0xfffffff0, ra) +lw s4, (#0xfffffff8, ra) +lw s4, (#0xfffffffc, ra) +lw s4, (#0xfffffffe, ra) +lw s4, (#0xffffffff, ra) +lw s4, (#0, ra) +lw s4, (#1, ra) +lw s4, (#2, ra) +lw s4, (#4, ra) +lw s4, (#8, ra) +lw s4, (#0x10, ra) +lw s4, (#0x20, ra) +lw s4, (#0x40, ra) +lw s4, (#0x80, ra) +lw s4, (#0x100, ra) +lw s4, (#0x200, ra) +lw s4, (#0x400, ra) +lw s4, (#0x7ff, ra) +lw s4, (#0xfffff801, t0) +lw s4, (#0xfffffc00, t0) +lw s4, (#0xfffffe00, t0) +lw s4, (#0xffffff00, t0) +lw s4, (#0xffffff80, t0) +lw s4, (#0xffffffc0, t0) +lw s4, (#0xffffffe0, t0) +lw s4, (#0xfffffff0, t0) +lw s4, (#0xfffffff8, t0) +lw s4, (#0xfffffffc, t0) +lw s4, (#0xfffffffe, t0) +lw s4, (#0xffffffff, t0) +lw s4, (#0, t0) +lw s4, (#1, t0) +lw s4, (#2, t0) +lw s4, (#4, t0) +lw s4, (#8, t0) +lw s4, (#0x10, t0) +lw s4, (#0x20, t0) +lw s4, (#0x40, t0) +lw s4, (#0x80, t0) +lw s4, (#0x100, t0) +lw s4, (#0x200, t0) +lw s4, (#0x400, t0) +lw s4, (#0x7ff, t0) +lw s4, (#0xfffff801, a0) +lw s4, (#0xfffffc00, a0) +lw s4, (#0xfffffe00, a0) +lw s4, (#0xffffff00, a0) +lw s4, (#0xffffff80, a0) +lw s4, (#0xffffffc0, a0) +lw s4, (#0xffffffe0, a0) +lw s4, (#0xfffffff0, a0) +lw s4, (#0xfffffff8, a0) +lw s4, (#0xfffffffc, a0) +lw s4, (#0xfffffffe, a0) +lw s4, (#0xffffffff, a0) +lw s4, (#0, a0) +lw s4, (#1, a0) +lw s4, (#2, a0) +lw s4, (#4, a0) +lw s4, (#8, a0) +lw s4, (#0x10, a0) +lw s4, (#0x20, a0) +lw s4, (#0x40, a0) +lw s4, (#0x80, a0) +lw s4, (#0x100, a0) +lw s4, (#0x200, a0) +lw s4, (#0x400, a0) +lw s4, (#0x7ff, a0) +lw s4, (#0xfffff801, a5) +lw s4, (#0xfffffc00, a5) +lw s4, (#0xfffffe00, a5) +lw s4, (#0xffffff00, a5) +lw s4, (#0xffffff80, a5) +lw s4, (#0xffffffc0, a5) +lw s4, (#0xffffffe0, a5) +lw s4, (#0xfffffff0, a5) +lw s4, (#0xfffffff8, a5) +lw s4, (#0xfffffffc, a5) +lw s4, (#0xfffffffe, a5) +lw s4, (#0xffffffff, a5) +lw s4, (#0, a5) +lw s4, (#1, a5) +lw s4, (#2, a5) +lw s4, (#4, a5) +lw s4, (#8, a5) +lw s4, (#0x10, a5) +lw s4, (#0x20, a5) +lw s4, (#0x40, a5) +lw s4, (#0x80, a5) +lw s4, (#0x100, a5) +lw s4, (#0x200, a5) +lw s4, (#0x400, a5) +lw s4, (#0x7ff, a5) +lw s4, (#0xfffff801, s4) +lw s4, (#0xfffffc00, s4) +lw s4, (#0xfffffe00, s4) +lw s4, (#0xffffff00, s4) +lw s4, (#0xffffff80, s4) +lw s4, (#0xffffffc0, s4) +lw s4, (#0xffffffe0, s4) +lw s4, (#0xfffffff0, s4) +lw s4, (#0xfffffff8, s4) +lw s4, (#0xfffffffc, s4) +lw s4, (#0xfffffffe, s4) +lw s4, (#0xffffffff, s4) +lw s4, (#0, s4) +lw s4, (#1, s4) +lw s4, (#2, s4) +lw s4, (#4, s4) +lw s4, (#8, s4) +lw s4, (#0x10, s4) +lw s4, (#0x20, s4) +lw s4, (#0x40, s4) +lw s4, (#0x80, s4) +lw s4, (#0x100, s4) +lw s4, (#0x200, s4) +lw s4, (#0x400, s4) +lw s4, (#0x7ff, s4) +lw s4, (#0xfffff801, s9) +lw s4, (#0xfffffc00, s9) +lw s4, (#0xfffffe00, s9) +lw s4, (#0xffffff00, s9) +lw s4, (#0xffffff80, s9) +lw s4, (#0xffffffc0, s9) +lw s4, (#0xffffffe0, s9) +lw s4, (#0xfffffff0, s9) +lw s4, (#0xfffffff8, s9) +lw s4, (#0xfffffffc, s9) +lw s4, (#0xfffffffe, s9) +lw s4, (#0xffffffff, s9) +lw s4, (#0, s9) +lw s4, (#1, s9) +lw s4, (#2, s9) +lw s4, (#4, s9) +lw s4, (#8, s9) +lw s4, (#0x10, s9) +lw s4, (#0x20, s9) +lw s4, (#0x40, s9) +lw s4, (#0x80, s9) +lw s4, (#0x100, s9) +lw s4, (#0x200, s9) +lw s4, (#0x400, s9) +lw s4, (#0x7ff, s9) +lw s4, (#0xfffff801, t6) +lw s4, (#0xfffffc00, t6) +lw s4, (#0xfffffe00, t6) +lw s4, (#0xffffff00, t6) +lw s4, (#0xffffff80, t6) +lw s4, (#0xffffffc0, t6) +lw s4, (#0xffffffe0, t6) +lw s4, (#0xfffffff0, t6) +lw s4, (#0xfffffff8, t6) +lw s4, (#0xfffffffc, t6) +lw s4, (#0xfffffffe, t6) +lw s4, (#0xffffffff, t6) +lw s4, (#0, t6) +lw s4, (#1, t6) +lw s4, (#2, t6) +lw s4, (#4, t6) +lw s4, (#8, t6) +lw s4, (#0x10, t6) +lw s4, (#0x20, t6) +lw s4, (#0x40, t6) +lw s4, (#0x80, t6) +lw s4, (#0x100, t6) +lw s4, (#0x200, t6) +lw s4, (#0x400, t6) +lw s4, (#0x7ff, t6) +lw s9, (#0xfffff801, zero) +lw s9, (#0xfffffc00, zero) +lw s9, (#0xfffffe00, zero) +lw s9, (#0xffffff00, zero) +lw s9, (#0xffffff80, zero) +lw s9, (#0xffffffc0, zero) +lw s9, (#0xffffffe0, zero) +lw s9, (#0xfffffff0, zero) +lw s9, (#0xfffffff8, zero) +lw s9, (#0xfffffffc, zero) +lw s9, (#0xfffffffe, zero) +lw s9, (#0xffffffff, zero) +lw s9, (#0, zero) +lw s9, (#1, zero) +lw s9, (#2, zero) +lw s9, (#4, zero) +lw s9, (#8, zero) +lw s9, (#0x10, zero) +lw s9, (#0x20, zero) +lw s9, (#0x40, zero) +lw s9, (#0x80, zero) +lw s9, (#0x100, zero) +lw s9, (#0x200, zero) +lw s9, (#0x400, zero) +lw s9, (#0x7ff, zero) +lw s9, (#0xfffff801, ra) +lw s9, (#0xfffffc00, ra) +lw s9, (#0xfffffe00, ra) +lw s9, (#0xffffff00, ra) +lw s9, (#0xffffff80, ra) +lw s9, (#0xffffffc0, ra) +lw s9, (#0xffffffe0, ra) +lw s9, (#0xfffffff0, ra) +lw s9, (#0xfffffff8, ra) +lw s9, (#0xfffffffc, ra) +lw s9, (#0xfffffffe, ra) +lw s9, (#0xffffffff, ra) +lw s9, (#0, ra) +lw s9, (#1, ra) +lw s9, (#2, ra) +lw s9, (#4, ra) +lw s9, (#8, ra) +lw s9, (#0x10, ra) +lw s9, (#0x20, ra) +lw s9, (#0x40, ra) +lw s9, (#0x80, ra) +lw s9, (#0x100, ra) +lw s9, (#0x200, ra) +lw s9, (#0x400, ra) +lw s9, (#0x7ff, ra) +lw s9, (#0xfffff801, t0) +lw s9, (#0xfffffc00, t0) +lw s9, (#0xfffffe00, t0) +lw s9, (#0xffffff00, t0) +lw s9, (#0xffffff80, t0) +lw s9, (#0xffffffc0, t0) +lw s9, (#0xffffffe0, t0) +lw s9, (#0xfffffff0, t0) +lw s9, (#0xfffffff8, t0) +lw s9, (#0xfffffffc, t0) +lw s9, (#0xfffffffe, t0) +lw s9, (#0xffffffff, t0) +lw s9, (#0, t0) +lw s9, (#1, t0) +lw s9, (#2, t0) +lw s9, (#4, t0) +lw s9, (#8, t0) +lw s9, (#0x10, t0) +lw s9, (#0x20, t0) +lw s9, (#0x40, t0) +lw s9, (#0x80, t0) +lw s9, (#0x100, t0) +lw s9, (#0x200, t0) +lw s9, (#0x400, t0) +lw s9, (#0x7ff, t0) +lw s9, (#0xfffff801, a0) +lw s9, (#0xfffffc00, a0) +lw s9, (#0xfffffe00, a0) +lw s9, (#0xffffff00, a0) +lw s9, (#0xffffff80, a0) +lw s9, (#0xffffffc0, a0) +lw s9, (#0xffffffe0, a0) +lw s9, (#0xfffffff0, a0) +lw s9, (#0xfffffff8, a0) +lw s9, (#0xfffffffc, a0) +lw s9, (#0xfffffffe, a0) +lw s9, (#0xffffffff, a0) +lw s9, (#0, a0) +lw s9, (#1, a0) +lw s9, (#2, a0) +lw s9, (#4, a0) +lw s9, (#8, a0) +lw s9, (#0x10, a0) +lw s9, (#0x20, a0) +lw s9, (#0x40, a0) +lw s9, (#0x80, a0) +lw s9, (#0x100, a0) +lw s9, (#0x200, a0) +lw s9, (#0x400, a0) +lw s9, (#0x7ff, a0) +lw s9, (#0xfffff801, a5) +lw s9, (#0xfffffc00, a5) +lw s9, (#0xfffffe00, a5) +lw s9, (#0xffffff00, a5) +lw s9, (#0xffffff80, a5) +lw s9, (#0xffffffc0, a5) +lw s9, (#0xffffffe0, a5) +lw s9, (#0xfffffff0, a5) +lw s9, (#0xfffffff8, a5) +lw s9, (#0xfffffffc, a5) +lw s9, (#0xfffffffe, a5) +lw s9, (#0xffffffff, a5) +lw s9, (#0, a5) +lw s9, (#1, a5) +lw s9, (#2, a5) +lw s9, (#4, a5) +lw s9, (#8, a5) +lw s9, (#0x10, a5) +lw s9, (#0x20, a5) +lw s9, (#0x40, a5) +lw s9, (#0x80, a5) +lw s9, (#0x100, a5) +lw s9, (#0x200, a5) +lw s9, (#0x400, a5) +lw s9, (#0x7ff, a5) +lw s9, (#0xfffff801, s4) +lw s9, (#0xfffffc00, s4) +lw s9, (#0xfffffe00, s4) +lw s9, (#0xffffff00, s4) +lw s9, (#0xffffff80, s4) +lw s9, (#0xffffffc0, s4) +lw s9, (#0xffffffe0, s4) +lw s9, (#0xfffffff0, s4) +lw s9, (#0xfffffff8, s4) +lw s9, (#0xfffffffc, s4) +lw s9, (#0xfffffffe, s4) +lw s9, (#0xffffffff, s4) +lw s9, (#0, s4) +lw s9, (#1, s4) +lw s9, (#2, s4) +lw s9, (#4, s4) +lw s9, (#8, s4) +lw s9, (#0x10, s4) +lw s9, (#0x20, s4) +lw s9, (#0x40, s4) +lw s9, (#0x80, s4) +lw s9, (#0x100, s4) +lw s9, (#0x200, s4) +lw s9, (#0x400, s4) +lw s9, (#0x7ff, s4) +lw s9, (#0xfffff801, s9) +lw s9, (#0xfffffc00, s9) +lw s9, (#0xfffffe00, s9) +lw s9, (#0xffffff00, s9) +lw s9, (#0xffffff80, s9) +lw s9, (#0xffffffc0, s9) +lw s9, (#0xffffffe0, s9) +lw s9, (#0xfffffff0, s9) +lw s9, (#0xfffffff8, s9) +lw s9, (#0xfffffffc, s9) +lw s9, (#0xfffffffe, s9) +lw s9, (#0xffffffff, s9) +lw s9, (#0, s9) +lw s9, (#1, s9) +lw s9, (#2, s9) +lw s9, (#4, s9) +lw s9, (#8, s9) +lw s9, (#0x10, s9) +lw s9, (#0x20, s9) +lw s9, (#0x40, s9) +lw s9, (#0x80, s9) +lw s9, (#0x100, s9) +lw s9, (#0x200, s9) +lw s9, (#0x400, s9) +lw s9, (#0x7ff, s9) +lw s9, (#0xfffff801, t6) +lw s9, (#0xfffffc00, t6) +lw s9, (#0xfffffe00, t6) +lw s9, (#0xffffff00, t6) +lw s9, (#0xffffff80, t6) +lw s9, (#0xffffffc0, t6) +lw s9, (#0xffffffe0, t6) +lw s9, (#0xfffffff0, t6) +lw s9, (#0xfffffff8, t6) +lw s9, (#0xfffffffc, t6) +lw s9, (#0xfffffffe, t6) +lw s9, (#0xffffffff, t6) +lw s9, (#0, t6) +lw s9, (#1, t6) +lw s9, (#2, t6) +lw s9, (#4, t6) +lw s9, (#8, t6) +lw s9, (#0x10, t6) +lw s9, (#0x20, t6) +lw s9, (#0x40, t6) +lw s9, (#0x80, t6) +lw s9, (#0x100, t6) +lw s9, (#0x200, t6) +lw s9, (#0x400, t6) +lw s9, (#0x7ff, t6) +lw t6, (#0xfffff801, zero) +lw t6, (#0xfffffc00, zero) +lw t6, (#0xfffffe00, zero) +lw t6, (#0xffffff00, zero) +lw t6, (#0xffffff80, zero) +lw t6, (#0xffffffc0, zero) +lw t6, (#0xffffffe0, zero) +lw t6, (#0xfffffff0, zero) +lw t6, (#0xfffffff8, zero) +lw t6, (#0xfffffffc, zero) +lw t6, (#0xfffffffe, zero) +lw t6, (#0xffffffff, zero) +lw t6, (#0, zero) +lw t6, (#1, zero) +lw t6, (#2, zero) +lw t6, (#4, zero) +lw t6, (#8, zero) +lw t6, (#0x10, zero) +lw t6, (#0x20, zero) +lw t6, (#0x40, zero) +lw t6, (#0x80, zero) +lw t6, (#0x100, zero) +lw t6, (#0x200, zero) +lw t6, (#0x400, zero) +lw t6, (#0x7ff, zero) +lw t6, (#0xfffff801, ra) +lw t6, (#0xfffffc00, ra) +lw t6, (#0xfffffe00, ra) +lw t6, (#0xffffff00, ra) +lw t6, (#0xffffff80, ra) +lw t6, (#0xffffffc0, ra) +lw t6, (#0xffffffe0, ra) +lw t6, (#0xfffffff0, ra) +lw t6, (#0xfffffff8, ra) +lw t6, (#0xfffffffc, ra) +lw t6, (#0xfffffffe, ra) +lw t6, (#0xffffffff, ra) +lw t6, (#0, ra) +lw t6, (#1, ra) +lw t6, (#2, ra) +lw t6, (#4, ra) +lw t6, (#8, ra) +lw t6, (#0x10, ra) +lw t6, (#0x20, ra) +lw t6, (#0x40, ra) +lw t6, (#0x80, ra) +lw t6, (#0x100, ra) +lw t6, (#0x200, ra) +lw t6, (#0x400, ra) +lw t6, (#0x7ff, ra) +lw t6, (#0xfffff801, t0) +lw t6, (#0xfffffc00, t0) +lw t6, (#0xfffffe00, t0) +lw t6, (#0xffffff00, t0) +lw t6, (#0xffffff80, t0) +lw t6, (#0xffffffc0, t0) +lw t6, (#0xffffffe0, t0) +lw t6, (#0xfffffff0, t0) +lw t6, (#0xfffffff8, t0) +lw t6, (#0xfffffffc, t0) +lw t6, (#0xfffffffe, t0) +lw t6, (#0xffffffff, t0) +lw t6, (#0, t0) +lw t6, (#1, t0) +lw t6, (#2, t0) +lw t6, (#4, t0) +lw t6, (#8, t0) +lw t6, (#0x10, t0) +lw t6, (#0x20, t0) +lw t6, (#0x40, t0) +lw t6, (#0x80, t0) +lw t6, (#0x100, t0) +lw t6, (#0x200, t0) +lw t6, (#0x400, t0) +lw t6, (#0x7ff, t0) +lw t6, (#0xfffff801, a0) +lw t6, (#0xfffffc00, a0) +lw t6, (#0xfffffe00, a0) +lw t6, (#0xffffff00, a0) +lw t6, (#0xffffff80, a0) +lw t6, (#0xffffffc0, a0) +lw t6, (#0xffffffe0, a0) +lw t6, (#0xfffffff0, a0) +lw t6, (#0xfffffff8, a0) +lw t6, (#0xfffffffc, a0) +lw t6, (#0xfffffffe, a0) +lw t6, (#0xffffffff, a0) +lw t6, (#0, a0) +lw t6, (#1, a0) +lw t6, (#2, a0) +lw t6, (#4, a0) +lw t6, (#8, a0) +lw t6, (#0x10, a0) +lw t6, (#0x20, a0) +lw t6, (#0x40, a0) +lw t6, (#0x80, a0) +lw t6, (#0x100, a0) +lw t6, (#0x200, a0) +lw t6, (#0x400, a0) +lw t6, (#0x7ff, a0) +lw t6, (#0xfffff801, a5) +lw t6, (#0xfffffc00, a5) +lw t6, (#0xfffffe00, a5) +lw t6, (#0xffffff00, a5) +lw t6, (#0xffffff80, a5) +lw t6, (#0xffffffc0, a5) +lw t6, (#0xffffffe0, a5) +lw t6, (#0xfffffff0, a5) +lw t6, (#0xfffffff8, a5) +lw t6, (#0xfffffffc, a5) +lw t6, (#0xfffffffe, a5) +lw t6, (#0xffffffff, a5) +lw t6, (#0, a5) +lw t6, (#1, a5) +lw t6, (#2, a5) +lw t6, (#4, a5) +lw t6, (#8, a5) +lw t6, (#0x10, a5) +lw t6, (#0x20, a5) +lw t6, (#0x40, a5) +lw t6, (#0x80, a5) +lw t6, (#0x100, a5) +lw t6, (#0x200, a5) +lw t6, (#0x400, a5) +lw t6, (#0x7ff, a5) +lw t6, (#0xfffff801, s4) +lw t6, (#0xfffffc00, s4) +lw t6, (#0xfffffe00, s4) +lw t6, (#0xffffff00, s4) +lw t6, (#0xffffff80, s4) +lw t6, (#0xffffffc0, s4) +lw t6, (#0xffffffe0, s4) +lw t6, (#0xfffffff0, s4) +lw t6, (#0xfffffff8, s4) +lw t6, (#0xfffffffc, s4) +lw t6, (#0xfffffffe, s4) +lw t6, (#0xffffffff, s4) +lw t6, (#0, s4) +lw t6, (#1, s4) +lw t6, (#2, s4) +lw t6, (#4, s4) +lw t6, (#8, s4) +lw t6, (#0x10, s4) +lw t6, (#0x20, s4) +lw t6, (#0x40, s4) +lw t6, (#0x80, s4) +lw t6, (#0x100, s4) +lw t6, (#0x200, s4) +lw t6, (#0x400, s4) +lw t6, (#0x7ff, s4) +lw t6, (#0xfffff801, s9) +lw t6, (#0xfffffc00, s9) +lw t6, (#0xfffffe00, s9) +lw t6, (#0xffffff00, s9) +lw t6, (#0xffffff80, s9) +lw t6, (#0xffffffc0, s9) +lw t6, (#0xffffffe0, s9) +lw t6, (#0xfffffff0, s9) +lw t6, (#0xfffffff8, s9) +lw t6, (#0xfffffffc, s9) +lw t6, (#0xfffffffe, s9) +lw t6, (#0xffffffff, s9) +lw t6, (#0, s9) +lw t6, (#1, s9) +lw t6, (#2, s9) +lw t6, (#4, s9) +lw t6, (#8, s9) +lw t6, (#0x10, s9) +lw t6, (#0x20, s9) +lw t6, (#0x40, s9) +lw t6, (#0x80, s9) +lw t6, (#0x100, s9) +lw t6, (#0x200, s9) +lw t6, (#0x400, s9) +lw t6, (#0x7ff, s9) +lw t6, (#0xfffff801, t6) +lw t6, (#0xfffffc00, t6) +lw t6, (#0xfffffe00, t6) +lw t6, (#0xffffff00, t6) +lw t6, (#0xffffff80, t6) +lw t6, (#0xffffffc0, t6) +lw t6, (#0xffffffe0, t6) +lw t6, (#0xfffffff0, t6) +lw t6, (#0xfffffff8, t6) +lw t6, (#0xfffffffc, t6) +lw t6, (#0xfffffffe, t6) +lw t6, (#0xffffffff, t6) +lw t6, (#0, t6) +lw t6, (#1, t6) +lw t6, (#2, t6) +lw t6, (#4, t6) +lw t6, (#8, t6) +lw t6, (#0x10, t6) +lw t6, (#0x20, t6) +lw t6, (#0x40, t6) +lw t6, (#0x80, t6) +lw t6, (#0x100, t6) +lw t6, (#0x200, t6) +lw t6, (#0x400, t6) +lw t6, (#0x7ff, t6) diff --git a/tests/riscv/rv32i/or.asm b/tests/riscv/rv32i/or.asm new file mode 100644 index 0000000..e40e6d9 --- /dev/null +++ b/tests/riscv/rv32i/or.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +or zero, zero, zero +or zero, zero, ra +or zero, zero, t0 +or zero, zero, a0 +or zero, zero, a5 +or zero, zero, s4 +or zero, zero, s9 +or zero, zero, t6 +or zero, ra, zero +or zero, ra, ra +or zero, ra, t0 +or zero, ra, a0 +or zero, ra, a5 +or zero, ra, s4 +or zero, ra, s9 +or zero, ra, t6 +or zero, t0, zero +or zero, t0, ra +or zero, t0, t0 +or zero, t0, a0 +or zero, t0, a5 +or zero, t0, s4 +or zero, t0, s9 +or zero, t0, t6 +or zero, a0, zero +or zero, a0, ra +or zero, a0, t0 +or zero, a0, a0 +or zero, a0, a5 +or zero, a0, s4 +or zero, a0, s9 +or zero, a0, t6 +or zero, a5, zero +or zero, a5, ra +or zero, a5, t0 +or zero, a5, a0 +or zero, a5, a5 +or zero, a5, s4 +or zero, a5, s9 +or zero, a5, t6 +or zero, s4, zero +or zero, s4, ra +or zero, s4, t0 +or zero, s4, a0 +or zero, s4, a5 +or zero, s4, s4 +or zero, s4, s9 +or zero, s4, t6 +or zero, s9, zero +or zero, s9, ra +or zero, s9, t0 +or zero, s9, a0 +or zero, s9, a5 +or zero, s9, s4 +or zero, s9, s9 +or zero, s9, t6 +or zero, t6, zero +or zero, t6, ra +or zero, t6, t0 +or zero, t6, a0 +or zero, t6, a5 +or zero, t6, s4 +or zero, t6, s9 +or zero, t6, t6 +or ra, zero, zero +or ra, zero, ra +or ra, zero, t0 +or ra, zero, a0 +or ra, zero, a5 +or ra, zero, s4 +or ra, zero, s9 +or ra, zero, t6 +or ra, ra, zero +or ra, ra, ra +or ra, ra, t0 +or ra, ra, a0 +or ra, ra, a5 +or ra, ra, s4 +or ra, ra, s9 +or ra, ra, t6 +or ra, t0, zero +or ra, t0, ra +or ra, t0, t0 +or ra, t0, a0 +or ra, t0, a5 +or ra, t0, s4 +or ra, t0, s9 +or ra, t0, t6 +or ra, a0, zero +or ra, a0, ra +or ra, a0, t0 +or ra, a0, a0 +or ra, a0, a5 +or ra, a0, s4 +or ra, a0, s9 +or ra, a0, t6 +or ra, a5, zero +or ra, a5, ra +or ra, a5, t0 +or ra, a5, a0 +or ra, a5, a5 +or ra, a5, s4 +or ra, a5, s9 +or ra, a5, t6 +or ra, s4, zero +or ra, s4, ra +or ra, s4, t0 +or ra, s4, a0 +or ra, s4, a5 +or ra, s4, s4 +or ra, s4, s9 +or ra, s4, t6 +or ra, s9, zero +or ra, s9, ra +or ra, s9, t0 +or ra, s9, a0 +or ra, s9, a5 +or ra, s9, s4 +or ra, s9, s9 +or ra, s9, t6 +or ra, t6, zero +or ra, t6, ra +or ra, t6, t0 +or ra, t6, a0 +or ra, t6, a5 +or ra, t6, s4 +or ra, t6, s9 +or ra, t6, t6 +or t0, zero, zero +or t0, zero, ra +or t0, zero, t0 +or t0, zero, a0 +or t0, zero, a5 +or t0, zero, s4 +or t0, zero, s9 +or t0, zero, t6 +or t0, ra, zero +or t0, ra, ra +or t0, ra, t0 +or t0, ra, a0 +or t0, ra, a5 +or t0, ra, s4 +or t0, ra, s9 +or t0, ra, t6 +or t0, t0, zero +or t0, t0, ra +or t0, t0, t0 +or t0, t0, a0 +or t0, t0, a5 +or t0, t0, s4 +or t0, t0, s9 +or t0, t0, t6 +or t0, a0, zero +or t0, a0, ra +or t0, a0, t0 +or t0, a0, a0 +or t0, a0, a5 +or t0, a0, s4 +or t0, a0, s9 +or t0, a0, t6 +or t0, a5, zero +or t0, a5, ra +or t0, a5, t0 +or t0, a5, a0 +or t0, a5, a5 +or t0, a5, s4 +or t0, a5, s9 +or t0, a5, t6 +or t0, s4, zero +or t0, s4, ra +or t0, s4, t0 +or t0, s4, a0 +or t0, s4, a5 +or t0, s4, s4 +or t0, s4, s9 +or t0, s4, t6 +or t0, s9, zero +or t0, s9, ra +or t0, s9, t0 +or t0, s9, a0 +or t0, s9, a5 +or t0, s9, s4 +or t0, s9, s9 +or t0, s9, t6 +or t0, t6, zero +or t0, t6, ra +or t0, t6, t0 +or t0, t6, a0 +or t0, t6, a5 +or t0, t6, s4 +or t0, t6, s9 +or t0, t6, t6 +or a0, zero, zero +or a0, zero, ra +or a0, zero, t0 +or a0, zero, a0 +or a0, zero, a5 +or a0, zero, s4 +or a0, zero, s9 +or a0, zero, t6 +or a0, ra, zero +or a0, ra, ra +or a0, ra, t0 +or a0, ra, a0 +or a0, ra, a5 +or a0, ra, s4 +or a0, ra, s9 +or a0, ra, t6 +or a0, t0, zero +or a0, t0, ra +or a0, t0, t0 +or a0, t0, a0 +or a0, t0, a5 +or a0, t0, s4 +or a0, t0, s9 +or a0, t0, t6 +or a0, a0, zero +or a0, a0, ra +or a0, a0, t0 +or a0, a0, a0 +or a0, a0, a5 +or a0, a0, s4 +or a0, a0, s9 +or a0, a0, t6 +or a0, a5, zero +or a0, a5, ra +or a0, a5, t0 +or a0, a5, a0 +or a0, a5, a5 +or a0, a5, s4 +or a0, a5, s9 +or a0, a5, t6 +or a0, s4, zero +or a0, s4, ra +or a0, s4, t0 +or a0, s4, a0 +or a0, s4, a5 +or a0, s4, s4 +or a0, s4, s9 +or a0, s4, t6 +or a0, s9, zero +or a0, s9, ra +or a0, s9, t0 +or a0, s9, a0 +or a0, s9, a5 +or a0, s9, s4 +or a0, s9, s9 +or a0, s9, t6 +or a0, t6, zero +or a0, t6, ra +or a0, t6, t0 +or a0, t6, a0 +or a0, t6, a5 +or a0, t6, s4 +or a0, t6, s9 +or a0, t6, t6 +or a5, zero, zero +or a5, zero, ra +or a5, zero, t0 +or a5, zero, a0 +or a5, zero, a5 +or a5, zero, s4 +or a5, zero, s9 +or a5, zero, t6 +or a5, ra, zero +or a5, ra, ra +or a5, ra, t0 +or a5, ra, a0 +or a5, ra, a5 +or a5, ra, s4 +or a5, ra, s9 +or a5, ra, t6 +or a5, t0, zero +or a5, t0, ra +or a5, t0, t0 +or a5, t0, a0 +or a5, t0, a5 +or a5, t0, s4 +or a5, t0, s9 +or a5, t0, t6 +or a5, a0, zero +or a5, a0, ra +or a5, a0, t0 +or a5, a0, a0 +or a5, a0, a5 +or a5, a0, s4 +or a5, a0, s9 +or a5, a0, t6 +or a5, a5, zero +or a5, a5, ra +or a5, a5, t0 +or a5, a5, a0 +or a5, a5, a5 +or a5, a5, s4 +or a5, a5, s9 +or a5, a5, t6 +or a5, s4, zero +or a5, s4, ra +or a5, s4, t0 +or a5, s4, a0 +or a5, s4, a5 +or a5, s4, s4 +or a5, s4, s9 +or a5, s4, t6 +or a5, s9, zero +or a5, s9, ra +or a5, s9, t0 +or a5, s9, a0 +or a5, s9, a5 +or a5, s9, s4 +or a5, s9, s9 +or a5, s9, t6 +or a5, t6, zero +or a5, t6, ra +or a5, t6, t0 +or a5, t6, a0 +or a5, t6, a5 +or a5, t6, s4 +or a5, t6, s9 +or a5, t6, t6 +or s4, zero, zero +or s4, zero, ra +or s4, zero, t0 +or s4, zero, a0 +or s4, zero, a5 +or s4, zero, s4 +or s4, zero, s9 +or s4, zero, t6 +or s4, ra, zero +or s4, ra, ra +or s4, ra, t0 +or s4, ra, a0 +or s4, ra, a5 +or s4, ra, s4 +or s4, ra, s9 +or s4, ra, t6 +or s4, t0, zero +or s4, t0, ra +or s4, t0, t0 +or s4, t0, a0 +or s4, t0, a5 +or s4, t0, s4 +or s4, t0, s9 +or s4, t0, t6 +or s4, a0, zero +or s4, a0, ra +or s4, a0, t0 +or s4, a0, a0 +or s4, a0, a5 +or s4, a0, s4 +or s4, a0, s9 +or s4, a0, t6 +or s4, a5, zero +or s4, a5, ra +or s4, a5, t0 +or s4, a5, a0 +or s4, a5, a5 +or s4, a5, s4 +or s4, a5, s9 +or s4, a5, t6 +or s4, s4, zero +or s4, s4, ra +or s4, s4, t0 +or s4, s4, a0 +or s4, s4, a5 +or s4, s4, s4 +or s4, s4, s9 +or s4, s4, t6 +or s4, s9, zero +or s4, s9, ra +or s4, s9, t0 +or s4, s9, a0 +or s4, s9, a5 +or s4, s9, s4 +or s4, s9, s9 +or s4, s9, t6 +or s4, t6, zero +or s4, t6, ra +or s4, t6, t0 +or s4, t6, a0 +or s4, t6, a5 +or s4, t6, s4 +or s4, t6, s9 +or s4, t6, t6 +or s9, zero, zero +or s9, zero, ra +or s9, zero, t0 +or s9, zero, a0 +or s9, zero, a5 +or s9, zero, s4 +or s9, zero, s9 +or s9, zero, t6 +or s9, ra, zero +or s9, ra, ra +or s9, ra, t0 +or s9, ra, a0 +or s9, ra, a5 +or s9, ra, s4 +or s9, ra, s9 +or s9, ra, t6 +or s9, t0, zero +or s9, t0, ra +or s9, t0, t0 +or s9, t0, a0 +or s9, t0, a5 +or s9, t0, s4 +or s9, t0, s9 +or s9, t0, t6 +or s9, a0, zero +or s9, a0, ra +or s9, a0, t0 +or s9, a0, a0 +or s9, a0, a5 +or s9, a0, s4 +or s9, a0, s9 +or s9, a0, t6 +or s9, a5, zero +or s9, a5, ra +or s9, a5, t0 +or s9, a5, a0 +or s9, a5, a5 +or s9, a5, s4 +or s9, a5, s9 +or s9, a5, t6 +or s9, s4, zero +or s9, s4, ra +or s9, s4, t0 +or s9, s4, a0 +or s9, s4, a5 +or s9, s4, s4 +or s9, s4, s9 +or s9, s4, t6 +or s9, s9, zero +or s9, s9, ra +or s9, s9, t0 +or s9, s9, a0 +or s9, s9, a5 +or s9, s9, s4 +or s9, s9, s9 +or s9, s9, t6 +or s9, t6, zero +or s9, t6, ra +or s9, t6, t0 +or s9, t6, a0 +or s9, t6, a5 +or s9, t6, s4 +or s9, t6, s9 +or s9, t6, t6 +or t6, zero, zero +or t6, zero, ra +or t6, zero, t0 +or t6, zero, a0 +or t6, zero, a5 +or t6, zero, s4 +or t6, zero, s9 +or t6, zero, t6 +or t6, ra, zero +or t6, ra, ra +or t6, ra, t0 +or t6, ra, a0 +or t6, ra, a5 +or t6, ra, s4 +or t6, ra, s9 +or t6, ra, t6 +or t6, t0, zero +or t6, t0, ra +or t6, t0, t0 +or t6, t0, a0 +or t6, t0, a5 +or t6, t0, s4 +or t6, t0, s9 +or t6, t0, t6 +or t6, a0, zero +or t6, a0, ra +or t6, a0, t0 +or t6, a0, a0 +or t6, a0, a5 +or t6, a0, s4 +or t6, a0, s9 +or t6, a0, t6 +or t6, a5, zero +or t6, a5, ra +or t6, a5, t0 +or t6, a5, a0 +or t6, a5, a5 +or t6, a5, s4 +or t6, a5, s9 +or t6, a5, t6 +or t6, s4, zero +or t6, s4, ra +or t6, s4, t0 +or t6, s4, a0 +or t6, s4, a5 +or t6, s4, s4 +or t6, s4, s9 +or t6, s4, t6 +or t6, s9, zero +or t6, s9, ra +or t6, s9, t0 +or t6, s9, a0 +or t6, s9, a5 +or t6, s9, s4 +or t6, s9, s9 +or t6, s9, t6 +or t6, t6, zero +or t6, t6, ra +or t6, t6, t0 +or t6, t6, a0 +or t6, t6, a5 +or t6, t6, s4 +or t6, t6, s9 +or t6, t6, t6 + diff --git a/tests/riscv/rv32i/or.bin b/tests/riscv/rv32i/or.bin new file mode 100644 index 0000000000000000000000000000000000000000..b3e2f372609a59d448e2dc1b0e8e01399fb0d468 GIT binary patch literal 2048 zcmWmCVTYDY9ES1sA(1GNNc1803nUVW5{X1>xC~>MuaZb4N+c4!xWCYC7{eH5Eo)iJ zKEHi&a^L@RTpW(`@aWpL!=pR$N`A<(JU%!)`Y6W-hkN~Azt`{ed;MO&*YB_T|NOrz zujQwl$P@QZa^f4;eea&UkzaBuPu)MusW&&gzb|j)x17l{_b+nh%}wtg$UFHX=knbB ztDJjt%ln7&UjE93ym0>}7joPGNAf}b$)&t>|1OsYJN&z&JMv0?$gwpZ|B|wfvM5dE)*_PJH9K@7y2NIu9vxs;dg-vxib7w`pq z0bjru@CAGUU)5KA)mMGhSAEsjs~&&FU-4J`6@SHF@mKr-f50E`2mAqlz#s4j{1t!2 zU-4J`6@SHF@mKr-f50E`2mAqlz#s4j{1t!2U-4J`6@SHF@mKs6f5l(%SNs)!#b5E) z%Y(zszBl{c?0d8C&AvDL-t2p`@1}41rf>SDZ~CThSH1l=`)~H&?7!K6v;SuQ&Hgw0 z-|T<0|IPk4``_$;v;WQhoBcQYZ}#8pzuAAY|7QQq{x|#I?0>WW&Hgw0-|T<0|IPlJ z{Wtq>_TTKk*?+VDX8+CpoBcQYZ}#8pzuAAY|7QP<|HyCTH}V_#jr>M_BfpW~uJ8J; z@A|Iq`mXO+J^!8m&VT2>^WXXJ{CEB%|B?U5f8;;%ANh~`NB%qio&U~%=fCsc`S1L9 z{v-d9|HyyjKk^^>kNijeJO7>k&VT2>^WXXJ{CEC4|DFHNf9JpR-}&$Scm5N}9_#gZa{s;eq|H1#@fABx}AN&vg2mgcr z!T;cY@IUy^{APYLznS06Z{|1ioB5sksh|3(pZckv`gzs!Klz{hPyQ$WlmE&8zw}GL^y{j}zwj^o z3;)8u@Gtxef5Bhy7yJc(!C&wf{00BQzwj^o3;)8u@Gtxef5Bhy7yJc(!C&wf{00BQ gzwj^o3;)8u@Gtxe|H8lUFZ>Jt!oTn@{Oj`If6Dc2ZU6uP literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/or.disasm b/tests/riscv/rv32i/or.disasm new file mode 100644 index 0000000..4f1249e --- /dev/null +++ b/tests/riscv/rv32i/or.disasm @@ -0,0 +1,512 @@ +or zero, zero, zero +or zero, zero, ra +or zero, zero, t0 +or zero, zero, a0 +or zero, zero, a5 +or zero, zero, s4 +or zero, zero, s9 +or zero, zero, t6 +or zero, ra, zero +or zero, ra, ra +or zero, ra, t0 +or zero, ra, a0 +or zero, ra, a5 +or zero, ra, s4 +or zero, ra, s9 +or zero, ra, t6 +or zero, t0, zero +or zero, t0, ra +or zero, t0, t0 +or zero, t0, a0 +or zero, t0, a5 +or zero, t0, s4 +or zero, t0, s9 +or zero, t0, t6 +or zero, a0, zero +or zero, a0, ra +or zero, a0, t0 +or zero, a0, a0 +or zero, a0, a5 +or zero, a0, s4 +or zero, a0, s9 +or zero, a0, t6 +or zero, a5, zero +or zero, a5, ra +or zero, a5, t0 +or zero, a5, a0 +or zero, a5, a5 +or zero, a5, s4 +or zero, a5, s9 +or zero, a5, t6 +or zero, s4, zero +or zero, s4, ra +or zero, s4, t0 +or zero, s4, a0 +or zero, s4, a5 +or zero, s4, s4 +or zero, s4, s9 +or zero, s4, t6 +or zero, s9, zero +or zero, s9, ra +or zero, s9, t0 +or zero, s9, a0 +or zero, s9, a5 +or zero, s9, s4 +or zero, s9, s9 +or zero, s9, t6 +or zero, t6, zero +or zero, t6, ra +or zero, t6, t0 +or zero, t6, a0 +or zero, t6, a5 +or zero, t6, s4 +or zero, t6, s9 +or zero, t6, t6 +or ra, zero, zero +or ra, zero, ra +or ra, zero, t0 +or ra, zero, a0 +or ra, zero, a5 +or ra, zero, s4 +or ra, zero, s9 +or ra, zero, t6 +or ra, ra, zero +or ra, ra, ra +or ra, ra, t0 +or ra, ra, a0 +or ra, ra, a5 +or ra, ra, s4 +or ra, ra, s9 +or ra, ra, t6 +or ra, t0, zero +or ra, t0, ra +or ra, t0, t0 +or ra, t0, a0 +or ra, t0, a5 +or ra, t0, s4 +or ra, t0, s9 +or ra, t0, t6 +or ra, a0, zero +or ra, a0, ra +or ra, a0, t0 +or ra, a0, a0 +or ra, a0, a5 +or ra, a0, s4 +or ra, a0, s9 +or ra, a0, t6 +or ra, a5, zero +or ra, a5, ra +or ra, a5, t0 +or ra, a5, a0 +or ra, a5, a5 +or ra, a5, s4 +or ra, a5, s9 +or ra, a5, t6 +or ra, s4, zero +or ra, s4, ra +or ra, s4, t0 +or ra, s4, a0 +or ra, s4, a5 +or ra, s4, s4 +or ra, s4, s9 +or ra, s4, t6 +or ra, s9, zero +or ra, s9, ra +or ra, s9, t0 +or ra, s9, a0 +or ra, s9, a5 +or ra, s9, s4 +or ra, s9, s9 +or ra, s9, t6 +or ra, t6, zero +or ra, t6, ra +or ra, t6, t0 +or ra, t6, a0 +or ra, t6, a5 +or ra, t6, s4 +or ra, t6, s9 +or ra, t6, t6 +or t0, zero, zero +or t0, zero, ra +or t0, zero, t0 +or t0, zero, a0 +or t0, zero, a5 +or t0, zero, s4 +or t0, zero, s9 +or t0, zero, t6 +or t0, ra, zero +or t0, ra, ra +or t0, ra, t0 +or t0, ra, a0 +or t0, ra, a5 +or t0, ra, s4 +or t0, ra, s9 +or t0, ra, t6 +or t0, t0, zero +or t0, t0, ra +or t0, t0, t0 +or t0, t0, a0 +or t0, t0, a5 +or t0, t0, s4 +or t0, t0, s9 +or t0, t0, t6 +or t0, a0, zero +or t0, a0, ra +or t0, a0, t0 +or t0, a0, a0 +or t0, a0, a5 +or t0, a0, s4 +or t0, a0, s9 +or t0, a0, t6 +or t0, a5, zero +or t0, a5, ra +or t0, a5, t0 +or t0, a5, a0 +or t0, a5, a5 +or t0, a5, s4 +or t0, a5, s9 +or t0, a5, t6 +or t0, s4, zero +or t0, s4, ra +or t0, s4, t0 +or t0, s4, a0 +or t0, s4, a5 +or t0, s4, s4 +or t0, s4, s9 +or t0, s4, t6 +or t0, s9, zero +or t0, s9, ra +or t0, s9, t0 +or t0, s9, a0 +or t0, s9, a5 +or t0, s9, s4 +or t0, s9, s9 +or t0, s9, t6 +or t0, t6, zero +or t0, t6, ra +or t0, t6, t0 +or t0, t6, a0 +or t0, t6, a5 +or t0, t6, s4 +or t0, t6, s9 +or t0, t6, t6 +or a0, zero, zero +or a0, zero, ra +or a0, zero, t0 +or a0, zero, a0 +or a0, zero, a5 +or a0, zero, s4 +or a0, zero, s9 +or a0, zero, t6 +or a0, ra, zero +or a0, ra, ra +or a0, ra, t0 +or a0, ra, a0 +or a0, ra, a5 +or a0, ra, s4 +or a0, ra, s9 +or a0, ra, t6 +or a0, t0, zero +or a0, t0, ra +or a0, t0, t0 +or a0, t0, a0 +or a0, t0, a5 +or a0, t0, s4 +or a0, t0, s9 +or a0, t0, t6 +or a0, a0, zero +or a0, a0, ra +or a0, a0, t0 +or a0, a0, a0 +or a0, a0, a5 +or a0, a0, s4 +or a0, a0, s9 +or a0, a0, t6 +or a0, a5, zero +or a0, a5, ra +or a0, a5, t0 +or a0, a5, a0 +or a0, a5, a5 +or a0, a5, s4 +or a0, a5, s9 +or a0, a5, t6 +or a0, s4, zero +or a0, s4, ra +or a0, s4, t0 +or a0, s4, a0 +or a0, s4, a5 +or a0, s4, s4 +or a0, s4, s9 +or a0, s4, t6 +or a0, s9, zero +or a0, s9, ra +or a0, s9, t0 +or a0, s9, a0 +or a0, s9, a5 +or a0, s9, s4 +or a0, s9, s9 +or a0, s9, t6 +or a0, t6, zero +or a0, t6, ra +or a0, t6, t0 +or a0, t6, a0 +or a0, t6, a5 +or a0, t6, s4 +or a0, t6, s9 +or a0, t6, t6 +or a5, zero, zero +or a5, zero, ra +or a5, zero, t0 +or a5, zero, a0 +or a5, zero, a5 +or a5, zero, s4 +or a5, zero, s9 +or a5, zero, t6 +or a5, ra, zero +or a5, ra, ra +or a5, ra, t0 +or a5, ra, a0 +or a5, ra, a5 +or a5, ra, s4 +or a5, ra, s9 +or a5, ra, t6 +or a5, t0, zero +or a5, t0, ra +or a5, t0, t0 +or a5, t0, a0 +or a5, t0, a5 +or a5, t0, s4 +or a5, t0, s9 +or a5, t0, t6 +or a5, a0, zero +or a5, a0, ra +or a5, a0, t0 +or a5, a0, a0 +or a5, a0, a5 +or a5, a0, s4 +or a5, a0, s9 +or a5, a0, t6 +or a5, a5, zero +or a5, a5, ra +or a5, a5, t0 +or a5, a5, a0 +or a5, a5, a5 +or a5, a5, s4 +or a5, a5, s9 +or a5, a5, t6 +or a5, s4, zero +or a5, s4, ra +or a5, s4, t0 +or a5, s4, a0 +or a5, s4, a5 +or a5, s4, s4 +or a5, s4, s9 +or a5, s4, t6 +or a5, s9, zero +or a5, s9, ra +or a5, s9, t0 +or a5, s9, a0 +or a5, s9, a5 +or a5, s9, s4 +or a5, s9, s9 +or a5, s9, t6 +or a5, t6, zero +or a5, t6, ra +or a5, t6, t0 +or a5, t6, a0 +or a5, t6, a5 +or a5, t6, s4 +or a5, t6, s9 +or a5, t6, t6 +or s4, zero, zero +or s4, zero, ra +or s4, zero, t0 +or s4, zero, a0 +or s4, zero, a5 +or s4, zero, s4 +or s4, zero, s9 +or s4, zero, t6 +or s4, ra, zero +or s4, ra, ra +or s4, ra, t0 +or s4, ra, a0 +or s4, ra, a5 +or s4, ra, s4 +or s4, ra, s9 +or s4, ra, t6 +or s4, t0, zero +or s4, t0, ra +or s4, t0, t0 +or s4, t0, a0 +or s4, t0, a5 +or s4, t0, s4 +or s4, t0, s9 +or s4, t0, t6 +or s4, a0, zero +or s4, a0, ra +or s4, a0, t0 +or s4, a0, a0 +or s4, a0, a5 +or s4, a0, s4 +or s4, a0, s9 +or s4, a0, t6 +or s4, a5, zero +or s4, a5, ra +or s4, a5, t0 +or s4, a5, a0 +or s4, a5, a5 +or s4, a5, s4 +or s4, a5, s9 +or s4, a5, t6 +or s4, s4, zero +or s4, s4, ra +or s4, s4, t0 +or s4, s4, a0 +or s4, s4, a5 +or s4, s4, s4 +or s4, s4, s9 +or s4, s4, t6 +or s4, s9, zero +or s4, s9, ra +or s4, s9, t0 +or s4, s9, a0 +or s4, s9, a5 +or s4, s9, s4 +or s4, s9, s9 +or s4, s9, t6 +or s4, t6, zero +or s4, t6, ra +or s4, t6, t0 +or s4, t6, a0 +or s4, t6, a5 +or s4, t6, s4 +or s4, t6, s9 +or s4, t6, t6 +or s9, zero, zero +or s9, zero, ra +or s9, zero, t0 +or s9, zero, a0 +or s9, zero, a5 +or s9, zero, s4 +or s9, zero, s9 +or s9, zero, t6 +or s9, ra, zero +or s9, ra, ra +or s9, ra, t0 +or s9, ra, a0 +or s9, ra, a5 +or s9, ra, s4 +or s9, ra, s9 +or s9, ra, t6 +or s9, t0, zero +or s9, t0, ra +or s9, t0, t0 +or s9, t0, a0 +or s9, t0, a5 +or s9, t0, s4 +or s9, t0, s9 +or s9, t0, t6 +or s9, a0, zero +or s9, a0, ra +or s9, a0, t0 +or s9, a0, a0 +or s9, a0, a5 +or s9, a0, s4 +or s9, a0, s9 +or s9, a0, t6 +or s9, a5, zero +or s9, a5, ra +or s9, a5, t0 +or s9, a5, a0 +or s9, a5, a5 +or s9, a5, s4 +or s9, a5, s9 +or s9, a5, t6 +or s9, s4, zero +or s9, s4, ra +or s9, s4, t0 +or s9, s4, a0 +or s9, s4, a5 +or s9, s4, s4 +or s9, s4, s9 +or s9, s4, t6 +or s9, s9, zero +or s9, s9, ra +or s9, s9, t0 +or s9, s9, a0 +or s9, s9, a5 +or s9, s9, s4 +or s9, s9, s9 +or s9, s9, t6 +or s9, t6, zero +or s9, t6, ra +or s9, t6, t0 +or s9, t6, a0 +or s9, t6, a5 +or s9, t6, s4 +or s9, t6, s9 +or s9, t6, t6 +or t6, zero, zero +or t6, zero, ra +or t6, zero, t0 +or t6, zero, a0 +or t6, zero, a5 +or t6, zero, s4 +or t6, zero, s9 +or t6, zero, t6 +or t6, ra, zero +or t6, ra, ra +or t6, ra, t0 +or t6, ra, a0 +or t6, ra, a5 +or t6, ra, s4 +or t6, ra, s9 +or t6, ra, t6 +or t6, t0, zero +or t6, t0, ra +or t6, t0, t0 +or t6, t0, a0 +or t6, t0, a5 +or t6, t0, s4 +or t6, t0, s9 +or t6, t0, t6 +or t6, a0, zero +or t6, a0, ra +or t6, a0, t0 +or t6, a0, a0 +or t6, a0, a5 +or t6, a0, s4 +or t6, a0, s9 +or t6, a0, t6 +or t6, a5, zero +or t6, a5, ra +or t6, a5, t0 +or t6, a5, a0 +or t6, a5, a5 +or t6, a5, s4 +or t6, a5, s9 +or t6, a5, t6 +or t6, s4, zero +or t6, s4, ra +or t6, s4, t0 +or t6, s4, a0 +or t6, s4, a5 +or t6, s4, s4 +or t6, s4, s9 +or t6, s4, t6 +or t6, s9, zero +or t6, s9, ra +or t6, s9, t0 +or t6, s9, a0 +or t6, s9, a5 +or t6, s9, s4 +or t6, s9, s9 +or t6, s9, t6 +or t6, t6, zero +or t6, t6, ra +or t6, t6, t0 +or t6, t6, a0 +or t6, t6, a5 +or t6, t6, s4 +or t6, t6, s9 +or t6, t6, t6 diff --git a/tests/riscv/rv32i/ori.asm b/tests/riscv/rv32i/ori.asm new file mode 100644 index 0000000..0e17153 --- /dev/null +++ b/tests/riscv/rv32i/ori.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +ori zero, zero, #-2047 +ori zero, zero, #-1024 +ori zero, zero, #-512 +ori zero, zero, #-256 +ori zero, zero, #-128 +ori zero, zero, #-64 +ori zero, zero, #-32 +ori zero, zero, #-16 +ori zero, zero, #-8 +ori zero, zero, #-4 +ori zero, zero, #-2 +ori zero, zero, #-1 +ori zero, zero, #0 +ori zero, zero, #1 +ori zero, zero, #2 +ori zero, zero, #4 +ori zero, zero, #8 +ori zero, zero, #16 +ori zero, zero, #32 +ori zero, zero, #64 +ori zero, zero, #128 +ori zero, zero, #256 +ori zero, zero, #512 +ori zero, zero, #1024 +ori zero, zero, #2047 +ori zero, ra, #-2047 +ori zero, ra, #-1024 +ori zero, ra, #-512 +ori zero, ra, #-256 +ori zero, ra, #-128 +ori zero, ra, #-64 +ori zero, ra, #-32 +ori zero, ra, #-16 +ori zero, ra, #-8 +ori zero, ra, #-4 +ori zero, ra, #-2 +ori zero, ra, #-1 +ori zero, ra, #0 +ori zero, ra, #1 +ori zero, ra, #2 +ori zero, ra, #4 +ori zero, ra, #8 +ori zero, ra, #16 +ori zero, ra, #32 +ori zero, ra, #64 +ori zero, ra, #128 +ori zero, ra, #256 +ori zero, ra, #512 +ori zero, ra, #1024 +ori zero, ra, #2047 +ori zero, t0, #-2047 +ori zero, t0, #-1024 +ori zero, t0, #-512 +ori zero, t0, #-256 +ori zero, t0, #-128 +ori zero, t0, #-64 +ori zero, t0, #-32 +ori zero, t0, #-16 +ori zero, t0, #-8 +ori zero, t0, #-4 +ori zero, t0, #-2 +ori zero, t0, #-1 +ori zero, t0, #0 +ori zero, t0, #1 +ori zero, t0, #2 +ori zero, t0, #4 +ori zero, t0, #8 +ori zero, t0, #16 +ori zero, t0, #32 +ori zero, t0, #64 +ori zero, t0, #128 +ori zero, t0, #256 +ori zero, t0, #512 +ori zero, t0, #1024 +ori zero, t0, #2047 +ori zero, a0, #-2047 +ori zero, a0, #-1024 +ori zero, a0, #-512 +ori zero, a0, #-256 +ori zero, a0, #-128 +ori zero, a0, #-64 +ori zero, a0, #-32 +ori zero, a0, #-16 +ori zero, a0, #-8 +ori zero, a0, #-4 +ori zero, a0, #-2 +ori zero, a0, #-1 +ori zero, a0, #0 +ori zero, a0, #1 +ori zero, a0, #2 +ori zero, a0, #4 +ori zero, a0, #8 +ori zero, a0, #16 +ori zero, a0, #32 +ori zero, a0, #64 +ori zero, a0, #128 +ori zero, a0, #256 +ori zero, a0, #512 +ori zero, a0, #1024 +ori zero, a0, #2047 +ori zero, a5, #-2047 +ori zero, a5, #-1024 +ori zero, a5, #-512 +ori zero, a5, #-256 +ori zero, a5, #-128 +ori zero, a5, #-64 +ori zero, a5, #-32 +ori zero, a5, #-16 +ori zero, a5, #-8 +ori zero, a5, #-4 +ori zero, a5, #-2 +ori zero, a5, #-1 +ori zero, a5, #0 +ori zero, a5, #1 +ori zero, a5, #2 +ori zero, a5, #4 +ori zero, a5, #8 +ori zero, a5, #16 +ori zero, a5, #32 +ori zero, a5, #64 +ori zero, a5, #128 +ori zero, a5, #256 +ori zero, a5, #512 +ori zero, a5, #1024 +ori zero, a5, #2047 +ori zero, s4, #-2047 +ori zero, s4, #-1024 +ori zero, s4, #-512 +ori zero, s4, #-256 +ori zero, s4, #-128 +ori zero, s4, #-64 +ori zero, s4, #-32 +ori zero, s4, #-16 +ori zero, s4, #-8 +ori zero, s4, #-4 +ori zero, s4, #-2 +ori zero, s4, #-1 +ori zero, s4, #0 +ori zero, s4, #1 +ori zero, s4, #2 +ori zero, s4, #4 +ori zero, s4, #8 +ori zero, s4, #16 +ori zero, s4, #32 +ori zero, s4, #64 +ori zero, s4, #128 +ori zero, s4, #256 +ori zero, s4, #512 +ori zero, s4, #1024 +ori zero, s4, #2047 +ori zero, s9, #-2047 +ori zero, s9, #-1024 +ori zero, s9, #-512 +ori zero, s9, #-256 +ori zero, s9, #-128 +ori zero, s9, #-64 +ori zero, s9, #-32 +ori zero, s9, #-16 +ori zero, s9, #-8 +ori zero, s9, #-4 +ori zero, s9, #-2 +ori zero, s9, #-1 +ori zero, s9, #0 +ori zero, s9, #1 +ori zero, s9, #2 +ori zero, s9, #4 +ori zero, s9, #8 +ori zero, s9, #16 +ori zero, s9, #32 +ori zero, s9, #64 +ori zero, s9, #128 +ori zero, s9, #256 +ori zero, s9, #512 +ori zero, s9, #1024 +ori zero, s9, #2047 +ori zero, t6, #-2047 +ori zero, t6, #-1024 +ori zero, t6, #-512 +ori zero, t6, #-256 +ori zero, t6, #-128 +ori zero, t6, #-64 +ori zero, t6, #-32 +ori zero, t6, #-16 +ori zero, t6, #-8 +ori zero, t6, #-4 +ori zero, t6, #-2 +ori zero, t6, #-1 +ori zero, t6, #0 +ori zero, t6, #1 +ori zero, t6, #2 +ori zero, t6, #4 +ori zero, t6, #8 +ori zero, t6, #16 +ori zero, t6, #32 +ori zero, t6, #64 +ori zero, t6, #128 +ori zero, t6, #256 +ori zero, t6, #512 +ori zero, t6, #1024 +ori zero, t6, #2047 +ori ra, zero, #-2047 +ori ra, zero, #-1024 +ori ra, zero, #-512 +ori ra, zero, #-256 +ori ra, zero, #-128 +ori ra, zero, #-64 +ori ra, zero, #-32 +ori ra, zero, #-16 +ori ra, zero, #-8 +ori ra, zero, #-4 +ori ra, zero, #-2 +ori ra, zero, #-1 +ori ra, zero, #0 +ori ra, zero, #1 +ori ra, zero, #2 +ori ra, zero, #4 +ori ra, zero, #8 +ori ra, zero, #16 +ori ra, zero, #32 +ori ra, zero, #64 +ori ra, zero, #128 +ori ra, zero, #256 +ori ra, zero, #512 +ori ra, zero, #1024 +ori ra, zero, #2047 +ori ra, ra, #-2047 +ori ra, ra, #-1024 +ori ra, ra, #-512 +ori ra, ra, #-256 +ori ra, ra, #-128 +ori ra, ra, #-64 +ori ra, ra, #-32 +ori ra, ra, #-16 +ori ra, ra, #-8 +ori ra, ra, #-4 +ori ra, ra, #-2 +ori ra, ra, #-1 +ori ra, ra, #0 +ori ra, ra, #1 +ori ra, ra, #2 +ori ra, ra, #4 +ori ra, ra, #8 +ori ra, ra, #16 +ori ra, ra, #32 +ori ra, ra, #64 +ori ra, ra, #128 +ori ra, ra, #256 +ori ra, ra, #512 +ori ra, ra, #1024 +ori ra, ra, #2047 +ori ra, t0, #-2047 +ori ra, t0, #-1024 +ori ra, t0, #-512 +ori ra, t0, #-256 +ori ra, t0, #-128 +ori ra, t0, #-64 +ori ra, t0, #-32 +ori ra, t0, #-16 +ori ra, t0, #-8 +ori ra, t0, #-4 +ori ra, t0, #-2 +ori ra, t0, #-1 +ori ra, t0, #0 +ori ra, t0, #1 +ori ra, t0, #2 +ori ra, t0, #4 +ori ra, t0, #8 +ori ra, t0, #16 +ori ra, t0, #32 +ori ra, t0, #64 +ori ra, t0, #128 +ori ra, t0, #256 +ori ra, t0, #512 +ori ra, t0, #1024 +ori ra, t0, #2047 +ori ra, a0, #-2047 +ori ra, a0, #-1024 +ori ra, a0, #-512 +ori ra, a0, #-256 +ori ra, a0, #-128 +ori ra, a0, #-64 +ori ra, a0, #-32 +ori ra, a0, #-16 +ori ra, a0, #-8 +ori ra, a0, #-4 +ori ra, a0, #-2 +ori ra, a0, #-1 +ori ra, a0, #0 +ori ra, a0, #1 +ori ra, a0, #2 +ori ra, a0, #4 +ori ra, a0, #8 +ori ra, a0, #16 +ori ra, a0, #32 +ori ra, a0, #64 +ori ra, a0, #128 +ori ra, a0, #256 +ori ra, a0, #512 +ori ra, a0, #1024 +ori ra, a0, #2047 +ori ra, a5, #-2047 +ori ra, a5, #-1024 +ori ra, a5, #-512 +ori ra, a5, #-256 +ori ra, a5, #-128 +ori ra, a5, #-64 +ori ra, a5, #-32 +ori ra, a5, #-16 +ori ra, a5, #-8 +ori ra, a5, #-4 +ori ra, a5, #-2 +ori ra, a5, #-1 +ori ra, a5, #0 +ori ra, a5, #1 +ori ra, a5, #2 +ori ra, a5, #4 +ori ra, a5, #8 +ori ra, a5, #16 +ori ra, a5, #32 +ori ra, a5, #64 +ori ra, a5, #128 +ori ra, a5, #256 +ori ra, a5, #512 +ori ra, a5, #1024 +ori ra, a5, #2047 +ori ra, s4, #-2047 +ori ra, s4, #-1024 +ori ra, s4, #-512 +ori ra, s4, #-256 +ori ra, s4, #-128 +ori ra, s4, #-64 +ori ra, s4, #-32 +ori ra, s4, #-16 +ori ra, s4, #-8 +ori ra, s4, #-4 +ori ra, s4, #-2 +ori ra, s4, #-1 +ori ra, s4, #0 +ori ra, s4, #1 +ori ra, s4, #2 +ori ra, s4, #4 +ori ra, s4, #8 +ori ra, s4, #16 +ori ra, s4, #32 +ori ra, s4, #64 +ori ra, s4, #128 +ori ra, s4, #256 +ori ra, s4, #512 +ori ra, s4, #1024 +ori ra, s4, #2047 +ori ra, s9, #-2047 +ori ra, s9, #-1024 +ori ra, s9, #-512 +ori ra, s9, #-256 +ori ra, s9, #-128 +ori ra, s9, #-64 +ori ra, s9, #-32 +ori ra, s9, #-16 +ori ra, s9, #-8 +ori ra, s9, #-4 +ori ra, s9, #-2 +ori ra, s9, #-1 +ori ra, s9, #0 +ori ra, s9, #1 +ori ra, s9, #2 +ori ra, s9, #4 +ori ra, s9, #8 +ori ra, s9, #16 +ori ra, s9, #32 +ori ra, s9, #64 +ori ra, s9, #128 +ori ra, s9, #256 +ori ra, s9, #512 +ori ra, s9, #1024 +ori ra, s9, #2047 +ori ra, t6, #-2047 +ori ra, t6, #-1024 +ori ra, t6, #-512 +ori ra, t6, #-256 +ori ra, t6, #-128 +ori ra, t6, #-64 +ori ra, t6, #-32 +ori ra, t6, #-16 +ori ra, t6, #-8 +ori ra, t6, #-4 +ori ra, t6, #-2 +ori ra, t6, #-1 +ori ra, t6, #0 +ori ra, t6, #1 +ori ra, t6, #2 +ori ra, t6, #4 +ori ra, t6, #8 +ori ra, t6, #16 +ori ra, t6, #32 +ori ra, t6, #64 +ori ra, t6, #128 +ori ra, t6, #256 +ori ra, t6, #512 +ori ra, t6, #1024 +ori ra, t6, #2047 +ori t0, zero, #-2047 +ori t0, zero, #-1024 +ori t0, zero, #-512 +ori t0, zero, #-256 +ori t0, zero, #-128 +ori t0, zero, #-64 +ori t0, zero, #-32 +ori t0, zero, #-16 +ori t0, zero, #-8 +ori t0, zero, #-4 +ori t0, zero, #-2 +ori t0, zero, #-1 +ori t0, zero, #0 +ori t0, zero, #1 +ori t0, zero, #2 +ori t0, zero, #4 +ori t0, zero, #8 +ori t0, zero, #16 +ori t0, zero, #32 +ori t0, zero, #64 +ori t0, zero, #128 +ori t0, zero, #256 +ori t0, zero, #512 +ori t0, zero, #1024 +ori t0, zero, #2047 +ori t0, ra, #-2047 +ori t0, ra, #-1024 +ori t0, ra, #-512 +ori t0, ra, #-256 +ori t0, ra, #-128 +ori t0, ra, #-64 +ori t0, ra, #-32 +ori t0, ra, #-16 +ori t0, ra, #-8 +ori t0, ra, #-4 +ori t0, ra, #-2 +ori t0, ra, #-1 +ori t0, ra, #0 +ori t0, ra, #1 +ori t0, ra, #2 +ori t0, ra, #4 +ori t0, ra, #8 +ori t0, ra, #16 +ori t0, ra, #32 +ori t0, ra, #64 +ori t0, ra, #128 +ori t0, ra, #256 +ori t0, ra, #512 +ori t0, ra, #1024 +ori t0, ra, #2047 +ori t0, t0, #-2047 +ori t0, t0, #-1024 +ori t0, t0, #-512 +ori t0, t0, #-256 +ori t0, t0, #-128 +ori t0, t0, #-64 +ori t0, t0, #-32 +ori t0, t0, #-16 +ori t0, t0, #-8 +ori t0, t0, #-4 +ori t0, t0, #-2 +ori t0, t0, #-1 +ori t0, t0, #0 +ori t0, t0, #1 +ori t0, t0, #2 +ori t0, t0, #4 +ori t0, t0, #8 +ori t0, t0, #16 +ori t0, t0, #32 +ori t0, t0, #64 +ori t0, t0, #128 +ori t0, t0, #256 +ori t0, t0, #512 +ori t0, t0, #1024 +ori t0, t0, #2047 +ori t0, a0, #-2047 +ori t0, a0, #-1024 +ori t0, a0, #-512 +ori t0, a0, #-256 +ori t0, a0, #-128 +ori t0, a0, #-64 +ori t0, a0, #-32 +ori t0, a0, #-16 +ori t0, a0, #-8 +ori t0, a0, #-4 +ori t0, a0, #-2 +ori t0, a0, #-1 +ori t0, a0, #0 +ori t0, a0, #1 +ori t0, a0, #2 +ori t0, a0, #4 +ori t0, a0, #8 +ori t0, a0, #16 +ori t0, a0, #32 +ori t0, a0, #64 +ori t0, a0, #128 +ori t0, a0, #256 +ori t0, a0, #512 +ori t0, a0, #1024 +ori t0, a0, #2047 +ori t0, a5, #-2047 +ori t0, a5, #-1024 +ori t0, a5, #-512 +ori t0, a5, #-256 +ori t0, a5, #-128 +ori t0, a5, #-64 +ori t0, a5, #-32 +ori t0, a5, #-16 +ori t0, a5, #-8 +ori t0, a5, #-4 +ori t0, a5, #-2 +ori t0, a5, #-1 +ori t0, a5, #0 +ori t0, a5, #1 +ori t0, a5, #2 +ori t0, a5, #4 +ori t0, a5, #8 +ori t0, a5, #16 +ori t0, a5, #32 +ori t0, a5, #64 +ori t0, a5, #128 +ori t0, a5, #256 +ori t0, a5, #512 +ori t0, a5, #1024 +ori t0, a5, #2047 +ori t0, s4, #-2047 +ori t0, s4, #-1024 +ori t0, s4, #-512 +ori t0, s4, #-256 +ori t0, s4, #-128 +ori t0, s4, #-64 +ori t0, s4, #-32 +ori t0, s4, #-16 +ori t0, s4, #-8 +ori t0, s4, #-4 +ori t0, s4, #-2 +ori t0, s4, #-1 +ori t0, s4, #0 +ori t0, s4, #1 +ori t0, s4, #2 +ori t0, s4, #4 +ori t0, s4, #8 +ori t0, s4, #16 +ori t0, s4, #32 +ori t0, s4, #64 +ori t0, s4, #128 +ori t0, s4, #256 +ori t0, s4, #512 +ori t0, s4, #1024 +ori t0, s4, #2047 +ori t0, s9, #-2047 +ori t0, s9, #-1024 +ori t0, s9, #-512 +ori t0, s9, #-256 +ori t0, s9, #-128 +ori t0, s9, #-64 +ori t0, s9, #-32 +ori t0, s9, #-16 +ori t0, s9, #-8 +ori t0, s9, #-4 +ori t0, s9, #-2 +ori t0, s9, #-1 +ori t0, s9, #0 +ori t0, s9, #1 +ori t0, s9, #2 +ori t0, s9, #4 +ori t0, s9, #8 +ori t0, s9, #16 +ori t0, s9, #32 +ori t0, s9, #64 +ori t0, s9, #128 +ori t0, s9, #256 +ori t0, s9, #512 +ori t0, s9, #1024 +ori t0, s9, #2047 +ori t0, t6, #-2047 +ori t0, t6, #-1024 +ori t0, t6, #-512 +ori t0, t6, #-256 +ori t0, t6, #-128 +ori t0, t6, #-64 +ori t0, t6, #-32 +ori t0, t6, #-16 +ori t0, t6, #-8 +ori t0, t6, #-4 +ori t0, t6, #-2 +ori t0, t6, #-1 +ori t0, t6, #0 +ori t0, t6, #1 +ori t0, t6, #2 +ori t0, t6, #4 +ori t0, t6, #8 +ori t0, t6, #16 +ori t0, t6, #32 +ori t0, t6, #64 +ori t0, t6, #128 +ori t0, t6, #256 +ori t0, t6, #512 +ori t0, t6, #1024 +ori t0, t6, #2047 +ori a0, zero, #-2047 +ori a0, zero, #-1024 +ori a0, zero, #-512 +ori a0, zero, #-256 +ori a0, zero, #-128 +ori a0, zero, #-64 +ori a0, zero, #-32 +ori a0, zero, #-16 +ori a0, zero, #-8 +ori a0, zero, #-4 +ori a0, zero, #-2 +ori a0, zero, #-1 +ori a0, zero, #0 +ori a0, zero, #1 +ori a0, zero, #2 +ori a0, zero, #4 +ori a0, zero, #8 +ori a0, zero, #16 +ori a0, zero, #32 +ori a0, zero, #64 +ori a0, zero, #128 +ori a0, zero, #256 +ori a0, zero, #512 +ori a0, zero, #1024 +ori a0, zero, #2047 +ori a0, ra, #-2047 +ori a0, ra, #-1024 +ori a0, ra, #-512 +ori a0, ra, #-256 +ori a0, ra, #-128 +ori a0, ra, #-64 +ori a0, ra, #-32 +ori a0, ra, #-16 +ori a0, ra, #-8 +ori a0, ra, #-4 +ori a0, ra, #-2 +ori a0, ra, #-1 +ori a0, ra, #0 +ori a0, ra, #1 +ori a0, ra, #2 +ori a0, ra, #4 +ori a0, ra, #8 +ori a0, ra, #16 +ori a0, ra, #32 +ori a0, ra, #64 +ori a0, ra, #128 +ori a0, ra, #256 +ori a0, ra, #512 +ori a0, ra, #1024 +ori a0, ra, #2047 +ori a0, t0, #-2047 +ori a0, t0, #-1024 +ori a0, t0, #-512 +ori a0, t0, #-256 +ori a0, t0, #-128 +ori a0, t0, #-64 +ori a0, t0, #-32 +ori a0, t0, #-16 +ori a0, t0, #-8 +ori a0, t0, #-4 +ori a0, t0, #-2 +ori a0, t0, #-1 +ori a0, t0, #0 +ori a0, t0, #1 +ori a0, t0, #2 +ori a0, t0, #4 +ori a0, t0, #8 +ori a0, t0, #16 +ori a0, t0, #32 +ori a0, t0, #64 +ori a0, t0, #128 +ori a0, t0, #256 +ori a0, t0, #512 +ori a0, t0, #1024 +ori a0, t0, #2047 +ori a0, a0, #-2047 +ori a0, a0, #-1024 +ori a0, a0, #-512 +ori a0, a0, #-256 +ori a0, a0, #-128 +ori a0, a0, #-64 +ori a0, a0, #-32 +ori a0, a0, #-16 +ori a0, a0, #-8 +ori a0, a0, #-4 +ori a0, a0, #-2 +ori a0, a0, #-1 +ori a0, a0, #0 +ori a0, a0, #1 +ori a0, a0, #2 +ori a0, a0, #4 +ori a0, a0, #8 +ori a0, a0, #16 +ori a0, a0, #32 +ori a0, a0, #64 +ori a0, a0, #128 +ori a0, a0, #256 +ori a0, a0, #512 +ori a0, a0, #1024 +ori a0, a0, #2047 +ori a0, a5, #-2047 +ori a0, a5, #-1024 +ori a0, a5, #-512 +ori a0, a5, #-256 +ori a0, a5, #-128 +ori a0, a5, #-64 +ori a0, a5, #-32 +ori a0, a5, #-16 +ori a0, a5, #-8 +ori a0, a5, #-4 +ori a0, a5, #-2 +ori a0, a5, #-1 +ori a0, a5, #0 +ori a0, a5, #1 +ori a0, a5, #2 +ori a0, a5, #4 +ori a0, a5, #8 +ori a0, a5, #16 +ori a0, a5, #32 +ori a0, a5, #64 +ori a0, a5, #128 +ori a0, a5, #256 +ori a0, a5, #512 +ori a0, a5, #1024 +ori a0, a5, #2047 +ori a0, s4, #-2047 +ori a0, s4, #-1024 +ori a0, s4, #-512 +ori a0, s4, #-256 +ori a0, s4, #-128 +ori a0, s4, #-64 +ori a0, s4, #-32 +ori a0, s4, #-16 +ori a0, s4, #-8 +ori a0, s4, #-4 +ori a0, s4, #-2 +ori a0, s4, #-1 +ori a0, s4, #0 +ori a0, s4, #1 +ori a0, s4, #2 +ori a0, s4, #4 +ori a0, s4, #8 +ori a0, s4, #16 +ori a0, s4, #32 +ori a0, s4, #64 +ori a0, s4, #128 +ori a0, s4, #256 +ori a0, s4, #512 +ori a0, s4, #1024 +ori a0, s4, #2047 +ori a0, s9, #-2047 +ori a0, s9, #-1024 +ori a0, s9, #-512 +ori a0, s9, #-256 +ori a0, s9, #-128 +ori a0, s9, #-64 +ori a0, s9, #-32 +ori a0, s9, #-16 +ori a0, s9, #-8 +ori a0, s9, #-4 +ori a0, s9, #-2 +ori a0, s9, #-1 +ori a0, s9, #0 +ori a0, s9, #1 +ori a0, s9, #2 +ori a0, s9, #4 +ori a0, s9, #8 +ori a0, s9, #16 +ori a0, s9, #32 +ori a0, s9, #64 +ori a0, s9, #128 +ori a0, s9, #256 +ori a0, s9, #512 +ori a0, s9, #1024 +ori a0, s9, #2047 +ori a0, t6, #-2047 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#16 +ori t6, ra, #32 +ori t6, ra, #64 +ori t6, ra, #128 +ori t6, ra, #256 +ori t6, ra, #512 +ori t6, ra, #1024 +ori t6, ra, #2047 +ori t6, t0, #-2047 +ori t6, t0, #-1024 +ori t6, t0, #-512 +ori t6, t0, #-256 +ori t6, t0, #-128 +ori t6, t0, #-64 +ori t6, t0, #-32 +ori t6, t0, #-16 +ori t6, t0, #-8 +ori t6, t0, #-4 +ori t6, t0, #-2 +ori t6, t0, #-1 +ori t6, t0, #0 +ori t6, t0, #1 +ori t6, t0, #2 +ori t6, t0, #4 +ori t6, t0, #8 +ori t6, t0, #16 +ori t6, t0, #32 +ori t6, t0, #64 +ori t6, t0, #128 +ori t6, t0, #256 +ori t6, t0, #512 +ori t6, t0, #1024 +ori t6, t0, #2047 +ori t6, a0, #-2047 +ori t6, a0, #-1024 +ori t6, a0, #-512 +ori t6, a0, #-256 +ori t6, a0, #-128 +ori t6, a0, #-64 +ori t6, a0, #-32 +ori t6, a0, #-16 +ori t6, a0, #-8 +ori t6, a0, #-4 +ori t6, a0, #-2 +ori t6, a0, #-1 +ori t6, a0, #0 +ori t6, a0, #1 +ori t6, a0, #2 +ori t6, a0, #4 +ori t6, a0, #8 +ori t6, a0, #16 +ori t6, a0, #32 +ori t6, a0, #64 +ori t6, a0, #128 +ori t6, a0, #256 +ori t6, a0, #512 +ori t6, a0, #1024 +ori t6, a0, #2047 +ori t6, a5, #-2047 +ori t6, a5, #-1024 +ori t6, a5, #-512 +ori t6, a5, #-256 +ori t6, a5, #-128 +ori t6, a5, #-64 +ori t6, a5, #-32 +ori t6, a5, #-16 +ori t6, a5, #-8 +ori t6, a5, #-4 +ori t6, a5, #-2 +ori t6, a5, #-1 +ori t6, a5, #0 +ori t6, a5, #1 +ori t6, a5, #2 +ori t6, a5, #4 +ori t6, a5, #8 +ori t6, a5, #16 +ori t6, a5, #32 +ori t6, a5, #64 +ori t6, a5, #128 +ori t6, a5, #256 +ori t6, a5, #512 +ori t6, a5, #1024 +ori t6, a5, #2047 +ori t6, s4, #-2047 +ori t6, s4, #-1024 +ori t6, s4, #-512 +ori t6, s4, #-256 +ori t6, s4, #-128 +ori t6, s4, #-64 +ori t6, s4, #-32 +ori t6, s4, #-16 +ori t6, s4, #-8 +ori t6, s4, #-4 +ori t6, s4, #-2 +ori t6, s4, #-1 +ori t6, s4, #0 +ori t6, s4, #1 +ori t6, s4, #2 +ori t6, s4, #4 +ori t6, s4, #8 +ori t6, s4, #16 +ori t6, s4, #32 +ori t6, s4, #64 +ori t6, s4, #128 +ori t6, s4, #256 +ori t6, s4, #512 +ori t6, s4, #1024 +ori t6, s4, #2047 +ori t6, s9, #-2047 +ori t6, s9, #-1024 +ori t6, s9, #-512 +ori t6, s9, #-256 +ori t6, s9, #-128 +ori t6, s9, #-64 +ori t6, s9, #-32 +ori t6, s9, #-16 +ori t6, s9, #-8 +ori t6, s9, #-4 +ori t6, s9, #-2 +ori t6, s9, #-1 +ori t6, s9, #0 +ori t6, s9, #1 +ori t6, s9, #2 +ori t6, s9, #4 +ori t6, s9, #8 +ori t6, s9, #16 +ori t6, s9, #32 +ori t6, s9, #64 +ori t6, s9, #128 +ori t6, s9, #256 +ori t6, s9, #512 +ori t6, s9, #1024 +ori t6, s9, #2047 +ori t6, t6, #-2047 +ori t6, t6, #-1024 +ori t6, t6, #-512 +ori t6, t6, #-256 +ori t6, t6, #-128 +ori t6, t6, #-64 +ori t6, t6, #-32 +ori t6, t6, #-16 +ori t6, t6, #-8 +ori t6, t6, #-4 +ori t6, t6, #-2 +ori t6, t6, #-1 +ori t6, t6, #0 +ori t6, t6, #1 +ori t6, t6, #2 +ori t6, t6, #4 +ori t6, t6, #8 +ori t6, t6, #16 +ori t6, t6, #32 +ori t6, t6, #64 +ori t6, t6, #128 +ori t6, t6, #256 +ori t6, t6, #512 +ori t6, t6, #1024 +ori t6, t6, #2047 + diff --git a/tests/riscv/rv32i/ori.bin b/tests/riscv/rv32i/ori.bin new file mode 100644 index 0000000000000000000000000000000000000000..5a66f9db9a4b48a88e5961e9f435afa476a4a7dd GIT binary patch literal 6400 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Z(e$I~N7Ij{A5A}+el-1P`q3V*{{?X^Mb-cS literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/ori.disasm b/tests/riscv/rv32i/ori.disasm new file mode 100644 index 0000000..74729ca --- /dev/null +++ b/tests/riscv/rv32i/ori.disasm @@ -0,0 +1,1600 @@ +ori zero, zero, #0xfffff801 +ori zero, zero, #0xfffffc00 +ori zero, zero, #0xfffffe00 +ori zero, zero, #0xffffff00 +ori zero, zero, #0xffffff80 +ori zero, zero, #0xffffffc0 +ori zero, zero, #0xffffffe0 +ori zero, zero, #0xfffffff0 +ori zero, zero, #0xfffffff8 +ori zero, zero, #0xfffffffc +ori zero, zero, #0xfffffffe +ori zero, zero, #0xffffffff +ori zero, zero, #0 +ori zero, zero, #1 +ori zero, zero, #2 +ori zero, zero, #4 +ori zero, zero, #8 +ori zero, zero, #0x10 +ori zero, zero, #0x20 +ori zero, zero, #0x40 +ori zero, zero, #0x80 +ori zero, zero, #0x100 +ori zero, zero, #0x200 +ori zero, zero, #0x400 +ori zero, zero, #0x7ff +ori zero, ra, #0xfffff801 +ori zero, ra, #0xfffffc00 +ori zero, ra, #0xfffffe00 +ori zero, ra, #0xffffff00 +ori zero, ra, #0xffffff80 +ori zero, ra, #0xffffffc0 +ori zero, ra, #0xffffffe0 +ori zero, ra, #0xfffffff0 +ori zero, ra, #0xfffffff8 +ori zero, ra, #0xfffffffc +ori zero, ra, #0xfffffffe +ori zero, ra, #0xffffffff +ori zero, ra, #0 +ori zero, ra, #1 +ori zero, ra, #2 +ori zero, ra, #4 +ori zero, ra, #8 +ori zero, ra, #0x10 +ori zero, ra, #0x20 +ori zero, ra, #0x40 +ori zero, ra, #0x80 +ori zero, ra, #0x100 +ori zero, ra, #0x200 +ori zero, ra, #0x400 +ori zero, ra, #0x7ff +ori zero, t0, #0xfffff801 +ori zero, t0, #0xfffffc00 +ori zero, t0, #0xfffffe00 +ori zero, t0, #0xffffff00 +ori zero, t0, #0xffffff80 +ori zero, t0, #0xffffffc0 +ori zero, t0, #0xffffffe0 +ori zero, t0, #0xfffffff0 +ori zero, t0, #0xfffffff8 +ori zero, t0, #0xfffffffc +ori zero, t0, #0xfffffffe +ori zero, t0, #0xffffffff +ori zero, t0, #0 +ori zero, t0, #1 +ori zero, t0, #2 +ori zero, t0, #4 +ori zero, t0, #8 +ori zero, t0, #0x10 +ori zero, t0, #0x20 +ori zero, t0, #0x40 +ori zero, t0, #0x80 +ori zero, t0, #0x100 +ori zero, t0, #0x200 +ori zero, t0, #0x400 +ori zero, t0, #0x7ff +ori zero, a0, #0xfffff801 +ori zero, a0, #0xfffffc00 +ori zero, a0, #0xfffffe00 +ori zero, a0, #0xffffff00 +ori zero, a0, #0xffffff80 +ori zero, a0, #0xffffffc0 +ori zero, a0, #0xffffffe0 +ori zero, a0, #0xfffffff0 +ori zero, a0, #0xfffffff8 +ori zero, a0, #0xfffffffc +ori zero, a0, #0xfffffffe +ori zero, a0, #0xffffffff +ori zero, a0, #0 +ori zero, a0, #1 +ori zero, a0, #2 +ori zero, a0, #4 +ori zero, a0, #8 +ori zero, a0, #0x10 +ori zero, a0, #0x20 +ori zero, a0, #0x40 +ori zero, a0, #0x80 +ori zero, a0, #0x100 +ori zero, a0, #0x200 +ori zero, a0, #0x400 +ori zero, a0, #0x7ff +ori zero, a5, #0xfffff801 +ori zero, a5, #0xfffffc00 +ori zero, a5, #0xfffffe00 +ori zero, a5, #0xffffff00 +ori zero, a5, #0xffffff80 +ori zero, a5, #0xffffffc0 +ori zero, a5, #0xffffffe0 +ori zero, a5, #0xfffffff0 +ori zero, a5, #0xfffffff8 +ori zero, a5, #0xfffffffc +ori zero, a5, #0xfffffffe +ori zero, a5, #0xffffffff +ori zero, a5, #0 +ori zero, a5, #1 +ori zero, a5, #2 +ori zero, a5, #4 +ori zero, a5, #8 +ori zero, a5, #0x10 +ori zero, a5, #0x20 +ori zero, a5, #0x40 +ori zero, a5, #0x80 +ori zero, a5, #0x100 +ori zero, a5, #0x200 +ori zero, a5, #0x400 +ori zero, a5, #0x7ff +ori zero, s4, #0xfffff801 +ori zero, s4, #0xfffffc00 +ori zero, s4, #0xfffffe00 +ori zero, s4, #0xffffff00 +ori zero, s4, #0xffffff80 +ori zero, s4, #0xffffffc0 +ori zero, s4, #0xffffffe0 +ori zero, s4, #0xfffffff0 +ori zero, s4, #0xfffffff8 +ori zero, s4, #0xfffffffc +ori zero, s4, #0xfffffffe +ori zero, s4, #0xffffffff +ori zero, s4, #0 +ori zero, s4, #1 +ori zero, s4, #2 +ori zero, s4, #4 +ori zero, s4, #8 +ori zero, s4, #0x10 +ori zero, s4, #0x20 +ori zero, s4, #0x40 +ori zero, s4, #0x80 +ori zero, s4, #0x100 +ori zero, s4, #0x200 +ori zero, s4, #0x400 +ori zero, s4, #0x7ff +ori zero, s9, #0xfffff801 +ori zero, s9, #0xfffffc00 +ori zero, s9, #0xfffffe00 +ori zero, s9, #0xffffff00 +ori zero, s9, #0xffffff80 +ori zero, s9, #0xffffffc0 +ori zero, s9, #0xffffffe0 +ori zero, s9, #0xfffffff0 +ori zero, s9, #0xfffffff8 +ori zero, s9, #0xfffffffc +ori zero, s9, #0xfffffffe +ori zero, s9, #0xffffffff +ori zero, s9, #0 +ori zero, s9, #1 +ori zero, s9, #2 +ori zero, s9, #4 +ori zero, s9, #8 +ori zero, s9, #0x10 +ori zero, s9, #0x20 +ori zero, s9, #0x40 +ori zero, s9, #0x80 +ori zero, s9, #0x100 +ori zero, s9, #0x200 +ori zero, s9, #0x400 +ori zero, s9, #0x7ff +ori zero, t6, #0xfffff801 +ori zero, t6, #0xfffffc00 +ori zero, t6, #0xfffffe00 +ori zero, t6, #0xffffff00 +ori zero, t6, #0xffffff80 +ori zero, t6, #0xffffffc0 +ori zero, t6, #0xffffffe0 +ori zero, t6, #0xfffffff0 +ori zero, t6, #0xfffffff8 +ori zero, t6, #0xfffffffc +ori zero, t6, #0xfffffffe +ori zero, t6, #0xffffffff +ori zero, t6, #0 +ori zero, t6, #1 +ori zero, t6, #2 +ori zero, t6, #4 +ori zero, t6, #8 +ori zero, t6, #0x10 +ori zero, t6, #0x20 +ori zero, t6, #0x40 +ori zero, t6, #0x80 +ori zero, t6, #0x100 +ori zero, t6, #0x200 +ori zero, t6, #0x400 +ori zero, t6, #0x7ff +ori ra, zero, #0xfffff801 +ori ra, zero, #0xfffffc00 +ori ra, zero, #0xfffffe00 +ori ra, zero, #0xffffff00 +ori ra, zero, #0xffffff80 +ori ra, zero, #0xffffffc0 +ori ra, zero, #0xffffffe0 +ori ra, zero, #0xfffffff0 +ori ra, zero, #0xfffffff8 +ori ra, zero, #0xfffffffc +ori ra, zero, #0xfffffffe +ori ra, zero, #0xffffffff +ori ra, zero, #0 +ori ra, zero, #1 +ori ra, zero, #2 +ori ra, zero, #4 +ori ra, zero, #8 +ori ra, zero, #0x10 +ori ra, zero, #0x20 +ori ra, zero, #0x40 +ori ra, zero, #0x80 +ori ra, zero, #0x100 +ori ra, zero, #0x200 +ori ra, zero, #0x400 +ori ra, zero, #0x7ff +ori ra, ra, #0xfffff801 +ori ra, ra, #0xfffffc00 +ori ra, ra, #0xfffffe00 +ori ra, ra, #0xffffff00 +ori ra, ra, #0xffffff80 +ori ra, ra, #0xffffffc0 +ori ra, ra, #0xffffffe0 +ori ra, ra, #0xfffffff0 +ori ra, ra, #0xfffffff8 +ori ra, ra, #0xfffffffc +ori ra, ra, #0xfffffffe +ori ra, ra, #0xffffffff +ori ra, ra, #0 +ori ra, ra, #1 +ori ra, ra, #2 +ori ra, ra, #4 +ori ra, ra, #8 +ori ra, ra, #0x10 +ori ra, ra, #0x20 +ori ra, ra, #0x40 +ori ra, ra, #0x80 +ori ra, ra, #0x100 +ori ra, ra, #0x200 +ori ra, ra, #0x400 +ori ra, ra, #0x7ff +ori ra, t0, #0xfffff801 +ori ra, t0, #0xfffffc00 +ori ra, t0, #0xfffffe00 +ori ra, t0, #0xffffff00 +ori ra, t0, #0xffffff80 +ori ra, t0, #0xffffffc0 +ori ra, t0, #0xffffffe0 +ori ra, t0, #0xfffffff0 +ori ra, t0, #0xfffffff8 +ori ra, t0, #0xfffffffc +ori ra, t0, #0xfffffffe +ori ra, t0, #0xffffffff +ori ra, t0, #0 +ori ra, t0, #1 +ori ra, t0, #2 +ori ra, t0, #4 +ori ra, t0, #8 +ori ra, t0, #0x10 +ori ra, t0, #0x20 +ori ra, t0, #0x40 +ori ra, t0, #0x80 +ori ra, t0, #0x100 +ori ra, t0, #0x200 +ori ra, t0, #0x400 +ori ra, t0, #0x7ff +ori ra, a0, #0xfffff801 +ori ra, a0, #0xfffffc00 +ori ra, a0, #0xfffffe00 +ori ra, a0, #0xffffff00 +ori ra, a0, #0xffffff80 +ori ra, a0, #0xffffffc0 +ori ra, a0, #0xffffffe0 +ori ra, a0, #0xfffffff0 +ori ra, a0, #0xfffffff8 +ori ra, a0, #0xfffffffc +ori ra, a0, #0xfffffffe +ori ra, a0, #0xffffffff +ori ra, a0, #0 +ori ra, a0, #1 +ori ra, a0, #2 +ori ra, a0, #4 +ori ra, a0, #8 +ori ra, a0, #0x10 +ori ra, a0, #0x20 +ori ra, a0, #0x40 +ori ra, a0, #0x80 +ori ra, a0, #0x100 +ori ra, a0, #0x200 +ori ra, a0, #0x400 +ori ra, a0, #0x7ff +ori ra, a5, #0xfffff801 +ori ra, a5, #0xfffffc00 +ori ra, a5, #0xfffffe00 +ori ra, a5, #0xffffff00 +ori ra, a5, #0xffffff80 +ori ra, a5, #0xffffffc0 +ori ra, a5, #0xffffffe0 +ori ra, a5, #0xfffffff0 +ori ra, a5, #0xfffffff8 +ori ra, a5, #0xfffffffc +ori ra, a5, #0xfffffffe +ori ra, a5, #0xffffffff +ori ra, a5, #0 +ori ra, a5, #1 +ori ra, a5, #2 +ori ra, a5, #4 +ori ra, a5, #8 +ori ra, a5, #0x10 +ori ra, a5, #0x20 +ori ra, a5, #0x40 +ori ra, a5, #0x80 +ori ra, a5, #0x100 +ori ra, a5, #0x200 +ori ra, a5, #0x400 +ori ra, a5, #0x7ff +ori ra, s4, #0xfffff801 +ori ra, s4, #0xfffffc00 +ori ra, s4, #0xfffffe00 +ori ra, s4, #0xffffff00 +ori ra, s4, #0xffffff80 +ori ra, s4, #0xffffffc0 +ori ra, s4, #0xffffffe0 +ori ra, s4, #0xfffffff0 +ori ra, s4, #0xfffffff8 +ori ra, s4, #0xfffffffc +ori ra, s4, #0xfffffffe +ori ra, s4, #0xffffffff +ori ra, s4, #0 +ori ra, s4, #1 +ori ra, s4, #2 +ori ra, s4, #4 +ori ra, s4, #8 +ori ra, s4, #0x10 +ori ra, s4, #0x20 +ori ra, s4, #0x40 +ori ra, s4, #0x80 +ori ra, s4, #0x100 +ori ra, s4, #0x200 +ori ra, s4, #0x400 +ori ra, s4, #0x7ff +ori ra, s9, #0xfffff801 +ori ra, s9, #0xfffffc00 +ori ra, s9, #0xfffffe00 +ori ra, s9, #0xffffff00 +ori ra, s9, #0xffffff80 +ori ra, s9, #0xffffffc0 +ori ra, s9, #0xffffffe0 +ori ra, s9, #0xfffffff0 +ori ra, s9, #0xfffffff8 +ori ra, s9, #0xfffffffc +ori ra, s9, #0xfffffffe +ori ra, s9, #0xffffffff +ori ra, s9, #0 +ori ra, s9, #1 +ori ra, s9, #2 +ori ra, s9, #4 +ori ra, s9, #8 +ori ra, s9, #0x10 +ori ra, s9, #0x20 +ori ra, s9, #0x40 +ori ra, s9, #0x80 +ori ra, s9, #0x100 +ori ra, s9, #0x200 +ori ra, s9, #0x400 +ori ra, s9, #0x7ff +ori ra, t6, #0xfffff801 +ori ra, t6, #0xfffffc00 +ori ra, t6, #0xfffffe00 +ori ra, t6, #0xffffff00 +ori ra, t6, #0xffffff80 +ori ra, t6, #0xffffffc0 +ori ra, t6, #0xffffffe0 +ori ra, t6, #0xfffffff0 +ori ra, t6, #0xfffffff8 +ori ra, t6, #0xfffffffc +ori ra, t6, #0xfffffffe +ori ra, t6, #0xffffffff +ori ra, t6, #0 +ori ra, t6, #1 +ori ra, t6, #2 +ori ra, t6, #4 +ori ra, t6, #8 +ori ra, t6, #0x10 +ori ra, t6, #0x20 +ori ra, t6, #0x40 +ori ra, t6, #0x80 +ori ra, t6, #0x100 +ori ra, t6, #0x200 +ori ra, t6, #0x400 +ori ra, t6, #0x7ff +ori t0, zero, #0xfffff801 +ori t0, zero, #0xfffffc00 +ori t0, zero, #0xfffffe00 +ori t0, zero, #0xffffff00 +ori t0, zero, #0xffffff80 +ori t0, zero, #0xffffffc0 +ori t0, zero, #0xffffffe0 +ori t0, zero, #0xfffffff0 +ori t0, zero, #0xfffffff8 +ori t0, zero, #0xfffffffc +ori t0, zero, #0xfffffffe +ori t0, zero, #0xffffffff +ori t0, zero, #0 +ori t0, zero, #1 +ori t0, zero, #2 +ori t0, zero, #4 +ori t0, zero, #8 +ori t0, zero, #0x10 +ori t0, zero, #0x20 +ori t0, zero, #0x40 +ori t0, zero, #0x80 +ori t0, zero, #0x100 +ori t0, zero, #0x200 +ori t0, zero, #0x400 +ori t0, zero, #0x7ff +ori t0, ra, #0xfffff801 +ori t0, ra, #0xfffffc00 +ori t0, ra, #0xfffffe00 +ori t0, ra, #0xffffff00 +ori t0, ra, #0xffffff80 +ori t0, ra, #0xffffffc0 +ori t0, ra, #0xffffffe0 +ori t0, ra, #0xfffffff0 +ori t0, ra, #0xfffffff8 +ori t0, ra, #0xfffffffc +ori t0, ra, #0xfffffffe +ori t0, ra, #0xffffffff +ori t0, ra, #0 +ori t0, ra, #1 +ori t0, ra, #2 +ori t0, ra, #4 +ori t0, ra, #8 +ori t0, ra, #0x10 +ori t0, ra, #0x20 +ori t0, ra, #0x40 +ori t0, ra, #0x80 +ori t0, ra, #0x100 +ori t0, ra, #0x200 +ori t0, ra, #0x400 +ori t0, ra, #0x7ff +ori t0, t0, #0xfffff801 +ori t0, t0, #0xfffffc00 +ori t0, t0, #0xfffffe00 +ori t0, t0, #0xffffff00 +ori t0, t0, #0xffffff80 +ori t0, t0, #0xffffffc0 +ori t0, t0, #0xffffffe0 +ori t0, t0, #0xfffffff0 +ori t0, t0, #0xfffffff8 +ori t0, t0, #0xfffffffc +ori t0, t0, #0xfffffffe +ori t0, t0, #0xffffffff +ori t0, t0, #0 +ori t0, t0, #1 +ori t0, t0, #2 +ori t0, t0, #4 +ori t0, t0, #8 +ori t0, t0, #0x10 +ori t0, t0, #0x20 +ori t0, t0, #0x40 +ori t0, t0, #0x80 +ori t0, t0, #0x100 +ori t0, t0, #0x200 +ori t0, t0, #0x400 +ori t0, t0, #0x7ff +ori t0, a0, #0xfffff801 +ori t0, a0, #0xfffffc00 +ori t0, a0, #0xfffffe00 +ori t0, a0, #0xffffff00 +ori t0, a0, #0xffffff80 +ori t0, a0, #0xffffffc0 +ori t0, a0, #0xffffffe0 +ori t0, a0, #0xfffffff0 +ori t0, a0, #0xfffffff8 +ori t0, a0, #0xfffffffc +ori t0, a0, #0xfffffffe +ori t0, a0, #0xffffffff +ori t0, a0, #0 +ori t0, a0, #1 +ori t0, a0, #2 +ori t0, a0, #4 +ori t0, a0, #8 +ori t0, a0, #0x10 +ori t0, a0, #0x20 +ori t0, a0, #0x40 +ori t0, a0, #0x80 +ori t0, a0, #0x100 +ori t0, a0, #0x200 +ori t0, a0, #0x400 +ori t0, a0, #0x7ff +ori t0, a5, #0xfffff801 +ori t0, a5, #0xfffffc00 +ori t0, a5, #0xfffffe00 +ori t0, a5, #0xffffff00 +ori t0, a5, #0xffffff80 +ori t0, a5, #0xffffffc0 +ori t0, a5, #0xffffffe0 +ori t0, a5, #0xfffffff0 +ori t0, a5, #0xfffffff8 +ori t0, a5, #0xfffffffc +ori t0, a5, #0xfffffffe +ori t0, a5, #0xffffffff +ori t0, a5, #0 +ori t0, a5, #1 +ori t0, a5, #2 +ori t0, a5, #4 +ori t0, a5, #8 +ori t0, a5, #0x10 +ori t0, a5, #0x20 +ori t0, a5, #0x40 +ori t0, a5, #0x80 +ori t0, a5, #0x100 +ori t0, a5, #0x200 +ori t0, a5, #0x400 +ori t0, a5, #0x7ff +ori t0, s4, #0xfffff801 +ori t0, s4, #0xfffffc00 +ori t0, s4, #0xfffffe00 +ori t0, s4, #0xffffff00 +ori t0, s4, #0xffffff80 +ori t0, s4, #0xffffffc0 +ori t0, s4, #0xffffffe0 +ori t0, s4, #0xfffffff0 +ori t0, s4, #0xfffffff8 +ori t0, s4, #0xfffffffc +ori t0, s4, #0xfffffffe +ori t0, s4, #0xffffffff +ori t0, s4, #0 +ori t0, s4, #1 +ori t0, s4, #2 +ori t0, s4, #4 +ori t0, s4, #8 +ori t0, s4, #0x10 +ori t0, s4, #0x20 +ori t0, s4, #0x40 +ori t0, s4, #0x80 +ori t0, s4, #0x100 +ori t0, s4, #0x200 +ori t0, s4, #0x400 +ori t0, s4, #0x7ff +ori t0, s9, #0xfffff801 +ori t0, s9, #0xfffffc00 +ori t0, s9, #0xfffffe00 +ori t0, s9, #0xffffff00 +ori t0, s9, #0xffffff80 +ori t0, s9, #0xffffffc0 +ori t0, s9, #0xffffffe0 +ori t0, s9, #0xfffffff0 +ori t0, s9, #0xfffffff8 +ori t0, s9, #0xfffffffc +ori t0, s9, #0xfffffffe +ori t0, s9, #0xffffffff +ori t0, s9, #0 +ori t0, s9, #1 +ori t0, s9, #2 +ori t0, s9, #4 +ori t0, s9, #8 +ori t0, s9, #0x10 +ori t0, s9, #0x20 +ori t0, s9, #0x40 +ori t0, s9, #0x80 +ori t0, s9, #0x100 +ori t0, s9, #0x200 +ori t0, s9, #0x400 +ori t0, s9, #0x7ff +ori t0, t6, #0xfffff801 +ori t0, t6, #0xfffffc00 +ori t0, t6, #0xfffffe00 +ori t0, t6, #0xffffff00 +ori t0, t6, #0xffffff80 +ori t0, t6, #0xffffffc0 +ori t0, t6, #0xffffffe0 +ori t0, t6, #0xfffffff0 +ori t0, t6, #0xfffffff8 +ori t0, t6, #0xfffffffc +ori t0, t6, #0xfffffffe +ori t0, t6, #0xffffffff +ori t0, t6, #0 +ori t0, t6, #1 +ori t0, t6, #2 +ori t0, t6, #4 +ori t0, t6, #8 +ori t0, t6, #0x10 +ori t0, t6, #0x20 +ori t0, t6, #0x40 +ori t0, t6, #0x80 +ori t0, t6, #0x100 +ori t0, t6, #0x200 +ori t0, t6, #0x400 +ori t0, t6, #0x7ff +ori a0, zero, #0xfffff801 +ori a0, zero, #0xfffffc00 +ori a0, zero, #0xfffffe00 +ori a0, zero, #0xffffff00 +ori a0, zero, #0xffffff80 +ori a0, zero, #0xffffffc0 +ori a0, zero, #0xffffffe0 +ori a0, zero, #0xfffffff0 +ori a0, zero, #0xfffffff8 +ori a0, zero, #0xfffffffc +ori a0, zero, #0xfffffffe +ori a0, zero, #0xffffffff +ori a0, zero, #0 +ori a0, zero, #1 +ori a0, zero, #2 +ori a0, zero, #4 +ori a0, zero, #8 +ori a0, zero, #0x10 +ori a0, zero, #0x20 +ori a0, zero, #0x40 +ori a0, zero, #0x80 +ori a0, zero, #0x100 +ori a0, zero, #0x200 +ori a0, zero, #0x400 +ori a0, zero, #0x7ff +ori a0, ra, #0xfffff801 +ori a0, ra, #0xfffffc00 +ori a0, ra, #0xfffffe00 +ori a0, ra, #0xffffff00 +ori a0, ra, #0xffffff80 +ori a0, ra, #0xffffffc0 +ori a0, ra, #0xffffffe0 +ori a0, ra, #0xfffffff0 +ori a0, ra, #0xfffffff8 +ori a0, ra, #0xfffffffc +ori a0, ra, #0xfffffffe +ori a0, ra, #0xffffffff +ori a0, ra, #0 +ori a0, ra, #1 +ori a0, ra, #2 +ori a0, ra, #4 +ori a0, ra, #8 +ori a0, ra, #0x10 +ori a0, ra, #0x20 +ori a0, ra, #0x40 +ori a0, ra, #0x80 +ori a0, ra, #0x100 +ori a0, ra, #0x200 +ori a0, ra, #0x400 +ori a0, ra, #0x7ff +ori a0, t0, #0xfffff801 +ori a0, t0, #0xfffffc00 +ori a0, t0, #0xfffffe00 +ori a0, t0, #0xffffff00 +ori a0, t0, #0xffffff80 +ori a0, t0, #0xffffffc0 +ori a0, t0, #0xffffffe0 +ori a0, t0, #0xfffffff0 +ori a0, t0, #0xfffffff8 +ori a0, t0, #0xfffffffc +ori a0, t0, #0xfffffffe +ori a0, t0, #0xffffffff +ori a0, t0, #0 +ori a0, t0, #1 +ori a0, t0, #2 +ori a0, t0, #4 +ori a0, t0, #8 +ori a0, t0, #0x10 +ori a0, t0, #0x20 +ori a0, t0, #0x40 +ori a0, t0, #0x80 +ori a0, t0, #0x100 +ori a0, t0, #0x200 +ori a0, t0, #0x400 +ori a0, t0, #0x7ff +ori a0, a0, #0xfffff801 +ori a0, a0, #0xfffffc00 +ori a0, a0, #0xfffffe00 +ori a0, a0, #0xffffff00 +ori a0, a0, #0xffffff80 +ori a0, a0, #0xffffffc0 +ori a0, a0, #0xffffffe0 +ori a0, a0, #0xfffffff0 +ori a0, a0, #0xfffffff8 +ori a0, a0, #0xfffffffc +ori a0, a0, #0xfffffffe +ori a0, a0, #0xffffffff +ori a0, a0, #0 +ori a0, a0, #1 +ori a0, a0, #2 +ori a0, a0, #4 +ori a0, a0, #8 +ori a0, a0, #0x10 +ori a0, a0, #0x20 +ori a0, a0, #0x40 +ori a0, a0, #0x80 +ori a0, a0, #0x100 +ori a0, a0, #0x200 +ori a0, a0, #0x400 +ori a0, a0, #0x7ff +ori a0, a5, #0xfffff801 +ori a0, a5, #0xfffffc00 +ori a0, a5, #0xfffffe00 +ori a0, a5, #0xffffff00 +ori a0, a5, #0xffffff80 +ori a0, a5, #0xffffffc0 +ori a0, a5, #0xffffffe0 +ori a0, a5, #0xfffffff0 +ori a0, a5, #0xfffffff8 +ori a0, a5, #0xfffffffc +ori a0, a5, #0xfffffffe +ori a0, a5, #0xffffffff +ori a0, a5, #0 +ori a0, a5, #1 +ori a0, a5, #2 +ori a0, a5, #4 +ori a0, a5, #8 +ori a0, a5, #0x10 +ori a0, a5, #0x20 +ori a0, a5, #0x40 +ori a0, a5, #0x80 +ori a0, a5, #0x100 +ori a0, a5, #0x200 +ori a0, a5, #0x400 +ori a0, a5, #0x7ff +ori a0, s4, #0xfffff801 +ori a0, s4, #0xfffffc00 +ori a0, s4, #0xfffffe00 +ori a0, s4, #0xffffff00 +ori a0, s4, #0xffffff80 +ori a0, s4, #0xffffffc0 +ori a0, s4, #0xffffffe0 +ori a0, s4, #0xfffffff0 +ori a0, s4, #0xfffffff8 +ori a0, s4, #0xfffffffc +ori a0, s4, #0xfffffffe +ori a0, s4, #0xffffffff +ori a0, s4, #0 +ori a0, s4, #1 +ori a0, s4, #2 +ori a0, s4, #4 +ori a0, s4, #8 +ori a0, s4, #0x10 +ori a0, s4, #0x20 +ori a0, s4, #0x40 +ori a0, s4, #0x80 +ori a0, s4, #0x100 +ori a0, s4, #0x200 +ori a0, s4, #0x400 +ori a0, s4, #0x7ff +ori a0, s9, #0xfffff801 +ori a0, s9, #0xfffffc00 +ori a0, s9, #0xfffffe00 +ori a0, s9, #0xffffff00 +ori a0, s9, #0xffffff80 +ori a0, s9, #0xffffffc0 +ori a0, s9, #0xffffffe0 +ori a0, s9, #0xfffffff0 +ori a0, s9, #0xfffffff8 +ori a0, s9, #0xfffffffc +ori a0, s9, #0xfffffffe +ori a0, s9, #0xffffffff +ori a0, s9, #0 +ori a0, s9, #1 +ori a0, s9, #2 +ori a0, s9, #4 +ori a0, s9, #8 +ori a0, s9, #0x10 +ori a0, s9, #0x20 +ori a0, s9, #0x40 +ori a0, s9, #0x80 +ori a0, s9, #0x100 +ori a0, s9, #0x200 +ori a0, s9, #0x400 +ori a0, s9, #0x7ff +ori a0, t6, #0xfffff801 +ori a0, t6, #0xfffffc00 +ori a0, t6, #0xfffffe00 +ori a0, t6, #0xffffff00 +ori a0, t6, #0xffffff80 +ori a0, t6, #0xffffffc0 +ori a0, t6, #0xffffffe0 +ori a0, t6, #0xfffffff0 +ori a0, t6, #0xfffffff8 +ori a0, t6, #0xfffffffc +ori a0, t6, #0xfffffffe +ori a0, t6, #0xffffffff +ori a0, t6, #0 +ori a0, t6, #1 +ori a0, t6, #2 +ori a0, t6, #4 +ori a0, t6, #8 +ori a0, t6, #0x10 +ori a0, t6, #0x20 +ori a0, t6, #0x40 +ori a0, t6, #0x80 +ori a0, t6, #0x100 +ori a0, t6, #0x200 +ori a0, t6, #0x400 +ori a0, t6, #0x7ff +ori a5, zero, #0xfffff801 +ori a5, zero, #0xfffffc00 +ori a5, zero, #0xfffffe00 +ori a5, zero, #0xffffff00 +ori a5, zero, #0xffffff80 +ori a5, zero, #0xffffffc0 +ori a5, zero, #0xffffffe0 +ori a5, zero, #0xfffffff0 +ori a5, zero, #0xfffffff8 +ori a5, zero, #0xfffffffc +ori a5, zero, #0xfffffffe +ori a5, zero, #0xffffffff +ori a5, zero, #0 +ori a5, zero, #1 +ori a5, zero, #2 +ori a5, zero, #4 +ori a5, zero, #8 +ori a5, zero, #0x10 +ori a5, zero, #0x20 +ori a5, zero, #0x40 +ori a5, zero, #0x80 +ori a5, zero, #0x100 +ori a5, zero, #0x200 +ori a5, zero, #0x400 +ori a5, zero, #0x7ff +ori a5, ra, #0xfffff801 +ori a5, ra, #0xfffffc00 +ori a5, ra, #0xfffffe00 +ori a5, ra, #0xffffff00 +ori a5, ra, #0xffffff80 +ori a5, ra, #0xffffffc0 +ori a5, ra, #0xffffffe0 +ori a5, ra, #0xfffffff0 +ori a5, ra, #0xfffffff8 +ori a5, ra, #0xfffffffc +ori a5, ra, #0xfffffffe +ori a5, ra, #0xffffffff +ori a5, ra, #0 +ori a5, ra, #1 +ori a5, ra, #2 +ori a5, ra, #4 +ori a5, ra, #8 +ori a5, ra, #0x10 +ori a5, ra, #0x20 +ori a5, ra, #0x40 +ori a5, ra, #0x80 +ori a5, ra, #0x100 +ori a5, ra, #0x200 +ori a5, ra, #0x400 +ori a5, ra, #0x7ff +ori a5, t0, #0xfffff801 +ori a5, t0, #0xfffffc00 +ori a5, t0, #0xfffffe00 +ori a5, t0, #0xffffff00 +ori a5, t0, #0xffffff80 +ori a5, t0, #0xffffffc0 +ori a5, t0, #0xffffffe0 +ori a5, t0, #0xfffffff0 +ori a5, t0, #0xfffffff8 +ori a5, t0, #0xfffffffc +ori a5, t0, #0xfffffffe +ori a5, t0, #0xffffffff +ori a5, t0, #0 +ori a5, t0, #1 +ori a5, t0, #2 +ori a5, t0, #4 +ori a5, t0, #8 +ori a5, t0, #0x10 +ori a5, t0, #0x20 +ori a5, t0, #0x40 +ori a5, t0, #0x80 +ori a5, t0, #0x100 +ori a5, t0, #0x200 +ori a5, t0, #0x400 +ori a5, t0, #0x7ff +ori a5, a0, #0xfffff801 +ori a5, a0, #0xfffffc00 +ori a5, a0, #0xfffffe00 +ori a5, a0, #0xffffff00 +ori a5, a0, #0xffffff80 +ori a5, a0, #0xffffffc0 +ori a5, a0, #0xffffffe0 +ori a5, a0, #0xfffffff0 +ori a5, a0, #0xfffffff8 +ori a5, a0, #0xfffffffc +ori a5, a0, #0xfffffffe +ori a5, a0, #0xffffffff +ori a5, a0, #0 +ori a5, a0, #1 +ori a5, a0, #2 +ori a5, a0, #4 +ori a5, a0, #8 +ori a5, a0, #0x10 +ori a5, a0, #0x20 +ori a5, a0, #0x40 +ori a5, a0, #0x80 +ori a5, a0, #0x100 +ori a5, a0, #0x200 +ori a5, a0, #0x400 +ori a5, a0, #0x7ff +ori a5, a5, #0xfffff801 +ori a5, a5, #0xfffffc00 +ori a5, a5, #0xfffffe00 +ori a5, a5, #0xffffff00 +ori a5, a5, #0xffffff80 +ori a5, a5, #0xffffffc0 +ori a5, a5, #0xffffffe0 +ori a5, a5, #0xfffffff0 +ori a5, a5, #0xfffffff8 +ori a5, a5, #0xfffffffc +ori a5, a5, #0xfffffffe +ori a5, a5, #0xffffffff +ori a5, a5, #0 +ori a5, a5, #1 +ori a5, a5, #2 +ori a5, a5, #4 +ori a5, a5, #8 +ori a5, a5, #0x10 +ori a5, a5, #0x20 +ori a5, a5, #0x40 +ori a5, a5, #0x80 +ori a5, a5, #0x100 +ori a5, a5, #0x200 +ori a5, a5, #0x400 +ori a5, a5, #0x7ff +ori a5, s4, #0xfffff801 +ori a5, s4, #0xfffffc00 +ori a5, s4, #0xfffffe00 +ori a5, s4, #0xffffff00 +ori a5, s4, #0xffffff80 +ori a5, s4, #0xffffffc0 +ori a5, s4, #0xffffffe0 +ori a5, s4, #0xfffffff0 +ori a5, s4, #0xfffffff8 +ori a5, s4, #0xfffffffc +ori a5, s4, #0xfffffffe +ori a5, s4, #0xffffffff +ori a5, s4, #0 +ori a5, s4, #1 +ori a5, s4, #2 +ori a5, s4, #4 +ori a5, s4, #8 +ori a5, s4, #0x10 +ori a5, s4, #0x20 +ori a5, s4, #0x40 +ori a5, s4, #0x80 +ori a5, s4, #0x100 +ori a5, s4, #0x200 +ori a5, s4, #0x400 +ori a5, s4, #0x7ff +ori a5, s9, #0xfffff801 +ori a5, s9, #0xfffffc00 +ori a5, s9, #0xfffffe00 +ori a5, s9, #0xffffff00 +ori a5, s9, #0xffffff80 +ori a5, s9, #0xffffffc0 +ori a5, s9, #0xffffffe0 +ori a5, s9, #0xfffffff0 +ori a5, s9, #0xfffffff8 +ori a5, s9, #0xfffffffc +ori a5, s9, #0xfffffffe +ori a5, s9, #0xffffffff +ori a5, s9, #0 +ori a5, s9, #1 +ori a5, s9, #2 +ori a5, s9, #4 +ori a5, s9, #8 +ori a5, s9, #0x10 +ori a5, s9, #0x20 +ori a5, s9, #0x40 +ori a5, s9, #0x80 +ori a5, s9, #0x100 +ori a5, s9, #0x200 +ori a5, s9, #0x400 +ori a5, s9, #0x7ff +ori a5, t6, #0xfffff801 +ori a5, t6, #0xfffffc00 +ori a5, t6, #0xfffffe00 +ori a5, t6, #0xffffff00 +ori a5, t6, #0xffffff80 +ori a5, t6, #0xffffffc0 +ori a5, t6, #0xffffffe0 +ori a5, t6, #0xfffffff0 +ori a5, t6, #0xfffffff8 +ori a5, t6, #0xfffffffc +ori a5, t6, #0xfffffffe +ori a5, t6, #0xffffffff +ori a5, t6, #0 +ori a5, t6, #1 +ori a5, t6, #2 +ori a5, t6, #4 +ori a5, t6, #8 +ori a5, t6, #0x10 +ori a5, t6, #0x20 +ori a5, t6, #0x40 +ori a5, t6, #0x80 +ori a5, t6, #0x100 +ori a5, t6, #0x200 +ori a5, t6, #0x400 +ori a5, t6, #0x7ff +ori s4, zero, #0xfffff801 +ori s4, zero, #0xfffffc00 +ori s4, zero, #0xfffffe00 +ori s4, zero, #0xffffff00 +ori s4, zero, #0xffffff80 +ori s4, zero, #0xffffffc0 +ori s4, zero, #0xffffffe0 +ori s4, zero, #0xfffffff0 +ori s4, zero, #0xfffffff8 +ori s4, zero, #0xfffffffc +ori s4, zero, #0xfffffffe +ori s4, zero, #0xffffffff +ori s4, zero, #0 +ori s4, zero, #1 +ori s4, zero, #2 +ori s4, zero, #4 +ori s4, zero, #8 +ori s4, zero, #0x10 +ori s4, zero, #0x20 +ori s4, zero, #0x40 +ori s4, zero, #0x80 +ori s4, zero, #0x100 +ori s4, zero, #0x200 +ori s4, zero, #0x400 +ori s4, zero, #0x7ff +ori s4, ra, #0xfffff801 +ori s4, ra, #0xfffffc00 +ori s4, ra, #0xfffffe00 +ori s4, ra, #0xffffff00 +ori s4, ra, #0xffffff80 +ori s4, ra, #0xffffffc0 +ori s4, ra, #0xffffffe0 +ori s4, ra, #0xfffffff0 +ori s4, ra, #0xfffffff8 +ori s4, ra, #0xfffffffc +ori s4, ra, #0xfffffffe +ori s4, ra, #0xffffffff +ori s4, ra, #0 +ori s4, ra, #1 +ori s4, ra, #2 +ori s4, ra, #4 +ori s4, ra, #8 +ori s4, ra, #0x10 +ori s4, ra, #0x20 +ori s4, ra, #0x40 +ori s4, ra, #0x80 +ori s4, ra, #0x100 +ori s4, ra, #0x200 +ori s4, ra, #0x400 +ori s4, ra, #0x7ff +ori s4, t0, #0xfffff801 +ori s4, t0, #0xfffffc00 +ori s4, t0, #0xfffffe00 +ori s4, t0, #0xffffff00 +ori s4, t0, #0xffffff80 +ori s4, t0, #0xffffffc0 +ori s4, t0, #0xffffffe0 +ori s4, t0, #0xfffffff0 +ori s4, t0, #0xfffffff8 +ori s4, t0, #0xfffffffc +ori s4, t0, #0xfffffffe +ori s4, t0, #0xffffffff +ori s4, t0, #0 +ori s4, t0, #1 +ori s4, t0, #2 +ori s4, t0, #4 +ori s4, t0, #8 +ori s4, t0, #0x10 +ori s4, t0, #0x20 +ori s4, t0, #0x40 +ori s4, t0, #0x80 +ori s4, t0, #0x100 +ori s4, t0, #0x200 +ori s4, t0, #0x400 +ori s4, t0, #0x7ff +ori s4, a0, #0xfffff801 +ori s4, a0, #0xfffffc00 +ori s4, a0, #0xfffffe00 +ori s4, a0, #0xffffff00 +ori s4, a0, #0xffffff80 +ori s4, a0, #0xffffffc0 +ori s4, a0, #0xffffffe0 +ori s4, a0, #0xfffffff0 +ori s4, a0, #0xfffffff8 +ori s4, a0, #0xfffffffc +ori s4, a0, #0xfffffffe +ori s4, a0, #0xffffffff +ori s4, a0, #0 +ori s4, a0, #1 +ori s4, a0, #2 +ori s4, a0, #4 +ori s4, a0, #8 +ori s4, a0, #0x10 +ori s4, a0, #0x20 +ori s4, a0, #0x40 +ori s4, a0, #0x80 +ori s4, a0, #0x100 +ori s4, a0, #0x200 +ori s4, a0, #0x400 +ori s4, a0, #0x7ff +ori s4, a5, #0xfffff801 +ori s4, a5, #0xfffffc00 +ori s4, a5, #0xfffffe00 +ori s4, a5, #0xffffff00 +ori s4, a5, #0xffffff80 +ori s4, a5, #0xffffffc0 +ori s4, a5, #0xffffffe0 +ori s4, a5, #0xfffffff0 +ori s4, a5, #0xfffffff8 +ori s4, a5, #0xfffffffc +ori s4, a5, #0xfffffffe +ori s4, a5, #0xffffffff +ori s4, a5, #0 +ori s4, a5, #1 +ori s4, a5, #2 +ori s4, a5, #4 +ori s4, a5, #8 +ori s4, a5, #0x10 +ori s4, a5, #0x20 +ori s4, a5, #0x40 +ori s4, a5, #0x80 +ori s4, a5, #0x100 +ori s4, a5, #0x200 +ori s4, a5, #0x400 +ori s4, a5, #0x7ff +ori s4, s4, #0xfffff801 +ori s4, s4, #0xfffffc00 +ori s4, s4, #0xfffffe00 +ori s4, s4, #0xffffff00 +ori s4, s4, #0xffffff80 +ori s4, s4, #0xffffffc0 +ori s4, s4, #0xffffffe0 +ori s4, s4, #0xfffffff0 +ori s4, s4, #0xfffffff8 +ori s4, s4, #0xfffffffc +ori s4, s4, #0xfffffffe +ori s4, s4, #0xffffffff +ori s4, s4, #0 +ori s4, s4, #1 +ori s4, s4, #2 +ori s4, s4, #4 +ori s4, s4, #8 +ori s4, s4, #0x10 +ori s4, s4, #0x20 +ori s4, s4, #0x40 +ori s4, s4, #0x80 +ori s4, s4, #0x100 +ori s4, s4, #0x200 +ori s4, s4, #0x400 +ori s4, s4, #0x7ff +ori s4, s9, #0xfffff801 +ori s4, s9, #0xfffffc00 +ori s4, s9, #0xfffffe00 +ori s4, s9, #0xffffff00 +ori s4, s9, #0xffffff80 +ori s4, s9, #0xffffffc0 +ori s4, s9, #0xffffffe0 +ori s4, s9, #0xfffffff0 +ori s4, s9, #0xfffffff8 +ori s4, s9, #0xfffffffc +ori s4, s9, #0xfffffffe +ori s4, s9, #0xffffffff +ori s4, s9, #0 +ori s4, s9, #1 +ori s4, s9, #2 +ori s4, s9, #4 +ori s4, s9, #8 +ori s4, s9, #0x10 +ori s4, s9, #0x20 +ori s4, s9, #0x40 +ori s4, s9, #0x80 +ori s4, s9, #0x100 +ori s4, s9, #0x200 +ori s4, s9, #0x400 +ori s4, s9, #0x7ff +ori s4, t6, #0xfffff801 +ori s4, t6, #0xfffffc00 +ori s4, t6, #0xfffffe00 +ori s4, t6, #0xffffff00 +ori s4, t6, #0xffffff80 +ori s4, t6, #0xffffffc0 +ori s4, t6, #0xffffffe0 +ori s4, t6, #0xfffffff0 +ori s4, t6, #0xfffffff8 +ori s4, t6, #0xfffffffc +ori s4, t6, #0xfffffffe +ori s4, t6, #0xffffffff +ori s4, t6, #0 +ori s4, t6, #1 +ori s4, t6, #2 +ori s4, t6, #4 +ori s4, t6, #8 +ori s4, t6, #0x10 +ori s4, t6, #0x20 +ori s4, t6, #0x40 +ori s4, t6, #0x80 +ori s4, t6, #0x100 +ori s4, t6, #0x200 +ori s4, t6, #0x400 +ori s4, t6, #0x7ff +ori s9, zero, #0xfffff801 +ori s9, zero, #0xfffffc00 +ori s9, zero, #0xfffffe00 +ori s9, zero, #0xffffff00 +ori s9, zero, #0xffffff80 +ori s9, zero, #0xffffffc0 +ori s9, zero, #0xffffffe0 +ori s9, zero, #0xfffffff0 +ori s9, zero, #0xfffffff8 +ori s9, zero, #0xfffffffc +ori s9, zero, #0xfffffffe +ori s9, zero, #0xffffffff +ori s9, zero, #0 +ori s9, zero, #1 +ori s9, zero, #2 +ori s9, zero, #4 +ori s9, zero, #8 +ori s9, zero, #0x10 +ori s9, zero, #0x20 +ori s9, zero, #0x40 +ori s9, zero, #0x80 +ori s9, zero, #0x100 +ori s9, zero, #0x200 +ori s9, zero, #0x400 +ori s9, zero, #0x7ff +ori s9, ra, #0xfffff801 +ori s9, ra, #0xfffffc00 +ori s9, ra, #0xfffffe00 +ori s9, ra, #0xffffff00 +ori s9, ra, #0xffffff80 +ori s9, ra, #0xffffffc0 +ori s9, ra, #0xffffffe0 +ori s9, ra, #0xfffffff0 +ori s9, ra, #0xfffffff8 +ori s9, ra, #0xfffffffc +ori s9, ra, #0xfffffffe +ori s9, ra, #0xffffffff +ori s9, ra, #0 +ori s9, ra, #1 +ori s9, ra, #2 +ori s9, ra, #4 +ori s9, ra, #8 +ori s9, ra, #0x10 +ori s9, ra, #0x20 +ori s9, ra, #0x40 +ori s9, ra, #0x80 +ori s9, ra, #0x100 +ori s9, ra, #0x200 +ori s9, ra, #0x400 +ori s9, ra, #0x7ff +ori s9, t0, #0xfffff801 +ori s9, t0, #0xfffffc00 +ori s9, t0, #0xfffffe00 +ori s9, t0, #0xffffff00 +ori s9, t0, #0xffffff80 +ori s9, t0, #0xffffffc0 +ori s9, t0, #0xffffffe0 +ori s9, t0, #0xfffffff0 +ori s9, t0, #0xfffffff8 +ori s9, t0, #0xfffffffc +ori s9, t0, #0xfffffffe +ori s9, t0, #0xffffffff +ori s9, t0, #0 +ori s9, t0, #1 +ori s9, t0, #2 +ori s9, t0, #4 +ori s9, t0, #8 +ori s9, t0, #0x10 +ori s9, t0, #0x20 +ori s9, t0, #0x40 +ori s9, t0, #0x80 +ori s9, t0, #0x100 +ori s9, t0, #0x200 +ori s9, t0, #0x400 +ori s9, t0, #0x7ff +ori s9, a0, #0xfffff801 +ori s9, a0, #0xfffffc00 +ori s9, a0, #0xfffffe00 +ori s9, a0, #0xffffff00 +ori s9, a0, #0xffffff80 +ori s9, a0, #0xffffffc0 +ori s9, a0, #0xffffffe0 +ori s9, a0, #0xfffffff0 +ori s9, a0, #0xfffffff8 +ori s9, a0, #0xfffffffc +ori s9, a0, #0xfffffffe +ori s9, a0, #0xffffffff +ori s9, a0, #0 +ori s9, a0, #1 +ori s9, a0, #2 +ori s9, a0, #4 +ori s9, a0, #8 +ori s9, a0, #0x10 +ori s9, a0, #0x20 +ori s9, a0, #0x40 +ori s9, a0, #0x80 +ori s9, a0, #0x100 +ori s9, a0, #0x200 +ori s9, a0, #0x400 +ori s9, a0, #0x7ff +ori s9, a5, #0xfffff801 +ori s9, a5, #0xfffffc00 +ori s9, a5, #0xfffffe00 +ori s9, a5, #0xffffff00 +ori s9, a5, #0xffffff80 +ori s9, a5, #0xffffffc0 +ori s9, a5, #0xffffffe0 +ori s9, a5, #0xfffffff0 +ori s9, a5, #0xfffffff8 +ori s9, a5, #0xfffffffc +ori s9, a5, #0xfffffffe +ori s9, a5, #0xffffffff +ori s9, a5, #0 +ori s9, a5, #1 +ori s9, a5, #2 +ori s9, a5, #4 +ori s9, a5, #8 +ori s9, a5, #0x10 +ori s9, a5, #0x20 +ori s9, a5, #0x40 +ori s9, a5, #0x80 +ori s9, a5, #0x100 +ori s9, a5, #0x200 +ori s9, a5, #0x400 +ori s9, a5, #0x7ff +ori s9, s4, #0xfffff801 +ori s9, s4, #0xfffffc00 +ori s9, s4, #0xfffffe00 +ori s9, s4, #0xffffff00 +ori s9, s4, #0xffffff80 +ori s9, s4, #0xffffffc0 +ori s9, s4, #0xffffffe0 +ori s9, s4, #0xfffffff0 +ori s9, s4, #0xfffffff8 +ori s9, s4, #0xfffffffc +ori s9, s4, #0xfffffffe +ori s9, s4, #0xffffffff +ori s9, s4, #0 +ori s9, s4, #1 +ori s9, s4, #2 +ori s9, s4, #4 +ori s9, s4, #8 +ori s9, s4, #0x10 +ori s9, s4, #0x20 +ori s9, s4, #0x40 +ori s9, s4, #0x80 +ori s9, s4, #0x100 +ori s9, s4, #0x200 +ori s9, s4, #0x400 +ori s9, s4, #0x7ff +ori s9, s9, #0xfffff801 +ori s9, s9, #0xfffffc00 +ori s9, s9, #0xfffffe00 +ori s9, s9, #0xffffff00 +ori s9, s9, #0xffffff80 +ori s9, s9, #0xffffffc0 +ori s9, s9, #0xffffffe0 +ori s9, s9, #0xfffffff0 +ori s9, s9, #0xfffffff8 +ori s9, s9, #0xfffffffc +ori s9, s9, #0xfffffffe +ori s9, s9, #0xffffffff +ori s9, s9, #0 +ori s9, s9, #1 +ori s9, s9, #2 +ori s9, s9, #4 +ori s9, s9, #8 +ori s9, s9, #0x10 +ori s9, s9, #0x20 +ori s9, s9, #0x40 +ori s9, s9, #0x80 +ori s9, s9, #0x100 +ori s9, s9, #0x200 +ori s9, s9, #0x400 +ori s9, s9, #0x7ff +ori s9, t6, #0xfffff801 +ori s9, t6, #0xfffffc00 +ori s9, t6, #0xfffffe00 +ori s9, t6, #0xffffff00 +ori s9, t6, #0xffffff80 +ori s9, t6, #0xffffffc0 +ori s9, t6, #0xffffffe0 +ori s9, t6, #0xfffffff0 +ori s9, t6, #0xfffffff8 +ori s9, t6, #0xfffffffc +ori s9, t6, #0xfffffffe +ori s9, t6, #0xffffffff +ori s9, t6, #0 +ori s9, t6, #1 +ori s9, t6, #2 +ori s9, t6, #4 +ori s9, t6, #8 +ori s9, t6, #0x10 +ori s9, t6, #0x20 +ori s9, t6, #0x40 +ori s9, t6, #0x80 +ori s9, t6, #0x100 +ori s9, t6, #0x200 +ori s9, t6, #0x400 +ori s9, t6, #0x7ff +ori t6, zero, #0xfffff801 +ori t6, zero, #0xfffffc00 +ori t6, zero, #0xfffffe00 +ori t6, zero, #0xffffff00 +ori t6, zero, #0xffffff80 +ori t6, zero, #0xffffffc0 +ori t6, zero, #0xffffffe0 +ori t6, zero, #0xfffffff0 +ori t6, zero, #0xfffffff8 +ori t6, zero, #0xfffffffc +ori t6, zero, #0xfffffffe +ori t6, zero, #0xffffffff +ori t6, zero, #0 +ori t6, zero, #1 +ori t6, zero, #2 +ori t6, zero, #4 +ori t6, zero, #8 +ori t6, zero, #0x10 +ori t6, zero, #0x20 +ori t6, zero, #0x40 +ori t6, zero, #0x80 +ori t6, zero, #0x100 +ori t6, zero, #0x200 +ori t6, zero, #0x400 +ori t6, zero, #0x7ff +ori t6, ra, #0xfffff801 +ori t6, ra, #0xfffffc00 +ori t6, ra, #0xfffffe00 +ori t6, ra, #0xffffff00 +ori t6, ra, #0xffffff80 +ori t6, ra, #0xffffffc0 +ori t6, ra, #0xffffffe0 +ori t6, ra, #0xfffffff0 +ori t6, ra, #0xfffffff8 +ori t6, ra, #0xfffffffc +ori t6, ra, #0xfffffffe +ori t6, ra, #0xffffffff +ori t6, ra, #0 +ori t6, ra, #1 +ori t6, ra, #2 +ori t6, ra, #4 +ori t6, ra, #8 +ori t6, ra, #0x10 +ori t6, ra, #0x20 +ori t6, ra, #0x40 +ori t6, ra, #0x80 +ori t6, ra, #0x100 +ori t6, ra, #0x200 +ori t6, ra, #0x400 +ori t6, ra, #0x7ff +ori t6, t0, #0xfffff801 +ori t6, t0, #0xfffffc00 +ori t6, t0, #0xfffffe00 +ori t6, t0, #0xffffff00 +ori t6, t0, #0xffffff80 +ori t6, t0, #0xffffffc0 +ori t6, t0, #0xffffffe0 +ori t6, t0, #0xfffffff0 +ori t6, t0, #0xfffffff8 +ori t6, t0, #0xfffffffc +ori t6, t0, #0xfffffffe +ori t6, t0, #0xffffffff +ori t6, t0, #0 +ori t6, t0, #1 +ori t6, t0, #2 +ori t6, t0, #4 +ori t6, t0, #8 +ori t6, t0, #0x10 +ori t6, t0, #0x20 +ori t6, t0, #0x40 +ori t6, t0, #0x80 +ori t6, t0, #0x100 +ori t6, t0, #0x200 +ori t6, t0, #0x400 +ori t6, t0, #0x7ff +ori t6, a0, #0xfffff801 +ori t6, a0, #0xfffffc00 +ori t6, a0, #0xfffffe00 +ori t6, a0, #0xffffff00 +ori t6, a0, #0xffffff80 +ori t6, a0, #0xffffffc0 +ori t6, a0, #0xffffffe0 +ori t6, a0, #0xfffffff0 +ori t6, a0, #0xfffffff8 +ori t6, a0, #0xfffffffc +ori t6, a0, #0xfffffffe +ori t6, a0, #0xffffffff +ori t6, a0, #0 +ori t6, a0, #1 +ori t6, a0, #2 +ori t6, a0, #4 +ori t6, a0, #8 +ori t6, a0, #0x10 +ori t6, a0, #0x20 +ori t6, a0, #0x40 +ori t6, a0, #0x80 +ori t6, a0, #0x100 +ori t6, a0, #0x200 +ori t6, a0, #0x400 +ori t6, a0, #0x7ff +ori t6, a5, #0xfffff801 +ori t6, a5, #0xfffffc00 +ori t6, a5, #0xfffffe00 +ori t6, a5, #0xffffff00 +ori t6, a5, #0xffffff80 +ori t6, a5, #0xffffffc0 +ori t6, a5, #0xffffffe0 +ori t6, a5, #0xfffffff0 +ori t6, a5, #0xfffffff8 +ori t6, a5, #0xfffffffc +ori t6, a5, #0xfffffffe +ori t6, a5, #0xffffffff +ori t6, a5, #0 +ori t6, a5, #1 +ori t6, a5, #2 +ori t6, a5, #4 +ori t6, a5, #8 +ori t6, a5, #0x10 +ori t6, a5, #0x20 +ori t6, a5, #0x40 +ori t6, a5, #0x80 +ori t6, a5, #0x100 +ori t6, a5, #0x200 +ori t6, a5, #0x400 +ori t6, a5, #0x7ff +ori t6, s4, #0xfffff801 +ori t6, s4, #0xfffffc00 +ori t6, s4, #0xfffffe00 +ori t6, s4, #0xffffff00 +ori t6, s4, #0xffffff80 +ori t6, s4, #0xffffffc0 +ori t6, s4, #0xffffffe0 +ori t6, s4, #0xfffffff0 +ori t6, s4, #0xfffffff8 +ori t6, s4, #0xfffffffc +ori t6, s4, #0xfffffffe +ori t6, s4, #0xffffffff +ori t6, s4, #0 +ori t6, s4, #1 +ori t6, s4, #2 +ori t6, s4, #4 +ori t6, s4, #8 +ori t6, s4, #0x10 +ori t6, s4, #0x20 +ori t6, s4, #0x40 +ori t6, s4, #0x80 +ori t6, s4, #0x100 +ori t6, s4, #0x200 +ori t6, s4, #0x400 +ori t6, s4, #0x7ff +ori t6, s9, #0xfffff801 +ori t6, s9, #0xfffffc00 +ori t6, s9, #0xfffffe00 +ori t6, s9, #0xffffff00 +ori t6, s9, #0xffffff80 +ori t6, s9, #0xffffffc0 +ori t6, s9, #0xffffffe0 +ori t6, s9, #0xfffffff0 +ori t6, s9, #0xfffffff8 +ori t6, s9, #0xfffffffc +ori t6, s9, #0xfffffffe +ori t6, s9, #0xffffffff +ori t6, s9, #0 +ori t6, s9, #1 +ori t6, s9, #2 +ori t6, s9, #4 +ori t6, s9, #8 +ori t6, s9, #0x10 +ori t6, s9, #0x20 +ori t6, s9, #0x40 +ori t6, s9, #0x80 +ori t6, s9, #0x100 +ori t6, s9, #0x200 +ori t6, s9, #0x400 +ori t6, s9, #0x7ff +ori t6, t6, #0xfffff801 +ori t6, t6, #0xfffffc00 +ori t6, t6, #0xfffffe00 +ori t6, t6, #0xffffff00 +ori t6, t6, #0xffffff80 +ori t6, t6, #0xffffffc0 +ori t6, t6, #0xffffffe0 +ori t6, t6, #0xfffffff0 +ori t6, t6, #0xfffffff8 +ori t6, t6, #0xfffffffc +ori t6, t6, #0xfffffffe +ori t6, t6, #0xffffffff +ori t6, t6, #0 +ori t6, t6, #1 +ori t6, t6, #2 +ori t6, t6, #4 +ori t6, t6, #8 +ori t6, t6, #0x10 +ori t6, t6, #0x20 +ori t6, t6, #0x40 +ori t6, t6, #0x80 +ori t6, t6, #0x100 +ori t6, t6, #0x200 +ori t6, t6, #0x400 +ori t6, t6, #0x7ff diff --git a/tests/riscv/rv32i/sb.asm b/tests/riscv/rv32i/sb.asm new file mode 100644 index 0000000..65986ca --- /dev/null +++ b/tests/riscv/rv32i/sb.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +sb zero, (#-2047, zero) +sb zero, (#-1024, zero) +sb zero, (#-512, zero) +sb zero, (#-256, zero) +sb zero, (#-128, zero) +sb zero, (#-64, zero) +sb zero, (#-32, zero) +sb zero, (#-16, zero) +sb zero, (#-8, zero) +sb zero, (#-4, zero) +sb zero, (#-2, zero) +sb zero, (#-1, zero) +sb zero, (#0, zero) +sb zero, (#1, zero) +sb zero, (#2, zero) +sb zero, (#4, zero) +sb zero, (#8, zero) +sb zero, (#16, zero) +sb zero, (#32, zero) +sb zero, (#64, zero) +sb zero, (#128, zero) +sb zero, (#256, zero) +sb zero, (#512, zero) +sb zero, (#1024, zero) +sb zero, (#2047, zero) +sb zero, (#-2047, ra) +sb zero, (#-1024, ra) +sb zero, (#-512, ra) +sb zero, (#-256, ra) +sb zero, (#-128, ra) +sb zero, (#-64, ra) +sb zero, (#-32, ra) +sb zero, (#-16, ra) +sb zero, (#-8, ra) +sb zero, (#-4, ra) +sb zero, (#-2, ra) +sb zero, (#-1, ra) +sb zero, (#0, ra) +sb zero, (#1, ra) +sb zero, (#2, ra) +sb zero, (#4, ra) +sb zero, (#8, ra) +sb zero, (#16, ra) +sb zero, (#32, ra) +sb zero, (#64, ra) +sb zero, (#128, ra) +sb zero, (#256, ra) +sb zero, (#512, ra) +sb zero, (#1024, ra) +sb zero, (#2047, ra) +sb zero, (#-2047, t0) +sb zero, (#-1024, t0) +sb zero, (#-512, t0) +sb zero, (#-256, t0) +sb zero, (#-128, t0) +sb zero, (#-64, t0) +sb zero, (#-32, t0) +sb zero, (#-16, t0) +sb zero, (#-8, t0) +sb zero, (#-4, t0) +sb zero, (#-2, t0) +sb zero, (#-1, t0) +sb zero, (#0, t0) +sb zero, (#1, t0) +sb zero, (#2, t0) +sb zero, (#4, t0) +sb zero, (#8, t0) +sb zero, (#16, t0) +sb zero, (#32, t0) +sb zero, (#64, t0) +sb zero, (#128, t0) +sb zero, (#256, t0) +sb zero, (#512, t0) +sb zero, (#1024, t0) +sb zero, (#2047, t0) +sb zero, (#-2047, a0) +sb zero, (#-1024, a0) +sb zero, (#-512, a0) +sb zero, (#-256, a0) +sb zero, (#-128, a0) +sb zero, (#-64, a0) +sb zero, (#-32, a0) +sb zero, (#-16, a0) +sb zero, (#-8, a0) +sb zero, (#-4, a0) +sb zero, (#-2, a0) +sb zero, (#-1, a0) +sb zero, (#0, a0) +sb zero, (#1, a0) +sb zero, (#2, a0) +sb zero, (#4, a0) +sb zero, (#8, a0) +sb zero, (#16, a0) +sb zero, (#32, a0) +sb zero, (#64, a0) +sb zero, (#128, a0) +sb zero, (#256, a0) +sb zero, (#512, a0) +sb zero, (#1024, a0) +sb zero, (#2047, a0) +sb zero, (#-2047, a5) +sb zero, (#-1024, a5) +sb zero, (#-512, a5) +sb zero, (#-256, a5) +sb zero, (#-128, a5) +sb zero, (#-64, a5) +sb zero, (#-32, a5) +sb zero, (#-16, a5) +sb zero, (#-8, a5) +sb zero, (#-4, a5) +sb zero, (#-2, a5) +sb zero, (#-1, a5) +sb zero, (#0, a5) +sb zero, (#1, a5) +sb zero, (#2, a5) +sb zero, (#4, a5) +sb zero, (#8, a5) +sb zero, (#16, a5) +sb zero, (#32, a5) +sb zero, (#64, a5) +sb zero, (#128, a5) +sb zero, (#256, a5) +sb zero, (#512, a5) +sb zero, (#1024, a5) +sb zero, (#2047, a5) +sb zero, (#-2047, s4) +sb zero, (#-1024, s4) +sb zero, (#-512, s4) +sb zero, (#-256, s4) +sb zero, (#-128, s4) +sb zero, (#-64, s4) +sb zero, (#-32, s4) +sb zero, (#-16, s4) +sb zero, (#-8, s4) +sb zero, (#-4, s4) +sb zero, (#-2, s4) +sb zero, (#-1, s4) +sb zero, (#0, s4) +sb zero, (#1, s4) +sb zero, (#2, s4) +sb zero, (#4, s4) +sb zero, (#8, s4) +sb zero, (#16, s4) +sb zero, (#32, s4) +sb zero, (#64, s4) +sb zero, (#128, s4) +sb zero, (#256, s4) +sb zero, (#512, s4) +sb zero, (#1024, s4) +sb zero, (#2047, s4) +sb zero, (#-2047, s9) +sb zero, (#-1024, s9) +sb zero, (#-512, s9) +sb zero, (#-256, s9) +sb zero, (#-128, s9) +sb zero, (#-64, s9) +sb zero, (#-32, s9) +sb zero, (#-16, s9) +sb zero, (#-8, s9) +sb zero, (#-4, s9) +sb zero, (#-2, s9) +sb zero, (#-1, s9) +sb zero, (#0, s9) +sb zero, (#1, s9) +sb zero, (#2, s9) +sb zero, (#4, s9) +sb zero, (#8, s9) +sb zero, (#16, s9) +sb zero, (#32, s9) +sb zero, (#64, s9) +sb zero, (#128, s9) +sb zero, (#256, s9) +sb zero, (#512, s9) +sb zero, (#1024, s9) +sb zero, (#2047, s9) +sb zero, (#-2047, t6) +sb zero, (#-1024, t6) +sb zero, (#-512, t6) +sb zero, (#-256, t6) +sb zero, (#-128, t6) +sb zero, (#-64, t6) +sb zero, (#-32, t6) +sb zero, (#-16, t6) +sb zero, (#-8, t6) +sb zero, (#-4, t6) +sb zero, (#-2, t6) +sb zero, (#-1, t6) +sb zero, (#0, t6) +sb zero, (#1, t6) +sb zero, (#2, t6) +sb zero, (#4, t6) +sb zero, (#8, t6) +sb zero, (#16, t6) +sb zero, (#32, t6) +sb zero, (#64, t6) +sb zero, (#128, t6) +sb zero, (#256, t6) +sb zero, (#512, t6) +sb zero, (#1024, t6) +sb zero, (#2047, t6) +sb ra, (#-2047, zero) +sb ra, (#-1024, zero) +sb ra, (#-512, zero) +sb ra, (#-256, zero) +sb ra, (#-128, zero) +sb ra, (#-64, zero) +sb ra, (#-32, zero) +sb ra, (#-16, zero) +sb ra, (#-8, zero) +sb ra, (#-4, zero) +sb ra, (#-2, zero) +sb ra, (#-1, zero) +sb ra, (#0, zero) +sb ra, (#1, zero) +sb ra, (#2, zero) +sb ra, (#4, zero) +sb ra, (#8, zero) +sb ra, (#16, zero) +sb ra, (#32, zero) +sb ra, (#64, zero) +sb ra, (#128, zero) +sb ra, (#256, zero) +sb ra, (#512, zero) +sb ra, (#1024, zero) +sb ra, (#2047, zero) +sb ra, (#-2047, ra) +sb ra, (#-1024, ra) +sb ra, (#-512, ra) +sb ra, (#-256, ra) +sb ra, (#-128, ra) +sb ra, (#-64, ra) +sb ra, (#-32, ra) +sb ra, (#-16, ra) +sb ra, (#-8, ra) +sb ra, (#-4, ra) +sb ra, (#-2, ra) +sb ra, (#-1, ra) +sb ra, (#0, ra) +sb ra, (#1, ra) +sb ra, (#2, ra) +sb ra, (#4, ra) +sb ra, (#8, ra) +sb ra, (#16, ra) +sb ra, (#32, ra) +sb ra, (#64, ra) +sb ra, (#128, ra) +sb ra, (#256, ra) +sb ra, (#512, ra) +sb ra, (#1024, ra) +sb ra, (#2047, ra) +sb ra, (#-2047, t0) +sb ra, (#-1024, t0) +sb ra, (#-512, t0) +sb ra, (#-256, t0) +sb ra, (#-128, t0) +sb ra, (#-64, t0) +sb ra, (#-32, t0) +sb ra, (#-16, t0) +sb ra, (#-8, t0) +sb ra, (#-4, t0) +sb ra, (#-2, t0) +sb ra, (#-1, t0) +sb ra, (#0, t0) +sb ra, (#1, t0) +sb ra, (#2, t0) +sb ra, (#4, t0) +sb ra, (#8, t0) +sb ra, (#16, t0) +sb ra, (#32, t0) +sb ra, (#64, t0) +sb ra, (#128, t0) +sb ra, (#256, t0) +sb ra, (#512, t0) +sb ra, (#1024, t0) +sb ra, (#2047, t0) +sb ra, (#-2047, a0) +sb ra, (#-1024, a0) +sb ra, (#-512, a0) +sb ra, (#-256, a0) +sb ra, (#-128, a0) +sb ra, (#-64, a0) +sb ra, (#-32, a0) +sb ra, (#-16, a0) +sb ra, (#-8, a0) +sb ra, (#-4, a0) +sb ra, (#-2, a0) +sb ra, (#-1, a0) +sb ra, (#0, a0) +sb ra, (#1, a0) +sb ra, (#2, a0) +sb ra, (#4, a0) +sb ra, (#8, a0) +sb ra, (#16, a0) +sb ra, (#32, a0) +sb ra, (#64, a0) +sb ra, (#128, a0) +sb ra, (#256, a0) +sb ra, (#512, a0) +sb ra, (#1024, a0) +sb ra, (#2047, a0) +sb ra, (#-2047, a5) +sb ra, (#-1024, a5) +sb ra, (#-512, a5) +sb ra, (#-256, a5) +sb ra, (#-128, a5) +sb ra, (#-64, a5) +sb ra, (#-32, a5) +sb ra, (#-16, a5) +sb ra, (#-8, a5) +sb ra, (#-4, a5) +sb ra, (#-2, a5) +sb ra, (#-1, a5) +sb ra, (#0, a5) +sb ra, (#1, a5) +sb ra, (#2, a5) +sb ra, (#4, a5) +sb ra, (#8, a5) +sb ra, (#16, a5) +sb ra, (#32, a5) +sb ra, (#64, a5) +sb ra, (#128, a5) +sb ra, (#256, a5) +sb ra, (#512, a5) +sb ra, (#1024, a5) +sb ra, (#2047, a5) +sb ra, (#-2047, s4) +sb ra, (#-1024, s4) +sb ra, (#-512, s4) +sb ra, (#-256, s4) +sb ra, (#-128, s4) +sb ra, (#-64, s4) +sb ra, (#-32, s4) +sb ra, (#-16, s4) +sb ra, (#-8, s4) +sb ra, (#-4, s4) +sb ra, (#-2, s4) +sb ra, (#-1, s4) +sb ra, (#0, s4) +sb ra, (#1, s4) +sb ra, (#2, s4) +sb ra, (#4, s4) +sb ra, (#8, s4) +sb ra, (#16, s4) +sb ra, (#32, s4) +sb ra, (#64, s4) +sb ra, (#128, s4) +sb ra, (#256, s4) +sb ra, (#512, s4) +sb ra, (#1024, s4) +sb ra, (#2047, s4) +sb ra, (#-2047, s9) +sb ra, (#-1024, s9) +sb ra, (#-512, s9) +sb ra, (#-256, s9) +sb ra, (#-128, s9) +sb ra, (#-64, s9) +sb ra, (#-32, s9) +sb ra, (#-16, s9) +sb ra, (#-8, s9) +sb ra, (#-4, s9) +sb ra, (#-2, s9) +sb ra, (#-1, s9) +sb ra, (#0, s9) +sb ra, (#1, s9) +sb ra, (#2, s9) +sb ra, (#4, s9) +sb ra, (#8, s9) +sb ra, (#16, s9) +sb ra, (#32, s9) +sb ra, (#64, s9) +sb ra, (#128, s9) +sb ra, (#256, s9) +sb ra, (#512, s9) +sb ra, (#1024, s9) +sb ra, (#2047, s9) +sb ra, (#-2047, t6) +sb ra, (#-1024, t6) +sb ra, (#-512, t6) +sb ra, (#-256, t6) +sb ra, (#-128, t6) +sb ra, (#-64, t6) +sb ra, (#-32, t6) +sb ra, (#-16, t6) +sb ra, (#-8, t6) +sb ra, (#-4, t6) +sb ra, (#-2, t6) +sb ra, (#-1, t6) +sb ra, (#0, t6) +sb ra, (#1, t6) +sb ra, (#2, t6) +sb ra, (#4, t6) +sb ra, (#8, t6) +sb ra, (#16, t6) +sb ra, (#32, t6) +sb ra, (#64, t6) +sb ra, (#128, t6) +sb ra, (#256, t6) +sb ra, (#512, t6) +sb ra, (#1024, t6) +sb ra, (#2047, t6) +sb t0, (#-2047, zero) +sb t0, (#-1024, zero) +sb t0, (#-512, zero) +sb t0, (#-256, zero) +sb t0, (#-128, zero) +sb t0, (#-64, zero) +sb t0, (#-32, zero) +sb t0, (#-16, zero) +sb t0, (#-8, zero) +sb t0, (#-4, zero) +sb t0, (#-2, zero) +sb t0, (#-1, zero) +sb t0, (#0, zero) +sb t0, (#1, zero) +sb t0, (#2, zero) +sb t0, (#4, zero) +sb t0, (#8, zero) +sb t0, (#16, zero) +sb t0, (#32, zero) +sb t0, (#64, zero) +sb t0, (#128, zero) +sb t0, (#256, zero) +sb t0, (#512, zero) +sb t0, (#1024, zero) +sb t0, (#2047, zero) +sb t0, (#-2047, ra) +sb t0, (#-1024, ra) +sb t0, (#-512, ra) +sb t0, (#-256, ra) +sb t0, (#-128, ra) +sb t0, (#-64, ra) +sb t0, (#-32, ra) +sb t0, (#-16, ra) +sb t0, (#-8, ra) +sb t0, (#-4, ra) +sb t0, (#-2, ra) +sb t0, (#-1, ra) +sb t0, (#0, ra) +sb t0, (#1, ra) +sb t0, (#2, ra) +sb t0, (#4, ra) +sb t0, (#8, ra) +sb t0, (#16, ra) +sb t0, (#32, ra) +sb t0, (#64, ra) +sb t0, (#128, ra) +sb t0, (#256, ra) +sb t0, (#512, ra) +sb t0, (#1024, ra) +sb t0, (#2047, ra) +sb t0, (#-2047, t0) +sb t0, (#-1024, t0) +sb t0, (#-512, t0) +sb t0, (#-256, t0) +sb t0, (#-128, t0) +sb t0, (#-64, t0) +sb t0, (#-32, t0) +sb t0, (#-16, t0) +sb t0, (#-8, t0) +sb t0, (#-4, t0) +sb t0, (#-2, t0) +sb t0, (#-1, t0) +sb t0, (#0, t0) +sb t0, (#1, t0) +sb t0, (#2, t0) +sb t0, (#4, t0) +sb t0, (#8, t0) +sb t0, (#16, t0) +sb t0, (#32, t0) +sb t0, (#64, t0) +sb t0, (#128, t0) +sb t0, (#256, t0) +sb t0, (#512, t0) +sb t0, (#1024, t0) +sb t0, (#2047, t0) +sb t0, (#-2047, a0) +sb t0, (#-1024, a0) +sb t0, (#-512, a0) +sb t0, (#-256, a0) +sb t0, (#-128, a0) +sb t0, (#-64, a0) +sb t0, (#-32, a0) +sb t0, (#-16, a0) +sb t0, (#-8, a0) +sb t0, (#-4, a0) +sb t0, (#-2, a0) +sb t0, (#-1, a0) +sb t0, (#0, a0) +sb t0, (#1, a0) +sb t0, (#2, a0) +sb t0, (#4, a0) +sb t0, (#8, a0) +sb t0, (#16, a0) +sb t0, (#32, a0) +sb t0, (#64, a0) +sb t0, (#128, a0) +sb t0, (#256, a0) +sb t0, (#512, a0) +sb t0, (#1024, a0) +sb t0, (#2047, a0) +sb t0, (#-2047, a5) +sb t0, (#-1024, a5) +sb t0, (#-512, a5) +sb t0, (#-256, a5) +sb t0, (#-128, a5) +sb t0, (#-64, a5) +sb t0, (#-32, a5) +sb t0, (#-16, a5) +sb t0, (#-8, a5) +sb t0, (#-4, a5) +sb t0, (#-2, a5) +sb t0, (#-1, a5) +sb t0, (#0, a5) +sb t0, (#1, a5) +sb t0, (#2, a5) +sb t0, (#4, a5) +sb t0, (#8, a5) +sb t0, (#16, a5) +sb t0, (#32, a5) +sb t0, (#64, a5) +sb t0, (#128, a5) +sb t0, (#256, a5) +sb t0, (#512, a5) +sb t0, (#1024, a5) +sb t0, (#2047, a5) +sb t0, (#-2047, s4) +sb t0, (#-1024, s4) +sb t0, (#-512, s4) +sb t0, (#-256, s4) +sb t0, (#-128, s4) +sb t0, (#-64, s4) +sb t0, (#-32, s4) +sb t0, (#-16, s4) +sb t0, (#-8, s4) +sb t0, (#-4, s4) +sb t0, (#-2, s4) +sb t0, (#-1, s4) +sb t0, (#0, s4) +sb t0, (#1, s4) +sb t0, (#2, s4) +sb t0, (#4, s4) +sb t0, (#8, s4) +sb t0, (#16, s4) +sb t0, (#32, s4) +sb t0, (#64, s4) +sb t0, (#128, s4) +sb t0, (#256, s4) +sb t0, (#512, s4) +sb t0, (#1024, s4) +sb t0, (#2047, s4) +sb t0, (#-2047, s9) +sb t0, (#-1024, s9) +sb t0, (#-512, s9) +sb t0, (#-256, s9) +sb t0, (#-128, s9) +sb t0, (#-64, s9) +sb t0, (#-32, s9) +sb t0, (#-16, s9) +sb t0, (#-8, s9) +sb t0, (#-4, s9) +sb t0, (#-2, s9) +sb t0, (#-1, s9) +sb t0, (#0, s9) +sb t0, (#1, s9) +sb t0, (#2, s9) +sb t0, (#4, s9) +sb t0, (#8, s9) +sb t0, (#16, s9) +sb t0, (#32, s9) +sb t0, (#64, s9) +sb t0, (#128, s9) +sb t0, (#256, s9) +sb t0, (#512, s9) +sb t0, (#1024, s9) +sb t0, (#2047, s9) +sb t0, (#-2047, t6) +sb t0, (#-1024, t6) +sb t0, (#-512, t6) +sb t0, (#-256, t6) +sb t0, (#-128, t6) +sb t0, (#-64, t6) +sb t0, (#-32, t6) +sb t0, (#-16, t6) +sb t0, (#-8, t6) +sb t0, (#-4, t6) +sb t0, (#-2, t6) +sb t0, (#-1, t6) +sb t0, (#0, t6) +sb t0, (#1, t6) +sb t0, (#2, t6) +sb t0, (#4, t6) +sb t0, (#8, t6) +sb t0, (#16, t6) +sb t0, (#32, t6) +sb t0, (#64, t6) +sb t0, (#128, t6) +sb t0, (#256, t6) +sb t0, (#512, t6) +sb t0, (#1024, t6) +sb t0, (#2047, t6) +sb a0, (#-2047, zero) +sb a0, (#-1024, zero) +sb a0, (#-512, zero) +sb a0, (#-256, zero) +sb a0, (#-128, zero) +sb a0, (#-64, zero) +sb a0, (#-32, zero) +sb a0, (#-16, zero) +sb a0, (#-8, zero) +sb a0, (#-4, zero) +sb a0, (#-2, zero) +sb a0, (#-1, zero) +sb a0, (#0, zero) +sb a0, (#1, zero) +sb a0, (#2, zero) +sb a0, (#4, zero) +sb a0, (#8, zero) +sb a0, (#16, zero) +sb a0, (#32, zero) +sb a0, (#64, zero) +sb a0, (#128, zero) +sb a0, (#256, zero) +sb a0, (#512, zero) +sb a0, (#1024, zero) +sb a0, (#2047, zero) +sb a0, (#-2047, ra) +sb a0, (#-1024, ra) +sb a0, (#-512, ra) +sb a0, (#-256, ra) +sb a0, (#-128, ra) +sb a0, (#-64, ra) +sb a0, (#-32, ra) +sb a0, (#-16, ra) +sb a0, (#-8, ra) +sb a0, (#-4, ra) +sb a0, (#-2, ra) +sb a0, (#-1, ra) +sb a0, (#0, ra) +sb a0, (#1, ra) +sb a0, (#2, ra) +sb a0, (#4, ra) +sb a0, (#8, ra) +sb a0, (#16, ra) +sb a0, (#32, ra) +sb a0, (#64, ra) +sb a0, (#128, ra) +sb a0, (#256, ra) +sb a0, (#512, ra) +sb a0, (#1024, ra) +sb a0, (#2047, ra) +sb a0, (#-2047, t0) +sb a0, (#-1024, t0) +sb a0, (#-512, t0) +sb a0, (#-256, t0) +sb a0, (#-128, t0) +sb a0, (#-64, t0) +sb a0, (#-32, t0) +sb a0, (#-16, t0) +sb a0, (#-8, t0) +sb a0, (#-4, t0) +sb a0, (#-2, t0) +sb a0, (#-1, t0) +sb a0, (#0, t0) +sb a0, (#1, t0) +sb a0, (#2, t0) +sb a0, (#4, t0) +sb a0, (#8, t0) +sb a0, (#16, t0) +sb a0, (#32, t0) +sb a0, (#64, t0) +sb a0, (#128, t0) +sb a0, (#256, t0) +sb a0, (#512, t0) +sb a0, (#1024, t0) +sb a0, (#2047, t0) +sb a0, (#-2047, a0) +sb a0, (#-1024, a0) +sb a0, (#-512, a0) +sb a0, (#-256, a0) +sb a0, (#-128, a0) +sb a0, (#-64, a0) +sb a0, (#-32, a0) +sb a0, (#-16, a0) +sb a0, (#-8, a0) +sb a0, (#-4, a0) +sb a0, (#-2, a0) +sb a0, (#-1, a0) +sb a0, (#0, a0) +sb a0, (#1, a0) +sb a0, (#2, a0) +sb a0, (#4, a0) +sb a0, (#8, a0) +sb a0, (#16, a0) +sb a0, (#32, a0) +sb a0, (#64, a0) +sb a0, (#128, a0) +sb a0, (#256, a0) +sb a0, (#512, a0) +sb a0, (#1024, a0) +sb a0, (#2047, a0) +sb a0, (#-2047, a5) +sb a0, (#-1024, a5) +sb a0, (#-512, a5) +sb a0, (#-256, a5) +sb a0, (#-128, a5) +sb a0, (#-64, a5) +sb a0, (#-32, a5) +sb a0, (#-16, a5) +sb a0, (#-8, a5) +sb a0, (#-4, a5) +sb a0, (#-2, a5) +sb a0, (#-1, a5) +sb a0, (#0, a5) +sb a0, (#1, a5) +sb a0, (#2, a5) +sb a0, (#4, a5) +sb a0, (#8, a5) +sb a0, (#16, a5) +sb a0, (#32, a5) +sb a0, (#64, a5) +sb a0, (#128, a5) +sb a0, (#256, a5) +sb a0, (#512, a5) +sb a0, (#1024, a5) +sb a0, (#2047, a5) +sb a0, (#-2047, s4) +sb a0, (#-1024, s4) +sb a0, (#-512, s4) +sb a0, (#-256, s4) +sb a0, (#-128, s4) +sb a0, (#-64, s4) +sb a0, (#-32, s4) +sb a0, (#-16, s4) +sb a0, (#-8, s4) +sb a0, (#-4, s4) +sb a0, (#-2, s4) +sb a0, (#-1, s4) +sb a0, (#0, s4) +sb a0, (#1, s4) +sb a0, (#2, s4) +sb a0, (#4, s4) +sb a0, (#8, s4) +sb a0, (#16, s4) +sb a0, (#32, s4) +sb a0, (#64, s4) +sb a0, (#128, s4) +sb a0, (#256, s4) +sb a0, (#512, s4) +sb a0, (#1024, s4) +sb a0, (#2047, s4) +sb a0, (#-2047, s9) +sb a0, (#-1024, s9) +sb a0, (#-512, s9) +sb a0, (#-256, s9) +sb a0, (#-128, s9) +sb a0, (#-64, s9) +sb a0, (#-32, s9) +sb a0, (#-16, s9) +sb a0, (#-8, s9) +sb a0, (#-4, s9) +sb a0, (#-2, s9) +sb a0, (#-1, s9) +sb a0, (#0, s9) +sb a0, (#1, s9) +sb a0, (#2, s9) +sb a0, (#4, s9) +sb a0, (#8, s9) +sb a0, (#16, s9) +sb a0, (#32, s9) +sb a0, (#64, s9) +sb a0, (#128, s9) +sb a0, (#256, s9) +sb a0, (#512, s9) +sb a0, (#1024, s9) +sb a0, (#2047, s9) +sb a0, (#-2047, t6) +sb a0, (#-1024, t6) +sb a0, (#-512, t6) +sb a0, (#-256, t6) +sb a0, (#-128, t6) +sb a0, (#-64, t6) +sb a0, (#-32, t6) +sb a0, (#-16, t6) +sb a0, (#-8, t6) +sb a0, (#-4, t6) +sb a0, (#-2, t6) +sb a0, (#-1, t6) +sb a0, (#0, t6) +sb a0, (#1, t6) +sb a0, (#2, t6) +sb a0, (#4, t6) +sb a0, (#8, t6) +sb a0, (#16, t6) +sb a0, (#32, t6) +sb a0, (#64, t6) +sb a0, (#128, t6) +sb a0, (#256, t6) +sb a0, (#512, t6) +sb a0, (#1024, t6) +sb a0, (#2047, t6) +sb a5, (#-2047, zero) +sb a5, (#-1024, zero) +sb a5, (#-512, zero) +sb a5, (#-256, zero) +sb a5, (#-128, zero) +sb a5, (#-64, zero) +sb a5, (#-32, zero) +sb a5, (#-16, zero) +sb a5, (#-8, zero) +sb a5, (#-4, zero) +sb a5, (#-2, zero) +sb a5, (#-1, zero) +sb a5, (#0, zero) +sb a5, (#1, zero) +sb a5, (#2, zero) +sb a5, (#4, zero) +sb a5, (#8, zero) +sb a5, (#16, zero) +sb a5, (#32, zero) +sb a5, (#64, zero) +sb a5, (#128, zero) +sb a5, (#256, zero) +sb a5, (#512, zero) +sb a5, (#1024, zero) +sb a5, (#2047, zero) +sb a5, (#-2047, ra) +sb a5, (#-1024, ra) +sb a5, (#-512, ra) +sb a5, (#-256, ra) +sb a5, (#-128, ra) +sb a5, (#-64, ra) +sb a5, (#-32, ra) +sb a5, (#-16, ra) +sb a5, (#-8, ra) +sb a5, (#-4, ra) +sb a5, (#-2, ra) +sb a5, (#-1, ra) +sb a5, (#0, ra) +sb a5, (#1, ra) +sb a5, (#2, ra) +sb a5, (#4, ra) +sb a5, (#8, ra) +sb a5, (#16, ra) +sb a5, (#32, ra) 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s4, (#-256, zero) +sb s4, (#-128, zero) +sb s4, (#-64, zero) +sb s4, (#-32, zero) +sb s4, (#-16, zero) +sb s4, (#-8, zero) +sb s4, (#-4, zero) +sb s4, (#-2, zero) +sb s4, (#-1, zero) +sb s4, (#0, zero) +sb s4, (#1, zero) +sb s4, (#2, zero) +sb s4, (#4, zero) +sb s4, (#8, zero) +sb s4, (#16, zero) +sb s4, (#32, zero) +sb s4, (#64, zero) +sb s4, (#128, zero) +sb s4, (#256, zero) +sb s4, (#512, zero) +sb s4, (#1024, zero) +sb s4, (#2047, zero) +sb s4, (#-2047, ra) +sb s4, (#-1024, ra) +sb s4, (#-512, ra) +sb s4, (#-256, ra) +sb s4, (#-128, ra) +sb s4, (#-64, ra) +sb s4, (#-32, ra) +sb s4, (#-16, ra) +sb s4, (#-8, ra) +sb s4, (#-4, ra) +sb s4, (#-2, ra) +sb s4, (#-1, ra) +sb s4, (#0, ra) +sb s4, (#1, ra) +sb s4, (#2, ra) +sb s4, (#4, ra) +sb s4, (#8, ra) +sb s4, (#16, ra) +sb s4, (#32, ra) +sb s4, (#64, ra) +sb s4, (#128, ra) +sb s4, (#256, ra) +sb s4, (#512, ra) +sb s4, (#1024, ra) +sb s4, (#2047, ra) +sb s4, (#-2047, t0) +sb s4, (#-1024, t0) +sb s4, (#-512, t0) +sb s4, (#-256, t0) +sb s4, (#-128, t0) +sb s4, (#-64, t0) +sb s4, (#-32, t0) +sb s4, (#-16, t0) +sb s4, (#-8, t0) +sb s4, (#-4, t0) +sb s4, (#-2, t0) +sb s4, (#-1, t0) +sb s4, (#0, t0) +sb s4, (#1, t0) +sb s4, (#2, t0) +sb s4, (#4, t0) +sb s4, (#8, t0) +sb s4, (#16, t0) +sb s4, (#32, t0) +sb s4, (#64, t0) +sb s4, (#128, t0) +sb s4, (#256, t0) +sb s4, (#512, t0) +sb s4, (#1024, t0) +sb s4, (#2047, t0) +sb s4, (#-2047, a0) +sb s4, (#-1024, a0) +sb s4, (#-512, a0) +sb s4, (#-256, a0) +sb s4, (#-128, a0) +sb s4, (#-64, a0) +sb s4, (#-32, a0) +sb s4, (#-16, a0) +sb s4, (#-8, a0) +sb s4, (#-4, a0) +sb s4, (#-2, a0) +sb s4, (#-1, a0) +sb s4, (#0, a0) +sb s4, (#1, a0) +sb s4, (#2, a0) +sb s4, (#4, a0) +sb s4, (#8, a0) +sb s4, (#16, a0) +sb s4, (#32, a0) +sb s4, (#64, a0) +sb s4, (#128, a0) +sb s4, (#256, a0) +sb s4, (#512, a0) +sb s4, (#1024, a0) +sb s4, (#2047, a0) +sb s4, (#-2047, a5) +sb s4, (#-1024, a5) +sb s4, (#-512, a5) +sb s4, (#-256, a5) +sb s4, (#-128, a5) +sb s4, (#-64, a5) +sb s4, (#-32, a5) +sb s4, (#-16, a5) +sb s4, (#-8, a5) +sb s4, (#-4, a5) +sb s4, (#-2, a5) +sb s4, (#-1, a5) +sb s4, (#0, a5) +sb s4, (#1, a5) +sb s4, (#2, a5) +sb s4, (#4, a5) +sb s4, (#8, a5) +sb s4, (#16, a5) +sb s4, (#32, a5) +sb s4, (#64, a5) +sb s4, (#128, a5) +sb s4, (#256, a5) +sb s4, (#512, a5) +sb s4, (#1024, a5) +sb s4, (#2047, a5) +sb s4, (#-2047, s4) +sb s4, (#-1024, s4) +sb s4, (#-512, s4) +sb s4, (#-256, s4) +sb s4, (#-128, s4) +sb s4, (#-64, s4) +sb s4, (#-32, s4) +sb s4, (#-16, s4) +sb s4, (#-8, s4) +sb s4, (#-4, s4) +sb s4, (#-2, s4) +sb s4, (#-1, s4) +sb s4, (#0, s4) +sb s4, (#1, s4) +sb s4, (#2, s4) +sb s4, (#4, s4) +sb s4, (#8, s4) +sb s4, (#16, s4) +sb s4, (#32, s4) +sb s4, (#64, s4) +sb s4, (#128, s4) +sb s4, (#256, s4) +sb s4, (#512, s4) +sb s4, (#1024, s4) +sb s4, (#2047, s4) +sb s4, (#-2047, s9) +sb s4, (#-1024, s9) +sb s4, (#-512, s9) +sb s4, (#-256, s9) +sb s4, (#-128, s9) +sb s4, (#-64, s9) +sb s4, (#-32, s9) +sb s4, (#-16, s9) +sb s4, (#-8, s9) +sb s4, (#-4, s9) +sb s4, (#-2, s9) +sb s4, (#-1, s9) +sb s4, (#0, s9) +sb s4, (#1, s9) +sb s4, (#2, s9) +sb s4, (#4, s9) +sb s4, (#8, s9) +sb s4, (#16, s9) +sb s4, (#32, s9) +sb s4, (#64, s9) +sb s4, (#128, s9) +sb s4, (#256, s9) +sb s4, (#512, s9) +sb s4, (#1024, s9) +sb s4, (#2047, s9) +sb s4, (#-2047, t6) +sb s4, (#-1024, t6) +sb s4, (#-512, t6) +sb s4, (#-256, t6) +sb s4, (#-128, t6) +sb s4, (#-64, t6) +sb s4, (#-32, t6) +sb s4, (#-16, t6) +sb s4, (#-8, t6) +sb s4, (#-4, t6) +sb s4, (#-2, t6) +sb s4, (#-1, t6) +sb s4, (#0, t6) +sb s4, (#1, t6) +sb s4, (#2, t6) +sb s4, (#4, t6) +sb s4, (#8, t6) +sb s4, (#16, t6) +sb s4, (#32, t6) +sb s4, (#64, t6) +sb s4, (#128, t6) +sb s4, (#256, t6) +sb s4, (#512, t6) +sb s4, (#1024, t6) +sb s4, (#2047, t6) +sb s9, (#-2047, zero) +sb s9, (#-1024, zero) +sb s9, (#-512, zero) +sb s9, (#-256, zero) +sb s9, (#-128, zero) +sb s9, (#-64, zero) +sb s9, (#-32, zero) +sb s9, (#-16, zero) +sb s9, (#-8, zero) +sb s9, (#-4, zero) +sb s9, (#-2, zero) +sb s9, (#-1, zero) +sb s9, (#0, zero) +sb s9, (#1, zero) +sb s9, (#2, zero) +sb s9, (#4, zero) +sb s9, (#8, zero) +sb s9, (#16, zero) +sb s9, (#32, zero) +sb s9, (#64, zero) +sb s9, (#128, zero) +sb s9, (#256, zero) +sb s9, (#512, zero) +sb s9, (#1024, zero) +sb s9, (#2047, zero) +sb s9, (#-2047, ra) +sb s9, (#-1024, ra) +sb s9, (#-512, ra) +sb s9, (#-256, ra) +sb s9, (#-128, ra) +sb s9, (#-64, ra) +sb s9, (#-32, ra) +sb s9, (#-16, ra) +sb s9, (#-8, ra) +sb s9, (#-4, ra) +sb s9, (#-2, ra) +sb s9, (#-1, ra) +sb s9, (#0, ra) +sb s9, (#1, ra) +sb s9, (#2, ra) +sb s9, (#4, ra) +sb s9, (#8, ra) +sb s9, (#16, ra) +sb s9, (#32, ra) +sb s9, (#64, ra) +sb s9, (#128, ra) +sb s9, (#256, ra) +sb s9, (#512, ra) +sb s9, (#1024, ra) +sb s9, (#2047, ra) +sb s9, (#-2047, t0) +sb s9, (#-1024, t0) +sb s9, (#-512, t0) +sb s9, (#-256, t0) +sb s9, (#-128, t0) +sb s9, (#-64, t0) +sb s9, (#-32, t0) +sb s9, (#-16, t0) +sb s9, (#-8, t0) +sb s9, (#-4, t0) +sb s9, (#-2, t0) +sb s9, (#-1, t0) +sb s9, (#0, t0) +sb s9, (#1, t0) +sb s9, (#2, t0) +sb s9, (#4, t0) +sb s9, (#8, t0) +sb s9, (#16, t0) +sb s9, (#32, t0) +sb s9, (#64, t0) +sb s9, (#128, t0) +sb s9, (#256, t0) +sb s9, (#512, t0) +sb s9, (#1024, t0) +sb s9, (#2047, t0) +sb s9, (#-2047, a0) +sb s9, (#-1024, a0) +sb s9, (#-512, a0) +sb s9, (#-256, a0) +sb s9, (#-128, a0) +sb s9, (#-64, a0) +sb s9, (#-32, a0) +sb s9, (#-16, a0) +sb s9, (#-8, a0) +sb s9, (#-4, a0) +sb s9, (#-2, a0) +sb s9, (#-1, a0) +sb s9, (#0, a0) +sb s9, (#1, a0) +sb s9, (#2, a0) +sb s9, (#4, a0) +sb s9, (#8, a0) +sb s9, (#16, a0) +sb s9, (#32, a0) +sb s9, (#64, a0) +sb s9, (#128, a0) +sb s9, (#256, a0) +sb s9, (#512, a0) +sb s9, (#1024, a0) +sb s9, (#2047, a0) +sb s9, (#-2047, a5) +sb s9, (#-1024, a5) +sb s9, (#-512, a5) +sb s9, (#-256, a5) +sb s9, (#-128, a5) +sb s9, (#-64, a5) +sb s9, (#-32, a5) +sb s9, (#-16, a5) +sb s9, (#-8, a5) +sb s9, (#-4, a5) +sb s9, (#-2, a5) +sb s9, (#-1, a5) +sb s9, (#0, a5) +sb s9, (#1, a5) +sb s9, (#2, a5) +sb s9, (#4, a5) +sb s9, (#8, a5) +sb s9, (#16, a5) +sb s9, (#32, a5) +sb s9, (#64, a5) +sb s9, (#128, a5) +sb s9, (#256, a5) +sb s9, (#512, a5) +sb s9, (#1024, a5) +sb s9, (#2047, a5) +sb s9, (#-2047, s4) +sb s9, (#-1024, s4) +sb s9, (#-512, s4) +sb s9, (#-256, s4) +sb s9, (#-128, s4) +sb s9, (#-64, s4) +sb s9, (#-32, s4) +sb s9, (#-16, s4) +sb s9, (#-8, s4) +sb s9, (#-4, s4) +sb s9, (#-2, s4) +sb s9, (#-1, s4) +sb s9, (#0, s4) +sb s9, (#1, s4) +sb s9, (#2, s4) +sb s9, (#4, s4) +sb s9, (#8, s4) +sb s9, (#16, s4) +sb s9, (#32, s4) +sb s9, (#64, s4) +sb s9, (#128, s4) +sb s9, (#256, s4) +sb s9, (#512, s4) +sb s9, (#1024, s4) +sb s9, (#2047, s4) +sb s9, (#-2047, s9) +sb s9, (#-1024, s9) +sb s9, (#-512, s9) +sb s9, (#-256, s9) +sb s9, (#-128, s9) +sb s9, (#-64, s9) +sb s9, (#-32, s9) +sb s9, (#-16, s9) +sb s9, (#-8, s9) +sb s9, (#-4, s9) +sb s9, (#-2, s9) +sb s9, (#-1, s9) +sb s9, (#0, s9) +sb s9, (#1, s9) +sb s9, (#2, s9) +sb s9, (#4, s9) +sb s9, (#8, s9) +sb s9, (#16, s9) +sb s9, (#32, s9) +sb s9, (#64, s9) +sb s9, (#128, s9) +sb s9, (#256, s9) +sb s9, (#512, s9) +sb s9, (#1024, s9) +sb s9, (#2047, s9) +sb s9, (#-2047, t6) +sb s9, (#-1024, t6) +sb s9, (#-512, t6) +sb s9, (#-256, t6) +sb s9, (#-128, t6) +sb s9, (#-64, t6) +sb s9, (#-32, t6) +sb s9, (#-16, t6) +sb s9, (#-8, t6) +sb s9, (#-4, t6) +sb s9, (#-2, t6) +sb s9, (#-1, t6) +sb s9, (#0, t6) +sb s9, (#1, t6) +sb s9, (#2, t6) +sb s9, (#4, t6) +sb s9, (#8, t6) +sb s9, (#16, t6) +sb s9, (#32, t6) +sb s9, (#64, t6) +sb s9, (#128, t6) +sb s9, (#256, t6) +sb s9, (#512, t6) +sb s9, (#1024, t6) +sb s9, (#2047, t6) +sb t6, (#-2047, zero) +sb t6, (#-1024, zero) +sb t6, (#-512, zero) +sb t6, (#-256, zero) +sb t6, (#-128, zero) +sb t6, (#-64, zero) +sb t6, (#-32, zero) +sb t6, (#-16, zero) +sb t6, (#-8, zero) +sb t6, (#-4, zero) +sb t6, (#-2, zero) +sb t6, (#-1, zero) +sb t6, (#0, zero) +sb t6, (#1, zero) +sb t6, (#2, zero) +sb t6, (#4, zero) +sb t6, (#8, zero) +sb t6, (#16, zero) +sb t6, (#32, zero) +sb t6, (#64, zero) +sb t6, (#128, zero) +sb t6, (#256, zero) +sb t6, (#512, zero) +sb t6, (#1024, zero) +sb t6, (#2047, zero) +sb t6, (#-2047, ra) +sb t6, (#-1024, ra) +sb t6, (#-512, ra) +sb t6, (#-256, ra) +sb t6, (#-128, ra) +sb t6, (#-64, ra) +sb t6, (#-32, ra) +sb t6, (#-16, ra) +sb t6, (#-8, ra) +sb t6, (#-4, ra) +sb t6, (#-2, ra) +sb t6, (#-1, ra) +sb t6, (#0, ra) +sb t6, (#1, ra) +sb t6, (#2, ra) +sb t6, (#4, ra) +sb t6, (#8, ra) +sb t6, (#16, ra) +sb t6, (#32, ra) +sb t6, (#64, ra) +sb t6, (#128, ra) +sb t6, (#256, ra) +sb t6, (#512, ra) +sb t6, (#1024, ra) +sb t6, (#2047, ra) +sb t6, (#-2047, t0) +sb t6, (#-1024, t0) +sb t6, (#-512, t0) +sb t6, (#-256, t0) +sb t6, (#-128, t0) +sb t6, (#-64, t0) +sb t6, (#-32, t0) +sb t6, (#-16, t0) +sb t6, (#-8, t0) +sb t6, (#-4, t0) +sb t6, (#-2, t0) +sb t6, (#-1, t0) +sb t6, (#0, t0) +sb t6, (#1, t0) +sb t6, (#2, t0) +sb t6, (#4, t0) +sb t6, (#8, t0) +sb t6, (#16, t0) +sb t6, (#32, t0) +sb t6, (#64, t0) +sb t6, (#128, t0) +sb t6, (#256, t0) +sb t6, (#512, t0) +sb t6, (#1024, t0) +sb t6, (#2047, t0) +sb t6, (#-2047, a0) +sb t6, (#-1024, a0) +sb t6, (#-512, a0) +sb t6, (#-256, a0) +sb t6, (#-128, a0) +sb t6, (#-64, a0) +sb t6, (#-32, a0) +sb t6, (#-16, a0) +sb t6, (#-8, a0) +sb t6, (#-4, a0) +sb t6, (#-2, a0) +sb t6, (#-1, a0) +sb t6, (#0, a0) +sb t6, (#1, a0) +sb t6, (#2, a0) +sb t6, (#4, a0) +sb t6, (#8, a0) +sb t6, (#16, a0) +sb t6, (#32, a0) +sb t6, (#64, a0) +sb t6, (#128, a0) +sb t6, (#256, a0) +sb t6, (#512, a0) +sb t6, (#1024, a0) +sb t6, (#2047, a0) +sb t6, (#-2047, a5) +sb t6, (#-1024, a5) +sb t6, (#-512, a5) +sb t6, (#-256, a5) +sb t6, (#-128, a5) +sb t6, (#-64, a5) +sb t6, (#-32, a5) +sb t6, (#-16, a5) +sb t6, (#-8, a5) +sb t6, (#-4, a5) +sb t6, (#-2, a5) +sb t6, (#-1, a5) +sb t6, (#0, a5) +sb t6, (#1, a5) +sb t6, (#2, a5) +sb t6, (#4, a5) +sb t6, (#8, a5) +sb t6, (#16, a5) +sb t6, (#32, a5) +sb t6, (#64, a5) +sb t6, (#128, a5) +sb t6, (#256, a5) +sb t6, (#512, a5) +sb t6, (#1024, a5) +sb t6, (#2047, a5) +sb t6, (#-2047, s4) +sb t6, (#-1024, s4) +sb t6, (#-512, s4) +sb t6, (#-256, s4) +sb t6, (#-128, s4) +sb t6, (#-64, s4) +sb t6, (#-32, s4) +sb t6, (#-16, s4) +sb t6, (#-8, s4) +sb t6, (#-4, s4) +sb t6, (#-2, s4) +sb t6, (#-1, s4) +sb t6, (#0, s4) +sb t6, (#1, s4) +sb t6, (#2, s4) +sb t6, (#4, s4) +sb t6, (#8, s4) +sb t6, (#16, s4) +sb t6, (#32, s4) +sb t6, (#64, s4) +sb t6, (#128, s4) +sb t6, (#256, s4) +sb t6, (#512, s4) +sb t6, (#1024, s4) +sb t6, (#2047, s4) +sb t6, (#-2047, s9) +sb t6, (#-1024, s9) +sb t6, (#-512, s9) +sb t6, (#-256, s9) +sb t6, (#-128, s9) +sb t6, (#-64, s9) +sb t6, (#-32, s9) +sb t6, (#-16, s9) +sb t6, (#-8, s9) +sb t6, (#-4, s9) +sb t6, (#-2, s9) +sb t6, (#-1, s9) +sb t6, (#0, s9) +sb t6, (#1, s9) +sb t6, (#2, s9) +sb t6, (#4, s9) +sb t6, (#8, s9) +sb t6, (#16, s9) +sb t6, (#32, s9) +sb t6, (#64, s9) +sb t6, (#128, s9) +sb t6, (#256, s9) +sb t6, (#512, s9) +sb t6, (#1024, s9) +sb t6, (#2047, s9) +sb t6, (#-2047, t6) +sb t6, (#-1024, t6) +sb t6, (#-512, t6) +sb t6, (#-256, t6) +sb t6, (#-128, t6) +sb t6, (#-64, t6) +sb t6, (#-32, t6) +sb t6, (#-16, t6) +sb t6, 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z{*%Ax^I!hv@84k~Y=n)l5jMg`_+CLtMQsDW|Km5=FLFi{gpIHfHo`{O2pjdEjniQk zrxRw_IJI$VM2+9p}R=&L_;!ajxTB$GHwl zD(Z6`-Zbe!wB7-s2W!VDc3Ixciv=%7u9?u8C-y3lc< zg9c4nqzfGvIxciv=(y;k<3h*fFpJ9xGjv?)xYTi}gOZB+QinG#bzJHoXGB3<>bTT# zspC?|Wgi`vHm-(QTuqo^3AMy@jPLMj%OXuI-YeD2Qhr&pMuUJnMMwqvKh} z%P>nX6K3dm(ea|=MF(vL_)TI?6seN*nbsi+aKg8?}wvMs0(Vin_MpjoL$hucdNNu(WXOp?pEG3cdNNu(V$6-GyKXwREec zThXRNcj;E%v~;VbThX9Ni?npBrCTlCYUx(XK5n(tu^Re6Xu=E~D;+BxD;<ic+*az+%y*2dPx*2dPxwvUbN-~SH`L(_Nw literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/sh.disasm b/tests/riscv/rv32i/sh.disasm new file mode 100644 index 0000000..534ed5a --- /dev/null +++ b/tests/riscv/rv32i/sh.disasm @@ -0,0 +1,1600 @@ +sh zero, (#-2047, zero) +sh zero, (#-1024, zero) +sh zero, (#-512, zero) +sh zero, (#-256, zero) +sh zero, (#-128, zero) +sh zero, (#-64, zero) +sh zero, (#-32, zero) +sh zero, (#-16, zero) +sh zero, (#-8, zero) +sh zero, (#-4, zero) +sh zero, (#-2, zero) +sh zero, (#-1, zero) +sh zero, (#0, zero) +sh zero, (#1, zero) +sh zero, (#2, zero) +sh zero, (#4, zero) +sh zero, (#8, zero) +sh zero, (#16, zero) +sh zero, (#32, zero) +sh zero, (#64, zero) +sh zero, (#128, zero) +sh zero, (#256, zero) +sh zero, (#512, zero) +sh zero, (#1024, zero) +sh zero, (#2047, zero) +sh zero, (#-2047, ra) +sh zero, (#-1024, ra) +sh zero, (#-512, ra) +sh zero, (#-256, ra) +sh zero, (#-128, ra) +sh zero, (#-64, ra) +sh zero, (#-32, ra) +sh zero, (#-16, ra) +sh zero, (#-8, ra) +sh zero, (#-4, ra) +sh zero, (#-2, ra) +sh zero, (#-1, ra) +sh zero, (#0, ra) +sh zero, (#1, ra) +sh zero, (#2, ra) +sh zero, (#4, ra) +sh zero, (#8, ra) +sh zero, (#16, ra) +sh zero, (#32, ra) +sh zero, (#64, ra) +sh zero, (#128, ra) +sh zero, (#256, ra) +sh zero, (#512, ra) +sh zero, (#1024, ra) +sh zero, (#2047, ra) +sh zero, (#-2047, t0) +sh zero, (#-1024, t0) +sh zero, (#-512, t0) +sh zero, (#-256, t0) +sh zero, (#-128, t0) +sh zero, (#-64, t0) +sh zero, (#-32, t0) +sh zero, (#-16, t0) +sh zero, (#-8, t0) +sh zero, (#-4, t0) +sh zero, (#-2, t0) +sh zero, (#-1, t0) +sh zero, (#0, t0) +sh zero, (#1, t0) +sh zero, (#2, t0) +sh zero, (#4, t0) +sh zero, (#8, t0) +sh zero, (#16, t0) +sh zero, (#32, t0) +sh zero, (#64, t0) +sh zero, (#128, t0) +sh zero, (#256, t0) +sh zero, (#512, t0) +sh zero, (#1024, t0) +sh zero, (#2047, t0) +sh zero, (#-2047, a0) +sh zero, (#-1024, a0) +sh zero, (#-512, a0) +sh zero, (#-256, a0) +sh zero, (#-128, a0) +sh zero, (#-64, a0) +sh zero, (#-32, a0) +sh zero, (#-16, a0) +sh zero, (#-8, a0) +sh zero, (#-4, a0) +sh zero, (#-2, a0) +sh zero, (#-1, a0) +sh zero, (#0, a0) +sh zero, (#1, a0) +sh zero, (#2, a0) +sh zero, (#4, a0) +sh zero, (#8, a0) +sh zero, (#16, a0) +sh zero, (#32, a0) +sh zero, (#64, a0) +sh zero, (#128, a0) +sh zero, (#256, a0) +sh zero, (#512, a0) +sh zero, (#1024, a0) +sh zero, (#2047, a0) +sh zero, (#-2047, a5) +sh zero, (#-1024, a5) +sh zero, (#-512, a5) +sh zero, (#-256, a5) +sh zero, (#-128, a5) +sh zero, (#-64, a5) +sh zero, (#-32, a5) +sh zero, (#-16, a5) +sh zero, (#-8, a5) +sh zero, (#-4, a5) +sh zero, (#-2, a5) +sh zero, (#-1, a5) +sh zero, (#0, a5) +sh zero, (#1, a5) +sh zero, (#2, a5) +sh zero, (#4, a5) +sh zero, (#8, a5) +sh zero, (#16, a5) +sh zero, (#32, a5) +sh zero, (#64, a5) +sh zero, (#128, a5) +sh zero, (#256, a5) +sh zero, (#512, a5) +sh zero, (#1024, a5) +sh zero, (#2047, a5) +sh zero, (#-2047, s4) +sh zero, (#-1024, s4) +sh zero, (#-512, s4) +sh zero, (#-256, s4) +sh zero, (#-128, s4) +sh zero, (#-64, s4) +sh zero, (#-32, s4) +sh zero, (#-16, s4) +sh zero, (#-8, s4) +sh zero, (#-4, s4) +sh zero, (#-2, s4) +sh zero, (#-1, s4) +sh zero, (#0, s4) +sh zero, (#1, s4) +sh zero, (#2, s4) +sh zero, (#4, s4) +sh zero, (#8, s4) +sh zero, (#16, s4) +sh zero, (#32, s4) +sh zero, (#64, s4) +sh zero, (#128, s4) +sh zero, (#256, s4) +sh zero, (#512, s4) +sh zero, (#1024, s4) +sh zero, (#2047, s4) +sh zero, (#-2047, s9) +sh zero, (#-1024, s9) +sh zero, (#-512, s9) +sh zero, (#-256, s9) +sh zero, (#-128, s9) +sh zero, (#-64, s9) +sh zero, (#-32, s9) +sh zero, (#-16, s9) +sh zero, (#-8, s9) +sh zero, (#-4, s9) +sh zero, (#-2, s9) +sh zero, (#-1, s9) +sh zero, (#0, s9) +sh zero, (#1, s9) +sh zero, (#2, s9) +sh zero, (#4, s9) +sh zero, (#8, s9) +sh zero, (#16, s9) +sh zero, (#32, s9) +sh zero, (#64, s9) +sh zero, (#128, s9) +sh zero, (#256, s9) +sh zero, (#512, s9) +sh zero, (#1024, s9) +sh zero, (#2047, s9) +sh zero, (#-2047, t6) +sh zero, (#-1024, t6) +sh zero, (#-512, t6) +sh zero, (#-256, t6) +sh zero, (#-128, t6) +sh zero, (#-64, t6) +sh zero, (#-32, t6) +sh zero, (#-16, t6) +sh zero, (#-8, t6) +sh zero, (#-4, t6) +sh zero, (#-2, t6) +sh zero, (#-1, t6) +sh zero, (#0, t6) +sh zero, (#1, t6) +sh zero, (#2, t6) +sh zero, (#4, t6) +sh zero, (#8, t6) +sh zero, (#16, t6) +sh zero, (#32, t6) +sh zero, (#64, t6) +sh zero, (#128, t6) +sh zero, (#256, t6) +sh zero, (#512, t6) +sh zero, (#1024, t6) +sh zero, (#2047, t6) +sh ra, (#-2047, zero) +sh ra, (#-1024, zero) +sh ra, (#-512, zero) +sh ra, (#-256, zero) +sh ra, (#-128, zero) +sh ra, (#-64, zero) +sh ra, (#-32, zero) +sh ra, (#-16, zero) +sh ra, (#-8, zero) +sh ra, (#-4, zero) +sh ra, (#-2, zero) +sh ra, (#-1, zero) +sh ra, (#0, zero) +sh ra, (#1, zero) +sh ra, (#2, zero) +sh ra, (#4, zero) +sh ra, (#8, zero) +sh ra, (#16, zero) +sh ra, (#32, zero) +sh ra, (#64, zero) +sh ra, (#128, zero) +sh ra, (#256, zero) +sh ra, (#512, zero) +sh ra, (#1024, zero) +sh ra, (#2047, zero) +sh ra, (#-2047, ra) +sh ra, (#-1024, ra) +sh ra, (#-512, ra) +sh ra, (#-256, ra) +sh ra, (#-128, ra) +sh ra, (#-64, ra) +sh ra, (#-32, ra) +sh ra, (#-16, ra) +sh ra, (#-8, ra) +sh ra, (#-4, ra) +sh ra, (#-2, ra) +sh ra, (#-1, ra) +sh ra, (#0, ra) +sh ra, (#1, ra) +sh ra, (#2, ra) +sh ra, (#4, ra) +sh ra, (#8, ra) +sh ra, (#16, ra) +sh ra, (#32, ra) +sh ra, (#64, ra) +sh ra, (#128, ra) +sh ra, (#256, ra) +sh ra, (#512, ra) +sh ra, (#1024, ra) +sh ra, (#2047, ra) +sh ra, (#-2047, t0) +sh ra, (#-1024, t0) +sh ra, (#-512, t0) +sh ra, (#-256, t0) +sh ra, (#-128, t0) +sh ra, (#-64, t0) +sh ra, (#-32, t0) +sh ra, (#-16, t0) +sh ra, (#-8, t0) +sh ra, (#-4, t0) +sh ra, (#-2, t0) +sh ra, (#-1, t0) +sh ra, (#0, t0) +sh ra, (#1, t0) +sh ra, (#2, t0) +sh ra, (#4, t0) +sh ra, (#8, t0) +sh ra, (#16, t0) +sh ra, (#32, t0) +sh ra, (#64, t0) +sh ra, (#128, t0) +sh ra, (#256, t0) +sh ra, (#512, t0) +sh ra, (#1024, t0) +sh ra, (#2047, t0) +sh ra, (#-2047, a0) +sh ra, (#-1024, a0) +sh ra, (#-512, a0) +sh ra, (#-256, a0) +sh ra, (#-128, a0) +sh ra, (#-64, a0) +sh ra, (#-32, a0) +sh ra, (#-16, a0) +sh ra, (#-8, a0) +sh ra, (#-4, a0) +sh ra, (#-2, a0) +sh ra, (#-1, a0) +sh ra, (#0, a0) +sh ra, (#1, a0) +sh ra, (#2, a0) +sh ra, (#4, a0) +sh ra, (#8, a0) +sh ra, (#16, a0) +sh ra, (#32, a0) +sh ra, (#64, a0) +sh ra, (#128, a0) +sh ra, (#256, a0) +sh ra, (#512, a0) +sh ra, (#1024, a0) +sh ra, (#2047, a0) +sh ra, (#-2047, a5) +sh ra, (#-1024, a5) +sh ra, (#-512, a5) +sh ra, (#-256, a5) +sh ra, (#-128, a5) +sh ra, (#-64, a5) +sh ra, (#-32, a5) +sh ra, (#-16, a5) +sh ra, (#-8, a5) +sh ra, (#-4, a5) +sh ra, (#-2, a5) +sh ra, (#-1, a5) +sh ra, (#0, a5) +sh ra, (#1, a5) +sh ra, (#2, a5) +sh ra, (#4, a5) +sh ra, (#8, a5) +sh ra, (#16, a5) +sh ra, (#32, a5) +sh ra, (#64, a5) +sh ra, (#128, a5) +sh ra, (#256, a5) +sh ra, (#512, a5) +sh ra, (#1024, a5) +sh ra, (#2047, a5) +sh ra, (#-2047, s4) +sh ra, (#-1024, s4) +sh ra, (#-512, s4) +sh ra, (#-256, s4) +sh ra, (#-128, s4) +sh ra, (#-64, s4) +sh ra, (#-32, s4) +sh ra, (#-16, s4) +sh ra, (#-8, s4) +sh ra, (#-4, s4) +sh ra, (#-2, s4) +sh ra, (#-1, s4) +sh ra, (#0, s4) +sh ra, (#1, s4) +sh ra, (#2, s4) +sh ra, (#4, s4) +sh ra, (#8, s4) +sh ra, (#16, s4) +sh ra, (#32, s4) +sh ra, (#64, s4) +sh ra, (#128, s4) +sh ra, (#256, s4) +sh ra, (#512, s4) +sh ra, (#1024, s4) +sh ra, (#2047, s4) +sh ra, (#-2047, s9) +sh ra, (#-1024, s9) +sh ra, (#-512, s9) +sh ra, (#-256, s9) +sh ra, (#-128, s9) +sh ra, (#-64, s9) +sh ra, (#-32, s9) +sh ra, (#-16, s9) +sh ra, (#-8, s9) +sh ra, (#-4, s9) +sh ra, (#-2, s9) +sh ra, (#-1, s9) +sh ra, (#0, s9) +sh ra, (#1, s9) +sh ra, (#2, s9) +sh ra, (#4, s9) +sh ra, (#8, s9) +sh ra, (#16, s9) +sh ra, (#32, s9) +sh ra, (#64, s9) +sh ra, (#128, s9) +sh ra, (#256, s9) +sh ra, (#512, s9) +sh ra, (#1024, s9) +sh ra, (#2047, s9) +sh ra, (#-2047, t6) +sh ra, (#-1024, t6) +sh ra, (#-512, t6) +sh ra, (#-256, t6) +sh ra, (#-128, t6) +sh ra, (#-64, t6) +sh ra, (#-32, t6) +sh ra, (#-16, t6) +sh ra, (#-8, t6) +sh ra, (#-4, t6) +sh ra, (#-2, t6) +sh ra, (#-1, t6) +sh ra, (#0, t6) +sh ra, (#1, t6) +sh ra, (#2, t6) +sh ra, (#4, t6) +sh ra, (#8, t6) +sh ra, (#16, t6) +sh ra, (#32, t6) +sh ra, (#64, t6) +sh ra, (#128, t6) +sh ra, (#256, t6) +sh ra, (#512, t6) +sh ra, (#1024, t6) +sh ra, (#2047, t6) +sh t0, (#-2047, zero) +sh t0, (#-1024, zero) +sh t0, (#-512, zero) +sh t0, (#-256, zero) +sh t0, (#-128, zero) +sh t0, (#-64, zero) +sh t0, (#-32, zero) +sh t0, (#-16, zero) +sh t0, (#-8, zero) +sh t0, (#-4, zero) +sh t0, (#-2, zero) +sh t0, (#-1, zero) +sh t0, (#0, zero) +sh t0, (#1, zero) +sh t0, (#2, zero) +sh t0, (#4, zero) +sh t0, (#8, zero) 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t0) +sh t0, (#128, t0) +sh t0, (#256, t0) +sh t0, (#512, t0) +sh t0, (#1024, t0) +sh t0, (#2047, t0) +sh t0, (#-2047, a0) +sh t0, (#-1024, a0) +sh t0, (#-512, a0) +sh t0, (#-256, a0) +sh t0, (#-128, a0) +sh t0, (#-64, a0) +sh t0, (#-32, a0) +sh t0, (#-16, a0) +sh t0, (#-8, a0) +sh t0, (#-4, a0) +sh t0, (#-2, a0) +sh t0, (#-1, a0) +sh t0, (#0, a0) +sh t0, (#1, a0) +sh t0, (#2, a0) +sh t0, (#4, a0) +sh t0, (#8, a0) +sh t0, (#16, a0) +sh t0, (#32, a0) +sh t0, (#64, a0) +sh t0, (#128, a0) +sh t0, (#256, a0) +sh t0, (#512, a0) +sh t0, (#1024, a0) +sh t0, (#2047, a0) +sh t0, (#-2047, a5) +sh t0, (#-1024, a5) +sh t0, (#-512, a5) +sh t0, (#-256, a5) +sh t0, (#-128, a5) +sh t0, (#-64, a5) +sh t0, (#-32, a5) +sh t0, (#-16, a5) +sh t0, (#-8, a5) +sh t0, (#-4, a5) +sh t0, (#-2, a5) +sh t0, (#-1, a5) +sh t0, (#0, a5) +sh t0, (#1, a5) +sh t0, (#2, a5) +sh t0, (#4, a5) +sh t0, (#8, a5) +sh t0, (#16, a5) +sh t0, (#32, a5) +sh t0, (#64, a5) +sh t0, (#128, a5) +sh t0, (#256, a5) +sh t0, (#512, a5) +sh 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(#16, a0) +sh a5, (#32, a0) +sh a5, (#64, a0) +sh a5, (#128, a0) +sh a5, (#256, a0) +sh a5, (#512, a0) +sh a5, (#1024, a0) +sh a5, (#2047, a0) +sh a5, (#-2047, a5) +sh a5, (#-1024, a5) +sh a5, (#-512, a5) +sh a5, (#-256, a5) +sh a5, (#-128, a5) +sh a5, (#-64, a5) +sh a5, (#-32, a5) +sh a5, (#-16, a5) +sh a5, (#-8, a5) +sh a5, (#-4, a5) +sh a5, (#-2, a5) +sh a5, (#-1, a5) +sh a5, (#0, a5) +sh a5, (#1, a5) +sh a5, (#2, a5) +sh a5, (#4, a5) +sh a5, (#8, a5) +sh a5, (#16, a5) +sh a5, (#32, a5) +sh a5, (#64, a5) +sh a5, (#128, a5) +sh a5, (#256, a5) +sh a5, (#512, a5) +sh a5, (#1024, a5) +sh a5, (#2047, a5) +sh a5, (#-2047, s4) +sh a5, (#-1024, s4) +sh a5, (#-512, s4) +sh a5, (#-256, s4) +sh a5, (#-128, s4) +sh a5, (#-64, s4) +sh a5, (#-32, s4) +sh a5, (#-16, s4) +sh a5, (#-8, s4) +sh a5, (#-4, s4) +sh a5, (#-2, s4) +sh a5, (#-1, s4) +sh a5, (#0, s4) +sh a5, (#1, s4) +sh a5, (#2, s4) +sh a5, (#4, s4) +sh a5, (#8, s4) +sh a5, (#16, s4) +sh a5, (#32, s4) +sh a5, (#64, s4) +sh a5, (#128, s4) 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(#2047, t6) +sh s4, (#-2047, zero) +sh s4, (#-1024, zero) +sh s4, (#-512, zero) +sh s4, (#-256, zero) +sh s4, (#-128, zero) +sh s4, (#-64, zero) +sh s4, (#-32, zero) +sh s4, (#-16, zero) +sh s4, (#-8, zero) +sh s4, (#-4, zero) +sh s4, (#-2, zero) +sh s4, (#-1, zero) +sh s4, (#0, zero) +sh s4, (#1, zero) +sh s4, (#2, zero) +sh s4, (#4, zero) +sh s4, (#8, zero) +sh s4, (#16, zero) +sh s4, (#32, zero) +sh s4, (#64, zero) +sh s4, (#128, zero) +sh s4, (#256, zero) +sh s4, (#512, zero) +sh s4, (#1024, zero) +sh s4, (#2047, zero) +sh s4, (#-2047, ra) +sh s4, (#-1024, ra) +sh s4, (#-512, ra) +sh s4, (#-256, ra) +sh s4, (#-128, ra) +sh s4, (#-64, ra) +sh s4, (#-32, ra) +sh s4, (#-16, ra) +sh s4, (#-8, ra) +sh s4, (#-4, ra) +sh s4, (#-2, ra) +sh s4, (#-1, ra) +sh s4, (#0, ra) +sh s4, (#1, ra) +sh s4, (#2, ra) +sh s4, (#4, ra) +sh s4, (#8, ra) +sh s4, (#16, ra) +sh s4, (#32, ra) +sh s4, (#64, ra) +sh s4, (#128, ra) +sh s4, (#256, ra) +sh s4, (#512, ra) +sh s4, (#1024, ra) +sh s4, (#2047, ra) +sh s4, (#-2047, t0) +sh s4, (#-1024, t0) +sh s4, (#-512, t0) +sh s4, (#-256, t0) +sh s4, (#-128, t0) +sh s4, (#-64, t0) +sh s4, (#-32, t0) +sh s4, (#-16, t0) +sh s4, (#-8, t0) +sh s4, (#-4, t0) +sh s4, (#-2, t0) +sh s4, (#-1, t0) +sh s4, (#0, t0) +sh s4, (#1, t0) +sh s4, (#2, t0) +sh s4, (#4, t0) +sh s4, (#8, t0) +sh s4, (#16, t0) +sh s4, (#32, t0) +sh s4, (#64, t0) +sh s4, (#128, t0) +sh s4, (#256, t0) +sh s4, (#512, t0) +sh s4, (#1024, t0) +sh s4, (#2047, t0) +sh s4, (#-2047, a0) +sh s4, (#-1024, a0) +sh s4, (#-512, a0) +sh s4, (#-256, a0) +sh s4, (#-128, a0) +sh s4, (#-64, a0) +sh s4, (#-32, a0) +sh s4, (#-16, a0) +sh s4, (#-8, a0) +sh s4, (#-4, a0) +sh s4, (#-2, a0) +sh s4, (#-1, a0) +sh s4, (#0, a0) +sh s4, (#1, a0) +sh s4, (#2, a0) +sh s4, (#4, a0) +sh s4, (#8, a0) +sh s4, (#16, a0) +sh s4, (#32, a0) +sh s4, (#64, a0) +sh s4, (#128, a0) +sh s4, (#256, a0) +sh s4, (#512, a0) +sh s4, (#1024, a0) +sh s4, (#2047, a0) +sh s4, (#-2047, a5) +sh s4, (#-1024, a5) +sh s4, (#-512, a5) +sh s4, (#-256, a5) +sh s4, (#-128, a5) +sh s4, (#-64, a5) +sh s4, (#-32, a5) +sh s4, (#-16, a5) +sh s4, (#-8, a5) +sh s4, (#-4, a5) +sh s4, (#-2, a5) +sh s4, (#-1, a5) +sh s4, (#0, a5) +sh s4, (#1, a5) +sh s4, (#2, a5) +sh s4, (#4, a5) +sh s4, (#8, a5) +sh s4, (#16, a5) +sh s4, (#32, a5) +sh s4, (#64, a5) +sh s4, (#128, a5) +sh s4, (#256, a5) +sh s4, (#512, a5) +sh s4, (#1024, a5) +sh s4, (#2047, a5) +sh s4, (#-2047, s4) +sh s4, (#-1024, s4) +sh s4, (#-512, s4) +sh s4, (#-256, s4) +sh s4, (#-128, s4) +sh s4, (#-64, s4) +sh s4, (#-32, s4) +sh s4, (#-16, s4) +sh s4, (#-8, s4) +sh s4, (#-4, s4) +sh s4, (#-2, s4) +sh s4, (#-1, s4) +sh s4, (#0, s4) +sh s4, (#1, s4) +sh s4, (#2, s4) +sh s4, (#4, s4) +sh s4, (#8, s4) +sh s4, (#16, s4) +sh s4, (#32, s4) +sh s4, (#64, s4) +sh s4, (#128, s4) +sh s4, (#256, s4) +sh s4, (#512, s4) +sh s4, (#1024, s4) +sh s4, (#2047, s4) +sh s4, (#-2047, s9) +sh s4, (#-1024, s9) +sh s4, (#-512, s9) +sh s4, (#-256, s9) +sh s4, (#-128, s9) +sh s4, (#-64, s9) +sh s4, (#-32, s9) +sh s4, (#-16, s9) +sh s4, (#-8, s9) +sh s4, (#-4, s9) +sh s4, (#-2, s9) +sh s4, (#-1, s9) +sh s4, (#0, s9) +sh s4, (#1, s9) +sh s4, (#2, s9) +sh s4, (#4, s9) +sh s4, (#8, s9) +sh s4, (#16, s9) +sh s4, (#32, s9) +sh s4, (#64, s9) +sh s4, (#128, s9) +sh s4, (#256, s9) +sh s4, (#512, s9) +sh s4, (#1024, s9) +sh s4, (#2047, s9) +sh s4, (#-2047, t6) +sh s4, (#-1024, t6) +sh s4, (#-512, t6) +sh s4, (#-256, t6) +sh s4, (#-128, t6) +sh s4, (#-64, t6) +sh s4, (#-32, t6) +sh s4, (#-16, t6) +sh s4, (#-8, t6) +sh s4, (#-4, t6) +sh s4, (#-2, t6) +sh s4, (#-1, t6) +sh s4, (#0, t6) +sh s4, (#1, t6) +sh s4, (#2, t6) +sh s4, (#4, t6) +sh s4, (#8, t6) +sh s4, (#16, t6) +sh s4, (#32, t6) +sh s4, (#64, t6) +sh s4, (#128, t6) +sh s4, (#256, t6) +sh s4, (#512, t6) +sh s4, (#1024, t6) +sh s4, (#2047, t6) +sh s9, (#-2047, zero) +sh s9, (#-1024, zero) +sh s9, (#-512, zero) +sh s9, (#-256, zero) +sh s9, (#-128, zero) +sh s9, (#-64, zero) +sh s9, (#-32, zero) +sh s9, (#-16, zero) +sh s9, (#-8, zero) +sh s9, (#-4, zero) +sh s9, (#-2, zero) +sh s9, (#-1, zero) +sh s9, (#0, zero) +sh s9, (#1, zero) +sh s9, (#2, zero) +sh s9, (#4, zero) +sh s9, (#8, zero) +sh s9, (#16, zero) +sh s9, (#32, zero) +sh s9, (#64, zero) +sh s9, (#128, zero) +sh s9, (#256, zero) +sh s9, (#512, zero) +sh s9, (#1024, zero) +sh s9, (#2047, zero) +sh s9, (#-2047, ra) +sh s9, (#-1024, ra) +sh s9, (#-512, ra) +sh s9, (#-256, ra) +sh s9, (#-128, ra) +sh s9, (#-64, ra) +sh s9, (#-32, ra) +sh s9, (#-16, ra) +sh s9, (#-8, ra) +sh s9, (#-4, ra) +sh s9, (#-2, ra) +sh s9, (#-1, ra) +sh s9, (#0, ra) +sh s9, (#1, ra) +sh s9, (#2, ra) +sh s9, (#4, ra) +sh s9, (#8, ra) +sh s9, (#16, ra) +sh s9, (#32, ra) +sh s9, (#64, ra) +sh s9, (#128, ra) +sh s9, (#256, ra) +sh s9, (#512, ra) +sh s9, (#1024, ra) +sh s9, (#2047, ra) +sh s9, (#-2047, t0) +sh s9, (#-1024, t0) +sh s9, (#-512, t0) +sh s9, (#-256, t0) +sh s9, (#-128, t0) +sh s9, (#-64, t0) +sh s9, (#-32, t0) +sh s9, (#-16, t0) +sh s9, (#-8, t0) +sh s9, (#-4, t0) +sh s9, (#-2, t0) +sh s9, (#-1, t0) +sh s9, (#0, t0) +sh s9, (#1, t0) +sh s9, (#2, t0) +sh s9, (#4, t0) +sh s9, (#8, t0) +sh s9, (#16, t0) +sh s9, (#32, t0) +sh s9, (#64, t0) +sh s9, (#128, t0) +sh s9, (#256, t0) +sh s9, (#512, t0) +sh s9, (#1024, t0) +sh s9, (#2047, t0) +sh s9, (#-2047, a0) +sh s9, (#-1024, a0) +sh s9, (#-512, a0) +sh s9, (#-256, a0) +sh s9, (#-128, a0) +sh s9, (#-64, a0) +sh s9, (#-32, a0) +sh s9, (#-16, a0) +sh s9, (#-8, a0) +sh s9, (#-4, a0) +sh s9, (#-2, a0) +sh s9, (#-1, a0) +sh s9, (#0, a0) +sh s9, (#1, a0) +sh s9, (#2, a0) +sh s9, (#4, a0) +sh s9, (#8, a0) +sh s9, (#16, a0) +sh s9, (#32, a0) +sh s9, (#64, a0) +sh s9, (#128, a0) +sh s9, (#256, a0) +sh s9, (#512, a0) +sh s9, (#1024, a0) +sh s9, (#2047, a0) +sh s9, (#-2047, a5) +sh s9, (#-1024, a5) +sh s9, (#-512, a5) +sh s9, (#-256, a5) +sh s9, (#-128, a5) +sh s9, (#-64, a5) +sh s9, (#-32, a5) +sh s9, (#-16, a5) +sh s9, (#-8, a5) +sh s9, (#-4, a5) +sh s9, (#-2, a5) +sh s9, (#-1, a5) +sh s9, (#0, a5) +sh s9, (#1, a5) +sh s9, (#2, a5) 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s9) +sh s9, (#64, s9) +sh s9, (#128, s9) +sh s9, (#256, s9) +sh s9, (#512, s9) +sh s9, (#1024, s9) +sh s9, (#2047, s9) +sh s9, (#-2047, t6) +sh s9, (#-1024, t6) +sh s9, (#-512, t6) +sh s9, (#-256, t6) +sh s9, (#-128, t6) +sh s9, (#-64, t6) +sh s9, (#-32, t6) +sh s9, (#-16, t6) +sh s9, (#-8, t6) +sh s9, (#-4, t6) +sh s9, (#-2, t6) +sh s9, (#-1, t6) +sh s9, (#0, t6) +sh s9, (#1, t6) +sh s9, (#2, t6) +sh s9, (#4, t6) +sh s9, (#8, t6) +sh s9, (#16, t6) +sh s9, (#32, t6) +sh s9, (#64, t6) +sh s9, (#128, t6) +sh s9, (#256, t6) +sh s9, (#512, t6) +sh s9, (#1024, t6) +sh s9, (#2047, t6) +sh t6, (#-2047, zero) +sh t6, (#-1024, zero) +sh t6, (#-512, zero) +sh t6, (#-256, zero) +sh t6, (#-128, zero) +sh t6, (#-64, zero) +sh t6, (#-32, zero) +sh t6, (#-16, zero) +sh t6, (#-8, zero) +sh t6, (#-4, zero) +sh t6, (#-2, zero) +sh t6, (#-1, zero) +sh t6, (#0, zero) +sh t6, (#1, zero) +sh t6, (#2, zero) +sh t6, (#4, zero) +sh t6, (#8, zero) +sh t6, (#16, zero) +sh t6, (#32, zero) +sh t6, (#64, zero) +sh t6, (#128, zero) +sh t6, (#256, zero) +sh t6, (#512, zero) +sh t6, (#1024, zero) +sh t6, (#2047, zero) +sh t6, (#-2047, ra) +sh t6, (#-1024, ra) +sh t6, (#-512, ra) +sh t6, (#-256, ra) +sh t6, (#-128, ra) +sh t6, (#-64, ra) +sh t6, (#-32, ra) +sh t6, (#-16, ra) +sh t6, (#-8, ra) +sh t6, (#-4, ra) +sh t6, (#-2, ra) +sh t6, (#-1, ra) +sh t6, (#0, ra) +sh t6, (#1, ra) +sh t6, (#2, ra) +sh t6, (#4, ra) +sh t6, (#8, ra) +sh t6, (#16, ra) +sh t6, (#32, ra) +sh t6, (#64, ra) +sh t6, (#128, ra) +sh t6, (#256, ra) +sh t6, (#512, ra) +sh t6, (#1024, ra) +sh t6, (#2047, ra) +sh t6, (#-2047, t0) +sh t6, (#-1024, t0) +sh t6, (#-512, t0) +sh t6, (#-256, t0) +sh t6, (#-128, t0) +sh t6, (#-64, t0) +sh t6, (#-32, t0) +sh t6, (#-16, t0) +sh t6, (#-8, t0) +sh t6, (#-4, t0) +sh t6, (#-2, t0) +sh t6, (#-1, t0) +sh t6, (#0, t0) +sh t6, (#1, t0) +sh t6, (#2, t0) +sh t6, (#4, t0) +sh t6, (#8, t0) +sh t6, (#16, t0) +sh t6, (#32, t0) +sh t6, (#64, t0) +sh t6, (#128, t0) +sh t6, (#256, t0) +sh t6, (#512, t0) +sh t6, (#1024, t0) +sh t6, (#2047, t0) +sh t6, (#-2047, a0) +sh t6, (#-1024, a0) +sh t6, (#-512, a0) +sh t6, (#-256, a0) +sh t6, (#-128, a0) +sh t6, (#-64, a0) +sh t6, (#-32, a0) +sh t6, (#-16, a0) +sh t6, (#-8, a0) +sh t6, (#-4, a0) +sh t6, (#-2, a0) +sh t6, (#-1, a0) +sh t6, (#0, a0) +sh t6, (#1, a0) +sh t6, (#2, a0) +sh t6, (#4, a0) +sh t6, (#8, a0) +sh t6, (#16, a0) +sh t6, (#32, a0) +sh t6, (#64, a0) +sh t6, (#128, a0) +sh t6, (#256, a0) +sh t6, (#512, a0) +sh t6, (#1024, a0) +sh t6, (#2047, a0) +sh t6, (#-2047, a5) +sh t6, (#-1024, a5) +sh t6, (#-512, a5) +sh t6, (#-256, a5) +sh t6, (#-128, a5) +sh t6, (#-64, a5) +sh t6, (#-32, a5) +sh t6, (#-16, a5) +sh t6, (#-8, a5) +sh t6, (#-4, a5) +sh t6, (#-2, a5) +sh t6, (#-1, a5) +sh t6, (#0, a5) +sh t6, (#1, a5) +sh t6, (#2, a5) +sh t6, (#4, a5) +sh t6, (#8, a5) +sh t6, (#16, a5) +sh t6, (#32, a5) +sh t6, (#64, a5) +sh t6, (#128, a5) +sh t6, (#256, a5) +sh t6, (#512, a5) +sh t6, (#1024, a5) +sh t6, (#2047, a5) +sh t6, (#-2047, s4) +sh t6, (#-1024, s4) +sh t6, (#-512, s4) +sh t6, (#-256, s4) +sh t6, (#-128, s4) +sh t6, (#-64, s4) +sh t6, (#-32, s4) +sh t6, (#-16, s4) +sh t6, (#-8, s4) +sh t6, (#-4, s4) +sh t6, (#-2, s4) +sh t6, (#-1, s4) +sh t6, (#0, s4) +sh t6, (#1, s4) +sh t6, (#2, s4) +sh t6, (#4, s4) +sh t6, (#8, s4) +sh t6, (#16, s4) +sh t6, (#32, s4) +sh t6, (#64, s4) +sh t6, (#128, s4) +sh t6, (#256, s4) +sh t6, (#512, s4) +sh t6, (#1024, s4) +sh t6, (#2047, s4) +sh t6, (#-2047, s9) +sh t6, (#-1024, s9) +sh t6, (#-512, s9) +sh t6, (#-256, s9) +sh t6, (#-128, s9) +sh t6, (#-64, s9) +sh t6, (#-32, s9) +sh t6, (#-16, s9) +sh t6, (#-8, s9) +sh t6, (#-4, s9) +sh t6, (#-2, s9) +sh t6, (#-1, s9) +sh t6, (#0, s9) +sh t6, (#1, s9) +sh t6, (#2, s9) +sh t6, (#4, s9) +sh t6, (#8, s9) +sh t6, (#16, s9) +sh t6, (#32, s9) +sh t6, (#64, s9) +sh t6, (#128, s9) +sh t6, (#256, s9) +sh t6, (#512, s9) +sh t6, (#1024, s9) +sh t6, (#2047, s9) +sh t6, (#-2047, t6) +sh t6, (#-1024, t6) +sh t6, (#-512, t6) +sh t6, (#-256, t6) +sh t6, (#-128, t6) +sh t6, (#-64, t6) +sh t6, (#-32, t6) +sh t6, (#-16, t6) +sh t6, (#-8, t6) +sh t6, (#-4, t6) +sh t6, (#-2, t6) +sh t6, (#-1, t6) +sh t6, (#0, t6) +sh t6, (#1, t6) +sh t6, (#2, t6) +sh t6, (#4, t6) +sh t6, (#8, t6) +sh t6, (#16, t6) +sh t6, (#32, t6) +sh t6, (#64, t6) +sh t6, (#128, t6) +sh t6, (#256, t6) +sh t6, (#512, t6) +sh t6, (#1024, t6) +sh t6, (#2047, t6) diff --git a/tests/riscv/rv32i/sll.asm b/tests/riscv/rv32i/sll.asm new file mode 100644 index 0000000..2689226 --- /dev/null +++ b/tests/riscv/rv32i/sll.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +sll zero, zero, zero +sll zero, zero, ra +sll zero, zero, t0 +sll zero, zero, a0 +sll zero, zero, a5 +sll zero, zero, s4 +sll zero, zero, s9 +sll zero, zero, t6 +sll zero, ra, zero +sll zero, ra, ra +sll zero, ra, t0 +sll zero, ra, a0 +sll zero, ra, a5 +sll zero, ra, s4 +sll zero, ra, s9 +sll zero, ra, t6 +sll zero, t0, zero +sll zero, t0, ra +sll zero, t0, t0 +sll zero, t0, a0 +sll zero, t0, a5 +sll zero, t0, s4 +sll zero, t0, s9 +sll zero, t0, t6 +sll zero, a0, zero +sll zero, a0, ra +sll zero, a0, t0 +sll zero, a0, a0 +sll zero, a0, a5 +sll zero, a0, s4 +sll zero, a0, s9 +sll zero, a0, t6 +sll zero, a5, zero +sll zero, a5, ra +sll zero, a5, t0 +sll zero, a5, a0 +sll zero, a5, a5 +sll zero, a5, s4 +sll zero, a5, s9 +sll zero, a5, t6 +sll zero, s4, zero +sll zero, s4, ra +sll zero, s4, t0 +sll zero, s4, a0 +sll zero, s4, a5 +sll zero, s4, s4 +sll zero, s4, s9 +sll zero, s4, t6 +sll zero, s9, zero +sll zero, s9, ra +sll zero, s9, t0 +sll zero, s9, a0 +sll zero, s9, a5 +sll zero, s9, s4 +sll zero, s9, s9 +sll zero, s9, t6 +sll zero, t6, zero +sll zero, t6, ra +sll zero, t6, t0 +sll zero, t6, a0 +sll zero, t6, a5 +sll zero, t6, s4 +sll zero, t6, s9 +sll zero, t6, t6 +sll ra, zero, zero +sll ra, zero, ra +sll ra, zero, t0 +sll ra, zero, a0 +sll ra, zero, a5 +sll ra, zero, s4 +sll ra, zero, s9 +sll ra, zero, t6 +sll ra, ra, zero +sll ra, ra, ra +sll ra, ra, t0 +sll ra, ra, a0 +sll ra, ra, a5 +sll ra, ra, s4 +sll ra, ra, s9 +sll ra, ra, t6 +sll ra, t0, zero +sll ra, t0, ra +sll ra, t0, t0 +sll ra, t0, a0 +sll ra, t0, a5 +sll ra, t0, s4 +sll ra, t0, s9 +sll ra, t0, t6 +sll ra, a0, zero +sll ra, a0, ra +sll ra, a0, t0 +sll ra, a0, a0 +sll ra, a0, a5 +sll ra, a0, s4 +sll ra, a0, s9 +sll ra, a0, t6 +sll ra, a5, zero +sll ra, a5, ra +sll ra, a5, t0 +sll ra, a5, a0 +sll ra, a5, a5 +sll ra, a5, s4 +sll ra, a5, s9 +sll ra, a5, t6 +sll ra, s4, zero +sll ra, s4, ra +sll ra, s4, t0 +sll ra, s4, a0 +sll ra, s4, a5 +sll ra, s4, s4 +sll ra, s4, s9 +sll ra, s4, t6 +sll ra, s9, zero +sll ra, s9, ra +sll ra, s9, t0 +sll ra, s9, a0 +sll ra, s9, a5 +sll ra, s9, s4 +sll ra, s9, s9 +sll ra, s9, t6 +sll ra, t6, zero +sll ra, t6, ra +sll ra, t6, t0 +sll ra, t6, a0 +sll ra, t6, a5 +sll ra, t6, s4 +sll ra, t6, s9 +sll ra, t6, t6 +sll t0, zero, zero +sll t0, zero, ra +sll t0, zero, t0 +sll t0, zero, a0 +sll t0, zero, a5 +sll t0, zero, s4 +sll t0, zero, s9 +sll t0, zero, t6 +sll t0, ra, zero +sll t0, ra, ra +sll t0, ra, t0 +sll t0, ra, a0 +sll t0, ra, a5 +sll t0, ra, s4 +sll t0, ra, s9 +sll t0, ra, t6 +sll t0, t0, zero +sll t0, t0, ra +sll t0, t0, t0 +sll t0, t0, a0 +sll t0, t0, a5 +sll t0, t0, s4 +sll t0, t0, s9 +sll t0, t0, t6 +sll t0, a0, zero +sll t0, a0, ra +sll t0, a0, t0 +sll t0, a0, a0 +sll t0, a0, a5 +sll t0, a0, s4 +sll t0, a0, s9 +sll t0, a0, t6 +sll t0, a5, zero +sll t0, a5, ra +sll t0, a5, t0 +sll t0, a5, a0 +sll t0, a5, a5 +sll t0, a5, s4 +sll t0, a5, s9 +sll t0, a5, t6 +sll t0, s4, zero +sll t0, s4, ra +sll t0, s4, t0 +sll t0, s4, a0 +sll t0, s4, a5 +sll t0, s4, s4 +sll t0, s4, s9 +sll t0, s4, t6 +sll t0, s9, zero +sll t0, s9, ra +sll t0, s9, t0 +sll t0, s9, a0 +sll t0, s9, a5 +sll t0, s9, s4 +sll t0, s9, s9 +sll t0, s9, t6 +sll t0, t6, zero +sll t0, t6, ra +sll t0, t6, t0 +sll t0, t6, a0 +sll t0, t6, a5 +sll t0, t6, s4 +sll t0, t6, s9 +sll t0, t6, t6 +sll a0, zero, zero +sll a0, zero, ra +sll a0, zero, t0 +sll a0, zero, a0 +sll a0, zero, a5 +sll a0, zero, s4 +sll a0, zero, s9 +sll a0, zero, t6 +sll a0, ra, zero +sll a0, ra, ra +sll a0, ra, t0 +sll a0, ra, a0 +sll a0, ra, a5 +sll a0, ra, s4 +sll a0, ra, s9 +sll a0, ra, t6 +sll a0, t0, zero +sll a0, t0, ra +sll a0, t0, t0 +sll a0, t0, a0 +sll a0, t0, a5 +sll a0, t0, s4 +sll a0, t0, s9 +sll a0, t0, t6 +sll a0, a0, zero +sll a0, a0, ra +sll a0, a0, t0 +sll a0, a0, a0 +sll a0, a0, a5 +sll a0, a0, s4 +sll a0, a0, s9 +sll a0, a0, t6 +sll a0, a5, zero +sll a0, a5, ra +sll a0, a5, t0 +sll a0, a5, a0 +sll a0, a5, a5 +sll a0, a5, s4 +sll a0, a5, s9 +sll a0, a5, t6 +sll a0, s4, zero +sll a0, s4, ra +sll a0, s4, t0 +sll a0, s4, a0 +sll a0, s4, a5 +sll a0, s4, s4 +sll a0, s4, s9 +sll a0, s4, t6 +sll a0, s9, zero +sll a0, s9, ra +sll a0, s9, t0 +sll a0, s9, a0 +sll a0, s9, a5 +sll a0, s9, s4 +sll a0, s9, s9 +sll a0, s9, t6 +sll a0, t6, zero +sll a0, t6, ra +sll a0, t6, t0 +sll a0, t6, a0 +sll a0, t6, a5 +sll a0, t6, s4 +sll a0, t6, s9 +sll a0, t6, t6 +sll a5, zero, zero +sll a5, zero, ra +sll a5, zero, t0 +sll a5, zero, a0 +sll a5, zero, a5 +sll a5, zero, s4 +sll a5, zero, s9 +sll a5, zero, t6 +sll a5, ra, zero +sll a5, ra, ra +sll a5, ra, t0 +sll a5, ra, a0 +sll a5, ra, a5 +sll a5, ra, s4 +sll a5, ra, s9 +sll a5, ra, t6 +sll a5, t0, zero +sll a5, t0, ra +sll a5, t0, t0 +sll a5, t0, a0 +sll a5, t0, a5 +sll a5, t0, s4 +sll a5, t0, s9 +sll a5, t0, t6 +sll a5, a0, zero +sll a5, a0, ra +sll a5, a0, t0 +sll a5, a0, a0 +sll a5, a0, a5 +sll a5, a0, s4 +sll a5, a0, s9 +sll a5, a0, t6 +sll a5, a5, zero +sll a5, a5, ra +sll a5, a5, t0 +sll a5, a5, a0 +sll a5, a5, a5 +sll a5, a5, s4 +sll a5, a5, s9 +sll a5, a5, t6 +sll a5, s4, zero +sll a5, s4, ra +sll a5, s4, t0 +sll a5, s4, a0 +sll a5, s4, a5 +sll a5, s4, s4 +sll a5, s4, s9 +sll a5, s4, t6 +sll a5, s9, zero +sll a5, s9, ra +sll a5, s9, t0 +sll a5, s9, a0 +sll a5, s9, a5 +sll a5, s9, s4 +sll a5, s9, s9 +sll a5, s9, t6 +sll a5, t6, zero +sll a5, t6, ra +sll a5, t6, t0 +sll a5, t6, a0 +sll a5, t6, a5 +sll a5, t6, s4 +sll a5, t6, s9 +sll a5, t6, t6 +sll s4, zero, zero +sll s4, zero, ra +sll s4, zero, t0 +sll s4, zero, a0 +sll s4, zero, a5 +sll s4, zero, s4 +sll s4, zero, s9 +sll s4, zero, t6 +sll s4, ra, zero +sll s4, ra, ra +sll s4, ra, t0 +sll s4, ra, a0 +sll s4, ra, a5 +sll s4, ra, s4 +sll s4, ra, s9 +sll s4, ra, t6 +sll s4, t0, zero +sll s4, t0, ra +sll s4, t0, t0 +sll s4, t0, a0 +sll s4, t0, a5 +sll s4, t0, s4 +sll s4, t0, s9 +sll s4, t0, t6 +sll s4, a0, zero +sll s4, a0, ra +sll s4, a0, t0 +sll s4, a0, a0 +sll s4, a0, a5 +sll s4, a0, s4 +sll s4, a0, s9 +sll s4, a0, t6 +sll s4, a5, zero +sll s4, a5, ra +sll s4, a5, t0 +sll s4, a5, a0 +sll s4, a5, a5 +sll s4, a5, s4 +sll s4, a5, s9 +sll s4, a5, t6 +sll s4, s4, zero +sll s4, s4, ra +sll s4, s4, t0 +sll s4, s4, a0 +sll s4, s4, a5 +sll s4, s4, s4 +sll s4, s4, s9 +sll s4, s4, t6 +sll s4, s9, zero +sll s4, s9, ra +sll s4, s9, t0 +sll s4, s9, a0 +sll s4, s9, a5 +sll s4, s9, s4 +sll s4, s9, s9 +sll s4, s9, t6 +sll s4, t6, zero +sll s4, t6, ra +sll s4, t6, t0 +sll s4, t6, a0 +sll s4, t6, a5 +sll s4, t6, s4 +sll s4, t6, s9 +sll s4, t6, t6 +sll s9, zero, zero +sll s9, zero, ra +sll s9, zero, t0 +sll s9, zero, a0 +sll s9, zero, a5 +sll s9, zero, s4 +sll s9, zero, s9 +sll s9, zero, t6 +sll s9, ra, zero +sll s9, ra, ra +sll s9, ra, t0 +sll s9, ra, a0 +sll s9, ra, a5 +sll s9, ra, s4 +sll s9, ra, s9 +sll s9, ra, t6 +sll s9, t0, zero +sll s9, t0, ra +sll s9, t0, t0 +sll s9, t0, a0 +sll s9, t0, a5 +sll s9, t0, s4 +sll s9, t0, s9 +sll s9, t0, t6 +sll s9, a0, zero +sll s9, a0, ra +sll s9, a0, t0 +sll s9, a0, a0 +sll s9, a0, a5 +sll s9, a0, s4 +sll s9, a0, s9 +sll s9, a0, t6 +sll s9, a5, zero +sll s9, a5, ra +sll s9, a5, t0 +sll s9, a5, a0 +sll s9, a5, a5 +sll s9, a5, s4 +sll s9, a5, s9 +sll s9, a5, t6 +sll s9, s4, zero +sll s9, s4, ra +sll s9, s4, t0 +sll s9, s4, a0 +sll s9, s4, a5 +sll s9, s4, s4 +sll s9, s4, s9 +sll s9, s4, t6 +sll s9, s9, zero +sll s9, s9, ra +sll s9, s9, t0 +sll s9, s9, a0 +sll s9, s9, a5 +sll s9, s9, s4 +sll s9, s9, s9 +sll s9, s9, t6 +sll s9, t6, zero +sll s9, t6, ra +sll s9, t6, t0 +sll s9, t6, a0 +sll s9, t6, a5 +sll s9, t6, s4 +sll s9, t6, s9 +sll s9, t6, t6 +sll t6, zero, zero +sll t6, zero, ra +sll t6, zero, t0 +sll t6, zero, a0 +sll t6, zero, a5 +sll t6, zero, s4 +sll t6, zero, s9 +sll t6, zero, t6 +sll t6, ra, zero +sll t6, ra, ra +sll t6, ra, t0 +sll t6, ra, a0 +sll t6, ra, a5 +sll t6, ra, s4 +sll t6, ra, s9 +sll t6, ra, t6 +sll t6, t0, zero +sll t6, t0, ra +sll t6, t0, t0 +sll t6, t0, a0 +sll t6, t0, a5 +sll t6, t0, s4 +sll t6, t0, s9 +sll t6, t0, t6 +sll t6, a0, zero +sll t6, a0, ra +sll t6, a0, t0 +sll t6, a0, a0 +sll t6, a0, a5 +sll t6, a0, s4 +sll t6, a0, s9 +sll t6, a0, t6 +sll t6, a5, zero +sll t6, a5, ra +sll t6, a5, t0 +sll t6, a5, a0 +sll t6, a5, a5 +sll t6, a5, s4 +sll t6, a5, s9 +sll t6, a5, t6 +sll t6, s4, zero +sll t6, s4, ra +sll t6, s4, t0 +sll t6, s4, a0 +sll t6, s4, a5 +sll t6, s4, s4 +sll t6, s4, s9 +sll t6, s4, t6 +sll t6, s9, zero +sll t6, s9, ra +sll t6, s9, t0 +sll t6, s9, a0 +sll t6, s9, a5 +sll t6, s9, s4 +sll t6, s9, s9 +sll t6, s9, t6 +sll t6, t6, zero +sll t6, t6, ra +sll t6, t6, t0 +sll t6, t6, a0 +sll t6, t6, a5 +sll t6, t6, s4 +sll t6, t6, s9 +sll t6, t6, t6 + diff --git a/tests/riscv/rv32i/sll.bin b/tests/riscv/rv32i/sll.bin new file mode 100644 index 0000000000000000000000000000000000000000..186b2980762dfda5a2394780ba36f2158b4958c7 GIT binary patch literal 2048 zcmWmC;f9?%9EI`jQl&~qh!7zcF*k6ODph)vDph(*TZj-LN2yY!AKn|QVGLuK^V=U5 zd;eFwJf3xZ_2kL*)s_4!|H)tZ=X8B_mcOU#v;M3<>(BbL{;WUi&zJtG|3N;=ce#<* z?oDodPq~w~?nCapdEtGQFY-(7<(>PKdv9KPU*xO& zmIrz7zT`n(`CsLm{EPq~w~?nCapdEtGQFY-(7<(>PK zdv9KPU*xO&mIrz7zT`n(`CsLm{EHz7 zw@Z(|;cxgG{)WHdZ}=PjfIr|5_yhicKj07e1OA4;;cxgG{)WHdZ}=PjfIr|5_yhic zKj07e1OA4;;cxgG{)WHdZ}=PjhQHx&_#6I)zu|BA+vDjv+IO_?Xy4JkqkTvFj`khx zyX(8Y>$|?|yT0rDrMLfX|K0w({dfEC_TTNl+kdqGX#dgvqy0zwkM zyZv|j@AlvAzw@8?P5dT)6TgYy#Bbs^@jLWGKlDRC^g}=NgT2B zfAT;1pZrh$C;yZG$$#cQ^Pl<8{Ad0%|C#^H|Kxx2Klz{hPyQ$WlmE$o=0EeF`Oo}k z{xkoX|IGj7fAT;1pZrh$C;yZG$^Ybk@;~{X{7?QT|C9g8f8n?ATlg*f7JduAh2O&O z(l7neFa6Rl{nD>X&;R0o@xS;(zhK_+R`l z{ulp?|H6Oazwlr9FZ>t&3;%`x#sA`e@xS3;=v%wGTi literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/sll.disasm b/tests/riscv/rv32i/sll.disasm new file mode 100644 index 0000000..90c29f3 --- /dev/null +++ b/tests/riscv/rv32i/sll.disasm @@ -0,0 +1,512 @@ +sll zero, zero, zero +sll zero, zero, ra +sll zero, zero, t0 +sll zero, zero, a0 +sll zero, zero, a5 +sll zero, zero, s4 +sll zero, zero, s9 +sll zero, zero, t6 +sll zero, ra, zero +sll zero, ra, ra +sll zero, ra, t0 +sll zero, ra, a0 +sll zero, ra, a5 +sll zero, ra, s4 +sll zero, ra, s9 +sll zero, ra, t6 +sll zero, t0, zero +sll zero, t0, ra +sll zero, t0, t0 +sll zero, t0, a0 +sll zero, t0, a5 +sll zero, t0, s4 +sll zero, t0, s9 +sll zero, t0, t6 +sll zero, a0, zero +sll zero, a0, ra +sll zero, a0, t0 +sll zero, a0, a0 +sll zero, a0, a5 +sll zero, a0, s4 +sll zero, a0, s9 +sll zero, a0, t6 +sll zero, a5, zero +sll zero, a5, ra +sll zero, a5, t0 +sll zero, a5, a0 +sll zero, a5, a5 +sll zero, a5, s4 +sll zero, a5, s9 +sll zero, a5, t6 +sll zero, s4, zero +sll zero, s4, ra +sll zero, s4, t0 +sll zero, s4, a0 +sll zero, s4, a5 +sll zero, s4, s4 +sll zero, s4, s9 +sll zero, s4, t6 +sll zero, s9, zero +sll zero, s9, ra +sll zero, s9, t0 +sll zero, s9, a0 +sll zero, s9, a5 +sll zero, s9, s4 +sll zero, s9, s9 +sll zero, s9, t6 +sll zero, t6, zero +sll zero, t6, ra +sll zero, t6, t0 +sll zero, t6, a0 +sll zero, t6, a5 +sll zero, t6, s4 +sll zero, t6, s9 +sll zero, t6, t6 +sll ra, zero, zero +sll ra, zero, ra +sll ra, zero, t0 +sll ra, zero, a0 +sll ra, zero, a5 +sll ra, zero, s4 +sll ra, zero, s9 +sll ra, zero, t6 +sll ra, ra, zero +sll ra, ra, ra +sll ra, ra, t0 +sll ra, ra, a0 +sll ra, ra, a5 +sll ra, ra, s4 +sll ra, ra, s9 +sll ra, ra, t6 +sll ra, t0, zero +sll ra, t0, ra +sll ra, t0, t0 +sll ra, t0, a0 +sll ra, t0, a5 +sll ra, t0, s4 +sll ra, t0, s9 +sll ra, t0, t6 +sll ra, a0, zero +sll ra, a0, ra +sll ra, a0, t0 +sll ra, a0, a0 +sll ra, a0, a5 +sll ra, a0, s4 +sll ra, a0, s9 +sll ra, a0, t6 +sll ra, a5, zero +sll ra, a5, ra +sll ra, a5, t0 +sll ra, a5, a0 +sll ra, a5, a5 +sll ra, a5, s4 +sll ra, a5, s9 +sll ra, a5, t6 +sll ra, s4, zero +sll ra, s4, ra +sll ra, s4, t0 +sll ra, s4, a0 +sll ra, s4, a5 +sll ra, s4, s4 +sll ra, s4, s9 +sll ra, s4, t6 +sll ra, s9, zero +sll ra, s9, ra +sll ra, s9, t0 +sll ra, s9, a0 +sll ra, s9, a5 +sll ra, s9, s4 +sll ra, s9, s9 +sll ra, s9, t6 +sll ra, t6, zero +sll ra, t6, ra +sll ra, t6, t0 +sll ra, t6, a0 +sll ra, t6, a5 +sll ra, t6, s4 +sll ra, t6, s9 +sll ra, t6, t6 +sll t0, zero, zero +sll t0, zero, ra +sll t0, zero, t0 +sll t0, zero, a0 +sll t0, zero, a5 +sll t0, zero, s4 +sll t0, zero, s9 +sll t0, zero, t6 +sll t0, ra, zero +sll t0, ra, ra +sll t0, ra, t0 +sll t0, ra, a0 +sll t0, ra, a5 +sll t0, ra, s4 +sll t0, ra, s9 +sll t0, ra, t6 +sll t0, t0, zero +sll t0, t0, ra +sll t0, t0, t0 +sll t0, t0, a0 +sll t0, t0, a5 +sll t0, t0, s4 +sll t0, t0, s9 +sll t0, t0, t6 +sll t0, a0, zero +sll t0, a0, ra +sll t0, a0, t0 +sll t0, a0, a0 +sll t0, a0, a5 +sll t0, a0, s4 +sll t0, a0, s9 +sll t0, a0, t6 +sll t0, a5, zero +sll t0, a5, ra +sll t0, a5, t0 +sll t0, a5, a0 +sll t0, a5, a5 +sll t0, a5, s4 +sll t0, a5, s9 +sll t0, a5, t6 +sll t0, s4, zero +sll t0, s4, ra +sll t0, s4, t0 +sll t0, s4, a0 +sll t0, s4, a5 +sll t0, s4, s4 +sll t0, s4, s9 +sll t0, s4, t6 +sll t0, s9, zero +sll t0, s9, ra +sll t0, s9, t0 +sll t0, s9, a0 +sll t0, s9, a5 +sll t0, s9, s4 +sll t0, s9, s9 +sll t0, s9, t6 +sll t0, t6, zero +sll t0, t6, ra +sll t0, t6, t0 +sll t0, t6, a0 +sll t0, t6, a5 +sll t0, t6, s4 +sll t0, t6, s9 +sll t0, t6, t6 +sll a0, zero, zero +sll a0, zero, ra +sll a0, zero, t0 +sll a0, zero, a0 +sll a0, zero, a5 +sll a0, zero, s4 +sll a0, zero, s9 +sll a0, zero, t6 +sll a0, ra, zero +sll a0, ra, ra +sll a0, ra, t0 +sll a0, ra, a0 +sll a0, ra, a5 +sll a0, ra, s4 +sll a0, ra, s9 +sll a0, ra, t6 +sll a0, t0, zero +sll a0, t0, ra +sll a0, t0, t0 +sll a0, t0, a0 +sll a0, t0, a5 +sll a0, t0, s4 +sll a0, t0, s9 +sll a0, t0, t6 +sll a0, a0, zero +sll a0, a0, ra +sll a0, a0, t0 +sll a0, a0, a0 +sll a0, a0, a5 +sll a0, a0, s4 +sll a0, a0, s9 +sll a0, a0, t6 +sll a0, a5, zero +sll a0, a5, ra +sll a0, a5, t0 +sll a0, a5, a0 +sll a0, a5, a5 +sll a0, a5, s4 +sll a0, a5, s9 +sll a0, a5, t6 +sll a0, s4, zero +sll a0, s4, ra +sll a0, s4, t0 +sll a0, s4, a0 +sll a0, s4, a5 +sll a0, s4, s4 +sll a0, s4, s9 +sll a0, s4, t6 +sll a0, s9, zero +sll a0, s9, ra +sll a0, s9, t0 +sll a0, s9, a0 +sll a0, s9, a5 +sll a0, s9, s4 +sll a0, s9, s9 +sll a0, s9, t6 +sll a0, t6, zero +sll a0, t6, ra +sll a0, t6, t0 +sll a0, t6, a0 +sll a0, t6, a5 +sll a0, t6, s4 +sll a0, t6, s9 +sll a0, t6, t6 +sll a5, zero, zero +sll a5, zero, ra +sll a5, zero, t0 +sll a5, zero, a0 +sll a5, zero, a5 +sll a5, zero, s4 +sll a5, zero, s9 +sll a5, zero, t6 +sll a5, ra, zero +sll a5, ra, ra +sll a5, ra, t0 +sll a5, ra, a0 +sll a5, ra, a5 +sll a5, ra, s4 +sll a5, ra, s9 +sll a5, ra, t6 +sll a5, t0, zero +sll a5, t0, ra +sll a5, t0, t0 +sll a5, t0, a0 +sll a5, t0, a5 +sll a5, t0, s4 +sll a5, t0, s9 +sll a5, t0, t6 +sll a5, a0, zero +sll a5, a0, ra +sll a5, a0, t0 +sll a5, a0, a0 +sll a5, a0, a5 +sll a5, a0, s4 +sll a5, a0, s9 +sll a5, a0, t6 +sll a5, a5, zero +sll a5, a5, ra +sll a5, a5, t0 +sll a5, a5, a0 +sll a5, a5, a5 +sll a5, a5, s4 +sll a5, a5, s9 +sll a5, a5, t6 +sll a5, s4, zero +sll a5, s4, ra +sll a5, s4, t0 +sll a5, s4, a0 +sll a5, s4, a5 +sll a5, s4, s4 +sll a5, s4, s9 +sll a5, s4, t6 +sll a5, s9, zero +sll a5, s9, ra +sll a5, s9, t0 +sll a5, s9, a0 +sll a5, s9, a5 +sll a5, s9, s4 +sll a5, s9, s9 +sll a5, s9, t6 +sll a5, t6, zero +sll a5, t6, ra +sll a5, t6, t0 +sll a5, t6, a0 +sll a5, t6, a5 +sll a5, t6, s4 +sll a5, t6, s9 +sll a5, t6, t6 +sll s4, zero, zero +sll s4, zero, ra +sll s4, zero, t0 +sll s4, zero, a0 +sll s4, zero, a5 +sll s4, zero, s4 +sll s4, zero, s9 +sll s4, zero, t6 +sll s4, ra, zero +sll s4, ra, ra +sll s4, ra, t0 +sll s4, ra, a0 +sll s4, ra, a5 +sll s4, ra, s4 +sll s4, ra, s9 +sll s4, ra, t6 +sll s4, t0, zero +sll s4, t0, ra +sll s4, t0, t0 +sll s4, t0, a0 +sll s4, t0, a5 +sll s4, t0, s4 +sll s4, t0, s9 +sll s4, t0, t6 +sll s4, a0, zero +sll s4, a0, ra +sll s4, a0, t0 +sll s4, a0, a0 +sll s4, a0, a5 +sll s4, a0, s4 +sll s4, a0, s9 +sll s4, a0, t6 +sll s4, a5, zero +sll s4, a5, ra +sll s4, a5, t0 +sll s4, a5, a0 +sll s4, a5, a5 +sll s4, a5, s4 +sll s4, a5, s9 +sll s4, a5, t6 +sll s4, s4, zero +sll s4, s4, ra +sll s4, s4, t0 +sll s4, s4, a0 +sll s4, s4, a5 +sll s4, s4, s4 +sll s4, s4, s9 +sll s4, s4, t6 +sll s4, s9, zero +sll s4, s9, ra +sll s4, s9, t0 +sll s4, s9, a0 +sll s4, s9, a5 +sll s4, s9, s4 +sll s4, s9, s9 +sll s4, s9, t6 +sll s4, t6, zero +sll s4, t6, ra +sll s4, t6, t0 +sll s4, t6, a0 +sll s4, t6, a5 +sll s4, t6, s4 +sll s4, t6, s9 +sll s4, t6, t6 +sll s9, zero, zero +sll s9, zero, ra +sll s9, zero, t0 +sll s9, zero, a0 +sll s9, zero, a5 +sll s9, zero, s4 +sll s9, zero, s9 +sll s9, zero, t6 +sll s9, ra, zero +sll s9, ra, ra +sll s9, ra, t0 +sll s9, ra, a0 +sll s9, ra, a5 +sll s9, ra, s4 +sll s9, ra, s9 +sll s9, ra, t6 +sll s9, t0, zero +sll s9, t0, ra +sll s9, t0, t0 +sll s9, t0, a0 +sll s9, t0, a5 +sll s9, t0, s4 +sll s9, t0, s9 +sll s9, t0, t6 +sll s9, a0, zero +sll s9, a0, ra +sll s9, a0, t0 +sll s9, a0, a0 +sll s9, a0, a5 +sll s9, a0, s4 +sll s9, a0, s9 +sll s9, a0, t6 +sll s9, a5, zero +sll s9, a5, ra +sll s9, a5, t0 +sll s9, a5, a0 +sll s9, a5, a5 +sll s9, a5, s4 +sll s9, a5, s9 +sll s9, a5, t6 +sll s9, s4, zero +sll s9, s4, ra +sll s9, s4, t0 +sll s9, s4, a0 +sll s9, s4, a5 +sll s9, s4, s4 +sll s9, s4, s9 +sll s9, s4, t6 +sll s9, s9, zero +sll s9, s9, ra +sll s9, s9, t0 +sll s9, s9, a0 +sll s9, s9, a5 +sll s9, s9, s4 +sll s9, s9, s9 +sll s9, s9, t6 +sll s9, t6, zero +sll s9, t6, ra +sll s9, t6, t0 +sll s9, t6, a0 +sll s9, t6, a5 +sll s9, t6, s4 +sll s9, t6, s9 +sll s9, t6, t6 +sll t6, zero, zero +sll t6, zero, ra +sll t6, zero, t0 +sll t6, zero, a0 +sll t6, zero, a5 +sll t6, zero, s4 +sll t6, zero, s9 +sll t6, zero, t6 +sll t6, ra, zero +sll t6, ra, ra +sll t6, ra, t0 +sll t6, ra, a0 +sll t6, ra, a5 +sll t6, ra, s4 +sll t6, ra, s9 +sll t6, ra, t6 +sll t6, t0, zero +sll t6, t0, ra +sll t6, t0, t0 +sll t6, t0, a0 +sll t6, t0, a5 +sll t6, t0, s4 +sll t6, t0, s9 +sll t6, t0, t6 +sll t6, a0, zero +sll t6, a0, ra +sll t6, a0, t0 +sll t6, a0, a0 +sll t6, a0, a5 +sll t6, a0, s4 +sll t6, a0, s9 +sll t6, a0, t6 +sll t6, a5, zero +sll t6, a5, ra +sll t6, a5, t0 +sll t6, a5, a0 +sll t6, a5, a5 +sll t6, a5, s4 +sll t6, a5, s9 +sll t6, a5, t6 +sll t6, s4, zero +sll t6, s4, ra +sll t6, s4, t0 +sll t6, s4, a0 +sll t6, s4, a5 +sll t6, s4, s4 +sll t6, s4, s9 +sll t6, s4, t6 +sll t6, s9, zero +sll t6, s9, ra +sll t6, s9, t0 +sll t6, s9, a0 +sll t6, s9, a5 +sll t6, s9, s4 +sll t6, s9, s9 +sll t6, s9, t6 +sll t6, t6, zero +sll t6, t6, ra +sll t6, t6, t0 +sll t6, t6, a0 +sll t6, t6, a5 +sll t6, t6, s4 +sll t6, t6, s9 +sll t6, t6, t6 diff --git a/tests/riscv/rv32i/slli.asm b/tests/riscv/rv32i/slli.asm new file mode 100644 index 0000000..016048f --- /dev/null +++ b/tests/riscv/rv32i/slli.asm @@ -0,0 +1,452 @@ +.lang riscv32 +.org 0x0 + +slli zero, zero, #0 +slli zero, zero, #1 +slli zero, zero, #2 +slli zero, zero, #4 +slli zero, zero, #8 +slli zero, zero, #16 +slli zero, zero, #31 +slli zero, ra, #0 +slli zero, ra, #1 +slli zero, ra, #2 +slli zero, ra, #4 +slli zero, ra, #8 +slli zero, ra, #16 +slli zero, ra, #31 +slli zero, t0, #0 +slli zero, t0, #1 +slli zero, t0, #2 +slli zero, t0, #4 +slli zero, t0, #8 +slli zero, t0, #16 +slli zero, t0, #31 +slli zero, a0, #0 +slli zero, a0, #1 +slli zero, a0, #2 +slli zero, a0, #4 +slli zero, a0, #8 +slli zero, a0, #16 +slli zero, a0, #31 +slli zero, a5, #0 +slli zero, a5, #1 +slli zero, a5, #2 +slli zero, a5, #4 +slli zero, a5, #8 +slli zero, a5, #16 +slli zero, a5, #31 +slli zero, s4, #0 +slli zero, s4, #1 +slli zero, s4, #2 +slli zero, s4, #4 +slli zero, s4, #8 +slli zero, s4, #16 +slli zero, s4, #31 +slli zero, s9, #0 +slli zero, s9, #1 +slli zero, s9, #2 +slli zero, s9, #4 +slli zero, s9, #8 +slli zero, s9, #16 +slli zero, s9, #31 +slli zero, t6, #0 +slli zero, t6, #1 +slli zero, t6, #2 +slli zero, t6, #4 +slli zero, t6, #8 +slli zero, t6, #16 +slli zero, t6, #31 +slli ra, zero, #0 +slli ra, zero, #1 +slli ra, zero, #2 +slli ra, zero, #4 +slli ra, zero, #8 +slli ra, zero, #16 +slli ra, zero, #31 +slli ra, ra, #0 +slli ra, ra, #1 +slli ra, ra, #2 +slli ra, ra, #4 +slli ra, ra, #8 +slli ra, ra, #16 +slli ra, ra, #31 +slli ra, t0, #0 +slli ra, t0, #1 +slli ra, t0, #2 +slli ra, t0, #4 +slli ra, t0, #8 +slli ra, t0, #16 +slli ra, t0, #31 +slli ra, a0, #0 +slli ra, a0, #1 +slli ra, a0, #2 +slli ra, a0, #4 +slli ra, a0, #8 +slli ra, a0, #16 +slli ra, a0, #31 +slli ra, a5, #0 +slli ra, a5, #1 +slli ra, a5, #2 +slli ra, a5, #4 +slli ra, a5, #8 +slli ra, a5, #16 +slli ra, a5, #31 +slli ra, s4, #0 +slli ra, s4, #1 +slli ra, s4, #2 +slli ra, s4, #4 +slli ra, s4, #8 +slli ra, s4, #16 +slli ra, s4, #31 +slli ra, s9, #0 +slli ra, s9, #1 +slli ra, s9, #2 +slli ra, s9, #4 +slli ra, s9, #8 +slli ra, s9, #16 +slli ra, s9, #31 +slli ra, t6, #0 +slli ra, t6, #1 +slli ra, t6, #2 +slli ra, t6, #4 +slli ra, t6, #8 +slli ra, t6, #16 +slli ra, t6, #31 +slli t0, zero, #0 +slli t0, zero, #1 +slli t0, zero, #2 +slli t0, zero, #4 +slli t0, zero, #8 +slli t0, zero, #16 +slli t0, zero, #31 +slli t0, ra, #0 +slli t0, ra, #1 +slli t0, ra, #2 +slli t0, ra, #4 +slli t0, ra, #8 +slli t0, ra, #16 +slli t0, ra, #31 +slli t0, t0, #0 +slli t0, t0, #1 +slli t0, t0, #2 +slli t0, t0, #4 +slli t0, t0, #8 +slli t0, t0, #16 +slli t0, t0, #31 +slli t0, a0, #0 +slli t0, a0, #1 +slli t0, a0, #2 +slli t0, a0, #4 +slli t0, a0, #8 +slli t0, a0, #16 +slli t0, a0, #31 +slli t0, a5, #0 +slli t0, a5, #1 +slli t0, a5, #2 +slli t0, a5, #4 +slli t0, a5, #8 +slli t0, a5, #16 +slli t0, a5, #31 +slli t0, s4, #0 +slli t0, s4, #1 +slli t0, s4, #2 +slli t0, s4, #4 +slli t0, s4, #8 +slli t0, s4, #16 +slli t0, s4, #31 +slli t0, s9, #0 +slli t0, s9, #1 +slli t0, s9, #2 +slli t0, s9, #4 +slli t0, s9, #8 +slli t0, s9, #16 +slli t0, s9, #31 +slli t0, t6, #0 +slli t0, t6, #1 +slli t0, t6, #2 +slli t0, t6, #4 +slli t0, t6, #8 +slli t0, t6, #16 +slli t0, t6, #31 +slli a0, zero, #0 +slli a0, zero, #1 +slli a0, zero, #2 +slli a0, zero, #4 +slli a0, zero, #8 +slli a0, zero, #16 +slli a0, zero, #31 +slli a0, ra, #0 +slli a0, ra, #1 +slli a0, ra, #2 +slli a0, ra, #4 +slli a0, ra, #8 +slli a0, ra, #16 +slli a0, ra, #31 +slli a0, t0, #0 +slli a0, t0, #1 +slli a0, t0, #2 +slli a0, t0, #4 +slli a0, t0, #8 +slli a0, t0, #16 +slli a0, t0, #31 +slli a0, a0, #0 +slli a0, a0, #1 +slli a0, a0, #2 +slli a0, a0, #4 +slli a0, a0, #8 +slli a0, a0, #16 +slli a0, a0, #31 +slli a0, a5, #0 +slli a0, a5, #1 +slli a0, a5, #2 +slli a0, a5, #4 +slli a0, a5, #8 +slli a0, a5, #16 +slli a0, a5, #31 +slli a0, s4, #0 +slli a0, s4, #1 +slli a0, s4, #2 +slli a0, s4, #4 +slli a0, s4, #8 +slli a0, s4, #16 +slli a0, s4, #31 +slli a0, s9, #0 +slli a0, s9, #1 +slli a0, s9, #2 +slli a0, s9, #4 +slli a0, s9, #8 +slli a0, s9, #16 +slli a0, s9, #31 +slli a0, t6, #0 +slli a0, t6, #1 +slli a0, t6, #2 +slli a0, t6, #4 +slli a0, t6, #8 +slli a0, t6, #16 +slli a0, t6, #31 +slli a5, zero, #0 +slli a5, zero, #1 +slli a5, zero, #2 +slli a5, zero, #4 +slli a5, zero, #8 +slli a5, zero, #16 +slli a5, zero, #31 +slli a5, ra, #0 +slli a5, ra, #1 +slli a5, ra, #2 +slli a5, ra, #4 +slli a5, ra, #8 +slli a5, ra, #16 +slli a5, ra, #31 +slli a5, t0, #0 +slli a5, t0, #1 +slli a5, t0, #2 +slli a5, t0, #4 +slli a5, t0, #8 +slli a5, t0, #16 +slli a5, t0, #31 +slli a5, a0, #0 +slli a5, a0, #1 +slli a5, a0, #2 +slli a5, a0, #4 +slli a5, a0, #8 +slli a5, a0, #16 +slli a5, a0, #31 +slli a5, a5, #0 +slli a5, a5, #1 +slli a5, a5, #2 +slli a5, a5, #4 +slli a5, a5, #8 +slli a5, a5, #16 +slli a5, a5, #31 +slli a5, s4, #0 +slli a5, s4, #1 +slli a5, s4, #2 +slli a5, s4, #4 +slli a5, s4, #8 +slli a5, s4, #16 +slli a5, s4, #31 +slli a5, s9, #0 +slli a5, s9, #1 +slli a5, s9, #2 +slli a5, s9, #4 +slli a5, s9, #8 +slli a5, s9, #16 +slli a5, s9, #31 +slli a5, t6, #0 +slli a5, t6, #1 +slli a5, t6, #2 +slli a5, t6, #4 +slli a5, t6, #8 +slli a5, t6, #16 +slli a5, t6, #31 +slli s4, zero, #0 +slli s4, zero, #1 +slli s4, zero, #2 +slli s4, zero, #4 +slli s4, zero, #8 +slli s4, zero, #16 +slli s4, zero, #31 +slli s4, ra, #0 +slli s4, ra, #1 +slli s4, ra, #2 +slli s4, ra, #4 +slli s4, ra, #8 +slli s4, ra, #16 +slli s4, ra, #31 +slli s4, t0, #0 +slli s4, t0, #1 +slli s4, t0, #2 +slli s4, t0, #4 +slli s4, t0, #8 +slli s4, t0, #16 +slli s4, t0, #31 +slli s4, a0, #0 +slli s4, a0, #1 +slli s4, a0, #2 +slli s4, a0, #4 +slli s4, a0, #8 +slli s4, a0, #16 +slli s4, a0, #31 +slli s4, a5, #0 +slli s4, a5, #1 +slli s4, a5, #2 +slli s4, a5, #4 +slli s4, a5, #8 +slli s4, a5, #16 +slli s4, a5, #31 +slli s4, s4, #0 +slli s4, s4, #1 +slli s4, s4, #2 +slli s4, s4, #4 +slli s4, s4, #8 +slli s4, s4, #16 +slli s4, s4, #31 +slli s4, s9, #0 +slli s4, s9, #1 +slli s4, s9, #2 +slli s4, s9, #4 +slli s4, s9, #8 +slli s4, s9, #16 +slli s4, s9, #31 +slli s4, t6, #0 +slli s4, t6, #1 +slli s4, t6, #2 +slli s4, t6, #4 +slli s4, t6, #8 +slli s4, t6, #16 +slli s4, t6, #31 +slli s9, zero, #0 +slli s9, zero, #1 +slli s9, zero, #2 +slli s9, zero, #4 +slli s9, zero, #8 +slli s9, zero, #16 +slli s9, zero, #31 +slli s9, ra, #0 +slli s9, ra, #1 +slli s9, ra, #2 +slli s9, ra, #4 +slli s9, ra, #8 +slli s9, ra, #16 +slli s9, ra, #31 +slli s9, t0, #0 +slli s9, t0, #1 +slli s9, t0, #2 +slli s9, t0, #4 +slli s9, t0, #8 +slli s9, t0, #16 +slli s9, t0, #31 +slli s9, a0, #0 +slli s9, a0, #1 +slli s9, a0, #2 +slli s9, a0, #4 +slli s9, a0, #8 +slli s9, a0, #16 +slli s9, a0, #31 +slli s9, a5, #0 +slli s9, a5, #1 +slli s9, a5, #2 +slli s9, a5, #4 +slli s9, a5, #8 +slli s9, a5, #16 +slli s9, a5, #31 +slli s9, s4, #0 +slli s9, s4, #1 +slli s9, s4, #2 +slli s9, s4, #4 +slli s9, s4, #8 +slli s9, s4, #16 +slli s9, s4, #31 +slli s9, s9, #0 +slli s9, s9, #1 +slli s9, s9, #2 +slli s9, s9, #4 +slli s9, s9, #8 +slli s9, s9, #16 +slli s9, s9, #31 +slli s9, t6, #0 +slli s9, t6, #1 +slli s9, t6, #2 +slli s9, t6, #4 +slli s9, t6, #8 +slli s9, t6, #16 +slli s9, t6, #31 +slli t6, zero, #0 +slli t6, zero, #1 +slli t6, zero, #2 +slli t6, zero, #4 +slli t6, zero, #8 +slli t6, zero, #16 +slli t6, zero, #31 +slli t6, ra, #0 +slli t6, ra, #1 +slli t6, ra, #2 +slli t6, ra, #4 +slli t6, ra, #8 +slli t6, ra, #16 +slli t6, ra, #31 +slli t6, t0, #0 +slli t6, t0, #1 +slli t6, t0, #2 +slli t6, t0, #4 +slli t6, t0, #8 +slli t6, t0, #16 +slli t6, t0, #31 +slli t6, a0, #0 +slli t6, a0, #1 +slli t6, a0, #2 +slli t6, a0, #4 +slli t6, a0, #8 +slli t6, a0, #16 +slli t6, a0, #31 +slli t6, a5, #0 +slli t6, a5, #1 +slli t6, a5, #2 +slli t6, a5, #4 +slli t6, a5, #8 +slli t6, a5, #16 +slli t6, a5, #31 +slli t6, s4, #0 +slli t6, s4, #1 +slli t6, s4, #2 +slli t6, s4, #4 +slli t6, s4, #8 +slli t6, s4, #16 +slli t6, s4, #31 +slli t6, s9, #0 +slli t6, s9, #1 +slli t6, s9, #2 +slli t6, s9, #4 +slli t6, s9, #8 +slli t6, s9, #16 +slli t6, s9, #31 +slli t6, t6, #0 +slli t6, t6, #1 +slli t6, t6, #2 +slli t6, t6, #4 +slli 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--- /dev/null +++ b/tests/riscv/rv32i/slti.disasm @@ -0,0 +1,1600 @@ +slti zero, zero, #0xfffff801 +slti zero, zero, #0xfffffc00 +slti zero, zero, #0xfffffe00 +slti zero, zero, #0xffffff00 +slti zero, zero, #0xffffff80 +slti zero, zero, #0xffffffc0 +slti zero, zero, #0xffffffe0 +slti zero, zero, #0xfffffff0 +slti zero, zero, #0xfffffff8 +slti zero, zero, #0xfffffffc +slti zero, zero, #0xfffffffe +slti zero, zero, #0xffffffff +slti zero, zero, #0 +slti zero, zero, #1 +slti zero, zero, #2 +slti zero, zero, #4 +slti zero, zero, #8 +slti zero, zero, #0x10 +slti zero, zero, #0x20 +slti zero, zero, #0x40 +slti zero, zero, #0x80 +slti zero, zero, #0x100 +slti zero, zero, #0x200 +slti zero, zero, #0x400 +slti zero, zero, #0x7ff +slti zero, ra, #0xfffff801 +slti zero, ra, #0xfffffc00 +slti zero, ra, #0xfffffe00 +slti zero, ra, #0xffffff00 +slti zero, ra, #0xffffff80 +slti zero, ra, #0xffffffc0 +slti zero, ra, #0xffffffe0 +slti zero, ra, #0xfffffff0 +slti zero, ra, #0xfffffff8 +slti zero, ra, #0xfffffffc +slti zero, ra, #0xfffffffe +slti zero, ra, #0xffffffff +slti zero, ra, #0 +slti zero, ra, #1 +slti zero, ra, #2 +slti zero, ra, #4 +slti zero, ra, #8 +slti zero, ra, #0x10 +slti zero, ra, #0x20 +slti zero, ra, #0x40 +slti zero, ra, #0x80 +slti zero, ra, #0x100 +slti zero, ra, #0x200 +slti zero, ra, #0x400 +slti zero, ra, #0x7ff +slti zero, t0, #0xfffff801 +slti zero, t0, #0xfffffc00 +slti zero, t0, #0xfffffe00 +slti zero, t0, #0xffffff00 +slti zero, t0, #0xffffff80 +slti zero, t0, #0xffffffc0 +slti zero, t0, #0xffffffe0 +slti zero, t0, #0xfffffff0 +slti zero, t0, #0xfffffff8 +slti zero, t0, #0xfffffffc +slti zero, t0, #0xfffffffe +slti zero, t0, #0xffffffff +slti zero, t0, #0 +slti zero, t0, #1 +slti zero, t0, #2 +slti zero, t0, #4 +slti zero, t0, #8 +slti zero, t0, #0x10 +slti zero, t0, #0x20 +slti zero, t0, #0x40 +slti zero, t0, #0x80 +slti zero, t0, #0x100 +slti zero, t0, #0x200 +slti zero, t0, #0x400 +slti zero, t0, #0x7ff +slti zero, a0, #0xfffff801 +slti zero, a0, #0xfffffc00 +slti zero, a0, #0xfffffe00 +slti zero, a0, #0xffffff00 +slti zero, a0, #0xffffff80 +slti zero, a0, #0xffffffc0 +slti zero, a0, #0xffffffe0 +slti zero, a0, #0xfffffff0 +slti zero, a0, #0xfffffff8 +slti zero, a0, #0xfffffffc +slti zero, a0, #0xfffffffe +slti zero, a0, #0xffffffff +slti zero, a0, #0 +slti zero, a0, #1 +slti zero, a0, #2 +slti zero, a0, #4 +slti zero, a0, #8 +slti zero, a0, #0x10 +slti zero, a0, #0x20 +slti zero, a0, #0x40 +slti zero, a0, #0x80 +slti zero, a0, #0x100 +slti zero, a0, #0x200 +slti zero, a0, #0x400 +slti zero, a0, #0x7ff +slti zero, a5, #0xfffff801 +slti zero, a5, #0xfffffc00 +slti zero, a5, #0xfffffe00 +slti zero, a5, #0xffffff00 +slti zero, a5, #0xffffff80 +slti zero, a5, #0xffffffc0 +slti zero, a5, #0xffffffe0 +slti zero, a5, #0xfffffff0 +slti zero, a5, #0xfffffff8 +slti zero, a5, #0xfffffffc +slti zero, a5, #0xfffffffe +slti zero, a5, #0xffffffff +slti zero, a5, #0 +slti zero, a5, #1 +slti zero, a5, #2 +slti zero, a5, #4 +slti zero, a5, #8 +slti zero, a5, #0x10 +slti zero, a5, #0x20 +slti zero, a5, #0x40 +slti zero, a5, #0x80 +slti zero, a5, #0x100 +slti zero, a5, #0x200 +slti zero, a5, #0x400 +slti zero, a5, #0x7ff +slti zero, s4, #0xfffff801 +slti zero, s4, #0xfffffc00 +slti zero, s4, #0xfffffe00 +slti zero, s4, #0xffffff00 +slti zero, s4, #0xffffff80 +slti zero, s4, #0xffffffc0 +slti zero, s4, #0xffffffe0 +slti zero, s4, #0xfffffff0 +slti zero, s4, #0xfffffff8 +slti zero, s4, #0xfffffffc +slti zero, s4, #0xfffffffe +slti zero, s4, #0xffffffff +slti zero, s4, #0 +slti zero, s4, #1 +slti zero, s4, #2 +slti zero, s4, #4 +slti zero, s4, #8 +slti zero, s4, #0x10 +slti zero, s4, #0x20 +slti zero, s4, #0x40 +slti zero, s4, #0x80 +slti zero, s4, #0x100 +slti zero, s4, #0x200 +slti zero, s4, #0x400 +slti zero, s4, #0x7ff +slti zero, s9, #0xfffff801 +slti zero, s9, #0xfffffc00 +slti zero, s9, #0xfffffe00 +slti zero, s9, #0xffffff00 +slti zero, s9, #0xffffff80 +slti zero, s9, #0xffffffc0 +slti zero, s9, #0xffffffe0 +slti zero, s9, #0xfffffff0 +slti zero, s9, #0xfffffff8 +slti zero, s9, #0xfffffffc +slti zero, s9, #0xfffffffe +slti zero, s9, #0xffffffff +slti zero, s9, #0 +slti zero, s9, #1 +slti zero, s9, #2 +slti zero, s9, #4 +slti zero, s9, #8 +slti zero, s9, #0x10 +slti zero, s9, #0x20 +slti zero, s9, #0x40 +slti zero, s9, #0x80 +slti zero, s9, #0x100 +slti zero, s9, #0x200 +slti zero, s9, #0x400 +slti zero, s9, #0x7ff +slti zero, t6, #0xfffff801 +slti zero, t6, #0xfffffc00 +slti zero, t6, #0xfffffe00 +slti zero, t6, #0xffffff00 +slti zero, t6, #0xffffff80 +slti zero, t6, #0xffffffc0 +slti zero, t6, #0xffffffe0 +slti zero, t6, #0xfffffff0 +slti zero, t6, #0xfffffff8 +slti zero, t6, #0xfffffffc +slti zero, t6, #0xfffffffe +slti zero, t6, #0xffffffff +slti zero, t6, #0 +slti zero, t6, #1 +slti zero, t6, #2 +slti zero, t6, #4 +slti zero, t6, #8 +slti zero, t6, #0x10 +slti zero, t6, #0x20 +slti zero, t6, #0x40 +slti zero, t6, #0x80 +slti zero, t6, #0x100 +slti zero, t6, #0x200 +slti zero, t6, #0x400 +slti zero, t6, #0x7ff +slti ra, zero, #0xfffff801 +slti ra, zero, #0xfffffc00 +slti ra, zero, #0xfffffe00 +slti ra, zero, #0xffffff00 +slti ra, zero, #0xffffff80 +slti ra, zero, #0xffffffc0 +slti ra, zero, #0xffffffe0 +slti ra, zero, #0xfffffff0 +slti ra, zero, #0xfffffff8 +slti ra, zero, #0xfffffffc +slti ra, zero, #0xfffffffe +slti ra, zero, #0xffffffff +slti ra, zero, #0 +slti ra, zero, #1 +slti ra, zero, #2 +slti ra, zero, #4 +slti ra, zero, #8 +slti ra, zero, #0x10 +slti ra, zero, #0x20 +slti ra, zero, #0x40 +slti ra, zero, #0x80 +slti ra, zero, #0x100 +slti ra, zero, #0x200 +slti ra, zero, #0x400 +slti ra, zero, #0x7ff +slti ra, ra, #0xfffff801 +slti ra, ra, #0xfffffc00 +slti ra, ra, #0xfffffe00 +slti ra, ra, #0xffffff00 +slti ra, ra, #0xffffff80 +slti ra, ra, #0xffffffc0 +slti ra, ra, #0xffffffe0 +slti ra, ra, #0xfffffff0 +slti ra, ra, #0xfffffff8 +slti ra, ra, #0xfffffffc +slti ra, ra, #0xfffffffe +slti ra, ra, #0xffffffff +slti ra, ra, #0 +slti ra, ra, #1 +slti ra, ra, #2 +slti ra, ra, #4 +slti ra, ra, #8 +slti ra, ra, #0x10 +slti ra, ra, #0x20 +slti ra, ra, #0x40 +slti ra, ra, #0x80 +slti ra, ra, #0x100 +slti ra, ra, #0x200 +slti ra, ra, #0x400 +slti ra, ra, #0x7ff +slti ra, t0, #0xfffff801 +slti ra, t0, #0xfffffc00 +slti ra, t0, #0xfffffe00 +slti ra, t0, #0xffffff00 +slti ra, t0, #0xffffff80 +slti ra, t0, #0xffffffc0 +slti ra, t0, #0xffffffe0 +slti ra, t0, #0xfffffff0 +slti ra, t0, #0xfffffff8 +slti ra, t0, #0xfffffffc +slti ra, t0, #0xfffffffe +slti ra, t0, #0xffffffff +slti ra, t0, #0 +slti ra, t0, #1 +slti ra, t0, #2 +slti ra, t0, #4 +slti ra, t0, #8 +slti ra, t0, #0x10 +slti ra, t0, #0x20 +slti ra, t0, #0x40 +slti ra, t0, #0x80 +slti ra, t0, #0x100 +slti ra, t0, #0x200 +slti ra, t0, #0x400 +slti ra, t0, #0x7ff +slti ra, a0, #0xfffff801 +slti ra, a0, #0xfffffc00 +slti ra, a0, #0xfffffe00 +slti ra, a0, #0xffffff00 +slti ra, a0, #0xffffff80 +slti ra, a0, #0xffffffc0 +slti ra, a0, #0xffffffe0 +slti ra, a0, #0xfffffff0 +slti ra, a0, #0xfffffff8 +slti ra, a0, #0xfffffffc +slti ra, a0, #0xfffffffe +slti ra, a0, #0xffffffff +slti ra, a0, #0 +slti ra, a0, #1 +slti ra, a0, #2 +slti ra, a0, #4 +slti ra, a0, #8 +slti ra, a0, #0x10 +slti ra, a0, #0x20 +slti ra, a0, #0x40 +slti ra, a0, #0x80 +slti ra, a0, #0x100 +slti ra, a0, #0x200 +slti ra, a0, #0x400 +slti ra, a0, #0x7ff +slti ra, a5, #0xfffff801 +slti ra, a5, #0xfffffc00 +slti ra, a5, #0xfffffe00 +slti ra, a5, #0xffffff00 +slti ra, a5, #0xffffff80 +slti ra, a5, #0xffffffc0 +slti ra, a5, #0xffffffe0 +slti ra, a5, #0xfffffff0 +slti ra, a5, #0xfffffff8 +slti ra, a5, #0xfffffffc +slti ra, a5, #0xfffffffe +slti ra, a5, #0xffffffff +slti ra, a5, #0 +slti ra, a5, #1 +slti ra, a5, #2 +slti ra, a5, #4 +slti ra, a5, #8 +slti ra, a5, #0x10 +slti ra, a5, #0x20 +slti ra, a5, #0x40 +slti ra, a5, #0x80 +slti ra, a5, #0x100 +slti ra, a5, #0x200 +slti ra, a5, #0x400 +slti ra, a5, #0x7ff +slti ra, s4, #0xfffff801 +slti ra, s4, #0xfffffc00 +slti ra, s4, #0xfffffe00 +slti ra, s4, #0xffffff00 +slti ra, s4, #0xffffff80 +slti ra, s4, #0xffffffc0 +slti ra, s4, #0xffffffe0 +slti ra, s4, #0xfffffff0 +slti ra, s4, #0xfffffff8 +slti ra, s4, #0xfffffffc +slti ra, s4, #0xfffffffe +slti ra, s4, #0xffffffff +slti ra, s4, #0 +slti ra, s4, #1 +slti ra, s4, #2 +slti ra, s4, #4 +slti ra, s4, #8 +slti ra, s4, #0x10 +slti ra, s4, #0x20 +slti ra, s4, #0x40 +slti ra, s4, #0x80 +slti ra, s4, #0x100 +slti ra, s4, #0x200 +slti ra, s4, #0x400 +slti ra, s4, #0x7ff +slti ra, s9, #0xfffff801 +slti ra, s9, #0xfffffc00 +slti ra, s9, #0xfffffe00 +slti ra, s9, #0xffffff00 +slti ra, s9, #0xffffff80 +slti ra, s9, #0xffffffc0 +slti ra, s9, #0xffffffe0 +slti ra, s9, #0xfffffff0 +slti ra, s9, #0xfffffff8 +slti ra, s9, #0xfffffffc +slti ra, s9, #0xfffffffe +slti ra, s9, #0xffffffff +slti ra, s9, #0 +slti ra, s9, #1 +slti ra, s9, #2 +slti ra, s9, #4 +slti ra, s9, #8 +slti ra, s9, #0x10 +slti ra, s9, #0x20 +slti ra, s9, #0x40 +slti ra, s9, #0x80 +slti ra, s9, #0x100 +slti ra, s9, #0x200 +slti ra, s9, #0x400 +slti ra, s9, #0x7ff +slti ra, t6, #0xfffff801 +slti ra, t6, #0xfffffc00 +slti ra, t6, #0xfffffe00 +slti ra, t6, #0xffffff00 +slti ra, t6, #0xffffff80 +slti ra, t6, #0xffffffc0 +slti ra, t6, #0xffffffe0 +slti ra, t6, #0xfffffff0 +slti ra, t6, #0xfffffff8 +slti ra, t6, #0xfffffffc +slti ra, t6, #0xfffffffe +slti ra, t6, #0xffffffff +slti ra, t6, #0 +slti ra, t6, #1 +slti ra, t6, #2 +slti ra, t6, #4 +slti ra, t6, #8 +slti ra, t6, #0x10 +slti ra, t6, #0x20 +slti ra, t6, #0x40 +slti ra, t6, #0x80 +slti ra, t6, #0x100 +slti ra, t6, #0x200 +slti ra, t6, #0x400 +slti ra, t6, #0x7ff +slti t0, zero, #0xfffff801 +slti t0, zero, #0xfffffc00 +slti t0, zero, #0xfffffe00 +slti t0, zero, #0xffffff00 +slti t0, zero, #0xffffff80 +slti t0, zero, #0xffffffc0 +slti t0, zero, #0xffffffe0 +slti t0, zero, #0xfffffff0 +slti t0, zero, #0xfffffff8 +slti t0, zero, #0xfffffffc +slti t0, zero, #0xfffffffe +slti t0, zero, #0xffffffff +slti t0, zero, #0 +slti t0, zero, #1 +slti t0, zero, #2 +slti t0, zero, #4 +slti t0, zero, #8 +slti t0, zero, #0x10 +slti t0, zero, #0x20 +slti t0, zero, #0x40 +slti t0, zero, #0x80 +slti t0, zero, #0x100 +slti t0, zero, #0x200 +slti t0, zero, #0x400 +slti t0, zero, #0x7ff +slti t0, ra, #0xfffff801 +slti t0, ra, #0xfffffc00 +slti t0, ra, #0xfffffe00 +slti t0, ra, #0xffffff00 +slti t0, ra, #0xffffff80 +slti t0, ra, #0xffffffc0 +slti t0, ra, #0xffffffe0 +slti t0, ra, #0xfffffff0 +slti t0, ra, #0xfffffff8 +slti t0, ra, #0xfffffffc +slti t0, ra, #0xfffffffe +slti t0, ra, #0xffffffff +slti t0, ra, #0 +slti t0, ra, #1 +slti t0, ra, #2 +slti t0, ra, #4 +slti t0, ra, #8 +slti t0, ra, #0x10 +slti t0, ra, #0x20 +slti t0, ra, #0x40 +slti t0, ra, #0x80 +slti t0, ra, #0x100 +slti t0, ra, #0x200 +slti t0, ra, #0x400 +slti t0, ra, #0x7ff +slti t0, t0, #0xfffff801 +slti t0, t0, #0xfffffc00 +slti t0, t0, #0xfffffe00 +slti t0, t0, #0xffffff00 +slti t0, t0, #0xffffff80 +slti t0, t0, #0xffffffc0 +slti t0, t0, #0xffffffe0 +slti t0, t0, #0xfffffff0 +slti t0, t0, #0xfffffff8 +slti t0, t0, #0xfffffffc +slti t0, t0, #0xfffffffe +slti t0, t0, #0xffffffff +slti t0, t0, #0 +slti t0, t0, #1 +slti t0, t0, #2 +slti t0, t0, #4 +slti t0, t0, #8 +slti t0, t0, #0x10 +slti t0, t0, #0x20 +slti t0, t0, #0x40 +slti t0, t0, #0x80 +slti t0, t0, #0x100 +slti t0, t0, #0x200 +slti t0, t0, #0x400 +slti t0, t0, #0x7ff +slti t0, a0, #0xfffff801 +slti t0, a0, #0xfffffc00 +slti t0, a0, #0xfffffe00 +slti t0, a0, #0xffffff00 +slti t0, a0, #0xffffff80 +slti t0, a0, #0xffffffc0 +slti t0, a0, #0xffffffe0 +slti t0, a0, #0xfffffff0 +slti t0, a0, #0xfffffff8 +slti t0, a0, #0xfffffffc +slti t0, a0, #0xfffffffe +slti t0, a0, #0xffffffff +slti t0, a0, #0 +slti t0, a0, #1 +slti t0, a0, #2 +slti t0, a0, #4 +slti t0, a0, #8 +slti t0, a0, #0x10 +slti t0, a0, #0x20 +slti t0, a0, #0x40 +slti t0, a0, #0x80 +slti t0, a0, #0x100 +slti t0, a0, #0x200 +slti t0, a0, #0x400 +slti t0, a0, #0x7ff +slti t0, a5, #0xfffff801 +slti t0, a5, #0xfffffc00 +slti t0, a5, #0xfffffe00 +slti t0, a5, #0xffffff00 +slti t0, a5, #0xffffff80 +slti t0, a5, #0xffffffc0 +slti t0, a5, #0xffffffe0 +slti t0, a5, #0xfffffff0 +slti t0, a5, #0xfffffff8 +slti t0, a5, #0xfffffffc +slti t0, a5, #0xfffffffe +slti t0, a5, #0xffffffff +slti t0, a5, #0 +slti t0, a5, #1 +slti t0, a5, #2 +slti t0, a5, #4 +slti t0, a5, #8 +slti t0, a5, #0x10 +slti t0, a5, #0x20 +slti t0, a5, #0x40 +slti t0, a5, #0x80 +slti t0, a5, #0x100 +slti t0, a5, #0x200 +slti t0, a5, #0x400 +slti t0, a5, #0x7ff +slti t0, s4, #0xfffff801 +slti t0, s4, #0xfffffc00 +slti t0, s4, #0xfffffe00 +slti t0, s4, #0xffffff00 +slti t0, s4, #0xffffff80 +slti t0, s4, #0xffffffc0 +slti t0, s4, #0xffffffe0 +slti t0, s4, #0xfffffff0 +slti t0, s4, #0xfffffff8 +slti t0, s4, #0xfffffffc +slti t0, s4, #0xfffffffe +slti t0, s4, #0xffffffff +slti t0, s4, #0 +slti t0, s4, #1 +slti t0, s4, #2 +slti t0, s4, #4 +slti t0, s4, #8 +slti t0, s4, #0x10 +slti t0, s4, #0x20 +slti t0, s4, #0x40 +slti t0, s4, #0x80 +slti t0, s4, #0x100 +slti t0, s4, #0x200 +slti t0, s4, #0x400 +slti t0, s4, #0x7ff +slti t0, s9, #0xfffff801 +slti t0, s9, #0xfffffc00 +slti t0, s9, #0xfffffe00 +slti t0, s9, #0xffffff00 +slti t0, s9, #0xffffff80 +slti t0, s9, #0xffffffc0 +slti t0, s9, #0xffffffe0 +slti t0, s9, #0xfffffff0 +slti t0, s9, #0xfffffff8 +slti t0, s9, #0xfffffffc +slti t0, s9, #0xfffffffe +slti t0, s9, #0xffffffff +slti t0, s9, #0 +slti t0, s9, #1 +slti t0, s9, #2 +slti t0, s9, #4 +slti t0, s9, #8 +slti t0, s9, #0x10 +slti t0, s9, #0x20 +slti t0, s9, #0x40 +slti t0, s9, #0x80 +slti t0, s9, #0x100 +slti t0, s9, #0x200 +slti t0, s9, #0x400 +slti t0, s9, #0x7ff +slti t0, t6, #0xfffff801 +slti t0, t6, #0xfffffc00 +slti t0, t6, #0xfffffe00 +slti t0, t6, #0xffffff00 +slti t0, t6, #0xffffff80 +slti t0, t6, #0xffffffc0 +slti t0, t6, #0xffffffe0 +slti t0, t6, #0xfffffff0 +slti t0, t6, #0xfffffff8 +slti t0, t6, #0xfffffffc +slti t0, t6, #0xfffffffe +slti t0, t6, #0xffffffff +slti t0, t6, #0 +slti t0, t6, #1 +slti t0, t6, #2 +slti t0, t6, #4 +slti t0, t6, #8 +slti t0, t6, #0x10 +slti t0, t6, #0x20 +slti t0, t6, #0x40 +slti t0, t6, #0x80 +slti t0, t6, #0x100 +slti t0, t6, #0x200 +slti t0, t6, #0x400 +slti t0, t6, #0x7ff +slti a0, zero, #0xfffff801 +slti a0, zero, #0xfffffc00 +slti a0, zero, #0xfffffe00 +slti a0, zero, #0xffffff00 +slti a0, zero, #0xffffff80 +slti a0, zero, #0xffffffc0 +slti a0, zero, #0xffffffe0 +slti a0, zero, #0xfffffff0 +slti a0, zero, #0xfffffff8 +slti a0, zero, #0xfffffffc +slti a0, zero, #0xfffffffe +slti a0, zero, #0xffffffff +slti a0, zero, #0 +slti a0, zero, #1 +slti a0, zero, #2 +slti a0, zero, #4 +slti a0, zero, #8 +slti a0, zero, #0x10 +slti a0, zero, #0x20 +slti a0, zero, #0x40 +slti a0, zero, #0x80 +slti a0, zero, #0x100 +slti a0, zero, #0x200 +slti a0, zero, #0x400 +slti a0, zero, #0x7ff +slti a0, ra, #0xfffff801 +slti a0, ra, #0xfffffc00 +slti a0, ra, #0xfffffe00 +slti a0, ra, #0xffffff00 +slti a0, ra, #0xffffff80 +slti a0, ra, #0xffffffc0 +slti a0, ra, #0xffffffe0 +slti a0, ra, #0xfffffff0 +slti a0, ra, #0xfffffff8 +slti a0, ra, #0xfffffffc +slti a0, ra, #0xfffffffe +slti a0, ra, #0xffffffff +slti a0, ra, #0 +slti a0, ra, #1 +slti a0, ra, #2 +slti a0, ra, #4 +slti a0, ra, #8 +slti a0, ra, #0x10 +slti a0, ra, #0x20 +slti a0, ra, #0x40 +slti a0, ra, #0x80 +slti a0, ra, #0x100 +slti a0, ra, #0x200 +slti a0, ra, #0x400 +slti a0, ra, #0x7ff +slti a0, t0, #0xfffff801 +slti a0, t0, #0xfffffc00 +slti a0, t0, #0xfffffe00 +slti a0, t0, #0xffffff00 +slti a0, t0, #0xffffff80 +slti a0, t0, #0xffffffc0 +slti a0, t0, #0xffffffe0 +slti a0, t0, #0xfffffff0 +slti a0, t0, #0xfffffff8 +slti a0, t0, #0xfffffffc +slti a0, t0, #0xfffffffe +slti a0, t0, #0xffffffff +slti a0, t0, #0 +slti a0, t0, #1 +slti a0, t0, #2 +slti a0, t0, #4 +slti a0, t0, #8 +slti a0, t0, #0x10 +slti a0, t0, #0x20 +slti a0, t0, #0x40 +slti a0, t0, #0x80 +slti a0, t0, #0x100 +slti a0, t0, #0x200 +slti a0, t0, #0x400 +slti a0, t0, #0x7ff +slti a0, a0, #0xfffff801 +slti a0, a0, #0xfffffc00 +slti a0, a0, #0xfffffe00 +slti a0, a0, #0xffffff00 +slti a0, a0, #0xffffff80 +slti a0, a0, #0xffffffc0 +slti a0, a0, #0xffffffe0 +slti a0, a0, #0xfffffff0 +slti a0, a0, #0xfffffff8 +slti a0, a0, #0xfffffffc +slti a0, a0, #0xfffffffe +slti a0, a0, #0xffffffff +slti a0, a0, #0 +slti a0, a0, #1 +slti a0, a0, #2 +slti a0, a0, #4 +slti a0, a0, #8 +slti a0, a0, #0x10 +slti a0, a0, #0x20 +slti a0, a0, #0x40 +slti a0, a0, #0x80 +slti a0, a0, #0x100 +slti a0, a0, #0x200 +slti a0, a0, #0x400 +slti a0, a0, #0x7ff +slti a0, a5, #0xfffff801 +slti a0, a5, #0xfffffc00 +slti a0, a5, #0xfffffe00 +slti a0, a5, #0xffffff00 +slti a0, a5, #0xffffff80 +slti a0, a5, #0xffffffc0 +slti a0, a5, #0xffffffe0 +slti a0, a5, #0xfffffff0 +slti a0, a5, #0xfffffff8 +slti a0, a5, #0xfffffffc +slti a0, a5, #0xfffffffe +slti a0, a5, #0xffffffff +slti a0, a5, #0 +slti a0, a5, #1 +slti a0, a5, #2 +slti a0, a5, #4 +slti a0, a5, #8 +slti a0, a5, #0x10 +slti a0, a5, #0x20 +slti a0, a5, #0x40 +slti a0, a5, #0x80 +slti a0, a5, #0x100 +slti a0, a5, #0x200 +slti a0, a5, #0x400 +slti a0, a5, #0x7ff +slti a0, s4, #0xfffff801 +slti a0, s4, #0xfffffc00 +slti a0, s4, #0xfffffe00 +slti a0, s4, #0xffffff00 +slti a0, s4, #0xffffff80 +slti a0, s4, #0xffffffc0 +slti a0, s4, #0xffffffe0 +slti a0, s4, #0xfffffff0 +slti a0, s4, #0xfffffff8 +slti a0, s4, #0xfffffffc +slti a0, s4, #0xfffffffe +slti a0, s4, #0xffffffff +slti a0, s4, #0 +slti a0, s4, #1 +slti a0, s4, #2 +slti a0, s4, #4 +slti a0, s4, #8 +slti a0, s4, #0x10 +slti a0, s4, #0x20 +slti a0, s4, #0x40 +slti a0, s4, #0x80 +slti a0, s4, #0x100 +slti a0, s4, #0x200 +slti a0, s4, #0x400 +slti a0, s4, #0x7ff +slti a0, s9, #0xfffff801 +slti a0, s9, #0xfffffc00 +slti a0, s9, #0xfffffe00 +slti a0, s9, #0xffffff00 +slti a0, s9, #0xffffff80 +slti a0, s9, #0xffffffc0 +slti a0, s9, #0xffffffe0 +slti a0, s9, #0xfffffff0 +slti a0, s9, #0xfffffff8 +slti a0, s9, #0xfffffffc +slti a0, s9, #0xfffffffe +slti a0, s9, #0xffffffff +slti a0, s9, #0 +slti a0, s9, #1 +slti a0, s9, #2 +slti a0, s9, #4 +slti a0, s9, #8 +slti a0, s9, #0x10 +slti a0, s9, #0x20 +slti a0, s9, #0x40 +slti a0, s9, #0x80 +slti a0, s9, #0x100 +slti a0, s9, #0x200 +slti a0, s9, #0x400 +slti a0, s9, #0x7ff +slti a0, t6, #0xfffff801 +slti a0, t6, #0xfffffc00 +slti a0, t6, #0xfffffe00 +slti a0, t6, #0xffffff00 +slti a0, t6, #0xffffff80 +slti a0, t6, #0xffffffc0 +slti a0, t6, #0xffffffe0 +slti a0, t6, #0xfffffff0 +slti a0, t6, #0xfffffff8 +slti a0, t6, #0xfffffffc +slti a0, t6, #0xfffffffe +slti a0, t6, #0xffffffff +slti a0, t6, #0 +slti a0, t6, #1 +slti a0, t6, #2 +slti a0, t6, #4 +slti a0, t6, #8 +slti a0, t6, #0x10 +slti a0, t6, #0x20 +slti a0, t6, #0x40 +slti a0, t6, #0x80 +slti a0, t6, #0x100 +slti a0, t6, #0x200 +slti a0, t6, #0x400 +slti a0, t6, #0x7ff +slti a5, zero, #0xfffff801 +slti a5, zero, #0xfffffc00 +slti a5, zero, #0xfffffe00 +slti a5, zero, #0xffffff00 +slti a5, zero, #0xffffff80 +slti a5, zero, #0xffffffc0 +slti a5, zero, #0xffffffe0 +slti a5, zero, #0xfffffff0 +slti a5, zero, #0xfffffff8 +slti a5, zero, #0xfffffffc +slti a5, zero, #0xfffffffe +slti a5, zero, #0xffffffff +slti a5, zero, #0 +slti a5, zero, #1 +slti a5, zero, #2 +slti a5, zero, #4 +slti a5, zero, #8 +slti a5, zero, #0x10 +slti a5, zero, #0x20 +slti a5, zero, #0x40 +slti a5, zero, #0x80 +slti a5, zero, #0x100 +slti a5, zero, #0x200 +slti a5, zero, #0x400 +slti a5, zero, #0x7ff +slti a5, ra, #0xfffff801 +slti a5, ra, #0xfffffc00 +slti a5, ra, #0xfffffe00 +slti a5, ra, #0xffffff00 +slti a5, ra, #0xffffff80 +slti a5, ra, #0xffffffc0 +slti a5, ra, #0xffffffe0 +slti a5, ra, #0xfffffff0 +slti a5, ra, #0xfffffff8 +slti a5, ra, #0xfffffffc +slti a5, ra, #0xfffffffe +slti a5, ra, #0xffffffff +slti a5, ra, #0 +slti a5, ra, #1 +slti a5, ra, #2 +slti a5, ra, #4 +slti a5, ra, #8 +slti a5, ra, #0x10 +slti a5, ra, #0x20 +slti a5, ra, #0x40 +slti a5, ra, #0x80 +slti a5, ra, #0x100 +slti a5, ra, #0x200 +slti a5, ra, #0x400 +slti a5, ra, #0x7ff +slti a5, t0, #0xfffff801 +slti a5, t0, #0xfffffc00 +slti a5, t0, #0xfffffe00 +slti a5, t0, #0xffffff00 +slti a5, t0, #0xffffff80 +slti a5, t0, #0xffffffc0 +slti a5, t0, #0xffffffe0 +slti a5, t0, #0xfffffff0 +slti a5, t0, #0xfffffff8 +slti a5, t0, #0xfffffffc +slti a5, t0, #0xfffffffe +slti a5, t0, #0xffffffff +slti a5, t0, #0 +slti a5, t0, #1 +slti a5, t0, #2 +slti a5, t0, #4 +slti a5, t0, #8 +slti a5, t0, #0x10 +slti a5, t0, #0x20 +slti a5, t0, #0x40 +slti a5, t0, #0x80 +slti a5, t0, #0x100 +slti a5, t0, #0x200 +slti a5, t0, #0x400 +slti a5, t0, #0x7ff +slti a5, a0, #0xfffff801 +slti a5, a0, #0xfffffc00 +slti a5, a0, #0xfffffe00 +slti a5, a0, #0xffffff00 +slti a5, a0, #0xffffff80 +slti a5, a0, #0xffffffc0 +slti a5, a0, #0xffffffe0 +slti a5, a0, #0xfffffff0 +slti a5, a0, #0xfffffff8 +slti a5, a0, #0xfffffffc +slti a5, a0, #0xfffffffe +slti a5, a0, #0xffffffff +slti a5, a0, #0 +slti a5, a0, #1 +slti a5, a0, #2 +slti a5, a0, #4 +slti a5, a0, #8 +slti a5, a0, #0x10 +slti a5, a0, #0x20 +slti a5, a0, #0x40 +slti a5, a0, #0x80 +slti a5, a0, #0x100 +slti a5, a0, #0x200 +slti a5, a0, #0x400 +slti a5, a0, #0x7ff +slti a5, a5, #0xfffff801 +slti a5, a5, #0xfffffc00 +slti a5, a5, #0xfffffe00 +slti a5, a5, #0xffffff00 +slti a5, a5, #0xffffff80 +slti a5, a5, #0xffffffc0 +slti a5, a5, #0xffffffe0 +slti a5, a5, #0xfffffff0 +slti a5, a5, #0xfffffff8 +slti a5, a5, #0xfffffffc +slti a5, a5, #0xfffffffe +slti a5, a5, #0xffffffff +slti a5, a5, #0 +slti a5, a5, #1 +slti a5, a5, #2 +slti a5, a5, #4 +slti a5, a5, #8 +slti a5, a5, #0x10 +slti a5, a5, #0x20 +slti a5, a5, #0x40 +slti a5, a5, #0x80 +slti a5, a5, #0x100 +slti a5, a5, #0x200 +slti a5, a5, #0x400 +slti a5, a5, #0x7ff +slti a5, s4, #0xfffff801 +slti a5, s4, #0xfffffc00 +slti a5, s4, #0xfffffe00 +slti a5, s4, #0xffffff00 +slti a5, s4, #0xffffff80 +slti a5, s4, #0xffffffc0 +slti a5, s4, #0xffffffe0 +slti a5, s4, #0xfffffff0 +slti a5, s4, #0xfffffff8 +slti a5, s4, #0xfffffffc +slti a5, s4, #0xfffffffe +slti a5, s4, #0xffffffff +slti a5, s4, #0 +slti a5, s4, #1 +slti a5, s4, #2 +slti a5, s4, #4 +slti a5, s4, #8 +slti a5, s4, #0x10 +slti a5, s4, #0x20 +slti a5, s4, #0x40 +slti a5, s4, #0x80 +slti a5, s4, #0x100 +slti a5, s4, #0x200 +slti a5, s4, #0x400 +slti a5, s4, #0x7ff +slti a5, s9, #0xfffff801 +slti a5, s9, #0xfffffc00 +slti a5, s9, #0xfffffe00 +slti a5, s9, #0xffffff00 +slti a5, s9, #0xffffff80 +slti a5, s9, #0xffffffc0 +slti a5, s9, #0xffffffe0 +slti a5, s9, #0xfffffff0 +slti a5, s9, #0xfffffff8 +slti a5, s9, #0xfffffffc +slti a5, s9, #0xfffffffe +slti a5, s9, #0xffffffff +slti a5, s9, #0 +slti a5, s9, #1 +slti a5, s9, #2 +slti a5, s9, #4 +slti a5, s9, #8 +slti a5, s9, #0x10 +slti a5, s9, #0x20 +slti a5, s9, #0x40 +slti a5, s9, #0x80 +slti a5, s9, #0x100 +slti a5, s9, #0x200 +slti a5, s9, #0x400 +slti a5, s9, #0x7ff +slti a5, t6, #0xfffff801 +slti a5, t6, #0xfffffc00 +slti a5, t6, #0xfffffe00 +slti a5, t6, #0xffffff00 +slti a5, t6, #0xffffff80 +slti a5, t6, #0xffffffc0 +slti a5, t6, #0xffffffe0 +slti a5, t6, #0xfffffff0 +slti a5, t6, #0xfffffff8 +slti a5, t6, #0xfffffffc +slti a5, t6, #0xfffffffe +slti a5, t6, #0xffffffff +slti a5, t6, #0 +slti a5, t6, #1 +slti a5, t6, #2 +slti a5, t6, #4 +slti a5, t6, #8 +slti a5, t6, #0x10 +slti a5, t6, #0x20 +slti a5, t6, #0x40 +slti a5, t6, #0x80 +slti a5, t6, #0x100 +slti a5, t6, #0x200 +slti a5, t6, #0x400 +slti a5, t6, #0x7ff +slti s4, zero, #0xfffff801 +slti s4, zero, #0xfffffc00 +slti s4, zero, #0xfffffe00 +slti s4, zero, #0xffffff00 +slti s4, zero, #0xffffff80 +slti s4, zero, #0xffffffc0 +slti s4, zero, #0xffffffe0 +slti s4, zero, #0xfffffff0 +slti s4, zero, #0xfffffff8 +slti s4, zero, #0xfffffffc +slti s4, zero, #0xfffffffe +slti s4, zero, #0xffffffff +slti s4, zero, #0 +slti s4, zero, #1 +slti s4, zero, #2 +slti s4, zero, #4 +slti s4, zero, #8 +slti s4, zero, #0x10 +slti s4, zero, #0x20 +slti s4, zero, #0x40 +slti s4, zero, #0x80 +slti s4, zero, #0x100 +slti s4, zero, #0x200 +slti s4, zero, #0x400 +slti s4, zero, #0x7ff +slti s4, ra, #0xfffff801 +slti s4, ra, #0xfffffc00 +slti s4, ra, #0xfffffe00 +slti s4, ra, #0xffffff00 +slti s4, ra, #0xffffff80 +slti s4, ra, #0xffffffc0 +slti s4, ra, #0xffffffe0 +slti s4, ra, #0xfffffff0 +slti s4, ra, #0xfffffff8 +slti s4, ra, #0xfffffffc +slti s4, ra, #0xfffffffe +slti s4, ra, #0xffffffff +slti s4, ra, #0 +slti s4, ra, #1 +slti s4, ra, #2 +slti s4, ra, #4 +slti s4, ra, #8 +slti s4, ra, #0x10 +slti s4, ra, #0x20 +slti s4, ra, #0x40 +slti s4, ra, #0x80 +slti s4, ra, #0x100 +slti s4, ra, #0x200 +slti s4, ra, #0x400 +slti s4, ra, #0x7ff +slti s4, t0, #0xfffff801 +slti s4, t0, #0xfffffc00 +slti s4, t0, #0xfffffe00 +slti s4, t0, #0xffffff00 +slti s4, t0, #0xffffff80 +slti s4, t0, #0xffffffc0 +slti s4, t0, #0xffffffe0 +slti s4, t0, #0xfffffff0 +slti s4, t0, #0xfffffff8 +slti s4, t0, #0xfffffffc +slti s4, t0, #0xfffffffe +slti s4, t0, #0xffffffff +slti s4, t0, #0 +slti s4, t0, #1 +slti s4, t0, #2 +slti s4, t0, #4 +slti s4, t0, #8 +slti s4, t0, #0x10 +slti s4, t0, #0x20 +slti s4, t0, #0x40 +slti s4, t0, #0x80 +slti s4, t0, #0x100 +slti s4, t0, #0x200 +slti s4, t0, #0x400 +slti s4, t0, #0x7ff +slti s4, a0, #0xfffff801 +slti s4, a0, #0xfffffc00 +slti s4, a0, #0xfffffe00 +slti s4, a0, #0xffffff00 +slti s4, a0, #0xffffff80 +slti s4, a0, #0xffffffc0 +slti s4, a0, #0xffffffe0 +slti s4, a0, #0xfffffff0 +slti s4, a0, #0xfffffff8 +slti s4, a0, #0xfffffffc +slti s4, a0, #0xfffffffe +slti s4, a0, #0xffffffff +slti s4, a0, #0 +slti s4, a0, #1 +slti s4, a0, #2 +slti s4, a0, #4 +slti s4, a0, #8 +slti s4, a0, #0x10 +slti s4, a0, #0x20 +slti s4, a0, #0x40 +slti s4, a0, #0x80 +slti s4, a0, #0x100 +slti s4, a0, #0x200 +slti s4, a0, #0x400 +slti s4, a0, #0x7ff +slti s4, a5, #0xfffff801 +slti s4, a5, #0xfffffc00 +slti s4, a5, #0xfffffe00 +slti s4, a5, #0xffffff00 +slti s4, a5, #0xffffff80 +slti s4, a5, #0xffffffc0 +slti s4, a5, #0xffffffe0 +slti s4, a5, #0xfffffff0 +slti s4, a5, #0xfffffff8 +slti s4, a5, #0xfffffffc +slti s4, a5, #0xfffffffe +slti s4, a5, #0xffffffff +slti s4, a5, #0 +slti s4, a5, #1 +slti s4, a5, #2 +slti s4, a5, #4 +slti s4, a5, #8 +slti s4, a5, #0x10 +slti s4, a5, #0x20 +slti s4, a5, #0x40 +slti s4, a5, #0x80 +slti s4, a5, #0x100 +slti s4, a5, #0x200 +slti s4, a5, #0x400 +slti s4, a5, #0x7ff +slti s4, s4, #0xfffff801 +slti s4, s4, #0xfffffc00 +slti s4, s4, #0xfffffe00 +slti s4, s4, #0xffffff00 +slti s4, s4, #0xffffff80 +slti s4, s4, #0xffffffc0 +slti s4, s4, #0xffffffe0 +slti s4, s4, #0xfffffff0 +slti s4, s4, #0xfffffff8 +slti s4, s4, #0xfffffffc +slti s4, s4, #0xfffffffe +slti s4, s4, #0xffffffff +slti s4, s4, #0 +slti s4, s4, #1 +slti s4, s4, #2 +slti s4, s4, #4 +slti s4, s4, #8 +slti s4, s4, #0x10 +slti s4, s4, #0x20 +slti s4, s4, #0x40 +slti s4, s4, #0x80 +slti s4, s4, #0x100 +slti s4, s4, #0x200 +slti s4, s4, #0x400 +slti s4, s4, #0x7ff +slti s4, s9, #0xfffff801 +slti s4, s9, #0xfffffc00 +slti s4, s9, #0xfffffe00 +slti s4, s9, #0xffffff00 +slti s4, s9, #0xffffff80 +slti s4, s9, #0xffffffc0 +slti s4, s9, #0xffffffe0 +slti s4, s9, #0xfffffff0 +slti s4, s9, #0xfffffff8 +slti s4, s9, #0xfffffffc +slti s4, s9, #0xfffffffe +slti s4, s9, #0xffffffff +slti s4, s9, #0 +slti s4, s9, #1 +slti s4, s9, #2 +slti s4, s9, #4 +slti s4, s9, #8 +slti s4, s9, #0x10 +slti s4, s9, #0x20 +slti s4, s9, #0x40 +slti s4, s9, #0x80 +slti s4, s9, #0x100 +slti s4, s9, #0x200 +slti s4, s9, #0x400 +slti s4, s9, #0x7ff +slti s4, t6, #0xfffff801 +slti s4, t6, #0xfffffc00 +slti s4, t6, #0xfffffe00 +slti s4, t6, #0xffffff00 +slti s4, t6, #0xffffff80 +slti s4, t6, #0xffffffc0 +slti s4, t6, #0xffffffe0 +slti s4, t6, #0xfffffff0 +slti s4, t6, #0xfffffff8 +slti s4, t6, #0xfffffffc +slti s4, t6, #0xfffffffe +slti s4, t6, #0xffffffff +slti s4, t6, #0 +slti s4, t6, #1 +slti s4, t6, #2 +slti s4, t6, #4 +slti s4, t6, #8 +slti s4, t6, #0x10 +slti s4, t6, #0x20 +slti s4, t6, #0x40 +slti s4, t6, #0x80 +slti s4, t6, #0x100 +slti s4, t6, #0x200 +slti s4, t6, #0x400 +slti s4, t6, #0x7ff +slti s9, zero, #0xfffff801 +slti s9, zero, #0xfffffc00 +slti s9, zero, #0xfffffe00 +slti s9, zero, #0xffffff00 +slti s9, zero, #0xffffff80 +slti s9, zero, #0xffffffc0 +slti s9, zero, #0xffffffe0 +slti s9, zero, #0xfffffff0 +slti s9, zero, #0xfffffff8 +slti s9, zero, #0xfffffffc +slti s9, zero, #0xfffffffe +slti s9, zero, #0xffffffff +slti s9, zero, #0 +slti s9, zero, #1 +slti s9, zero, #2 +slti s9, zero, #4 +slti s9, zero, #8 +slti s9, zero, #0x10 +slti s9, zero, #0x20 +slti s9, zero, #0x40 +slti s9, zero, #0x80 +slti s9, zero, #0x100 +slti s9, zero, #0x200 +slti s9, zero, #0x400 +slti s9, zero, #0x7ff +slti s9, ra, #0xfffff801 +slti s9, ra, #0xfffffc00 +slti s9, ra, #0xfffffe00 +slti s9, ra, #0xffffff00 +slti s9, ra, #0xffffff80 +slti s9, ra, #0xffffffc0 +slti s9, ra, #0xffffffe0 +slti s9, ra, #0xfffffff0 +slti s9, ra, #0xfffffff8 +slti s9, ra, #0xfffffffc +slti s9, ra, #0xfffffffe +slti s9, ra, #0xffffffff +slti s9, ra, #0 +slti s9, ra, #1 +slti s9, ra, #2 +slti s9, ra, #4 +slti s9, ra, #8 +slti s9, ra, #0x10 +slti s9, ra, #0x20 +slti s9, ra, #0x40 +slti s9, ra, #0x80 +slti s9, ra, #0x100 +slti s9, ra, #0x200 +slti s9, ra, #0x400 +slti s9, ra, #0x7ff +slti s9, t0, #0xfffff801 +slti s9, t0, #0xfffffc00 +slti s9, t0, #0xfffffe00 +slti s9, t0, #0xffffff00 +slti s9, t0, #0xffffff80 +slti s9, t0, #0xffffffc0 +slti s9, t0, #0xffffffe0 +slti s9, t0, #0xfffffff0 +slti s9, t0, #0xfffffff8 +slti s9, t0, #0xfffffffc +slti s9, t0, #0xfffffffe +slti s9, t0, #0xffffffff +slti s9, t0, #0 +slti s9, t0, #1 +slti s9, t0, #2 +slti s9, t0, #4 +slti s9, t0, #8 +slti s9, t0, #0x10 +slti s9, t0, #0x20 +slti s9, t0, #0x40 +slti s9, t0, #0x80 +slti s9, t0, #0x100 +slti s9, t0, #0x200 +slti s9, t0, #0x400 +slti s9, t0, #0x7ff +slti s9, a0, #0xfffff801 +slti s9, a0, #0xfffffc00 +slti s9, a0, #0xfffffe00 +slti s9, a0, #0xffffff00 +slti s9, a0, #0xffffff80 +slti s9, a0, #0xffffffc0 +slti s9, a0, #0xffffffe0 +slti s9, a0, #0xfffffff0 +slti s9, a0, #0xfffffff8 +slti s9, a0, #0xfffffffc +slti s9, a0, #0xfffffffe +slti s9, a0, #0xffffffff +slti s9, a0, #0 +slti s9, a0, #1 +slti s9, a0, #2 +slti s9, a0, #4 +slti s9, a0, #8 +slti s9, a0, #0x10 +slti s9, a0, #0x20 +slti s9, a0, #0x40 +slti s9, a0, #0x80 +slti s9, a0, #0x100 +slti s9, a0, #0x200 +slti s9, a0, #0x400 +slti s9, a0, #0x7ff +slti s9, a5, #0xfffff801 +slti s9, a5, #0xfffffc00 +slti s9, a5, #0xfffffe00 +slti s9, a5, #0xffffff00 +slti s9, a5, #0xffffff80 +slti s9, a5, #0xffffffc0 +slti s9, a5, #0xffffffe0 +slti s9, a5, #0xfffffff0 +slti s9, a5, #0xfffffff8 +slti s9, a5, #0xfffffffc +slti s9, a5, #0xfffffffe +slti s9, a5, #0xffffffff +slti s9, a5, #0 +slti s9, a5, #1 +slti s9, a5, #2 +slti s9, a5, #4 +slti s9, a5, #8 +slti s9, a5, #0x10 +slti s9, a5, #0x20 +slti s9, a5, #0x40 +slti s9, a5, #0x80 +slti s9, a5, #0x100 +slti s9, a5, #0x200 +slti s9, a5, #0x400 +slti s9, a5, #0x7ff +slti s9, s4, #0xfffff801 +slti s9, s4, #0xfffffc00 +slti s9, s4, #0xfffffe00 +slti s9, s4, #0xffffff00 +slti s9, s4, #0xffffff80 +slti s9, s4, #0xffffffc0 +slti s9, s4, #0xffffffe0 +slti s9, s4, #0xfffffff0 +slti s9, s4, #0xfffffff8 +slti s9, s4, #0xfffffffc +slti s9, s4, #0xfffffffe +slti s9, s4, #0xffffffff +slti s9, s4, #0 +slti s9, s4, #1 +slti s9, s4, #2 +slti s9, s4, #4 +slti s9, s4, #8 +slti s9, s4, #0x10 +slti s9, s4, #0x20 +slti s9, s4, #0x40 +slti s9, s4, #0x80 +slti s9, s4, #0x100 +slti s9, s4, #0x200 +slti s9, s4, #0x400 +slti s9, s4, #0x7ff +slti s9, s9, #0xfffff801 +slti s9, s9, #0xfffffc00 +slti s9, s9, #0xfffffe00 +slti s9, s9, #0xffffff00 +slti s9, s9, #0xffffff80 +slti s9, s9, #0xffffffc0 +slti s9, s9, #0xffffffe0 +slti s9, s9, #0xfffffff0 +slti s9, s9, #0xfffffff8 +slti s9, s9, #0xfffffffc +slti s9, s9, #0xfffffffe +slti s9, s9, #0xffffffff +slti s9, s9, #0 +slti s9, s9, #1 +slti s9, s9, #2 +slti s9, s9, #4 +slti s9, s9, #8 +slti s9, s9, #0x10 +slti s9, s9, #0x20 +slti s9, s9, #0x40 +slti s9, s9, #0x80 +slti s9, s9, #0x100 +slti s9, s9, #0x200 +slti s9, s9, #0x400 +slti s9, s9, #0x7ff +slti s9, t6, #0xfffff801 +slti s9, t6, #0xfffffc00 +slti s9, t6, #0xfffffe00 +slti s9, t6, #0xffffff00 +slti s9, t6, #0xffffff80 +slti s9, t6, #0xffffffc0 +slti s9, t6, #0xffffffe0 +slti s9, t6, #0xfffffff0 +slti s9, t6, #0xfffffff8 +slti s9, t6, #0xfffffffc +slti s9, t6, #0xfffffffe +slti s9, t6, #0xffffffff +slti s9, t6, #0 +slti s9, t6, #1 +slti s9, t6, #2 +slti s9, t6, #4 +slti s9, t6, #8 +slti s9, t6, #0x10 +slti s9, t6, #0x20 +slti s9, t6, #0x40 +slti s9, t6, #0x80 +slti s9, t6, #0x100 +slti s9, t6, #0x200 +slti s9, t6, #0x400 +slti s9, t6, #0x7ff +slti t6, zero, #0xfffff801 +slti t6, zero, #0xfffffc00 +slti t6, zero, #0xfffffe00 +slti t6, zero, #0xffffff00 +slti t6, zero, #0xffffff80 +slti t6, zero, #0xffffffc0 +slti t6, zero, #0xffffffe0 +slti t6, zero, #0xfffffff0 +slti t6, zero, #0xfffffff8 +slti t6, zero, #0xfffffffc +slti t6, zero, #0xfffffffe +slti t6, zero, #0xffffffff +slti t6, zero, #0 +slti t6, zero, #1 +slti t6, zero, #2 +slti t6, zero, #4 +slti t6, zero, #8 +slti t6, zero, #0x10 +slti t6, zero, #0x20 +slti t6, zero, #0x40 +slti t6, zero, #0x80 +slti t6, zero, #0x100 +slti t6, zero, #0x200 +slti t6, zero, #0x400 +slti t6, zero, #0x7ff +slti t6, ra, #0xfffff801 +slti t6, ra, #0xfffffc00 +slti t6, ra, #0xfffffe00 +slti t6, ra, #0xffffff00 +slti t6, ra, #0xffffff80 +slti t6, ra, #0xffffffc0 +slti t6, ra, #0xffffffe0 +slti t6, ra, #0xfffffff0 +slti t6, ra, #0xfffffff8 +slti t6, ra, #0xfffffffc +slti t6, ra, #0xfffffffe +slti t6, ra, #0xffffffff +slti t6, ra, #0 +slti t6, ra, #1 +slti t6, ra, #2 +slti t6, ra, #4 +slti t6, ra, #8 +slti t6, ra, #0x10 +slti t6, ra, #0x20 +slti t6, ra, #0x40 +slti t6, ra, #0x80 +slti t6, ra, #0x100 +slti t6, ra, #0x200 +slti t6, ra, #0x400 +slti t6, ra, #0x7ff +slti t6, t0, #0xfffff801 +slti t6, t0, #0xfffffc00 +slti t6, t0, #0xfffffe00 +slti t6, t0, #0xffffff00 +slti t6, t0, #0xffffff80 +slti t6, t0, #0xffffffc0 +slti t6, t0, #0xffffffe0 +slti t6, t0, #0xfffffff0 +slti t6, t0, #0xfffffff8 +slti t6, t0, #0xfffffffc +slti t6, t0, #0xfffffffe +slti t6, t0, #0xffffffff +slti t6, t0, #0 +slti t6, t0, #1 +slti t6, t0, #2 +slti t6, t0, #4 +slti t6, t0, #8 +slti t6, t0, #0x10 +slti t6, t0, #0x20 +slti t6, t0, #0x40 +slti t6, t0, #0x80 +slti t6, t0, #0x100 +slti t6, t0, #0x200 +slti t6, t0, #0x400 +slti t6, t0, #0x7ff +slti t6, a0, #0xfffff801 +slti t6, a0, #0xfffffc00 +slti t6, a0, #0xfffffe00 +slti t6, a0, #0xffffff00 +slti t6, a0, #0xffffff80 +slti t6, a0, #0xffffffc0 +slti t6, a0, #0xffffffe0 +slti t6, a0, #0xfffffff0 +slti t6, a0, #0xfffffff8 +slti t6, a0, #0xfffffffc +slti t6, a0, #0xfffffffe +slti t6, a0, #0xffffffff +slti t6, a0, #0 +slti t6, a0, #1 +slti t6, a0, #2 +slti t6, a0, #4 +slti t6, a0, #8 +slti t6, a0, #0x10 +slti t6, a0, #0x20 +slti t6, a0, #0x40 +slti t6, a0, #0x80 +slti t6, a0, #0x100 +slti t6, a0, #0x200 +slti t6, a0, #0x400 +slti t6, a0, #0x7ff +slti t6, a5, #0xfffff801 +slti t6, a5, #0xfffffc00 +slti t6, a5, #0xfffffe00 +slti t6, a5, #0xffffff00 +slti t6, a5, #0xffffff80 +slti t6, a5, #0xffffffc0 +slti t6, a5, #0xffffffe0 +slti t6, a5, #0xfffffff0 +slti t6, a5, #0xfffffff8 +slti t6, a5, #0xfffffffc +slti t6, a5, #0xfffffffe +slti t6, a5, #0xffffffff +slti t6, a5, #0 +slti t6, a5, #1 +slti t6, a5, #2 +slti t6, a5, #4 +slti t6, a5, #8 +slti t6, a5, #0x10 +slti t6, a5, #0x20 +slti t6, a5, #0x40 +slti t6, a5, #0x80 +slti t6, a5, #0x100 +slti t6, a5, #0x200 +slti t6, a5, #0x400 +slti t6, a5, #0x7ff +slti t6, s4, #0xfffff801 +slti t6, s4, #0xfffffc00 +slti t6, s4, #0xfffffe00 +slti t6, s4, #0xffffff00 +slti t6, s4, #0xffffff80 +slti t6, s4, #0xffffffc0 +slti t6, s4, #0xffffffe0 +slti t6, s4, #0xfffffff0 +slti t6, s4, #0xfffffff8 +slti t6, s4, #0xfffffffc +slti t6, s4, #0xfffffffe +slti t6, s4, #0xffffffff +slti t6, s4, #0 +slti t6, s4, #1 +slti t6, s4, #2 +slti t6, s4, #4 +slti t6, s4, #8 +slti t6, s4, #0x10 +slti t6, s4, #0x20 +slti t6, s4, #0x40 +slti t6, s4, #0x80 +slti t6, s4, #0x100 +slti t6, s4, #0x200 +slti t6, s4, #0x400 +slti t6, s4, #0x7ff +slti t6, s9, #0xfffff801 +slti t6, s9, #0xfffffc00 +slti t6, s9, #0xfffffe00 +slti t6, s9, #0xffffff00 +slti t6, s9, #0xffffff80 +slti t6, s9, #0xffffffc0 +slti t6, s9, #0xffffffe0 +slti t6, s9, #0xfffffff0 +slti t6, s9, #0xfffffff8 +slti t6, s9, #0xfffffffc +slti t6, s9, #0xfffffffe +slti t6, s9, #0xffffffff +slti t6, s9, #0 +slti t6, s9, #1 +slti t6, s9, #2 +slti t6, s9, #4 +slti t6, s9, #8 +slti t6, s9, #0x10 +slti t6, s9, #0x20 +slti t6, s9, #0x40 +slti t6, s9, #0x80 +slti t6, s9, #0x100 +slti t6, s9, #0x200 +slti t6, s9, #0x400 +slti t6, s9, #0x7ff +slti t6, t6, #0xfffff801 +slti t6, t6, #0xfffffc00 +slti t6, t6, #0xfffffe00 +slti t6, t6, #0xffffff00 +slti t6, t6, #0xffffff80 +slti t6, t6, #0xffffffc0 +slti t6, t6, #0xffffffe0 +slti t6, t6, #0xfffffff0 +slti t6, t6, #0xfffffff8 +slti t6, t6, #0xfffffffc +slti t6, t6, #0xfffffffe +slti t6, t6, #0xffffffff +slti t6, t6, #0 +slti t6, t6, #1 +slti t6, t6, #2 +slti t6, t6, #4 +slti t6, t6, #8 +slti t6, t6, #0x10 +slti t6, t6, #0x20 +slti t6, t6, #0x40 +slti t6, t6, #0x80 +slti t6, t6, #0x100 +slti t6, t6, #0x200 +slti t6, t6, #0x400 +slti t6, t6, #0x7ff diff --git a/tests/riscv/rv32i/sltiu.asm b/tests/riscv/rv32i/sltiu.asm new file mode 100644 index 0000000..c964656 --- /dev/null +++ b/tests/riscv/rv32i/sltiu.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +sltiu zero, zero, #-2047 +sltiu zero, zero, #-1024 +sltiu zero, zero, #-512 +sltiu zero, zero, #-256 +sltiu zero, zero, #-128 +sltiu zero, zero, #-64 +sltiu zero, zero, #-32 +sltiu zero, zero, #-16 +sltiu zero, zero, #-8 +sltiu zero, zero, #-4 +sltiu zero, zero, #-2 +sltiu zero, zero, #-1 +sltiu zero, zero, #0 +sltiu zero, zero, #1 +sltiu zero, zero, #2 +sltiu zero, zero, #4 +sltiu zero, zero, #8 +sltiu zero, zero, #16 +sltiu zero, zero, #32 +sltiu zero, zero, #64 +sltiu zero, zero, #128 +sltiu zero, zero, #256 +sltiu zero, zero, #512 +sltiu zero, zero, #1024 +sltiu zero, zero, #2047 +sltiu zero, ra, #-2047 +sltiu zero, ra, #-1024 +sltiu zero, ra, #-512 +sltiu zero, ra, #-256 +sltiu zero, ra, #-128 +sltiu zero, ra, #-64 +sltiu zero, ra, #-32 +sltiu zero, ra, #-16 +sltiu zero, ra, #-8 +sltiu zero, ra, #-4 +sltiu zero, ra, #-2 +sltiu zero, ra, #-1 +sltiu zero, ra, #0 +sltiu zero, ra, #1 +sltiu zero, ra, #2 +sltiu zero, ra, #4 +sltiu zero, ra, #8 +sltiu zero, ra, #16 +sltiu zero, ra, #32 +sltiu zero, ra, #64 +sltiu zero, ra, #128 +sltiu zero, ra, #256 +sltiu zero, ra, #512 +sltiu zero, ra, #1024 +sltiu zero, ra, #2047 +sltiu zero, t0, #-2047 +sltiu zero, t0, #-1024 +sltiu zero, t0, #-512 +sltiu zero, t0, #-256 +sltiu zero, t0, #-128 +sltiu zero, t0, #-64 +sltiu zero, t0, #-32 +sltiu zero, t0, #-16 +sltiu zero, t0, #-8 +sltiu zero, t0, #-4 +sltiu zero, t0, #-2 +sltiu zero, t0, #-1 +sltiu zero, t0, #0 +sltiu zero, t0, #1 +sltiu zero, t0, #2 +sltiu zero, t0, #4 +sltiu zero, t0, #8 +sltiu zero, t0, #16 +sltiu zero, t0, #32 +sltiu zero, t0, #64 +sltiu zero, t0, #128 +sltiu zero, t0, #256 +sltiu zero, t0, #512 +sltiu zero, t0, #1024 +sltiu zero, t0, #2047 +sltiu zero, a0, #-2047 +sltiu zero, a0, #-1024 +sltiu zero, a0, #-512 +sltiu zero, a0, #-256 +sltiu zero, a0, #-128 +sltiu zero, a0, #-64 +sltiu zero, a0, #-32 +sltiu zero, a0, #-16 +sltiu zero, a0, #-8 +sltiu zero, a0, #-4 +sltiu zero, a0, #-2 +sltiu zero, a0, #-1 +sltiu zero, a0, #0 +sltiu zero, a0, #1 +sltiu zero, a0, #2 +sltiu zero, a0, #4 +sltiu zero, a0, #8 +sltiu zero, a0, #16 +sltiu zero, a0, #32 +sltiu zero, a0, #64 +sltiu zero, a0, #128 +sltiu zero, a0, #256 +sltiu zero, a0, #512 +sltiu zero, a0, #1024 +sltiu zero, a0, #2047 +sltiu zero, a5, #-2047 +sltiu zero, a5, #-1024 +sltiu zero, a5, #-512 +sltiu zero, a5, #-256 +sltiu zero, a5, #-128 +sltiu zero, a5, #-64 +sltiu zero, a5, #-32 +sltiu zero, a5, #-16 +sltiu zero, a5, #-8 +sltiu zero, a5, #-4 +sltiu zero, a5, #-2 +sltiu zero, a5, #-1 +sltiu zero, a5, #0 +sltiu zero, a5, #1 +sltiu zero, a5, #2 +sltiu zero, a5, #4 +sltiu zero, a5, #8 +sltiu zero, a5, #16 +sltiu zero, a5, #32 +sltiu zero, a5, #64 +sltiu zero, a5, #128 +sltiu zero, a5, #256 +sltiu zero, a5, #512 +sltiu zero, a5, #1024 +sltiu zero, a5, #2047 +sltiu zero, s4, #-2047 +sltiu zero, s4, #-1024 +sltiu zero, s4, #-512 +sltiu zero, s4, #-256 +sltiu zero, s4, #-128 +sltiu zero, s4, #-64 +sltiu zero, s4, #-32 +sltiu zero, s4, #-16 +sltiu zero, s4, #-8 +sltiu zero, s4, #-4 +sltiu zero, s4, #-2 +sltiu zero, s4, #-1 +sltiu zero, s4, #0 +sltiu zero, s4, #1 +sltiu zero, s4, #2 +sltiu zero, s4, #4 +sltiu zero, s4, #8 +sltiu zero, s4, #16 +sltiu zero, s4, #32 +sltiu zero, s4, #64 +sltiu zero, s4, #128 +sltiu zero, s4, #256 +sltiu zero, s4, #512 +sltiu zero, s4, #1024 +sltiu zero, s4, #2047 +sltiu zero, s9, #-2047 +sltiu zero, s9, #-1024 +sltiu zero, s9, #-512 +sltiu zero, s9, #-256 +sltiu zero, s9, #-128 +sltiu zero, s9, #-64 +sltiu zero, s9, #-32 +sltiu zero, s9, #-16 +sltiu zero, s9, #-8 +sltiu zero, s9, #-4 +sltiu zero, s9, #-2 +sltiu zero, s9, #-1 +sltiu zero, s9, #0 +sltiu zero, s9, #1 +sltiu zero, s9, #2 +sltiu zero, s9, #4 +sltiu zero, s9, #8 +sltiu zero, s9, #16 +sltiu zero, s9, #32 +sltiu zero, s9, #64 +sltiu zero, s9, #128 +sltiu zero, s9, #256 +sltiu zero, s9, #512 +sltiu zero, s9, #1024 +sltiu zero, s9, #2047 +sltiu zero, t6, #-2047 +sltiu zero, t6, #-1024 +sltiu zero, t6, #-512 +sltiu zero, t6, #-256 +sltiu zero, t6, #-128 +sltiu zero, t6, #-64 +sltiu zero, t6, #-32 +sltiu zero, t6, #-16 +sltiu zero, t6, #-8 +sltiu zero, t6, #-4 +sltiu zero, t6, #-2 +sltiu zero, t6, #-1 +sltiu zero, t6, #0 +sltiu zero, t6, #1 +sltiu zero, t6, #2 +sltiu zero, t6, #4 +sltiu zero, t6, #8 +sltiu zero, t6, #16 +sltiu zero, t6, #32 +sltiu zero, t6, #64 +sltiu zero, t6, #128 +sltiu zero, t6, #256 +sltiu zero, t6, #512 +sltiu zero, t6, #1024 +sltiu zero, t6, #2047 +sltiu ra, zero, #-2047 +sltiu ra, zero, #-1024 +sltiu ra, zero, #-512 +sltiu ra, zero, #-256 +sltiu ra, zero, #-128 +sltiu ra, zero, #-64 +sltiu ra, zero, #-32 +sltiu ra, zero, #-16 +sltiu ra, zero, #-8 +sltiu ra, zero, #-4 +sltiu ra, zero, #-2 +sltiu ra, zero, #-1 +sltiu ra, zero, #0 +sltiu ra, zero, #1 +sltiu ra, zero, #2 +sltiu ra, zero, #4 +sltiu ra, zero, #8 +sltiu ra, zero, #16 +sltiu ra, zero, #32 +sltiu ra, zero, #64 +sltiu ra, zero, #128 +sltiu ra, zero, #256 +sltiu ra, zero, #512 +sltiu ra, zero, #1024 +sltiu ra, zero, #2047 +sltiu ra, ra, #-2047 +sltiu ra, ra, #-1024 +sltiu ra, ra, #-512 +sltiu ra, ra, #-256 +sltiu ra, ra, #-128 +sltiu ra, ra, #-64 +sltiu ra, ra, #-32 +sltiu ra, ra, #-16 +sltiu ra, ra, #-8 +sltiu ra, ra, #-4 +sltiu ra, ra, #-2 +sltiu ra, ra, #-1 +sltiu ra, ra, #0 +sltiu ra, ra, #1 +sltiu ra, ra, #2 +sltiu ra, ra, #4 +sltiu ra, ra, #8 +sltiu ra, ra, #16 +sltiu ra, ra, #32 +sltiu ra, ra, #64 +sltiu ra, ra, #128 +sltiu ra, ra, #256 +sltiu ra, ra, #512 +sltiu ra, ra, #1024 +sltiu ra, ra, #2047 +sltiu ra, t0, #-2047 +sltiu ra, t0, #-1024 +sltiu ra, t0, #-512 +sltiu ra, t0, #-256 +sltiu ra, t0, #-128 +sltiu ra, t0, #-64 +sltiu ra, t0, #-32 +sltiu ra, t0, #-16 +sltiu ra, t0, #-8 +sltiu ra, t0, #-4 +sltiu ra, t0, #-2 +sltiu ra, t0, #-1 +sltiu ra, t0, #0 +sltiu ra, t0, #1 +sltiu ra, t0, #2 +sltiu ra, t0, #4 +sltiu ra, t0, #8 +sltiu ra, t0, #16 +sltiu ra, t0, #32 +sltiu ra, t0, #64 +sltiu ra, t0, #128 +sltiu ra, t0, #256 +sltiu ra, t0, #512 +sltiu ra, t0, #1024 +sltiu ra, t0, #2047 +sltiu ra, a0, #-2047 +sltiu ra, a0, #-1024 +sltiu ra, a0, #-512 +sltiu ra, a0, #-256 +sltiu ra, a0, #-128 +sltiu ra, a0, #-64 +sltiu ra, a0, #-32 +sltiu ra, a0, #-16 +sltiu ra, a0, #-8 +sltiu ra, a0, #-4 +sltiu ra, a0, #-2 +sltiu ra, a0, #-1 +sltiu ra, a0, #0 +sltiu ra, a0, #1 +sltiu ra, a0, #2 +sltiu ra, a0, #4 +sltiu ra, a0, #8 +sltiu ra, a0, #16 +sltiu ra, a0, #32 +sltiu ra, a0, #64 +sltiu ra, a0, #128 +sltiu ra, a0, #256 +sltiu ra, a0, #512 +sltiu ra, a0, #1024 +sltiu ra, a0, #2047 +sltiu ra, a5, #-2047 +sltiu ra, a5, #-1024 +sltiu ra, a5, #-512 +sltiu ra, a5, #-256 +sltiu ra, a5, #-128 +sltiu ra, a5, #-64 +sltiu ra, a5, #-32 +sltiu ra, a5, #-16 +sltiu ra, a5, #-8 +sltiu ra, a5, #-4 +sltiu ra, a5, #-2 +sltiu ra, a5, #-1 +sltiu ra, a5, #0 +sltiu ra, a5, #1 +sltiu ra, a5, #2 +sltiu ra, a5, #4 +sltiu ra, a5, #8 +sltiu ra, a5, #16 +sltiu ra, a5, #32 +sltiu ra, a5, #64 +sltiu ra, a5, #128 +sltiu ra, a5, #256 +sltiu ra, a5, #512 +sltiu ra, a5, #1024 +sltiu ra, a5, #2047 +sltiu ra, s4, #-2047 +sltiu ra, s4, #-1024 +sltiu ra, s4, #-512 +sltiu ra, s4, #-256 +sltiu ra, s4, #-128 +sltiu ra, s4, #-64 +sltiu ra, s4, #-32 +sltiu ra, s4, #-16 +sltiu ra, s4, #-8 +sltiu ra, s4, #-4 +sltiu ra, s4, #-2 +sltiu ra, s4, #-1 +sltiu ra, s4, #0 +sltiu ra, s4, #1 +sltiu ra, s4, #2 +sltiu ra, s4, #4 +sltiu ra, s4, #8 +sltiu ra, s4, #16 +sltiu ra, s4, #32 +sltiu ra, s4, #64 +sltiu ra, s4, #128 +sltiu ra, s4, #256 +sltiu ra, s4, #512 +sltiu ra, s4, #1024 +sltiu ra, s4, #2047 +sltiu ra, s9, #-2047 +sltiu ra, s9, #-1024 +sltiu ra, s9, #-512 +sltiu ra, s9, #-256 +sltiu ra, s9, #-128 +sltiu ra, s9, #-64 +sltiu ra, s9, #-32 +sltiu ra, s9, #-16 +sltiu ra, s9, #-8 +sltiu ra, s9, #-4 +sltiu ra, s9, #-2 +sltiu ra, s9, #-1 +sltiu ra, s9, #0 +sltiu ra, s9, #1 +sltiu ra, s9, #2 +sltiu ra, s9, #4 +sltiu ra, s9, #8 +sltiu ra, s9, #16 +sltiu ra, s9, #32 +sltiu ra, s9, #64 +sltiu ra, s9, #128 +sltiu ra, s9, #256 +sltiu ra, s9, #512 +sltiu ra, s9, #1024 +sltiu ra, s9, #2047 +sltiu ra, t6, #-2047 +sltiu ra, t6, #-1024 +sltiu ra, t6, #-512 +sltiu ra, t6, #-256 +sltiu ra, t6, #-128 +sltiu ra, t6, #-64 +sltiu ra, t6, #-32 +sltiu ra, t6, #-16 +sltiu ra, t6, #-8 +sltiu ra, t6, #-4 +sltiu ra, t6, #-2 +sltiu ra, t6, #-1 +sltiu ra, t6, #0 +sltiu ra, t6, #1 +sltiu ra, t6, #2 +sltiu ra, t6, #4 +sltiu ra, t6, #8 +sltiu ra, t6, #16 +sltiu ra, t6, #32 +sltiu ra, t6, #64 +sltiu ra, t6, #128 +sltiu ra, t6, #256 +sltiu ra, t6, #512 +sltiu ra, t6, #1024 +sltiu ra, t6, #2047 +sltiu t0, zero, #-2047 +sltiu t0, zero, #-1024 +sltiu t0, zero, #-512 +sltiu t0, zero, #-256 +sltiu t0, zero, #-128 +sltiu t0, zero, #-64 +sltiu t0, zero, #-32 +sltiu t0, zero, #-16 +sltiu t0, zero, #-8 +sltiu t0, zero, #-4 +sltiu t0, zero, #-2 +sltiu t0, zero, #-1 +sltiu t0, zero, #0 +sltiu t0, zero, #1 +sltiu t0, zero, #2 +sltiu t0, zero, #4 +sltiu t0, zero, #8 +sltiu t0, zero, #16 +sltiu t0, zero, #32 +sltiu t0, zero, #64 +sltiu t0, zero, #128 +sltiu t0, zero, #256 +sltiu t0, zero, #512 +sltiu t0, zero, #1024 +sltiu t0, zero, #2047 +sltiu t0, ra, #-2047 +sltiu t0, ra, #-1024 +sltiu t0, ra, #-512 +sltiu t0, ra, #-256 +sltiu t0, ra, #-128 +sltiu t0, ra, #-64 +sltiu t0, ra, #-32 +sltiu t0, ra, #-16 +sltiu t0, ra, #-8 +sltiu t0, ra, #-4 +sltiu t0, ra, #-2 +sltiu t0, ra, #-1 +sltiu t0, ra, #0 +sltiu t0, ra, #1 +sltiu t0, ra, #2 +sltiu t0, ra, #4 +sltiu t0, ra, #8 +sltiu t0, ra, #16 +sltiu t0, ra, #32 +sltiu t0, ra, #64 +sltiu t0, ra, #128 +sltiu t0, ra, #256 +sltiu t0, ra, #512 +sltiu t0, ra, #1024 +sltiu t0, ra, #2047 +sltiu t0, t0, #-2047 +sltiu t0, t0, #-1024 +sltiu t0, t0, #-512 +sltiu t0, t0, #-256 +sltiu t0, t0, #-128 +sltiu t0, t0, #-64 +sltiu t0, t0, #-32 +sltiu t0, t0, #-16 +sltiu t0, t0, #-8 +sltiu t0, t0, #-4 +sltiu t0, t0, #-2 +sltiu t0, t0, #-1 +sltiu t0, t0, #0 +sltiu t0, t0, #1 +sltiu t0, t0, #2 +sltiu t0, t0, #4 +sltiu t0, t0, #8 +sltiu t0, t0, #16 +sltiu t0, t0, #32 +sltiu t0, t0, #64 +sltiu t0, t0, #128 +sltiu t0, t0, #256 +sltiu t0, t0, #512 +sltiu t0, t0, #1024 +sltiu t0, t0, #2047 +sltiu t0, a0, #-2047 +sltiu t0, a0, #-1024 +sltiu t0, a0, #-512 +sltiu t0, a0, #-256 +sltiu t0, a0, #-128 +sltiu t0, a0, #-64 +sltiu t0, a0, #-32 +sltiu t0, a0, #-16 +sltiu t0, a0, #-8 +sltiu t0, a0, #-4 +sltiu t0, a0, #-2 +sltiu t0, a0, #-1 +sltiu t0, a0, #0 +sltiu t0, a0, #1 +sltiu t0, a0, #2 +sltiu t0, a0, #4 +sltiu t0, a0, #8 +sltiu t0, a0, #16 +sltiu t0, a0, #32 +sltiu t0, a0, #64 +sltiu t0, a0, #128 +sltiu t0, a0, #256 +sltiu t0, a0, #512 +sltiu t0, a0, #1024 +sltiu t0, a0, #2047 +sltiu t0, a5, #-2047 +sltiu t0, a5, #-1024 +sltiu t0, a5, #-512 +sltiu t0, a5, #-256 +sltiu t0, a5, #-128 +sltiu t0, a5, #-64 +sltiu t0, a5, #-32 +sltiu t0, a5, #-16 +sltiu t0, a5, #-8 +sltiu t0, a5, #-4 +sltiu t0, a5, #-2 +sltiu t0, a5, #-1 +sltiu t0, a5, #0 +sltiu t0, a5, #1 +sltiu t0, a5, #2 +sltiu t0, a5, #4 +sltiu t0, a5, #8 +sltiu t0, a5, #16 +sltiu t0, a5, #32 +sltiu t0, a5, #64 +sltiu t0, a5, #128 +sltiu t0, a5, #256 +sltiu t0, a5, #512 +sltiu t0, a5, #1024 +sltiu t0, a5, #2047 +sltiu t0, s4, #-2047 +sltiu t0, s4, #-1024 +sltiu t0, s4, #-512 +sltiu t0, s4, #-256 +sltiu t0, s4, #-128 +sltiu t0, s4, #-64 +sltiu t0, s4, #-32 +sltiu t0, s4, #-16 +sltiu t0, s4, #-8 +sltiu t0, s4, #-4 +sltiu t0, s4, #-2 +sltiu t0, s4, #-1 +sltiu t0, s4, #0 +sltiu t0, s4, #1 +sltiu t0, s4, #2 +sltiu t0, s4, #4 +sltiu t0, s4, #8 +sltiu t0, s4, #16 +sltiu t0, s4, #32 +sltiu t0, s4, #64 +sltiu t0, s4, #128 +sltiu t0, s4, #256 +sltiu t0, s4, #512 +sltiu t0, s4, #1024 +sltiu t0, s4, #2047 +sltiu t0, s9, #-2047 +sltiu t0, s9, #-1024 +sltiu t0, s9, #-512 +sltiu t0, s9, #-256 +sltiu t0, s9, #-128 +sltiu t0, s9, #-64 +sltiu t0, s9, #-32 +sltiu t0, s9, #-16 +sltiu t0, s9, #-8 +sltiu t0, s9, #-4 +sltiu t0, s9, #-2 +sltiu t0, s9, #-1 +sltiu t0, s9, #0 +sltiu t0, s9, #1 +sltiu t0, s9, #2 +sltiu t0, s9, #4 +sltiu t0, s9, #8 +sltiu t0, s9, #16 +sltiu t0, s9, #32 +sltiu t0, s9, #64 +sltiu t0, s9, #128 +sltiu t0, s9, #256 +sltiu t0, s9, #512 +sltiu t0, s9, #1024 +sltiu t0, s9, #2047 +sltiu t0, t6, #-2047 +sltiu t0, t6, #-1024 +sltiu t0, t6, #-512 +sltiu t0, t6, #-256 +sltiu t0, t6, #-128 +sltiu t0, t6, #-64 +sltiu t0, t6, #-32 +sltiu t0, t6, #-16 +sltiu t0, t6, #-8 +sltiu t0, t6, #-4 +sltiu t0, t6, #-2 +sltiu t0, t6, #-1 +sltiu t0, t6, #0 +sltiu t0, t6, #1 +sltiu t0, t6, #2 +sltiu t0, t6, #4 +sltiu t0, t6, #8 +sltiu t0, t6, #16 +sltiu t0, t6, #32 +sltiu t0, t6, #64 +sltiu t0, t6, #128 +sltiu t0, t6, #256 +sltiu t0, t6, #512 +sltiu t0, t6, #1024 +sltiu t0, t6, #2047 +sltiu a0, zero, #-2047 +sltiu a0, zero, #-1024 +sltiu a0, zero, #-512 +sltiu a0, zero, #-256 +sltiu a0, zero, #-128 +sltiu a0, zero, #-64 +sltiu a0, zero, #-32 +sltiu a0, zero, #-16 +sltiu a0, zero, #-8 +sltiu a0, zero, #-4 +sltiu a0, zero, #-2 +sltiu a0, zero, #-1 +sltiu a0, zero, #0 +sltiu a0, zero, #1 +sltiu a0, zero, #2 +sltiu a0, zero, #4 +sltiu a0, zero, #8 +sltiu a0, zero, #16 +sltiu a0, zero, #32 +sltiu a0, zero, #64 +sltiu a0, zero, #128 +sltiu a0, zero, #256 +sltiu a0, zero, #512 +sltiu a0, zero, #1024 +sltiu a0, zero, #2047 +sltiu a0, ra, #-2047 +sltiu a0, ra, #-1024 +sltiu a0, ra, #-512 +sltiu a0, ra, #-256 +sltiu a0, ra, #-128 +sltiu a0, ra, #-64 +sltiu a0, ra, #-32 +sltiu a0, ra, #-16 +sltiu a0, ra, #-8 +sltiu a0, ra, #-4 +sltiu a0, ra, #-2 +sltiu a0, ra, #-1 +sltiu a0, ra, #0 +sltiu a0, ra, #1 +sltiu a0, ra, #2 +sltiu a0, ra, #4 +sltiu a0, ra, #8 +sltiu a0, ra, #16 +sltiu a0, ra, #32 +sltiu a0, ra, #64 +sltiu a0, ra, #128 +sltiu a0, ra, #256 +sltiu a0, ra, #512 +sltiu a0, ra, #1024 +sltiu a0, ra, #2047 +sltiu a0, t0, #-2047 +sltiu a0, t0, #-1024 +sltiu a0, t0, #-512 +sltiu a0, t0, #-256 +sltiu a0, t0, #-128 +sltiu a0, t0, #-64 +sltiu a0, t0, #-32 +sltiu a0, t0, #-16 +sltiu a0, t0, #-8 +sltiu a0, t0, #-4 +sltiu a0, t0, #-2 +sltiu a0, t0, #-1 +sltiu a0, t0, #0 +sltiu a0, t0, #1 +sltiu a0, t0, #2 +sltiu a0, t0, #4 +sltiu a0, t0, #8 +sltiu a0, t0, #16 +sltiu a0, t0, #32 +sltiu a0, t0, #64 +sltiu a0, t0, #128 +sltiu a0, t0, #256 +sltiu a0, t0, #512 +sltiu a0, t0, #1024 +sltiu a0, t0, #2047 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a0, t6, #-1024 +sltiu a0, t6, #-512 +sltiu a0, t6, #-256 +sltiu a0, t6, #-128 +sltiu a0, t6, #-64 +sltiu a0, t6, #-32 +sltiu a0, t6, #-16 +sltiu a0, t6, #-8 +sltiu a0, t6, #-4 +sltiu a0, t6, #-2 +sltiu a0, t6, #-1 +sltiu a0, t6, #0 +sltiu a0, t6, #1 +sltiu a0, t6, #2 +sltiu a0, t6, #4 +sltiu a0, t6, #8 +sltiu a0, t6, #16 +sltiu a0, t6, #32 +sltiu a0, t6, #64 +sltiu a0, t6, #128 +sltiu a0, t6, #256 +sltiu a0, t6, #512 +sltiu a0, t6, #1024 +sltiu a0, t6, #2047 +sltiu a5, zero, #-2047 +sltiu a5, zero, #-1024 +sltiu a5, zero, #-512 +sltiu a5, zero, #-256 +sltiu a5, zero, #-128 +sltiu a5, zero, #-64 +sltiu a5, zero, #-32 +sltiu a5, zero, #-16 +sltiu a5, zero, #-8 +sltiu a5, zero, #-4 +sltiu a5, zero, #-2 +sltiu a5, zero, #-1 +sltiu a5, zero, #0 +sltiu a5, zero, #1 +sltiu a5, zero, #2 +sltiu a5, zero, #4 +sltiu a5, zero, #8 +sltiu a5, zero, #16 +sltiu a5, zero, #32 +sltiu a5, zero, #64 +sltiu a5, zero, #128 +sltiu a5, zero, #256 +sltiu a5, zero, #512 +sltiu a5, zero, #1024 +sltiu a5, zero, #2047 +sltiu a5, ra, #-2047 +sltiu a5, ra, #-1024 +sltiu a5, ra, #-512 +sltiu a5, ra, #-256 +sltiu a5, ra, #-128 +sltiu a5, ra, #-64 +sltiu a5, ra, #-32 +sltiu a5, ra, #-16 +sltiu a5, ra, #-8 +sltiu a5, ra, #-4 +sltiu a5, ra, #-2 +sltiu a5, ra, #-1 +sltiu a5, ra, #0 +sltiu a5, ra, #1 +sltiu a5, ra, #2 +sltiu a5, ra, #4 +sltiu a5, ra, #8 +sltiu a5, ra, #16 +sltiu a5, ra, #32 +sltiu a5, ra, #64 +sltiu a5, ra, #128 +sltiu a5, ra, #256 +sltiu a5, ra, #512 +sltiu a5, ra, #1024 +sltiu a5, ra, #2047 +sltiu a5, t0, #-2047 +sltiu a5, t0, #-1024 +sltiu a5, t0, #-512 +sltiu a5, t0, #-256 +sltiu a5, t0, #-128 +sltiu a5, t0, #-64 +sltiu a5, t0, #-32 +sltiu a5, t0, #-16 +sltiu a5, t0, #-8 +sltiu a5, t0, #-4 +sltiu a5, t0, #-2 +sltiu a5, t0, #-1 +sltiu a5, t0, #0 +sltiu a5, t0, #1 +sltiu a5, t0, #2 +sltiu a5, t0, #4 +sltiu a5, t0, #8 +sltiu a5, t0, #16 +sltiu a5, t0, #32 +sltiu a5, t0, #64 +sltiu a5, t0, #128 +sltiu a5, t0, #256 +sltiu a5, t0, #512 +sltiu a5, t0, #1024 +sltiu a5, t0, #2047 +sltiu a5, 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#-1024 +sltiu a5, t6, #-512 +sltiu a5, t6, #-256 +sltiu a5, t6, #-128 +sltiu a5, t6, #-64 +sltiu a5, t6, #-32 +sltiu a5, t6, #-16 +sltiu a5, t6, #-8 +sltiu a5, t6, #-4 +sltiu a5, t6, #-2 +sltiu a5, t6, #-1 +sltiu a5, t6, #0 +sltiu a5, t6, #1 +sltiu a5, t6, #2 +sltiu a5, t6, #4 +sltiu a5, t6, #8 +sltiu a5, t6, #16 +sltiu a5, t6, #32 +sltiu a5, t6, #64 +sltiu a5, t6, #128 +sltiu a5, t6, #256 +sltiu a5, t6, #512 +sltiu a5, t6, #1024 +sltiu a5, t6, #2047 +sltiu s4, zero, #-2047 +sltiu s4, zero, #-1024 +sltiu s4, zero, #-512 +sltiu s4, zero, #-256 +sltiu s4, zero, #-128 +sltiu s4, zero, #-64 +sltiu s4, zero, #-32 +sltiu s4, zero, #-16 +sltiu s4, zero, #-8 +sltiu s4, zero, #-4 +sltiu s4, zero, #-2 +sltiu s4, zero, #-1 +sltiu s4, zero, #0 +sltiu s4, zero, #1 +sltiu s4, zero, #2 +sltiu s4, zero, #4 +sltiu s4, zero, #8 +sltiu s4, zero, #16 +sltiu s4, zero, #32 +sltiu s4, zero, #64 +sltiu s4, zero, #128 +sltiu s4, zero, #256 +sltiu s4, zero, #512 +sltiu s4, zero, #1024 +sltiu s4, zero, #2047 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zKZ<@#-rdQ&J2flr@B{bwiHBwK?oQs_$-6swcc-Q?g9B#Vz`HwncPH=es*Eb5%BV7`j4Gqbs4}XIDx=D%GOCO!qspiQT3zhN7aw2AGK}F;3?kV6ZE6%N7aw2A5}l9e$;k0b6F<+nDk@n zR(MwWG3m#oACrDe`Z4Lpq#u)hOkHCJ&+rzXp&yfeO!_hD$D|*VeoWnL=CV}%sQOX+ z7531NsvlK9s(w`csQOX$qv}WP8#8#0clZMRsQOX$qv}W1kE$QFpUqsBNk68|Emqh= zKPLT{^kdSGNk1n2nDk@Pk7?7G!3(^{SLny2ACrDe`Z4Lpq#u)hO!`svqi%1p!XElj z^`q)X)sLzlRX?hJRQ;&i#tdHK1HM5&s(w`csQOX$qv}W1kE$P4KdOFI{iym;^`q)X t)sLzlRX?hJRQ;&>QT3zhN7aw2A5}l9epLOa`cd_x>POX&svq^?^8aa78OHzs literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/sltiu.disasm b/tests/riscv/rv32i/sltiu.disasm new file mode 100644 index 0000000..0f69e07 --- /dev/null +++ b/tests/riscv/rv32i/sltiu.disasm @@ -0,0 +1,1600 @@ +sltiu zero, zero, #0xfffff801 +sltiu zero, zero, #0xfffffc00 +sltiu zero, zero, #0xfffffe00 +sltiu zero, zero, #0xffffff00 +sltiu zero, zero, #0xffffff80 +sltiu zero, zero, #0xffffffc0 +sltiu zero, zero, #0xffffffe0 +sltiu zero, zero, #0xfffffff0 +sltiu zero, zero, #0xfffffff8 +sltiu zero, zero, #0xfffffffc +sltiu zero, zero, #0xfffffffe +sltiu zero, zero, #0xffffffff +sltiu zero, zero, #0 +sltiu zero, zero, #1 +sltiu zero, zero, #2 +sltiu zero, zero, #4 +sltiu zero, zero, #8 +sltiu zero, zero, #0x10 +sltiu zero, zero, #0x20 +sltiu zero, zero, #0x40 +sltiu zero, zero, #0x80 +sltiu zero, zero, #0x100 +sltiu zero, zero, #0x200 +sltiu zero, zero, #0x400 +sltiu zero, zero, #0x7ff +sltiu zero, ra, #0xfffff801 +sltiu zero, ra, #0xfffffc00 +sltiu zero, ra, #0xfffffe00 +sltiu zero, ra, #0xffffff00 +sltiu zero, ra, #0xffffff80 +sltiu zero, ra, #0xffffffc0 +sltiu zero, ra, #0xffffffe0 +sltiu zero, ra, #0xfffffff0 +sltiu zero, ra, #0xfffffff8 +sltiu zero, ra, #0xfffffffc +sltiu zero, ra, #0xfffffffe +sltiu zero, ra, #0xffffffff +sltiu zero, ra, #0 +sltiu zero, ra, #1 +sltiu zero, ra, #2 +sltiu zero, ra, #4 +sltiu zero, ra, #8 +sltiu zero, ra, #0x10 +sltiu zero, ra, #0x20 +sltiu zero, ra, #0x40 +sltiu zero, ra, #0x80 +sltiu zero, ra, #0x100 +sltiu zero, ra, #0x200 +sltiu zero, ra, #0x400 +sltiu zero, ra, #0x7ff +sltiu zero, t0, #0xfffff801 +sltiu zero, t0, #0xfffffc00 +sltiu zero, t0, #0xfffffe00 +sltiu zero, t0, #0xffffff00 +sltiu zero, t0, #0xffffff80 +sltiu zero, t0, #0xffffffc0 +sltiu zero, t0, #0xffffffe0 +sltiu zero, t0, #0xfffffff0 +sltiu zero, t0, #0xfffffff8 +sltiu zero, t0, #0xfffffffc +sltiu zero, t0, #0xfffffffe +sltiu zero, t0, #0xffffffff +sltiu zero, t0, #0 +sltiu zero, t0, #1 +sltiu zero, t0, #2 +sltiu zero, t0, #4 +sltiu zero, t0, #8 +sltiu zero, t0, #0x10 +sltiu zero, t0, #0x20 +sltiu zero, t0, #0x40 +sltiu zero, t0, #0x80 +sltiu zero, t0, #0x100 +sltiu zero, t0, #0x200 +sltiu zero, t0, #0x400 +sltiu zero, t0, #0x7ff +sltiu zero, a0, #0xfffff801 +sltiu zero, a0, #0xfffffc00 +sltiu zero, a0, #0xfffffe00 +sltiu zero, a0, #0xffffff00 +sltiu zero, a0, #0xffffff80 +sltiu zero, a0, #0xffffffc0 +sltiu zero, a0, #0xffffffe0 +sltiu zero, a0, #0xfffffff0 +sltiu zero, a0, #0xfffffff8 +sltiu zero, a0, #0xfffffffc +sltiu zero, a0, #0xfffffffe +sltiu zero, a0, #0xffffffff +sltiu zero, a0, #0 +sltiu zero, a0, #1 +sltiu zero, a0, #2 +sltiu zero, a0, #4 +sltiu zero, a0, #8 +sltiu zero, a0, #0x10 +sltiu zero, a0, #0x20 +sltiu zero, a0, #0x40 +sltiu zero, a0, #0x80 +sltiu zero, a0, #0x100 +sltiu zero, a0, #0x200 +sltiu zero, a0, #0x400 +sltiu zero, a0, #0x7ff +sltiu zero, a5, #0xfffff801 +sltiu zero, a5, #0xfffffc00 +sltiu zero, a5, #0xfffffe00 +sltiu zero, a5, #0xffffff00 +sltiu zero, a5, #0xffffff80 +sltiu zero, a5, #0xffffffc0 +sltiu zero, a5, #0xffffffe0 +sltiu zero, a5, #0xfffffff0 +sltiu zero, a5, #0xfffffff8 +sltiu zero, a5, #0xfffffffc +sltiu zero, a5, #0xfffffffe +sltiu zero, a5, #0xffffffff +sltiu zero, a5, #0 +sltiu zero, a5, #1 +sltiu zero, a5, #2 +sltiu zero, a5, #4 +sltiu zero, a5, #8 +sltiu zero, a5, #0x10 +sltiu zero, a5, #0x20 +sltiu zero, a5, #0x40 +sltiu zero, a5, #0x80 +sltiu zero, a5, #0x100 +sltiu zero, a5, #0x200 +sltiu zero, a5, #0x400 +sltiu zero, a5, #0x7ff +sltiu zero, s4, #0xfffff801 +sltiu zero, s4, #0xfffffc00 +sltiu zero, s4, #0xfffffe00 +sltiu zero, s4, #0xffffff00 +sltiu zero, s4, #0xffffff80 +sltiu zero, s4, #0xffffffc0 +sltiu zero, s4, #0xffffffe0 +sltiu zero, s4, #0xfffffff0 +sltiu zero, s4, #0xfffffff8 +sltiu zero, s4, #0xfffffffc +sltiu zero, s4, #0xfffffffe +sltiu zero, s4, #0xffffffff +sltiu zero, s4, #0 +sltiu zero, s4, #1 +sltiu zero, s4, #2 +sltiu zero, s4, #4 +sltiu zero, s4, #8 +sltiu zero, s4, #0x10 +sltiu zero, s4, #0x20 +sltiu zero, s4, #0x40 +sltiu zero, s4, #0x80 +sltiu zero, s4, #0x100 +sltiu zero, s4, #0x200 +sltiu zero, s4, #0x400 +sltiu zero, s4, #0x7ff +sltiu zero, s9, #0xfffff801 +sltiu zero, s9, #0xfffffc00 +sltiu zero, s9, #0xfffffe00 +sltiu zero, s9, #0xffffff00 +sltiu zero, s9, #0xffffff80 +sltiu zero, s9, #0xffffffc0 +sltiu zero, s9, #0xffffffe0 +sltiu zero, s9, #0xfffffff0 +sltiu zero, s9, #0xfffffff8 +sltiu zero, s9, #0xfffffffc +sltiu zero, s9, #0xfffffffe +sltiu zero, s9, #0xffffffff +sltiu zero, s9, #0 +sltiu zero, s9, #1 +sltiu zero, s9, #2 +sltiu zero, s9, #4 +sltiu zero, s9, #8 +sltiu zero, s9, #0x10 +sltiu zero, s9, #0x20 +sltiu zero, s9, #0x40 +sltiu zero, s9, #0x80 +sltiu zero, s9, #0x100 +sltiu zero, s9, #0x200 +sltiu zero, s9, #0x400 +sltiu zero, s9, #0x7ff +sltiu zero, t6, #0xfffff801 +sltiu zero, t6, #0xfffffc00 +sltiu zero, t6, #0xfffffe00 +sltiu zero, t6, #0xffffff00 +sltiu zero, t6, #0xffffff80 +sltiu zero, t6, #0xffffffc0 +sltiu zero, t6, #0xffffffe0 +sltiu zero, t6, #0xfffffff0 +sltiu zero, t6, #0xfffffff8 +sltiu zero, t6, #0xfffffffc +sltiu zero, t6, #0xfffffffe +sltiu zero, t6, #0xffffffff +sltiu zero, t6, #0 +sltiu zero, t6, #1 +sltiu zero, t6, #2 +sltiu zero, t6, #4 +sltiu zero, t6, #8 +sltiu zero, t6, #0x10 +sltiu zero, t6, #0x20 +sltiu zero, t6, #0x40 +sltiu zero, t6, #0x80 +sltiu zero, t6, #0x100 +sltiu zero, t6, #0x200 +sltiu zero, t6, #0x400 +sltiu zero, t6, #0x7ff +sltiu ra, zero, #0xfffff801 +sltiu ra, zero, #0xfffffc00 +sltiu ra, zero, #0xfffffe00 +sltiu ra, zero, #0xffffff00 +sltiu ra, zero, #0xffffff80 +sltiu ra, zero, #0xffffffc0 +sltiu ra, zero, #0xffffffe0 +sltiu ra, zero, #0xfffffff0 +sltiu ra, zero, #0xfffffff8 +sltiu ra, zero, #0xfffffffc +sltiu ra, zero, #0xfffffffe +sltiu ra, zero, #0xffffffff +sltiu ra, zero, #0 +sltiu ra, zero, #1 +sltiu ra, zero, #2 +sltiu ra, zero, #4 +sltiu ra, zero, #8 +sltiu ra, zero, #0x10 +sltiu ra, zero, #0x20 +sltiu ra, zero, #0x40 +sltiu ra, zero, #0x80 +sltiu ra, zero, #0x100 +sltiu ra, zero, #0x200 +sltiu ra, zero, #0x400 +sltiu ra, zero, #0x7ff +sltiu ra, ra, #0xfffff801 +sltiu ra, ra, #0xfffffc00 +sltiu ra, ra, #0xfffffe00 +sltiu ra, ra, #0xffffff00 +sltiu ra, ra, #0xffffff80 +sltiu ra, ra, #0xffffffc0 +sltiu ra, ra, #0xffffffe0 +sltiu ra, ra, #0xfffffff0 +sltiu ra, ra, #0xfffffff8 +sltiu ra, ra, #0xfffffffc +sltiu ra, ra, #0xfffffffe +sltiu ra, ra, #0xffffffff +sltiu ra, ra, #0 +sltiu ra, ra, #1 +sltiu ra, ra, #2 +sltiu ra, ra, #4 +sltiu ra, ra, #8 +sltiu ra, ra, #0x10 +sltiu ra, ra, #0x20 +sltiu ra, ra, #0x40 +sltiu ra, ra, #0x80 +sltiu ra, ra, #0x100 +sltiu ra, ra, #0x200 +sltiu ra, ra, #0x400 +sltiu ra, ra, #0x7ff +sltiu ra, t0, #0xfffff801 +sltiu ra, t0, #0xfffffc00 +sltiu ra, t0, #0xfffffe00 +sltiu ra, t0, #0xffffff00 +sltiu ra, t0, #0xffffff80 +sltiu ra, t0, #0xffffffc0 +sltiu ra, t0, #0xffffffe0 +sltiu ra, t0, #0xfffffff0 +sltiu ra, t0, #0xfffffff8 +sltiu ra, t0, #0xfffffffc +sltiu ra, t0, #0xfffffffe +sltiu ra, t0, #0xffffffff +sltiu ra, t0, #0 +sltiu ra, t0, #1 +sltiu ra, t0, #2 +sltiu ra, t0, #4 +sltiu ra, t0, #8 +sltiu ra, t0, #0x10 +sltiu ra, t0, #0x20 +sltiu ra, t0, #0x40 +sltiu ra, t0, #0x80 +sltiu ra, t0, #0x100 +sltiu ra, t0, #0x200 +sltiu ra, t0, #0x400 +sltiu ra, t0, #0x7ff +sltiu ra, a0, #0xfffff801 +sltiu ra, a0, #0xfffffc00 +sltiu ra, a0, #0xfffffe00 +sltiu ra, a0, #0xffffff00 +sltiu ra, a0, #0xffffff80 +sltiu ra, a0, #0xffffffc0 +sltiu ra, a0, #0xffffffe0 +sltiu ra, a0, #0xfffffff0 +sltiu ra, a0, #0xfffffff8 +sltiu ra, a0, #0xfffffffc +sltiu ra, a0, #0xfffffffe +sltiu ra, a0, #0xffffffff +sltiu ra, a0, #0 +sltiu ra, a0, #1 +sltiu ra, a0, #2 +sltiu ra, a0, #4 +sltiu ra, a0, #8 +sltiu ra, a0, #0x10 +sltiu ra, a0, #0x20 +sltiu ra, a0, #0x40 +sltiu ra, a0, #0x80 +sltiu ra, a0, #0x100 +sltiu ra, a0, #0x200 +sltiu ra, a0, #0x400 +sltiu ra, a0, #0x7ff +sltiu ra, a5, #0xfffff801 +sltiu ra, a5, #0xfffffc00 +sltiu ra, a5, #0xfffffe00 +sltiu ra, a5, #0xffffff00 +sltiu ra, a5, #0xffffff80 +sltiu ra, a5, #0xffffffc0 +sltiu ra, a5, #0xffffffe0 +sltiu ra, a5, #0xfffffff0 +sltiu ra, a5, #0xfffffff8 +sltiu ra, a5, #0xfffffffc +sltiu ra, a5, #0xfffffffe +sltiu ra, a5, #0xffffffff +sltiu ra, a5, #0 +sltiu ra, a5, #1 +sltiu ra, a5, #2 +sltiu ra, a5, #4 +sltiu ra, a5, #8 +sltiu ra, a5, #0x10 +sltiu ra, a5, #0x20 +sltiu ra, a5, #0x40 +sltiu ra, a5, #0x80 +sltiu ra, a5, #0x100 +sltiu ra, a5, #0x200 +sltiu ra, a5, #0x400 +sltiu ra, a5, #0x7ff +sltiu ra, s4, #0xfffff801 +sltiu ra, s4, #0xfffffc00 +sltiu ra, s4, #0xfffffe00 +sltiu ra, s4, #0xffffff00 +sltiu ra, s4, #0xffffff80 +sltiu ra, s4, #0xffffffc0 +sltiu ra, s4, #0xffffffe0 +sltiu ra, s4, #0xfffffff0 +sltiu ra, s4, #0xfffffff8 +sltiu ra, s4, #0xfffffffc +sltiu ra, s4, #0xfffffffe +sltiu ra, s4, #0xffffffff +sltiu ra, s4, #0 +sltiu ra, s4, #1 +sltiu ra, s4, #2 +sltiu ra, s4, #4 +sltiu ra, s4, #8 +sltiu ra, s4, #0x10 +sltiu ra, s4, #0x20 +sltiu ra, s4, #0x40 +sltiu ra, s4, #0x80 +sltiu ra, s4, #0x100 +sltiu ra, s4, #0x200 +sltiu ra, s4, #0x400 +sltiu ra, s4, #0x7ff +sltiu ra, s9, #0xfffff801 +sltiu ra, s9, #0xfffffc00 +sltiu ra, s9, #0xfffffe00 +sltiu ra, s9, #0xffffff00 +sltiu ra, s9, #0xffffff80 +sltiu ra, s9, #0xffffffc0 +sltiu ra, s9, #0xffffffe0 +sltiu ra, s9, #0xfffffff0 +sltiu ra, s9, #0xfffffff8 +sltiu ra, s9, #0xfffffffc +sltiu ra, s9, #0xfffffffe +sltiu ra, s9, #0xffffffff +sltiu ra, s9, #0 +sltiu ra, s9, #1 +sltiu ra, s9, #2 +sltiu ra, s9, #4 +sltiu ra, s9, #8 +sltiu ra, s9, #0x10 +sltiu ra, s9, #0x20 +sltiu ra, s9, #0x40 +sltiu ra, s9, #0x80 +sltiu ra, s9, #0x100 +sltiu ra, s9, #0x200 +sltiu ra, s9, #0x400 +sltiu ra, s9, #0x7ff +sltiu ra, t6, #0xfffff801 +sltiu ra, t6, #0xfffffc00 +sltiu ra, t6, #0xfffffe00 +sltiu ra, t6, #0xffffff00 +sltiu ra, t6, #0xffffff80 +sltiu ra, t6, #0xffffffc0 +sltiu ra, t6, #0xffffffe0 +sltiu ra, t6, #0xfffffff0 +sltiu ra, t6, #0xfffffff8 +sltiu ra, t6, #0xfffffffc +sltiu ra, t6, #0xfffffffe +sltiu ra, t6, #0xffffffff +sltiu ra, t6, #0 +sltiu ra, t6, #1 +sltiu ra, t6, #2 +sltiu ra, t6, #4 +sltiu ra, t6, #8 +sltiu ra, t6, #0x10 +sltiu ra, t6, #0x20 +sltiu ra, t6, #0x40 +sltiu ra, t6, #0x80 +sltiu ra, t6, #0x100 +sltiu ra, t6, #0x200 +sltiu ra, t6, #0x400 +sltiu ra, t6, #0x7ff +sltiu t0, zero, #0xfffff801 +sltiu t0, zero, #0xfffffc00 +sltiu t0, zero, #0xfffffe00 +sltiu t0, zero, #0xffffff00 +sltiu t0, zero, #0xffffff80 +sltiu t0, zero, #0xffffffc0 +sltiu t0, zero, #0xffffffe0 +sltiu t0, zero, #0xfffffff0 +sltiu t0, zero, #0xfffffff8 +sltiu t0, zero, #0xfffffffc +sltiu t0, zero, #0xfffffffe +sltiu t0, zero, #0xffffffff +sltiu t0, zero, #0 +sltiu t0, zero, #1 +sltiu t0, zero, #2 +sltiu t0, zero, #4 +sltiu t0, zero, #8 +sltiu t0, zero, #0x10 +sltiu t0, zero, #0x20 +sltiu t0, zero, #0x40 +sltiu t0, zero, #0x80 +sltiu t0, zero, #0x100 +sltiu t0, zero, #0x200 +sltiu t0, zero, #0x400 +sltiu t0, zero, #0x7ff +sltiu t0, ra, #0xfffff801 +sltiu t0, ra, #0xfffffc00 +sltiu t0, ra, #0xfffffe00 +sltiu t0, ra, #0xffffff00 +sltiu t0, ra, #0xffffff80 +sltiu t0, ra, #0xffffffc0 +sltiu t0, ra, #0xffffffe0 +sltiu t0, ra, #0xfffffff0 +sltiu t0, ra, #0xfffffff8 +sltiu t0, ra, #0xfffffffc +sltiu t0, ra, #0xfffffffe +sltiu t0, ra, #0xffffffff +sltiu t0, ra, #0 +sltiu t0, ra, #1 +sltiu t0, ra, #2 +sltiu t0, ra, #4 +sltiu t0, ra, #8 +sltiu t0, ra, #0x10 +sltiu t0, ra, #0x20 +sltiu t0, ra, #0x40 +sltiu t0, ra, #0x80 +sltiu t0, ra, #0x100 +sltiu t0, ra, #0x200 +sltiu t0, ra, #0x400 +sltiu t0, ra, #0x7ff +sltiu t0, t0, #0xfffff801 +sltiu t0, t0, #0xfffffc00 +sltiu t0, t0, #0xfffffe00 +sltiu t0, t0, #0xffffff00 +sltiu t0, t0, #0xffffff80 +sltiu t0, t0, #0xffffffc0 +sltiu t0, t0, #0xffffffe0 +sltiu t0, t0, #0xfffffff0 +sltiu t0, t0, #0xfffffff8 +sltiu t0, t0, #0xfffffffc +sltiu t0, t0, #0xfffffffe +sltiu t0, t0, #0xffffffff +sltiu t0, t0, #0 +sltiu t0, t0, #1 +sltiu t0, t0, #2 +sltiu t0, t0, #4 +sltiu t0, t0, #8 +sltiu t0, t0, #0x10 +sltiu t0, t0, #0x20 +sltiu t0, t0, #0x40 +sltiu t0, t0, #0x80 +sltiu t0, t0, #0x100 +sltiu t0, t0, #0x200 +sltiu t0, t0, #0x400 +sltiu t0, t0, #0x7ff +sltiu t0, a0, #0xfffff801 +sltiu t0, a0, #0xfffffc00 +sltiu t0, a0, #0xfffffe00 +sltiu t0, a0, #0xffffff00 +sltiu t0, a0, #0xffffff80 +sltiu t0, a0, #0xffffffc0 +sltiu t0, a0, #0xffffffe0 +sltiu t0, a0, #0xfffffff0 +sltiu t0, a0, #0xfffffff8 +sltiu t0, a0, #0xfffffffc +sltiu t0, a0, #0xfffffffe +sltiu t0, a0, #0xffffffff +sltiu t0, a0, #0 +sltiu t0, a0, #1 +sltiu t0, a0, #2 +sltiu t0, a0, #4 +sltiu t0, a0, #8 +sltiu t0, a0, #0x10 +sltiu t0, a0, #0x20 +sltiu t0, a0, #0x40 +sltiu t0, a0, #0x80 +sltiu t0, a0, #0x100 +sltiu t0, a0, #0x200 +sltiu t0, a0, #0x400 +sltiu t0, a0, #0x7ff +sltiu t0, a5, #0xfffff801 +sltiu t0, a5, #0xfffffc00 +sltiu t0, a5, #0xfffffe00 +sltiu t0, a5, #0xffffff00 +sltiu t0, a5, #0xffffff80 +sltiu t0, a5, #0xffffffc0 +sltiu t0, a5, #0xffffffe0 +sltiu t0, a5, #0xfffffff0 +sltiu t0, a5, #0xfffffff8 +sltiu t0, a5, #0xfffffffc +sltiu t0, a5, #0xfffffffe +sltiu t0, a5, #0xffffffff +sltiu t0, a5, #0 +sltiu t0, a5, #1 +sltiu t0, a5, #2 +sltiu t0, a5, #4 +sltiu t0, a5, #8 +sltiu t0, a5, #0x10 +sltiu t0, a5, #0x20 +sltiu t0, a5, #0x40 +sltiu t0, a5, #0x80 +sltiu t0, a5, #0x100 +sltiu t0, a5, #0x200 +sltiu t0, a5, #0x400 +sltiu t0, a5, #0x7ff +sltiu t0, s4, #0xfffff801 +sltiu t0, s4, #0xfffffc00 +sltiu t0, s4, #0xfffffe00 +sltiu t0, s4, #0xffffff00 +sltiu t0, s4, #0xffffff80 +sltiu t0, s4, #0xffffffc0 +sltiu t0, s4, #0xffffffe0 +sltiu t0, s4, #0xfffffff0 +sltiu t0, s4, #0xfffffff8 +sltiu t0, s4, #0xfffffffc +sltiu t0, s4, #0xfffffffe +sltiu t0, s4, #0xffffffff +sltiu t0, s4, #0 +sltiu t0, s4, #1 +sltiu t0, s4, #2 +sltiu t0, s4, #4 +sltiu t0, s4, #8 +sltiu t0, s4, #0x10 +sltiu t0, s4, #0x20 +sltiu t0, s4, #0x40 +sltiu t0, s4, #0x80 +sltiu t0, s4, #0x100 +sltiu t0, s4, #0x200 +sltiu t0, s4, #0x400 +sltiu t0, s4, #0x7ff +sltiu t0, s9, #0xfffff801 +sltiu t0, s9, #0xfffffc00 +sltiu t0, s9, #0xfffffe00 +sltiu t0, s9, #0xffffff00 +sltiu t0, s9, #0xffffff80 +sltiu t0, s9, #0xffffffc0 +sltiu t0, s9, #0xffffffe0 +sltiu t0, s9, #0xfffffff0 +sltiu t0, s9, #0xfffffff8 +sltiu t0, s9, #0xfffffffc +sltiu t0, s9, #0xfffffffe +sltiu t0, s9, #0xffffffff +sltiu t0, s9, #0 +sltiu t0, s9, #1 +sltiu t0, s9, #2 +sltiu t0, s9, #4 +sltiu t0, s9, #8 +sltiu t0, s9, #0x10 +sltiu t0, s9, #0x20 +sltiu t0, s9, #0x40 +sltiu t0, s9, #0x80 +sltiu t0, s9, #0x100 +sltiu t0, s9, #0x200 +sltiu t0, s9, #0x400 +sltiu t0, s9, #0x7ff +sltiu t0, t6, #0xfffff801 +sltiu t0, t6, #0xfffffc00 +sltiu t0, t6, #0xfffffe00 +sltiu t0, t6, #0xffffff00 +sltiu t0, t6, #0xffffff80 +sltiu t0, t6, #0xffffffc0 +sltiu t0, t6, #0xffffffe0 +sltiu t0, t6, #0xfffffff0 +sltiu t0, t6, #0xfffffff8 +sltiu t0, t6, #0xfffffffc +sltiu t0, t6, #0xfffffffe +sltiu t0, t6, #0xffffffff +sltiu t0, t6, #0 +sltiu t0, t6, #1 +sltiu t0, t6, #2 +sltiu t0, t6, #4 +sltiu t0, t6, #8 +sltiu t0, t6, #0x10 +sltiu t0, t6, #0x20 +sltiu t0, t6, #0x40 +sltiu t0, t6, #0x80 +sltiu t0, t6, #0x100 +sltiu t0, t6, #0x200 +sltiu t0, t6, #0x400 +sltiu t0, t6, #0x7ff +sltiu a0, zero, #0xfffff801 +sltiu a0, zero, #0xfffffc00 +sltiu a0, zero, #0xfffffe00 +sltiu a0, zero, #0xffffff00 +sltiu a0, zero, #0xffffff80 +sltiu a0, zero, #0xffffffc0 +sltiu a0, zero, #0xffffffe0 +sltiu a0, zero, #0xfffffff0 +sltiu a0, zero, #0xfffffff8 +sltiu a0, zero, #0xfffffffc +sltiu a0, zero, #0xfffffffe +sltiu a0, zero, #0xffffffff +sltiu a0, zero, #0 +sltiu a0, zero, #1 +sltiu a0, zero, #2 +sltiu a0, zero, #4 +sltiu a0, zero, #8 +sltiu a0, zero, #0x10 +sltiu a0, zero, #0x20 +sltiu a0, zero, #0x40 +sltiu a0, zero, #0x80 +sltiu a0, zero, #0x100 +sltiu a0, zero, #0x200 +sltiu a0, zero, #0x400 +sltiu a0, zero, #0x7ff +sltiu a0, ra, #0xfffff801 +sltiu a0, ra, #0xfffffc00 +sltiu a0, ra, #0xfffffe00 +sltiu a0, ra, #0xffffff00 +sltiu a0, ra, #0xffffff80 +sltiu a0, ra, #0xffffffc0 +sltiu a0, ra, #0xffffffe0 +sltiu a0, ra, #0xfffffff0 +sltiu a0, ra, #0xfffffff8 +sltiu a0, ra, #0xfffffffc +sltiu a0, ra, #0xfffffffe +sltiu a0, ra, #0xffffffff +sltiu a0, ra, #0 +sltiu a0, ra, #1 +sltiu a0, ra, #2 +sltiu a0, ra, #4 +sltiu a0, ra, #8 +sltiu a0, ra, #0x10 +sltiu a0, ra, #0x20 +sltiu a0, ra, #0x40 +sltiu a0, ra, #0x80 +sltiu a0, ra, #0x100 +sltiu a0, ra, #0x200 +sltiu a0, ra, #0x400 +sltiu a0, ra, #0x7ff +sltiu a0, t0, #0xfffff801 +sltiu a0, t0, #0xfffffc00 +sltiu a0, t0, #0xfffffe00 +sltiu a0, t0, #0xffffff00 +sltiu a0, t0, #0xffffff80 +sltiu a0, t0, #0xffffffc0 +sltiu a0, t0, #0xffffffe0 +sltiu a0, t0, #0xfffffff0 +sltiu a0, t0, #0xfffffff8 +sltiu a0, t0, #0xfffffffc +sltiu a0, t0, #0xfffffffe +sltiu a0, t0, #0xffffffff +sltiu a0, t0, #0 +sltiu a0, t0, #1 +sltiu a0, t0, #2 +sltiu a0, t0, #4 +sltiu a0, t0, #8 +sltiu a0, t0, #0x10 +sltiu a0, t0, #0x20 +sltiu a0, t0, #0x40 +sltiu a0, t0, #0x80 +sltiu a0, t0, #0x100 +sltiu a0, t0, #0x200 +sltiu a0, t0, #0x400 +sltiu a0, t0, #0x7ff +sltiu a0, a0, #0xfffff801 +sltiu a0, a0, #0xfffffc00 +sltiu a0, a0, #0xfffffe00 +sltiu a0, a0, #0xffffff00 +sltiu a0, a0, #0xffffff80 +sltiu a0, a0, #0xffffffc0 +sltiu a0, a0, #0xffffffe0 +sltiu a0, a0, #0xfffffff0 +sltiu a0, a0, #0xfffffff8 +sltiu a0, a0, #0xfffffffc +sltiu a0, a0, #0xfffffffe +sltiu a0, a0, #0xffffffff +sltiu a0, a0, #0 +sltiu a0, a0, #1 +sltiu a0, a0, #2 +sltiu a0, a0, #4 +sltiu a0, a0, #8 +sltiu a0, a0, #0x10 +sltiu a0, a0, #0x20 +sltiu a0, a0, #0x40 +sltiu a0, a0, #0x80 +sltiu a0, a0, #0x100 +sltiu a0, a0, #0x200 +sltiu a0, a0, #0x400 +sltiu a0, a0, #0x7ff +sltiu a0, a5, #0xfffff801 +sltiu a0, a5, #0xfffffc00 +sltiu a0, a5, #0xfffffe00 +sltiu a0, a5, #0xffffff00 +sltiu a0, a5, #0xffffff80 +sltiu a0, a5, #0xffffffc0 +sltiu a0, a5, #0xffffffe0 +sltiu a0, a5, #0xfffffff0 +sltiu a0, a5, #0xfffffff8 +sltiu a0, a5, #0xfffffffc +sltiu a0, a5, #0xfffffffe +sltiu a0, a5, #0xffffffff +sltiu a0, a5, #0 +sltiu a0, a5, #1 +sltiu a0, a5, #2 +sltiu a0, a5, #4 +sltiu a0, a5, #8 +sltiu a0, a5, #0x10 +sltiu a0, a5, #0x20 +sltiu a0, a5, #0x40 +sltiu a0, a5, #0x80 +sltiu a0, a5, #0x100 +sltiu a0, a5, #0x200 +sltiu a0, a5, #0x400 +sltiu a0, a5, #0x7ff +sltiu a0, s4, #0xfffff801 +sltiu a0, s4, #0xfffffc00 +sltiu a0, s4, #0xfffffe00 +sltiu a0, s4, #0xffffff00 +sltiu a0, s4, #0xffffff80 +sltiu a0, s4, #0xffffffc0 +sltiu a0, s4, #0xffffffe0 +sltiu a0, s4, #0xfffffff0 +sltiu a0, s4, #0xfffffff8 +sltiu a0, s4, #0xfffffffc +sltiu a0, s4, #0xfffffffe +sltiu a0, s4, #0xffffffff +sltiu a0, s4, #0 +sltiu a0, s4, #1 +sltiu a0, s4, #2 +sltiu a0, s4, #4 +sltiu a0, s4, #8 +sltiu a0, s4, #0x10 +sltiu a0, s4, #0x20 +sltiu a0, s4, #0x40 +sltiu a0, s4, #0x80 +sltiu a0, s4, #0x100 +sltiu a0, s4, #0x200 +sltiu a0, s4, #0x400 +sltiu a0, s4, #0x7ff +sltiu a0, s9, #0xfffff801 +sltiu a0, s9, #0xfffffc00 +sltiu a0, s9, #0xfffffe00 +sltiu a0, s9, #0xffffff00 +sltiu a0, s9, #0xffffff80 +sltiu a0, s9, #0xffffffc0 +sltiu a0, s9, #0xffffffe0 +sltiu a0, s9, #0xfffffff0 +sltiu a0, s9, #0xfffffff8 +sltiu a0, s9, #0xfffffffc +sltiu a0, s9, #0xfffffffe +sltiu a0, s9, #0xffffffff +sltiu a0, s9, #0 +sltiu a0, s9, #1 +sltiu a0, s9, #2 +sltiu a0, s9, #4 +sltiu a0, s9, #8 +sltiu a0, s9, #0x10 +sltiu a0, s9, #0x20 +sltiu a0, s9, #0x40 +sltiu a0, s9, #0x80 +sltiu a0, s9, #0x100 +sltiu a0, s9, #0x200 +sltiu a0, s9, #0x400 +sltiu a0, s9, #0x7ff +sltiu a0, t6, #0xfffff801 +sltiu a0, t6, #0xfffffc00 +sltiu a0, t6, #0xfffffe00 +sltiu a0, t6, #0xffffff00 +sltiu a0, t6, #0xffffff80 +sltiu a0, t6, #0xffffffc0 +sltiu a0, t6, #0xffffffe0 +sltiu a0, t6, #0xfffffff0 +sltiu a0, t6, #0xfffffff8 +sltiu a0, t6, #0xfffffffc +sltiu a0, t6, #0xfffffffe +sltiu a0, t6, #0xffffffff +sltiu a0, t6, #0 +sltiu a0, t6, #1 +sltiu a0, t6, #2 +sltiu a0, t6, #4 +sltiu a0, t6, #8 +sltiu a0, t6, #0x10 +sltiu a0, t6, #0x20 +sltiu a0, t6, #0x40 +sltiu a0, t6, #0x80 +sltiu a0, t6, #0x100 +sltiu a0, t6, #0x200 +sltiu a0, t6, #0x400 +sltiu a0, t6, #0x7ff +sltiu a5, zero, #0xfffff801 +sltiu a5, zero, #0xfffffc00 +sltiu a5, zero, #0xfffffe00 +sltiu a5, zero, #0xffffff00 +sltiu a5, zero, #0xffffff80 +sltiu a5, zero, #0xffffffc0 +sltiu a5, zero, #0xffffffe0 +sltiu a5, zero, #0xfffffff0 +sltiu a5, zero, #0xfffffff8 +sltiu a5, zero, #0xfffffffc +sltiu a5, zero, #0xfffffffe +sltiu a5, zero, #0xffffffff +sltiu a5, zero, #0 +sltiu a5, zero, #1 +sltiu a5, zero, #2 +sltiu a5, zero, #4 +sltiu a5, zero, #8 +sltiu a5, zero, #0x10 +sltiu a5, zero, #0x20 +sltiu a5, zero, #0x40 +sltiu a5, zero, #0x80 +sltiu a5, zero, #0x100 +sltiu a5, zero, #0x200 +sltiu a5, zero, #0x400 +sltiu a5, zero, #0x7ff +sltiu a5, ra, #0xfffff801 +sltiu a5, ra, #0xfffffc00 +sltiu a5, ra, #0xfffffe00 +sltiu a5, ra, #0xffffff00 +sltiu a5, ra, #0xffffff80 +sltiu a5, ra, #0xffffffc0 +sltiu a5, ra, #0xffffffe0 +sltiu a5, ra, #0xfffffff0 +sltiu a5, ra, #0xfffffff8 +sltiu a5, ra, #0xfffffffc +sltiu a5, ra, #0xfffffffe +sltiu a5, ra, #0xffffffff +sltiu a5, ra, #0 +sltiu a5, ra, #1 +sltiu a5, ra, #2 +sltiu a5, ra, #4 +sltiu a5, ra, #8 +sltiu a5, ra, #0x10 +sltiu a5, ra, #0x20 +sltiu a5, ra, #0x40 +sltiu a5, ra, #0x80 +sltiu a5, ra, #0x100 +sltiu a5, ra, #0x200 +sltiu a5, ra, #0x400 +sltiu a5, ra, #0x7ff +sltiu a5, t0, #0xfffff801 +sltiu a5, t0, #0xfffffc00 +sltiu a5, t0, #0xfffffe00 +sltiu a5, t0, #0xffffff00 +sltiu a5, t0, #0xffffff80 +sltiu a5, t0, #0xffffffc0 +sltiu a5, t0, #0xffffffe0 +sltiu a5, t0, #0xfffffff0 +sltiu a5, t0, #0xfffffff8 +sltiu a5, t0, #0xfffffffc +sltiu a5, t0, #0xfffffffe +sltiu a5, t0, #0xffffffff +sltiu a5, t0, #0 +sltiu a5, t0, #1 +sltiu a5, t0, #2 +sltiu a5, t0, #4 +sltiu a5, t0, #8 +sltiu a5, t0, #0x10 +sltiu a5, t0, #0x20 +sltiu a5, t0, #0x40 +sltiu a5, t0, #0x80 +sltiu a5, t0, #0x100 +sltiu a5, t0, #0x200 +sltiu a5, t0, #0x400 +sltiu a5, t0, #0x7ff +sltiu a5, a0, #0xfffff801 +sltiu a5, a0, #0xfffffc00 +sltiu a5, a0, #0xfffffe00 +sltiu a5, a0, #0xffffff00 +sltiu a5, a0, #0xffffff80 +sltiu a5, a0, #0xffffffc0 +sltiu a5, a0, #0xffffffe0 +sltiu a5, a0, #0xfffffff0 +sltiu a5, a0, #0xfffffff8 +sltiu a5, a0, #0xfffffffc +sltiu a5, a0, #0xfffffffe +sltiu a5, a0, #0xffffffff +sltiu a5, a0, #0 +sltiu a5, a0, #1 +sltiu a5, a0, #2 +sltiu a5, a0, #4 +sltiu a5, a0, #8 +sltiu a5, a0, #0x10 +sltiu a5, a0, #0x20 +sltiu a5, a0, #0x40 +sltiu a5, a0, #0x80 +sltiu a5, a0, #0x100 +sltiu a5, a0, #0x200 +sltiu a5, a0, #0x400 +sltiu a5, a0, #0x7ff +sltiu a5, a5, #0xfffff801 +sltiu a5, a5, #0xfffffc00 +sltiu a5, a5, #0xfffffe00 +sltiu a5, a5, #0xffffff00 +sltiu a5, a5, #0xffffff80 +sltiu a5, a5, #0xffffffc0 +sltiu a5, a5, #0xffffffe0 +sltiu a5, a5, #0xfffffff0 +sltiu a5, a5, #0xfffffff8 +sltiu a5, a5, #0xfffffffc +sltiu a5, a5, #0xfffffffe +sltiu a5, a5, #0xffffffff +sltiu a5, a5, #0 +sltiu a5, a5, #1 +sltiu a5, a5, #2 +sltiu a5, a5, #4 +sltiu a5, a5, #8 +sltiu a5, a5, #0x10 +sltiu a5, a5, #0x20 +sltiu a5, a5, #0x40 +sltiu a5, a5, #0x80 +sltiu a5, a5, #0x100 +sltiu a5, a5, #0x200 +sltiu a5, a5, #0x400 +sltiu a5, a5, #0x7ff +sltiu a5, s4, #0xfffff801 +sltiu a5, s4, #0xfffffc00 +sltiu a5, s4, #0xfffffe00 +sltiu a5, s4, #0xffffff00 +sltiu a5, s4, #0xffffff80 +sltiu a5, s4, #0xffffffc0 +sltiu a5, s4, #0xffffffe0 +sltiu a5, s4, #0xfffffff0 +sltiu a5, s4, #0xfffffff8 +sltiu a5, s4, #0xfffffffc +sltiu a5, s4, #0xfffffffe +sltiu a5, s4, #0xffffffff +sltiu a5, s4, #0 +sltiu a5, s4, #1 +sltiu a5, s4, #2 +sltiu a5, s4, #4 +sltiu a5, s4, #8 +sltiu a5, s4, #0x10 +sltiu a5, s4, #0x20 +sltiu a5, s4, #0x40 +sltiu a5, s4, #0x80 +sltiu a5, s4, #0x100 +sltiu a5, s4, #0x200 +sltiu a5, s4, #0x400 +sltiu a5, s4, #0x7ff +sltiu a5, s9, #0xfffff801 +sltiu a5, s9, #0xfffffc00 +sltiu a5, s9, #0xfffffe00 +sltiu a5, s9, #0xffffff00 +sltiu a5, s9, #0xffffff80 +sltiu a5, s9, #0xffffffc0 +sltiu a5, s9, #0xffffffe0 +sltiu a5, s9, #0xfffffff0 +sltiu a5, s9, #0xfffffff8 +sltiu a5, s9, #0xfffffffc +sltiu a5, s9, #0xfffffffe +sltiu a5, s9, #0xffffffff +sltiu a5, s9, #0 +sltiu a5, s9, #1 +sltiu a5, s9, #2 +sltiu a5, s9, #4 +sltiu a5, s9, #8 +sltiu a5, s9, #0x10 +sltiu a5, s9, #0x20 +sltiu a5, s9, #0x40 +sltiu a5, s9, #0x80 +sltiu a5, s9, #0x100 +sltiu a5, s9, #0x200 +sltiu a5, s9, #0x400 +sltiu a5, s9, #0x7ff +sltiu a5, t6, #0xfffff801 +sltiu a5, t6, #0xfffffc00 +sltiu a5, t6, #0xfffffe00 +sltiu a5, t6, #0xffffff00 +sltiu a5, t6, #0xffffff80 +sltiu a5, t6, #0xffffffc0 +sltiu a5, t6, #0xffffffe0 +sltiu a5, t6, #0xfffffff0 +sltiu a5, t6, #0xfffffff8 +sltiu a5, t6, #0xfffffffc +sltiu a5, t6, #0xfffffffe +sltiu a5, t6, #0xffffffff +sltiu a5, t6, #0 +sltiu a5, t6, #1 +sltiu a5, t6, #2 +sltiu a5, t6, #4 +sltiu a5, t6, #8 +sltiu a5, t6, #0x10 +sltiu a5, t6, #0x20 +sltiu a5, t6, #0x40 +sltiu a5, t6, #0x80 +sltiu a5, t6, #0x100 +sltiu a5, t6, #0x200 +sltiu a5, t6, #0x400 +sltiu a5, t6, #0x7ff +sltiu s4, zero, #0xfffff801 +sltiu s4, zero, #0xfffffc00 +sltiu s4, zero, #0xfffffe00 +sltiu s4, zero, #0xffffff00 +sltiu s4, zero, #0xffffff80 +sltiu s4, zero, #0xffffffc0 +sltiu s4, zero, #0xffffffe0 +sltiu s4, zero, #0xfffffff0 +sltiu s4, zero, #0xfffffff8 +sltiu s4, zero, #0xfffffffc +sltiu s4, zero, #0xfffffffe +sltiu s4, zero, #0xffffffff +sltiu s4, zero, #0 +sltiu s4, zero, #1 +sltiu s4, zero, #2 +sltiu s4, zero, #4 +sltiu s4, zero, #8 +sltiu s4, zero, #0x10 +sltiu s4, zero, #0x20 +sltiu s4, zero, #0x40 +sltiu s4, zero, #0x80 +sltiu s4, zero, #0x100 +sltiu s4, zero, #0x200 +sltiu s4, zero, #0x400 +sltiu s4, zero, #0x7ff +sltiu s4, ra, #0xfffff801 +sltiu s4, ra, #0xfffffc00 +sltiu s4, ra, #0xfffffe00 +sltiu s4, ra, #0xffffff00 +sltiu s4, ra, #0xffffff80 +sltiu s4, ra, #0xffffffc0 +sltiu s4, ra, #0xffffffe0 +sltiu s4, ra, #0xfffffff0 +sltiu s4, ra, #0xfffffff8 +sltiu s4, ra, #0xfffffffc +sltiu s4, ra, #0xfffffffe +sltiu s4, ra, #0xffffffff +sltiu s4, ra, #0 +sltiu s4, ra, #1 +sltiu s4, ra, #2 +sltiu s4, ra, #4 +sltiu s4, ra, #8 +sltiu s4, ra, #0x10 +sltiu s4, ra, #0x20 +sltiu s4, ra, #0x40 +sltiu s4, ra, #0x80 +sltiu s4, ra, #0x100 +sltiu s4, ra, #0x200 +sltiu s4, ra, #0x400 +sltiu s4, ra, #0x7ff +sltiu s4, t0, #0xfffff801 +sltiu s4, t0, #0xfffffc00 +sltiu s4, t0, #0xfffffe00 +sltiu s4, t0, #0xffffff00 +sltiu s4, t0, #0xffffff80 +sltiu s4, t0, #0xffffffc0 +sltiu s4, t0, #0xffffffe0 +sltiu s4, t0, #0xfffffff0 +sltiu s4, t0, #0xfffffff8 +sltiu s4, t0, #0xfffffffc +sltiu s4, t0, #0xfffffffe +sltiu s4, t0, #0xffffffff +sltiu s4, t0, #0 +sltiu s4, t0, #1 +sltiu s4, t0, #2 +sltiu s4, t0, #4 +sltiu s4, t0, #8 +sltiu s4, t0, #0x10 +sltiu s4, t0, #0x20 +sltiu s4, t0, #0x40 +sltiu s4, t0, #0x80 +sltiu s4, t0, #0x100 +sltiu s4, t0, #0x200 +sltiu s4, t0, #0x400 +sltiu s4, t0, #0x7ff +sltiu s4, a0, #0xfffff801 +sltiu s4, a0, #0xfffffc00 +sltiu s4, a0, #0xfffffe00 +sltiu s4, a0, #0xffffff00 +sltiu s4, a0, #0xffffff80 +sltiu s4, a0, #0xffffffc0 +sltiu s4, a0, #0xffffffe0 +sltiu s4, a0, #0xfffffff0 +sltiu s4, a0, #0xfffffff8 +sltiu s4, a0, #0xfffffffc +sltiu s4, a0, #0xfffffffe +sltiu s4, a0, #0xffffffff +sltiu s4, a0, #0 +sltiu s4, a0, #1 +sltiu s4, a0, #2 +sltiu s4, a0, #4 +sltiu s4, a0, #8 +sltiu s4, a0, #0x10 +sltiu s4, a0, #0x20 +sltiu s4, a0, #0x40 +sltiu s4, a0, #0x80 +sltiu s4, a0, #0x100 +sltiu s4, a0, #0x200 +sltiu s4, a0, #0x400 +sltiu s4, a0, #0x7ff +sltiu s4, a5, #0xfffff801 +sltiu s4, a5, #0xfffffc00 +sltiu s4, a5, #0xfffffe00 +sltiu s4, a5, #0xffffff00 +sltiu s4, a5, #0xffffff80 +sltiu s4, a5, #0xffffffc0 +sltiu s4, a5, #0xffffffe0 +sltiu s4, a5, #0xfffffff0 +sltiu s4, a5, #0xfffffff8 +sltiu s4, a5, #0xfffffffc +sltiu s4, a5, #0xfffffffe +sltiu s4, a5, #0xffffffff +sltiu s4, a5, #0 +sltiu s4, a5, #1 +sltiu s4, a5, #2 +sltiu s4, a5, #4 +sltiu s4, a5, #8 +sltiu s4, a5, #0x10 +sltiu s4, a5, #0x20 +sltiu s4, a5, #0x40 +sltiu s4, a5, #0x80 +sltiu s4, a5, #0x100 +sltiu s4, a5, #0x200 +sltiu s4, a5, #0x400 +sltiu s4, a5, #0x7ff +sltiu s4, s4, #0xfffff801 +sltiu s4, s4, #0xfffffc00 +sltiu s4, s4, #0xfffffe00 +sltiu s4, s4, #0xffffff00 +sltiu s4, s4, #0xffffff80 +sltiu s4, s4, #0xffffffc0 +sltiu s4, s4, #0xffffffe0 +sltiu s4, s4, #0xfffffff0 +sltiu s4, s4, #0xfffffff8 +sltiu s4, s4, #0xfffffffc +sltiu s4, s4, #0xfffffffe +sltiu s4, s4, #0xffffffff +sltiu s4, s4, #0 +sltiu s4, s4, #1 +sltiu s4, s4, #2 +sltiu s4, s4, #4 +sltiu s4, s4, #8 +sltiu s4, s4, #0x10 +sltiu s4, s4, #0x20 +sltiu s4, s4, #0x40 +sltiu s4, s4, #0x80 +sltiu s4, s4, #0x100 +sltiu s4, s4, #0x200 +sltiu s4, s4, #0x400 +sltiu s4, s4, #0x7ff +sltiu s4, s9, #0xfffff801 +sltiu s4, s9, #0xfffffc00 +sltiu s4, s9, #0xfffffe00 +sltiu s4, s9, #0xffffff00 +sltiu s4, s9, #0xffffff80 +sltiu s4, s9, #0xffffffc0 +sltiu s4, s9, #0xffffffe0 +sltiu s4, s9, #0xfffffff0 +sltiu s4, s9, #0xfffffff8 +sltiu s4, s9, #0xfffffffc +sltiu s4, s9, #0xfffffffe +sltiu s4, s9, #0xffffffff +sltiu s4, s9, #0 +sltiu s4, s9, #1 +sltiu s4, s9, #2 +sltiu s4, s9, #4 +sltiu s4, s9, #8 +sltiu s4, s9, #0x10 +sltiu s4, s9, #0x20 +sltiu s4, s9, #0x40 +sltiu s4, s9, #0x80 +sltiu s4, s9, #0x100 +sltiu s4, s9, #0x200 +sltiu s4, s9, #0x400 +sltiu s4, s9, #0x7ff +sltiu s4, t6, #0xfffff801 +sltiu s4, t6, #0xfffffc00 +sltiu s4, t6, #0xfffffe00 +sltiu s4, t6, #0xffffff00 +sltiu s4, t6, #0xffffff80 +sltiu s4, t6, #0xffffffc0 +sltiu s4, t6, #0xffffffe0 +sltiu s4, t6, #0xfffffff0 +sltiu s4, t6, #0xfffffff8 +sltiu s4, t6, #0xfffffffc +sltiu s4, t6, #0xfffffffe +sltiu s4, t6, #0xffffffff +sltiu s4, t6, #0 +sltiu s4, t6, #1 +sltiu s4, t6, #2 +sltiu s4, t6, #4 +sltiu s4, t6, #8 +sltiu s4, t6, #0x10 +sltiu s4, t6, #0x20 +sltiu s4, t6, #0x40 +sltiu s4, t6, #0x80 +sltiu s4, t6, #0x100 +sltiu s4, t6, #0x200 +sltiu s4, t6, #0x400 +sltiu s4, t6, #0x7ff +sltiu s9, zero, #0xfffff801 +sltiu s9, zero, #0xfffffc00 +sltiu s9, zero, #0xfffffe00 +sltiu s9, zero, #0xffffff00 +sltiu s9, zero, #0xffffff80 +sltiu s9, zero, #0xffffffc0 +sltiu s9, zero, #0xffffffe0 +sltiu s9, zero, #0xfffffff0 +sltiu s9, zero, #0xfffffff8 +sltiu s9, zero, #0xfffffffc +sltiu s9, zero, #0xfffffffe +sltiu s9, zero, #0xffffffff +sltiu s9, zero, #0 +sltiu s9, zero, #1 +sltiu s9, zero, #2 +sltiu s9, zero, #4 +sltiu s9, zero, #8 +sltiu s9, zero, #0x10 +sltiu s9, zero, #0x20 +sltiu s9, zero, #0x40 +sltiu s9, zero, #0x80 +sltiu s9, zero, #0x100 +sltiu s9, zero, #0x200 +sltiu s9, zero, #0x400 +sltiu s9, zero, #0x7ff +sltiu s9, ra, #0xfffff801 +sltiu s9, ra, #0xfffffc00 +sltiu s9, ra, #0xfffffe00 +sltiu s9, ra, #0xffffff00 +sltiu s9, ra, #0xffffff80 +sltiu s9, ra, #0xffffffc0 +sltiu s9, ra, #0xffffffe0 +sltiu s9, ra, #0xfffffff0 +sltiu s9, ra, #0xfffffff8 +sltiu s9, ra, #0xfffffffc +sltiu s9, ra, #0xfffffffe +sltiu s9, ra, #0xffffffff +sltiu s9, ra, #0 +sltiu s9, ra, #1 +sltiu s9, ra, #2 +sltiu s9, ra, #4 +sltiu s9, ra, #8 +sltiu s9, ra, #0x10 +sltiu s9, ra, #0x20 +sltiu s9, ra, #0x40 +sltiu s9, ra, #0x80 +sltiu s9, ra, #0x100 +sltiu s9, ra, #0x200 +sltiu s9, ra, #0x400 +sltiu s9, ra, #0x7ff +sltiu s9, t0, #0xfffff801 +sltiu s9, t0, #0xfffffc00 +sltiu s9, t0, #0xfffffe00 +sltiu s9, t0, #0xffffff00 +sltiu s9, t0, #0xffffff80 +sltiu s9, t0, #0xffffffc0 +sltiu s9, t0, #0xffffffe0 +sltiu s9, t0, #0xfffffff0 +sltiu s9, t0, #0xfffffff8 +sltiu s9, t0, #0xfffffffc +sltiu s9, t0, #0xfffffffe +sltiu s9, t0, #0xffffffff +sltiu s9, t0, #0 +sltiu s9, t0, #1 +sltiu s9, t0, #2 +sltiu s9, t0, #4 +sltiu s9, t0, #8 +sltiu s9, t0, #0x10 +sltiu s9, t0, #0x20 +sltiu s9, t0, #0x40 +sltiu s9, t0, #0x80 +sltiu s9, t0, #0x100 +sltiu s9, t0, #0x200 +sltiu s9, t0, #0x400 +sltiu s9, t0, #0x7ff +sltiu s9, a0, #0xfffff801 +sltiu s9, a0, #0xfffffc00 +sltiu s9, a0, #0xfffffe00 +sltiu s9, a0, #0xffffff00 +sltiu s9, a0, #0xffffff80 +sltiu s9, a0, #0xffffffc0 +sltiu s9, a0, #0xffffffe0 +sltiu s9, a0, #0xfffffff0 +sltiu s9, a0, #0xfffffff8 +sltiu s9, a0, #0xfffffffc +sltiu s9, a0, #0xfffffffe +sltiu s9, a0, #0xffffffff +sltiu s9, a0, #0 +sltiu s9, a0, #1 +sltiu s9, a0, #2 +sltiu s9, a0, #4 +sltiu s9, a0, #8 +sltiu s9, a0, #0x10 +sltiu s9, a0, #0x20 +sltiu s9, a0, #0x40 +sltiu s9, a0, #0x80 +sltiu s9, a0, #0x100 +sltiu s9, a0, #0x200 +sltiu s9, a0, #0x400 +sltiu s9, a0, #0x7ff +sltiu s9, a5, #0xfffff801 +sltiu s9, a5, #0xfffffc00 +sltiu s9, a5, #0xfffffe00 +sltiu s9, a5, #0xffffff00 +sltiu s9, a5, #0xffffff80 +sltiu s9, a5, #0xffffffc0 +sltiu s9, a5, #0xffffffe0 +sltiu s9, a5, #0xfffffff0 +sltiu s9, a5, #0xfffffff8 +sltiu s9, a5, #0xfffffffc +sltiu s9, a5, #0xfffffffe +sltiu s9, a5, #0xffffffff +sltiu s9, a5, #0 +sltiu s9, a5, #1 +sltiu s9, a5, #2 +sltiu s9, a5, #4 +sltiu s9, a5, #8 +sltiu s9, a5, #0x10 +sltiu s9, a5, #0x20 +sltiu s9, a5, #0x40 +sltiu s9, a5, #0x80 +sltiu s9, a5, #0x100 +sltiu s9, a5, #0x200 +sltiu s9, a5, #0x400 +sltiu s9, a5, #0x7ff +sltiu s9, s4, #0xfffff801 +sltiu s9, s4, #0xfffffc00 +sltiu s9, s4, #0xfffffe00 +sltiu s9, s4, #0xffffff00 +sltiu s9, s4, #0xffffff80 +sltiu s9, s4, #0xffffffc0 +sltiu s9, s4, #0xffffffe0 +sltiu s9, s4, #0xfffffff0 +sltiu s9, s4, #0xfffffff8 +sltiu s9, s4, #0xfffffffc +sltiu s9, s4, #0xfffffffe +sltiu s9, s4, #0xffffffff +sltiu s9, s4, #0 +sltiu s9, s4, #1 +sltiu s9, s4, #2 +sltiu s9, s4, #4 +sltiu s9, s4, #8 +sltiu s9, s4, #0x10 +sltiu s9, s4, #0x20 +sltiu s9, s4, #0x40 +sltiu s9, s4, #0x80 +sltiu s9, s4, #0x100 +sltiu s9, s4, #0x200 +sltiu s9, s4, #0x400 +sltiu s9, s4, #0x7ff +sltiu s9, s9, #0xfffff801 +sltiu s9, s9, #0xfffffc00 +sltiu s9, s9, #0xfffffe00 +sltiu s9, s9, #0xffffff00 +sltiu s9, s9, #0xffffff80 +sltiu s9, s9, #0xffffffc0 +sltiu s9, s9, #0xffffffe0 +sltiu s9, s9, #0xfffffff0 +sltiu s9, s9, #0xfffffff8 +sltiu s9, s9, #0xfffffffc +sltiu s9, s9, #0xfffffffe +sltiu s9, s9, #0xffffffff +sltiu s9, s9, #0 +sltiu s9, s9, #1 +sltiu s9, s9, #2 +sltiu s9, s9, #4 +sltiu s9, s9, #8 +sltiu s9, s9, #0x10 +sltiu s9, s9, #0x20 +sltiu s9, s9, #0x40 +sltiu s9, s9, #0x80 +sltiu s9, s9, #0x100 +sltiu s9, s9, #0x200 +sltiu s9, s9, #0x400 +sltiu s9, s9, #0x7ff +sltiu s9, t6, #0xfffff801 +sltiu s9, t6, #0xfffffc00 +sltiu s9, t6, #0xfffffe00 +sltiu s9, t6, #0xffffff00 +sltiu s9, t6, #0xffffff80 +sltiu s9, t6, #0xffffffc0 +sltiu s9, t6, #0xffffffe0 +sltiu s9, t6, #0xfffffff0 +sltiu s9, t6, #0xfffffff8 +sltiu s9, t6, #0xfffffffc +sltiu s9, t6, #0xfffffffe +sltiu s9, t6, #0xffffffff +sltiu s9, t6, #0 +sltiu s9, t6, #1 +sltiu s9, t6, #2 +sltiu s9, t6, #4 +sltiu s9, t6, #8 +sltiu s9, t6, #0x10 +sltiu s9, t6, #0x20 +sltiu s9, t6, #0x40 +sltiu s9, t6, #0x80 +sltiu s9, t6, #0x100 +sltiu s9, t6, #0x200 +sltiu s9, t6, #0x400 +sltiu s9, t6, #0x7ff +sltiu t6, zero, #0xfffff801 +sltiu t6, zero, #0xfffffc00 +sltiu t6, zero, #0xfffffe00 +sltiu t6, zero, #0xffffff00 +sltiu t6, zero, #0xffffff80 +sltiu t6, zero, #0xffffffc0 +sltiu t6, zero, #0xffffffe0 +sltiu t6, zero, #0xfffffff0 +sltiu t6, zero, #0xfffffff8 +sltiu t6, zero, #0xfffffffc +sltiu t6, zero, #0xfffffffe +sltiu t6, zero, #0xffffffff +sltiu t6, zero, #0 +sltiu t6, zero, #1 +sltiu t6, zero, #2 +sltiu t6, zero, #4 +sltiu t6, zero, #8 +sltiu t6, zero, #0x10 +sltiu t6, zero, #0x20 +sltiu t6, zero, #0x40 +sltiu t6, zero, #0x80 +sltiu t6, zero, #0x100 +sltiu t6, zero, #0x200 +sltiu t6, zero, #0x400 +sltiu t6, zero, #0x7ff +sltiu t6, ra, #0xfffff801 +sltiu t6, ra, #0xfffffc00 +sltiu t6, ra, #0xfffffe00 +sltiu t6, ra, #0xffffff00 +sltiu t6, ra, #0xffffff80 +sltiu t6, ra, #0xffffffc0 +sltiu t6, ra, #0xffffffe0 +sltiu t6, ra, #0xfffffff0 +sltiu t6, ra, #0xfffffff8 +sltiu t6, ra, #0xfffffffc +sltiu t6, ra, #0xfffffffe +sltiu t6, ra, #0xffffffff +sltiu t6, ra, #0 +sltiu t6, ra, #1 +sltiu t6, ra, #2 +sltiu t6, ra, #4 +sltiu t6, ra, #8 +sltiu t6, ra, #0x10 +sltiu t6, ra, #0x20 +sltiu t6, ra, #0x40 +sltiu t6, ra, #0x80 +sltiu t6, ra, #0x100 +sltiu t6, ra, #0x200 +sltiu t6, ra, #0x400 +sltiu t6, ra, #0x7ff +sltiu t6, t0, #0xfffff801 +sltiu t6, t0, #0xfffffc00 +sltiu t6, t0, #0xfffffe00 +sltiu t6, t0, #0xffffff00 +sltiu t6, t0, #0xffffff80 +sltiu t6, t0, #0xffffffc0 +sltiu t6, t0, #0xffffffe0 +sltiu t6, t0, #0xfffffff0 +sltiu t6, t0, #0xfffffff8 +sltiu t6, t0, #0xfffffffc +sltiu t6, t0, #0xfffffffe +sltiu t6, t0, #0xffffffff +sltiu t6, t0, #0 +sltiu t6, t0, #1 +sltiu t6, t0, #2 +sltiu t6, t0, #4 +sltiu t6, t0, #8 +sltiu t6, t0, #0x10 +sltiu t6, t0, #0x20 +sltiu t6, t0, #0x40 +sltiu t6, t0, #0x80 +sltiu t6, t0, #0x100 +sltiu t6, t0, #0x200 +sltiu t6, t0, #0x400 +sltiu t6, t0, #0x7ff +sltiu t6, a0, #0xfffff801 +sltiu t6, a0, #0xfffffc00 +sltiu t6, a0, #0xfffffe00 +sltiu t6, a0, #0xffffff00 +sltiu t6, a0, #0xffffff80 +sltiu t6, a0, #0xffffffc0 +sltiu t6, a0, #0xffffffe0 +sltiu t6, a0, #0xfffffff0 +sltiu t6, a0, #0xfffffff8 +sltiu t6, a0, #0xfffffffc +sltiu t6, a0, #0xfffffffe +sltiu t6, a0, #0xffffffff +sltiu t6, a0, #0 +sltiu t6, a0, #1 +sltiu t6, a0, #2 +sltiu t6, a0, #4 +sltiu t6, a0, #8 +sltiu t6, a0, #0x10 +sltiu t6, a0, #0x20 +sltiu t6, a0, #0x40 +sltiu t6, a0, #0x80 +sltiu t6, a0, #0x100 +sltiu t6, a0, #0x200 +sltiu t6, a0, #0x400 +sltiu t6, a0, #0x7ff +sltiu t6, a5, #0xfffff801 +sltiu t6, a5, #0xfffffc00 +sltiu t6, a5, #0xfffffe00 +sltiu t6, a5, #0xffffff00 +sltiu t6, a5, #0xffffff80 +sltiu t6, a5, #0xffffffc0 +sltiu t6, a5, #0xffffffe0 +sltiu t6, a5, #0xfffffff0 +sltiu t6, a5, #0xfffffff8 +sltiu t6, a5, #0xfffffffc +sltiu t6, a5, #0xfffffffe +sltiu t6, a5, #0xffffffff +sltiu t6, a5, #0 +sltiu t6, a5, #1 +sltiu t6, a5, #2 +sltiu t6, a5, #4 +sltiu t6, a5, #8 +sltiu t6, a5, #0x10 +sltiu t6, a5, #0x20 +sltiu t6, a5, #0x40 +sltiu t6, a5, #0x80 +sltiu t6, a5, #0x100 +sltiu t6, a5, #0x200 +sltiu t6, a5, #0x400 +sltiu t6, a5, #0x7ff +sltiu t6, s4, #0xfffff801 +sltiu t6, s4, #0xfffffc00 +sltiu t6, s4, #0xfffffe00 +sltiu t6, s4, #0xffffff00 +sltiu t6, s4, #0xffffff80 +sltiu t6, s4, #0xffffffc0 +sltiu t6, s4, #0xffffffe0 +sltiu t6, s4, #0xfffffff0 +sltiu t6, s4, #0xfffffff8 +sltiu t6, s4, #0xfffffffc +sltiu t6, s4, #0xfffffffe +sltiu t6, s4, #0xffffffff +sltiu t6, s4, #0 +sltiu t6, s4, #1 +sltiu t6, s4, #2 +sltiu t6, s4, #4 +sltiu t6, s4, #8 +sltiu t6, s4, #0x10 +sltiu t6, s4, #0x20 +sltiu t6, s4, #0x40 +sltiu t6, s4, #0x80 +sltiu t6, s4, #0x100 +sltiu t6, s4, #0x200 +sltiu t6, s4, #0x400 +sltiu t6, s4, #0x7ff +sltiu t6, s9, #0xfffff801 +sltiu t6, s9, #0xfffffc00 +sltiu t6, s9, #0xfffffe00 +sltiu t6, s9, #0xffffff00 +sltiu t6, s9, #0xffffff80 +sltiu t6, s9, #0xffffffc0 +sltiu t6, s9, #0xffffffe0 +sltiu t6, s9, #0xfffffff0 +sltiu t6, s9, #0xfffffff8 +sltiu t6, s9, #0xfffffffc +sltiu t6, s9, #0xfffffffe +sltiu t6, s9, #0xffffffff +sltiu t6, s9, #0 +sltiu t6, s9, #1 +sltiu t6, s9, #2 +sltiu t6, s9, #4 +sltiu t6, s9, #8 +sltiu t6, s9, #0x10 +sltiu t6, s9, #0x20 +sltiu t6, s9, #0x40 +sltiu t6, s9, #0x80 +sltiu t6, s9, #0x100 +sltiu t6, s9, #0x200 +sltiu t6, s9, #0x400 +sltiu t6, s9, #0x7ff +sltiu t6, t6, #0xfffff801 +sltiu t6, t6, #0xfffffc00 +sltiu t6, t6, #0xfffffe00 +sltiu t6, t6, #0xffffff00 +sltiu t6, t6, #0xffffff80 +sltiu t6, t6, #0xffffffc0 +sltiu t6, t6, #0xffffffe0 +sltiu t6, t6, #0xfffffff0 +sltiu t6, t6, #0xfffffff8 +sltiu t6, t6, #0xfffffffc +sltiu t6, t6, #0xfffffffe +sltiu t6, t6, #0xffffffff +sltiu t6, t6, #0 +sltiu t6, t6, #1 +sltiu t6, t6, #2 +sltiu t6, t6, #4 +sltiu t6, t6, #8 +sltiu t6, t6, #0x10 +sltiu t6, t6, #0x20 +sltiu t6, t6, #0x40 +sltiu t6, t6, #0x80 +sltiu t6, t6, #0x100 +sltiu t6, t6, #0x200 +sltiu t6, t6, #0x400 +sltiu t6, t6, #0x7ff diff --git a/tests/riscv/rv32i/sltu.asm b/tests/riscv/rv32i/sltu.asm new file mode 100644 index 0000000..ce0955f --- /dev/null +++ b/tests/riscv/rv32i/sltu.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +sltu zero, zero, zero +sltu zero, zero, ra +sltu zero, zero, t0 +sltu zero, zero, a0 +sltu zero, zero, a5 +sltu zero, zero, s4 +sltu zero, zero, s9 +sltu zero, zero, t6 +sltu zero, ra, zero +sltu zero, ra, ra +sltu zero, ra, t0 +sltu zero, ra, a0 +sltu zero, ra, a5 +sltu zero, ra, s4 +sltu zero, ra, s9 +sltu zero, ra, t6 +sltu zero, t0, zero +sltu zero, t0, ra +sltu zero, t0, t0 +sltu zero, t0, a0 +sltu zero, t0, a5 +sltu zero, t0, s4 +sltu zero, t0, s9 +sltu zero, t0, t6 +sltu zero, a0, zero +sltu zero, a0, ra +sltu zero, a0, t0 +sltu zero, a0, a0 +sltu zero, a0, a5 +sltu zero, a0, s4 +sltu zero, a0, s9 +sltu zero, a0, t6 +sltu zero, a5, zero +sltu zero, a5, ra +sltu zero, a5, t0 +sltu zero, a5, a0 +sltu zero, a5, a5 +sltu zero, a5, s4 +sltu zero, a5, s9 +sltu zero, a5, t6 +sltu zero, s4, zero +sltu zero, s4, ra +sltu zero, s4, t0 +sltu zero, s4, a0 +sltu zero, s4, a5 +sltu zero, s4, s4 +sltu zero, s4, s9 +sltu zero, s4, t6 +sltu zero, s9, zero +sltu zero, s9, ra +sltu zero, s9, t0 +sltu zero, s9, a0 +sltu zero, s9, a5 +sltu zero, s9, s4 +sltu zero, s9, s9 +sltu zero, s9, t6 +sltu zero, t6, zero +sltu zero, t6, ra +sltu zero, t6, t0 +sltu zero, t6, a0 +sltu zero, t6, a5 +sltu zero, t6, s4 +sltu zero, t6, s9 +sltu zero, t6, t6 +sltu ra, zero, zero +sltu ra, zero, ra +sltu ra, zero, t0 +sltu ra, zero, a0 +sltu ra, zero, a5 +sltu ra, zero, s4 +sltu ra, zero, s9 +sltu ra, zero, t6 +sltu ra, ra, zero +sltu ra, ra, ra +sltu ra, ra, t0 +sltu ra, ra, a0 +sltu ra, ra, a5 +sltu ra, ra, s4 +sltu ra, ra, s9 +sltu ra, ra, t6 +sltu ra, t0, zero +sltu ra, t0, ra +sltu ra, t0, t0 +sltu ra, t0, a0 +sltu ra, t0, a5 +sltu ra, t0, s4 +sltu ra, t0, s9 +sltu ra, t0, t6 +sltu ra, a0, zero +sltu ra, a0, ra +sltu ra, a0, t0 +sltu ra, a0, a0 +sltu ra, a0, a5 +sltu ra, a0, s4 +sltu ra, a0, s9 +sltu ra, a0, t6 +sltu ra, a5, zero +sltu ra, a5, ra +sltu ra, a5, t0 +sltu ra, a5, a0 +sltu ra, a5, a5 +sltu ra, a5, s4 +sltu ra, a5, s9 +sltu ra, a5, t6 +sltu ra, s4, zero +sltu ra, s4, ra +sltu ra, s4, t0 +sltu ra, s4, a0 +sltu ra, s4, a5 +sltu ra, s4, s4 +sltu ra, s4, s9 +sltu ra, s4, t6 +sltu ra, s9, zero +sltu ra, s9, ra +sltu ra, s9, t0 +sltu ra, s9, a0 +sltu ra, s9, a5 +sltu ra, s9, s4 +sltu ra, s9, s9 +sltu ra, s9, t6 +sltu ra, t6, zero +sltu ra, t6, ra +sltu ra, t6, t0 +sltu ra, t6, a0 +sltu ra, t6, a5 +sltu ra, t6, s4 +sltu ra, t6, s9 +sltu ra, t6, t6 +sltu t0, zero, zero +sltu t0, zero, ra +sltu t0, zero, t0 +sltu t0, zero, a0 +sltu t0, zero, a5 +sltu t0, zero, s4 +sltu t0, zero, s9 +sltu t0, zero, t6 +sltu t0, ra, zero +sltu t0, ra, ra +sltu t0, ra, t0 +sltu t0, ra, a0 +sltu t0, ra, a5 +sltu t0, ra, s4 +sltu t0, ra, s9 +sltu t0, ra, t6 +sltu t0, t0, zero +sltu t0, t0, ra +sltu t0, t0, t0 +sltu t0, t0, a0 +sltu t0, t0, a5 +sltu t0, t0, s4 +sltu t0, t0, s9 +sltu t0, t0, t6 +sltu t0, a0, zero +sltu t0, a0, ra +sltu t0, a0, t0 +sltu t0, a0, a0 +sltu t0, a0, a5 +sltu t0, a0, s4 +sltu t0, a0, s9 +sltu t0, a0, t6 +sltu t0, a5, zero +sltu t0, a5, ra +sltu t0, a5, t0 +sltu t0, a5, a0 +sltu t0, a5, a5 +sltu t0, a5, s4 +sltu t0, a5, s9 +sltu t0, a5, t6 +sltu t0, s4, zero +sltu t0, s4, ra +sltu t0, s4, t0 +sltu t0, s4, a0 +sltu t0, s4, a5 +sltu t0, s4, s4 +sltu t0, s4, s9 +sltu t0, s4, t6 +sltu t0, s9, zero +sltu t0, s9, ra +sltu t0, s9, t0 +sltu t0, s9, a0 +sltu t0, s9, a5 +sltu t0, s9, s4 +sltu t0, s9, s9 +sltu t0, s9, t6 +sltu t0, t6, zero +sltu t0, t6, ra +sltu t0, t6, t0 +sltu t0, t6, a0 +sltu t0, t6, a5 +sltu t0, t6, s4 +sltu t0, t6, s9 +sltu t0, t6, t6 +sltu a0, zero, zero +sltu a0, zero, ra +sltu a0, zero, t0 +sltu a0, zero, a0 +sltu a0, zero, a5 +sltu a0, zero, s4 +sltu a0, zero, s9 +sltu a0, zero, t6 +sltu a0, ra, zero +sltu a0, ra, ra +sltu a0, ra, t0 +sltu a0, ra, a0 +sltu a0, ra, a5 +sltu a0, ra, s4 +sltu a0, ra, s9 +sltu a0, ra, t6 +sltu a0, t0, zero +sltu a0, t0, ra +sltu a0, t0, t0 +sltu a0, t0, a0 +sltu a0, t0, a5 +sltu a0, t0, s4 +sltu a0, t0, s9 +sltu a0, t0, t6 +sltu a0, a0, zero +sltu a0, a0, ra +sltu a0, a0, t0 +sltu a0, a0, a0 +sltu a0, a0, a5 +sltu a0, a0, s4 +sltu a0, a0, s9 +sltu a0, a0, t6 +sltu a0, a5, zero +sltu a0, a5, ra +sltu a0, a5, t0 +sltu a0, a5, a0 +sltu a0, a5, a5 +sltu a0, a5, s4 +sltu a0, a5, s9 +sltu a0, a5, t6 +sltu a0, s4, zero +sltu a0, s4, ra +sltu a0, s4, t0 +sltu a0, s4, a0 +sltu a0, s4, a5 +sltu a0, s4, s4 +sltu a0, s4, s9 +sltu a0, s4, t6 +sltu a0, s9, zero +sltu a0, s9, ra +sltu a0, s9, t0 +sltu a0, s9, a0 +sltu a0, s9, a5 +sltu a0, s9, s4 +sltu a0, s9, s9 +sltu a0, s9, t6 +sltu a0, t6, zero +sltu a0, t6, ra +sltu a0, t6, t0 +sltu a0, t6, a0 +sltu a0, t6, a5 +sltu a0, t6, s4 +sltu a0, t6, s9 +sltu a0, t6, t6 +sltu a5, zero, zero +sltu a5, zero, ra +sltu a5, zero, t0 +sltu a5, zero, a0 +sltu a5, zero, a5 +sltu a5, zero, s4 +sltu a5, zero, s9 +sltu a5, zero, t6 +sltu a5, ra, zero +sltu a5, ra, ra +sltu a5, ra, t0 +sltu a5, ra, a0 +sltu a5, ra, a5 +sltu a5, ra, s4 +sltu a5, ra, s9 +sltu a5, ra, t6 +sltu a5, t0, zero +sltu a5, t0, ra +sltu a5, t0, t0 +sltu a5, t0, a0 +sltu a5, t0, a5 +sltu a5, t0, s4 +sltu a5, t0, s9 +sltu a5, t0, t6 +sltu a5, a0, zero +sltu a5, a0, ra +sltu a5, a0, t0 +sltu a5, a0, a0 +sltu a5, a0, a5 +sltu a5, a0, s4 +sltu a5, a0, s9 +sltu a5, a0, t6 +sltu a5, a5, zero +sltu a5, a5, ra +sltu a5, a5, t0 +sltu a5, a5, a0 +sltu a5, a5, a5 +sltu a5, a5, s4 +sltu a5, a5, s9 +sltu a5, a5, t6 +sltu a5, s4, zero +sltu a5, s4, ra +sltu a5, s4, t0 +sltu a5, s4, a0 +sltu a5, s4, a5 +sltu a5, s4, s4 +sltu a5, s4, s9 +sltu a5, s4, t6 +sltu a5, s9, zero +sltu a5, s9, ra +sltu a5, s9, t0 +sltu a5, s9, a0 +sltu a5, s9, a5 +sltu a5, s9, s4 +sltu a5, s9, s9 +sltu a5, s9, t6 +sltu a5, t6, zero +sltu a5, t6, ra +sltu a5, t6, t0 +sltu a5, t6, a0 +sltu a5, t6, a5 +sltu a5, t6, s4 +sltu a5, t6, s9 +sltu a5, t6, t6 +sltu s4, zero, zero +sltu s4, zero, ra +sltu s4, zero, t0 +sltu s4, zero, a0 +sltu s4, zero, a5 +sltu s4, zero, s4 +sltu s4, zero, s9 +sltu s4, zero, t6 +sltu s4, ra, zero +sltu s4, ra, ra +sltu s4, ra, t0 +sltu s4, ra, a0 +sltu s4, ra, a5 +sltu s4, ra, s4 +sltu s4, ra, s9 +sltu s4, ra, t6 +sltu s4, t0, zero +sltu s4, t0, ra +sltu s4, t0, t0 +sltu s4, t0, a0 +sltu s4, t0, a5 +sltu s4, t0, s4 +sltu s4, t0, s9 +sltu s4, t0, t6 +sltu s4, a0, zero +sltu s4, a0, ra +sltu s4, a0, t0 +sltu s4, a0, a0 +sltu s4, a0, a5 +sltu s4, a0, s4 +sltu s4, a0, s9 +sltu s4, a0, t6 +sltu s4, a5, zero +sltu s4, a5, ra +sltu s4, a5, t0 +sltu s4, a5, a0 +sltu s4, a5, a5 +sltu s4, a5, s4 +sltu s4, a5, s9 +sltu s4, a5, t6 +sltu s4, s4, zero +sltu s4, s4, ra +sltu s4, s4, t0 +sltu s4, s4, a0 +sltu s4, s4, a5 +sltu s4, s4, s4 +sltu s4, s4, s9 +sltu s4, s4, t6 +sltu s4, s9, zero +sltu s4, s9, ra +sltu s4, s9, t0 +sltu s4, s9, a0 +sltu s4, s9, a5 +sltu s4, s9, s4 +sltu s4, s9, s9 +sltu s4, s9, t6 +sltu s4, t6, zero +sltu s4, t6, ra +sltu s4, t6, t0 +sltu s4, t6, a0 +sltu s4, t6, a5 +sltu s4, t6, s4 +sltu s4, t6, s9 +sltu s4, t6, t6 +sltu s9, zero, zero +sltu s9, zero, ra +sltu s9, zero, t0 +sltu s9, zero, a0 +sltu s9, zero, a5 +sltu s9, zero, s4 +sltu s9, zero, s9 +sltu s9, zero, t6 +sltu s9, ra, zero +sltu s9, ra, ra +sltu s9, ra, t0 +sltu s9, ra, a0 +sltu s9, ra, a5 +sltu s9, ra, s4 +sltu s9, ra, s9 +sltu s9, ra, t6 +sltu s9, t0, zero +sltu s9, t0, ra +sltu s9, t0, t0 +sltu s9, t0, a0 +sltu s9, t0, a5 +sltu s9, t0, s4 +sltu s9, t0, s9 +sltu s9, t0, t6 +sltu s9, a0, zero +sltu s9, a0, ra +sltu s9, a0, t0 +sltu s9, a0, a0 +sltu s9, a0, a5 +sltu s9, a0, s4 +sltu s9, a0, s9 +sltu s9, a0, t6 +sltu s9, a5, zero +sltu s9, a5, ra +sltu s9, a5, t0 +sltu s9, a5, a0 +sltu s9, a5, a5 +sltu s9, a5, s4 +sltu s9, a5, s9 +sltu s9, a5, t6 +sltu s9, s4, zero +sltu s9, s4, ra +sltu s9, s4, t0 +sltu s9, s4, a0 +sltu s9, s4, a5 +sltu s9, s4, s4 +sltu s9, s4, s9 +sltu s9, s4, t6 +sltu s9, s9, zero +sltu s9, s9, ra +sltu s9, s9, t0 +sltu s9, s9, a0 +sltu s9, s9, a5 +sltu s9, s9, s4 +sltu s9, s9, s9 +sltu s9, s9, t6 +sltu s9, t6, zero +sltu s9, t6, ra +sltu s9, t6, t0 +sltu s9, t6, a0 +sltu s9, t6, a5 +sltu s9, t6, s4 +sltu s9, t6, s9 +sltu s9, t6, t6 +sltu t6, zero, zero +sltu t6, zero, ra +sltu t6, zero, t0 +sltu t6, zero, a0 +sltu t6, zero, a5 +sltu t6, zero, s4 +sltu t6, zero, s9 +sltu t6, zero, t6 +sltu t6, ra, zero +sltu t6, ra, ra +sltu t6, ra, t0 +sltu t6, ra, a0 +sltu t6, ra, a5 +sltu t6, ra, s4 +sltu t6, ra, s9 +sltu t6, ra, t6 +sltu t6, t0, zero +sltu t6, t0, ra +sltu t6, t0, t0 +sltu t6, t0, a0 +sltu t6, t0, a5 +sltu t6, t0, s4 +sltu t6, t0, s9 +sltu t6, t0, t6 +sltu t6, a0, zero +sltu t6, a0, ra +sltu t6, a0, t0 +sltu t6, a0, a0 +sltu t6, a0, a5 +sltu t6, a0, s4 +sltu t6, a0, s9 +sltu t6, a0, t6 +sltu t6, a5, zero +sltu t6, a5, ra +sltu t6, a5, t0 +sltu t6, a5, a0 +sltu t6, a5, a5 +sltu t6, a5, s4 +sltu t6, a5, s9 +sltu t6, a5, t6 +sltu t6, s4, zero +sltu t6, s4, ra +sltu t6, s4, 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ra, a5 +sra s9, ra, s4 +sra s9, ra, s9 +sra s9, ra, t6 +sra s9, t0, zero +sra s9, t0, ra +sra s9, t0, t0 +sra s9, t0, a0 +sra s9, t0, a5 +sra s9, t0, s4 +sra s9, t0, s9 +sra s9, t0, t6 +sra s9, a0, zero +sra s9, a0, ra +sra s9, a0, t0 +sra s9, a0, a0 +sra s9, a0, a5 +sra s9, a0, s4 +sra s9, a0, s9 +sra s9, a0, t6 +sra s9, a5, zero +sra s9, a5, ra +sra s9, a5, t0 +sra s9, a5, a0 +sra s9, a5, a5 +sra s9, a5, s4 +sra s9, a5, s9 +sra s9, a5, t6 +sra s9, s4, zero +sra s9, s4, ra +sra s9, s4, t0 +sra s9, s4, a0 +sra s9, s4, a5 +sra s9, s4, s4 +sra s9, s4, s9 +sra s9, s4, t6 +sra s9, s9, zero +sra s9, s9, ra +sra s9, s9, t0 +sra s9, s9, a0 +sra s9, s9, a5 +sra s9, s9, s4 +sra s9, s9, s9 +sra s9, s9, t6 +sra s9, t6, zero +sra s9, t6, ra +sra s9, t6, t0 +sra s9, t6, a0 +sra s9, t6, a5 +sra s9, t6, s4 +sra s9, t6, s9 +sra s9, t6, t6 +sra t6, zero, zero +sra t6, zero, ra +sra t6, zero, t0 +sra t6, zero, a0 +sra t6, zero, a5 +sra t6, zero, s4 +sra t6, zero, s9 +sra t6, zero, t6 +sra t6, ra, zero +sra t6, ra, ra +sra t6, ra, t0 +sra t6, ra, a0 +sra t6, ra, a5 +sra t6, ra, s4 +sra t6, ra, s9 +sra t6, ra, t6 +sra t6, t0, zero +sra t6, t0, ra +sra t6, t0, t0 +sra t6, t0, a0 +sra t6, t0, a5 +sra t6, t0, s4 +sra t6, t0, s9 +sra t6, t0, t6 +sra t6, a0, zero +sra t6, a0, ra +sra t6, a0, t0 +sra t6, a0, a0 +sra t6, a0, a5 +sra t6, a0, s4 +sra t6, a0, s9 +sra t6, a0, t6 +sra t6, a5, zero +sra t6, a5, ra +sra t6, a5, t0 +sra t6, a5, a0 +sra t6, a5, a5 +sra t6, a5, s4 +sra t6, a5, s9 +sra t6, a5, t6 +sra t6, s4, zero +sra t6, s4, ra +sra t6, s4, t0 +sra t6, s4, a0 +sra t6, s4, a5 +sra t6, s4, s4 +sra t6, s4, s9 +sra t6, s4, t6 +sra t6, s9, zero +sra t6, s9, ra +sra t6, s9, t0 +sra t6, s9, a0 +sra t6, s9, a5 +sra t6, s9, s4 +sra t6, s9, s9 +sra t6, s9, t6 +sra t6, t6, zero +sra t6, t6, ra +sra t6, t6, t0 +sra t6, t6, a0 +sra t6, t6, a5 +sra t6, t6, s4 +sra t6, t6, s9 +sra t6, t6, t6 diff --git a/tests/riscv/rv32i/srai.asm b/tests/riscv/rv32i/srai.asm new file mode 100644 index 0000000..4478b36 --- /dev/null +++ b/tests/riscv/rv32i/srai.asm @@ -0,0 +1,452 @@ +.lang riscv32 +.org 0x0 + +srai zero, zero, #0 +srai zero, zero, #1 +srai zero, zero, #2 +srai zero, zero, #4 +srai zero, zero, #8 +srai zero, zero, #16 +srai zero, zero, #31 +srai zero, ra, #0 +srai zero, ra, #1 +srai zero, ra, #2 +srai zero, ra, #4 +srai zero, ra, #8 +srai zero, ra, #16 +srai zero, ra, #31 +srai zero, t0, #0 +srai zero, t0, #1 +srai zero, t0, #2 +srai zero, t0, #4 +srai zero, t0, #8 +srai zero, t0, #16 +srai zero, t0, #31 +srai zero, a0, #0 +srai zero, a0, #1 +srai zero, a0, #2 +srai zero, a0, #4 +srai zero, a0, #8 +srai zero, a0, #16 +srai zero, a0, #31 +srai zero, a5, #0 +srai zero, a5, #1 +srai zero, a5, #2 +srai zero, a5, #4 +srai zero, a5, #8 +srai zero, a5, #16 +srai zero, a5, #31 +srai zero, s4, #0 +srai zero, s4, #1 +srai zero, s4, #2 +srai zero, s4, #4 +srai zero, s4, #8 +srai zero, s4, #16 +srai zero, s4, #31 +srai zero, s9, #0 +srai zero, s9, #1 +srai zero, s9, #2 +srai zero, s9, #4 +srai zero, s9, #8 +srai zero, s9, #16 +srai zero, s9, #31 +srai zero, t6, #0 +srai zero, t6, #1 +srai zero, t6, #2 +srai zero, t6, #4 +srai zero, t6, #8 +srai zero, t6, #16 +srai zero, t6, #31 +srai ra, zero, #0 +srai ra, zero, #1 +srai ra, zero, #2 +srai ra, zero, #4 +srai ra, zero, #8 +srai ra, zero, #16 +srai ra, zero, #31 +srai ra, ra, #0 +srai ra, ra, #1 +srai ra, ra, #2 +srai ra, ra, #4 +srai ra, ra, #8 +srai ra, ra, #16 +srai ra, ra, #31 +srai ra, t0, #0 +srai ra, t0, #1 +srai ra, t0, #2 +srai ra, t0, #4 +srai ra, t0, #8 +srai ra, t0, #16 +srai ra, t0, #31 +srai ra, a0, #0 +srai ra, a0, #1 +srai ra, a0, #2 +srai ra, a0, #4 +srai ra, a0, #8 +srai ra, a0, #16 +srai ra, a0, #31 +srai ra, a5, #0 +srai ra, a5, #1 +srai ra, a5, #2 +srai ra, a5, #4 +srai ra, a5, #8 +srai ra, a5, #16 +srai ra, a5, #31 +srai ra, s4, #0 +srai ra, s4, #1 +srai ra, s4, #2 +srai ra, s4, #4 +srai ra, s4, #8 +srai ra, s4, #16 +srai ra, s4, #31 +srai ra, s9, #0 +srai ra, s9, #1 +srai ra, s9, #2 +srai ra, s9, #4 +srai ra, s9, #8 +srai ra, s9, #16 +srai ra, s9, #31 +srai ra, t6, #0 +srai ra, t6, #1 +srai ra, t6, #2 +srai ra, t6, #4 +srai ra, t6, #8 +srai ra, t6, #16 +srai ra, t6, #31 +srai t0, zero, #0 +srai t0, zero, #1 +srai t0, zero, #2 +srai t0, zero, #4 +srai t0, zero, #8 +srai t0, zero, #16 +srai t0, zero, #31 +srai t0, ra, #0 +srai t0, ra, #1 +srai t0, ra, #2 +srai t0, ra, #4 +srai t0, ra, #8 +srai t0, ra, #16 +srai t0, ra, #31 +srai t0, t0, #0 +srai t0, t0, #1 +srai t0, t0, #2 +srai t0, t0, #4 +srai t0, t0, #8 +srai t0, t0, #16 +srai t0, t0, #31 +srai t0, a0, #0 +srai t0, a0, #1 +srai t0, a0, #2 +srai t0, a0, #4 +srai t0, a0, #8 +srai t0, a0, #16 +srai t0, a0, #31 +srai t0, a5, #0 +srai t0, a5, #1 +srai t0, a5, #2 +srai t0, a5, #4 +srai t0, a5, #8 +srai t0, a5, #16 +srai t0, a5, #31 +srai t0, s4, #0 +srai t0, s4, #1 +srai t0, s4, #2 +srai t0, s4, #4 +srai t0, s4, #8 +srai t0, s4, #16 +srai t0, s4, #31 +srai t0, s9, #0 +srai t0, s9, #1 +srai t0, s9, #2 +srai t0, s9, #4 +srai t0, s9, #8 +srai t0, s9, #16 +srai t0, s9, #31 +srai t0, t6, #0 +srai t0, t6, #1 +srai t0, t6, #2 +srai t0, t6, #4 +srai t0, t6, #8 +srai t0, t6, #16 +srai t0, t6, #31 +srai a0, zero, #0 +srai a0, zero, #1 +srai a0, zero, #2 +srai a0, zero, #4 +srai a0, zero, #8 +srai a0, zero, #16 +srai a0, zero, #31 +srai a0, ra, #0 +srai a0, ra, #1 +srai a0, ra, #2 +srai a0, ra, #4 +srai a0, ra, #8 +srai a0, ra, #16 +srai a0, ra, #31 +srai a0, t0, #0 +srai a0, t0, #1 +srai a0, t0, #2 +srai a0, t0, #4 +srai a0, t0, #8 +srai a0, t0, #16 +srai a0, t0, #31 +srai a0, a0, #0 +srai a0, a0, #1 +srai a0, a0, #2 +srai a0, a0, #4 +srai a0, a0, #8 +srai a0, a0, #16 +srai a0, a0, #31 +srai a0, a5, #0 +srai a0, a5, #1 +srai a0, a5, #2 +srai a0, a5, #4 +srai a0, a5, #8 +srai a0, a5, #16 +srai a0, a5, #31 +srai a0, s4, #0 +srai a0, s4, #1 +srai a0, s4, #2 +srai a0, s4, #4 +srai a0, s4, #8 +srai a0, s4, #16 +srai a0, s4, #31 +srai a0, s9, #0 +srai a0, s9, #1 +srai a0, s9, #2 +srai a0, s9, #4 +srai a0, s9, #8 +srai a0, s9, #16 +srai a0, s9, #31 +srai a0, t6, #0 +srai a0, t6, #1 +srai a0, t6, #2 +srai a0, t6, #4 +srai a0, t6, #8 +srai a0, t6, #16 +srai a0, t6, #31 +srai a5, zero, #0 +srai a5, zero, #1 +srai a5, zero, #2 +srai a5, zero, #4 +srai a5, zero, #8 +srai a5, zero, #16 +srai a5, zero, #31 +srai a5, ra, #0 +srai a5, ra, #1 +srai a5, ra, #2 +srai a5, ra, #4 +srai a5, ra, #8 +srai a5, ra, #16 +srai a5, ra, #31 +srai a5, t0, #0 +srai a5, t0, #1 +srai a5, t0, #2 +srai a5, t0, #4 +srai a5, t0, #8 +srai a5, t0, #16 +srai a5, t0, #31 +srai a5, a0, #0 +srai a5, a0, #1 +srai a5, a0, #2 +srai a5, a0, #4 +srai a5, a0, #8 +srai a5, a0, #16 +srai a5, a0, #31 +srai a5, a5, #0 +srai a5, a5, #1 +srai a5, a5, #2 +srai a5, a5, #4 +srai a5, a5, #8 +srai a5, a5, #16 +srai a5, a5, #31 +srai a5, s4, #0 +srai a5, s4, #1 +srai a5, s4, #2 +srai a5, s4, #4 +srai a5, s4, #8 +srai a5, s4, #16 +srai a5, s4, #31 +srai a5, s9, #0 +srai a5, s9, #1 +srai a5, s9, #2 +srai a5, s9, #4 +srai a5, s9, #8 +srai a5, s9, #16 +srai a5, s9, #31 +srai a5, t6, #0 +srai a5, t6, #1 +srai a5, t6, #2 +srai a5, t6, #4 +srai a5, t6, #8 +srai a5, t6, #16 +srai a5, t6, #31 +srai s4, zero, #0 +srai s4, zero, #1 +srai s4, zero, #2 +srai s4, zero, #4 +srai s4, zero, #8 +srai s4, zero, #16 +srai s4, zero, #31 +srai s4, ra, #0 +srai s4, ra, #1 +srai s4, ra, #2 +srai s4, ra, #4 +srai s4, ra, #8 +srai s4, ra, #16 +srai s4, ra, #31 +srai s4, t0, #0 +srai s4, t0, #1 +srai s4, t0, #2 +srai s4, t0, #4 +srai s4, t0, #8 +srai s4, t0, #16 +srai s4, t0, #31 +srai s4, a0, #0 +srai s4, a0, #1 +srai s4, a0, #2 +srai s4, a0, #4 +srai s4, a0, #8 +srai s4, a0, #16 +srai s4, a0, #31 +srai s4, a5, #0 +srai s4, a5, #1 +srai s4, a5, #2 +srai s4, a5, #4 +srai s4, a5, #8 +srai s4, a5, #16 +srai s4, a5, #31 +srai s4, s4, #0 +srai s4, s4, #1 +srai s4, s4, #2 +srai s4, s4, #4 +srai s4, s4, #8 +srai s4, s4, #16 +srai s4, s4, #31 +srai s4, s9, #0 +srai s4, s9, #1 +srai s4, s9, #2 +srai s4, s9, #4 +srai s4, s9, #8 +srai s4, s9, #16 +srai s4, s9, #31 +srai s4, t6, #0 +srai s4, t6, #1 +srai s4, t6, #2 +srai s4, t6, #4 +srai s4, t6, #8 +srai s4, t6, #16 +srai s4, t6, #31 +srai s9, zero, #0 +srai s9, zero, #1 +srai s9, zero, #2 +srai s9, zero, #4 +srai s9, zero, #8 +srai s9, zero, #16 +srai s9, zero, #31 +srai s9, ra, #0 +srai s9, ra, #1 +srai s9, ra, #2 +srai s9, ra, #4 +srai s9, ra, #8 +srai s9, ra, #16 +srai s9, ra, #31 +srai s9, t0, #0 +srai s9, t0, #1 +srai s9, t0, #2 +srai s9, t0, #4 +srai s9, t0, #8 +srai s9, t0, #16 +srai s9, t0, #31 +srai s9, a0, #0 +srai s9, a0, #1 +srai s9, a0, #2 +srai s9, a0, #4 +srai s9, a0, #8 +srai s9, a0, #16 +srai s9, a0, #31 +srai s9, a5, #0 +srai s9, a5, #1 +srai s9, a5, #2 +srai s9, a5, #4 +srai s9, a5, #8 +srai s9, a5, #16 +srai s9, a5, #31 +srai s9, s4, #0 +srai s9, s4, #1 +srai s9, s4, #2 +srai s9, s4, #4 +srai s9, s4, #8 +srai s9, s4, #16 +srai s9, s4, #31 +srai s9, s9, #0 +srai s9, s9, #1 +srai s9, s9, #2 +srai s9, s9, #4 +srai s9, s9, #8 +srai s9, s9, #16 +srai s9, s9, #31 +srai s9, t6, #0 +srai s9, t6, #1 +srai s9, t6, #2 +srai s9, t6, #4 +srai s9, t6, #8 +srai s9, t6, #16 +srai s9, t6, #31 +srai t6, zero, #0 +srai t6, zero, #1 +srai t6, zero, #2 +srai t6, zero, #4 +srai t6, zero, #8 +srai t6, zero, #16 +srai t6, zero, #31 +srai t6, ra, #0 +srai t6, ra, #1 +srai t6, ra, #2 +srai t6, ra, #4 +srai t6, ra, #8 +srai t6, ra, #16 +srai t6, ra, #31 +srai t6, t0, #0 +srai t6, t0, #1 +srai t6, t0, #2 +srai t6, t0, #4 +srai t6, t0, #8 +srai t6, t0, #16 +srai t6, t0, #31 +srai t6, a0, #0 +srai t6, a0, #1 +srai t6, a0, #2 +srai t6, a0, #4 +srai t6, a0, #8 +srai t6, a0, #16 +srai t6, a0, #31 +srai t6, a5, #0 +srai t6, a5, #1 +srai t6, a5, #2 +srai t6, a5, #4 +srai t6, a5, #8 +srai t6, a5, #16 +srai t6, a5, #31 +srai t6, s4, #0 +srai t6, s4, #1 +srai t6, s4, #2 +srai t6, s4, #4 +srai t6, s4, #8 +srai t6, s4, #16 +srai t6, s4, #31 +srai t6, s9, #0 +srai t6, s9, #1 +srai t6, s9, #2 +srai t6, s9, #4 +srai t6, s9, #8 +srai t6, s9, #16 +srai t6, s9, #31 +srai t6, t6, #0 +srai t6, t6, #1 +srai t6, t6, #2 +srai t6, t6, #4 +srai t6, t6, #8 +srai t6, t6, #16 +srai t6, t6, #31 + diff --git a/tests/riscv/rv32i/srai.bin b/tests/riscv/rv32i/srai.bin new file mode 100644 index 0000000000000000000000000000000000000000..220b8384178e42927f2c7b5a1eaca9478a849fe8 GIT binary patch literal 1792 zcmWmCafg*n9LDi1Ygx-aT8TuDNF;g-ok%2F!?+p4yp=~J68&+%v11s+80IY`5{Z32 z=Z}lq@0xS?`d&A;_g>%J{v-d&Yxz&^9d2%a9Bz)fqwc6X>W;dj?s)3XeBYO+@`$G79#@wvJGIPCa#d^^4!-;U4C{nVZLzAsPZjeL?b z_n&@y?mr&LGkGhY<=p+3{=&P5@?74@7rAi%t-ti{k-U)i@>MR~|LCv0dn_;IgM5=K z_rG%O`-!}gkMdov-SGts0YktLFa!(%L%>jVRabRYS9MiaPaVFBui~rtD!z)Z;tTi! zzJM>_3-|)QfUn}K_$t1Nui~rtD!za(;0yQyzJM>_3-~I&im&3U_$t1Nui~rtD!z)Z z;;Z;7zIu1Ki8dH*Fxp_W!Dxfg2BQr&UDGvP(=}bwwNq!G%|4rbHv4S$+3d5~XSB~~ zpV2;}eMb9?_8IN7*=MuQW}nSIn|(I>Z1x%LGumgg&uE{~KBIj``)u~v?6cWtv(ILq z%|4rbHv4S$+3d5~XS2^{pN+qbqm84Dqm84Dqm84Dqps_^uIsw4>$-mG`0M<2{yKl1 zzs_IhZ{u&{Z{u&{Z{u&{Z{x4?*ZJ%Gb^bbkoxjfC#^1)@#^1)@#^1)@#$V^J^Vj+7 z{B{01f1SV1U+1s$*ZJ%Gb^bbkiKE0(;wW*HI7%EPj)rdNhHmJFZs^9T<8Sac_#6BU z{sw=8zrZWe$rf%w{Zk{^+CV!K^$=~E} z@;CX*{AKRQcf}vn27?y77mTu{mZt2#k!?*A)d<);gx9}}| z1z*8e@D+RoU%^-KEqn{#!ng1(d<);gSMU{l1z*8e@D+Ro-@>=>Eqn{#!ng1(d<);g Px9}}|3*W-G?hgM0N~FXu literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/srai.disasm b/tests/riscv/rv32i/srai.disasm new file mode 100644 index 0000000..5607405 --- /dev/null +++ b/tests/riscv/rv32i/srai.disasm @@ -0,0 +1,448 @@ +srai zero, zero, #0 +srai zero, zero, #1 +srai zero, zero, #2 +srai zero, zero, #4 +srai zero, zero, #8 +srai zero, zero, #16 +srai zero, zero, #31 +srai zero, ra, #0 +srai zero, ra, #1 +srai zero, ra, #2 +srai zero, ra, #4 +srai zero, ra, #8 +srai zero, ra, #16 +srai zero, ra, #31 +srai zero, t0, #0 +srai zero, t0, #1 +srai zero, t0, #2 +srai zero, t0, #4 +srai zero, t0, #8 +srai zero, t0, #16 +srai zero, t0, #31 +srai zero, a0, #0 +srai zero, a0, #1 +srai zero, a0, #2 +srai zero, a0, #4 +srai zero, a0, #8 +srai zero, a0, #16 +srai zero, a0, #31 +srai zero, a5, #0 +srai zero, a5, #1 +srai zero, a5, #2 +srai zero, a5, #4 +srai zero, a5, #8 +srai zero, a5, #16 +srai zero, a5, #31 +srai zero, s4, #0 +srai zero, s4, #1 +srai zero, s4, #2 +srai zero, s4, #4 +srai zero, s4, #8 +srai zero, s4, #16 +srai zero, s4, #31 +srai zero, s9, #0 +srai zero, s9, #1 +srai zero, s9, #2 +srai zero, s9, #4 +srai zero, s9, #8 +srai zero, s9, #16 +srai zero, s9, #31 +srai zero, t6, #0 +srai zero, t6, #1 +srai zero, t6, #2 +srai zero, t6, #4 +srai zero, t6, #8 +srai zero, t6, #16 +srai zero, t6, #31 +srai ra, zero, #0 +srai ra, zero, #1 +srai ra, zero, #2 +srai ra, zero, #4 +srai ra, zero, #8 +srai ra, zero, #16 +srai ra, zero, #31 +srai ra, ra, #0 +srai ra, ra, #1 +srai ra, ra, #2 +srai ra, ra, #4 +srai ra, ra, #8 +srai ra, ra, #16 +srai ra, ra, #31 +srai ra, t0, #0 +srai ra, t0, #1 +srai ra, t0, #2 +srai ra, t0, #4 +srai ra, t0, #8 +srai ra, t0, #16 +srai ra, t0, #31 +srai ra, a0, #0 +srai ra, a0, #1 +srai ra, a0, #2 +srai ra, a0, #4 +srai ra, a0, #8 +srai ra, a0, #16 +srai ra, a0, #31 +srai ra, a5, #0 +srai ra, a5, #1 +srai ra, a5, #2 +srai ra, a5, #4 +srai ra, a5, #8 +srai ra, a5, #16 +srai ra, a5, #31 +srai ra, s4, #0 +srai ra, s4, #1 +srai ra, s4, #2 +srai ra, s4, #4 +srai ra, s4, #8 +srai ra, s4, #16 +srai ra, s4, #31 +srai ra, s9, #0 +srai ra, s9, #1 +srai ra, s9, #2 +srai ra, s9, #4 +srai ra, s9, #8 +srai ra, s9, #16 +srai ra, s9, #31 +srai ra, t6, #0 +srai ra, t6, #1 +srai ra, t6, #2 +srai ra, t6, #4 +srai ra, t6, #8 +srai ra, t6, #16 +srai ra, t6, #31 +srai t0, zero, #0 +srai t0, zero, #1 +srai t0, zero, #2 +srai t0, zero, #4 +srai t0, zero, #8 +srai t0, zero, #16 +srai t0, zero, #31 +srai t0, ra, #0 +srai t0, ra, #1 +srai t0, ra, #2 +srai t0, ra, #4 +srai t0, ra, #8 +srai t0, ra, #16 +srai t0, ra, #31 +srai t0, t0, #0 +srai t0, t0, #1 +srai t0, t0, #2 +srai t0, t0, #4 +srai t0, t0, #8 +srai t0, t0, #16 +srai t0, t0, #31 +srai t0, a0, #0 +srai t0, a0, #1 +srai t0, a0, #2 +srai t0, a0, #4 +srai t0, a0, #8 +srai t0, a0, #16 +srai t0, a0, #31 +srai t0, a5, #0 +srai t0, a5, #1 +srai t0, a5, #2 +srai t0, a5, #4 +srai t0, a5, #8 +srai t0, a5, #16 +srai t0, a5, #31 +srai t0, s4, #0 +srai t0, s4, #1 +srai t0, s4, #2 +srai t0, s4, #4 +srai t0, s4, #8 +srai t0, s4, #16 +srai t0, s4, #31 +srai t0, s9, #0 +srai t0, s9, #1 +srai t0, s9, #2 +srai t0, s9, #4 +srai t0, s9, #8 +srai t0, s9, #16 +srai t0, s9, #31 +srai t0, t6, #0 +srai t0, t6, #1 +srai t0, t6, #2 +srai t0, t6, #4 +srai t0, t6, #8 +srai t0, t6, #16 +srai t0, t6, #31 +srai a0, zero, #0 +srai a0, zero, #1 +srai a0, zero, #2 +srai a0, zero, #4 +srai a0, zero, #8 +srai a0, zero, #16 +srai a0, zero, #31 +srai a0, ra, #0 +srai a0, ra, #1 +srai a0, ra, #2 +srai a0, ra, #4 +srai a0, ra, #8 +srai a0, ra, #16 +srai a0, ra, #31 +srai a0, t0, #0 +srai a0, t0, #1 +srai a0, t0, #2 +srai a0, t0, #4 +srai a0, t0, #8 +srai a0, t0, #16 +srai a0, t0, #31 +srai a0, a0, #0 +srai a0, a0, #1 +srai a0, a0, #2 +srai a0, a0, #4 +srai a0, a0, #8 +srai a0, a0, #16 +srai a0, a0, #31 +srai a0, a5, #0 +srai a0, a5, #1 +srai a0, a5, #2 +srai a0, a5, #4 +srai a0, a5, #8 +srai a0, a5, #16 +srai a0, a5, #31 +srai a0, s4, #0 +srai a0, s4, #1 +srai a0, s4, #2 +srai a0, s4, #4 +srai a0, s4, #8 +srai a0, s4, #16 +srai a0, s4, #31 +srai a0, s9, #0 +srai a0, s9, #1 +srai a0, s9, #2 +srai a0, s9, #4 +srai a0, s9, #8 +srai a0, s9, #16 +srai a0, s9, #31 +srai a0, t6, #0 +srai a0, t6, #1 +srai a0, t6, #2 +srai a0, t6, #4 +srai a0, t6, #8 +srai a0, t6, #16 +srai a0, t6, #31 +srai a5, zero, #0 +srai a5, zero, #1 +srai a5, zero, #2 +srai a5, zero, #4 +srai a5, zero, #8 +srai a5, zero, #16 +srai a5, zero, #31 +srai a5, ra, #0 +srai a5, ra, #1 +srai a5, ra, #2 +srai a5, ra, #4 +srai a5, ra, #8 +srai a5, ra, #16 +srai a5, ra, #31 +srai a5, t0, #0 +srai a5, t0, #1 +srai a5, t0, #2 +srai a5, t0, #4 +srai a5, t0, #8 +srai a5, t0, #16 +srai a5, t0, #31 +srai a5, a0, #0 +srai a5, a0, #1 +srai a5, a0, #2 +srai a5, a0, #4 +srai a5, a0, #8 +srai a5, a0, #16 +srai a5, a0, #31 +srai a5, a5, #0 +srai a5, a5, #1 +srai a5, a5, #2 +srai a5, a5, #4 +srai a5, a5, #8 +srai a5, a5, #16 +srai a5, a5, #31 +srai a5, s4, #0 +srai a5, s4, #1 +srai a5, s4, #2 +srai a5, s4, #4 +srai a5, s4, #8 +srai a5, s4, #16 +srai a5, s4, #31 +srai a5, s9, #0 +srai a5, s9, #1 +srai a5, s9, #2 +srai a5, s9, #4 +srai a5, s9, #8 +srai a5, s9, #16 +srai a5, s9, #31 +srai a5, t6, #0 +srai a5, t6, #1 +srai a5, t6, #2 +srai a5, t6, #4 +srai a5, t6, #8 +srai a5, t6, #16 +srai a5, t6, #31 +srai s4, zero, #0 +srai s4, zero, #1 +srai s4, zero, #2 +srai s4, zero, #4 +srai s4, zero, #8 +srai s4, zero, #16 +srai s4, zero, #31 +srai s4, ra, #0 +srai s4, ra, #1 +srai s4, ra, #2 +srai s4, ra, #4 +srai s4, ra, #8 +srai s4, ra, #16 +srai s4, ra, #31 +srai s4, t0, #0 +srai s4, t0, #1 +srai s4, t0, #2 +srai s4, t0, #4 +srai s4, t0, #8 +srai s4, t0, #16 +srai s4, t0, #31 +srai s4, a0, #0 +srai s4, a0, #1 +srai s4, a0, #2 +srai s4, a0, #4 +srai s4, a0, #8 +srai s4, a0, #16 +srai s4, a0, #31 +srai s4, a5, #0 +srai s4, a5, #1 +srai s4, a5, #2 +srai s4, a5, #4 +srai s4, a5, #8 +srai s4, a5, #16 +srai s4, a5, #31 +srai s4, s4, #0 +srai s4, s4, #1 +srai s4, s4, #2 +srai s4, s4, #4 +srai s4, s4, #8 +srai s4, s4, #16 +srai s4, s4, #31 +srai s4, s9, #0 +srai s4, s9, #1 +srai s4, s9, #2 +srai s4, s9, #4 +srai s4, s9, #8 +srai s4, s9, #16 +srai s4, s9, #31 +srai s4, t6, #0 +srai s4, t6, #1 +srai s4, t6, #2 +srai s4, t6, #4 +srai s4, t6, #8 +srai s4, t6, #16 +srai s4, t6, #31 +srai s9, zero, #0 +srai s9, zero, #1 +srai s9, zero, #2 +srai s9, zero, #4 +srai s9, zero, #8 +srai s9, zero, #16 +srai s9, zero, #31 +srai s9, ra, #0 +srai s9, ra, #1 +srai s9, ra, #2 +srai s9, ra, #4 +srai s9, ra, #8 +srai s9, ra, #16 +srai s9, ra, #31 +srai s9, t0, #0 +srai s9, t0, #1 +srai s9, t0, #2 +srai s9, t0, #4 +srai s9, t0, #8 +srai s9, t0, #16 +srai s9, t0, #31 +srai s9, a0, #0 +srai s9, a0, #1 +srai s9, a0, #2 +srai s9, a0, #4 +srai s9, a0, #8 +srai s9, a0, #16 +srai s9, a0, #31 +srai s9, a5, #0 +srai s9, a5, #1 +srai s9, a5, #2 +srai s9, a5, #4 +srai s9, a5, #8 +srai s9, a5, #16 +srai s9, a5, #31 +srai s9, s4, #0 +srai s9, s4, #1 +srai s9, s4, #2 +srai s9, s4, #4 +srai s9, s4, #8 +srai s9, s4, #16 +srai s9, s4, #31 +srai s9, s9, #0 +srai s9, s9, #1 +srai s9, s9, #2 +srai s9, s9, #4 +srai s9, s9, #8 +srai s9, s9, #16 +srai s9, s9, #31 +srai s9, t6, #0 +srai s9, t6, #1 +srai s9, t6, #2 +srai s9, t6, #4 +srai s9, t6, #8 +srai s9, t6, #16 +srai s9, t6, #31 +srai t6, zero, #0 +srai t6, zero, #1 +srai t6, zero, #2 +srai t6, zero, #4 +srai t6, zero, #8 +srai t6, zero, #16 +srai t6, zero, #31 +srai t6, ra, #0 +srai t6, ra, #1 +srai t6, ra, #2 +srai t6, ra, #4 +srai t6, ra, #8 +srai t6, ra, #16 +srai t6, ra, #31 +srai t6, t0, #0 +srai t6, t0, #1 +srai t6, t0, #2 +srai t6, t0, #4 +srai t6, t0, #8 +srai t6, t0, #16 +srai t6, t0, #31 +srai t6, a0, #0 +srai t6, a0, #1 +srai t6, a0, #2 +srai t6, a0, #4 +srai t6, a0, #8 +srai t6, a0, #16 +srai t6, a0, #31 +srai t6, a5, #0 +srai t6, a5, #1 +srai t6, a5, #2 +srai t6, a5, #4 +srai t6, a5, #8 +srai t6, a5, #16 +srai t6, a5, #31 +srai t6, s4, #0 +srai t6, s4, #1 +srai t6, s4, #2 +srai t6, s4, #4 +srai t6, s4, #8 +srai t6, s4, #16 +srai t6, s4, #31 +srai t6, s9, #0 +srai t6, s9, #1 +srai t6, s9, #2 +srai t6, s9, #4 +srai t6, s9, #8 +srai t6, s9, #16 +srai t6, s9, #31 +srai t6, t6, #0 +srai t6, t6, #1 +srai t6, t6, #2 +srai t6, t6, #4 +srai t6, t6, #8 +srai t6, t6, #16 +srai t6, t6, #31 diff --git a/tests/riscv/rv32i/srl.asm b/tests/riscv/rv32i/srl.asm new file mode 100644 index 0000000..ad2a9e4 --- /dev/null +++ b/tests/riscv/rv32i/srl.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +srl zero, zero, zero +srl zero, zero, ra +srl zero, zero, t0 +srl zero, zero, a0 +srl zero, zero, a5 +srl zero, zero, s4 +srl zero, zero, s9 +srl zero, zero, t6 +srl zero, ra, zero +srl zero, ra, ra +srl zero, ra, t0 +srl zero, ra, a0 +srl zero, ra, a5 +srl zero, ra, s4 +srl zero, ra, s9 +srl zero, ra, t6 +srl zero, t0, zero +srl zero, t0, ra +srl zero, t0, t0 +srl zero, t0, a0 +srl zero, t0, a5 +srl zero, t0, s4 +srl zero, t0, s9 +srl zero, t0, t6 +srl zero, a0, zero +srl zero, a0, ra +srl zero, a0, t0 +srl zero, a0, a0 +srl zero, a0, a5 +srl zero, a0, s4 +srl zero, a0, s9 +srl zero, a0, t6 +srl zero, a5, zero +srl zero, a5, ra +srl zero, a5, t0 +srl zero, a5, a0 +srl zero, a5, a5 +srl zero, a5, s4 +srl zero, a5, s9 +srl zero, a5, t6 +srl zero, s4, zero +srl zero, s4, ra +srl zero, s4, t0 +srl zero, s4, a0 +srl zero, s4, a5 +srl zero, s4, s4 +srl zero, s4, s9 +srl zero, s4, t6 +srl zero, s9, zero +srl zero, s9, ra +srl zero, s9, t0 +srl zero, s9, a0 +srl zero, s9, a5 +srl zero, s9, s4 +srl zero, s9, s9 +srl zero, s9, t6 +srl zero, t6, zero +srl zero, t6, ra +srl zero, t6, t0 +srl zero, t6, a0 +srl zero, t6, a5 +srl zero, t6, s4 +srl zero, t6, s9 +srl zero, t6, t6 +srl ra, zero, zero +srl ra, zero, ra +srl ra, zero, t0 +srl ra, zero, a0 +srl ra, zero, a5 +srl ra, zero, s4 +srl ra, zero, s9 +srl ra, zero, t6 +srl ra, ra, zero +srl ra, ra, ra +srl ra, ra, t0 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t0, a0 +srl t0, t0, a5 +srl t0, t0, s4 +srl t0, t0, s9 +srl t0, t0, t6 +srl t0, a0, zero +srl t0, a0, ra +srl t0, a0, t0 +srl t0, a0, a0 +srl t0, a0, a5 +srl t0, a0, s4 +srl t0, a0, s9 +srl t0, a0, t6 +srl t0, a5, zero +srl t0, a5, ra +srl t0, a5, t0 +srl t0, a5, a0 +srl t0, a5, a5 +srl t0, a5, s4 +srl t0, a5, s9 +srl t0, a5, t6 +srl t0, s4, zero +srl t0, s4, ra +srl t0, s4, t0 +srl t0, s4, a0 +srl t0, s4, a5 +srl t0, s4, s4 +srl t0, s4, s9 +srl t0, s4, t6 +srl t0, s9, zero +srl t0, s9, ra +srl t0, s9, t0 +srl t0, s9, a0 +srl t0, s9, a5 +srl t0, s9, s4 +srl t0, s9, s9 +srl t0, s9, t6 +srl t0, t6, zero +srl t0, t6, ra +srl t0, t6, t0 +srl t0, t6, a0 +srl t0, t6, a5 +srl t0, t6, s4 +srl t0, t6, s9 +srl t0, t6, t6 +srl a0, zero, zero +srl a0, zero, ra +srl a0, zero, t0 +srl a0, zero, a0 +srl a0, zero, a5 +srl a0, zero, s4 +srl a0, zero, s9 +srl a0, zero, t6 +srl a0, ra, zero +srl a0, ra, ra +srl a0, ra, t0 +srl a0, ra, a0 +srl a0, ra, a5 +srl a0, ra, s4 +srl a0, ra, s9 +srl a0, ra, t6 +srl a0, t0, zero +srl a0, t0, ra +srl a0, t0, t0 +srl a0, t0, a0 +srl a0, t0, a5 +srl a0, t0, s4 +srl a0, t0, s9 +srl a0, t0, t6 +srl a0, a0, zero +srl a0, a0, ra +srl a0, a0, t0 +srl a0, a0, a0 +srl a0, a0, a5 +srl a0, a0, s4 +srl a0, a0, s9 +srl a0, a0, t6 +srl a0, a5, zero +srl a0, a5, ra +srl a0, a5, t0 +srl a0, a5, a0 +srl a0, a5, a5 +srl a0, a5, s4 +srl a0, a5, s9 +srl a0, a5, t6 +srl a0, s4, zero +srl a0, s4, ra +srl a0, s4, t0 +srl a0, s4, a0 +srl a0, s4, a5 +srl a0, s4, s4 +srl a0, s4, s9 +srl a0, s4, t6 +srl a0, s9, zero +srl a0, s9, ra +srl a0, s9, t0 +srl a0, s9, a0 +srl a0, s9, a5 +srl a0, s9, s4 +srl a0, s9, s9 +srl a0, s9, t6 +srl a0, t6, zero +srl a0, t6, ra +srl a0, t6, t0 +srl a0, t6, a0 +srl a0, t6, a5 +srl a0, t6, s4 +srl a0, t6, s9 +srl a0, t6, t6 +srl a5, zero, zero +srl a5, zero, ra +srl a5, zero, t0 +srl a5, zero, a0 +srl a5, zero, a5 +srl a5, zero, s4 +srl a5, zero, s9 +srl a5, zero, t6 +srl a5, ra, zero +srl a5, ra, ra +srl a5, ra, t0 +srl a5, ra, a0 +srl a5, ra, a5 +srl a5, ra, s4 +srl a5, ra, s9 +srl a5, ra, t6 +srl a5, t0, zero +srl a5, t0, ra +srl a5, t0, t0 +srl a5, t0, a0 +srl a5, t0, a5 +srl a5, t0, s4 +srl a5, t0, s9 +srl a5, t0, t6 +srl a5, a0, zero +srl a5, a0, ra +srl a5, a0, t0 +srl a5, a0, a0 +srl a5, a0, a5 +srl a5, a0, s4 +srl a5, a0, s9 +srl a5, a0, t6 +srl a5, a5, zero +srl a5, a5, ra +srl a5, a5, t0 +srl a5, a5, a0 +srl a5, a5, a5 +srl a5, a5, s4 +srl a5, a5, s9 +srl a5, a5, t6 +srl a5, s4, zero +srl a5, s4, ra +srl a5, s4, t0 +srl a5, s4, a0 +srl a5, s4, a5 +srl a5, s4, s4 +srl a5, s4, s9 +srl a5, s4, t6 +srl a5, s9, zero +srl a5, s9, ra +srl a5, s9, t0 +srl a5, s9, a0 +srl a5, s9, a5 +srl a5, s9, s4 +srl a5, s9, s9 +srl a5, s9, t6 +srl a5, t6, zero +srl a5, t6, ra +srl a5, t6, t0 +srl a5, t6, a0 +srl a5, t6, a5 +srl a5, t6, s4 +srl a5, t6, s9 +srl a5, t6, t6 +srl s4, zero, zero +srl s4, zero, ra +srl s4, zero, t0 +srl s4, zero, a0 +srl s4, zero, a5 +srl s4, zero, s4 +srl s4, zero, s9 +srl s4, zero, t6 +srl s4, ra, zero +srl s4, ra, ra +srl s4, ra, t0 +srl s4, ra, a0 +srl s4, ra, a5 +srl s4, ra, s4 +srl s4, ra, s9 +srl s4, ra, t6 +srl s4, t0, zero +srl s4, t0, ra +srl s4, t0, t0 +srl s4, t0, a0 +srl s4, t0, a5 +srl s4, t0, s4 +srl s4, t0, s9 +srl s4, t0, t6 +srl s4, a0, zero +srl s4, a0, ra +srl s4, a0, t0 +srl s4, a0, a0 +srl s4, a0, a5 +srl s4, a0, s4 +srl s4, a0, s9 +srl s4, a0, t6 +srl s4, a5, zero +srl s4, a5, ra +srl s4, a5, t0 +srl s4, a5, a0 +srl s4, a5, a5 +srl s4, a5, s4 +srl s4, a5, s9 +srl s4, a5, t6 +srl s4, s4, zero +srl s4, s4, ra +srl s4, s4, t0 +srl s4, s4, a0 +srl s4, s4, a5 +srl s4, s4, s4 +srl s4, s4, s9 +srl s4, s4, t6 +srl s4, s9, zero +srl s4, s9, ra +srl s4, s9, t0 +srl s4, s9, a0 +srl s4, s9, a5 +srl s4, s9, s4 +srl s4, s9, s9 +srl s4, s9, t6 +srl s4, t6, zero +srl s4, t6, ra +srl s4, t6, t0 +srl s4, t6, a0 +srl s4, t6, a5 +srl s4, t6, s4 +srl s4, t6, s9 +srl s4, t6, t6 +srl s9, zero, zero +srl s9, zero, ra +srl s9, zero, t0 +srl s9, zero, a0 +srl s9, zero, a5 +srl s9, zero, s4 +srl s9, zero, s9 +srl s9, zero, t6 +srl s9, ra, zero +srl s9, ra, ra +srl s9, ra, t0 +srl s9, ra, a0 +srl s9, ra, a5 +srl s9, ra, s4 +srl s9, ra, s9 +srl s9, ra, t6 +srl s9, t0, zero +srl s9, t0, ra +srl s9, t0, t0 +srl s9, t0, a0 +srl s9, t0, a5 +srl s9, t0, s4 +srl s9, t0, s9 +srl s9, t0, t6 +srl s9, a0, zero +srl s9, a0, ra +srl s9, a0, t0 +srl s9, a0, a0 +srl s9, a0, a5 +srl s9, a0, s4 +srl s9, a0, s9 +srl s9, a0, t6 +srl s9, a5, zero +srl s9, a5, ra +srl s9, a5, t0 +srl s9, a5, a0 +srl s9, a5, a5 +srl s9, a5, s4 +srl s9, a5, s9 +srl s9, a5, t6 +srl s9, s4, zero +srl s9, s4, ra +srl s9, s4, t0 +srl s9, s4, a0 +srl s9, s4, a5 +srl s9, s4, s4 +srl s9, s4, s9 +srl s9, s4, t6 +srl s9, s9, zero +srl s9, s9, ra +srl s9, s9, t0 +srl s9, s9, a0 +srl s9, s9, a5 +srl s9, s9, s4 +srl s9, s9, s9 +srl s9, s9, t6 +srl s9, t6, zero +srl s9, t6, ra +srl s9, t6, t0 +srl s9, t6, a0 +srl s9, t6, a5 +srl s9, t6, s4 +srl s9, t6, s9 +srl s9, t6, t6 +srl t6, zero, zero +srl t6, zero, ra +srl t6, zero, t0 +srl t6, zero, a0 +srl t6, zero, a5 +srl t6, zero, s4 +srl t6, zero, s9 +srl t6, zero, t6 +srl t6, ra, zero +srl t6, ra, ra +srl t6, ra, t0 +srl t6, ra, a0 +srl t6, ra, a5 +srl t6, ra, s4 +srl t6, ra, s9 +srl t6, ra, t6 +srl t6, t0, zero +srl t6, t0, ra +srl t6, t0, t0 +srl t6, t0, a0 +srl t6, t0, a5 +srl t6, t0, s4 +srl t6, t0, s9 +srl t6, t0, t6 +srl t6, a0, zero +srl t6, a0, ra +srl t6, a0, t0 +srl t6, a0, a0 +srl t6, a0, a5 +srl t6, a0, s4 +srl t6, a0, s9 +srl t6, a0, t6 +srl t6, a5, zero +srl t6, a5, ra +srl t6, a5, t0 +srl t6, a5, a0 +srl t6, a5, a5 +srl t6, a5, s4 +srl t6, a5, s9 +srl t6, a5, t6 +srl t6, s4, zero +srl t6, s4, ra +srl t6, s4, t0 +srl t6, s4, a0 +srl t6, s4, a5 +srl t6, s4, s4 +srl t6, s4, s9 +srl t6, s4, t6 +srl t6, s9, zero +srl t6, s9, ra +srl t6, s9, t0 +srl t6, s9, a0 +srl t6, s9, a5 +srl t6, s9, s4 +srl t6, s9, s9 +srl t6, s9, t6 +srl t6, t6, zero +srl t6, t6, ra +srl t6, t6, t0 +srl t6, t6, a0 +srl t6, t6, a5 +srl t6, t6, s4 +srl t6, t6, s9 +srl t6, t6, t6 diff --git a/tests/riscv/rv32i/srli.asm b/tests/riscv/rv32i/srli.asm new file mode 100644 index 0000000..9efbe5a --- /dev/null +++ b/tests/riscv/rv32i/srli.asm @@ -0,0 +1,452 @@ +.lang riscv32 +.org 0x0 + +srli zero, zero, #0 +srli zero, zero, #1 +srli zero, zero, #2 +srli zero, zero, #4 +srli zero, zero, #8 +srli zero, zero, #16 +srli zero, zero, #31 +srli zero, ra, #0 +srli zero, ra, #1 +srli zero, ra, #2 +srli zero, ra, #4 +srli zero, ra, #8 +srli zero, ra, #16 +srli zero, ra, #31 +srli zero, t0, #0 +srli zero, t0, #1 +srli zero, t0, #2 +srli zero, t0, #4 +srli zero, t0, #8 +srli zero, t0, #16 +srli zero, t0, #31 +srli zero, a0, #0 +srli zero, a0, #1 +srli zero, a0, #2 +srli zero, a0, #4 +srli zero, a0, #8 +srli zero, a0, #16 +srli zero, a0, #31 +srli zero, a5, #0 +srli zero, a5, #1 +srli zero, a5, #2 +srli zero, a5, #4 +srli zero, a5, #8 +srli zero, a5, #16 +srli zero, a5, #31 +srli zero, s4, #0 +srli zero, s4, #1 +srli zero, s4, #2 +srli zero, s4, #4 +srli zero, s4, #8 +srli zero, s4, #16 +srli zero, s4, #31 +srli zero, s9, #0 +srli zero, s9, #1 +srli zero, s9, #2 +srli zero, s9, #4 +srli zero, s9, #8 +srli zero, s9, #16 +srli zero, s9, #31 +srli zero, t6, #0 +srli zero, t6, #1 +srli zero, t6, #2 +srli zero, t6, #4 +srli zero, t6, #8 +srli zero, t6, #16 +srli zero, t6, #31 +srli ra, zero, #0 +srli ra, zero, #1 +srli ra, zero, #2 +srli ra, zero, #4 +srli ra, zero, #8 +srli ra, zero, #16 +srli ra, zero, #31 +srli ra, ra, #0 +srli ra, ra, #1 +srli ra, ra, #2 +srli ra, ra, #4 +srli ra, ra, #8 +srli ra, ra, #16 +srli ra, ra, #31 +srli ra, t0, #0 +srli ra, t0, #1 +srli ra, t0, #2 +srli ra, t0, #4 +srli ra, t0, #8 +srli ra, t0, #16 +srli ra, t0, #31 +srli ra, a0, #0 +srli ra, a0, #1 +srli ra, a0, #2 +srli ra, a0, #4 +srli ra, a0, #8 +srli ra, a0, #16 +srli ra, a0, #31 +srli ra, a5, #0 +srli ra, a5, #1 +srli ra, a5, #2 +srli ra, a5, #4 +srli ra, a5, #8 +srli ra, a5, #16 +srli ra, a5, #31 +srli ra, s4, #0 +srli ra, s4, #1 +srli ra, s4, #2 +srli ra, s4, #4 +srli ra, s4, #8 +srli ra, s4, #16 +srli ra, s4, #31 +srli ra, s9, #0 +srli ra, s9, #1 +srli ra, s9, #2 +srli ra, s9, #4 +srli ra, s9, #8 +srli ra, s9, #16 +srli ra, s9, #31 +srli ra, t6, #0 +srli ra, t6, #1 +srli ra, t6, #2 +srli ra, t6, #4 +srli ra, t6, #8 +srli ra, t6, #16 +srli ra, t6, #31 +srli t0, zero, #0 +srli t0, zero, #1 +srli t0, zero, #2 +srli t0, zero, #4 +srli t0, zero, #8 +srli t0, zero, #16 +srli t0, zero, #31 +srli t0, ra, #0 +srli t0, ra, #1 +srli t0, ra, #2 +srli t0, ra, #4 +srli t0, ra, #8 +srli t0, ra, #16 +srli t0, ra, #31 +srli t0, t0, #0 +srli t0, t0, #1 +srli t0, t0, #2 +srli t0, t0, #4 +srli t0, t0, #8 +srli t0, t0, #16 +srli t0, t0, #31 +srli t0, a0, #0 +srli t0, a0, #1 +srli t0, a0, #2 +srli t0, a0, #4 +srli t0, a0, #8 +srli t0, a0, #16 +srli t0, a0, #31 +srli t0, a5, #0 +srli t0, a5, #1 +srli t0, a5, #2 +srli t0, a5, #4 +srli t0, a5, #8 +srli t0, a5, #16 +srli t0, a5, #31 +srli t0, s4, #0 +srli t0, s4, #1 +srli t0, s4, #2 +srli t0, s4, #4 +srli t0, s4, #8 +srli t0, s4, #16 +srli t0, s4, #31 +srli t0, s9, #0 +srli t0, s9, #1 +srli t0, s9, #2 +srli t0, s9, #4 +srli t0, s9, #8 +srli t0, s9, #16 +srli t0, s9, #31 +srli t0, t6, #0 +srli t0, t6, #1 +srli t0, t6, #2 +srli t0, t6, #4 +srli t0, t6, #8 +srli t0, t6, #16 +srli t0, t6, #31 +srli a0, zero, #0 +srli a0, zero, #1 +srli a0, zero, #2 +srli a0, zero, #4 +srli a0, zero, #8 +srli a0, zero, #16 +srli a0, zero, #31 +srli a0, ra, #0 +srli a0, ra, #1 +srli a0, ra, #2 +srli a0, ra, #4 +srli a0, ra, #8 +srli a0, ra, #16 +srli a0, ra, #31 +srli a0, t0, #0 +srli a0, t0, #1 +srli a0, t0, #2 +srli a0, t0, #4 +srli a0, t0, #8 +srli a0, t0, #16 +srli a0, t0, #31 +srli a0, a0, #0 +srli a0, a0, #1 +srli a0, a0, #2 +srli a0, a0, #4 +srli a0, a0, #8 +srli a0, a0, #16 +srli a0, a0, #31 +srli a0, a5, #0 +srli a0, a5, #1 +srli a0, a5, #2 +srli a0, a5, #4 +srli a0, a5, #8 +srli a0, a5, #16 +srli a0, a5, #31 +srli a0, s4, #0 +srli a0, s4, #1 +srli a0, s4, #2 +srli a0, s4, #4 +srli a0, s4, #8 +srli a0, s4, #16 +srli a0, s4, #31 +srli a0, s9, #0 +srli a0, s9, #1 +srli a0, s9, #2 +srli a0, s9, #4 +srli a0, s9, #8 +srli a0, s9, #16 +srli a0, s9, #31 +srli a0, t6, #0 +srli a0, t6, #1 +srli a0, t6, #2 +srli a0, t6, #4 +srli a0, t6, #8 +srli a0, t6, #16 +srli a0, t6, #31 +srli a5, zero, #0 +srli a5, zero, #1 +srli a5, zero, #2 +srli a5, zero, #4 +srli a5, zero, #8 +srli a5, zero, #16 +srli a5, zero, #31 +srli a5, ra, #0 +srli a5, ra, #1 +srli a5, ra, #2 +srli a5, ra, #4 +srli a5, ra, #8 +srli a5, ra, #16 +srli a5, ra, #31 +srli a5, t0, #0 +srli a5, t0, #1 +srli a5, t0, #2 +srli a5, t0, #4 +srli a5, t0, #8 +srli a5, t0, #16 +srli a5, t0, #31 +srli a5, a0, #0 +srli a5, a0, #1 +srli a5, a0, #2 +srli a5, a0, #4 +srli a5, a0, #8 +srli a5, a0, #16 +srli a5, a0, #31 +srli a5, a5, #0 +srli a5, a5, #1 +srli a5, a5, #2 +srli a5, a5, #4 +srli a5, a5, #8 +srli a5, a5, #16 +srli a5, a5, #31 +srli a5, s4, #0 +srli a5, s4, #1 +srli a5, s4, #2 +srli a5, s4, #4 +srli a5, s4, #8 +srli a5, s4, #16 +srli a5, s4, #31 +srli a5, s9, #0 +srli a5, s9, #1 +srli a5, s9, #2 +srli a5, s9, #4 +srli a5, s9, #8 +srli a5, s9, #16 +srli a5, s9, #31 +srli a5, t6, #0 +srli a5, t6, #1 +srli a5, t6, #2 +srli a5, t6, #4 +srli a5, t6, #8 +srli a5, t6, #16 +srli a5, t6, #31 +srli s4, zero, #0 +srli s4, zero, #1 +srli s4, zero, #2 +srli s4, zero, #4 +srli s4, zero, #8 +srli s4, zero, #16 +srli s4, zero, #31 +srli s4, ra, #0 +srli s4, ra, #1 +srli s4, ra, #2 +srli s4, ra, #4 +srli s4, ra, #8 +srli s4, ra, #16 +srli s4, ra, #31 +srli s4, t0, #0 +srli s4, t0, #1 +srli s4, t0, #2 +srli s4, t0, #4 +srli s4, t0, #8 +srli s4, t0, #16 +srli s4, t0, #31 +srli s4, a0, #0 +srli s4, a0, #1 +srli s4, a0, #2 +srli s4, a0, #4 +srli s4, a0, #8 +srli s4, a0, #16 +srli s4, a0, #31 +srli s4, a5, #0 +srli s4, a5, #1 +srli s4, a5, #2 +srli s4, a5, #4 +srli s4, a5, #8 +srli s4, a5, #16 +srli s4, a5, #31 +srli s4, s4, #0 +srli s4, s4, #1 +srli s4, s4, #2 +srli s4, s4, #4 +srli s4, s4, #8 +srli s4, s4, #16 +srli s4, s4, #31 +srli s4, s9, #0 +srli s4, s9, #1 +srli s4, s9, #2 +srli s4, s9, #4 +srli s4, s9, #8 +srli s4, s9, #16 +srli s4, s9, #31 +srli s4, t6, #0 +srli s4, t6, #1 +srli s4, t6, #2 +srli s4, t6, #4 +srli s4, t6, #8 +srli s4, t6, #16 +srli s4, t6, #31 +srli s9, zero, #0 +srli s9, zero, #1 +srli s9, zero, #2 +srli s9, zero, #4 +srli s9, zero, #8 +srli s9, zero, #16 +srli s9, zero, #31 +srli s9, ra, #0 +srli s9, ra, #1 +srli s9, ra, #2 +srli s9, ra, #4 +srli s9, ra, #8 +srli s9, ra, #16 +srli s9, ra, #31 +srli s9, t0, #0 +srli s9, t0, #1 +srli s9, t0, #2 +srli s9, t0, #4 +srli s9, t0, #8 +srli s9, t0, #16 +srli s9, t0, #31 +srli s9, a0, #0 +srli s9, a0, #1 +srli s9, a0, #2 +srli s9, a0, #4 +srli s9, a0, #8 +srli s9, a0, #16 +srli s9, a0, #31 +srli s9, a5, #0 +srli s9, a5, #1 +srli s9, a5, #2 +srli s9, a5, #4 +srli s9, a5, #8 +srli s9, a5, #16 +srli s9, a5, #31 +srli s9, s4, #0 +srli s9, s4, #1 +srli s9, s4, #2 +srli s9, s4, #4 +srli s9, s4, #8 +srli s9, s4, #16 +srli s9, s4, #31 +srli s9, s9, #0 +srli s9, s9, #1 +srli s9, s9, #2 +srli s9, s9, #4 +srli s9, s9, #8 +srli s9, s9, #16 +srli s9, s9, #31 +srli s9, t6, #0 +srli s9, t6, #1 +srli s9, t6, #2 +srli s9, t6, #4 +srli s9, t6, #8 +srli s9, t6, #16 +srli s9, t6, #31 +srli t6, zero, #0 +srli t6, zero, #1 +srli t6, zero, #2 +srli t6, zero, #4 +srli t6, zero, #8 +srli t6, zero, #16 +srli t6, zero, #31 +srli t6, ra, #0 +srli t6, ra, #1 +srli t6, ra, #2 +srli t6, ra, #4 +srli t6, ra, #8 +srli t6, ra, #16 +srli t6, ra, #31 +srli t6, t0, #0 +srli t6, t0, #1 +srli t6, t0, #2 +srli t6, t0, #4 +srli t6, t0, #8 +srli t6, t0, #16 +srli t6, t0, #31 +srli t6, a0, #0 +srli t6, a0, #1 +srli t6, a0, #2 +srli t6, a0, #4 +srli t6, a0, #8 +srli t6, a0, #16 +srli t6, a0, #31 +srli t6, a5, #0 +srli t6, a5, #1 +srli t6, a5, #2 +srli t6, a5, #4 +srli t6, a5, #8 +srli t6, a5, #16 +srli t6, a5, #31 +srli t6, s4, #0 +srli t6, s4, #1 +srli t6, s4, #2 +srli t6, s4, #4 +srli t6, s4, #8 +srli t6, s4, #16 +srli t6, s4, #31 +srli t6, s9, #0 +srli t6, s9, #1 +srli t6, s9, #2 +srli t6, s9, #4 +srli t6, s9, #8 +srli t6, s9, #16 +srli t6, s9, #31 +srli t6, t6, #0 +srli t6, t6, #1 +srli t6, t6, #2 +srli t6, t6, #4 +srli t6, t6, #8 +srli t6, t6, #16 +srli t6, t6, #31 + diff --git a/tests/riscv/rv32i/srli.bin b/tests/riscv/rv32i/srli.bin new file mode 100644 index 0000000000000000000000000000000000000000..2275ce9dbdf8b0943bd277cca5c401adc7384a27 GIT binary patch literal 1792 zcmWmCafg*p9ER~d%Uag5KOKogiA18ekVqt2!x$dJyp^9wB>LmLv11s+80IY`5{d0| z{UFdb?W;eOsXO<5PoByf`6TD= zKmGQ?f83X6@>V{}h5Il4rFReHxxAAva_RnCf92gnc_HuRt6aJN(O-M_NM6bZ`6k!y zf91yaV|gVX<-6Rt-|Y_g4)_lE4)_lE+}wZc4)_lE4)_lE4*1;MPu;oid-7D?$R{~> z|LM0E{^Pzpleh9&F5G|VFTHyp&*hzbkxTdA`YZ1q$_sffU**dEkN(=bNAglW$Tzum z|0_4XAImHGDBtDA9bdo@Fa!(%L%_ z3-|)QfG^++_$t1Nui~rtD!z)Z;tTi!zJM>_3-|)QfUn}K_$t1Nui~rtD!z)Z;;Z;7 zzKXBnt9QG7w83bD(FUUpMjMPa7;UiWny%@ZuIZYtojUt$_Sx*S*=MuQW}nSIqkTsE zjP@DrGumgg&uE{`KAU|u`)u~v?6cWtv(IRs(LSSnM*EER8SOLLXS2^{pUpm-eKz}S z_Sx*S*=MuQW}nSIn|(I>Z2TpT5=V)n#8KiXag;dfx~}WGuIsw4>!*&t&R^%R^Vj+7 z{B`~ke~G`uU*a$Em-tKkb^bbkoxjds=dbhE`AhsI{t|zQzr-=^8I)9zN z&R^%R^Vj+7{B{01f1SV1-^S6#(ZT_2 z_zJ#)uiz{A3ciAG;am6?zJ+h$Tlf~fg0J8!_zJ#)uiz{A7QTgV;am6?zJ+h$Tlf~f Og>T_o_!ho(xBCa9tW+-m literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/srli.disasm b/tests/riscv/rv32i/srli.disasm new file mode 100644 index 0000000..8e3d1c0 --- /dev/null +++ b/tests/riscv/rv32i/srli.disasm @@ -0,0 +1,448 @@ +srli zero, zero, #0 +srli zero, zero, #1 +srli zero, zero, #2 +srli zero, zero, #4 +srli zero, zero, #8 +srli zero, zero, #16 +srli zero, zero, #31 +srli zero, ra, #0 +srli zero, ra, #1 +srli zero, ra, #2 +srli zero, ra, #4 +srli zero, ra, #8 +srli zero, ra, #16 +srli zero, ra, #31 +srli zero, t0, #0 +srli zero, t0, #1 +srli zero, t0, #2 +srli zero, t0, #4 +srli zero, t0, #8 +srli zero, t0, #16 +srli zero, t0, #31 +srli zero, a0, #0 +srli zero, a0, #1 +srli zero, a0, #2 +srli zero, a0, #4 +srli zero, a0, #8 +srli zero, a0, #16 +srli zero, a0, #31 +srli zero, a5, #0 +srli zero, a5, #1 +srli zero, a5, #2 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+srli s4, a5, #16 +srli s4, a5, #31 +srli s4, s4, #0 +srli s4, s4, #1 +srli s4, s4, #2 +srli s4, s4, #4 +srli s4, s4, #8 +srli s4, s4, #16 +srli s4, s4, #31 +srli s4, s9, #0 +srli s4, s9, #1 +srli s4, s9, #2 +srli s4, s9, #4 +srli s4, s9, #8 +srli s4, s9, #16 +srli s4, s9, #31 +srli s4, t6, #0 +srli s4, t6, #1 +srli s4, t6, #2 +srli s4, t6, #4 +srli s4, t6, #8 +srli s4, t6, #16 +srli s4, t6, #31 +srli s9, zero, #0 +srli s9, zero, #1 +srli s9, zero, #2 +srli s9, zero, #4 +srli s9, zero, #8 +srli s9, zero, #16 +srli s9, zero, #31 +srli s9, ra, #0 +srli s9, ra, #1 +srli s9, ra, #2 +srli s9, ra, #4 +srli s9, ra, #8 +srli s9, ra, #16 +srli s9, ra, #31 +srli s9, t0, #0 +srli s9, t0, #1 +srli s9, t0, #2 +srli s9, t0, #4 +srli s9, t0, #8 +srli s9, t0, #16 +srli s9, t0, #31 +srli s9, a0, #0 +srli s9, a0, #1 +srli s9, a0, #2 +srli s9, a0, #4 +srli s9, a0, #8 +srli s9, a0, #16 +srli s9, a0, #31 +srli s9, a5, #0 +srli s9, a5, #1 +srli s9, a5, #2 +srli s9, a5, #4 +srli s9, a5, #8 +srli s9, a5, #16 +srli s9, a5, #31 +srli s9, s4, #0 +srli s9, s4, #1 +srli s9, s4, #2 +srli s9, s4, #4 +srli s9, s4, #8 +srli s9, s4, #16 +srli s9, s4, #31 +srli s9, s9, #0 +srli s9, s9, #1 +srli s9, s9, #2 +srli s9, s9, #4 +srli s9, s9, #8 +srli s9, s9, #16 +srli s9, s9, #31 +srli s9, t6, #0 +srli s9, t6, #1 +srli s9, t6, #2 +srli s9, t6, #4 +srli s9, t6, #8 +srli s9, t6, #16 +srli s9, t6, #31 +srli t6, zero, #0 +srli t6, zero, #1 +srli t6, zero, #2 +srli t6, zero, #4 +srli t6, zero, #8 +srli t6, zero, #16 +srli t6, zero, #31 +srli t6, ra, #0 +srli t6, ra, #1 +srli t6, ra, #2 +srli t6, ra, #4 +srli t6, ra, #8 +srli t6, ra, #16 +srli t6, ra, #31 +srli t6, t0, #0 +srli t6, t0, #1 +srli t6, t0, #2 +srli t6, t0, #4 +srli t6, t0, #8 +srli t6, t0, #16 +srli t6, t0, #31 +srli t6, a0, #0 +srli t6, a0, #1 +srli t6, a0, #2 +srli t6, a0, #4 +srli t6, a0, #8 +srli t6, a0, #16 +srli t6, a0, #31 +srli t6, a5, #0 +srli t6, a5, #1 +srli t6, a5, #2 +srli t6, a5, #4 +srli t6, a5, #8 +srli t6, a5, #16 +srli t6, a5, #31 +srli t6, s4, #0 +srli t6, s4, #1 +srli t6, s4, #2 +srli t6, s4, #4 +srli t6, s4, #8 +srli t6, s4, #16 +srli t6, s4, #31 +srli t6, s9, #0 +srli t6, s9, #1 +srli t6, s9, #2 +srli t6, s9, #4 +srli t6, s9, #8 +srli t6, s9, #16 +srli t6, s9, #31 +srli t6, t6, #0 +srli t6, t6, #1 +srli t6, t6, #2 +srli t6, t6, #4 +srli t6, t6, #8 +srli t6, t6, #16 +srli t6, t6, #31 diff --git a/tests/riscv/rv32i/sub.asm b/tests/riscv/rv32i/sub.asm new file mode 100644 index 0000000..bae6174 --- /dev/null +++ b/tests/riscv/rv32i/sub.asm @@ -0,0 +1,516 @@ +.lang riscv32 +.org 0x0 + +sub zero, zero, zero +sub zero, zero, ra +sub zero, zero, t0 +sub zero, zero, a0 +sub zero, zero, a5 +sub zero, zero, s4 +sub zero, zero, s9 +sub zero, zero, t6 +sub zero, ra, zero +sub zero, ra, ra +sub zero, ra, t0 +sub zero, ra, a0 +sub zero, ra, a5 +sub zero, ra, s4 +sub zero, ra, s9 +sub zero, ra, t6 +sub zero, t0, zero +sub zero, t0, ra +sub zero, t0, t0 +sub zero, t0, a0 +sub zero, t0, a5 +sub zero, t0, s4 +sub zero, t0, s9 +sub zero, t0, t6 +sub zero, a0, zero +sub zero, a0, ra +sub zero, a0, t0 +sub zero, a0, a0 +sub zero, a0, a5 +sub zero, a0, s4 +sub zero, a0, s9 +sub zero, a0, t6 +sub zero, a5, zero +sub zero, a5, ra +sub zero, a5, t0 +sub zero, a5, a0 +sub zero, a5, a5 +sub zero, a5, s4 +sub zero, a5, s9 +sub zero, a5, t6 +sub zero, s4, zero +sub zero, s4, ra +sub zero, s4, t0 +sub zero, s4, a0 +sub zero, s4, a5 +sub zero, s4, s4 +sub zero, s4, s9 +sub zero, s4, t6 +sub zero, s9, zero +sub zero, s9, ra +sub zero, s9, t0 +sub zero, s9, a0 +sub zero, s9, a5 +sub zero, s9, s4 +sub zero, s9, s9 +sub zero, s9, t6 +sub zero, t6, zero +sub zero, t6, ra +sub zero, t6, t0 +sub zero, t6, a0 +sub zero, t6, a5 +sub zero, t6, s4 +sub zero, t6, s9 +sub zero, t6, t6 +sub ra, zero, zero +sub ra, zero, ra +sub ra, zero, t0 +sub ra, zero, a0 +sub ra, zero, a5 +sub ra, zero, s4 +sub ra, zero, s9 +sub ra, zero, t6 +sub ra, ra, zero +sub ra, ra, ra +sub ra, ra, t0 +sub ra, ra, a0 +sub ra, ra, a5 +sub ra, ra, s4 +sub ra, ra, s9 +sub ra, ra, t6 +sub ra, t0, zero +sub ra, t0, ra +sub ra, t0, t0 +sub ra, t0, a0 +sub ra, t0, a5 +sub ra, t0, s4 +sub ra, t0, s9 +sub ra, t0, t6 +sub ra, a0, zero +sub ra, a0, ra +sub ra, a0, t0 +sub ra, a0, a0 +sub ra, a0, a5 +sub ra, a0, s4 +sub ra, a0, s9 +sub ra, a0, t6 +sub ra, a5, zero +sub ra, a5, ra +sub ra, a5, t0 +sub ra, a5, a0 +sub ra, a5, a5 +sub ra, a5, s4 +sub ra, a5, s9 +sub ra, a5, t6 +sub ra, s4, zero +sub ra, s4, ra +sub ra, s4, t0 +sub ra, s4, a0 +sub ra, s4, a5 +sub ra, s4, s4 +sub ra, s4, s9 +sub ra, s4, t6 +sub ra, s9, zero +sub ra, s9, ra +sub ra, s9, t0 +sub ra, s9, a0 +sub ra, s9, a5 +sub ra, s9, s4 +sub ra, s9, s9 +sub ra, s9, t6 +sub ra, t6, zero +sub ra, t6, ra +sub ra, t6, t0 +sub ra, t6, a0 +sub ra, t6, a5 +sub ra, t6, s4 +sub ra, t6, s9 +sub ra, t6, t6 +sub t0, zero, zero +sub t0, zero, ra +sub t0, zero, t0 +sub t0, zero, a0 +sub t0, zero, a5 +sub t0, zero, s4 +sub t0, zero, s9 +sub t0, zero, t6 +sub t0, ra, zero +sub t0, ra, ra +sub t0, ra, t0 +sub t0, ra, a0 +sub t0, ra, a5 +sub t0, ra, s4 +sub t0, ra, s9 +sub t0, ra, t6 +sub t0, t0, zero +sub t0, t0, ra +sub t0, t0, t0 +sub t0, t0, a0 +sub t0, t0, a5 +sub t0, t0, s4 +sub t0, t0, s9 +sub t0, t0, t6 +sub t0, a0, zero +sub t0, a0, ra +sub t0, a0, t0 +sub t0, a0, a0 +sub t0, a0, a5 +sub t0, a0, s4 +sub t0, a0, s9 +sub t0, a0, t6 +sub t0, a5, zero +sub t0, a5, ra +sub t0, a5, t0 +sub t0, a5, a0 +sub t0, a5, a5 +sub t0, a5, s4 +sub t0, a5, s9 +sub t0, a5, t6 +sub t0, s4, zero +sub t0, s4, ra +sub t0, s4, t0 +sub t0, s4, a0 +sub t0, s4, a5 +sub t0, s4, s4 +sub t0, s4, s9 +sub t0, s4, t6 +sub t0, s9, zero +sub t0, s9, ra +sub t0, s9, t0 +sub t0, s9, a0 +sub t0, s9, a5 +sub t0, s9, s4 +sub t0, s9, s9 +sub t0, s9, t6 +sub t0, t6, zero +sub t0, t6, ra +sub t0, t6, t0 +sub t0, t6, a0 +sub t0, t6, a5 +sub t0, t6, s4 +sub t0, t6, s9 +sub t0, t6, t6 +sub a0, zero, zero +sub a0, zero, ra +sub a0, zero, t0 +sub a0, zero, a0 +sub a0, zero, a5 +sub a0, zero, s4 +sub a0, zero, s9 +sub a0, zero, t6 +sub a0, ra, zero +sub a0, ra, ra +sub a0, ra, t0 +sub a0, ra, a0 +sub a0, ra, a5 +sub a0, ra, s4 +sub a0, ra, s9 +sub a0, ra, t6 +sub a0, t0, zero +sub a0, t0, ra +sub a0, t0, t0 +sub a0, t0, a0 +sub a0, t0, a5 +sub a0, t0, s4 +sub a0, t0, s9 +sub a0, t0, t6 +sub a0, a0, zero +sub a0, a0, ra +sub a0, a0, t0 +sub a0, a0, a0 +sub a0, a0, a5 +sub a0, a0, s4 +sub a0, a0, s9 +sub a0, a0, t6 +sub a0, a5, zero +sub a0, a5, ra +sub a0, a5, t0 +sub a0, a5, a0 +sub a0, a5, a5 +sub a0, a5, s4 +sub a0, a5, s9 +sub a0, a5, t6 +sub a0, s4, zero +sub a0, s4, ra +sub a0, s4, t0 +sub a0, s4, a0 +sub a0, s4, a5 +sub a0, s4, s4 +sub a0, s4, s9 +sub a0, s4, t6 +sub a0, s9, zero +sub a0, s9, ra +sub a0, s9, t0 +sub a0, s9, a0 +sub a0, s9, a5 +sub a0, s9, s4 +sub a0, s9, s9 +sub a0, s9, t6 +sub a0, t6, zero +sub a0, t6, ra +sub a0, t6, t0 +sub a0, t6, a0 +sub a0, t6, a5 +sub a0, t6, s4 +sub a0, t6, s9 +sub a0, t6, t6 +sub a5, zero, zero +sub a5, zero, ra +sub a5, zero, t0 +sub a5, zero, a0 +sub a5, zero, a5 +sub a5, zero, s4 +sub a5, zero, s9 +sub a5, zero, t6 +sub a5, ra, zero +sub a5, ra, ra +sub a5, ra, t0 +sub a5, ra, a0 +sub a5, ra, a5 +sub a5, ra, s4 +sub a5, ra, s9 +sub a5, ra, t6 +sub a5, t0, zero +sub a5, t0, ra +sub a5, t0, t0 +sub a5, t0, a0 +sub a5, t0, a5 +sub a5, t0, s4 +sub a5, t0, s9 +sub a5, t0, t6 +sub a5, a0, zero +sub a5, a0, ra +sub a5, a0, t0 +sub a5, a0, a0 +sub a5, a0, a5 +sub a5, a0, s4 +sub a5, a0, s9 +sub a5, a0, t6 +sub a5, a5, zero +sub a5, a5, ra +sub a5, a5, t0 +sub a5, a5, a0 +sub a5, a5, a5 +sub a5, a5, s4 +sub a5, a5, s9 +sub a5, a5, t6 +sub a5, s4, zero +sub a5, s4, ra +sub a5, s4, t0 +sub a5, s4, a0 +sub a5, s4, a5 +sub a5, s4, s4 +sub a5, s4, s9 +sub a5, s4, t6 +sub a5, s9, zero +sub a5, s9, ra +sub a5, s9, t0 +sub a5, s9, a0 +sub a5, s9, a5 +sub a5, s9, s4 +sub a5, s9, s9 +sub a5, s9, t6 +sub a5, t6, zero +sub a5, t6, ra +sub a5, t6, t0 +sub a5, t6, a0 +sub a5, t6, a5 +sub a5, t6, s4 +sub a5, t6, s9 +sub a5, t6, t6 +sub s4, zero, zero +sub s4, zero, ra +sub s4, zero, t0 +sub s4, zero, a0 +sub s4, zero, a5 +sub s4, zero, s4 +sub s4, zero, s9 +sub s4, zero, t6 +sub s4, ra, zero +sub s4, ra, ra +sub s4, ra, t0 +sub s4, ra, a0 +sub s4, ra, a5 +sub s4, ra, s4 +sub s4, ra, s9 +sub s4, ra, t6 +sub s4, t0, zero +sub s4, t0, ra +sub s4, t0, t0 +sub s4, t0, a0 +sub s4, t0, a5 +sub s4, t0, s4 +sub s4, t0, s9 +sub s4, t0, t6 +sub s4, a0, zero +sub s4, a0, ra +sub s4, a0, t0 +sub s4, a0, a0 +sub s4, a0, a5 +sub s4, a0, s4 +sub s4, a0, s9 +sub s4, a0, t6 +sub s4, a5, zero +sub s4, a5, ra +sub s4, a5, t0 +sub s4, a5, a0 +sub s4, a5, a5 +sub s4, a5, s4 +sub s4, a5, s9 +sub s4, a5, t6 +sub s4, s4, zero +sub s4, s4, ra +sub s4, s4, t0 +sub s4, s4, a0 +sub s4, s4, a5 +sub s4, s4, s4 +sub s4, s4, s9 +sub s4, s4, t6 +sub s4, s9, zero +sub s4, s9, ra +sub s4, s9, t0 +sub s4, s9, a0 +sub s4, s9, a5 +sub s4, s9, s4 +sub s4, s9, s9 +sub s4, s9, t6 +sub s4, t6, zero +sub s4, t6, ra +sub s4, t6, t0 +sub s4, t6, a0 +sub s4, t6, a5 +sub s4, t6, s4 +sub s4, t6, s9 +sub s4, t6, t6 +sub s9, zero, zero +sub s9, zero, ra +sub s9, zero, t0 +sub s9, zero, a0 +sub s9, zero, a5 +sub s9, zero, s4 +sub s9, zero, s9 +sub s9, zero, t6 +sub s9, ra, zero +sub s9, ra, ra +sub s9, ra, t0 +sub s9, ra, a0 +sub s9, ra, a5 +sub s9, ra, s4 +sub s9, ra, s9 +sub s9, ra, t6 +sub s9, t0, zero +sub s9, t0, ra +sub s9, t0, t0 +sub s9, t0, a0 +sub s9, t0, a5 +sub s9, t0, s4 +sub s9, t0, s9 +sub s9, t0, t6 +sub s9, a0, zero +sub s9, a0, ra +sub s9, a0, t0 +sub s9, a0, a0 +sub s9, a0, a5 +sub s9, a0, s4 +sub s9, a0, s9 +sub s9, a0, t6 +sub s9, a5, zero +sub s9, a5, ra +sub s9, a5, t0 +sub s9, a5, a0 +sub s9, a5, a5 +sub s9, a5, s4 +sub s9, a5, s9 +sub s9, a5, t6 +sub s9, s4, zero +sub s9, s4, ra +sub s9, s4, t0 +sub s9, s4, a0 +sub s9, s4, a5 +sub s9, s4, s4 +sub s9, s4, s9 +sub s9, s4, t6 +sub s9, s9, zero +sub s9, s9, ra +sub s9, s9, t0 +sub s9, s9, a0 +sub s9, s9, a5 +sub s9, s9, s4 +sub s9, s9, s9 +sub s9, s9, t6 +sub s9, t6, zero +sub s9, t6, ra +sub s9, t6, t0 +sub s9, t6, a0 +sub s9, t6, a5 +sub s9, t6, s4 +sub s9, t6, s9 +sub s9, t6, t6 +sub t6, zero, zero +sub t6, zero, ra +sub t6, zero, t0 +sub t6, zero, a0 +sub t6, zero, a5 +sub t6, zero, s4 +sub t6, zero, s9 +sub t6, zero, t6 +sub t6, ra, zero +sub t6, ra, ra +sub t6, ra, t0 +sub t6, ra, a0 +sub t6, ra, a5 +sub t6, ra, s4 +sub t6, ra, s9 +sub t6, ra, t6 +sub t6, t0, zero +sub t6, t0, ra +sub t6, t0, t0 +sub t6, t0, a0 +sub t6, t0, a5 +sub t6, t0, s4 +sub t6, t0, s9 +sub t6, t0, t6 +sub t6, a0, zero +sub t6, a0, ra +sub t6, a0, t0 +sub t6, a0, a0 +sub t6, a0, a5 +sub t6, a0, s4 +sub t6, a0, s9 +sub t6, a0, t6 +sub t6, a5, zero +sub t6, a5, ra +sub t6, a5, t0 +sub t6, a5, a0 +sub t6, a5, a5 +sub t6, a5, s4 +sub t6, a5, s9 +sub t6, a5, t6 +sub t6, s4, zero +sub t6, s4, ra +sub t6, s4, t0 +sub t6, s4, a0 +sub t6, s4, a5 +sub t6, s4, s4 +sub t6, s4, s9 +sub t6, s4, t6 +sub t6, s9, zero +sub t6, s9, ra +sub t6, s9, t0 +sub t6, s9, a0 +sub t6, s9, a5 +sub t6, s9, s4 +sub t6, s9, s9 +sub t6, s9, t6 +sub t6, t6, zero +sub t6, t6, ra +sub t6, t6, t0 +sub t6, t6, a0 +sub t6, t6, a5 +sub t6, t6, s4 +sub t6, t6, s9 +sub t6, t6, t6 + diff --git a/tests/riscv/rv32i/sub.bin b/tests/riscv/rv32i/sub.bin new file mode 100644 index 0000000000000000000000000000000000000000..e47482c7ffb31b3d69095cfcc859742c8701d575 GIT binary patch literal 2048 zcmWmCafj7Q9LMoBjA0COMIzCI*eB3NBGDCz#C-Q(tYz=( z{PE$O?`QmYdwmTE5ApJazvdm%b5w@4mc|?{X#2+&{{dH_7`4@>YJxwLEwKB-h?# z?;pxL`6)N@!u_+{cvHN8B=6;y+{#P$FLEo@|Htx={FXa;<^EOh2Ydlvz!&fZd;wp; z7w|QG(>Hz7H+|DLeLMB|8~%pB;cxgG{)WHd5BLNAfIr|5_yhicKj3fp8~%pB;cxgG z{)WHd5BLNAfIr|5_yhicKj3fp8~%pB;cxgG{)WHdZ}=PjhQHx&_#6I)zujG&NBfTU z9ql{XceL+l-_gFKeRqA=cYW7)eb;w=KlS$C?Z4Z9xBqVc-Tu4%cl(d_AMHQdf3*K- z|Iz-V{YU%n_TTNl+kdzJZvWl>yZv|jkM-Lga5(*;D7Kx_#gZy{uBR+|HOad zKk=XVPy7%52mgcr!T;cY@IUw;{15&I|AYU*|KNY{KlmT~XMQukncvKB<~Q@3`OW-J z{nStW)KC4?PyIag{7?QT|C9g8|Kxx2Kl#u6XZ|z)ng7gx=0EeF`Jenx{wM#F|H=R4 zfAT;1&-`cpGyj?Y%zx%T^Pl;j{7?QT|C9g8|Kxx2Klz{hPyQ$WlmE&8iJ*%Fa8(*i~q&{;(zg9_%Hky{tN$w|H6Oa zzwp2KU;Hor7ypa@#sA`e@n85a{1^TU|Aqg;f8oFIzxZGLFa8(*i~q&{;(zhK_+R`l z{ulp?|Hc2}f8nqAD!z)Z;;Z;7zKXBn+xo5F`mNvkt>5~6>hW*<8~?_?@o)Sa|HfbO zSNs)!#b5DP{1t!2zwvMU8~?_?@o)Sa|HfbOSNs)!#b5DP{1t!2zwvMU8~?_?@o)Sa W|Hi-ZZ~Pno#=r4z{2TwiyZ9e_<}7Xi literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/sub.disasm b/tests/riscv/rv32i/sub.disasm new file mode 100644 index 0000000..ab68cc5 --- /dev/null +++ b/tests/riscv/rv32i/sub.disasm @@ -0,0 +1,512 @@ +sub zero, zero, zero +sub zero, zero, ra +sub zero, zero, t0 +sub zero, zero, a0 +sub zero, zero, a5 +sub zero, zero, s4 +sub zero, zero, s9 +sub zero, zero, t6 +sub zero, ra, zero +sub zero, ra, ra +sub zero, ra, t0 +sub zero, ra, a0 +sub zero, ra, a5 +sub zero, ra, s4 +sub zero, ra, s9 +sub zero, ra, t6 +sub zero, t0, zero +sub zero, t0, ra +sub zero, t0, t0 +sub zero, t0, a0 +sub zero, t0, a5 +sub zero, t0, s4 +sub zero, t0, s9 +sub zero, t0, t6 +sub zero, a0, zero +sub zero, a0, ra +sub zero, a0, t0 +sub zero, a0, a0 +sub zero, a0, a5 +sub zero, a0, s4 +sub zero, a0, s9 +sub zero, a0, t6 +sub zero, a5, zero +sub zero, a5, ra +sub zero, a5, t0 +sub zero, a5, a0 +sub zero, a5, a5 +sub zero, a5, s4 +sub zero, a5, s9 +sub zero, a5, t6 +sub zero, s4, zero +sub zero, s4, ra +sub zero, s4, t0 +sub zero, s4, a0 +sub zero, s4, a5 +sub zero, s4, s4 +sub zero, s4, s9 +sub zero, s4, t6 +sub zero, s9, zero +sub zero, s9, ra +sub zero, s9, t0 +sub zero, s9, a0 +sub zero, s9, a5 +sub zero, s9, s4 +sub zero, s9, s9 +sub zero, s9, t6 +sub zero, t6, zero +sub zero, t6, ra +sub zero, t6, t0 +sub zero, t6, a0 +sub zero, t6, a5 +sub zero, t6, s4 +sub zero, t6, s9 +sub zero, t6, t6 +sub ra, zero, zero +sub ra, zero, ra +sub ra, zero, t0 +sub ra, zero, a0 +sub ra, zero, a5 +sub ra, zero, s4 +sub ra, zero, s9 +sub ra, zero, t6 +sub ra, ra, zero +sub ra, ra, ra +sub ra, ra, t0 +sub ra, ra, a0 +sub ra, ra, a5 +sub ra, ra, s4 +sub ra, ra, s9 +sub ra, ra, t6 +sub ra, t0, zero +sub ra, t0, ra +sub ra, t0, t0 +sub ra, t0, a0 +sub ra, t0, a5 +sub ra, t0, s4 +sub ra, t0, s9 +sub ra, t0, t6 +sub ra, a0, zero +sub ra, a0, ra +sub ra, a0, t0 +sub ra, a0, a0 +sub ra, a0, a5 +sub ra, a0, s4 +sub ra, a0, s9 +sub ra, a0, t6 +sub ra, a5, zero +sub ra, a5, ra +sub ra, a5, t0 +sub ra, a5, a0 +sub ra, a5, a5 +sub ra, a5, s4 +sub ra, a5, s9 +sub ra, a5, t6 +sub ra, s4, zero +sub ra, s4, ra +sub ra, s4, t0 +sub ra, s4, a0 +sub ra, s4, a5 +sub ra, s4, s4 +sub ra, s4, s9 +sub ra, s4, t6 +sub ra, s9, zero +sub ra, s9, ra +sub ra, s9, t0 +sub ra, s9, a0 +sub ra, s9, a5 +sub ra, s9, s4 +sub ra, s9, s9 +sub ra, s9, t6 +sub ra, t6, zero +sub ra, t6, ra +sub ra, t6, t0 +sub ra, t6, a0 +sub ra, t6, a5 +sub ra, t6, s4 +sub ra, t6, s9 +sub ra, t6, t6 +sub t0, zero, zero +sub t0, zero, ra +sub t0, zero, t0 +sub t0, zero, a0 +sub t0, zero, a5 +sub t0, zero, s4 +sub t0, zero, s9 +sub t0, zero, t6 +sub t0, ra, zero +sub t0, ra, ra +sub t0, ra, t0 +sub t0, ra, a0 +sub t0, ra, a5 +sub t0, ra, s4 +sub t0, ra, s9 +sub t0, ra, t6 +sub t0, t0, zero +sub t0, t0, ra +sub t0, t0, t0 +sub t0, t0, a0 +sub t0, t0, a5 +sub t0, t0, s4 +sub t0, t0, s9 +sub t0, t0, t6 +sub t0, a0, zero +sub t0, a0, ra +sub t0, a0, t0 +sub t0, a0, a0 +sub t0, a0, a5 +sub t0, a0, s4 +sub t0, a0, s9 +sub t0, a0, t6 +sub t0, a5, zero +sub t0, a5, ra +sub t0, a5, t0 +sub t0, a5, a0 +sub t0, a5, a5 +sub t0, a5, s4 +sub t0, a5, s9 +sub t0, a5, t6 +sub t0, s4, zero +sub t0, s4, ra +sub t0, s4, t0 +sub t0, s4, a0 +sub t0, s4, a5 +sub t0, s4, s4 +sub t0, s4, s9 +sub t0, s4, t6 +sub t0, s9, zero +sub t0, s9, ra +sub t0, s9, t0 +sub t0, s9, a0 +sub t0, s9, a5 +sub t0, s9, s4 +sub t0, s9, s9 +sub t0, s9, t6 +sub t0, t6, zero +sub t0, t6, ra +sub t0, t6, t0 +sub t0, t6, a0 +sub t0, t6, a5 +sub t0, t6, s4 +sub t0, t6, s9 +sub t0, t6, t6 +sub a0, zero, zero +sub a0, zero, ra +sub a0, zero, t0 +sub a0, zero, a0 +sub a0, zero, a5 +sub a0, zero, s4 +sub a0, zero, s9 +sub a0, zero, t6 +sub a0, ra, zero +sub a0, ra, ra +sub a0, ra, t0 +sub a0, ra, a0 +sub a0, ra, a5 +sub a0, ra, s4 +sub a0, ra, s9 +sub a0, ra, t6 +sub a0, t0, zero +sub a0, t0, ra +sub a0, t0, t0 +sub a0, t0, a0 +sub a0, t0, a5 +sub a0, t0, s4 +sub a0, t0, s9 +sub a0, t0, t6 +sub a0, a0, zero +sub a0, a0, ra +sub a0, a0, t0 +sub a0, a0, a0 +sub a0, a0, a5 +sub a0, a0, s4 +sub a0, a0, s9 +sub a0, a0, t6 +sub a0, a5, zero +sub a0, a5, ra +sub a0, a5, t0 +sub a0, a5, a0 +sub a0, a5, a5 +sub a0, a5, s4 +sub a0, a5, s9 +sub a0, a5, t6 +sub a0, s4, zero +sub a0, s4, ra +sub a0, s4, t0 +sub a0, s4, a0 +sub a0, s4, a5 +sub a0, s4, s4 +sub a0, s4, s9 +sub a0, s4, t6 +sub a0, s9, zero +sub a0, s9, ra +sub a0, s9, t0 +sub a0, s9, a0 +sub a0, s9, a5 +sub a0, s9, s4 +sub a0, s9, s9 +sub a0, s9, t6 +sub a0, t6, zero +sub a0, t6, ra +sub a0, t6, t0 +sub a0, t6, a0 +sub a0, t6, a5 +sub a0, t6, s4 +sub a0, t6, s9 +sub a0, t6, t6 +sub a5, zero, zero +sub a5, zero, ra +sub a5, zero, t0 +sub a5, zero, a0 +sub a5, zero, a5 +sub a5, zero, s4 +sub a5, zero, s9 +sub a5, zero, t6 +sub a5, ra, zero +sub a5, ra, ra +sub a5, ra, t0 +sub a5, ra, a0 +sub a5, ra, a5 +sub a5, ra, s4 +sub a5, ra, s9 +sub a5, ra, t6 +sub a5, t0, zero +sub a5, t0, ra +sub a5, t0, t0 +sub a5, t0, a0 +sub a5, t0, a5 +sub a5, t0, s4 +sub a5, t0, s9 +sub a5, t0, t6 +sub a5, a0, zero +sub a5, a0, ra +sub a5, a0, t0 +sub a5, a0, a0 +sub a5, a0, a5 +sub a5, a0, s4 +sub a5, a0, s9 +sub a5, a0, t6 +sub a5, a5, zero +sub a5, a5, ra +sub a5, a5, t0 +sub a5, a5, a0 +sub a5, a5, a5 +sub a5, a5, s4 +sub a5, a5, s9 +sub a5, a5, t6 +sub a5, s4, zero +sub a5, s4, ra +sub a5, s4, t0 +sub a5, s4, a0 +sub a5, s4, a5 +sub a5, s4, s4 +sub a5, s4, s9 +sub a5, s4, t6 +sub a5, s9, zero +sub a5, s9, ra +sub a5, s9, t0 +sub a5, s9, a0 +sub a5, s9, a5 +sub a5, s9, s4 +sub a5, s9, s9 +sub a5, s9, t6 +sub a5, t6, zero +sub a5, t6, ra +sub a5, t6, t0 +sub a5, t6, a0 +sub a5, t6, a5 +sub a5, t6, s4 +sub a5, t6, s9 +sub a5, t6, t6 +sub s4, zero, zero +sub s4, zero, ra +sub s4, zero, t0 +sub s4, zero, a0 +sub s4, zero, a5 +sub s4, zero, s4 +sub s4, zero, s9 +sub s4, zero, t6 +sub s4, ra, zero +sub s4, ra, ra +sub s4, ra, t0 +sub s4, ra, a0 +sub s4, ra, a5 +sub s4, ra, s4 +sub s4, ra, s9 +sub s4, ra, t6 +sub s4, t0, zero +sub s4, t0, ra +sub s4, t0, t0 +sub s4, t0, a0 +sub s4, t0, a5 +sub s4, t0, s4 +sub s4, t0, s9 +sub s4, t0, t6 +sub s4, a0, zero +sub s4, a0, ra +sub s4, a0, t0 +sub s4, a0, a0 +sub s4, a0, a5 +sub s4, a0, s4 +sub s4, a0, s9 +sub s4, a0, t6 +sub s4, a5, zero +sub s4, a5, ra +sub s4, a5, t0 +sub s4, a5, a0 +sub s4, a5, a5 +sub s4, a5, s4 +sub s4, a5, s9 +sub s4, a5, t6 +sub s4, s4, zero +sub s4, s4, ra +sub s4, s4, t0 +sub s4, s4, a0 +sub s4, s4, a5 +sub s4, s4, s4 +sub s4, s4, s9 +sub s4, s4, t6 +sub s4, s9, zero +sub s4, s9, ra +sub s4, s9, t0 +sub s4, s9, a0 +sub s4, s9, a5 +sub s4, s9, s4 +sub s4, s9, s9 +sub s4, s9, t6 +sub s4, t6, zero +sub s4, t6, ra +sub s4, t6, t0 +sub s4, t6, a0 +sub s4, t6, a5 +sub s4, t6, s4 +sub s4, t6, s9 +sub s4, t6, t6 +sub s9, zero, zero +sub s9, zero, ra +sub s9, zero, t0 +sub s9, zero, a0 +sub s9, zero, a5 +sub s9, zero, s4 +sub s9, zero, s9 +sub s9, zero, t6 +sub s9, ra, zero +sub s9, ra, ra +sub s9, ra, t0 +sub s9, ra, a0 +sub s9, ra, a5 +sub s9, ra, s4 +sub s9, ra, s9 +sub s9, ra, t6 +sub s9, t0, zero +sub s9, t0, ra +sub s9, t0, t0 +sub s9, t0, a0 +sub s9, t0, a5 +sub s9, t0, s4 +sub s9, t0, s9 +sub s9, t0, t6 +sub s9, a0, zero +sub s9, a0, ra +sub s9, a0, t0 +sub s9, a0, a0 +sub s9, a0, a5 +sub s9, a0, s4 +sub s9, a0, s9 +sub s9, a0, t6 +sub s9, a5, zero +sub s9, a5, ra +sub s9, a5, t0 +sub s9, a5, a0 +sub s9, a5, a5 +sub s9, a5, s4 +sub s9, a5, s9 +sub s9, a5, t6 +sub s9, s4, zero +sub s9, s4, ra +sub s9, s4, t0 +sub s9, s4, a0 +sub s9, s4, a5 +sub s9, s4, s4 +sub s9, s4, s9 +sub s9, s4, t6 +sub s9, s9, zero +sub s9, s9, ra +sub s9, s9, t0 +sub s9, s9, a0 +sub s9, s9, a5 +sub s9, s9, s4 +sub s9, s9, s9 +sub s9, s9, t6 +sub s9, t6, zero +sub s9, t6, ra +sub s9, t6, t0 +sub s9, t6, a0 +sub s9, t6, a5 +sub s9, t6, s4 +sub s9, t6, s9 +sub s9, t6, t6 +sub t6, zero, zero +sub t6, zero, ra +sub t6, zero, t0 +sub t6, zero, a0 +sub t6, zero, a5 +sub t6, zero, s4 +sub t6, zero, s9 +sub t6, zero, t6 +sub t6, ra, zero +sub t6, ra, ra +sub t6, ra, t0 +sub t6, ra, a0 +sub t6, ra, a5 +sub t6, ra, s4 +sub t6, ra, s9 +sub t6, ra, t6 +sub t6, t0, zero +sub t6, t0, ra +sub t6, t0, t0 +sub t6, t0, a0 +sub t6, t0, a5 +sub t6, t0, s4 +sub t6, t0, s9 +sub t6, t0, t6 +sub t6, a0, zero +sub t6, a0, ra +sub t6, a0, t0 +sub t6, a0, a0 +sub t6, a0, a5 +sub t6, a0, s4 +sub t6, a0, s9 +sub t6, a0, t6 +sub t6, a5, zero +sub t6, a5, ra +sub t6, a5, t0 +sub t6, a5, a0 +sub t6, a5, a5 +sub t6, a5, s4 +sub t6, a5, s9 +sub t6, a5, t6 +sub t6, s4, zero +sub t6, s4, ra +sub t6, s4, t0 +sub t6, s4, a0 +sub t6, s4, a5 +sub t6, s4, s4 +sub t6, s4, s9 +sub t6, s4, t6 +sub t6, s9, zero +sub t6, s9, ra +sub t6, s9, t0 +sub t6, s9, a0 +sub t6, s9, a5 +sub t6, s9, s4 +sub t6, s9, s9 +sub t6, s9, t6 +sub t6, t6, zero +sub t6, t6, ra +sub t6, t6, t0 +sub t6, t6, a0 +sub t6, t6, a5 +sub t6, t6, s4 +sub t6, t6, s9 +sub t6, t6, t6 diff --git a/tests/riscv/rv32i/sw.asm b/tests/riscv/rv32i/sw.asm new file mode 100644 index 0000000..88fbc0a --- /dev/null +++ b/tests/riscv/rv32i/sw.asm @@ -0,0 +1,1604 @@ +.lang riscv32 +.org 0x0 + +sw zero, (#-2047, zero) +sw zero, (#-1024, zero) +sw zero, (#-512, zero) +sw zero, (#-256, zero) +sw zero, (#-128, zero) +sw zero, (#-64, zero) +sw zero, (#-32, zero) +sw zero, (#-16, zero) +sw zero, (#-8, zero) +sw zero, (#-4, zero) +sw zero, (#-2, zero) +sw zero, (#-1, zero) +sw zero, (#0, zero) +sw zero, (#1, zero) +sw zero, (#2, zero) +sw zero, (#4, zero) +sw zero, (#8, zero) +sw zero, (#16, zero) +sw zero, (#32, zero) +sw zero, (#64, zero) +sw zero, (#128, zero) +sw zero, (#256, zero) +sw zero, (#512, zero) +sw zero, (#1024, zero) +sw zero, (#2047, zero) +sw zero, (#-2047, ra) +sw zero, (#-1024, ra) +sw zero, (#-512, ra) +sw zero, (#-256, ra) +sw zero, (#-128, ra) +sw zero, (#-64, ra) +sw zero, (#-32, ra) +sw zero, (#-16, ra) +sw zero, (#-8, ra) +sw zero, (#-4, ra) +sw zero, (#-2, ra) +sw zero, (#-1, ra) +sw zero, (#0, ra) +sw zero, (#1, ra) +sw zero, (#2, ra) +sw zero, (#4, ra) +sw zero, (#8, ra) +sw zero, (#16, ra) +sw zero, (#32, ra) +sw zero, (#64, ra) +sw zero, (#128, ra) +sw zero, (#256, ra) +sw zero, (#512, ra) +sw zero, (#1024, ra) +sw zero, (#2047, ra) +sw zero, (#-2047, t0) +sw zero, (#-1024, t0) +sw zero, (#-512, t0) +sw zero, (#-256, t0) +sw zero, (#-128, t0) +sw zero, (#-64, t0) +sw zero, (#-32, t0) +sw zero, (#-16, t0) +sw zero, (#-8, t0) +sw zero, (#-4, t0) +sw zero, (#-2, t0) +sw zero, (#-1, t0) +sw zero, (#0, t0) +sw zero, (#1, t0) +sw zero, (#2, t0) +sw zero, (#4, t0) +sw zero, (#8, t0) +sw zero, (#16, t0) +sw zero, (#32, t0) +sw zero, (#64, t0) +sw zero, (#128, t0) +sw zero, (#256, t0) +sw zero, (#512, t0) +sw zero, (#1024, t0) +sw zero, (#2047, t0) +sw zero, (#-2047, a0) +sw zero, (#-1024, a0) +sw zero, (#-512, a0) +sw zero, (#-256, a0) +sw zero, (#-128, a0) +sw zero, (#-64, a0) +sw zero, (#-32, a0) +sw zero, (#-16, a0) +sw zero, (#-8, a0) +sw zero, (#-4, a0) +sw zero, (#-2, a0) +sw zero, (#-1, a0) +sw zero, (#0, a0) +sw zero, (#1, a0) +sw zero, (#2, a0) +sw zero, (#4, a0) +sw zero, (#8, a0) +sw zero, (#16, a0) +sw zero, (#32, a0) +sw zero, (#64, a0) +sw zero, (#128, a0) +sw zero, (#256, a0) +sw zero, (#512, a0) +sw zero, (#1024, a0) +sw zero, (#2047, a0) +sw zero, (#-2047, a5) +sw zero, (#-1024, a5) +sw zero, (#-512, a5) +sw zero, (#-256, a5) +sw zero, (#-128, a5) +sw zero, (#-64, a5) +sw zero, (#-32, a5) +sw zero, (#-16, a5) +sw zero, (#-8, a5) +sw zero, (#-4, a5) +sw zero, (#-2, a5) +sw zero, (#-1, a5) +sw zero, (#0, a5) +sw zero, (#1, a5) +sw zero, (#2, a5) +sw zero, (#4, a5) +sw zero, (#8, a5) +sw zero, (#16, a5) +sw zero, (#32, a5) +sw zero, (#64, a5) +sw zero, (#128, a5) +sw zero, (#256, a5) +sw zero, (#512, a5) +sw zero, (#1024, a5) +sw zero, (#2047, a5) +sw zero, (#-2047, s4) +sw zero, (#-1024, s4) +sw zero, (#-512, s4) +sw zero, (#-256, s4) +sw zero, (#-128, s4) +sw zero, (#-64, s4) +sw zero, (#-32, s4) +sw zero, (#-16, s4) +sw zero, (#-8, s4) +sw zero, (#-4, s4) +sw zero, (#-2, s4) +sw zero, (#-1, s4) +sw zero, (#0, s4) +sw zero, (#1, s4) +sw zero, (#2, s4) +sw zero, (#4, s4) +sw zero, (#8, s4) +sw zero, (#16, s4) +sw zero, (#32, s4) +sw zero, (#64, s4) +sw zero, (#128, s4) +sw zero, (#256, s4) +sw zero, (#512, s4) +sw zero, (#1024, s4) +sw zero, (#2047, s4) +sw zero, (#-2047, s9) +sw zero, (#-1024, s9) +sw zero, (#-512, s9) +sw zero, (#-256, s9) +sw zero, (#-128, s9) +sw zero, (#-64, s9) +sw zero, (#-32, s9) +sw zero, (#-16, s9) +sw zero, (#-8, s9) +sw zero, (#-4, s9) +sw zero, (#-2, s9) +sw zero, (#-1, s9) +sw zero, (#0, s9) +sw zero, (#1, s9) +sw zero, (#2, s9) +sw zero, (#4, s9) +sw zero, (#8, s9) +sw zero, (#16, s9) +sw zero, (#32, s9) +sw zero, (#64, s9) +sw zero, (#128, s9) +sw zero, (#256, s9) +sw zero, (#512, s9) +sw zero, (#1024, s9) +sw zero, (#2047, s9) +sw zero, (#-2047, t6) +sw zero, (#-1024, t6) +sw zero, (#-512, t6) +sw zero, (#-256, t6) +sw zero, (#-128, t6) +sw zero, (#-64, t6) +sw zero, (#-32, t6) +sw zero, (#-16, t6) +sw zero, (#-8, t6) +sw zero, (#-4, t6) +sw zero, (#-2, t6) +sw zero, (#-1, t6) +sw zero, (#0, t6) +sw zero, (#1, t6) +sw zero, (#2, t6) +sw zero, (#4, t6) +sw zero, (#8, t6) +sw zero, (#16, t6) +sw zero, (#32, t6) +sw zero, (#64, t6) +sw zero, (#128, t6) +sw zero, (#256, t6) +sw zero, (#512, t6) +sw zero, (#1024, t6) +sw zero, (#2047, t6) +sw ra, (#-2047, zero) +sw ra, (#-1024, zero) +sw ra, (#-512, zero) +sw ra, (#-256, zero) +sw ra, (#-128, zero) +sw ra, (#-64, zero) +sw ra, (#-32, zero) +sw ra, (#-16, zero) +sw ra, (#-8, zero) +sw ra, (#-4, zero) +sw ra, (#-2, zero) +sw ra, (#-1, zero) +sw ra, (#0, zero) +sw ra, (#1, zero) +sw ra, (#2, zero) +sw ra, (#4, zero) +sw ra, (#8, zero) +sw ra, (#16, zero) +sw ra, (#32, zero) +sw ra, (#64, zero) +sw ra, (#128, zero) +sw ra, (#256, zero) +sw ra, (#512, zero) +sw ra, (#1024, zero) +sw ra, (#2047, zero) +sw ra, (#-2047, ra) +sw ra, (#-1024, ra) +sw ra, (#-512, ra) +sw ra, (#-256, ra) +sw ra, (#-128, ra) +sw ra, (#-64, ra) +sw ra, (#-32, ra) +sw ra, (#-16, ra) +sw ra, (#-8, ra) +sw ra, (#-4, ra) +sw ra, (#-2, ra) +sw ra, (#-1, ra) +sw ra, (#0, ra) +sw ra, (#1, ra) +sw ra, (#2, ra) +sw ra, (#4, ra) +sw ra, (#8, ra) +sw ra, (#16, ra) +sw ra, (#32, ra) +sw ra, (#64, ra) +sw ra, (#128, ra) +sw ra, (#256, ra) +sw ra, (#512, ra) +sw ra, (#1024, ra) +sw ra, (#2047, ra) +sw ra, (#-2047, t0) +sw ra, (#-1024, t0) +sw ra, (#-512, t0) +sw ra, (#-256, t0) +sw ra, (#-128, t0) +sw ra, (#-64, t0) +sw ra, (#-32, t0) +sw ra, (#-16, t0) +sw ra, (#-8, t0) +sw ra, (#-4, t0) +sw ra, (#-2, t0) +sw ra, (#-1, t0) +sw ra, (#0, t0) +sw ra, (#1, t0) +sw ra, (#2, t0) +sw ra, (#4, t0) +sw ra, (#8, t0) +sw ra, (#16, t0) +sw ra, (#32, t0) +sw ra, (#64, t0) +sw ra, (#128, t0) +sw ra, (#256, t0) +sw ra, (#512, t0) +sw ra, (#1024, t0) +sw ra, (#2047, t0) +sw ra, (#-2047, a0) +sw ra, (#-1024, a0) +sw ra, (#-512, a0) +sw ra, (#-256, a0) +sw ra, (#-128, a0) +sw ra, (#-64, a0) +sw ra, (#-32, a0) +sw ra, (#-16, a0) +sw ra, (#-8, a0) +sw ra, (#-4, a0) +sw ra, (#-2, a0) +sw ra, (#-1, a0) +sw ra, (#0, a0) +sw ra, (#1, a0) +sw ra, (#2, a0) +sw ra, (#4, a0) +sw ra, (#8, a0) +sw ra, (#16, a0) +sw ra, (#32, a0) +sw ra, (#64, a0) +sw ra, (#128, a0) +sw ra, (#256, a0) +sw ra, (#512, a0) +sw ra, (#1024, a0) +sw ra, (#2047, a0) +sw ra, (#-2047, a5) +sw ra, (#-1024, a5) +sw ra, (#-512, a5) +sw ra, (#-256, a5) +sw ra, (#-128, a5) +sw ra, (#-64, a5) +sw ra, (#-32, a5) +sw ra, (#-16, a5) +sw ra, (#-8, a5) +sw ra, (#-4, a5) +sw ra, (#-2, a5) +sw ra, (#-1, a5) +sw ra, (#0, a5) +sw ra, (#1, a5) +sw ra, (#2, a5) +sw ra, (#4, a5) +sw ra, (#8, a5) +sw ra, (#16, a5) +sw ra, (#32, a5) +sw ra, (#64, a5) +sw ra, (#128, a5) +sw ra, (#256, a5) +sw ra, (#512, a5) +sw ra, (#1024, a5) +sw ra, (#2047, a5) +sw ra, (#-2047, s4) +sw ra, (#-1024, s4) +sw ra, (#-512, s4) +sw ra, (#-256, s4) +sw ra, (#-128, s4) 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+sw t6, (#8, a0) +sw t6, (#16, a0) +sw t6, (#32, a0) +sw t6, (#64, a0) +sw t6, (#128, a0) +sw t6, (#256, a0) +sw t6, (#512, a0) +sw t6, (#1024, a0) +sw t6, (#2047, a0) +sw t6, (#-2047, a5) +sw t6, (#-1024, a5) +sw t6, (#-512, a5) +sw t6, (#-256, a5) +sw t6, (#-128, a5) +sw t6, (#-64, a5) +sw t6, (#-32, a5) +sw t6, (#-16, a5) +sw t6, (#-8, a5) +sw t6, (#-4, a5) +sw t6, (#-2, a5) +sw t6, (#-1, a5) +sw t6, (#0, a5) +sw t6, (#1, a5) +sw t6, (#2, a5) +sw t6, (#4, a5) +sw t6, (#8, a5) +sw t6, (#16, a5) +sw t6, (#32, a5) +sw t6, (#64, a5) +sw t6, (#128, a5) +sw t6, (#256, a5) +sw t6, (#512, a5) +sw t6, (#1024, a5) +sw t6, (#2047, a5) +sw t6, (#-2047, s4) +sw t6, (#-1024, s4) +sw t6, (#-512, s4) +sw t6, (#-256, s4) +sw t6, (#-128, s4) +sw t6, (#-64, s4) +sw t6, (#-32, s4) +sw t6, (#-16, s4) +sw t6, (#-8, s4) +sw t6, (#-4, s4) +sw t6, (#-2, s4) +sw t6, (#-1, s4) +sw t6, (#0, s4) +sw t6, (#1, s4) +sw t6, (#2, s4) +sw t6, (#4, s4) +sw t6, (#8, s4) +sw t6, (#16, s4) +sw t6, (#32, s4) +sw t6, (#64, s4) +sw t6, (#128, s4) +sw t6, (#256, s4) +sw t6, (#512, s4) +sw t6, (#1024, s4) +sw t6, (#2047, s4) +sw t6, (#-2047, s9) +sw t6, (#-1024, s9) +sw t6, (#-512, s9) +sw t6, (#-256, s9) +sw t6, (#-128, s9) +sw t6, (#-64, s9) +sw t6, (#-32, s9) +sw t6, (#-16, s9) +sw t6, (#-8, s9) +sw t6, (#-4, s9) +sw t6, (#-2, s9) +sw t6, (#-1, s9) +sw t6, (#0, s9) +sw t6, (#1, s9) +sw t6, (#2, s9) +sw t6, (#4, s9) +sw t6, (#8, s9) +sw t6, (#16, s9) +sw t6, (#32, s9) +sw t6, (#64, s9) +sw t6, (#128, s9) +sw t6, (#256, s9) +sw t6, (#512, s9) +sw t6, (#1024, s9) +sw t6, (#2047, s9) +sw t6, (#-2047, t6) +sw t6, (#-1024, t6) +sw t6, (#-512, t6) +sw t6, (#-256, t6) +sw t6, (#-128, t6) +sw t6, (#-64, t6) +sw t6, (#-32, t6) +sw t6, (#-16, t6) +sw t6, (#-8, t6) +sw t6, (#-4, t6) +sw t6, (#-2, t6) +sw t6, (#-1, t6) +sw t6, (#0, t6) +sw t6, (#1, t6) +sw t6, (#2, t6) +sw t6, (#4, t6) +sw t6, (#8, t6) +sw t6, (#16, t6) +sw t6, (#32, t6) +sw t6, (#64, t6) +sw t6, (#128, t6) +sw t6, (#256, t6) +sw t6, (#512, t6) +sw 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zy91t;eysYj>c^@dtA4EdvFgXFA8Xf`!5fVD1pQd`W7UsUKUV!%^<(XNGmow6N7avd zI$#g|sQOX$qv}W1kE$P4KdOGzQ)32iG2t`xqv}W1kE$P4KdOGzQ*Y+6t@^Q^cO0;X zeysYj>c^@dtA4EdvFgXFAM3d>gLjzm1^Th-$EqKzeysYj>c^@dtA14dsFxiF?4ci3 zKdOFI{iym;^`q)X)sK2<%-}s1e1(2g{iym;^`q)X)sLzlRX?hJRQ;&>QT3zhN7aw2 tA5}l9epLOa`cd_x>POX&svlK9s(w`csQOX$qv}W1kE$P4KkD=2{{a@Fea8R* literal 0 HcmV?d00001 diff --git a/tests/riscv/rv32i/xori.disasm b/tests/riscv/rv32i/xori.disasm new file mode 100644 index 0000000..bf17f0a --- /dev/null +++ b/tests/riscv/rv32i/xori.disasm @@ -0,0 +1,1600 @@ +xori zero, zero, #0xfffff801 +xori zero, zero, #0xfffffc00 +xori zero, zero, #0xfffffe00 +xori zero, zero, #0xffffff00 +xori zero, zero, #0xffffff80 +xori zero, zero, #0xffffffc0 +xori zero, zero, #0xffffffe0 +xori zero, zero, #0xfffffff0 +xori zero, zero, #0xfffffff8 +xori zero, zero, #0xfffffffc +xori zero, zero, #0xfffffffe +xori zero, zero, #0xffffffff +xori zero, zero, #0 +xori zero, zero, #1 +xori zero, zero, #2 +xori zero, zero, #4 +xori zero, zero, #8 +xori zero, zero, #0x10 +xori zero, zero, #0x20 +xori zero, zero, #0x40 +xori zero, zero, #0x80 +xori zero, zero, #0x100 +xori zero, zero, #0x200 +xori zero, zero, #0x400 +xori zero, zero, #0x7ff +xori zero, ra, #0xfffff801 +xori zero, ra, #0xfffffc00 +xori zero, ra, #0xfffffe00 +xori zero, ra, #0xffffff00 +xori zero, ra, #0xffffff80 +xori zero, ra, #0xffffffc0 +xori zero, ra, #0xffffffe0 +xori zero, ra, #0xfffffff0 +xori zero, ra, #0xfffffff8 +xori zero, ra, #0xfffffffc +xori zero, ra, #0xfffffffe +xori zero, ra, #0xffffffff +xori zero, ra, #0 +xori zero, ra, #1 +xori zero, ra, #2 +xori zero, ra, #4 +xori zero, ra, #8 +xori zero, ra, #0x10 +xori zero, ra, #0x20 +xori zero, ra, #0x40 +xori zero, ra, #0x80 +xori zero, ra, #0x100 +xori zero, ra, #0x200 +xori zero, ra, #0x400 +xori zero, ra, #0x7ff +xori zero, t0, #0xfffff801 +xori zero, t0, #0xfffffc00 +xori zero, t0, #0xfffffe00 +xori zero, t0, #0xffffff00 +xori zero, t0, #0xffffff80 +xori zero, t0, #0xffffffc0 +xori zero, t0, #0xffffffe0 +xori zero, t0, #0xfffffff0 +xori zero, t0, #0xfffffff8 +xori zero, t0, #0xfffffffc +xori zero, t0, #0xfffffffe +xori zero, t0, #0xffffffff +xori zero, t0, #0 +xori zero, t0, #1 +xori zero, t0, #2 +xori zero, t0, #4 +xori zero, t0, #8 +xori zero, t0, #0x10 +xori zero, t0, #0x20 +xori zero, t0, #0x40 +xori zero, t0, #0x80 +xori zero, t0, #0x100 +xori zero, t0, #0x200 +xori zero, t0, #0x400 +xori zero, t0, #0x7ff +xori zero, a0, #0xfffff801 +xori zero, a0, #0xfffffc00 +xori zero, a0, #0xfffffe00 +xori zero, a0, #0xffffff00 +xori zero, a0, #0xffffff80 +xori zero, a0, #0xffffffc0 +xori zero, a0, #0xffffffe0 +xori zero, a0, #0xfffffff0 +xori zero, a0, #0xfffffff8 +xori zero, a0, #0xfffffffc +xori zero, a0, #0xfffffffe +xori zero, a0, #0xffffffff +xori zero, a0, #0 +xori zero, a0, #1 +xori zero, a0, #2 +xori zero, a0, #4 +xori zero, a0, #8 +xori zero, a0, #0x10 +xori zero, a0, #0x20 +xori zero, a0, #0x40 +xori zero, a0, #0x80 +xori zero, a0, #0x100 +xori zero, a0, #0x200 +xori zero, a0, #0x400 +xori zero, a0, #0x7ff +xori zero, a5, #0xfffff801 +xori zero, a5, #0xfffffc00 +xori zero, a5, #0xfffffe00 +xori zero, a5, #0xffffff00 +xori zero, a5, #0xffffff80 +xori zero, a5, #0xffffffc0 +xori zero, a5, #0xffffffe0 +xori zero, a5, #0xfffffff0 +xori zero, a5, #0xfffffff8 +xori zero, a5, #0xfffffffc +xori zero, a5, #0xfffffffe +xori zero, a5, #0xffffffff +xori zero, a5, #0 +xori zero, a5, #1 +xori zero, a5, #2 +xori zero, a5, #4 +xori zero, a5, #8 +xori zero, a5, #0x10 +xori zero, a5, #0x20 +xori zero, a5, #0x40 +xori zero, a5, #0x80 +xori zero, a5, #0x100 +xori zero, a5, #0x200 +xori zero, a5, #0x400 +xori zero, a5, #0x7ff +xori zero, s4, #0xfffff801 +xori zero, s4, #0xfffffc00 +xori zero, s4, #0xfffffe00 +xori zero, s4, #0xffffff00 +xori zero, s4, #0xffffff80 +xori zero, s4, #0xffffffc0 +xori zero, s4, #0xffffffe0 +xori zero, s4, #0xfffffff0 +xori zero, s4, #0xfffffff8 +xori zero, s4, #0xfffffffc +xori zero, s4, #0xfffffffe +xori zero, s4, #0xffffffff +xori zero, s4, #0 +xori zero, s4, #1 +xori zero, s4, #2 +xori zero, s4, #4 +xori zero, s4, #8 +xori zero, s4, #0x10 +xori zero, s4, #0x20 +xori zero, s4, #0x40 +xori zero, s4, #0x80 +xori zero, s4, #0x100 +xori zero, s4, #0x200 +xori zero, s4, #0x400 +xori zero, s4, #0x7ff +xori zero, s9, #0xfffff801 +xori zero, s9, #0xfffffc00 +xori zero, s9, #0xfffffe00 +xori zero, s9, #0xffffff00 +xori zero, s9, #0xffffff80 +xori zero, s9, #0xffffffc0 +xori zero, s9, #0xffffffe0 +xori zero, s9, #0xfffffff0 +xori zero, s9, #0xfffffff8 +xori zero, s9, #0xfffffffc +xori zero, s9, #0xfffffffe +xori zero, s9, #0xffffffff +xori zero, s9, #0 +xori zero, s9, #1 +xori zero, s9, #2 +xori zero, s9, #4 +xori zero, s9, #8 +xori zero, s9, #0x10 +xori zero, s9, #0x20 +xori zero, s9, #0x40 +xori zero, s9, #0x80 +xori zero, s9, #0x100 +xori zero, s9, #0x200 +xori zero, s9, #0x400 +xori zero, s9, #0x7ff +xori zero, t6, #0xfffff801 +xori zero, t6, #0xfffffc00 +xori zero, t6, #0xfffffe00 +xori zero, t6, #0xffffff00 +xori zero, t6, #0xffffff80 +xori zero, t6, #0xffffffc0 +xori zero, t6, #0xffffffe0 +xori zero, t6, #0xfffffff0 +xori zero, t6, #0xfffffff8 +xori zero, t6, #0xfffffffc +xori zero, t6, #0xfffffffe +xori zero, t6, #0xffffffff +xori zero, t6, #0 +xori zero, t6, #1 +xori zero, t6, #2 +xori zero, t6, #4 +xori zero, t6, #8 +xori zero, t6, #0x10 +xori zero, t6, #0x20 +xori zero, t6, #0x40 +xori zero, t6, #0x80 +xori zero, t6, #0x100 +xori zero, t6, #0x200 +xori zero, t6, #0x400 +xori zero, t6, #0x7ff +xori ra, zero, #0xfffff801 +xori ra, zero, #0xfffffc00 +xori ra, zero, #0xfffffe00 +xori ra, zero, #0xffffff00 +xori ra, zero, #0xffffff80 +xori ra, zero, #0xffffffc0 +xori ra, zero, #0xffffffe0 +xori ra, zero, #0xfffffff0 +xori ra, zero, #0xfffffff8 +xori ra, zero, #0xfffffffc +xori ra, zero, #0xfffffffe +xori ra, zero, #0xffffffff +xori ra, zero, #0 +xori ra, zero, #1 +xori ra, zero, #2 +xori ra, zero, #4 +xori ra, zero, #8 +xori ra, zero, #0x10 +xori ra, zero, #0x20 +xori ra, zero, #0x40 +xori ra, zero, #0x80 +xori ra, zero, #0x100 +xori ra, zero, #0x200 +xori ra, zero, #0x400 +xori ra, zero, #0x7ff +xori ra, ra, #0xfffff801 +xori ra, ra, #0xfffffc00 +xori ra, ra, #0xfffffe00 +xori ra, ra, #0xffffff00 +xori ra, ra, #0xffffff80 +xori ra, ra, #0xffffffc0 +xori ra, ra, #0xffffffe0 +xori ra, ra, #0xfffffff0 +xori ra, ra, #0xfffffff8 +xori ra, ra, #0xfffffffc +xori ra, ra, #0xfffffffe +xori ra, ra, #0xffffffff +xori ra, ra, #0 +xori ra, ra, #1 +xori ra, ra, #2 +xori ra, ra, #4 +xori ra, ra, #8 +xori ra, ra, #0x10 +xori ra, ra, #0x20 +xori ra, ra, #0x40 +xori ra, ra, #0x80 +xori ra, ra, #0x100 +xori ra, ra, #0x200 +xori ra, ra, #0x400 +xori ra, ra, #0x7ff +xori ra, t0, #0xfffff801 +xori ra, t0, #0xfffffc00 +xori ra, t0, #0xfffffe00 +xori ra, t0, #0xffffff00 +xori ra, t0, #0xffffff80 +xori ra, t0, #0xffffffc0 +xori ra, t0, #0xffffffe0 +xori ra, t0, #0xfffffff0 +xori ra, t0, #0xfffffff8 +xori ra, t0, #0xfffffffc +xori ra, t0, #0xfffffffe +xori ra, t0, #0xffffffff +xori ra, t0, #0 +xori ra, t0, #1 +xori ra, t0, #2 +xori ra, t0, #4 +xori ra, t0, #8 +xori ra, t0, #0x10 +xori ra, t0, #0x20 +xori ra, t0, #0x40 +xori ra, t0, #0x80 +xori ra, t0, #0x100 +xori ra, t0, #0x200 +xori ra, t0, #0x400 +xori ra, t0, #0x7ff +xori ra, a0, #0xfffff801 +xori ra, a0, #0xfffffc00 +xori ra, a0, #0xfffffe00 +xori ra, a0, #0xffffff00 +xori ra, a0, #0xffffff80 +xori ra, a0, #0xffffffc0 +xori ra, a0, #0xffffffe0 +xori ra, a0, #0xfffffff0 +xori ra, a0, #0xfffffff8 +xori ra, a0, #0xfffffffc +xori ra, a0, #0xfffffffe +xori ra, a0, #0xffffffff +xori ra, a0, #0 +xori ra, a0, #1 +xori ra, a0, #2 +xori ra, a0, #4 +xori ra, a0, #8 +xori ra, a0, #0x10 +xori ra, a0, #0x20 +xori ra, a0, #0x40 +xori ra, a0, #0x80 +xori ra, a0, #0x100 +xori ra, a0, #0x200 +xori ra, a0, #0x400 +xori ra, a0, #0x7ff +xori ra, a5, #0xfffff801 +xori ra, a5, #0xfffffc00 +xori ra, a5, #0xfffffe00 +xori ra, a5, #0xffffff00 +xori ra, a5, #0xffffff80 +xori ra, a5, #0xffffffc0 +xori ra, a5, #0xffffffe0 +xori ra, a5, #0xfffffff0 +xori ra, a5, #0xfffffff8 +xori ra, a5, #0xfffffffc +xori ra, a5, #0xfffffffe +xori ra, a5, #0xffffffff +xori ra, a5, #0 +xori ra, a5, #1 +xori ra, a5, #2 +xori ra, a5, #4 +xori ra, a5, #8 +xori ra, a5, #0x10 +xori ra, a5, #0x20 +xori ra, a5, #0x40 +xori ra, a5, #0x80 +xori ra, a5, #0x100 +xori ra, a5, #0x200 +xori ra, a5, #0x400 +xori ra, a5, #0x7ff +xori ra, s4, #0xfffff801 +xori ra, s4, #0xfffffc00 +xori ra, s4, #0xfffffe00 +xori ra, s4, #0xffffff00 +xori ra, s4, #0xffffff80 +xori ra, s4, #0xffffffc0 +xori ra, s4, #0xffffffe0 +xori ra, s4, #0xfffffff0 +xori ra, s4, #0xfffffff8 +xori ra, s4, #0xfffffffc +xori ra, s4, #0xfffffffe +xori ra, s4, #0xffffffff +xori ra, s4, #0 +xori ra, s4, #1 +xori ra, s4, #2 +xori ra, s4, #4 +xori ra, s4, #8 +xori ra, s4, #0x10 +xori ra, s4, #0x20 +xori ra, s4, #0x40 +xori ra, s4, #0x80 +xori ra, s4, #0x100 +xori ra, s4, #0x200 +xori ra, s4, #0x400 +xori ra, s4, #0x7ff +xori ra, s9, #0xfffff801 +xori ra, s9, #0xfffffc00 +xori ra, s9, #0xfffffe00 +xori ra, s9, #0xffffff00 +xori ra, s9, #0xffffff80 +xori ra, s9, #0xffffffc0 +xori ra, s9, #0xffffffe0 +xori ra, s9, #0xfffffff0 +xori ra, s9, #0xfffffff8 +xori ra, s9, #0xfffffffc +xori ra, s9, #0xfffffffe +xori ra, s9, #0xffffffff +xori ra, s9, #0 +xori ra, s9, #1 +xori ra, s9, #2 +xori ra, s9, #4 +xori ra, s9, #8 +xori ra, s9, #0x10 +xori ra, s9, #0x20 +xori ra, s9, #0x40 +xori ra, s9, #0x80 +xori ra, s9, #0x100 +xori ra, s9, #0x200 +xori ra, s9, #0x400 +xori ra, s9, #0x7ff +xori ra, t6, #0xfffff801 +xori ra, t6, #0xfffffc00 +xori ra, t6, #0xfffffe00 +xori ra, t6, #0xffffff00 +xori ra, t6, #0xffffff80 +xori ra, t6, #0xffffffc0 +xori ra, t6, #0xffffffe0 +xori ra, t6, #0xfffffff0 +xori ra, t6, #0xfffffff8 +xori ra, t6, #0xfffffffc +xori ra, t6, #0xfffffffe +xori ra, t6, #0xffffffff +xori ra, t6, #0 +xori ra, t6, #1 +xori ra, t6, #2 +xori ra, t6, #4 +xori ra, t6, #8 +xori ra, t6, #0x10 +xori ra, t6, #0x20 +xori ra, t6, #0x40 +xori ra, t6, #0x80 +xori ra, t6, #0x100 +xori ra, t6, #0x200 +xori ra, t6, #0x400 +xori ra, t6, #0x7ff +xori t0, zero, #0xfffff801 +xori t0, zero, #0xfffffc00 +xori t0, zero, #0xfffffe00 +xori t0, zero, #0xffffff00 +xori t0, zero, #0xffffff80 +xori t0, zero, #0xffffffc0 +xori t0, zero, #0xffffffe0 +xori t0, zero, #0xfffffff0 +xori t0, zero, #0xfffffff8 +xori t0, zero, #0xfffffffc +xori t0, zero, #0xfffffffe +xori t0, zero, #0xffffffff +xori t0, zero, #0 +xori t0, zero, #1 +xori t0, zero, #2 +xori t0, zero, #4 +xori t0, zero, #8 +xori t0, zero, #0x10 +xori t0, zero, #0x20 +xori t0, zero, #0x40 +xori t0, zero, #0x80 +xori t0, zero, #0x100 +xori t0, zero, #0x200 +xori t0, zero, #0x400 +xori t0, zero, #0x7ff +xori t0, ra, #0xfffff801 +xori t0, ra, #0xfffffc00 +xori t0, ra, #0xfffffe00 +xori t0, ra, #0xffffff00 +xori t0, ra, #0xffffff80 +xori t0, ra, #0xffffffc0 +xori t0, ra, #0xffffffe0 +xori t0, ra, #0xfffffff0 +xori t0, ra, #0xfffffff8 +xori t0, ra, #0xfffffffc +xori t0, ra, #0xfffffffe +xori t0, ra, #0xffffffff +xori t0, ra, #0 +xori t0, ra, #1 +xori t0, ra, #2 +xori t0, ra, #4 +xori t0, ra, #8 +xori t0, ra, #0x10 +xori t0, ra, #0x20 +xori t0, ra, #0x40 +xori t0, ra, #0x80 +xori t0, ra, #0x100 +xori t0, ra, #0x200 +xori t0, ra, #0x400 +xori t0, ra, #0x7ff +xori t0, t0, #0xfffff801 +xori t0, t0, #0xfffffc00 +xori t0, t0, #0xfffffe00 +xori t0, t0, #0xffffff00 +xori t0, t0, #0xffffff80 +xori t0, t0, #0xffffffc0 +xori t0, t0, #0xffffffe0 +xori t0, t0, #0xfffffff0 +xori t0, t0, #0xfffffff8 +xori t0, t0, #0xfffffffc +xori t0, t0, #0xfffffffe +xori t0, t0, #0xffffffff +xori t0, t0, #0 +xori t0, t0, #1 +xori t0, t0, #2 +xori t0, t0, #4 +xori t0, t0, #8 +xori t0, t0, #0x10 +xori t0, t0, #0x20 +xori t0, t0, #0x40 +xori t0, t0, #0x80 +xori t0, t0, #0x100 +xori t0, t0, #0x200 +xori t0, t0, #0x400 +xori t0, t0, #0x7ff +xori t0, a0, #0xfffff801 +xori t0, a0, #0xfffffc00 +xori t0, a0, #0xfffffe00 +xori t0, a0, #0xffffff00 +xori t0, a0, #0xffffff80 +xori t0, a0, #0xffffffc0 +xori t0, a0, #0xffffffe0 +xori t0, a0, #0xfffffff0 +xori t0, a0, #0xfffffff8 +xori t0, a0, #0xfffffffc +xori t0, a0, #0xfffffffe +xori t0, a0, #0xffffffff +xori t0, a0, #0 +xori t0, a0, #1 +xori t0, a0, #2 +xori t0, a0, #4 +xori t0, a0, #8 +xori t0, a0, #0x10 +xori t0, a0, #0x20 +xori t0, a0, #0x40 +xori t0, a0, #0x80 +xori t0, a0, #0x100 +xori t0, a0, #0x200 +xori t0, a0, #0x400 +xori t0, a0, #0x7ff +xori t0, a5, #0xfffff801 +xori t0, a5, #0xfffffc00 +xori t0, a5, #0xfffffe00 +xori t0, a5, #0xffffff00 +xori t0, a5, #0xffffff80 +xori t0, a5, #0xffffffc0 +xori t0, a5, #0xffffffe0 +xori t0, a5, #0xfffffff0 +xori t0, a5, #0xfffffff8 +xori t0, a5, #0xfffffffc +xori t0, a5, #0xfffffffe +xori t0, a5, #0xffffffff +xori t0, a5, #0 +xori t0, a5, #1 +xori t0, a5, #2 +xori t0, a5, #4 +xori t0, a5, #8 +xori t0, a5, #0x10 +xori t0, a5, #0x20 +xori t0, a5, #0x40 +xori t0, a5, #0x80 +xori t0, a5, #0x100 +xori t0, a5, #0x200 +xori t0, a5, #0x400 +xori t0, a5, #0x7ff +xori t0, s4, #0xfffff801 +xori t0, s4, #0xfffffc00 +xori t0, s4, #0xfffffe00 +xori t0, s4, #0xffffff00 +xori t0, s4, #0xffffff80 +xori t0, s4, #0xffffffc0 +xori t0, s4, #0xffffffe0 +xori t0, s4, #0xfffffff0 +xori t0, s4, #0xfffffff8 +xori t0, s4, #0xfffffffc +xori t0, s4, #0xfffffffe +xori t0, s4, #0xffffffff +xori t0, s4, #0 +xori t0, s4, #1 +xori t0, s4, #2 +xori t0, s4, #4 +xori t0, s4, #8 +xori t0, s4, #0x10 +xori t0, s4, #0x20 +xori t0, s4, #0x40 +xori t0, s4, #0x80 +xori t0, s4, #0x100 +xori t0, s4, #0x200 +xori t0, s4, #0x400 +xori t0, s4, #0x7ff +xori t0, s9, #0xfffff801 +xori t0, s9, #0xfffffc00 +xori t0, s9, #0xfffffe00 +xori t0, s9, #0xffffff00 +xori t0, s9, #0xffffff80 +xori t0, s9, #0xffffffc0 +xori t0, s9, #0xffffffe0 +xori t0, s9, #0xfffffff0 +xori t0, s9, #0xfffffff8 +xori t0, s9, #0xfffffffc +xori t0, s9, #0xfffffffe +xori t0, s9, #0xffffffff +xori t0, s9, #0 +xori t0, s9, #1 +xori t0, s9, #2 +xori t0, s9, #4 +xori t0, s9, #8 +xori t0, s9, #0x10 +xori t0, s9, #0x20 +xori t0, s9, #0x40 +xori t0, s9, #0x80 +xori t0, s9, #0x100 +xori t0, s9, #0x200 +xori t0, s9, #0x400 +xori t0, s9, #0x7ff +xori t0, t6, #0xfffff801 +xori t0, t6, #0xfffffc00 +xori t0, t6, #0xfffffe00 +xori t0, t6, #0xffffff00 +xori t0, t6, #0xffffff80 +xori t0, t6, #0xffffffc0 +xori t0, t6, #0xffffffe0 +xori t0, t6, #0xfffffff0 +xori t0, t6, #0xfffffff8 +xori t0, t6, #0xfffffffc +xori t0, t6, #0xfffffffe +xori t0, t6, #0xffffffff +xori t0, t6, #0 +xori t0, t6, #1 +xori t0, t6, #2 +xori t0, t6, #4 +xori t0, t6, #8 +xori t0, t6, #0x10 +xori t0, t6, #0x20 +xori t0, t6, #0x40 +xori t0, t6, #0x80 +xori t0, t6, #0x100 +xori t0, t6, #0x200 +xori t0, t6, #0x400 +xori t0, t6, #0x7ff +xori a0, zero, #0xfffff801 +xori a0, zero, #0xfffffc00 +xori a0, zero, #0xfffffe00 +xori a0, zero, #0xffffff00 +xori a0, zero, #0xffffff80 +xori a0, zero, #0xffffffc0 +xori a0, zero, #0xffffffe0 +xori a0, zero, #0xfffffff0 +xori a0, zero, #0xfffffff8 +xori a0, zero, #0xfffffffc +xori a0, zero, #0xfffffffe +xori a0, zero, #0xffffffff +xori a0, zero, #0 +xori a0, zero, #1 +xori a0, zero, #2 +xori a0, zero, #4 +xori a0, zero, #8 +xori a0, zero, #0x10 +xori a0, zero, #0x20 +xori a0, zero, #0x40 +xori a0, zero, #0x80 +xori a0, zero, #0x100 +xori a0, zero, #0x200 +xori a0, zero, #0x400 +xori a0, zero, #0x7ff +xori a0, ra, #0xfffff801 +xori a0, ra, #0xfffffc00 +xori a0, ra, #0xfffffe00 +xori a0, ra, #0xffffff00 +xori a0, ra, #0xffffff80 +xori a0, ra, #0xffffffc0 +xori a0, ra, #0xffffffe0 +xori a0, ra, #0xfffffff0 +xori a0, ra, #0xfffffff8 +xori a0, ra, #0xfffffffc +xori a0, ra, #0xfffffffe +xori a0, ra, #0xffffffff +xori a0, ra, #0 +xori a0, ra, #1 +xori a0, ra, #2 +xori a0, ra, #4 +xori a0, ra, #8 +xori a0, ra, #0x10 +xori a0, ra, #0x20 +xori a0, ra, #0x40 +xori a0, ra, #0x80 +xori a0, ra, #0x100 +xori a0, ra, #0x200 +xori a0, ra, #0x400 +xori a0, ra, #0x7ff +xori a0, t0, #0xfffff801 +xori a0, t0, #0xfffffc00 +xori a0, t0, #0xfffffe00 +xori a0, t0, #0xffffff00 +xori a0, t0, #0xffffff80 +xori a0, t0, #0xffffffc0 +xori a0, t0, #0xffffffe0 +xori a0, t0, #0xfffffff0 +xori a0, t0, #0xfffffff8 +xori a0, t0, #0xfffffffc +xori a0, t0, #0xfffffffe +xori a0, t0, #0xffffffff +xori a0, t0, #0 +xori a0, t0, #1 +xori a0, t0, #2 +xori a0, t0, #4 +xori a0, t0, #8 +xori a0, t0, #0x10 +xori a0, t0, #0x20 +xori a0, t0, #0x40 +xori a0, t0, #0x80 +xori a0, t0, #0x100 +xori a0, t0, #0x200 +xori a0, t0, #0x400 +xori a0, t0, #0x7ff +xori a0, a0, #0xfffff801 +xori a0, a0, #0xfffffc00 +xori a0, a0, #0xfffffe00 +xori a0, a0, #0xffffff00 +xori a0, a0, #0xffffff80 +xori a0, a0, #0xffffffc0 +xori a0, a0, #0xffffffe0 +xori a0, a0, #0xfffffff0 +xori a0, a0, #0xfffffff8 +xori a0, a0, #0xfffffffc +xori a0, a0, #0xfffffffe +xori a0, a0, #0xffffffff +xori a0, a0, #0 +xori a0, a0, #1 +xori a0, a0, #2 +xori a0, a0, #4 +xori a0, a0, #8 +xori a0, a0, #0x10 +xori a0, a0, #0x20 +xori a0, a0, #0x40 +xori a0, a0, #0x80 +xori a0, a0, #0x100 +xori a0, a0, #0x200 +xori a0, a0, #0x400 +xori a0, a0, #0x7ff +xori a0, a5, #0xfffff801 +xori a0, a5, #0xfffffc00 +xori a0, a5, #0xfffffe00 +xori a0, a5, #0xffffff00 +xori a0, a5, #0xffffff80 +xori a0, a5, #0xffffffc0 +xori a0, a5, #0xffffffe0 +xori a0, a5, #0xfffffff0 +xori a0, a5, #0xfffffff8 +xori a0, a5, #0xfffffffc +xori a0, a5, #0xfffffffe +xori a0, a5, #0xffffffff +xori a0, a5, #0 +xori a0, a5, #1 +xori a0, a5, #2 +xori a0, a5, #4 +xori a0, a5, #8 +xori a0, a5, #0x10 +xori a0, a5, #0x20 +xori a0, a5, #0x40 +xori a0, a5, #0x80 +xori a0, a5, #0x100 +xori a0, a5, #0x200 +xori a0, a5, #0x400 +xori a0, a5, #0x7ff +xori a0, s4, #0xfffff801 +xori a0, s4, #0xfffffc00 +xori a0, s4, #0xfffffe00 +xori a0, s4, #0xffffff00 +xori a0, s4, #0xffffff80 +xori a0, s4, #0xffffffc0 +xori a0, s4, #0xffffffe0 +xori a0, s4, #0xfffffff0 +xori a0, s4, #0xfffffff8 +xori a0, s4, #0xfffffffc +xori a0, s4, #0xfffffffe +xori a0, s4, #0xffffffff +xori a0, s4, #0 +xori a0, s4, #1 +xori a0, s4, #2 +xori a0, s4, #4 +xori a0, s4, #8 +xori a0, s4, #0x10 +xori a0, s4, #0x20 +xori a0, s4, #0x40 +xori a0, s4, #0x80 +xori a0, s4, #0x100 +xori a0, s4, #0x200 +xori a0, s4, #0x400 +xori a0, s4, #0x7ff +xori a0, s9, #0xfffff801 +xori a0, s9, #0xfffffc00 +xori a0, s9, #0xfffffe00 +xori a0, s9, #0xffffff00 +xori a0, s9, #0xffffff80 +xori a0, s9, #0xffffffc0 +xori a0, s9, #0xffffffe0 +xori a0, s9, #0xfffffff0 +xori a0, s9, #0xfffffff8 +xori a0, s9, #0xfffffffc +xori a0, s9, #0xfffffffe +xori a0, s9, #0xffffffff +xori a0, s9, #0 +xori a0, s9, #1 +xori a0, s9, #2 +xori a0, s9, #4 +xori a0, s9, #8 +xori a0, s9, #0x10 +xori a0, s9, #0x20 +xori a0, s9, #0x40 +xori a0, s9, #0x80 +xori a0, s9, #0x100 +xori a0, s9, #0x200 +xori a0, s9, #0x400 +xori a0, s9, #0x7ff +xori a0, t6, #0xfffff801 +xori a0, t6, #0xfffffc00 +xori a0, t6, #0xfffffe00 +xori a0, t6, #0xffffff00 +xori a0, t6, #0xffffff80 +xori a0, t6, #0xffffffc0 +xori a0, t6, #0xffffffe0 +xori a0, t6, #0xfffffff0 +xori a0, t6, #0xfffffff8 +xori a0, t6, #0xfffffffc +xori a0, t6, #0xfffffffe +xori a0, t6, #0xffffffff +xori a0, t6, #0 +xori a0, t6, #1 +xori a0, t6, #2 +xori a0, t6, #4 +xori a0, t6, #8 +xori a0, t6, #0x10 +xori a0, t6, #0x20 +xori a0, t6, #0x40 +xori a0, t6, #0x80 +xori a0, t6, #0x100 +xori a0, t6, #0x200 +xori a0, t6, #0x400 +xori a0, t6, #0x7ff +xori a5, zero, #0xfffff801 +xori a5, zero, #0xfffffc00 +xori a5, zero, #0xfffffe00 +xori a5, zero, #0xffffff00 +xori a5, zero, #0xffffff80 +xori a5, zero, #0xffffffc0 +xori a5, zero, #0xffffffe0 +xori a5, zero, #0xfffffff0 +xori a5, zero, #0xfffffff8 +xori a5, zero, #0xfffffffc +xori a5, zero, #0xfffffffe +xori a5, zero, #0xffffffff +xori a5, zero, #0 +xori a5, zero, #1 +xori a5, zero, #2 +xori a5, zero, #4 +xori a5, zero, #8 +xori a5, zero, #0x10 +xori a5, zero, #0x20 +xori a5, zero, #0x40 +xori a5, zero, #0x80 +xori a5, zero, #0x100 +xori a5, zero, #0x200 +xori a5, zero, #0x400 +xori a5, zero, #0x7ff +xori a5, ra, #0xfffff801 +xori a5, ra, #0xfffffc00 +xori a5, ra, #0xfffffe00 +xori a5, ra, #0xffffff00 +xori a5, ra, #0xffffff80 +xori a5, ra, #0xffffffc0 +xori a5, ra, #0xffffffe0 +xori a5, ra, #0xfffffff0 +xori a5, ra, #0xfffffff8 +xori a5, ra, #0xfffffffc +xori a5, ra, #0xfffffffe +xori a5, ra, #0xffffffff +xori a5, ra, #0 +xori a5, ra, #1 +xori a5, ra, #2 +xori a5, ra, #4 +xori a5, ra, #8 +xori a5, ra, #0x10 +xori a5, ra, #0x20 +xori a5, ra, #0x40 +xori a5, ra, #0x80 +xori a5, ra, #0x100 +xori a5, ra, #0x200 +xori a5, ra, #0x400 +xori a5, ra, #0x7ff +xori a5, t0, #0xfffff801 +xori a5, t0, #0xfffffc00 +xori a5, t0, #0xfffffe00 +xori a5, t0, #0xffffff00 +xori a5, t0, #0xffffff80 +xori a5, t0, #0xffffffc0 +xori a5, t0, #0xffffffe0 +xori a5, t0, #0xfffffff0 +xori a5, t0, #0xfffffff8 +xori a5, t0, #0xfffffffc +xori a5, t0, #0xfffffffe +xori a5, t0, #0xffffffff +xori a5, t0, #0 +xori a5, t0, #1 +xori a5, t0, #2 +xori a5, t0, #4 +xori a5, t0, #8 +xori a5, t0, #0x10 +xori a5, t0, #0x20 +xori a5, t0, #0x40 +xori a5, t0, #0x80 +xori a5, t0, #0x100 +xori a5, t0, #0x200 +xori a5, t0, #0x400 +xori a5, t0, #0x7ff +xori a5, a0, #0xfffff801 +xori a5, a0, #0xfffffc00 +xori a5, a0, #0xfffffe00 +xori a5, a0, #0xffffff00 +xori a5, a0, #0xffffff80 +xori a5, a0, #0xffffffc0 +xori a5, a0, #0xffffffe0 +xori a5, a0, #0xfffffff0 +xori a5, a0, #0xfffffff8 +xori a5, a0, #0xfffffffc +xori a5, a0, #0xfffffffe +xori a5, a0, #0xffffffff +xori a5, a0, #0 +xori a5, a0, #1 +xori a5, a0, #2 +xori a5, a0, #4 +xori a5, a0, #8 +xori a5, a0, #0x10 +xori a5, a0, #0x20 +xori a5, a0, #0x40 +xori a5, a0, #0x80 +xori a5, a0, #0x100 +xori a5, a0, #0x200 +xori a5, a0, #0x400 +xori a5, a0, #0x7ff +xori a5, a5, #0xfffff801 +xori a5, a5, #0xfffffc00 +xori a5, a5, #0xfffffe00 +xori a5, a5, #0xffffff00 +xori a5, a5, #0xffffff80 +xori a5, a5, #0xffffffc0 +xori a5, a5, #0xffffffe0 +xori a5, a5, #0xfffffff0 +xori a5, a5, #0xfffffff8 +xori a5, a5, #0xfffffffc +xori a5, a5, #0xfffffffe +xori a5, a5, #0xffffffff +xori a5, a5, #0 +xori a5, a5, #1 +xori a5, a5, #2 +xori a5, a5, #4 +xori a5, a5, #8 +xori a5, a5, #0x10 +xori a5, a5, #0x20 +xori a5, a5, #0x40 +xori a5, a5, #0x80 +xori a5, a5, #0x100 +xori a5, a5, #0x200 +xori a5, a5, #0x400 +xori a5, a5, #0x7ff +xori a5, s4, #0xfffff801 +xori a5, s4, #0xfffffc00 +xori a5, s4, #0xfffffe00 +xori a5, s4, #0xffffff00 +xori a5, s4, #0xffffff80 +xori a5, s4, #0xffffffc0 +xori a5, s4, #0xffffffe0 +xori a5, s4, #0xfffffff0 +xori a5, s4, #0xfffffff8 +xori a5, s4, #0xfffffffc +xori a5, s4, #0xfffffffe +xori a5, s4, #0xffffffff +xori a5, s4, #0 +xori a5, s4, #1 +xori a5, s4, #2 +xori a5, s4, #4 +xori a5, s4, #8 +xori a5, s4, #0x10 +xori a5, s4, #0x20 +xori a5, s4, #0x40 +xori a5, s4, #0x80 +xori a5, s4, #0x100 +xori a5, s4, #0x200 +xori a5, s4, #0x400 +xori a5, s4, #0x7ff +xori a5, s9, #0xfffff801 +xori a5, s9, #0xfffffc00 +xori a5, s9, #0xfffffe00 +xori a5, s9, #0xffffff00 +xori a5, s9, #0xffffff80 +xori a5, s9, #0xffffffc0 +xori a5, s9, #0xffffffe0 +xori a5, s9, #0xfffffff0 +xori a5, s9, #0xfffffff8 +xori a5, s9, #0xfffffffc +xori a5, s9, #0xfffffffe +xori a5, s9, #0xffffffff +xori a5, s9, #0 +xori a5, s9, #1 +xori a5, s9, #2 +xori a5, s9, #4 +xori a5, s9, #8 +xori a5, s9, #0x10 +xori a5, s9, #0x20 +xori a5, s9, #0x40 +xori a5, s9, #0x80 +xori a5, s9, #0x100 +xori a5, s9, #0x200 +xori a5, s9, #0x400 +xori a5, s9, #0x7ff +xori a5, t6, #0xfffff801 +xori a5, t6, #0xfffffc00 +xori a5, t6, #0xfffffe00 +xori a5, t6, #0xffffff00 +xori a5, t6, #0xffffff80 +xori a5, t6, #0xffffffc0 +xori a5, t6, #0xffffffe0 +xori a5, t6, #0xfffffff0 +xori a5, t6, #0xfffffff8 +xori a5, t6, #0xfffffffc +xori a5, t6, #0xfffffffe +xori a5, t6, #0xffffffff +xori a5, t6, #0 +xori a5, t6, #1 +xori a5, t6, #2 +xori a5, t6, #4 +xori a5, t6, #8 +xori a5, t6, #0x10 +xori a5, t6, #0x20 +xori a5, t6, #0x40 +xori a5, t6, #0x80 +xori a5, t6, #0x100 +xori a5, t6, #0x200 +xori a5, t6, #0x400 +xori a5, t6, #0x7ff +xori s4, zero, #0xfffff801 +xori s4, zero, #0xfffffc00 +xori s4, zero, #0xfffffe00 +xori s4, zero, #0xffffff00 +xori s4, zero, #0xffffff80 +xori s4, zero, #0xffffffc0 +xori s4, zero, #0xffffffe0 +xori s4, zero, #0xfffffff0 +xori s4, zero, #0xfffffff8 +xori s4, zero, #0xfffffffc +xori s4, zero, #0xfffffffe +xori s4, zero, #0xffffffff +xori s4, zero, #0 +xori s4, zero, #1 +xori s4, zero, #2 +xori s4, zero, #4 +xori s4, zero, #8 +xori s4, zero, #0x10 +xori s4, zero, #0x20 +xori s4, zero, #0x40 +xori s4, zero, #0x80 +xori s4, zero, #0x100 +xori s4, zero, #0x200 +xori s4, zero, #0x400 +xori s4, zero, #0x7ff +xori s4, ra, #0xfffff801 +xori s4, ra, #0xfffffc00 +xori s4, ra, #0xfffffe00 +xori s4, ra, #0xffffff00 +xori s4, ra, #0xffffff80 +xori s4, ra, #0xffffffc0 +xori s4, ra, #0xffffffe0 +xori s4, ra, #0xfffffff0 +xori s4, ra, #0xfffffff8 +xori s4, ra, #0xfffffffc +xori s4, ra, #0xfffffffe +xori s4, ra, #0xffffffff +xori s4, ra, #0 +xori s4, ra, #1 +xori s4, ra, #2 +xori s4, ra, #4 +xori s4, ra, #8 +xori s4, ra, #0x10 +xori s4, ra, #0x20 +xori s4, ra, #0x40 +xori s4, ra, #0x80 +xori s4, ra, #0x100 +xori s4, ra, #0x200 +xori s4, ra, #0x400 +xori s4, ra, #0x7ff +xori s4, t0, #0xfffff801 +xori s4, t0, #0xfffffc00 +xori s4, t0, #0xfffffe00 +xori s4, t0, #0xffffff00 +xori s4, t0, #0xffffff80 +xori s4, t0, #0xffffffc0 +xori s4, t0, #0xffffffe0 +xori s4, t0, #0xfffffff0 +xori s4, t0, #0xfffffff8 +xori s4, t0, #0xfffffffc +xori s4, t0, #0xfffffffe +xori s4, t0, #0xffffffff +xori s4, t0, #0 +xori s4, t0, #1 +xori s4, t0, #2 +xori s4, t0, #4 +xori s4, t0, #8 +xori s4, t0, #0x10 +xori s4, t0, #0x20 +xori s4, t0, #0x40 +xori s4, t0, #0x80 +xori s4, t0, #0x100 +xori s4, t0, #0x200 +xori s4, t0, #0x400 +xori s4, t0, #0x7ff +xori s4, a0, #0xfffff801 +xori s4, a0, #0xfffffc00 +xori s4, a0, #0xfffffe00 +xori s4, a0, #0xffffff00 +xori s4, a0, #0xffffff80 +xori s4, a0, #0xffffffc0 +xori s4, a0, #0xffffffe0 +xori s4, a0, #0xfffffff0 +xori s4, a0, #0xfffffff8 +xori s4, a0, #0xfffffffc +xori s4, a0, #0xfffffffe +xori s4, a0, #0xffffffff +xori s4, a0, #0 +xori s4, a0, #1 +xori s4, a0, #2 +xori s4, a0, #4 +xori s4, a0, #8 +xori s4, a0, #0x10 +xori s4, a0, #0x20 +xori s4, a0, #0x40 +xori s4, a0, #0x80 +xori s4, a0, #0x100 +xori s4, a0, #0x200 +xori s4, a0, #0x400 +xori s4, a0, #0x7ff +xori s4, a5, #0xfffff801 +xori s4, a5, #0xfffffc00 +xori s4, a5, #0xfffffe00 +xori s4, a5, #0xffffff00 +xori s4, a5, #0xffffff80 +xori s4, a5, #0xffffffc0 +xori s4, a5, #0xffffffe0 +xori s4, a5, #0xfffffff0 +xori s4, a5, #0xfffffff8 +xori s4, a5, #0xfffffffc +xori s4, a5, #0xfffffffe +xori s4, a5, #0xffffffff +xori s4, a5, #0 +xori s4, a5, #1 +xori s4, a5, #2 +xori s4, a5, #4 +xori s4, a5, #8 +xori s4, a5, #0x10 +xori s4, a5, #0x20 +xori s4, a5, #0x40 +xori s4, a5, #0x80 +xori s4, a5, #0x100 +xori s4, a5, #0x200 +xori s4, a5, #0x400 +xori s4, a5, #0x7ff +xori s4, s4, #0xfffff801 +xori s4, s4, #0xfffffc00 +xori s4, s4, #0xfffffe00 +xori s4, s4, #0xffffff00 +xori s4, s4, #0xffffff80 +xori s4, s4, #0xffffffc0 +xori s4, s4, #0xffffffe0 +xori s4, s4, #0xfffffff0 +xori s4, s4, #0xfffffff8 +xori s4, s4, #0xfffffffc +xori s4, s4, #0xfffffffe +xori s4, s4, #0xffffffff +xori s4, s4, #0 +xori s4, s4, #1 +xori s4, s4, #2 +xori s4, s4, #4 +xori s4, s4, #8 +xori s4, s4, #0x10 +xori s4, s4, #0x20 +xori s4, s4, #0x40 +xori s4, s4, #0x80 +xori s4, s4, #0x100 +xori s4, s4, #0x200 +xori s4, s4, #0x400 +xori s4, s4, #0x7ff +xori s4, s9, #0xfffff801 +xori s4, s9, #0xfffffc00 +xori s4, s9, #0xfffffe00 +xori s4, s9, #0xffffff00 +xori s4, s9, #0xffffff80 +xori s4, s9, #0xffffffc0 +xori s4, s9, #0xffffffe0 +xori s4, s9, #0xfffffff0 +xori s4, s9, #0xfffffff8 +xori s4, s9, #0xfffffffc +xori s4, s9, #0xfffffffe +xori s4, s9, #0xffffffff +xori s4, s9, #0 +xori s4, s9, #1 +xori s4, s9, #2 +xori s4, s9, #4 +xori s4, s9, #8 +xori s4, s9, #0x10 +xori s4, s9, #0x20 +xori s4, s9, #0x40 +xori s4, s9, #0x80 +xori s4, s9, #0x100 +xori s4, s9, #0x200 +xori s4, s9, #0x400 +xori s4, s9, #0x7ff +xori s4, t6, #0xfffff801 +xori s4, t6, #0xfffffc00 +xori s4, t6, #0xfffffe00 +xori s4, t6, #0xffffff00 +xori s4, t6, #0xffffff80 +xori s4, t6, #0xffffffc0 +xori s4, t6, #0xffffffe0 +xori s4, t6, #0xfffffff0 +xori s4, t6, #0xfffffff8 +xori s4, t6, #0xfffffffc +xori s4, t6, #0xfffffffe +xori s4, t6, #0xffffffff +xori s4, t6, #0 +xori s4, t6, #1 +xori s4, t6, #2 +xori s4, t6, #4 +xori s4, t6, #8 +xori s4, t6, #0x10 +xori s4, t6, #0x20 +xori s4, t6, #0x40 +xori s4, t6, #0x80 +xori s4, t6, #0x100 +xori s4, t6, #0x200 +xori s4, t6, #0x400 +xori s4, t6, #0x7ff +xori s9, zero, #0xfffff801 +xori s9, zero, #0xfffffc00 +xori s9, zero, #0xfffffe00 +xori s9, zero, #0xffffff00 +xori s9, zero, #0xffffff80 +xori s9, zero, #0xffffffc0 +xori s9, zero, #0xffffffe0 +xori s9, zero, #0xfffffff0 +xori s9, zero, #0xfffffff8 +xori s9, zero, #0xfffffffc +xori s9, zero, #0xfffffffe +xori s9, zero, #0xffffffff +xori s9, zero, #0 +xori s9, zero, #1 +xori s9, zero, #2 +xori s9, zero, #4 +xori s9, zero, #8 +xori s9, zero, #0x10 +xori s9, zero, #0x20 +xori s9, zero, #0x40 +xori s9, zero, #0x80 +xori s9, zero, #0x100 +xori s9, zero, #0x200 +xori s9, zero, #0x400 +xori s9, zero, #0x7ff +xori s9, ra, #0xfffff801 +xori s9, ra, #0xfffffc00 +xori s9, ra, #0xfffffe00 +xori s9, ra, #0xffffff00 +xori s9, ra, #0xffffff80 +xori s9, ra, #0xffffffc0 +xori s9, ra, #0xffffffe0 +xori s9, ra, #0xfffffff0 +xori s9, ra, #0xfffffff8 +xori s9, ra, #0xfffffffc +xori s9, ra, #0xfffffffe +xori s9, ra, #0xffffffff +xori s9, ra, #0 +xori s9, ra, #1 +xori s9, ra, #2 +xori s9, ra, #4 +xori s9, ra, #8 +xori s9, ra, #0x10 +xori s9, ra, #0x20 +xori s9, ra, #0x40 +xori s9, ra, #0x80 +xori s9, ra, #0x100 +xori s9, ra, #0x200 +xori s9, ra, #0x400 +xori s9, ra, #0x7ff +xori s9, t0, #0xfffff801 +xori s9, t0, #0xfffffc00 +xori s9, t0, #0xfffffe00 +xori s9, t0, #0xffffff00 +xori s9, t0, #0xffffff80 +xori s9, t0, #0xffffffc0 +xori s9, t0, #0xffffffe0 +xori s9, t0, #0xfffffff0 +xori s9, t0, #0xfffffff8 +xori s9, t0, #0xfffffffc +xori s9, t0, #0xfffffffe +xori s9, t0, #0xffffffff +xori s9, t0, #0 +xori s9, t0, #1 +xori s9, t0, #2 +xori s9, t0, #4 +xori s9, t0, #8 +xori s9, t0, #0x10 +xori s9, t0, #0x20 +xori s9, t0, #0x40 +xori s9, t0, #0x80 +xori s9, t0, #0x100 +xori s9, t0, #0x200 +xori s9, t0, #0x400 +xori s9, t0, #0x7ff +xori s9, a0, #0xfffff801 +xori s9, a0, #0xfffffc00 +xori s9, a0, #0xfffffe00 +xori s9, a0, #0xffffff00 +xori s9, a0, #0xffffff80 +xori s9, a0, #0xffffffc0 +xori s9, a0, #0xffffffe0 +xori s9, a0, #0xfffffff0 +xori s9, a0, #0xfffffff8 +xori s9, a0, #0xfffffffc +xori s9, a0, #0xfffffffe +xori s9, a0, #0xffffffff +xori s9, a0, #0 +xori s9, a0, #1 +xori s9, a0, #2 +xori s9, a0, #4 +xori s9, a0, #8 +xori s9, a0, #0x10 +xori s9, a0, #0x20 +xori s9, a0, #0x40 +xori s9, a0, #0x80 +xori s9, a0, #0x100 +xori s9, a0, #0x200 +xori s9, a0, #0x400 +xori s9, a0, #0x7ff +xori s9, a5, #0xfffff801 +xori s9, a5, #0xfffffc00 +xori s9, a5, #0xfffffe00 +xori s9, a5, #0xffffff00 +xori s9, a5, #0xffffff80 +xori s9, a5, #0xffffffc0 +xori s9, a5, #0xffffffe0 +xori s9, a5, #0xfffffff0 +xori s9, a5, #0xfffffff8 +xori s9, a5, #0xfffffffc +xori s9, a5, #0xfffffffe +xori s9, a5, #0xffffffff +xori s9, a5, #0 +xori s9, a5, #1 +xori s9, a5, #2 +xori s9, a5, #4 +xori s9, a5, #8 +xori s9, a5, #0x10 +xori s9, a5, #0x20 +xori s9, a5, #0x40 +xori s9, a5, #0x80 +xori s9, a5, #0x100 +xori s9, a5, #0x200 +xori s9, a5, #0x400 +xori s9, a5, #0x7ff +xori s9, s4, #0xfffff801 +xori s9, s4, #0xfffffc00 +xori s9, s4, #0xfffffe00 +xori s9, s4, #0xffffff00 +xori s9, s4, #0xffffff80 +xori s9, s4, #0xffffffc0 +xori s9, s4, #0xffffffe0 +xori s9, s4, #0xfffffff0 +xori s9, s4, #0xfffffff8 +xori s9, s4, #0xfffffffc +xori s9, s4, #0xfffffffe +xori s9, s4, #0xffffffff +xori s9, s4, #0 +xori s9, s4, #1 +xori s9, s4, #2 +xori s9, s4, #4 +xori s9, s4, #8 +xori s9, s4, #0x10 +xori s9, s4, #0x20 +xori s9, s4, #0x40 +xori s9, s4, #0x80 +xori s9, s4, #0x100 +xori s9, s4, #0x200 +xori s9, s4, #0x400 +xori s9, s4, #0x7ff +xori s9, s9, #0xfffff801 +xori s9, s9, #0xfffffc00 +xori s9, s9, #0xfffffe00 +xori s9, s9, #0xffffff00 +xori s9, s9, #0xffffff80 +xori s9, s9, #0xffffffc0 +xori s9, s9, #0xffffffe0 +xori s9, s9, #0xfffffff0 +xori s9, s9, #0xfffffff8 +xori s9, s9, #0xfffffffc +xori s9, s9, #0xfffffffe +xori s9, s9, #0xffffffff +xori s9, s9, #0 +xori s9, s9, #1 +xori s9, s9, #2 +xori s9, s9, #4 +xori s9, s9, #8 +xori s9, s9, #0x10 +xori s9, s9, #0x20 +xori s9, s9, #0x40 +xori s9, s9, #0x80 +xori s9, s9, #0x100 +xori s9, s9, #0x200 +xori s9, s9, #0x400 +xori s9, s9, #0x7ff +xori s9, t6, #0xfffff801 +xori s9, t6, #0xfffffc00 +xori s9, t6, #0xfffffe00 +xori s9, t6, #0xffffff00 +xori s9, t6, #0xffffff80 +xori s9, t6, #0xffffffc0 +xori s9, t6, #0xffffffe0 +xori s9, t6, #0xfffffff0 +xori s9, t6, #0xfffffff8 +xori s9, t6, #0xfffffffc +xori s9, t6, #0xfffffffe +xori s9, t6, #0xffffffff +xori s9, t6, #0 +xori s9, t6, #1 +xori s9, t6, #2 +xori s9, t6, #4 +xori s9, t6, #8 +xori s9, t6, #0x10 +xori s9, t6, #0x20 +xori s9, t6, #0x40 +xori s9, t6, #0x80 +xori s9, t6, #0x100 +xori s9, t6, #0x200 +xori s9, t6, #0x400 +xori s9, t6, #0x7ff +xori t6, zero, #0xfffff801 +xori t6, zero, #0xfffffc00 +xori t6, zero, #0xfffffe00 +xori t6, zero, #0xffffff00 +xori t6, zero, #0xffffff80 +xori t6, zero, #0xffffffc0 +xori t6, zero, #0xffffffe0 +xori t6, zero, #0xfffffff0 +xori t6, zero, #0xfffffff8 +xori t6, zero, #0xfffffffc +xori t6, zero, #0xfffffffe +xori t6, zero, #0xffffffff +xori t6, zero, #0 +xori t6, zero, #1 +xori t6, zero, #2 +xori t6, zero, #4 +xori t6, zero, #8 +xori t6, zero, #0x10 +xori t6, zero, #0x20 +xori t6, zero, #0x40 +xori t6, zero, #0x80 +xori t6, zero, #0x100 +xori t6, zero, #0x200 +xori t6, zero, #0x400 +xori t6, zero, #0x7ff +xori t6, ra, #0xfffff801 +xori t6, ra, #0xfffffc00 +xori t6, ra, #0xfffffe00 +xori t6, ra, #0xffffff00 +xori t6, ra, #0xffffff80 +xori t6, ra, #0xffffffc0 +xori t6, ra, #0xffffffe0 +xori t6, ra, #0xfffffff0 +xori t6, ra, #0xfffffff8 +xori t6, ra, #0xfffffffc +xori t6, ra, #0xfffffffe +xori t6, ra, #0xffffffff +xori t6, ra, #0 +xori t6, ra, #1 +xori t6, ra, #2 +xori t6, ra, #4 +xori t6, ra, #8 +xori t6, ra, #0x10 +xori t6, ra, #0x20 +xori t6, ra, #0x40 +xori t6, ra, #0x80 +xori t6, ra, #0x100 +xori t6, ra, #0x200 +xori t6, ra, #0x400 +xori t6, ra, #0x7ff +xori t6, t0, #0xfffff801 +xori t6, t0, #0xfffffc00 +xori t6, t0, #0xfffffe00 +xori t6, t0, #0xffffff00 +xori t6, t0, #0xffffff80 +xori t6, t0, #0xffffffc0 +xori t6, t0, #0xffffffe0 +xori t6, t0, #0xfffffff0 +xori t6, t0, #0xfffffff8 +xori t6, t0, #0xfffffffc +xori t6, t0, #0xfffffffe +xori t6, t0, #0xffffffff +xori t6, t0, #0 +xori t6, t0, #1 +xori t6, t0, #2 +xori t6, t0, #4 +xori t6, t0, #8 +xori t6, t0, #0x10 +xori t6, t0, #0x20 +xori t6, t0, #0x40 +xori t6, t0, #0x80 +xori t6, t0, #0x100 +xori t6, t0, #0x200 +xori t6, t0, #0x400 +xori t6, t0, #0x7ff +xori t6, a0, #0xfffff801 +xori t6, a0, #0xfffffc00 +xori t6, a0, #0xfffffe00 +xori t6, a0, #0xffffff00 +xori t6, a0, #0xffffff80 +xori t6, a0, #0xffffffc0 +xori t6, a0, #0xffffffe0 +xori t6, a0, #0xfffffff0 +xori t6, a0, #0xfffffff8 +xori t6, a0, #0xfffffffc +xori t6, a0, #0xfffffffe +xori t6, a0, #0xffffffff +xori t6, a0, #0 +xori t6, a0, #1 +xori t6, a0, #2 +xori t6, a0, #4 +xori t6, a0, #8 +xori t6, a0, #0x10 +xori t6, a0, #0x20 +xori t6, a0, #0x40 +xori t6, a0, #0x80 +xori t6, a0, #0x100 +xori t6, a0, #0x200 +xori t6, a0, #0x400 +xori t6, a0, #0x7ff +xori t6, a5, #0xfffff801 +xori t6, a5, #0xfffffc00 +xori t6, a5, #0xfffffe00 +xori t6, a5, #0xffffff00 +xori t6, a5, #0xffffff80 +xori t6, a5, #0xffffffc0 +xori t6, a5, #0xffffffe0 +xori t6, a5, #0xfffffff0 +xori t6, a5, #0xfffffff8 +xori t6, a5, #0xfffffffc +xori t6, a5, #0xfffffffe +xori t6, a5, #0xffffffff +xori t6, a5, #0 +xori t6, a5, #1 +xori t6, a5, #2 +xori t6, a5, #4 +xori t6, a5, #8 +xori t6, a5, #0x10 +xori t6, a5, #0x20 +xori t6, a5, #0x40 +xori t6, a5, #0x80 +xori t6, a5, #0x100 +xori t6, a5, #0x200 +xori t6, a5, #0x400 +xori t6, a5, #0x7ff +xori t6, s4, #0xfffff801 +xori t6, s4, #0xfffffc00 +xori t6, s4, #0xfffffe00 +xori t6, s4, #0xffffff00 +xori t6, s4, #0xffffff80 +xori t6, s4, #0xffffffc0 +xori t6, s4, #0xffffffe0 +xori t6, s4, #0xfffffff0 +xori t6, s4, #0xfffffff8 +xori t6, s4, #0xfffffffc +xori t6, s4, #0xfffffffe +xori t6, s4, #0xffffffff +xori t6, s4, #0 +xori t6, s4, #1 +xori t6, s4, #2 +xori t6, s4, #4 +xori t6, s4, #8 +xori t6, s4, #0x10 +xori t6, s4, #0x20 +xori t6, s4, #0x40 +xori t6, s4, #0x80 +xori t6, s4, #0x100 +xori t6, s4, #0x200 +xori t6, s4, #0x400 +xori t6, s4, #0x7ff +xori t6, s9, #0xfffff801 +xori t6, s9, #0xfffffc00 +xori t6, s9, #0xfffffe00 +xori t6, s9, #0xffffff00 +xori t6, s9, #0xffffff80 +xori t6, s9, #0xffffffc0 +xori t6, s9, #0xffffffe0 +xori t6, s9, #0xfffffff0 +xori t6, s9, #0xfffffff8 +xori t6, s9, #0xfffffffc +xori t6, s9, #0xfffffffe +xori t6, s9, #0xffffffff +xori t6, s9, #0 +xori t6, s9, #1 +xori t6, s9, #2 +xori t6, s9, #4 +xori t6, s9, #8 +xori t6, s9, #0x10 +xori t6, s9, #0x20 +xori t6, s9, #0x40 +xori t6, s9, #0x80 +xori t6, s9, #0x100 +xori t6, s9, #0x200 +xori t6, s9, #0x400 +xori t6, s9, #0x7ff +xori t6, t6, #0xfffff801 +xori t6, t6, #0xfffffc00 +xori t6, t6, #0xfffffe00 +xori t6, t6, #0xffffff00 +xori t6, t6, #0xffffff80 +xori t6, t6, #0xffffffc0 +xori t6, t6, #0xffffffe0 +xori t6, t6, #0xfffffff0 +xori t6, t6, #0xfffffff8 +xori t6, t6, #0xfffffffc +xori t6, t6, #0xfffffffe +xori t6, t6, #0xffffffff +xori t6, t6, #0 +xori t6, t6, #1 +xori t6, t6, #2 +xori t6, t6, #4 +xori t6, t6, #8 +xori t6, t6, #0x10 +xori t6, t6, #0x20 +xori t6, t6, #0x40 +xori t6, t6, #0x80 +xori t6, t6, #0x100 +xori t6, t6, #0x200 +xori t6, t6, #0x400 +xori t6, t6, #0x7ff diff --git a/tests/riscv/test_all_riscv.sh b/tests/riscv/test_all_riscv.sh new file mode 100755 index 0000000..3a802f0 --- /dev/null +++ b/tests/riscv/test_all_riscv.sh @@ -0,0 +1,217 @@ +#!/bin/bash + +# Comprehensive test script for all RISC-V extensions +# Tests base spec (rv32i) and all extensions + +cd "$(dirname "$0")/../.." +GOODASM="./build/goodasm" +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + local extension="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local base_name=$(basename "$asm_file" .asm) + local dir=$(dirname "$asm_file") + local bin_file="$dir/${base_name}.bin" + local disasm_file="$dir/${base_name}.disasm" + + # Assemble the file + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$extension: $base_name - Assembly failed") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$extension: $base_name - Empty binary file") + return 1 + fi + + # Disassemble the binary + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$extension: $base_name - Disassembly failed") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples like "1: "c.andi a0, #0xFF"") + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits, like " 06 ") + # These appear in disassembly output but aren't actual instructions + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$extension: $base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$extension: $base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$extension: $base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + else + local original_lower=$(echo "$original_normalized" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized" | tr '[:upper:]' '[:lower:]') + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$extension: $base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + fi + done + + return 0 +} + +# Test a directory of .asm files +test_directory() { + local test_dir="$1" + local extension="$2" + + echo "" + echo "==========================================" + echo "Testing $extension" + echo "==========================================" + + if [ ! -d "$test_dir" ]; then + echo " WARNING: Directory $test_dir does not exist" + return + fi + + local dir_passed=0 + local dir_failed=0 + + for asm_file in "$test_dir"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + local base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$extension"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$extension: $base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + dir_passed=$((dir_passed + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$extension: $base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + dir_failed=$((dir_failed + 1)) + fi + done + + echo " Summary: $dir_passed passed, $dir_failed failed" +} + +# Run tests for each extension +test_directory "tests/riscv/rv32i" "RV32I (Base)" +test_directory "tests/riscv/c-extension" "C Extension" +test_directory "tests/riscv/m-extension" "M Extension" +test_directory "tests/riscv/a-extension" "A Extension" +test_directory "tests/riscv/f-extension" "F Extension" +test_directory "tests/riscv/d-extension" "D Extension" +test_directory "tests/riscv/zicsr-extension" "Zicsr Extension" + +# Print summary +echo "" +echo "==========================================" +echo "Overall Test Summary" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_all_riscv_parallel.sh b/tests/riscv/test_all_riscv_parallel.sh new file mode 100755 index 0000000..f4b6970 --- /dev/null +++ b/tests/riscv/test_all_riscv_parallel.sh @@ -0,0 +1,337 @@ +#!/bin/bash + +# Comprehensive test script for all RISC-V extensions with parallelization +# Tests base spec (rv32i) and all extensions + +cd "$(dirname "$0")/../.." +GOODASM="./build/goodasm" +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Determine number of parallel jobs (use number of CPU cores, but cap at 8) +MAX_JOBS=4 +if command -v sysctl &> /dev/null 2>&1; then + # macOS - try to get CPU count, but don't fail if it doesn't work + CPU_COUNT=$(sysctl -n hw.ncpu 2>/dev/null || echo "4") + MAX_JOBS=$CPU_COUNT +elif command -v nproc &> /dev/null 2>&1; then + # Linux + MAX_JOBS=$(nproc 2>/dev/null || echo "4") +fi +# Cap at 8 to avoid overwhelming the system, minimum of 2 +if [ "$MAX_JOBS" -lt 2 ]; then + MAX_JOBS=2 +elif [ "$MAX_JOBS" -gt 32 ]; then + MAX_JOBS=32 +fi +echo "Using $MAX_JOBS parallel jobs" + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + local extension="$2" + + if [ ! -f "$asm_file" ]; then + echo "FAIL:$extension:$(basename "$asm_file" .asm):File not found" + return 1 + fi + + local base_name=$(basename "$asm_file" .asm) + local dir=$(dirname "$asm_file") + local bin_file="$dir/${base_name}.bin" + local disasm_file="$dir/${base_name}.disasm" + + # Assemble the file + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + echo "FAIL:$extension:$base_name:Assembly failed" + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + echo "FAIL:$extension:$base_name:Empty binary file" + return 1 + fi + + # Disassemble the binary + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + echo "FAIL:$extension:$base_name:Disassembly failed" + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples like "1: "c.andi a0, #0xFF"") + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits, like " 06 ") + # These appear in disassembly output but aren't actual instructions + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + echo "FAIL:$extension:$base_name:Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})" + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Normalize immediate values: convert hex to decimal for comparison + # The disassembler outputs hex (e.g., #0xfffff801) but tests use decimal (e.g., #-2047) + # Convert hex immediates to signed decimal for comparison + original_normalized=$(echo "$original_normalized" | python3 -c " +import sys +import re +for line in sys.stdin: + # Convert #0x... hex immediates to decimal + def hex_to_dec(match): + val = int(match.group(1), 16) + # Handle 32-bit sign extension + if val >= 0x80000000: + val = val - 0x100000000 + return '#' + str(val) + line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) + print(line, end='') +" 2>/dev/null || echo "$original_normalized") + + disasm_normalized=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +for line in sys.stdin: + # Convert #0x... hex immediates to decimal + def hex_to_dec(match): + val = int(match.group(1), 16) + # Handle 32-bit sign extension + if val >= 0x80000000: + val = val - 0x100000000 + return '#' + str(val) + line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) + print(line, end='') +" 2>/dev/null || echo "$disasm_normalized") + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + echo "FAIL:$extension:$base_name[$((i+1))]:Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'" + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + echo "FAIL:$extension:$base_name[$((i+1))]:Operand count mismatch: '$original_normalized' -> '$disasm_normalized'" + return 1 + fi + else + local original_lower=$(echo "$original_normalized" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized" | tr '[:upper:]' '[:lower:]') + if [ "$original_lower" != "$disasm_lower" ]; then + echo "FAIL:$extension:$base_name[$((i+1))]:Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'" + return 1 + fi + fi + done + + echo "PASS:$extension:$base_name" + return 0 +} + +# Export function and variables for parallel execution +export -f test_file +export GOODASM + +# Test a directory of .asm files in parallel +test_directory() { + local test_dir="$1" + local extension="$2" + + echo "" + echo "==========================================" + echo "Testing $extension" + echo "==========================================" + + if [ ! -d "$test_dir" ]; then + echo " WARNING: Directory $test_dir does not exist" + return + fi + + # Collect all .asm files + local asm_files=() + for asm_file in "$test_dir"/*.asm; do + if [ -f "$asm_file" ]; then + asm_files+=("$asm_file") + fi + done + + if [ ${#asm_files[@]} -eq 0 ]; then + echo " No test files found" + return + fi + + # Run tests in parallel using background jobs + local results_file=$(mktemp) + declare -a pids=() + local job_count=0 + + for asm_file in "${asm_files[@]}"; do + # Wait if we've reached max jobs + while [ $job_count -ge $MAX_JOBS ]; do + # Wait for any job to complete + declare -a new_pids=() + for pid in "${pids[@]}"; do + if [ -n "$pid" ] && [ "$pid" -gt 0 ] 2>/dev/null && kill -0 "$pid" 2>/dev/null; then + # Job still running + new_pids+=($pid) + else + # Job completed + if [ -n "$pid" ] && [ "$pid" -gt 0 ] 2>/dev/null; then + wait "$pid" 2>/dev/null || true + fi + job_count=$((job_count - 1)) + fi + done + pids=("${new_pids[@]}") + if [ $job_count -ge $MAX_JOBS ]; then + sleep 0.1 # Small delay to avoid busy waiting + fi + done + + # Run test in background + (test_file "$asm_file" "$extension" >> "$results_file" 2>&1) & + local new_pid=$! + if [ -n "$new_pid" ] && [ "$new_pid" -gt 0 ]; then + pids+=($new_pid) + job_count=$((job_count + 1)) + fi + done + + # Wait for all remaining jobs + for pid in "${pids[@]}"; do + if [ -n "$pid" ] && [ "$pid" -gt 0 ] 2>/dev/null; then + wait "$pid" 2>/dev/null || true + fi + done + + # Process results + local dir_passed=0 + local dir_failed=0 + + while IFS= read -r result; do + if [ -z "$result" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + + if [[ "$result" =~ ^PASS: ]]; then + local test_name=$(echo "$result" | cut -d: -f3) + echo " PASS: $test_name" + PASSED_TESTS+=("$extension: $test_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + dir_passed=$((dir_passed + 1)) + elif [[ "$result" =~ ^FAIL: ]]; then + local test_name=$(echo "$result" | cut -d: -f3) + local error_msg=$(echo "$result" | cut -d: -f4-) + echo " FAIL: $test_name" + FAILED_TESTS+=("$extension: $test_name") + ERRORS+=("$extension: $test_name - $error_msg") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + dir_failed=$((dir_failed + 1)) + fi + done < "$results_file" + + rm -f "$results_file" + + echo " Summary: $dir_passed passed, $dir_failed failed" +} + +# Run tests for each extension +test_directory "tests/riscv/rv32i" "RV32I (Base)" +test_directory "tests/riscv/c-extension" "C Extension" +test_directory "tests/riscv/m-extension" "M Extension" +test_directory "tests/riscv/a-extension" "A Extension" +test_directory "tests/riscv/f-extension" "F Extension" +test_directory "tests/riscv/d-extension" "D Extension" +test_directory "tests/riscv/zicsr-extension" "Zicsr Extension" + +# Print summary +echo "" +echo "==========================================" +echo "Overall Test Summary" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_c_extension.sh b/tests/riscv/test_c_extension.sh new file mode 100755 index 0000000..9d14f63 --- /dev/null +++ b/tests/riscv/test_c_extension.sh @@ -0,0 +1,198 @@ +#!/bin/bash + +# Script to test all C-type instruction unit tests +# For each .asm file, assemble it to .bin, disassemble to .disasm, +# and compare the instructions and operands + +cd "$(dirname "$0")" +TEST_DIR="tests/riscv/c-extension" +GOODASM="./build/goodasm" +ERRORS=() +FAILED_INSTRUCTIONS=() + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Get all .asm files in the c-extension directory +for asm_file in "$TEST_DIR"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + base_name=$(basename "$asm_file" .asm) + bin_file="$TEST_DIR/${base_name}.bin" + disasm_file="$TEST_DIR/${base_name}.disasm" + + echo "Testing: $base_name" + + # Assemble the file + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + echo " ERROR: Failed to assemble $asm_file" + ERRORS+=("$base_name: Assembly failed") + FAILED_INSTRUCTIONS+=("$base_name") + continue + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + echo " ERROR: Binary file is empty" + ERRORS+=("$base_name: Empty binary file") + FAILED_INSTRUCTIONS+=("$base_name") + continue + fi + + # Disassemble the binary + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + echo " ERROR: Failed to disassemble $bin_file" + ERRORS+=("$base_name: Disassembly failed") + FAILED_INSTRUCTIONS+=("$base_name") + continue + fi + + # Extract all instructions from the original .asm file (skip directives, blank lines, labels, and comments) + original_instrs=() + while IFS= read -r line; do + # Skip empty lines, directives, labels, and comments + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + # Trim whitespace + trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + disasm_instrs=() + while IFS= read -r line; do + trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + # Skip empty lines + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples like "1: "c.andi a0, #0xFF"") + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits, like " 06 ") + # These appear in disassembly output but aren't actual instructions + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + echo " FAIL: Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})" + echo " Original instructions: ${#original_instrs[@]}" + echo " Disassembled instructions: ${#disasm_instrs[@]}" + ERRORS+=("$base_name: Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + FAILED_INSTRUCTIONS+=("$base_name") + continue + fi + + # Compare each instruction pair + file_passed=true + for i in "${!original_instrs[@]}"; do + original_instr="${original_instrs[$i]}" + disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + echo " FAIL: Mnemonic mismatch for instruction $((i+1))" + echo " Original: $original_normalized" + echo " Disasm: $disasm_normalized" + ERRORS+=("$base_name[$((i+1))]: Mnemonic mismatch - '$original_normalized' -> '$disasm_normalized'") + file_passed=false + continue + fi + + # Check for operand mismatches + # Extract operands (everything after mnemonic) + original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + # Has label - check mnemonic matches and operand count + original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + + if [ "$original_op_count" != "$disasm_op_count" ]; then + echo " FAIL: Operand count mismatch for instruction $((i+1))" + echo " Original: $original_normalized" + echo " Disasm: $disasm_normalized" + ERRORS+=("$base_name[$((i+1))]: Operand count mismatch - '$original_normalized' -> '$disasm_normalized'") + file_passed=false + fi + # Note: For labels, we accept the mnemonic match and operand count as pass + else + # No labels - do comparison including operands (case-insensitive for hex) + # Normalize both strings to lowercase for comparison + original_lower=$(echo "$original_normalized" | tr '[:upper:]' '[:lower:]') + disasm_lower=$(echo "$disasm_normalized" | tr '[:upper:]' '[:lower:]') + if [ "$original_lower" != "$disasm_lower" ]; then + echo " FAIL: Instruction/operand mismatch for instruction $((i+1))" + echo " Original: $original_normalized" + echo " Disasm: $disasm_normalized" + ERRORS+=("$base_name[$((i+1))]: Instruction/operand mismatch - '$original_normalized' -> '$disasm_normalized'") + file_passed=false + fi + fi + done + + if [ "$file_passed" = true ]; then + if [ ${#original_instrs[@]} -eq 1 ]; then + echo " PASS: ${original_instrs[0]}" + else + echo " PASS: ${#original_instrs[@]} instructions" + fi + else + FAILED_INSTRUCTIONS+=("$base_name") + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Test Summary" +echo "==========================================" +total_tests=$(ls "$TEST_DIR"/*.asm 2>/dev/null | wc -l | tr -d ' ') +echo "Total tests: $total_tests" +echo "Failed tests: ${#FAILED_INSTRUCTIONS[@]}" + +if [ ${#FAILED_INSTRUCTIONS[@]} -gt 0 ]; then + echo "" + echo "Failed instructions:" + for instr in "${FAILED_INSTRUCTIONS[@]}"; do + echo " - $instr" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "All tests passed!" + exit 0 +fi diff --git a/tests/riscv/test_full_range_validation.sh b/tests/riscv/test_full_range_validation.sh new file mode 100755 index 0000000..65cdbb7 --- /dev/null +++ b/tests/riscv/test_full_range_validation.sh @@ -0,0 +1,567 @@ +#!/bin/bash +# +# Full Range RISC-V Validation Test +# Tests every instruction with full value range coverage +# Includes boundary values (min, max, zero, mid-range) +# Runtime: ~2-3 minutes +# + +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +cd "$SCRIPT_DIR/../.." +GOODASM="$(pwd)/build/goodasm" + +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + echo "Run 'make' first to build goodasm" + exit 1 +fi + +PASS=0 +FAIL=0 +FAILED_TESTS=() + +# Normalize hex to decimal for comparison +normalize_values() { + local input="$1" + echo "$input" | python3 -c " +import sys +import re + +line = sys.stdin.read().strip() + +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) + +result = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(result, end='') +" +} + +# Test a single instruction roundtrip +test_instr() { + local instr="$1" + local category="$2" + + echo -e ".lang riscv32\n.org 0x0\n$instr" > /tmp/test_full.asm + "$GOODASM" --riscv32 /tmp/test_full.asm -o /tmp/test_full.bin 2>/dev/null + + if [ ! -s /tmp/test_full.bin ]; then + echo " FAIL: $instr (assembly failed)" + FAILED_TESTS+=("[$category] $instr - assembly failed") + ((FAIL++)) + return 1 + fi + + result=$("$GOODASM" --riscv32 -d /tmp/test_full.bin 2>/dev/null | grep -v "^Colliding" | grep -v "^[0-9]*: \"" | head -1) + + orig_norm=$(echo "$instr" | tr '[:upper:]' '[:lower:]' | sed 's/[[:space:]]\+/ /g' | sed 's/,\s*/, /g' | sed 's/[[:space:]]*$//') + result_norm=$(echo "$result" | tr '[:upper:]' '[:lower:]' | sed 's/[[:space:]]\+/ /g' | sed 's/,\s*/, /g' | sed 's/[[:space:]]*$//') + + orig_norm=$(normalize_values "$orig_norm") + result_norm=$(normalize_values "$result_norm") + + if [ "$orig_norm" = "$result_norm" ]; then + ((PASS++)) + return 0 + else + echo " FAIL: $instr -> $result" + FAILED_TESTS+=("[$category] $instr -> $result") + ((FAIL++)) + return 1 + fi +} + +echo "==========================================" +echo "Full Range RISC-V Validation Test" +echo "==========================================" +echo "Testing every instruction with full value ranges..." +echo "" + +# ============================================================================ +# RV32I Base Integer Instructions +# ============================================================================ + +echo "=== R-type ALU (10 instructions) ===" +# Test with various register combinations including edge registers +for op in add sub and or xor sll srl sra slt sltu; do + test_instr "$op zero, zero, zero" "R-$op" + test_instr "$op t0, t1, t2" "R-$op" + test_instr "$op a0, a1, a2" "R-$op" + test_instr "$op s0, s1, s2" "R-$op" + test_instr "$op ra, sp, gp" "R-$op" + test_instr "$op t6, s11, a7" "R-$op" +done +echo " R-type: $PASS passed" +R_PASS=$PASS + +echo "" +echo "=== I-type ALU (6 instructions) ===" +# 12-bit signed immediate: -2048 to 2047 +for op in addi andi ori xori slti sltiu; do + test_instr "$op t0, t1, #0" "I-$op" + test_instr "$op t0, t1, #1" "I-$op" + test_instr "$op t0, t1, #-1" "I-$op" + test_instr "$op t0, t1, #127" "I-$op" + test_instr "$op t0, t1, #-128" "I-$op" + test_instr "$op t0, t1, #255" "I-$op" + test_instr "$op t0, t1, #1024" "I-$op" + test_instr "$op t0, t1, #-1024" "I-$op" + test_instr "$op t0, t1, #2047" "I-$op" + test_instr "$op t0, t1, #-2048" "I-$op" +done +echo " I-type ALU: $((PASS - R_PASS)) passed" +I_PASS=$PASS + +echo "" +echo "=== Shift Immediate (3 instructions) ===" +# 5-bit shift amount: 0-31 +for op in slli srli srai; do + test_instr "$op t0, t1, #0" "Shift-$op" + test_instr "$op t0, t1, #1" "Shift-$op" + test_instr "$op t0, t1, #7" "Shift-$op" + test_instr "$op t0, t1, #8" "Shift-$op" + test_instr "$op t0, t1, #15" "Shift-$op" + test_instr "$op t0, t1, #16" "Shift-$op" + test_instr "$op t0, t1, #24" "Shift-$op" + test_instr "$op t0, t1, #31" "Shift-$op" +done +echo " Shift: $((PASS - I_PASS)) passed" +SHIFT_PASS=$PASS + +echo "" +echo "=== Load (5 instructions) ===" +# 12-bit signed offset: -2048 to 2047 +for op in lw lh lb lhu lbu; do + test_instr "$op t0, (#0, t1)" "Load-$op" + test_instr "$op t0, (#1, t1)" "Load-$op" + test_instr "$op t0, (#-1, t1)" "Load-$op" + test_instr "$op t0, (#127, t1)" "Load-$op" + test_instr "$op t0, (#-128, t1)" "Load-$op" + test_instr "$op t0, (#1024, t1)" "Load-$op" + test_instr "$op t0, (#-1024, t1)" "Load-$op" + test_instr "$op t0, (#2047, t1)" "Load-$op" + test_instr "$op t0, (#-2048, t1)" "Load-$op" +done +echo " Load: $((PASS - SHIFT_PASS)) passed" +LOAD_PASS=$PASS + +echo "" +echo "=== Store (3 instructions) ===" +# 12-bit signed offset: -2048 to 2047 +for op in sw sh sb; do + test_instr "$op t0, (#0, t1)" "Store-$op" + test_instr "$op t0, (#1, t1)" "Store-$op" + test_instr "$op t0, (#-1, t1)" "Store-$op" + test_instr "$op t0, (#127, t1)" "Store-$op" + test_instr "$op t0, (#-128, t1)" "Store-$op" + test_instr "$op t0, (#1024, t1)" "Store-$op" + test_instr "$op t0, (#-1024, t1)" "Store-$op" + test_instr "$op t0, (#2047, t1)" "Store-$op" + test_instr "$op t0, (#-2048, t1)" "Store-$op" +done +echo " Store: $((PASS - LOAD_PASS)) passed" +STORE_PASS=$PASS + +echo "" +echo "=== U-type (2 instructions) ===" +# 20-bit upper immediate, must be multiple of 0x1000 +for op in lui auipc; do + test_instr "$op t0, #0x00000000" "U-$op" + test_instr "$op t0, #0x00001000" "U-$op" + test_instr "$op t0, #0x00010000" "U-$op" + test_instr "$op t0, #0x00100000" "U-$op" + test_instr "$op t0, #0x12345000" "U-$op" + test_instr "$op t0, #0x7FFFF000" "U-$op" + test_instr "$op t0, #0x80000000" "U-$op" + test_instr "$op t0, #0xFFFFF000" "U-$op" +done +echo " U-type: $((PASS - STORE_PASS)) passed" +U_PASS=$PASS + +echo "" +echo "=== Branch (6 instructions) ===" +# 13-bit signed offset, must be even: -4096 to 4094 +for op in beq bne blt bge bltu bgeu; do + test_instr "$op t0, t1, #2" "Branch-$op" + test_instr "$op t0, t1, #-2" "Branch-$op" + test_instr "$op t0, t1, #4" "Branch-$op" + test_instr "$op t0, t1, #-4" "Branch-$op" + test_instr "$op t0, t1, #256" "Branch-$op" + test_instr "$op t0, t1, #-256" "Branch-$op" + test_instr "$op t0, t1, #2048" "Branch-$op" + test_instr "$op t0, t1, #-2048" "Branch-$op" + test_instr "$op t0, t1, #4094" "Branch-$op" + test_instr "$op t0, t1, #-4096" "Branch-$op" +done +echo " Branch: $((PASS - U_PASS)) passed" +BRANCH_PASS=$PASS + +echo "" +echo "=== JAL (1 instruction) ===" +# 21-bit signed offset, must be even: -1048576 to 1048574 +test_instr "jal ra, #2" "JAL" +test_instr "jal ra, #-2" "JAL" +test_instr "jal ra, #4" "JAL" +test_instr "jal ra, #-4" "JAL" +test_instr "jal t0, #1024" "JAL" +test_instr "jal t0, #-1024" "JAL" +test_instr "jal t0, #65536" "JAL" +test_instr "jal t0, #-65536" "JAL" +test_instr "jal zero, #1048574" "JAL" +test_instr "jal zero, #-1048576" "JAL" +echo " JAL: $((PASS - BRANCH_PASS)) passed" +JAL_PASS=$PASS + +echo "" +echo "=== JALR (1 instruction) ===" +# 12-bit signed offset: -2048 to 2047 +test_instr "jalr ra, t0, #0" "JALR" +test_instr "jalr ra, t0, #1" "JALR" +test_instr "jalr ra, t0, #-1" "JALR" +test_instr "jalr ra, t0, #127" "JALR" +test_instr "jalr ra, t0, #-128" "JALR" +test_instr "jalr ra, t0, #1024" "JALR" +test_instr "jalr ra, t0, #-1024" "JALR" +test_instr "jalr t1, a0, #2047" "JALR" +test_instr "jalr t1, a0, #-2048" "JALR" +echo " JALR: $((PASS - JAL_PASS)) passed" +JALR_PASS=$PASS + +echo "" +echo "=== System (4 instructions) ===" +test_instr "ecall" "System" +test_instr "ebreak" "System" +test_instr "fence" "System" +test_instr "fence.i" "System" +echo " System: $((PASS - JALR_PASS)) passed" +SYS_PASS=$PASS + +# ============================================================================ +# M Extension - Multiply/Divide +# ============================================================================ + +echo "" +echo "=== M Extension (8 instructions) ===" +for op in mul mulh mulhsu mulhu div divu rem remu; do + test_instr "$op t0, t1, t2" "M-$op" + test_instr "$op a0, a1, a2" "M-$op" + test_instr "$op s0, s1, s2" "M-$op" +done +echo " M Extension: $((PASS - SYS_PASS)) passed" +M_PASS=$PASS + +# ============================================================================ +# A Extension - Atomics +# ============================================================================ + +echo "" +echo "=== A Extension (11 instructions) ===" +test_instr "lr.w t0, (t1)" "A-lr.w" +test_instr "lr.w a0, (a1)" "A-lr.w" +test_instr "lr.w s0, (s1)" "A-lr.w" +test_instr "sc.w t0, t2, (t1)" "A-sc.w" +test_instr "sc.w a0, a2, (a1)" "A-sc.w" +test_instr "sc.w s0, s2, (s1)" "A-sc.w" +for op in amoswap.w amoadd.w amoxor.w amoand.w amoor.w amomin.w amomax.w amominu.w amomaxu.w; do + test_instr "$op t0, t2, (t1)" "A-$op" + test_instr "$op a0, a2, (a1)" "A-$op" +done +echo " A Extension: $((PASS - M_PASS)) passed" +A_PASS=$PASS + +# ============================================================================ +# Zicsr Extension - CSR Instructions +# ============================================================================ + +echo "" +echo "=== Zicsr Extension (6 instructions) ===" +# CSR address: 12-bit (0-4095), uimm: 5-bit (0-31) +for op in csrrw csrrs csrrc; do + test_instr "$op t0, #0x000, t1" "Zicsr-$op" + test_instr "$op t0, #0x300, t1" "Zicsr-$op" + test_instr "$op a0, #0x341, a1" "Zicsr-$op" + test_instr "$op a0, #0xFFF, a1" "Zicsr-$op" +done +for op in csrrwi csrrsi csrrci; do + test_instr "$op t0, #0x000, #0" "Zicsr-$op" + test_instr "$op t0, #0x300, #5" "Zicsr-$op" + test_instr "$op a0, #0x341, #15" "Zicsr-$op" + test_instr "$op a0, #0xFFF, #31" "Zicsr-$op" +done +echo " Zicsr: $((PASS - A_PASS)) passed" +ZICSR_PASS=$PASS + +# ============================================================================ +# C Extension - Compressed Instructions +# ============================================================================ + +echo "" +echo "=== C Extension CR Format ===" +# c.add, c.mv: any register except x0 for rd +# c.jr, c.jalr: any register except x0 for rs1 +test_instr "c.add ra, sp" "C-CR" +test_instr "c.add a0, a1" "C-CR" +test_instr "c.add s0, s1" "C-CR" +test_instr "c.add t6, s11" "C-CR" +test_instr "c.mv ra, sp" "C-CR" +test_instr "c.mv a0, a1" "C-CR" +test_instr "c.mv s0, s1" "C-CR" +test_instr "c.mv t6, s11" "C-CR" +test_instr "c.jr ra" "C-CR" +test_instr "c.jr a0" "C-CR" +test_instr "c.jr t6" "C-CR" +test_instr "c.jalr ra" "C-CR" +test_instr "c.jalr a0" "C-CR" +test_instr "c.jalr t6" "C-CR" +echo " C-CR: $((PASS - ZICSR_PASS)) passed" +C_CR_PASS=$PASS + +echo "" +echo "=== C Extension CI Format ===" +# c.addi: 6-bit signed non-zero: -32 to -1, 1 to 31 +test_instr "c.addi a0, #1" "C-CI" +test_instr "c.addi a0, #-1" "C-CI" +test_instr "c.addi a0, #15" "C-CI" +test_instr "c.addi a0, #-16" "C-CI" +test_instr "c.addi a0, #31" "C-CI" +test_instr "c.addi a0, #-32" "C-CI" +test_instr "c.addi t0, #7" "C-CI" +test_instr "c.addi s0, #-7" "C-CI" + +# c.li: 6-bit signed: -32 to 31 +test_instr "c.li a0, #0" "C-CI" +test_instr "c.li a0, #1" "C-CI" +test_instr "c.li a0, #-1" "C-CI" +test_instr "c.li a0, #15" "C-CI" +test_instr "c.li a0, #-16" "C-CI" +test_instr "c.li a0, #31" "C-CI" +test_instr "c.li a0, #-32" "C-CI" + +# c.slli: 5-bit shift (RV32): 1-31 +test_instr "c.slli a0, #1" "C-CI" +test_instr "c.slli a0, #7" "C-CI" +test_instr "c.slli a0, #8" "C-CI" +test_instr "c.slli a0, #15" "C-CI" +test_instr "c.slli a0, #16" "C-CI" +test_instr "c.slli a0, #24" "C-CI" +test_instr "c.slli a0, #31" "C-CI" +test_instr "c.slli t0, #5" "C-CI" + +# c.lui: 6-bit signed, scaled to bits [17:12]: ±0x1F000 (excluding 0) +test_instr "c.lui a0, #0x1000" "C-CI" +test_instr "c.lui a0, #0x2000" "C-CI" +test_instr "c.lui a0, #0xF000" "C-CI" +test_instr "c.lui a0, #0x10000" "C-CI" +test_instr "c.lui a0, #0x1F000" "C-CI" +test_instr "c.lui a0, #0xFFFFF000" "C-CI" +test_instr "c.lui t0, #0xFFFFE000" "C-CI" + +# c.addi16sp: 10-bit signed, multiple of 16: -512 to 496 +test_instr "c.addi16sp #16" "C-CI" +test_instr "c.addi16sp #-16" "C-CI" +test_instr "c.addi16sp #32" "C-CI" +test_instr "c.addi16sp #-32" "C-CI" +test_instr "c.addi16sp #128" "C-CI" +test_instr "c.addi16sp #-128" "C-CI" +test_instr "c.addi16sp #256" "C-CI" +test_instr "c.addi16sp #-256" "C-CI" +test_instr "c.addi16sp #496" "C-CI" +test_instr "c.addi16sp #-512" "C-CI" + +# c.lwsp: 8-bit unsigned, scaled by 4: 0-252 +test_instr "c.lwsp a0, #0" "C-CI" +test_instr "c.lwsp a0, #4" "C-CI" +test_instr "c.lwsp a0, #8" "C-CI" +test_instr "c.lwsp a0, #60" "C-CI" +test_instr "c.lwsp a0, #64" "C-CI" +test_instr "c.lwsp a0, #124" "C-CI" +test_instr "c.lwsp a0, #128" "C-CI" +test_instr "c.lwsp a0, #188" "C-CI" +test_instr "c.lwsp a0, #192" "C-CI" +test_instr "c.lwsp a1, #252" "C-CI" +echo " C-CI: $((PASS - C_CR_PASS)) passed" +C_CI_PASS=$PASS + +echo "" +echo "=== C Extension CSS Format ===" +# c.swsp: 8-bit unsigned, scaled by 4: 0-252 +test_instr "c.swsp a0, #0" "C-CSS" +test_instr "c.swsp a0, #4" "C-CSS" +test_instr "c.swsp a0, #60" "C-CSS" +test_instr "c.swsp a0, #64" "C-CSS" +test_instr "c.swsp a0, #124" "C-CSS" +test_instr "c.swsp a0, #128" "C-CSS" +test_instr "c.swsp a0, #192" "C-CSS" +test_instr "c.swsp t0, #252" "C-CSS" +echo " C-CSS: $((PASS - C_CI_PASS)) passed" +C_CSS_PASS=$PASS + +echo "" +echo "=== C Extension CIW Format ===" +# c.addi4spn: 10-bit unsigned, scaled by 4, non-zero: 4-1020 +test_instr "c.addi4spn s0, #4" "C-CIW" +test_instr "c.addi4spn s0, #8" "C-CIW" +test_instr "c.addi4spn s0, #16" "C-CIW" +test_instr "c.addi4spn s0, #64" "C-CIW" +test_instr "c.addi4spn s0, #128" "C-CIW" +test_instr "c.addi4spn s0, #256" "C-CIW" +test_instr "c.addi4spn s0, #512" "C-CIW" +test_instr "c.addi4spn a0, #1020" "C-CIW" +echo " C-CIW: $((PASS - C_CSS_PASS)) passed" +C_CIW_PASS=$PASS + +echo "" +echo "=== C Extension CL Format ===" +# c.lw: 7-bit unsigned, scaled by 4: 0-124 +test_instr "c.lw s0, (#0, s1)" "C-CL" +test_instr "c.lw s0, (#4, s1)" "C-CL" +test_instr "c.lw s0, (#8, s1)" "C-CL" +test_instr "c.lw s0, (#16, s1)" "C-CL" +test_instr "c.lw a0, (#32, a1)" "C-CL" +test_instr "c.lw a0, (#60, a1)" "C-CL" +test_instr "c.lw a0, (#64, a1)" "C-CL" +test_instr "c.lw a0, (#96, a1)" "C-CL" +test_instr "c.lw a1, (#124, a0)" "C-CL" +echo " C-CL: $((PASS - C_CIW_PASS)) passed" +C_CL_PASS=$PASS + +echo "" +echo "=== C Extension CS Format ===" +# c.sw: 7-bit unsigned, scaled by 4: 0-124 +test_instr "c.sw s0, (#0, s1)" "C-CS" +test_instr "c.sw s0, (#4, s1)" "C-CS" +test_instr "c.sw s0, (#8, s1)" "C-CS" +test_instr "c.sw s0, (#16, s1)" "C-CS" +test_instr "c.sw a0, (#32, a1)" "C-CS" +test_instr "c.sw a0, (#60, a1)" "C-CS" +test_instr "c.sw a0, (#64, a1)" "C-CS" +test_instr "c.sw a0, (#96, a1)" "C-CS" +test_instr "c.sw a1, (#124, a0)" "C-CS" +echo " C-CS: $((PASS - C_CL_PASS)) passed" +C_CS_PASS=$PASS + +echo "" +echo "=== C Extension CA Format ===" +# Compressed registers only: s0-s7 (x8-x15) or a0-a7 (x10-x17, overlaps) +for op in c.sub c.xor c.or c.and; do + test_instr "$op s0, s1" "C-CA" + test_instr "$op s1, s0" "C-CA" + test_instr "$op a0, a1" "C-CA" + test_instr "$op a1, a0" "C-CA" + test_instr "$op s0, a0" "C-CA" + test_instr "$op a1, s1" "C-CA" +done +echo " C-CA: $((PASS - C_CS_PASS)) passed" +C_CA_PASS=$PASS + +echo "" +echo "=== C Extension CB Format ===" +# c.beqz, c.bnez: 9-bit signed, must be even: -256 to 254 +test_instr "c.beqz s0, #2" "C-CB" +test_instr "c.beqz s0, #-2" "C-CB" +test_instr "c.beqz s0, #4" "C-CB" +test_instr "c.beqz s0, #-4" "C-CB" +test_instr "c.beqz a0, #64" "C-CB" +test_instr "c.beqz a0, #-64" "C-CB" +test_instr "c.beqz a0, #128" "C-CB" +test_instr "c.beqz a0, #-128" "C-CB" +test_instr "c.beqz a0, #254" "C-CB" +test_instr "c.beqz a0, #-256" "C-CB" +test_instr "c.bnez s0, #2" "C-CB" +test_instr "c.bnez s0, #-2" "C-CB" +test_instr "c.bnez s0, #4" "C-CB" +test_instr "c.bnez s0, #-4" "C-CB" +test_instr "c.bnez a0, #64" "C-CB" +test_instr "c.bnez a0, #-64" "C-CB" +test_instr "c.bnez a0, #128" "C-CB" +test_instr "c.bnez a0, #-128" "C-CB" +test_instr "c.bnez a0, #254" "C-CB" +test_instr "c.bnez a0, #-256" "C-CB" + +# c.srli, c.srai: 5-bit shift (RV32): 1-31 +test_instr "c.srli s0, #1" "C-CB" +test_instr "c.srli s0, #7" "C-CB" +test_instr "c.srli s0, #8" "C-CB" +test_instr "c.srli a0, #15" "C-CB" +test_instr "c.srli a0, #16" "C-CB" +test_instr "c.srli a1, #24" "C-CB" +test_instr "c.srli a1, #31" "C-CB" +test_instr "c.srai s0, #1" "C-CB" +test_instr "c.srai s0, #7" "C-CB" +test_instr "c.srai s0, #8" "C-CB" +test_instr "c.srai a0, #15" "C-CB" +test_instr "c.srai a0, #16" "C-CB" +test_instr "c.srai a1, #24" "C-CB" +test_instr "c.srai a1, #31" "C-CB" + +# c.andi: 6-bit signed: -32 to 31 +test_instr "c.andi s0, #0" "C-CB" +test_instr "c.andi s0, #1" "C-CB" +test_instr "c.andi s0, #-1" "C-CB" +test_instr "c.andi s0, #15" "C-CB" +test_instr "c.andi s0, #-16" "C-CB" +test_instr "c.andi a0, #31" "C-CB" +test_instr "c.andi a0, #-32" "C-CB" +echo " C-CB: $((PASS - C_CA_PASS)) passed" +C_CB_PASS=$PASS + +echo "" +echo "=== C Extension CJ Format ===" +# c.j: 12-bit signed, must be even: -2048 to 2046 +test_instr "c.j #2" "C-CJ" +test_instr "c.j #-2" "C-CJ" +test_instr "c.j #4" "C-CJ" +test_instr "c.j #-4" "C-CJ" +test_instr "c.j #64" "C-CJ" +test_instr "c.j #-64" "C-CJ" +test_instr "c.j #256" "C-CJ" +test_instr "c.j #-256" "C-CJ" +test_instr "c.j #1024" "C-CJ" +test_instr "c.j #-1024" "C-CJ" +test_instr "c.j #2046" "C-CJ" +test_instr "c.j #-2048" "C-CJ" +echo " C-CJ: $((PASS - C_CB_PASS)) passed" +C_CJ_PASS=$PASS + +echo "" +echo "=== C Extension System ===" +test_instr "c.nop" "C-Sys" +test_instr "c.ebreak" "C-Sys" +echo " C-System: $((PASS - C_CJ_PASS)) passed" +C_SYS_PASS=$PASS + +# ============================================================================ +# Summary +# ============================================================================ + +echo "" +echo "==========================================" +echo "Test Summary" +echo "==========================================" +echo "Total: $((PASS + FAIL))" +echo "Passed: $PASS" +echo "Failed: $FAIL" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + exit 1 +else + echo "" + echo "All tests passed!" + echo "" + echo "==========================================" + echo "Full range validation complete!" + echo "==========================================" + exit 0 +fi diff --git a/tests/riscv/test_harnesses/test_a_extension.sh b/tests/riscv/test_harnesses/test_a_extension.sh new file mode 100755 index 0000000..23d44d2 --- /dev/null +++ b/tests/riscv/test_harnesses/test_a_extension.sh @@ -0,0 +1,248 @@ +#!/bin/bash + +# Test Harness for A Extension +# Performs round-trip assemble/disassemble comparison for all .asm files +# Generates fresh .bin and .disasm files each time + +# Get the directory where this script is located +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +# Navigate to project root (from tests/riscv/test_harnesses/ to root) +cd "$SCRIPT_DIR/../../.." +PROJECT_ROOT="$(pwd)" +GOODASM="$PROJECT_ROOT/build/goodasm" + +# Extension directory +EXTENSION_DIR="$PROJECT_ROOT/tests/riscv/a-extension" +EXTENSION_NAME="A Extension" + +# Arrays for tracking results +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + base_name="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local bin_file="$EXTENSION_DIR/${base_name}.bin" + local disasm_file="$EXTENSION_DIR/${base_name}.disasm" + + # Assemble the file (generates fresh binary) + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$base_name - Assembly failed") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$base_name - Empty binary file") + return 1 + fi + + # Disassemble the binary (generates fresh disassembly) + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$base_name - Disassembly failed") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples) + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits) + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + else + # Normalize hex values to decimal for comparison + # Convert hex immediates like #0xfffff801 to #-2047 + # This handles format differences between decimal and hex representation + local original_normalized_hex=$(echo "$original_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + local disasm_normalized_hex=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + + local original_lower=$(echo "$original_normalized_hex" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized_hex" | tr '[:upper:]' '[:lower:]') + + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + fi + done + + return 0 +} + +# Main test execution +echo "==========================================" +echo "Test Harness: $EXTENSION_NAME" +echo "==========================================" +echo "Extension directory: $EXTENSION_DIR" +echo "" + +# Check if extension directory exists +if [ ! -d "$EXTENSION_DIR" ]; then + echo "Error: Extension directory not found: $EXTENSION_DIR" + exit 1 +fi + +# Find all .asm files in the extension directory +for asm_file in "$EXTENSION_DIR"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$base_name"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Test Summary: $EXTENSION_NAME" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_harnesses/test_c_extension.sh b/tests/riscv/test_harnesses/test_c_extension.sh new file mode 100755 index 0000000..cbcbf97 --- /dev/null +++ b/tests/riscv/test_harnesses/test_c_extension.sh @@ -0,0 +1,248 @@ +#!/bin/bash + +# Test Harness for C Extension +# Performs round-trip assemble/disassemble comparison for all .asm files +# Generates fresh .bin and .disasm files each time + +# Get the directory where this script is located +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +# Navigate to project root (from tests/riscv/test_harnesses/ to root) +cd "$SCRIPT_DIR/../../.." +PROJECT_ROOT="$(pwd)" +GOODASM="$PROJECT_ROOT/build/goodasm" + +# Extension directory +EXTENSION_DIR="$PROJECT_ROOT/tests/riscv/c-extension" +EXTENSION_NAME="C Extension" + +# Arrays for tracking results +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + base_name="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local bin_file="$EXTENSION_DIR/${base_name}.bin" + local disasm_file="$EXTENSION_DIR/${base_name}.disasm" + + # Assemble the file (generates fresh binary) + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$base_name - Assembly failed") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$base_name - Empty binary file") + return 1 + fi + + # Disassemble the binary (generates fresh disassembly) + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$base_name - Disassembly failed") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples) + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits) + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + else + # Normalize hex values to decimal for comparison + # Convert hex immediates like #0xfffff801 to #-2047 + # This handles format differences between decimal and hex representation + local original_normalized_hex=$(echo "$original_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + local disasm_normalized_hex=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + + local original_lower=$(echo "$original_normalized_hex" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized_hex" | tr '[:upper:]' '[:lower:]') + + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + fi + done + + return 0 +} + +# Main test execution +echo "==========================================" +echo "Test Harness: $EXTENSION_NAME" +echo "==========================================" +echo "Extension directory: $EXTENSION_DIR" +echo "" + +# Check if extension directory exists +if [ ! -d "$EXTENSION_DIR" ]; then + echo "Error: Extension directory not found: $EXTENSION_DIR" + exit 1 +fi + +# Find all .asm files in the extension directory +for asm_file in "$EXTENSION_DIR"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$base_name"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Test Summary: $EXTENSION_NAME" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_harnesses/test_d_extension.sh b/tests/riscv/test_harnesses/test_d_extension.sh new file mode 100755 index 0000000..ca26e67 --- /dev/null +++ b/tests/riscv/test_harnesses/test_d_extension.sh @@ -0,0 +1,248 @@ +#!/bin/bash + +# Test Harness for D Extension +# Performs round-trip assemble/disassemble comparison for all .asm files +# Generates fresh .bin and .disasm files each time + +# Get the directory where this script is located +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +# Navigate to project root (from tests/riscv/test_harnesses/ to root) +cd "$SCRIPT_DIR/../../.." +PROJECT_ROOT="$(pwd)" +GOODASM="$PROJECT_ROOT/build/goodasm" + +# Extension directory +EXTENSION_DIR="$PROJECT_ROOT/tests/riscv/d-extension" +EXTENSION_NAME="D Extension" + +# Arrays for tracking results +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + base_name="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local bin_file="$EXTENSION_DIR/${base_name}.bin" + local disasm_file="$EXTENSION_DIR/${base_name}.disasm" + + # Assemble the file (generates fresh binary) + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$base_name - Assembly failed") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$base_name - Empty binary file") + return 1 + fi + + # Disassemble the binary (generates fresh disassembly) + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$base_name - Disassembly failed") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples) + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits) + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + else + # Normalize hex values to decimal for comparison + # Convert hex immediates like #0xfffff801 to #-2047 + # This handles format differences between decimal and hex representation + local original_normalized_hex=$(echo "$original_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + local disasm_normalized_hex=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + + local original_lower=$(echo "$original_normalized_hex" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized_hex" | tr '[:upper:]' '[:lower:]') + + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + fi + done + + return 0 +} + +# Main test execution +echo "==========================================" +echo "Test Harness: $EXTENSION_NAME" +echo "==========================================" +echo "Extension directory: $EXTENSION_DIR" +echo "" + +# Check if extension directory exists +if [ ! -d "$EXTENSION_DIR" ]; then + echo "Error: Extension directory not found: $EXTENSION_DIR" + exit 1 +fi + +# Find all .asm files in the extension directory +for asm_file in "$EXTENSION_DIR"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$base_name"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Test Summary: $EXTENSION_NAME" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_harnesses/test_f_extension.sh b/tests/riscv/test_harnesses/test_f_extension.sh new file mode 100755 index 0000000..83897d2 --- /dev/null +++ b/tests/riscv/test_harnesses/test_f_extension.sh @@ -0,0 +1,248 @@ +#!/bin/bash + +# Test Harness for F Extension +# Performs round-trip assemble/disassemble comparison for all .asm files +# Generates fresh .bin and .disasm files each time + +# Get the directory where this script is located +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +# Navigate to project root (from tests/riscv/test_harnesses/ to root) +cd "$SCRIPT_DIR/../../.." +PROJECT_ROOT="$(pwd)" +GOODASM="$PROJECT_ROOT/build/goodasm" + +# Extension directory +EXTENSION_DIR="$PROJECT_ROOT/tests/riscv/f-extension" +EXTENSION_NAME="F Extension" + +# Arrays for tracking results +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + base_name="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local bin_file="$EXTENSION_DIR/${base_name}.bin" + local disasm_file="$EXTENSION_DIR/${base_name}.disasm" + + # Assemble the file (generates fresh binary) + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$base_name - Assembly failed") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$base_name - Empty binary file") + return 1 + fi + + # Disassemble the binary (generates fresh disassembly) + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$base_name - Disassembly failed") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples) + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits) + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + else + # Normalize hex values to decimal for comparison + # Convert hex immediates like #0xfffff801 to #-2047 + # This handles format differences between decimal and hex representation + local original_normalized_hex=$(echo "$original_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + local disasm_normalized_hex=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + + local original_lower=$(echo "$original_normalized_hex" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized_hex" | tr '[:upper:]' '[:lower:]') + + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + fi + done + + return 0 +} + +# Main test execution +echo "==========================================" +echo "Test Harness: $EXTENSION_NAME" +echo "==========================================" +echo "Extension directory: $EXTENSION_DIR" +echo "" + +# Check if extension directory exists +if [ ! -d "$EXTENSION_DIR" ]; then + echo "Error: Extension directory not found: $EXTENSION_DIR" + exit 1 +fi + +# Find all .asm files in the extension directory +for asm_file in "$EXTENSION_DIR"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$base_name"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Test Summary: $EXTENSION_NAME" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_harnesses/test_m_extension.sh b/tests/riscv/test_harnesses/test_m_extension.sh new file mode 100755 index 0000000..d3d6747 --- /dev/null +++ b/tests/riscv/test_harnesses/test_m_extension.sh @@ -0,0 +1,248 @@ +#!/bin/bash + +# Test Harness for M Extension +# Performs round-trip assemble/disassemble comparison for all .asm files +# Generates fresh .bin and .disasm files each time + +# Get the directory where this script is located +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +# Navigate to project root (from tests/riscv/test_harnesses/ to root) +cd "$SCRIPT_DIR/../../.." +PROJECT_ROOT="$(pwd)" +GOODASM="$PROJECT_ROOT/build/goodasm" + +# Extension directory +EXTENSION_DIR="$PROJECT_ROOT/tests/riscv/m-extension" +EXTENSION_NAME="M Extension" + +# Arrays for tracking results +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + base_name="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local bin_file="$EXTENSION_DIR/${base_name}.bin" + local disasm_file="$EXTENSION_DIR/${base_name}.disasm" + + # Assemble the file (generates fresh binary) + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$base_name - Assembly failed") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$base_name - Empty binary file") + return 1 + fi + + # Disassemble the binary (generates fresh disassembly) + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$base_name - Disassembly failed") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples) + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits) + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + else + # Normalize hex values to decimal for comparison + # Convert hex immediates like #0xfffff801 to #-2047 + # This handles format differences between decimal and hex representation + local original_normalized_hex=$(echo "$original_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + local disasm_normalized_hex=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + + local original_lower=$(echo "$original_normalized_hex" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized_hex" | tr '[:upper:]' '[:lower:]') + + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + fi + done + + return 0 +} + +# Main test execution +echo "==========================================" +echo "Test Harness: $EXTENSION_NAME" +echo "==========================================" +echo "Extension directory: $EXTENSION_DIR" +echo "" + +# Check if extension directory exists +if [ ! -d "$EXTENSION_DIR" ]; then + echo "Error: Extension directory not found: $EXTENSION_DIR" + exit 1 +fi + +# Find all .asm files in the extension directory +for asm_file in "$EXTENSION_DIR"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$base_name"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Test Summary: $EXTENSION_NAME" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_harnesses/test_rv32i.sh b/tests/riscv/test_harnesses/test_rv32i.sh new file mode 100755 index 0000000..d44d5d5 --- /dev/null +++ b/tests/riscv/test_harnesses/test_rv32i.sh @@ -0,0 +1,248 @@ +#!/bin/bash + +# Test Harness for RV32I (Base) +# Performs round-trip assemble/disassemble comparison for all .asm files +# Generates fresh .bin and .disasm files each time + +# Get the directory where this script is located +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +# Navigate to project root (from tests/riscv/test_harnesses/ to root) +cd "$SCRIPT_DIR/../../.." +PROJECT_ROOT="$(pwd)" +GOODASM="$PROJECT_ROOT/build/goodasm" + +# Extension directory +EXTENSION_DIR="$PROJECT_ROOT/tests/riscv/rv32i" +EXTENSION_NAME="RV32I (Base)" + +# Arrays for tracking results +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + base_name="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local bin_file="$EXTENSION_DIR/${base_name}.bin" + local disasm_file="$EXTENSION_DIR/${base_name}.disasm" + + # Assemble the file (generates fresh binary) + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$base_name - Assembly failed") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$base_name - Empty binary file") + return 1 + fi + + # Disassemble the binary (generates fresh disassembly) + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$base_name - Disassembly failed") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples) + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits) + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + else + # Normalize hex values to decimal for comparison + # Convert hex immediates like #0xfffff801 to #-2047 + # This handles format differences between decimal and hex representation + local original_normalized_hex=$(echo "$original_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + local disasm_normalized_hex=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + + local original_lower=$(echo "$original_normalized_hex" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized_hex" | tr '[:upper:]' '[:lower:]') + + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + fi + done + + return 0 +} + +# Main test execution +echo "==========================================" +echo "Test Harness: $EXTENSION_NAME" +echo "==========================================" +echo "Extension directory: $EXTENSION_DIR" +echo "" + +# Check if extension directory exists +if [ ! -d "$EXTENSION_DIR" ]; then + echo "Error: Extension directory not found: $EXTENSION_DIR" + exit 1 +fi + +# Find all .asm files in the extension directory +for asm_file in "$EXTENSION_DIR"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$base_name"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Test Summary: $EXTENSION_NAME" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_harnesses/test_zicsr_extension.sh b/tests/riscv/test_harnesses/test_zicsr_extension.sh new file mode 100755 index 0000000..9f195a0 --- /dev/null +++ b/tests/riscv/test_harnesses/test_zicsr_extension.sh @@ -0,0 +1,248 @@ +#!/bin/bash + +# Test Harness for Zicsr Extension +# Performs round-trip assemble/disassemble comparison for all .asm files +# Generates fresh .bin and .disasm files each time + +# Get the directory where this script is located +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +# Navigate to project root (from tests/riscv/test_harnesses/ to root) +cd "$SCRIPT_DIR/../../.." +PROJECT_ROOT="$(pwd)" +GOODASM="$PROJECT_ROOT/build/goodasm" + +# Extension directory +EXTENSION_DIR="$PROJECT_ROOT/tests/riscv/zicsr-extension" +EXTENSION_NAME="Zicsr Extension" + +# Arrays for tracking results +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + base_name="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local bin_file="$EXTENSION_DIR/${base_name}.bin" + local disasm_file="$EXTENSION_DIR/${base_name}.disasm" + + # Assemble the file (generates fresh binary) + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$base_name - Assembly failed") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$base_name - Empty binary file") + return 1 + fi + + # Disassemble the binary (generates fresh disassembly) + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$base_name - Disassembly failed") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples) + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits) + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + else + # Normalize hex values to decimal for comparison + # Convert hex immediates like #0xfffff801 to #-2047 + # This handles format differences between decimal and hex representation + local original_normalized_hex=$(echo "$original_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + local disasm_normalized_hex=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + + local original_lower=$(echo "$original_normalized_hex" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized_hex" | tr '[:upper:]' '[:lower:]') + + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + return 1 + fi + fi + done + + return 0 +} + +# Main test execution +echo "==========================================" +echo "Test Harness: $EXTENSION_NAME" +echo "==========================================" +echo "Extension directory: $EXTENSION_DIR" +echo "" + +# Check if extension directory exists +if [ ! -d "$EXTENSION_DIR" ]; then + echo "Error: Extension directory not found: $EXTENSION_DIR" + exit 1 +fi + +# Find all .asm files in the extension directory +for asm_file in "$EXTENSION_DIR"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$base_name"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Test Summary: $EXTENSION_NAME" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_moderate_validation.sh b/tests/riscv/test_moderate_validation.sh new file mode 100755 index 0000000..172d4ac --- /dev/null +++ b/tests/riscv/test_moderate_validation.sh @@ -0,0 +1,426 @@ +#!/bin/bash +# +# Moderate RISC-V Validation Test +# Tests every instruction with a few representative operand combinations +# Covers edge cases (min/max values, different registers) +# Runtime: ~30-60 seconds +# + +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +cd "$SCRIPT_DIR/../.." +GOODASM="$(pwd)/build/goodasm" + +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + echo "Run 'make' first to build goodasm" + exit 1 +fi + +PASS=0 +FAIL=0 +FAILED_TESTS=() + +# Normalize hex to decimal for comparison +# Converts all #0xNNN patterns to decimal #NNN +normalize_values() { + local input="$1" + # Use Python for reliable hex-to-decimal conversion + echo "$input" | python3 -c " +import sys +import re + +line = sys.stdin.read().strip() + +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Handle 32-bit signed conversion for large values + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) + +# Convert #0x... patterns to decimal +result = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(result, end='') +" +} + +# Test a single instruction roundtrip +test_instr() { + local instr="$1" + local category="$2" + + echo -e ".lang riscv32\n.org 0x0\n$instr" > /tmp/test_mod.asm + "$GOODASM" --riscv32 /tmp/test_mod.asm -o /tmp/test_mod.bin 2>/dev/null + + if [ ! -s /tmp/test_mod.bin ]; then + echo " FAIL: $instr (assembly failed)" + FAILED_TESTS+=("[$category] $instr - assembly failed") + ((FAIL++)) + return 1 + fi + + result=$("$GOODASM" --riscv32 -d /tmp/test_mod.bin 2>/dev/null | grep -v "^Colliding" | grep -v "^[0-9]*: \"" | head -1) + + # Normalize for comparison (lowercase, normalize whitespace, trim) + orig_norm=$(echo "$instr" | tr '[:upper:]' '[:lower:]' | sed 's/[[:space:]]\+/ /g' | sed 's/,\s*/, /g' | sed 's/[[:space:]]*$//') + result_norm=$(echo "$result" | tr '[:upper:]' '[:lower:]' | sed 's/[[:space:]]\+/ /g' | sed 's/,\s*/, /g' | sed 's/[[:space:]]*$//') + + # Normalize hex values to decimal for comparison + orig_norm=$(normalize_values "$orig_norm") + result_norm=$(normalize_values "$result_norm") + + if [ "$orig_norm" = "$result_norm" ]; then + ((PASS++)) + return 0 + else + echo " FAIL: $instr -> $result" + FAILED_TESTS+=("[$category] $instr -> $result") + ((FAIL++)) + return 1 + fi +} + +echo "==========================================" +echo "Moderate RISC-V Validation Test" +echo "==========================================" +echo "Testing every instruction with representative operands..." +echo "" + +# ============================================================================ +# RV32I Base Integer Instructions +# ============================================================================ + +echo "=== R-type ALU (10 instructions × 3 variants = 30 tests) ===" +for op in add sub and or xor sll srl sra slt sltu; do + test_instr "$op t0, t1, t2" "R-$op" + test_instr "$op a0, a1, a2" "R-$op" + test_instr "$op s0, s1, s2" "R-$op" +done +echo " R-type: $PASS passed" +R_PASS=$PASS + +echo "" +echo "=== I-type ALU (7 instructions × 4 variants = 28 tests) ===" +for op in addi andi ori xori slti sltiu; do + test_instr "$op t0, t1, #0" "I-$op" + test_instr "$op t0, t1, #1" "I-$op" + test_instr "$op t0, t1, #-1" "I-$op" + test_instr "$op a0, a1, #2047" "I-$op" +done +# Special case for addi with min value +test_instr "addi t0, t1, #-2048" "I-addi" +test_instr "andi t0, t1, #0x7FF" "I-andi" +test_instr "ori t0, t1, #0x7FF" "I-ori" +test_instr "xori t0, t1, #0x7FF" "I-xori" +echo " I-type ALU: $((PASS - R_PASS)) passed" +I_PASS=$PASS + +echo "" +echo "=== Shift Immediate (3 instructions × 4 variants = 12 tests) ===" +for op in slli srli srai; do + test_instr "$op t0, t1, #0" "Shift-$op" + test_instr "$op t0, t1, #1" "Shift-$op" + test_instr "$op t0, t1, #15" "Shift-$op" + test_instr "$op t0, t1, #31" "Shift-$op" +done +echo " Shift: $((PASS - I_PASS)) passed" +SHIFT_PASS=$PASS + +echo "" +echo "=== Load (6 instructions × 4 variants = 24 tests) ===" +for op in lw lh lb lhu lbu; do + test_instr "$op t0, (#0, t1)" "Load-$op" + test_instr "$op t0, (#4, t1)" "Load-$op" + test_instr "$op t0, (#-4, t1)" "Load-$op" + test_instr "$op a0, (#2047, a1)" "Load-$op" +done +test_instr "lw t0, (#-2048, t1)" "Load-lw" +test_instr "lh t0, (#-2048, t1)" "Load-lh" +test_instr "lb t0, (#-2048, t1)" "Load-lb" +test_instr "lhu t0, (#-2048, t1)" "Load-lhu" +echo " Load: $((PASS - SHIFT_PASS)) passed" +LOAD_PASS=$PASS + +echo "" +echo "=== Store (3 instructions × 4 variants = 12 tests) ===" +for op in sw sh sb; do + test_instr "$op t0, (#0, t1)" "Store-$op" + test_instr "$op t0, (#4, t1)" "Store-$op" + test_instr "$op t0, (#-4, t1)" "Store-$op" + test_instr "$op a0, (#2047, a1)" "Store-$op" +done +echo " Store: $((PASS - LOAD_PASS)) passed" +STORE_PASS=$PASS + +echo "" +echo "=== U-type (2 instructions × 4 variants = 8 tests) ===" +for op in lui auipc; do + test_instr "$op t0, #0x00000000" "U-$op" + test_instr "$op t0, #0x00001000" "U-$op" + test_instr "$op t0, #0x12345000" "U-$op" + test_instr "$op t0, #0xFFFFF000" "U-$op" +done +echo " U-type: $((PASS - STORE_PASS)) passed" +U_PASS=$PASS + +echo "" +echo "=== Branch (6 instructions × 4 variants = 24 tests) ===" +for op in beq bne blt bge bltu bgeu; do + test_instr "$op t0, t1, #4" "Branch-$op" + test_instr "$op t0, t1, #-4" "Branch-$op" + test_instr "$op t0, t1, #256" "Branch-$op" + test_instr "$op a0, a1, #-256" "Branch-$op" +done +echo " Branch: $((PASS - U_PASS)) passed" +BRANCH_PASS=$PASS + +echo "" +echo "=== JAL (1 instruction × 4 variants = 4 tests) ===" +test_instr "jal ra, #4" "JAL" +test_instr "jal ra, #-4" "JAL" +test_instr "jal t0, #1024" "JAL" +test_instr "jal zero, #-1024" "JAL" +echo " JAL: $((PASS - BRANCH_PASS)) passed" +JAL_PASS=$PASS + +echo "" +echo "=== JALR (1 instruction × 4 variants = 4 tests) ===" +test_instr "jalr ra, t0, #0" "JALR" +test_instr "jalr ra, t0, #4" "JALR" +test_instr "jalr ra, t0, #-4" "JALR" +test_instr "jalr t1, a0, #2047" "JALR" +echo " JALR: $((PASS - JAL_PASS)) passed" +JALR_PASS=$PASS + +echo "" +echo "=== System (4 instructions = 4 tests) ===" +test_instr "ecall" "System" +test_instr "ebreak" "System" +test_instr "fence" "System" +test_instr "fence.i" "System" +echo " System: $((PASS - JALR_PASS)) passed" +SYS_PASS=$PASS + +# ============================================================================ +# M Extension - Multiply/Divide +# ============================================================================ + +echo "" +echo "=== M Extension (8 instructions × 2 variants = 16 tests) ===" +for op in mul mulh mulhsu mulhu div divu rem remu; do + test_instr "$op t0, t1, t2" "M-$op" + test_instr "$op a0, a1, a2" "M-$op" +done +echo " M Extension: $((PASS - SYS_PASS)) passed" +M_PASS=$PASS + +# ============================================================================ +# A Extension - Atomics +# ============================================================================ + +echo "" +echo "=== A Extension (11 instructions × 2 variants = 22 tests) ===" +test_instr "lr.w t0, (t1)" "A-lr.w" +test_instr "lr.w a0, (a1)" "A-lr.w" +test_instr "sc.w t0, t2, (t1)" "A-sc.w" +test_instr "sc.w a0, a2, (a1)" "A-sc.w" +for op in amoswap.w amoadd.w amoxor.w amoand.w amoor.w amomin.w amomax.w amominu.w amomaxu.w; do + test_instr "$op t0, t2, (t1)" "A-$op" + test_instr "$op a0, a2, (a1)" "A-$op" +done +echo " A Extension: $((PASS - M_PASS)) passed" +A_PASS=$PASS + +# ============================================================================ +# Zicsr Extension - CSR Instructions +# ============================================================================ + +echo "" +echo "=== Zicsr Extension (6 instructions × 2 variants = 12 tests) ===" +# Using numeric CSR addresses +for op in csrrw csrrs csrrc; do + test_instr "$op t0, #0x300, t1" "Zicsr-$op" + test_instr "$op a0, #0x341, a1" "Zicsr-$op" +done +for op in csrrwi csrrsi csrrci; do + test_instr "$op t0, #0x300, #5" "Zicsr-$op" + test_instr "$op a0, #0x341, #31" "Zicsr-$op" +done +echo " Zicsr: $((PASS - A_PASS)) passed" +ZICSR_PASS=$PASS + +# ============================================================================ +# C Extension - Compressed Instructions +# ============================================================================ + +echo "" +echo "=== C Extension CR Format (4 instructions × 3 variants = 12 tests) ===" +test_instr "c.add a0, a1" "C-CR" +test_instr "c.add s0, s1" "C-CR" +test_instr "c.add a2, a3" "C-CR" +test_instr "c.mv a0, a1" "C-CR" +test_instr "c.mv s0, s1" "C-CR" +test_instr "c.mv a2, a3" "C-CR" +test_instr "c.jr ra" "C-CR" +test_instr "c.jr a0" "C-CR" +test_instr "c.jr a5" "C-CR" +test_instr "c.jalr ra" "C-CR" +test_instr "c.jalr a0" "C-CR" +test_instr "c.jalr a5" "C-CR" +echo " C-CR: $((PASS - ZICSR_PASS)) passed" +C_CR_PASS=$PASS + +echo "" +echo "=== C Extension CI Format (6 instructions × 4-5 variants = 25 tests) ===" +test_instr "c.addi a0, #1" "C-CI" +test_instr "c.addi a0, #-1" "C-CI" +test_instr "c.addi a0, #31" "C-CI" +test_instr "c.addi a0, #-32" "C-CI" +test_instr "c.li a0, #0" "C-CI" +test_instr "c.li a0, #1" "C-CI" +test_instr "c.li a0, #-1" "C-CI" +test_instr "c.li a0, #31" "C-CI" +test_instr "c.slli a0, #1" "C-CI" +test_instr "c.slli a0, #15" "C-CI" +test_instr "c.slli a0, #31" "C-CI" +test_instr "c.slli t0, #5" "C-CI" +test_instr "c.lui a0, #0x1000" "C-CI" +test_instr "c.lui a0, #0x12000" "C-CI" +test_instr "c.lui a0, #0x1F000" "C-CI" +test_instr "c.lui t0, #0x10000" "C-CI" +test_instr "c.addi16sp #16" "C-CI" +test_instr "c.addi16sp #-16" "C-CI" +test_instr "c.addi16sp #496" "C-CI" +test_instr "c.addi16sp #-512" "C-CI" +# c.lwsp: offset is 8-bit unsigned, scaled by 4: 0-252 +test_instr "c.lwsp a0, #0" "C-CI" +test_instr "c.lwsp a0, #4" "C-CI" +test_instr "c.lwsp a0, #64" "C-CI" +test_instr "c.lwsp a0, #124" "C-CI" +test_instr "c.lwsp a1, #252" "C-CI" +echo " C-CI: $((PASS - C_CR_PASS)) passed" +C_CI_PASS=$PASS + +echo "" +echo "=== C Extension CSS Format (1 instruction × 4 variants = 4 tests) ===" +test_instr "c.swsp a0, #0" "C-CSS" +test_instr "c.swsp a0, #4" "C-CSS" +test_instr "c.swsp a0, #252" "C-CSS" +test_instr "c.swsp t0, #128" "C-CSS" +echo " C-CSS: $((PASS - C_CI_PASS)) passed" +C_CSS_PASS=$PASS + +echo "" +echo "=== C Extension CIW Format (1 instruction × 4 variants = 4 tests) ===" +test_instr "c.addi4spn s0, #4" "C-CIW" +test_instr "c.addi4spn s0, #8" "C-CIW" +test_instr "c.addi4spn s0, #256" "C-CIW" +test_instr "c.addi4spn a0, #1020" "C-CIW" +echo " C-CIW: $((PASS - C_CSS_PASS)) passed" +C_CIW_PASS=$PASS + +echo "" +echo "=== C Extension CL Format (1 instruction × 5 variants = 5 tests) ===" +# c.lw: 7-bit offset (5 bits scaled by 4), range 0-124 +test_instr "c.lw s0, (#0, s1)" "C-CL" +test_instr "c.lw s0, (#4, s1)" "C-CL" +test_instr "c.lw a0, (#60, a1)" "C-CL" +test_instr "c.lw a0, (#64, a1)" "C-CL" +test_instr "c.lw a1, (#124, a0)" "C-CL" +echo " C-CL: $((PASS - C_CIW_PASS)) passed" +C_CL_PASS=$PASS + +echo "" +echo "=== C Extension CS Format (1 instruction × 5 variants = 5 tests) ===" +# c.sw: 7-bit offset (5 bits scaled by 4), range 0-124 +test_instr "c.sw s0, (#0, s1)" "C-CS" +test_instr "c.sw s0, (#4, s1)" "C-CS" +test_instr "c.sw a0, (#60, a1)" "C-CS" +test_instr "c.sw a0, (#64, a1)" "C-CS" +test_instr "c.sw a1, (#124, a0)" "C-CS" +echo " C-CS: $((PASS - C_CL_PASS)) passed" +C_CS_PASS=$PASS + +echo "" +echo "=== C Extension CA Format (4 instructions × 2 variants = 8 tests) ===" +for op in c.sub c.xor c.or c.and; do + test_instr "$op s0, s1" "C-CA" + test_instr "$op a0, a1" "C-CA" +done +echo " C-CA: $((PASS - C_CS_PASS)) passed" +C_CA_PASS=$PASS + +echo "" +echo "=== C Extension CB Format (5 instructions × 4 variants = 20 tests) ===" +test_instr "c.beqz s0, #4" "C-CB" +test_instr "c.beqz s0, #-4" "C-CB" +test_instr "c.beqz a0, #254" "C-CB" +test_instr "c.beqz a0, #-256" "C-CB" +test_instr "c.bnez s0, #4" "C-CB" +test_instr "c.bnez s0, #-4" "C-CB" +test_instr "c.bnez a0, #254" "C-CB" +test_instr "c.bnez a0, #-256" "C-CB" +# c.srli/c.srai: 5-bit shift amount for RV32 (0-31) +test_instr "c.srli s0, #1" "C-CB" +test_instr "c.srli s0, #15" "C-CB" +test_instr "c.srli a0, #16" "C-CB" +test_instr "c.srli a1, #31" "C-CB" +test_instr "c.srai s0, #1" "C-CB" +test_instr "c.srai s0, #15" "C-CB" +test_instr "c.srai a0, #16" "C-CB" +test_instr "c.srai a1, #31" "C-CB" +test_instr "c.andi s0, #0" "C-CB" +test_instr "c.andi s0, #31" "C-CB" +test_instr "c.andi a0, #-1" "C-CB" +test_instr "c.andi a0, #-32" "C-CB" +echo " C-CB: $((PASS - C_CA_PASS)) passed" +C_CB_PASS=$PASS + +echo "" +echo "=== C Extension CJ Format (1 instruction × 4 variants = 4 tests) ===" +test_instr "c.j #4" "C-CJ" +test_instr "c.j #-4" "C-CJ" +test_instr "c.j #2046" "C-CJ" +test_instr "c.j #-2048" "C-CJ" +echo " C-CJ: $((PASS - C_CB_PASS)) passed" +C_CJ_PASS=$PASS + +echo "" +echo "=== C Extension System (2 instructions = 2 tests) ===" +test_instr "c.nop" "C-Sys" +test_instr "c.ebreak" "C-Sys" +echo " C-System: $((PASS - C_CJ_PASS)) passed" +C_SYS_PASS=$PASS + +# ============================================================================ +# Summary +# ============================================================================ + +echo "" +echo "==========================================" +echo "Test Summary" +echo "==========================================" +echo "Total: $((PASS + FAIL))" +echo "Passed: $PASS" +echo "Failed: $FAIL" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + exit 1 +else + echo "" + echo "All tests passed!" + echo "" + echo "==========================================" + echo "All known issues have been fixed!" + echo "==========================================" + exit 0 +fi diff --git a/tests/riscv/test_quick_validation.sh b/tests/riscv/test_quick_validation.sh new file mode 100755 index 0000000..826fd79 --- /dev/null +++ b/tests/riscv/test_quick_validation.sh @@ -0,0 +1,238 @@ +#!/bin/bash +# +# Quick RISC-V Validation Test +# Tests representative samples of each instruction category +# Runtime: ~5-10 seconds +# + +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +cd "$SCRIPT_DIR/../.." +GOODASM="$(pwd)/build/goodasm" + +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + echo "Run 'make' first to build goodasm" + exit 1 +fi + +PASS=0 +FAIL=0 +FAILED_TESTS=() + +# Test a single instruction roundtrip +test_instr() { + local instr="$1" + local category="$2" + + echo -e ".lang riscv32\n.org 0x0\n$instr" > /tmp/test_quick.asm + "$GOODASM" --riscv32 /tmp/test_quick.asm -o /tmp/test_quick.bin 2>/dev/null + + if [ ! -s /tmp/test_quick.bin ]; then + echo " FAIL: $instr (assembly failed)" + FAILED_TESTS+=("[$category] $instr - assembly failed") + ((FAIL++)) + return 1 + fi + + result=$("$GOODASM" --riscv32 -d /tmp/test_quick.bin 2>/dev/null | grep -v "^Colliding" | grep -v "^[0-9]*: \"" | head -1) + + # Normalize for comparison (trim whitespace, lowercase, normalize spaces) + orig_norm=$(echo "$instr" | tr '[:upper:]' '[:lower:]' | sed 's/[[:space:]]\+/ /g' | sed 's/,\s*/, /g' | sed 's/[[:space:]]*$//') + result_norm=$(echo "$result" | tr '[:upper:]' '[:lower:]' | sed 's/[[:space:]]\+/ /g' | sed 's/,\s*/, /g' | sed 's/[[:space:]]*$//') + + # Normalize negative hex values (e.g., #0xfffffffb -> #-5) + # This handles 32-bit signed representation + normalize_hex() { + echo "$1" | sed -E 's/#0x([0-9a-f]{8})/\n\1\n/g' | while IFS= read -r part; do + if [[ "$part" =~ ^[0-9a-f]{8}$ ]]; then + val=$((16#$part)) + if [ $val -ge $((0x80000000)) ]; then + val=$((val - 0x100000000)) + fi + echo -n "#$val" + else + echo -n "$part" + fi + done + } + orig_norm=$(normalize_hex "$orig_norm") + result_norm=$(normalize_hex "$result_norm") + + if [ "$orig_norm" = "$result_norm" ]; then + echo " PASS: $instr" + ((PASS++)) + return 0 + else + echo " FAIL: $instr -> $result" + FAILED_TESTS+=("[$category] $instr -> $result") + ((FAIL++)) + return 1 + fi +} + +echo "==========================================" +echo "Quick RISC-V Validation Test" +echo "==========================================" +echo "" + +echo "=== RV32I Base Instructions ===" +test_instr "add t0, t1, t2" "R-type" +test_instr "sub t0, t1, t2" "R-type" +test_instr "and t0, t1, t2" "R-type" +test_instr "or t0, t1, t2" "R-type" +test_instr "xor t0, t1, t2" "R-type" +test_instr "sll t0, t1, t2" "R-type" +test_instr "srl t0, t1, t2" "R-type" +test_instr "sra t0, t1, t2" "R-type" +test_instr "slt t0, t1, t2" "R-type" +test_instr "sltu t0, t1, t2" "R-type" + +echo "" +echo "=== I-type ALU ===" +test_instr "addi t0, t1, #5" "I-type" +test_instr "addi t0, t1, #-5" "I-type" +test_instr "andi t0, t1, #0x1F" "I-type" +test_instr "ori t0, t1, #0xF0" "I-type" +test_instr "xori t0, t1, #0xFF" "I-type" +test_instr "slti t0, t1, #10" "I-type" +test_instr "sltiu t0, t1, #10" "I-type" +test_instr "slli t0, t1, #5" "Shift" +test_instr "srli t0, t1, #5" "Shift" +test_instr "srai t0, t1, #5" "Shift" + +echo "" +echo "=== Load/Store ===" +test_instr "lw a0, (#4, a1)" "Load" +test_instr "lw a0, (#-4, a1)" "Load" +test_instr "lh a0, (#2, a1)" "Load" +test_instr "lb a0, (#1, a1)" "Load" +test_instr "lhu a0, (#2, a1)" "Load" +test_instr "lbu a0, (#1, a1)" "Load" +test_instr "sw a0, (#4, a1)" "Store" +test_instr "sw a0, (#-4, a1)" "Store" +test_instr "sh a0, (#2, a1)" "Store" +test_instr "sb a0, (#1, a1)" "Store" + +echo "" +echo "=== U-type ===" +test_instr "lui t0, #0x12345000" "U-type" +test_instr "auipc t0, #0x12345000" "U-type" + +echo "" +echo "=== Branch ===" +test_instr "beq t0, t1, #4" "Branch" +test_instr "beq t0, t1, #-4" "Branch" +test_instr "bne t0, t1, #8" "Branch" +test_instr "blt t0, t1, #12" "Branch" +test_instr "bge t0, t1, #16" "Branch" +test_instr "bltu t0, t1, #20" "Branch" +test_instr "bgeu t0, t1, #24" "Branch" + +echo "" +echo "=== JAL/JALR ===" +test_instr "jal ra, #4" "JAL" +test_instr "jal ra, #-4" "JAL" +test_instr "jalr ra, t0, #0" "JALR" +test_instr "jalr ra, t0, #4" "JALR" + +echo "" +echo "=== System ===" +test_instr "ecall" "System" +test_instr "ebreak" "System" + +echo "" +echo "=== M Extension ===" +test_instr "mul t0, t1, t2" "M-ext" +test_instr "mulh t0, t1, t2" "M-ext" +test_instr "mulhsu t0, t1, t2" "M-ext" +test_instr "mulhu t0, t1, t2" "M-ext" +test_instr "div t0, t1, t2" "M-ext" +test_instr "divu t0, t1, t2" "M-ext" +test_instr "rem t0, t1, t2" "M-ext" +test_instr "remu t0, t1, t2" "M-ext" + +echo "" +echo "=== A Extension ===" +test_instr "lr.w t0, (t1)" "A-ext" +test_instr "sc.w t0, t2, (t1)" "A-ext" +test_instr "amoswap.w t0, t2, (t1)" "A-ext" +test_instr "amoadd.w t0, t2, (t1)" "A-ext" +test_instr "amoxor.w t0, t2, (t1)" "A-ext" +test_instr "amoand.w t0, t2, (t1)" "A-ext" +test_instr "amoor.w t0, t2, (t1)" "A-ext" + +echo "" +echo "=== Zicsr Extension ===" +test_instr "csrrw t0, #0x300, t1" "Zicsr" +test_instr "csrrs t0, #0x300, t1" "Zicsr" +test_instr "csrrc t0, #0x300, t1" "Zicsr" +test_instr "csrrwi t0, #0x300, #5" "Zicsr" +test_instr "csrrsi t0, #0x300, #5" "Zicsr" +test_instr "csrrci t0, #0x300, #5" "Zicsr" + +echo "" +echo "=== C Extension CR/CI Format ===" +test_instr "c.add a0, a1" "C-CR" +test_instr "c.mv a0, a1" "C-CR" +test_instr "c.jr ra" "C-CR" +test_instr "c.jr a0" "C-CR" +test_instr "c.jalr ra" "C-CR" +test_instr "c.jalr a0" "C-CR" +test_instr "c.addi a0, #5" "C-CI" +test_instr "c.addi a0, #-5" "C-CI" +test_instr "c.slli a0, #3" "C-CI" +test_instr "c.li a0, #10" "C-CI" +test_instr "c.lui a0, #0x12000" "C-CI" + +echo "" +echo "=== C Extension CB/CA Format ===" +test_instr "c.sub s0, s1" "C-CA" +test_instr "c.and s0, s1" "C-CA" +test_instr "c.or s0, s1" "C-CA" +test_instr "c.xor s0, s1" "C-CA" +test_instr "c.beqz s0, #4" "C-CB" +test_instr "c.beqz s0, #-4" "C-CB" +test_instr "c.bnez s0, #6" "C-CB" +test_instr "c.andi s0, #7" "C-CB" +test_instr "c.srli s0, #2" "C-CB" +test_instr "c.srai s0, #2" "C-CB" + +echo "" +echo "=== C Extension CIW/CL/CS/CSS Format ===" +test_instr "c.addi4spn s0, #4" "C-CIW" +test_instr "c.addi4spn s0, #256" "C-CIW" +test_instr "c.lw a0, (#4, a1)" "C-CL" +test_instr "c.sw a0, (#4, a1)" "C-CS" +test_instr "c.lwsp a0, #4" "C-CSS" +test_instr "c.swsp a0, #4" "C-CSS" + +echo "" +echo "=== C Extension CJ Format ===" +test_instr "c.j #4" "C-CJ" +test_instr "c.j #-4" "C-CJ" + +echo "" +echo "=== C Extension System ===" +test_instr "c.nop" "C-Sys" +test_instr "c.ebreak" "C-Sys" + +echo "" +echo "==========================================" +echo "Test Summary" +echo "==========================================" +echo "Total: $((PASS + FAIL))" +echo "Passed: $PASS" +echo "Failed: $FAIL" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi diff --git a/tests/riscv/test_riscv.asm b/tests/riscv/test_riscv.asm new file mode 100644 index 0000000..66de1d6 --- /dev/null +++ b/tests/riscv/test_riscv.asm @@ -0,0 +1,254 @@ +.lang riscv32 +.org 0x0 + +; I-type instruction tests +addi a0, a0, #1 +slti a1, a2, #10 +sltiu a3, a4, #20 +xori a5, a6, #0xFF +ori a7, t0, #0xAA +andi t1, t2, #0xFF + +; I-type shift immediate instruction tests +slli a0, a1, #0 +slli a2, a3, #5 +slli a4, a5, #31 +srli a6, a7, #0 +srli t0, t1, #10 +srli t2, t3, #31 +srai t4, t5, #0 +srai t6, a0, #15 +srai a1, a2, #31 + +; R-type instruction tests +add a0, a1, a2 +sub a0, a1, a2 +sll a0, a1, a2 +slt a0, a1, a2 +sltu a0, a1, a2 +xor a0, a1, a2 +srl a0, a1, a2 +sra a0, a1, a2 +or a0, a1, a2 +and a0, a1, a2 + +; Control Transfer Instructions +; U-type instructions +lui a0, #0x12345 +auipc a1, #0x67890 + +; J-type instructions +jal ra, label1 +label1: + +; I-type control transfer instructions +jalr ra, a1, #0 +jalr a0, a2, #4 + +; B-type branch instructions +beq a0, a1, label2 +bne a0, a1, label3 +blt a0, a1, label4 +bge a0, a1, label5 +bltu a0, a1, label6 +bgeu a0, a1, label7 +label2: +label3: +label4: +label5: +label6: +label7: + +; Load Instructions (I-type) +lb a0, (#4, a1) +lh a2, (#8, a3) +lw a4, (#12, a5) +lbu a6, (#16, a7) +lhu t0, (#20, t1) + +; Store Instructions (S-type) +sb a0, (#4, a1) +sh a2, (#8, a3) +sw a4, (#12, a5) + +; System Instructions +ecall +ebreak +fence.i +fence #0xFF, zero, zero + +; M Extension Instructions (Multiplication and Division) +; Multiplication instructions +mul a0, a1, a2 +mulh a3, a4, a5 +mulhsu a6, a7, t0 +mulhu t1, t2, t3 + +; Division instructions +div a0, a1, a2 +divu a3, a4, a5 + +; Remainder instructions +rem a6, a7, t0 +remu t1, t2, t3 + +; A Extension Instructions (Atomic Memory Operations) +; Load-Reserved and Store-Conditional +lr.w a0, (a1) +sc.w a2, a3, (a4) + +; Atomic Memory Operations +amoswap.w a5, a6, (a7) +amoadd.w t0, t1, (t2) +amoxor.w t3, t4, (t5) +amoand.w t6, a0, (a1) +amoor.w a2, a3, (a4) +amomin.w a5, a6, (a7) +amomax.w t0, t1, (t2) +amominu.w t3, t4, (t5) +amomaxu.w t6, a0, (a1) + +; ZICSR Extension Instructions (CSR Operations) +; Register-based CSR instructions +csrrw a0, #0x300, a1 +csrrs a2, #0x301, a3 +csrrc a4, #0x302, a5 + +; Immediate-based CSR instructions +csrrwi a6, #0x300, #0 +csrrsi a7, #0x301, #15 +csrrci t0, #0x302, #31 + +; F Extension Instructions (Single-Precision Floating-Point) +; Load/Store instructions +flw f0, (#4, a1) +flw f1, (#8, a2) +fsw f0, (#4, a1) +fsw f1, (#8, a2) + +; Fused multiply-add instructions +fmadd.s f0, f1, f2, f3 +fmsub.s f4, f5, f6, f7 +fnmsub.s f8, f9, f10, f11 +fnmadd.s f12, f13, f14, f15 + +; Arithmetic instructions +fadd.s f0, f1, f2 +fsub.s f3, f4, f5 +fmul.s f6, f7, f8 +fdiv.s f9, f10, f11 +fsqrt.s f12, f13 + +; Sign injection instructions +fsgnj.s f0, f1, f2 +fsgnjn.s f3, f4, f5 +fsgnjx.s f6, f7, f8 + +; Min/Max instructions +fmin.s f0, f1, f2 +fmax.s f3, f4, f5 + +; Comparison instructions +feq.s a0, f1, f2 +flt.s a1, f3, f4 +fle.s a2, f5, f6 + +; Conversion instructions +fcvt.w.s a0, f1 +fcvt.wu.s a1, f2 +fcvt.s.w f0, a1 +fcvt.s.wu f1, a2 + +; Move instructions +fmv.x.w a0, f1 +fmv.w.x f0, a1 + +; Classify instruction +fclass.s a0, f1 + +; D Extension Instructions (Double-Precision Floating-Point) +; Load/Store instructions +fld f0, (#8, a1) +fld f1, (#16, a2) +fsd f0, (#8, a1) +fsd f1, (#16, a2) + +; Fused multiply-add instructions +fmadd.d f0, f1, f2, f3 +fmsub.d f4, f5, f6, f7 +fnmsub.d f8, f9, f10, f11 +fnmadd.d f12, f13, f14, f15 + +; Arithmetic instructions +fadd.d f0, f1, f2 +fsub.d f3, f4, f5 +fmul.d f6, f7, f8 +fdiv.d f9, f10, f11 +fsqrt.d f12, f13 + +; Sign injection instructions +fsgnj.d f0, f1, f2 +fsgnjn.d f3, f4, f5 +fsgnjx.d f6, f7, f8 + +; Min/Max instructions +fmin.d f0, f1, f2 +fmax.d f3, f4, f5 + +; Comparison instructions +feq.d a0, f1, f2 +flt.d a1, f3, f4 +fle.d a2, f5, f6 + +; Conversion instructions +fcvt.s.d f0, f1 +fcvt.d.s f1, f2 +fcvt.w.d a0, f1 +fcvt.wu.d a1, f2 +fcvt.d.w f0, a1 +fcvt.d.wu f1, a2 + +; Classify instruction +fclass.d a0, f1 + +; C Extension Instructions (Compressed 16-bit) +; Quadrant 0 instructions (rd' must be a0-a7 or s0-s1, which are x8-x15) +c.addi4spn a0, #16 +c.lw a1, (#4, a2) +c.sw a3, (#4, a4) + +; Quadrant 1 instructions +c.nop +c.addi a5, #5 +c.li a0, #10 +c.addi16sp #-32 +c.lui a1, #1 + +; Quadrant 2 instructions (register-based) - rd' and rs2' must be compressed registers (x8-x15) +c.srli a0, #3 +c.srai a1, #5 +c.andi a2, #0x1F +c.sub a3, a4 +c.xor a5, a0 +c.or a1, a2 +c.and a3, a4 + +; Control flow instructions +c.j label_c1 +label_c1: + +c.beqz a0, label_c2 +label_c2: + +c.bnez a1, label_c3 +label_c3: + +; Special instructions +c.slli a2, #2 +c.lwsp a3, #8 +c.jr a4 +c.mv a5, a0 +c.ebreak +c.jalr a6 +c.add a0, a1 +c.swsp a2, #12 diff --git a/tests/riscv/test_riscv_extensions.sh b/tests/riscv/test_riscv_extensions.sh new file mode 100755 index 0000000..2f34c61 --- /dev/null +++ b/tests/riscv/test_riscv_extensions.sh @@ -0,0 +1,375 @@ +#!/bin/bash + +# Test harness for RISC-V extensions +# Usage: ./test_riscv_extensions.sh [extension1] [extension2] ... +# If no arguments provided, tests all extensions +# Valid extensions: rv32i, c-extension, m-extension, a-extension, f-extension, d-extension, zicsr-extension +# Example: ./test_riscv_extensions.sh rv32i +# Example: ./test_riscv_extensions.sh rv32i m-extension + +cd "$(dirname "$0")" +GOODASM="./build/goodasm" +ERRORS=() +FAILED_TESTS=() +PASSED_TESTS=() +FAILED_INSTRUCTIONS=() +TOTAL_TESTS=0 +TOTAL_PASSED=0 +TOTAL_FAILED=0 + +# Check if goodasm exists +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +# Function to normalize immediate values for comparison +# Handles: negative decimals, hex values with different formatting (#0x0 vs #0x00 vs #0x000) +normalize_immediate() { + local imm="$1" + # Remove # prefix if present + imm=$(echo "$imm" | sed 's/^#//') + + # Check if it's a hex value + if echo "$imm" | grep -qE '^0x[0-9a-fA-F]+$'; then + # Convert hex to decimal, then back to normalized hex + local dec=$(printf "%d" "$imm" 2>/dev/null) + if [ $? -eq 0 ]; then + # Normalize to 32-bit signed, then format as hex + if [ "$dec" -ge 2147483648 ]; then + dec=$((dec - 4294967296)) + fi + printf "#%d" "$dec" + else + echo "#$imm" + fi + elif echo "$imm" | grep -qE '^-?[0-9]+$'; then + # It's already a decimal + echo "#$imm" + else + # Return as-is (might be a register or label) + echo "#$imm" + fi +} + +# Function to normalize an instruction string for comparison +normalize_instruction() { + local instr="$1" + # Replace hex immediates and normalize them + # This is a simplified approach - we'll handle common cases + echo "$instr" | sed -E 's/#0x([0-9a-fA-F]+)/#HEX\1/g' | \ + sed -E 's/#HEX([0-9a-fA-F]+)/$(normalize_hex \1)/g' +} + +# Function to get extension directory and name +get_extension_info() { + local ext="$1" + case "$ext" in + "rv32i") + echo "tests/riscv/rv32i|RV32I (Base)" + ;; + "c-extension") + echo "tests/riscv/c-extension|C Extension" + ;; + "m-extension") + echo "tests/riscv/m-extension|M Extension" + ;; + "a-extension") + echo "tests/riscv/a-extension|A Extension" + ;; + "f-extension") + echo "tests/riscv/f-extension|F Extension" + ;; + "d-extension") + echo "tests/riscv/d-extension|D Extension" + ;; + "zicsr-extension") + echo "tests/riscv/zicsr-extension|Zicsr Extension" + ;; + *) + echo "" + ;; + esac +} + +# Determine which extensions to test +EXTENSIONS_TO_TEST=() +if [ $# -eq 0 ]; then + # No arguments - test all extensions + EXTENSIONS_TO_TEST=("rv32i" "c-extension" "m-extension" "a-extension" "f-extension" "d-extension" "zicsr-extension") +else + # Test only specified extensions + for ext in "$@"; do + ext_info=$(get_extension_info "$ext") + if [ -n "$ext_info" ]; then + EXTENSIONS_TO_TEST+=("$ext") + else + echo "Warning: Unknown extension '$ext'. Valid extensions are:" + echo " - rv32i" + echo " - c-extension" + echo " - m-extension" + echo " - a-extension" + echo " - f-extension" + echo " - d-extension" + echo " - zicsr-extension" + fi + done +fi + +if [ ${#EXTENSIONS_TO_TEST[@]} -eq 0 ]; then + echo "Error: No valid extensions specified" + exit 1 +fi + +# Function to test a single .asm file +test_file() { + local asm_file="$1" + local extension="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local base_name=$(basename "$asm_file" .asm) + local dir=$(dirname "$asm_file") + local bin_file="$dir/${base_name}.bin" + local disasm_file="$dir/${base_name}.disasm" + + # Assemble the file + if ! "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1; then + ERRORS+=("$extension: $base_name - Assembly failed") + FAILED_INSTRUCTIONS+=("$base_name") + return 1 + fi + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + ERRORS+=("$extension: $base_name - Empty binary file") + FAILED_INSTRUCTIONS+=("$base_name") + return 1 + fi + + # Disassemble the binary + if ! "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1; then + ERRORS+=("$extension: $base_name - Disassembly failed") + FAILED_INSTRUCTIONS+=("$base_name") + return 1 + fi + + # Extract all instructions from the original .asm file + local original_instrs=() + while IFS= read -r line; do + if [[ "$line" =~ ^[[:space:]]*$ ]] || \ + [[ "$line" =~ ^[[:space:]]*\.lang ]] || \ + [[ "$line" =~ ^[[:space:]]*\.org ]] || \ + [[ "$line" =~ ^[[:space:]]*\; ]] || \ + [[ "$line" =~ ^[[:space:]]*[a-zA-Z_][a-zA-Z0-9_]*:[[:space:]]*$ ]]; then + continue + fi + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -n "$trimmed" ]; then + original_instrs+=("$trimmed") + fi + done < "$asm_file" + + # Get all disassembled instructions (non-empty lines, excluding collision debug messages) + local disasm_instrs=() + while IFS= read -r line; do + local trimmed=$(echo "$line" | sed 's/^[[:space:]]*//' | sed 's/[[:space:]]*$//') + if [ -z "$trimmed" ]; then + continue + fi + # Skip collision debug messages: + # - Lines starting with "Colliding matches:" + # - Lines matching pattern "^[0-9]+: \"" (numbered collision examples like "1: "c.andi a0, #0xFF"") + if [[ "$trimmed" =~ ^Colliding\ matches: ]] || [[ "$trimmed" =~ ^[0-9]+:\ \ \" ]]; then + continue + fi + # Skip hex byte lines (lines with only whitespace and hex digits, like " 06 ") + # These appear in disassembly output but aren't actual instructions + if [[ "$trimmed" =~ ^[[:space:]]*[0-9a-fA-F]{2}[[:space:]]*$ ]]; then + continue + fi + disasm_instrs+=("$trimmed") + done < "$disasm_file" + + # Check if counts match + if [ ${#original_instrs[@]} -ne ${#disasm_instrs[@]} ]; then + ERRORS+=("$extension: $base_name - Instruction count mismatch (${#original_instrs[@]} vs ${#disasm_instrs[@]})") + FAILED_INSTRUCTIONS+=("$base_name") + return 1 + fi + + # Compare each instruction pair + for i in "${!original_instrs[@]}"; do + local original_instr="${original_instrs[$i]}" + local disasm_instr="${disasm_instrs[$i]}" + + # Normalize by removing extra whitespace, trailing spaces, and comments + local original_normalized=$(echo "$original_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + local disasm_normalized=$(echo "$disasm_instr" | sed 's/;.*$//' | sed 's/[[:space:]]\+/ /g' | sed 's/,[[:space:]]\+/, /g' | sed 's/[[:space:]]*$//') + + # Extract mnemonics (first word) + local original_mnemonic=$(echo "$original_normalized" | cut -d' ' -f1) + local disasm_mnemonic=$(echo "$disasm_normalized" | cut -d' ' -f1) + + # Compare mnemonics first + if [ "$original_mnemonic" != "$disasm_mnemonic" ]; then + ERRORS+=("$extension: $base_name[$((i+1))] - Mnemonic mismatch: '$original_normalized' -> '$disasm_normalized'") + FAILED_INSTRUCTIONS+=("$base_name") + return 1 + fi + + # Check for operand mismatches + local original_ops=$(echo "$original_normalized" | sed 's/^[^ ]* //') + local disasm_ops=$(echo "$disasm_normalized" | sed 's/^[^ ]* //') + + # For instructions with labels, we can't do exact comparison on the label value + if echo "$original_normalized" | grep -q "label"; then + local original_op_count=$(echo "$original_ops" | tr ',' ' ' | wc -w | tr -d ' ') + local disasm_op_count=$(echo "$disasm_ops" | tr ',' ' ' | wc -w | tr -d ' ') + if [ "$original_op_count" != "$disasm_op_count" ]; then + ERRORS+=("$extension: $base_name[$((i+1))] - Operand count mismatch: '$original_normalized' -> '$disasm_normalized'") + FAILED_INSTRUCTIONS+=("$base_name") + return 1 + fi + else + # Normalize hex values to decimal for comparison + # Convert hex immediates like #0xfffff801 to #-2047 + # Also normalize hex formatting (#0x0, #0x00, #0x000 -> same value) + local original_normalized_hex=$(echo "$original_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +# Normalize hex formatting differences (#0x0 vs #0x00 -> keep as decimal now) +print(line, end='') +") + local disasm_normalized_hex=$(echo "$disasm_normalized" | python3 -c " +import sys +import re +line = sys.stdin.read() +# Convert hex to decimal +def hex_to_dec(match): + hex_val = match.group(1) + try: + val = int(hex_val, 16) + # Convert to 32-bit signed + if val >= 0x80000000: + val = val - 0x100000000 + return f'#{val}' + except: + return match.group(0) +line = re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.IGNORECASE) +print(line, end='') +") + + local original_lower=$(echo "$original_normalized_hex" | tr '[:upper:]' '[:lower:]') + local disasm_lower=$(echo "$disasm_normalized_hex" | tr '[:upper:]' '[:lower:]') + + if [ "$original_lower" != "$disasm_lower" ]; then + ERRORS+=("$extension: $base_name[$((i+1))] - Instruction/operand mismatch: '$original_normalized' -> '$disasm_normalized'") + FAILED_INSTRUCTIONS+=("$base_name") + return 1 + fi + fi + done + + return 0 +} + +# Test a directory of .asm files +test_directory() { + local test_dir="$1" + local extension="$2" + + echo "" + echo "==========================================" + echo "Testing $extension" + echo "==========================================" + + if [ ! -d "$test_dir" ]; then + echo " WARNING: Directory $test_dir does not exist" + return + fi + + local dir_passed=0 + local dir_failed=0 + + for asm_file in "$test_dir"/*.asm; do + if [ ! -f "$asm_file" ]; then + continue + fi + + TOTAL_TESTS=$((TOTAL_TESTS + 1)) + local base_name=$(basename "$asm_file" .asm) + + if test_file "$asm_file" "$extension"; then + echo " PASS: $base_name" + PASSED_TESTS+=("$extension: $base_name") + TOTAL_PASSED=$((TOTAL_PASSED + 1)) + dir_passed=$((dir_passed + 1)) + else + echo " FAIL: $base_name" + FAILED_TESTS+=("$extension: $base_name") + TOTAL_FAILED=$((TOTAL_FAILED + 1)) + dir_failed=$((dir_failed + 1)) + fi + done + + echo " Summary: $dir_passed passed, $dir_failed failed" +} + +# Run tests for specified extensions +for ext in "${EXTENSIONS_TO_TEST[@]}"; do + ext_info=$(get_extension_info "$ext") + if [ -n "$ext_info" ]; then + IFS='|' read -r test_dir ext_name <<< "$ext_info" + test_directory "$test_dir" "$ext_name" + fi +done + +# Print summary +echo "" +echo "==========================================" +echo "Overall Test Summary" +echo "==========================================" +echo "Total tests: $TOTAL_TESTS" +echo "Passed: $TOTAL_PASSED" +echo "Failed: $TOTAL_FAILED" + +if [ ${#FAILED_TESTS[@]} -gt 0 ]; then + echo "" + echo "Failed tests:" + for test in "${FAILED_TESTS[@]}"; do + echo " - $test" + done + echo "" + echo "Failed instructions (unique):" + # Get unique failed instructions + printf '%s\n' "${FAILED_INSTRUCTIONS[@]}" | sort -u | while read -r instr; do + echo " - $instr" + done + echo "" + echo "Detailed errors:" + for error in "${ERRORS[@]}"; do + echo " - $error" + done + exit 1 +else + echo "" + echo "All tests passed!" + exit 0 +fi + diff --git a/tests/riscv/test_sample.sh b/tests/riscv/test_sample.sh new file mode 100755 index 0000000..c5b2107 --- /dev/null +++ b/tests/riscv/test_sample.sh @@ -0,0 +1,98 @@ +#!/bin/bash + +# Quick test script that samples a few test files from each extension +# to verify encoding/decoding works + +cd "$(dirname "$0")/../.." +GOODASM="./build/goodasm" + +if [ ! -f "$GOODASM" ]; then + echo "Error: goodasm not found at $GOODASM" + exit 1 +fi + +test_file() { + local asm_file="$1" + local extension="$2" + + if [ ! -f "$asm_file" ]; then + return 1 + fi + + local base_name=$(basename "$asm_file" .asm) + local dir=$(dirname "$asm_file") + local bin_file="$dir/${base_name}.bin" + local disasm_file="$dir/${base_name}.disasm" + + # Assemble (suppress errors but capture them) + "$GOODASM" --riscv32 "$asm_file" -o "$bin_file" > /dev/null 2>&1 + + # Check if binary was created and is not empty + if [ ! -s "$bin_file" ]; then + echo " FAIL: $base_name - Empty or missing binary" + return 1 + fi + + # Disassemble + "$GOODASM" --riscv32 -d "$bin_file" > "$disasm_file" 2>&1 + + # Count instructions in original + local orig_count=$(grep -vE '^\s*$|^\.lang|^\.org|^;|^\s*[a-zA-Z_][a-zA-Z0-9_]*:\s*$' "$asm_file" | wc -l | tr -d ' ') + + # Count instructions in disassembly (skip hex bytes and collision messages) + local disasm_count=$(grep -vE '^\s*$|^Colliding matches:|^\s*[0-9]+:\s+\"|^\s*[0-9a-fA-F]{2}\s*$' "$disasm_file" | wc -l | tr -d ' ') + + if [ "$orig_count" -ne "$disasm_count" ]; then + echo " FAIL: $base_name - Count mismatch ($orig_count vs $disasm_count)" + return 1 + fi + + echo " PASS: $base_name ($orig_count instructions)" + return 0 +} + +echo "Testing sample files from each extension..." +echo "" + +# Test a few files from each extension +echo "RV32I Base:" +test_file "tests/riscv/rv32i/add.asm" "RV32I" +test_file "tests/riscv/rv32i/addi.asm" "RV32I" +test_file "tests/riscv/rv32i/beq.asm" "RV32I" +test_file "tests/riscv/rv32i/lw.asm" "RV32I" +test_file "tests/riscv/rv32i/sw.asm" "RV32I" + +echo "" +echo "C Extension:" +test_file "tests/riscv/c-extension/c_add.asm" "C" +test_file "tests/riscv/c-extension/c_addi.asm" "C" +test_file "tests/riscv/c-extension/c_lw.asm" "C" + +echo "" +echo "M Extension:" +test_file "tests/riscv/m-extension/mul.asm" "M" +test_file "tests/riscv/m-extension/div.asm" "M" + +echo "" +echo "A Extension:" +test_file "tests/riscv/a-extension/lr_w.asm" "A" +test_file "tests/riscv/a-extension/amoadd_w.asm" "A" + +echo "" +echo "F Extension:" +test_file "tests/riscv/f-extension/flw.asm" "F" +test_file "tests/riscv/f-extension/fadd_s.asm" "F" + +echo "" +echo "D Extension:" +test_file "tests/riscv/d-extension/fld.asm" "D" +test_file "tests/riscv/d-extension/fadd_d.asm" "D" + +echo "" +echo "Zicsr Extension:" +test_file "tests/riscv/zicsr-extension/csrrw.asm" "Zicsr" +test_file "tests/riscv/zicsr-extension/csrrwi.asm" "Zicsr" + +echo "" +echo "Done!" + diff --git a/tests/riscv/test_single_instruction.sh b/tests/riscv/test_single_instruction.sh new file mode 100755 index 0000000..7c4ea74 --- /dev/null +++ b/tests/riscv/test_single_instruction.sh @@ -0,0 +1,98 @@ +#!/bin/bash +# Test single RISC-V instruction roundtrip: assemble -> disassemble -> compare + +GOODASM="./build/goodasm" +TMPDIR="/tmp/riscv_test_$$" + +mkdir -p "$TMPDIR" +trap "rm -rf $TMPDIR" EXIT + +test_instruction() { + local instr="$1" + local name="$2" + + # Create assembly file + echo ".lang riscv32" > "$TMPDIR/test.asm" + echo ".org 0x0" >> "$TMPDIR/test.asm" + echo "$instr" >> "$TMPDIR/test.asm" + + # Assemble + if ! "$GOODASM" --riscv32 "$TMPDIR/test.asm" -o "$TMPDIR/test.bin" 2>"$TMPDIR/asm_err.txt"; then + echo "FAIL [$name]: Assembly failed" + cat "$TMPDIR/asm_err.txt" + return 1 + fi + + # Check binary not empty + if [ ! -s "$TMPDIR/test.bin" ]; then + echo "FAIL [$name]: Empty binary" + return 1 + fi + + # Disassemble + local disasm + disasm=$("$GOODASM" --riscv32 -d "$TMPDIR/test.bin" 2>"$TMPDIR/dis_err.txt") + if [ $? -ne 0 ]; then + echo "FAIL [$name]: Disassembly failed" + cat "$TMPDIR/dis_err.txt" + return 1 + fi + + # Normalize both strings for comparison + local orig_norm=$(echo "$instr" | tr '[:upper:]' '[:lower:]' | sed 's/[[:space:]]\+/ /g' | sed 's/^ *//' | sed 's/ *$//') + local dis_norm=$(echo "$disasm" | tr '[:upper:]' '[:lower:]' | sed 's/[[:space:]]\+/ /g' | sed 's/^ *//' | sed 's/ *$//') + + # Handle hex vs decimal immediate normalization + # Convert hex #0x... to decimal for comparison + orig_norm=$(echo "$orig_norm" | python3 -c " +import sys, re +for line in sys.stdin: + def hex_to_dec(m): + v = int(m.group(1), 16) + if v >= 0x80000000: v -= 0x100000000 + return '#' + str(v) + print(re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.I), end='') +" 2>/dev/null || echo "$orig_norm") + + dis_norm=$(echo "$dis_norm" | python3 -c " +import sys, re +for line in sys.stdin: + def hex_to_dec(m): + v = int(m.group(1), 16) + if v >= 0x80000000: v -= 0x100000000 + return '#' + str(v) + print(re.sub(r'#0x([0-9a-fA-F]+)', hex_to_dec, line, flags=re.I), end='') +" 2>/dev/null || echo "$dis_norm") + + if [ "$orig_norm" = "$dis_norm" ]; then + echo "PASS [$name]: $instr" + return 0 + else + echo "FAIL [$name]: Mismatch" + echo " Original: '$instr'" + echo " Disassembled: '$disasm'" + echo " Orig norm: '$orig_norm'" + echo " Dis norm: '$dis_norm'" + return 1 + fi +} + +# Run tests passed as arguments or from stdin +if [ $# -gt 0 ]; then + test_instruction "$1" "${2:-test}" +else + # Read instructions from stdin, one per line + pass=0 + fail=0 + while IFS= read -r line; do + if [ -n "$line" ] && [[ ! "$line" =~ ^# ]]; then + if test_instruction "$line" "$line"; then + ((pass++)) + else + ((fail++)) + fi + fi + done + echo "---" + echo "Total: $((pass + fail)), Passed: $pass, Failed: $fail" +fi diff --git a/tests/riscv/zicsr-extension/csrrc.asm b/tests/riscv/zicsr-extension/csrrc.asm new file mode 100644 index 0000000..88b6956 --- /dev/null +++ b/tests/riscv/zicsr-extension/csrrc.asm @@ -0,0 +1,644 @@ +.lang riscv32 +.org 0x0 + +csrrc zero, #0x0, zero +csrrc zero, #0x1, zero +csrrc zero, #0x2, zero +csrrc zero, #0x300, zero +csrrc zero, #0x301, zero +csrrc zero, #0x304, zero +csrrc zero, #0x305, zero +csrrc zero, #0x340, zero +csrrc zero, #0x341, zero +csrrc zero, #0xfff, zero +csrrc zero, #0x0, ra +csrrc zero, #0x1, ra +csrrc zero, #0x2, ra +csrrc zero, #0x300, ra +csrrc zero, #0x301, ra +csrrc zero, #0x304, ra +csrrc zero, #0x305, ra +csrrc zero, #0x340, ra +csrrc zero, #0x341, ra +csrrc zero, #0xfff, ra +csrrc zero, #0x0, t0 +csrrc zero, #0x1, t0 +csrrc zero, #0x2, t0 +csrrc zero, #0x300, t0 +csrrc zero, #0x301, t0 +csrrc zero, #0x304, t0 +csrrc zero, #0x305, t0 +csrrc zero, #0x340, t0 +csrrc zero, #0x341, t0 +csrrc zero, #0xfff, t0 +csrrc zero, #0x0, a0 +csrrc zero, #0x1, a0 +csrrc zero, #0x2, a0 +csrrc zero, #0x300, a0 +csrrc zero, #0x301, a0 +csrrc zero, #0x304, a0 +csrrc zero, #0x305, a0 +csrrc zero, #0x340, a0 +csrrc zero, #0x341, a0 +csrrc zero, #0xfff, a0 +csrrc zero, #0x0, a5 +csrrc zero, #0x1, a5 +csrrc zero, #0x2, a5 +csrrc zero, #0x300, a5 +csrrc zero, #0x301, a5 +csrrc zero, #0x304, a5 +csrrc zero, #0x305, a5 +csrrc zero, #0x340, a5 +csrrc zero, #0x341, a5 +csrrc zero, #0xfff, a5 +csrrc zero, #0x0, s4 +csrrc zero, #0x1, s4 +csrrc zero, #0x2, s4 +csrrc zero, #0x300, s4 +csrrc zero, #0x301, s4 +csrrc zero, #0x304, s4 +csrrc zero, #0x305, s4 +csrrc zero, #0x340, s4 +csrrc zero, #0x341, s4 +csrrc zero, #0xfff, s4 +csrrc zero, #0x0, s9 +csrrc zero, #0x1, s9 +csrrc zero, #0x2, s9 +csrrc zero, #0x300, s9 +csrrc zero, #0x301, s9 +csrrc zero, #0x304, s9 +csrrc zero, #0x305, s9 +csrrc zero, #0x340, s9 +csrrc zero, #0x341, s9 +csrrc zero, #0xfff, s9 +csrrc zero, #0x0, t6 +csrrc zero, #0x1, t6 +csrrc zero, #0x2, t6 +csrrc zero, #0x300, t6 +csrrc zero, #0x301, t6 +csrrc zero, #0x304, t6 +csrrc zero, #0x305, t6 +csrrc zero, #0x340, t6 +csrrc zero, #0x341, t6 +csrrc zero, #0xfff, t6 +csrrc ra, #0x0, zero +csrrc ra, #0x1, zero +csrrc ra, #0x2, zero +csrrc ra, #0x300, zero +csrrc ra, #0x301, zero +csrrc ra, #0x304, zero +csrrc ra, #0x305, zero +csrrc ra, #0x340, zero +csrrc ra, #0x341, zero +csrrc ra, #0xfff, zero +csrrc ra, #0x0, ra +csrrc ra, #0x1, ra +csrrc ra, #0x2, ra +csrrc ra, #0x300, ra +csrrc ra, #0x301, ra +csrrc ra, #0x304, ra +csrrc ra, #0x305, ra +csrrc ra, #0x340, ra +csrrc ra, #0x341, ra +csrrc ra, #0xfff, ra +csrrc ra, #0x0, t0 +csrrc ra, #0x1, t0 +csrrc ra, #0x2, t0 +csrrc ra, #0x300, t0 +csrrc ra, #0x301, t0 +csrrc ra, #0x304, t0 +csrrc ra, #0x305, t0 +csrrc ra, #0x340, t0 +csrrc ra, #0x341, t0 +csrrc ra, #0xfff, t0 +csrrc ra, #0x0, a0 +csrrc ra, #0x1, a0 +csrrc ra, #0x2, a0 +csrrc ra, #0x300, a0 +csrrc ra, #0x301, a0 +csrrc ra, #0x304, a0 +csrrc ra, #0x305, a0 +csrrc ra, #0x340, a0 +csrrc ra, #0x341, a0 +csrrc ra, #0xfff, a0 +csrrc ra, #0x0, a5 +csrrc ra, #0x1, a5 +csrrc ra, #0x2, a5 +csrrc ra, #0x300, a5 +csrrc ra, #0x301, a5 +csrrc ra, #0x304, a5 +csrrc ra, #0x305, a5 +csrrc ra, #0x340, a5 +csrrc ra, #0x341, a5 +csrrc ra, #0xfff, a5 +csrrc ra, #0x0, s4 +csrrc ra, #0x1, s4 +csrrc ra, #0x2, s4 +csrrc ra, #0x300, s4 +csrrc ra, #0x301, s4 +csrrc ra, #0x304, s4 +csrrc ra, #0x305, s4 +csrrc ra, #0x340, s4 +csrrc ra, #0x341, s4 +csrrc ra, #0xfff, s4 +csrrc ra, #0x0, s9 +csrrc ra, #0x1, s9 +csrrc ra, #0x2, s9 +csrrc ra, #0x300, s9 +csrrc ra, #0x301, s9 +csrrc ra, #0x304, s9 +csrrc ra, #0x305, s9 +csrrc ra, #0x340, s9 +csrrc ra, #0x341, s9 +csrrc ra, #0xfff, s9 +csrrc ra, #0x0, t6 +csrrc ra, #0x1, t6 +csrrc ra, #0x2, t6 +csrrc ra, #0x300, t6 +csrrc ra, #0x301, t6 +csrrc ra, #0x304, t6 +csrrc ra, #0x305, t6 +csrrc ra, #0x340, t6 +csrrc ra, #0x341, t6 +csrrc ra, #0xfff, t6 +csrrc t0, #0x0, zero +csrrc t0, #0x1, zero +csrrc t0, #0x2, zero +csrrc t0, #0x300, zero +csrrc t0, #0x301, zero +csrrc t0, #0x304, zero +csrrc t0, #0x305, zero +csrrc t0, #0x340, zero +csrrc t0, #0x341, zero +csrrc t0, #0xfff, zero +csrrc t0, #0x0, ra +csrrc t0, #0x1, ra +csrrc t0, #0x2, ra +csrrc t0, #0x300, ra +csrrc t0, #0x301, ra +csrrc t0, #0x304, ra +csrrc t0, #0x305, ra +csrrc t0, #0x340, ra +csrrc t0, #0x341, ra +csrrc t0, #0xfff, ra +csrrc t0, #0x0, t0 +csrrc t0, #0x1, t0 +csrrc t0, #0x2, t0 +csrrc t0, #0x300, t0 +csrrc t0, #0x301, t0 +csrrc t0, #0x304, t0 +csrrc t0, #0x305, t0 +csrrc t0, #0x340, t0 +csrrc t0, #0x341, t0 +csrrc t0, #0xfff, t0 +csrrc t0, #0x0, a0 +csrrc t0, #0x1, a0 +csrrc t0, #0x2, a0 +csrrc t0, #0x300, a0 +csrrc t0, #0x301, a0 +csrrc t0, #0x304, a0 +csrrc t0, #0x305, a0 +csrrc t0, #0x340, a0 +csrrc t0, #0x341, a0 +csrrc t0, #0xfff, a0 +csrrc t0, #0x0, a5 +csrrc t0, #0x1, a5 +csrrc t0, #0x2, a5 +csrrc t0, #0x300, a5 +csrrc t0, #0x301, a5 +csrrc t0, #0x304, a5 +csrrc t0, #0x305, a5 +csrrc t0, #0x340, a5 +csrrc t0, #0x341, a5 +csrrc t0, #0xfff, a5 +csrrc t0, #0x0, s4 +csrrc t0, #0x1, s4 +csrrc t0, #0x2, s4 +csrrc t0, #0x300, s4 +csrrc t0, #0x301, s4 +csrrc t0, #0x304, s4 +csrrc t0, #0x305, s4 +csrrc t0, #0x340, s4 +csrrc t0, #0x341, s4 +csrrc t0, #0xfff, s4 +csrrc t0, #0x0, s9 +csrrc t0, #0x1, s9 +csrrc t0, #0x2, s9 +csrrc t0, #0x300, s9 +csrrc t0, #0x301, s9 +csrrc t0, #0x304, s9 +csrrc t0, #0x305, s9 +csrrc t0, #0x340, s9 +csrrc t0, #0x341, s9 +csrrc t0, #0xfff, s9 +csrrc t0, #0x0, t6 +csrrc t0, #0x1, t6 +csrrc t0, #0x2, t6 +csrrc t0, #0x300, t6 +csrrc t0, #0x301, t6 +csrrc t0, #0x304, t6 +csrrc t0, #0x305, t6 +csrrc t0, #0x340, t6 +csrrc t0, #0x341, t6 +csrrc t0, #0xfff, t6 +csrrc a0, #0x0, zero +csrrc a0, #0x1, zero +csrrc a0, #0x2, zero +csrrc a0, #0x300, zero +csrrc a0, #0x301, zero +csrrc a0, #0x304, zero +csrrc a0, #0x305, zero +csrrc a0, #0x340, zero +csrrc a0, #0x341, zero +csrrc a0, #0xfff, zero +csrrc a0, #0x0, ra +csrrc a0, #0x1, ra +csrrc a0, #0x2, ra +csrrc a0, #0x300, ra +csrrc a0, #0x301, ra +csrrc a0, #0x304, ra +csrrc a0, #0x305, ra +csrrc a0, #0x340, ra +csrrc a0, #0x341, ra +csrrc a0, #0xfff, ra +csrrc a0, #0x0, t0 +csrrc a0, #0x1, t0 +csrrc a0, #0x2, t0 +csrrc a0, #0x300, t0 +csrrc a0, #0x301, t0 +csrrc a0, #0x304, t0 +csrrc a0, #0x305, t0 +csrrc a0, #0x340, t0 +csrrc a0, #0x341, t0 +csrrc a0, #0xfff, t0 +csrrc a0, #0x0, a0 +csrrc a0, #0x1, a0 +csrrc a0, #0x2, a0 +csrrc a0, #0x300, a0 +csrrc a0, #0x301, a0 +csrrc a0, #0x304, a0 +csrrc a0, #0x305, a0 +csrrc a0, #0x340, a0 +csrrc a0, #0x341, a0 +csrrc a0, #0xfff, a0 +csrrc a0, #0x0, a5 +csrrc a0, #0x1, a5 +csrrc a0, #0x2, a5 +csrrc a0, #0x300, a5 +csrrc a0, #0x301, a5 +csrrc a0, #0x304, a5 +csrrc a0, #0x305, a5 +csrrc a0, #0x340, a5 +csrrc a0, #0x341, a5 +csrrc a0, #0xfff, a5 +csrrc a0, #0x0, s4 +csrrc a0, #0x1, s4 +csrrc a0, #0x2, s4 +csrrc a0, #0x300, s4 +csrrc a0, #0x301, s4 +csrrc a0, #0x304, s4 +csrrc a0, #0x305, s4 +csrrc a0, #0x340, s4 +csrrc a0, #0x341, s4 +csrrc a0, #0xfff, s4 +csrrc a0, #0x0, s9 +csrrc a0, #0x1, s9 +csrrc a0, #0x2, s9 +csrrc a0, #0x300, s9 +csrrc a0, #0x301, s9 +csrrc a0, #0x304, s9 +csrrc a0, #0x305, s9 +csrrc a0, #0x340, s9 +csrrc a0, #0x341, s9 +csrrc a0, #0xfff, s9 +csrrc a0, #0x0, t6 +csrrc a0, #0x1, t6 +csrrc a0, #0x2, t6 +csrrc a0, #0x300, t6 +csrrc a0, #0x301, t6 +csrrc a0, #0x304, t6 +csrrc a0, #0x305, t6 +csrrc a0, #0x340, t6 +csrrc a0, #0x341, t6 +csrrc a0, #0xfff, t6 +csrrc a5, #0x0, zero +csrrc a5, #0x1, zero +csrrc a5, #0x2, zero +csrrc a5, #0x300, zero +csrrc a5, #0x301, zero +csrrc a5, #0x304, zero +csrrc a5, #0x305, zero +csrrc a5, #0x340, zero +csrrc a5, #0x341, zero +csrrc a5, #0xfff, zero +csrrc a5, #0x0, ra +csrrc a5, #0x1, ra +csrrc a5, #0x2, ra +csrrc a5, #0x300, ra +csrrc a5, #0x301, ra +csrrc a5, #0x304, ra +csrrc a5, #0x305, ra +csrrc a5, #0x340, ra +csrrc a5, #0x341, ra +csrrc a5, #0xfff, ra +csrrc a5, #0x0, t0 +csrrc a5, #0x1, t0 +csrrc a5, #0x2, t0 +csrrc a5, #0x300, t0 +csrrc a5, #0x301, t0 +csrrc a5, #0x304, t0 +csrrc a5, #0x305, t0 +csrrc a5, #0x340, t0 +csrrc a5, #0x341, t0 +csrrc a5, #0xfff, t0 +csrrc a5, #0x0, a0 +csrrc a5, #0x1, a0 +csrrc a5, #0x2, a0 +csrrc a5, #0x300, a0 +csrrc a5, #0x301, a0 +csrrc a5, #0x304, a0 +csrrc a5, #0x305, a0 +csrrc a5, #0x340, a0 +csrrc a5, #0x341, a0 +csrrc a5, #0xfff, a0 +csrrc a5, #0x0, a5 +csrrc a5, #0x1, a5 +csrrc a5, #0x2, a5 +csrrc a5, #0x300, a5 +csrrc a5, #0x301, a5 +csrrc a5, #0x304, a5 +csrrc a5, #0x305, a5 +csrrc a5, #0x340, a5 +csrrc a5, #0x341, a5 +csrrc a5, #0xfff, a5 +csrrc a5, #0x0, s4 +csrrc a5, #0x1, s4 +csrrc a5, #0x2, s4 +csrrc a5, #0x300, s4 +csrrc a5, #0x301, s4 +csrrc a5, #0x304, s4 +csrrc a5, #0x305, s4 +csrrc a5, #0x340, s4 +csrrc a5, #0x341, s4 +csrrc a5, #0xfff, s4 +csrrc a5, #0x0, s9 +csrrc a5, #0x1, s9 +csrrc a5, #0x2, s9 +csrrc a5, #0x300, s9 +csrrc a5, #0x301, s9 +csrrc a5, #0x304, s9 +csrrc a5, #0x305, s9 +csrrc a5, #0x340, s9 +csrrc a5, #0x341, s9 +csrrc a5, #0xfff, s9 +csrrc a5, #0x0, t6 +csrrc a5, #0x1, t6 +csrrc a5, #0x2, t6 +csrrc a5, #0x300, t6 +csrrc a5, #0x301, t6 +csrrc a5, #0x304, t6 +csrrc a5, #0x305, t6 +csrrc a5, #0x340, t6 +csrrc a5, #0x341, t6 +csrrc a5, #0xfff, t6 +csrrc s4, #0x0, zero +csrrc s4, #0x1, zero +csrrc s4, #0x2, zero +csrrc s4, #0x300, zero +csrrc s4, #0x301, zero +csrrc s4, #0x304, zero +csrrc s4, #0x305, zero +csrrc s4, #0x340, zero +csrrc s4, #0x341, zero +csrrc s4, #0xfff, zero +csrrc s4, #0x0, ra +csrrc s4, #0x1, ra +csrrc s4, #0x2, ra +csrrc s4, #0x300, ra +csrrc s4, #0x301, ra +csrrc s4, #0x304, ra +csrrc s4, #0x305, ra +csrrc s4, #0x340, ra +csrrc s4, #0x341, ra +csrrc s4, #0xfff, ra +csrrc s4, #0x0, t0 +csrrc s4, #0x1, t0 +csrrc s4, #0x2, t0 +csrrc s4, #0x300, t0 +csrrc s4, #0x301, t0 +csrrc s4, #0x304, t0 +csrrc s4, #0x305, t0 +csrrc s4, #0x340, t0 +csrrc s4, #0x341, t0 +csrrc s4, #0xfff, t0 +csrrc s4, #0x0, a0 +csrrc s4, #0x1, a0 +csrrc s4, #0x2, a0 +csrrc s4, #0x300, a0 +csrrc s4, #0x301, a0 +csrrc s4, #0x304, a0 +csrrc s4, #0x305, a0 +csrrc s4, #0x340, a0 +csrrc s4, #0x341, a0 +csrrc s4, #0xfff, a0 +csrrc s4, #0x0, a5 +csrrc s4, #0x1, a5 +csrrc s4, #0x2, a5 +csrrc s4, #0x300, a5 +csrrc s4, #0x301, a5 +csrrc s4, #0x304, a5 +csrrc s4, #0x305, a5 +csrrc s4, #0x340, a5 +csrrc s4, #0x341, a5 +csrrc s4, #0xfff, a5 +csrrc s4, #0x0, s4 +csrrc s4, #0x1, s4 +csrrc s4, #0x2, s4 +csrrc s4, #0x300, s4 +csrrc s4, #0x301, s4 +csrrc s4, #0x304, s4 +csrrc s4, #0x305, s4 +csrrc s4, #0x340, s4 +csrrc s4, #0x341, s4 +csrrc s4, #0xfff, s4 +csrrc s4, #0x0, s9 +csrrc s4, #0x1, s9 +csrrc s4, #0x2, s9 +csrrc s4, #0x300, s9 +csrrc s4, #0x301, s9 +csrrc s4, #0x304, s9 +csrrc s4, #0x305, s9 +csrrc s4, #0x340, s9 +csrrc s4, #0x341, s9 +csrrc s4, #0xfff, s9 +csrrc s4, #0x0, t6 +csrrc s4, #0x1, t6 +csrrc s4, #0x2, t6 +csrrc s4, #0x300, t6 +csrrc s4, #0x301, t6 +csrrc s4, #0x304, t6 +csrrc s4, #0x305, t6 +csrrc s4, #0x340, t6 +csrrc s4, #0x341, t6 +csrrc s4, #0xfff, t6 +csrrc s9, #0x0, zero +csrrc s9, #0x1, zero +csrrc s9, #0x2, zero +csrrc s9, #0x300, zero +csrrc s9, #0x301, zero +csrrc s9, #0x304, zero +csrrc s9, #0x305, zero +csrrc s9, #0x340, zero +csrrc s9, #0x341, zero +csrrc s9, #0xfff, zero +csrrc s9, #0x0, ra +csrrc s9, #0x1, ra +csrrc s9, #0x2, ra +csrrc s9, #0x300, ra +csrrc s9, #0x301, ra +csrrc s9, #0x304, ra +csrrc s9, #0x305, ra +csrrc s9, #0x340, ra +csrrc s9, #0x341, ra +csrrc s9, #0xfff, ra +csrrc s9, #0x0, t0 +csrrc s9, #0x1, t0 +csrrc s9, #0x2, t0 +csrrc s9, #0x300, t0 +csrrc s9, #0x301, t0 +csrrc s9, #0x304, t0 +csrrc s9, #0x305, t0 +csrrc s9, #0x340, t0 +csrrc s9, #0x341, t0 +csrrc s9, #0xfff, t0 +csrrc s9, #0x0, a0 +csrrc s9, #0x1, a0 +csrrc s9, #0x2, a0 +csrrc s9, #0x300, a0 +csrrc s9, #0x301, a0 +csrrc s9, #0x304, a0 +csrrc s9, #0x305, a0 +csrrc s9, #0x340, a0 +csrrc s9, #0x341, a0 +csrrc s9, #0xfff, a0 +csrrc s9, #0x0, a5 +csrrc s9, #0x1, a5 +csrrc s9, #0x2, a5 +csrrc s9, #0x300, a5 +csrrc s9, #0x301, a5 +csrrc s9, #0x304, a5 +csrrc s9, #0x305, a5 +csrrc s9, #0x340, a5 +csrrc s9, #0x341, a5 +csrrc s9, #0xfff, a5 +csrrc s9, #0x0, s4 +csrrc s9, #0x1, s4 +csrrc s9, #0x2, s4 +csrrc s9, #0x300, s4 +csrrc s9, #0x301, s4 +csrrc s9, #0x304, s4 +csrrc s9, #0x305, s4 +csrrc s9, #0x340, s4 +csrrc s9, #0x341, s4 +csrrc s9, #0xfff, s4 +csrrc s9, #0x0, s9 +csrrc s9, #0x1, s9 +csrrc s9, #0x2, s9 +csrrc s9, #0x300, s9 +csrrc s9, #0x301, s9 +csrrc s9, #0x304, s9 +csrrc s9, #0x305, s9 +csrrc s9, #0x340, s9 +csrrc s9, #0x341, s9 +csrrc s9, #0xfff, s9 +csrrc s9, #0x0, t6 +csrrc s9, #0x1, t6 +csrrc s9, #0x2, t6 +csrrc s9, #0x300, t6 +csrrc s9, #0x301, t6 +csrrc s9, #0x304, t6 +csrrc s9, #0x305, t6 +csrrc s9, #0x340, t6 +csrrc s9, #0x341, t6 +csrrc s9, #0xfff, t6 +csrrc t6, #0x0, zero +csrrc t6, #0x1, zero +csrrc t6, #0x2, zero +csrrc t6, #0x300, zero +csrrc t6, #0x301, zero +csrrc t6, #0x304, zero +csrrc t6, #0x305, zero +csrrc t6, #0x340, zero +csrrc t6, #0x341, zero +csrrc t6, #0xfff, zero +csrrc t6, #0x0, ra +csrrc t6, #0x1, ra +csrrc t6, #0x2, ra +csrrc t6, #0x300, ra +csrrc t6, #0x301, ra +csrrc t6, #0x304, ra +csrrc t6, #0x305, ra +csrrc t6, #0x340, ra +csrrc t6, #0x341, ra +csrrc t6, #0xfff, ra +csrrc t6, #0x0, t0 +csrrc t6, #0x1, t0 +csrrc t6, #0x2, t0 +csrrc t6, #0x300, t0 +csrrc t6, #0x301, t0 +csrrc t6, #0x304, t0 +csrrc t6, #0x305, t0 +csrrc t6, #0x340, t0 +csrrc t6, #0x341, t0 +csrrc t6, #0xfff, t0 +csrrc t6, #0x0, a0 +csrrc t6, #0x1, a0 +csrrc t6, #0x2, a0 +csrrc t6, #0x300, a0 +csrrc t6, #0x301, a0 +csrrc t6, #0x304, a0 +csrrc t6, #0x305, a0 +csrrc t6, #0x340, a0 +csrrc t6, #0x341, a0 +csrrc t6, #0xfff, a0 +csrrc t6, #0x0, a5 +csrrc t6, #0x1, a5 +csrrc t6, #0x2, a5 +csrrc t6, #0x300, a5 +csrrc t6, #0x301, a5 +csrrc t6, #0x304, a5 +csrrc t6, #0x305, a5 +csrrc t6, #0x340, a5 +csrrc t6, #0x341, a5 +csrrc t6, #0xfff, a5 +csrrc t6, #0x0, s4 +csrrc t6, #0x1, s4 +csrrc t6, #0x2, s4 +csrrc t6, #0x300, s4 +csrrc t6, #0x301, s4 +csrrc t6, #0x304, s4 +csrrc t6, #0x305, s4 +csrrc t6, #0x340, s4 +csrrc t6, #0x341, s4 +csrrc t6, #0xfff, s4 +csrrc t6, #0x0, s9 +csrrc t6, #0x1, s9 +csrrc t6, #0x2, s9 +csrrc t6, #0x300, s9 +csrrc t6, #0x301, s9 +csrrc t6, #0x304, s9 +csrrc t6, #0x305, s9 +csrrc t6, #0x340, s9 +csrrc t6, #0x341, s9 +csrrc t6, #0xfff, s9 +csrrc t6, #0x0, t6 +csrrc t6, #0x1, t6 +csrrc t6, #0x2, t6 +csrrc t6, #0x300, t6 +csrrc t6, #0x301, t6 +csrrc t6, #0x304, t6 +csrrc t6, #0x305, t6 +csrrc t6, #0x340, t6 +csrrc t6, #0x341, t6 +csrrc t6, #0xfff, t6 + diff --git a/tests/riscv/zicsr-extension/csrrc.bin b/tests/riscv/zicsr-extension/csrrc.bin new file mode 100644 index 0000000000000000000000000000000000000000..ed55b141b741263ff4b2e79534dd94931e9a3246 GIT binary patch literal 2560 zcmWmD@rE2t7=`h%tYHir%UIShpAaEJR@v6Hq9R0ykO&bXoQJ#B>f!E*{3okB&+=M6$?D#_{5(Az^^ST+y`$by@2GdwJL(EZ6u|90|BF8ymKZ{>?z`sYr5ySH}dMxM*sjT?C)zI#y}XpI8+-X6-(~C8UjFG_`F@aBa^>4WKFSZd z(mBZK^oZXhevkNhzVj@v<&&)Lz01$jBYuzgJ>uv2&a>#@=l$NhoO>6(U&~Xu@a&{+Y%GQm&e30+5b!#vG^sanA$Sb+>?I0iJhg|6#1iyewz$M@k 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b/tests/riscv/zicsr-extension/csrrc.disasm new file mode 100644 index 0000000..748529c --- /dev/null +++ b/tests/riscv/zicsr-extension/csrrc.disasm @@ -0,0 +1,640 @@ +csrrc zero, #0x000, zero +csrrc zero, #0x001, zero +csrrc zero, #0x002, zero +csrrc zero, #0x300, zero +csrrc zero, #0x301, zero +csrrc zero, #0x304, zero +csrrc zero, #0x305, zero +csrrc zero, #0x340, zero +csrrc zero, #0x341, zero +csrrc zero, #0xFFF, zero +csrrc zero, #0x000, ra +csrrc zero, #0x001, ra +csrrc zero, #0x002, ra +csrrc zero, #0x300, ra +csrrc zero, #0x301, ra +csrrc zero, #0x304, ra +csrrc zero, #0x305, ra +csrrc zero, #0x340, ra +csrrc zero, #0x341, ra +csrrc zero, #0xFFF, ra +csrrc zero, #0x000, t0 +csrrc zero, #0x001, t0 +csrrc zero, #0x002, t0 +csrrc zero, #0x300, t0 +csrrc zero, #0x301, t0 +csrrc zero, #0x304, t0 +csrrc zero, #0x305, t0 +csrrc zero, #0x340, t0 +csrrc zero, #0x341, t0 +csrrc zero, #0xFFF, t0 +csrrc zero, #0x000, a0 +csrrc zero, #0x001, a0 +csrrc zero, #0x002, a0 +csrrc zero, #0x300, a0 +csrrc zero, #0x301, a0 +csrrc zero, #0x304, a0 +csrrc zero, #0x305, a0 +csrrc zero, #0x340, a0 +csrrc zero, #0x341, a0 +csrrc zero, #0xFFF, a0 +csrrc zero, #0x000, a5 +csrrc zero, #0x001, a5 +csrrc zero, #0x002, a5 +csrrc zero, #0x300, a5 +csrrc zero, #0x301, a5 +csrrc zero, #0x304, a5 +csrrc zero, #0x305, a5 +csrrc zero, #0x340, a5 +csrrc zero, #0x341, a5 +csrrc zero, #0xFFF, a5 +csrrc zero, #0x000, s4 +csrrc zero, #0x001, s4 +csrrc zero, #0x002, s4 +csrrc zero, #0x300, s4 +csrrc zero, #0x301, s4 +csrrc zero, #0x304, s4 +csrrc zero, #0x305, s4 +csrrc zero, #0x340, s4 +csrrc zero, #0x341, s4 +csrrc zero, #0xFFF, s4 +csrrc zero, #0x000, s9 +csrrc zero, #0x001, s9 +csrrc zero, #0x002, s9 +csrrc zero, #0x300, s9 +csrrc zero, #0x301, s9 +csrrc zero, #0x304, s9 +csrrc zero, #0x305, s9 +csrrc zero, #0x340, s9 +csrrc zero, #0x341, s9 +csrrc zero, #0xFFF, s9 +csrrc zero, #0x000, t6 +csrrc zero, #0x001, t6 +csrrc zero, #0x002, t6 +csrrc zero, #0x300, t6 +csrrc zero, #0x301, t6 +csrrc zero, #0x304, t6 +csrrc zero, #0x305, t6 +csrrc zero, #0x340, t6 +csrrc zero, #0x341, t6 +csrrc zero, #0xFFF, t6 +csrrc ra, #0x000, zero +csrrc ra, #0x001, zero +csrrc ra, #0x002, zero +csrrc ra, #0x300, zero +csrrc ra, #0x301, zero +csrrc ra, #0x304, zero +csrrc ra, #0x305, zero +csrrc ra, #0x340, zero +csrrc ra, #0x341, zero +csrrc ra, #0xFFF, zero +csrrc ra, #0x000, ra +csrrc ra, #0x001, ra +csrrc ra, #0x002, ra +csrrc ra, #0x300, ra +csrrc ra, #0x301, ra +csrrc ra, #0x304, ra +csrrc ra, #0x305, ra +csrrc ra, #0x340, ra +csrrc ra, #0x341, ra +csrrc ra, #0xFFF, ra +csrrc ra, #0x000, t0 +csrrc ra, #0x001, t0 +csrrc ra, #0x002, t0 +csrrc ra, #0x300, t0 +csrrc ra, #0x301, t0 +csrrc ra, #0x304, t0 +csrrc ra, #0x305, t0 +csrrc ra, #0x340, t0 +csrrc ra, #0x341, t0 +csrrc ra, #0xFFF, t0 +csrrc ra, #0x000, a0 +csrrc ra, #0x001, a0 +csrrc ra, #0x002, a0 +csrrc ra, #0x300, a0 +csrrc ra, #0x301, a0 +csrrc ra, #0x304, a0 +csrrc ra, #0x305, a0 +csrrc ra, #0x340, a0 +csrrc ra, #0x341, a0 +csrrc ra, #0xFFF, a0 +csrrc ra, #0x000, a5 +csrrc ra, #0x001, a5 +csrrc ra, #0x002, a5 +csrrc ra, #0x300, a5 +csrrc ra, #0x301, a5 +csrrc ra, #0x304, a5 +csrrc ra, #0x305, a5 +csrrc ra, #0x340, a5 +csrrc ra, #0x341, a5 +csrrc ra, #0xFFF, a5 +csrrc ra, #0x000, s4 +csrrc ra, #0x001, s4 +csrrc ra, #0x002, s4 +csrrc ra, #0x300, s4 +csrrc ra, #0x301, s4 +csrrc ra, #0x304, s4 +csrrc ra, #0x305, s4 +csrrc ra, #0x340, s4 +csrrc ra, #0x341, s4 +csrrc ra, #0xFFF, s4 +csrrc ra, #0x000, s9 +csrrc ra, #0x001, s9 +csrrc ra, #0x002, s9 +csrrc ra, #0x300, s9 +csrrc ra, #0x301, s9 +csrrc ra, #0x304, s9 +csrrc ra, #0x305, s9 +csrrc ra, #0x340, s9 +csrrc ra, #0x341, s9 +csrrc ra, #0xFFF, s9 +csrrc ra, #0x000, t6 +csrrc ra, #0x001, t6 +csrrc ra, #0x002, t6 +csrrc ra, #0x300, t6 +csrrc ra, #0x301, t6 +csrrc ra, #0x304, t6 +csrrc ra, #0x305, t6 +csrrc ra, #0x340, t6 +csrrc ra, #0x341, t6 +csrrc ra, #0xFFF, t6 +csrrc t0, #0x000, zero +csrrc t0, #0x001, zero +csrrc t0, #0x002, zero +csrrc t0, #0x300, zero +csrrc t0, #0x301, zero +csrrc t0, #0x304, zero +csrrc t0, #0x305, zero +csrrc t0, #0x340, zero +csrrc t0, #0x341, zero +csrrc t0, #0xFFF, zero +csrrc t0, #0x000, ra +csrrc t0, #0x001, ra +csrrc t0, #0x002, ra +csrrc t0, #0x300, ra +csrrc t0, #0x301, ra +csrrc t0, #0x304, ra +csrrc t0, #0x305, ra +csrrc t0, #0x340, ra +csrrc t0, #0x341, ra +csrrc t0, #0xFFF, ra +csrrc t0, #0x000, t0 +csrrc t0, #0x001, t0 +csrrc t0, #0x002, t0 +csrrc t0, #0x300, t0 +csrrc t0, #0x301, t0 +csrrc t0, #0x304, t0 +csrrc t0, #0x305, t0 +csrrc t0, #0x340, t0 +csrrc t0, #0x341, t0 +csrrc t0, #0xFFF, t0 +csrrc t0, #0x000, a0 +csrrc t0, #0x001, a0 +csrrc t0, #0x002, a0 +csrrc t0, #0x300, a0 +csrrc t0, #0x301, a0 +csrrc t0, #0x304, a0 +csrrc t0, #0x305, a0 +csrrc t0, #0x340, a0 +csrrc t0, #0x341, a0 +csrrc t0, #0xFFF, a0 +csrrc t0, #0x000, a5 +csrrc t0, #0x001, a5 +csrrc t0, #0x002, a5 +csrrc t0, #0x300, a5 +csrrc t0, #0x301, a5 +csrrc t0, #0x304, a5 +csrrc t0, #0x305, a5 +csrrc t0, #0x340, a5 +csrrc t0, #0x341, a5 +csrrc t0, #0xFFF, a5 +csrrc t0, #0x000, s4 +csrrc t0, #0x001, s4 +csrrc t0, #0x002, s4 +csrrc t0, #0x300, s4 +csrrc t0, #0x301, s4 +csrrc t0, #0x304, s4 +csrrc t0, #0x305, s4 +csrrc t0, #0x340, s4 +csrrc t0, #0x341, s4 +csrrc t0, #0xFFF, s4 +csrrc t0, #0x000, s9 +csrrc t0, #0x001, s9 +csrrc t0, #0x002, s9 +csrrc t0, #0x300, s9 +csrrc t0, #0x301, s9 +csrrc t0, #0x304, s9 +csrrc t0, #0x305, s9 +csrrc t0, #0x340, s9 +csrrc t0, #0x341, s9 +csrrc t0, #0xFFF, s9 +csrrc t0, #0x000, t6 +csrrc t0, #0x001, t6 +csrrc t0, #0x002, t6 +csrrc t0, #0x300, t6 +csrrc t0, #0x301, t6 +csrrc t0, #0x304, t6 +csrrc t0, #0x305, t6 +csrrc t0, #0x340, t6 +csrrc t0, #0x341, t6 +csrrc t0, #0xFFF, t6 +csrrc a0, #0x000, zero +csrrc a0, #0x001, zero +csrrc a0, #0x002, zero +csrrc a0, #0x300, zero +csrrc a0, #0x301, zero +csrrc a0, #0x304, zero +csrrc a0, #0x305, zero +csrrc a0, #0x340, zero +csrrc a0, #0x341, zero +csrrc a0, #0xFFF, zero +csrrc a0, #0x000, ra +csrrc a0, #0x001, ra +csrrc a0, #0x002, ra +csrrc a0, #0x300, ra +csrrc a0, #0x301, ra +csrrc a0, #0x304, ra +csrrc a0, #0x305, ra +csrrc a0, #0x340, ra +csrrc a0, #0x341, ra +csrrc a0, #0xFFF, ra +csrrc a0, #0x000, t0 +csrrc a0, #0x001, t0 +csrrc a0, #0x002, t0 +csrrc a0, #0x300, t0 +csrrc a0, #0x301, t0 +csrrc a0, #0x304, t0 +csrrc a0, #0x305, t0 +csrrc a0, #0x340, t0 +csrrc a0, #0x341, t0 +csrrc a0, #0xFFF, t0 +csrrc a0, #0x000, a0 +csrrc a0, #0x001, a0 +csrrc a0, #0x002, a0 +csrrc a0, #0x300, a0 +csrrc a0, #0x301, a0 +csrrc a0, #0x304, a0 +csrrc a0, #0x305, a0 +csrrc a0, #0x340, a0 +csrrc a0, #0x341, a0 +csrrc a0, #0xFFF, a0 +csrrc a0, #0x000, a5 +csrrc a0, #0x001, a5 +csrrc a0, #0x002, a5 +csrrc a0, #0x300, a5 +csrrc a0, #0x301, a5 +csrrc a0, #0x304, a5 +csrrc a0, #0x305, a5 +csrrc a0, #0x340, a5 +csrrc a0, #0x341, a5 +csrrc a0, #0xFFF, a5 +csrrc a0, #0x000, s4 +csrrc a0, #0x001, s4 +csrrc a0, #0x002, s4 +csrrc a0, #0x300, s4 +csrrc a0, #0x301, s4 +csrrc a0, #0x304, s4 +csrrc a0, #0x305, s4 +csrrc a0, #0x340, s4 +csrrc a0, #0x341, s4 +csrrc a0, #0xFFF, s4 +csrrc a0, #0x000, s9 +csrrc a0, #0x001, s9 +csrrc a0, #0x002, s9 +csrrc a0, #0x300, s9 +csrrc a0, #0x301, s9 +csrrc a0, #0x304, s9 +csrrc a0, #0x305, s9 +csrrc a0, #0x340, s9 +csrrc a0, #0x341, s9 +csrrc a0, #0xFFF, s9 +csrrc a0, #0x000, t6 +csrrc a0, #0x001, t6 +csrrc a0, #0x002, t6 +csrrc a0, #0x300, t6 +csrrc a0, #0x301, t6 +csrrc a0, #0x304, t6 +csrrc a0, #0x305, t6 +csrrc a0, #0x340, t6 +csrrc a0, #0x341, t6 +csrrc a0, #0xFFF, t6 +csrrc a5, #0x000, zero +csrrc a5, #0x001, zero +csrrc a5, #0x002, zero +csrrc a5, #0x300, zero +csrrc a5, #0x301, zero +csrrc a5, #0x304, zero +csrrc a5, #0x305, zero +csrrc a5, #0x340, zero +csrrc a5, #0x341, zero +csrrc a5, #0xFFF, zero +csrrc a5, #0x000, ra +csrrc a5, #0x001, ra +csrrc a5, #0x002, ra +csrrc a5, #0x300, ra +csrrc a5, #0x301, ra +csrrc a5, #0x304, ra +csrrc a5, #0x305, ra +csrrc a5, #0x340, ra +csrrc a5, #0x341, ra +csrrc a5, #0xFFF, ra +csrrc a5, #0x000, t0 +csrrc a5, #0x001, t0 +csrrc a5, #0x002, t0 +csrrc a5, #0x300, t0 +csrrc a5, #0x301, t0 +csrrc a5, #0x304, t0 +csrrc a5, #0x305, t0 +csrrc a5, #0x340, t0 +csrrc a5, #0x341, t0 +csrrc a5, #0xFFF, t0 +csrrc a5, #0x000, a0 +csrrc a5, #0x001, a0 +csrrc a5, #0x002, a0 +csrrc a5, #0x300, a0 +csrrc a5, #0x301, a0 +csrrc a5, #0x304, a0 +csrrc a5, #0x305, a0 +csrrc a5, #0x340, a0 +csrrc a5, #0x341, a0 +csrrc a5, #0xFFF, a0 +csrrc a5, #0x000, a5 +csrrc a5, #0x001, a5 +csrrc a5, #0x002, a5 +csrrc a5, #0x300, a5 +csrrc a5, #0x301, a5 +csrrc a5, #0x304, a5 +csrrc a5, #0x305, a5 +csrrc a5, #0x340, a5 +csrrc a5, #0x341, a5 +csrrc a5, #0xFFF, a5 +csrrc a5, #0x000, s4 +csrrc a5, #0x001, s4 +csrrc a5, #0x002, s4 +csrrc a5, #0x300, s4 +csrrc a5, #0x301, s4 +csrrc a5, #0x304, s4 +csrrc a5, #0x305, s4 +csrrc a5, #0x340, s4 +csrrc a5, #0x341, s4 +csrrc a5, #0xFFF, s4 +csrrc a5, #0x000, s9 +csrrc a5, #0x001, s9 +csrrc a5, #0x002, s9 +csrrc a5, #0x300, s9 +csrrc a5, #0x301, s9 +csrrc a5, #0x304, s9 +csrrc a5, #0x305, s9 +csrrc a5, #0x340, s9 +csrrc a5, #0x341, s9 +csrrc a5, #0xFFF, s9 +csrrc a5, #0x000, t6 +csrrc a5, #0x001, t6 +csrrc a5, #0x002, t6 +csrrc a5, #0x300, t6 +csrrc a5, #0x301, t6 +csrrc a5, #0x304, t6 +csrrc a5, #0x305, t6 +csrrc a5, #0x340, t6 +csrrc a5, #0x341, t6 +csrrc a5, #0xFFF, t6 +csrrc s4, #0x000, zero +csrrc s4, #0x001, zero +csrrc s4, #0x002, zero +csrrc s4, #0x300, zero +csrrc s4, #0x301, zero +csrrc s4, #0x304, zero +csrrc s4, #0x305, zero +csrrc s4, #0x340, zero +csrrc s4, #0x341, zero +csrrc s4, #0xFFF, zero +csrrc s4, #0x000, ra +csrrc s4, #0x001, ra +csrrc s4, #0x002, ra +csrrc s4, #0x300, ra +csrrc s4, #0x301, ra +csrrc s4, #0x304, ra +csrrc s4, #0x305, ra +csrrc s4, #0x340, ra +csrrc s4, #0x341, ra +csrrc s4, #0xFFF, ra +csrrc s4, #0x000, t0 +csrrc s4, #0x001, t0 +csrrc s4, #0x002, t0 +csrrc s4, #0x300, t0 +csrrc s4, #0x301, t0 +csrrc s4, #0x304, t0 +csrrc s4, #0x305, t0 +csrrc s4, #0x340, t0 +csrrc s4, #0x341, t0 +csrrc s4, #0xFFF, t0 +csrrc s4, #0x000, a0 +csrrc s4, #0x001, a0 +csrrc s4, #0x002, a0 +csrrc s4, #0x300, a0 +csrrc s4, #0x301, a0 +csrrc s4, #0x304, a0 +csrrc s4, #0x305, a0 +csrrc s4, #0x340, a0 +csrrc s4, #0x341, a0 +csrrc s4, #0xFFF, a0 +csrrc s4, #0x000, a5 +csrrc s4, #0x001, a5 +csrrc s4, #0x002, a5 +csrrc s4, #0x300, a5 +csrrc s4, #0x301, a5 +csrrc s4, #0x304, a5 +csrrc s4, #0x305, a5 +csrrc s4, #0x340, a5 +csrrc s4, #0x341, a5 +csrrc s4, #0xFFF, a5 +csrrc s4, #0x000, s4 +csrrc s4, #0x001, s4 +csrrc s4, #0x002, s4 +csrrc s4, #0x300, s4 +csrrc s4, #0x301, s4 +csrrc s4, #0x304, s4 +csrrc s4, #0x305, s4 +csrrc s4, #0x340, s4 +csrrc s4, #0x341, s4 +csrrc s4, #0xFFF, s4 +csrrc s4, #0x000, s9 +csrrc s4, #0x001, s9 +csrrc s4, #0x002, s9 +csrrc s4, #0x300, s9 +csrrc s4, #0x301, s9 +csrrc s4, #0x304, s9 +csrrc s4, #0x305, s9 +csrrc s4, #0x340, s9 +csrrc s4, #0x341, s9 +csrrc s4, #0xFFF, s9 +csrrc s4, #0x000, t6 +csrrc s4, #0x001, t6 +csrrc s4, #0x002, t6 +csrrc s4, #0x300, t6 +csrrc s4, #0x301, t6 +csrrc s4, #0x304, t6 +csrrc s4, #0x305, t6 +csrrc s4, #0x340, t6 +csrrc s4, #0x341, t6 +csrrc s4, #0xFFF, t6 +csrrc s9, #0x000, zero +csrrc s9, #0x001, zero +csrrc s9, #0x002, zero +csrrc s9, #0x300, zero +csrrc s9, #0x301, zero +csrrc s9, #0x304, zero +csrrc s9, #0x305, zero +csrrc s9, #0x340, zero +csrrc s9, #0x341, zero +csrrc s9, #0xFFF, zero +csrrc s9, #0x000, ra +csrrc s9, #0x001, ra +csrrc s9, #0x002, ra +csrrc s9, #0x300, ra +csrrc s9, #0x301, ra +csrrc s9, #0x304, ra +csrrc s9, #0x305, ra +csrrc s9, #0x340, ra +csrrc s9, #0x341, ra +csrrc s9, #0xFFF, ra +csrrc s9, #0x000, t0 +csrrc s9, #0x001, t0 +csrrc s9, #0x002, t0 +csrrc s9, #0x300, t0 +csrrc s9, #0x301, t0 +csrrc s9, #0x304, t0 +csrrc s9, #0x305, t0 +csrrc s9, #0x340, t0 +csrrc s9, #0x341, t0 +csrrc s9, #0xFFF, t0 +csrrc s9, #0x000, a0 +csrrc s9, #0x001, a0 +csrrc s9, #0x002, a0 +csrrc s9, #0x300, a0 +csrrc s9, #0x301, a0 +csrrc s9, #0x304, a0 +csrrc s9, #0x305, a0 +csrrc s9, #0x340, a0 +csrrc s9, #0x341, a0 +csrrc s9, #0xFFF, a0 +csrrc s9, #0x000, a5 +csrrc s9, #0x001, a5 +csrrc s9, #0x002, a5 +csrrc s9, #0x300, a5 +csrrc s9, #0x301, a5 +csrrc s9, #0x304, a5 +csrrc s9, #0x305, a5 +csrrc s9, #0x340, a5 +csrrc s9, #0x341, a5 +csrrc s9, #0xFFF, a5 +csrrc s9, #0x000, s4 +csrrc s9, #0x001, s4 +csrrc s9, #0x002, s4 +csrrc s9, #0x300, s4 +csrrc s9, #0x301, s4 +csrrc s9, #0x304, s4 +csrrc s9, #0x305, s4 +csrrc s9, #0x340, s4 +csrrc s9, #0x341, s4 +csrrc s9, #0xFFF, s4 +csrrc s9, #0x000, s9 +csrrc s9, #0x001, s9 +csrrc s9, #0x002, s9 +csrrc s9, #0x300, s9 +csrrc s9, #0x301, s9 +csrrc s9, #0x304, s9 +csrrc s9, #0x305, s9 +csrrc s9, #0x340, s9 +csrrc s9, #0x341, s9 +csrrc s9, #0xFFF, s9 +csrrc s9, #0x000, t6 +csrrc s9, #0x001, t6 +csrrc s9, #0x002, t6 +csrrc s9, #0x300, t6 +csrrc s9, #0x301, t6 +csrrc s9, #0x304, t6 +csrrc s9, #0x305, t6 +csrrc s9, #0x340, t6 +csrrc s9, #0x341, t6 +csrrc s9, #0xFFF, t6 +csrrc t6, #0x000, zero +csrrc t6, #0x001, zero +csrrc t6, #0x002, zero +csrrc t6, #0x300, zero +csrrc t6, #0x301, zero +csrrc t6, #0x304, zero +csrrc t6, #0x305, zero +csrrc t6, #0x340, zero +csrrc t6, #0x341, zero +csrrc t6, #0xFFF, zero +csrrc t6, #0x000, ra +csrrc t6, #0x001, ra +csrrc t6, #0x002, ra +csrrc t6, #0x300, ra +csrrc t6, #0x301, ra +csrrc t6, #0x304, ra +csrrc t6, #0x305, ra +csrrc t6, #0x340, ra +csrrc t6, #0x341, ra +csrrc t6, #0xFFF, ra +csrrc t6, #0x000, t0 +csrrc t6, #0x001, t0 +csrrc t6, #0x002, t0 +csrrc t6, #0x300, t0 +csrrc t6, #0x301, t0 +csrrc t6, #0x304, t0 +csrrc t6, #0x305, t0 +csrrc t6, #0x340, t0 +csrrc t6, #0x341, t0 +csrrc t6, #0xFFF, t0 +csrrc t6, #0x000, a0 +csrrc t6, #0x001, a0 +csrrc t6, #0x002, a0 +csrrc t6, #0x300, a0 +csrrc t6, #0x301, a0 +csrrc t6, #0x304, a0 +csrrc t6, #0x305, a0 +csrrc t6, #0x340, a0 +csrrc t6, #0x341, a0 +csrrc t6, #0xFFF, a0 +csrrc t6, #0x000, a5 +csrrc t6, #0x001, a5 +csrrc t6, #0x002, a5 +csrrc t6, #0x300, a5 +csrrc t6, #0x301, a5 +csrrc t6, #0x304, a5 +csrrc t6, #0x305, a5 +csrrc t6, #0x340, a5 +csrrc t6, #0x341, a5 +csrrc t6, #0xFFF, a5 +csrrc t6, #0x000, s4 +csrrc t6, #0x001, s4 +csrrc t6, #0x002, s4 +csrrc t6, #0x300, s4 +csrrc t6, #0x301, s4 +csrrc t6, #0x304, s4 +csrrc t6, #0x305, s4 +csrrc t6, #0x340, s4 +csrrc t6, #0x341, s4 +csrrc t6, #0xFFF, s4 +csrrc t6, #0x000, s9 +csrrc t6, #0x001, s9 +csrrc t6, #0x002, s9 +csrrc t6, #0x300, s9 +csrrc t6, #0x301, s9 +csrrc t6, #0x304, s9 +csrrc t6, #0x305, s9 +csrrc t6, #0x340, s9 +csrrc t6, #0x341, s9 +csrrc t6, #0xFFF, s9 +csrrc t6, #0x000, t6 +csrrc t6, #0x001, t6 +csrrc t6, #0x002, t6 +csrrc t6, #0x300, t6 +csrrc t6, #0x301, t6 +csrrc t6, #0x304, t6 +csrrc t6, #0x305, t6 +csrrc t6, #0x340, t6 +csrrc t6, #0x341, t6 +csrrc t6, #0xFFF, t6 diff --git a/tests/riscv/zicsr-extension/csrrci.asm b/tests/riscv/zicsr-extension/csrrci.asm new file mode 100644 index 0000000..52d583d --- /dev/null +++ b/tests/riscv/zicsr-extension/csrrci.asm @@ -0,0 +1,644 @@ +.lang riscv32 +.org 0x0 + +csrrci zero, #0x0, #0 +csrrci zero, #0x1, #0 +csrrci zero, #0x2, #0 +csrrci zero, #0x300, #0 +csrrci zero, #0x301, #0 +csrrci zero, #0x304, #0 +csrrci zero, #0x305, #0 +csrrci zero, #0x340, #0 +csrrci zero, #0x341, #0 +csrrci zero, #0xfff, #0 +csrrci zero, #0x0, #1 +csrrci zero, #0x1, #1 +csrrci zero, #0x2, #1 +csrrci zero, #0x300, #1 +csrrci zero, #0x301, #1 +csrrci zero, #0x304, #1 +csrrci zero, #0x305, #1 +csrrci zero, #0x340, #1 +csrrci zero, #0x341, #1 +csrrci zero, #0xfff, #1 +csrrci zero, #0x0, #5 +csrrci zero, #0x1, #5 +csrrci zero, #0x2, #5 +csrrci zero, #0x300, #5 +csrrci zero, #0x301, #5 +csrrci zero, #0x304, #5 +csrrci zero, #0x305, #5 +csrrci zero, #0x340, #5 +csrrci zero, #0x341, #5 +csrrci zero, #0xfff, #5 +csrrci zero, #0x0, #10 +csrrci zero, #0x1, #10 +csrrci zero, #0x2, #10 +csrrci zero, #0x300, #10 +csrrci zero, #0x301, #10 +csrrci zero, #0x304, #10 +csrrci zero, #0x305, #10 +csrrci zero, #0x340, #10 +csrrci zero, #0x341, #10 +csrrci zero, #0xfff, #10 +csrrci zero, #0x0, #15 +csrrci zero, #0x1, #15 +csrrci zero, #0x2, #15 +csrrci zero, #0x300, #15 +csrrci zero, #0x301, #15 +csrrci zero, #0x304, #15 +csrrci zero, #0x305, #15 +csrrci zero, #0x340, #15 +csrrci zero, #0x341, #15 +csrrci zero, #0xfff, #15 +csrrci zero, #0x0, #20 +csrrci zero, #0x1, #20 +csrrci zero, #0x2, #20 +csrrci zero, #0x300, #20 +csrrci zero, #0x301, #20 +csrrci zero, #0x304, #20 +csrrci zero, #0x305, #20 +csrrci zero, #0x340, #20 +csrrci zero, #0x341, #20 +csrrci zero, #0xfff, #20 +csrrci zero, #0x0, #25 +csrrci zero, #0x1, #25 +csrrci zero, #0x2, #25 +csrrci zero, #0x300, #25 +csrrci zero, #0x301, #25 +csrrci zero, #0x304, #25 +csrrci zero, #0x305, #25 +csrrci zero, #0x340, #25 +csrrci zero, #0x341, #25 +csrrci zero, #0xfff, #25 +csrrci zero, #0x0, #31 +csrrci zero, #0x1, #31 +csrrci zero, #0x2, #31 +csrrci zero, #0x300, #31 +csrrci zero, #0x301, #31 +csrrci zero, #0x304, #31 +csrrci zero, #0x305, #31 +csrrci zero, #0x340, #31 +csrrci zero, #0x341, #31 +csrrci zero, #0xfff, #31 +csrrci ra, #0x0, #0 +csrrci ra, #0x1, #0 +csrrci ra, #0x2, #0 +csrrci ra, #0x300, #0 +csrrci ra, #0x301, #0 +csrrci ra, #0x304, #0 +csrrci ra, #0x305, #0 +csrrci ra, #0x340, #0 +csrrci ra, #0x341, #0 +csrrci ra, #0xfff, #0 +csrrci ra, #0x0, #1 +csrrci ra, #0x1, #1 +csrrci ra, #0x2, #1 +csrrci ra, #0x300, #1 +csrrci ra, #0x301, #1 +csrrci ra, #0x304, #1 +csrrci ra, #0x305, #1 +csrrci ra, #0x340, #1 +csrrci ra, #0x341, #1 +csrrci ra, #0xfff, #1 +csrrci ra, #0x0, #5 +csrrci ra, #0x1, #5 +csrrci ra, #0x2, #5 +csrrci ra, #0x300, #5 +csrrci ra, #0x301, #5 +csrrci ra, #0x304, #5 +csrrci ra, #0x305, #5 +csrrci ra, #0x340, #5 +csrrci ra, #0x341, #5 +csrrci ra, #0xfff, #5 +csrrci ra, #0x0, #10 +csrrci ra, #0x1, #10 +csrrci ra, #0x2, #10 +csrrci ra, #0x300, #10 +csrrci ra, #0x301, #10 +csrrci ra, #0x304, #10 +csrrci ra, #0x305, #10 +csrrci ra, #0x340, #10 +csrrci ra, #0x341, #10 +csrrci ra, #0xfff, #10 +csrrci ra, #0x0, #15 +csrrci ra, #0x1, #15 +csrrci ra, #0x2, #15 +csrrci ra, #0x300, #15 +csrrci ra, #0x301, #15 +csrrci ra, #0x304, #15 +csrrci ra, #0x305, #15 +csrrci ra, #0x340, #15 +csrrci ra, #0x341, #15 +csrrci ra, #0xfff, #15 +csrrci ra, #0x0, #20 +csrrci ra, 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+csrrci a0, #0x305, #31 +csrrci a0, #0x340, #31 +csrrci a0, #0x341, #31 +csrrci a0, #0xFFF, #31 +csrrci a5, #0x000, #0 +csrrci a5, #0x001, #0 +csrrci a5, #0x002, #0 +csrrci a5, #0x300, #0 +csrrci a5, #0x301, #0 +csrrci a5, #0x304, #0 +csrrci a5, #0x305, #0 +csrrci a5, #0x340, #0 +csrrci a5, #0x341, #0 +csrrci a5, #0xFFF, #0 +csrrci a5, #0x000, #1 +csrrci a5, #0x001, #1 +csrrci a5, #0x002, #1 +csrrci a5, #0x300, #1 +csrrci a5, #0x301, #1 +csrrci a5, #0x304, #1 +csrrci a5, #0x305, #1 +csrrci a5, #0x340, #1 +csrrci a5, #0x341, #1 +csrrci a5, #0xFFF, #1 +csrrci a5, #0x000, #5 +csrrci a5, #0x001, #5 +csrrci a5, #0x002, #5 +csrrci a5, #0x300, #5 +csrrci a5, #0x301, #5 +csrrci a5, #0x304, #5 +csrrci a5, #0x305, #5 +csrrci a5, #0x340, #5 +csrrci a5, #0x341, #5 +csrrci a5, #0xFFF, #5 +csrrci a5, #0x000, #10 +csrrci a5, #0x001, #10 +csrrci a5, #0x002, #10 +csrrci a5, #0x300, #10 +csrrci a5, #0x301, #10 +csrrci a5, #0x304, #10 +csrrci a5, #0x305, #10 +csrrci a5, #0x340, #10 +csrrci a5, #0x341, #10 +csrrci a5, #0xFFF, #10 +csrrci a5, #0x000, #15 +csrrci a5, #0x001, #15 +csrrci a5, #0x002, #15 +csrrci a5, #0x300, #15 +csrrci a5, #0x301, #15 +csrrci a5, #0x304, #15 +csrrci a5, #0x305, #15 +csrrci a5, #0x340, #15 +csrrci a5, #0x341, #15 +csrrci a5, #0xFFF, #15 +csrrci a5, #0x000, #20 +csrrci a5, #0x001, #20 +csrrci a5, #0x002, #20 +csrrci a5, #0x300, #20 +csrrci a5, #0x301, #20 +csrrci a5, #0x304, #20 +csrrci a5, #0x305, #20 +csrrci a5, #0x340, #20 +csrrci a5, #0x341, #20 +csrrci a5, #0xFFF, #20 +csrrci a5, #0x000, #25 +csrrci a5, #0x001, #25 +csrrci a5, #0x002, #25 +csrrci a5, #0x300, #25 +csrrci a5, #0x301, #25 +csrrci a5, #0x304, #25 +csrrci a5, #0x305, #25 +csrrci a5, #0x340, #25 +csrrci a5, #0x341, #25 +csrrci a5, #0xFFF, #25 +csrrci a5, #0x000, #31 +csrrci a5, #0x001, #31 +csrrci a5, #0x002, #31 +csrrci a5, #0x300, #31 +csrrci a5, #0x301, #31 +csrrci a5, #0x304, #31 +csrrci a5, #0x305, #31 +csrrci a5, #0x340, #31 +csrrci a5, #0x341, #31 +csrrci a5, #0xFFF, #31 +csrrci s4, #0x000, #0 +csrrci s4, #0x001, #0 +csrrci s4, #0x002, #0 +csrrci s4, #0x300, #0 +csrrci s4, #0x301, #0 +csrrci s4, #0x304, #0 +csrrci s4, #0x305, #0 +csrrci s4, #0x340, #0 +csrrci s4, #0x341, #0 +csrrci s4, #0xFFF, #0 +csrrci s4, #0x000, #1 +csrrci s4, #0x001, #1 +csrrci s4, #0x002, #1 +csrrci s4, #0x300, #1 +csrrci s4, #0x301, #1 +csrrci s4, #0x304, #1 +csrrci s4, #0x305, #1 +csrrci s4, #0x340, #1 +csrrci s4, #0x341, #1 +csrrci s4, #0xFFF, #1 +csrrci s4, #0x000, #5 +csrrci s4, #0x001, #5 +csrrci s4, #0x002, #5 +csrrci s4, #0x300, #5 +csrrci s4, #0x301, #5 +csrrci s4, #0x304, #5 +csrrci s4, #0x305, #5 +csrrci s4, #0x340, #5 +csrrci s4, #0x341, #5 +csrrci s4, #0xFFF, #5 +csrrci s4, #0x000, #10 +csrrci s4, #0x001, #10 +csrrci s4, #0x002, #10 +csrrci s4, #0x300, #10 +csrrci s4, #0x301, #10 +csrrci s4, #0x304, #10 +csrrci s4, #0x305, #10 +csrrci s4, #0x340, #10 +csrrci s4, #0x341, #10 +csrrci s4, #0xFFF, #10 +csrrci s4, #0x000, #15 +csrrci s4, #0x001, #15 +csrrci s4, #0x002, #15 +csrrci s4, #0x300, #15 +csrrci s4, #0x301, #15 +csrrci s4, #0x304, #15 +csrrci s4, #0x305, #15 +csrrci s4, #0x340, #15 +csrrci s4, #0x341, #15 +csrrci s4, #0xFFF, #15 +csrrci s4, #0x000, #20 +csrrci s4, #0x001, #20 +csrrci s4, #0x002, #20 +csrrci s4, #0x300, #20 +csrrci s4, #0x301, #20 +csrrci s4, #0x304, #20 +csrrci s4, #0x305, #20 +csrrci s4, #0x340, #20 +csrrci s4, #0x341, #20 +csrrci s4, #0xFFF, #20 +csrrci s4, #0x000, #25 +csrrci s4, #0x001, #25 +csrrci s4, #0x002, #25 +csrrci s4, #0x300, #25 +csrrci s4, #0x301, #25 +csrrci s4, #0x304, #25 +csrrci s4, #0x305, #25 +csrrci s4, #0x340, #25 +csrrci s4, #0x341, #25 +csrrci s4, #0xFFF, #25 +csrrci s4, #0x000, #31 +csrrci s4, #0x001, #31 +csrrci s4, #0x002, #31 +csrrci s4, #0x300, #31 +csrrci s4, #0x301, #31 +csrrci s4, #0x304, #31 +csrrci s4, #0x305, #31 +csrrci s4, #0x340, #31 +csrrci s4, #0x341, #31 +csrrci s4, #0xFFF, #31 +csrrci s9, #0x000, #0 +csrrci s9, #0x001, #0 +csrrci s9, #0x002, #0 +csrrci s9, #0x300, #0 +csrrci s9, #0x301, #0 +csrrci s9, #0x304, #0 +csrrci s9, #0x305, #0 +csrrci s9, #0x340, #0 +csrrci s9, #0x341, #0 +csrrci s9, #0xFFF, #0 +csrrci s9, #0x000, #1 +csrrci s9, #0x001, #1 +csrrci s9, #0x002, #1 +csrrci s9, #0x300, #1 +csrrci s9, #0x301, #1 +csrrci s9, #0x304, #1 +csrrci s9, #0x305, #1 +csrrci s9, #0x340, #1 +csrrci s9, #0x341, #1 +csrrci s9, #0xFFF, #1 +csrrci s9, #0x000, #5 +csrrci s9, #0x001, #5 +csrrci s9, #0x002, #5 +csrrci s9, #0x300, #5 +csrrci s9, #0x301, #5 +csrrci s9, #0x304, #5 +csrrci s9, #0x305, #5 +csrrci s9, #0x340, #5 +csrrci s9, #0x341, #5 +csrrci s9, #0xFFF, #5 +csrrci s9, #0x000, #10 +csrrci s9, #0x001, #10 +csrrci s9, #0x002, #10 +csrrci s9, #0x300, #10 +csrrci s9, #0x301, #10 +csrrci s9, #0x304, #10 +csrrci s9, #0x305, #10 +csrrci s9, #0x340, #10 +csrrci s9, #0x341, #10 +csrrci s9, #0xFFF, #10 +csrrci s9, #0x000, #15 +csrrci s9, #0x001, #15 +csrrci s9, #0x002, #15 +csrrci s9, #0x300, #15 +csrrci s9, #0x301, #15 +csrrci s9, #0x304, #15 +csrrci s9, #0x305, #15 +csrrci s9, #0x340, #15 +csrrci s9, #0x341, #15 +csrrci s9, #0xFFF, #15 +csrrci s9, #0x000, #20 +csrrci s9, #0x001, #20 +csrrci s9, #0x002, #20 +csrrci s9, #0x300, #20 +csrrci s9, #0x301, #20 +csrrci s9, #0x304, #20 +csrrci s9, #0x305, #20 +csrrci s9, #0x340, #20 +csrrci s9, #0x341, #20 +csrrci s9, #0xFFF, #20 +csrrci s9, #0x000, #25 +csrrci s9, #0x001, #25 +csrrci s9, #0x002, #25 +csrrci s9, #0x300, #25 +csrrci s9, #0x301, #25 +csrrci s9, #0x304, #25 +csrrci s9, #0x305, #25 +csrrci s9, #0x340, #25 +csrrci s9, #0x341, #25 +csrrci s9, #0xFFF, #25 +csrrci s9, #0x000, #31 +csrrci s9, #0x001, #31 +csrrci s9, #0x002, #31 +csrrci s9, #0x300, #31 +csrrci s9, #0x301, #31 +csrrci s9, #0x304, #31 +csrrci s9, #0x305, #31 +csrrci s9, #0x340, #31 +csrrci s9, #0x341, #31 +csrrci s9, #0xFFF, #31 +csrrci t6, #0x000, #0 +csrrci t6, #0x001, #0 +csrrci t6, #0x002, #0 +csrrci t6, #0x300, #0 +csrrci t6, #0x301, #0 +csrrci t6, #0x304, #0 +csrrci t6, #0x305, #0 +csrrci t6, #0x340, #0 +csrrci t6, #0x341, #0 +csrrci t6, #0xFFF, #0 +csrrci t6, #0x000, #1 +csrrci t6, #0x001, #1 +csrrci t6, #0x002, #1 +csrrci t6, #0x300, #1 +csrrci t6, #0x301, #1 +csrrci t6, #0x304, #1 +csrrci t6, #0x305, #1 +csrrci t6, #0x340, #1 +csrrci t6, #0x341, #1 +csrrci t6, #0xFFF, #1 +csrrci t6, #0x000, #5 +csrrci t6, #0x001, #5 +csrrci t6, #0x002, #5 +csrrci t6, #0x300, #5 +csrrci t6, #0x301, #5 +csrrci t6, #0x304, #5 +csrrci t6, #0x305, #5 +csrrci t6, #0x340, #5 +csrrci t6, #0x341, #5 +csrrci t6, #0xFFF, #5 +csrrci t6, #0x000, #10 +csrrci t6, #0x001, #10 +csrrci t6, #0x002, #10 +csrrci t6, #0x300, #10 +csrrci t6, #0x301, #10 +csrrci t6, #0x304, #10 +csrrci t6, #0x305, #10 +csrrci t6, #0x340, #10 +csrrci t6, #0x341, #10 +csrrci t6, #0xFFF, #10 +csrrci t6, #0x000, #15 +csrrci t6, #0x001, #15 +csrrci t6, #0x002, #15 +csrrci t6, #0x300, #15 +csrrci t6, #0x301, #15 +csrrci t6, #0x304, #15 +csrrci t6, #0x305, #15 +csrrci t6, #0x340, #15 +csrrci t6, #0x341, #15 +csrrci t6, #0xFFF, #15 +csrrci t6, #0x000, #20 +csrrci t6, #0x001, #20 +csrrci t6, #0x002, #20 +csrrci t6, #0x300, #20 +csrrci t6, #0x301, #20 +csrrci t6, #0x304, #20 +csrrci t6, #0x305, #20 +csrrci t6, #0x340, #20 +csrrci t6, #0x341, #20 +csrrci t6, #0xFFF, #20 +csrrci t6, #0x000, #25 +csrrci t6, #0x001, #25 +csrrci t6, #0x002, #25 +csrrci t6, #0x300, #25 +csrrci t6, #0x301, #25 +csrrci t6, #0x304, #25 +csrrci t6, #0x305, #25 +csrrci t6, #0x340, #25 +csrrci t6, #0x341, #25 +csrrci t6, #0xFFF, #25 +csrrci t6, #0x000, #31 +csrrci t6, #0x001, #31 +csrrci t6, #0x002, #31 +csrrci t6, #0x300, #31 +csrrci t6, #0x301, #31 +csrrci t6, #0x304, #31 +csrrci t6, #0x305, #31 +csrrci t6, #0x340, #31 +csrrci t6, #0x341, #31 +csrrci t6, #0xFFF, #31 diff --git a/tests/riscv/zicsr-extension/csrrs.asm b/tests/riscv/zicsr-extension/csrrs.asm new file mode 100644 index 0000000..4ba06ed --- /dev/null +++ b/tests/riscv/zicsr-extension/csrrs.asm @@ -0,0 +1,644 @@ +.lang riscv32 +.org 0x0 + +csrrs zero, #0x0, zero +csrrs zero, #0x1, zero +csrrs zero, #0x2, zero +csrrs zero, #0x300, zero +csrrs zero, #0x301, zero +csrrs zero, #0x304, zero +csrrs zero, #0x305, zero +csrrs zero, #0x340, zero +csrrs zero, #0x341, zero +csrrs zero, #0xfff, zero +csrrs zero, #0x0, ra +csrrs zero, #0x1, ra +csrrs zero, #0x2, ra +csrrs zero, #0x300, ra +csrrs zero, #0x301, ra +csrrs zero, #0x304, ra +csrrs zero, #0x305, ra +csrrs zero, #0x340, ra +csrrs zero, #0x341, ra +csrrs zero, #0xfff, ra +csrrs zero, #0x0, t0 +csrrs zero, #0x1, t0 +csrrs zero, #0x2, t0 +csrrs zero, #0x300, t0 +csrrs zero, #0x301, t0 +csrrs zero, #0x304, t0 +csrrs zero, #0x305, t0 +csrrs zero, #0x340, t0 +csrrs zero, #0x341, t0 +csrrs zero, #0xfff, t0 +csrrs zero, #0x0, a0 +csrrs zero, #0x1, a0 +csrrs zero, #0x2, a0 +csrrs zero, #0x300, a0 +csrrs zero, #0x301, a0 +csrrs zero, #0x304, a0 +csrrs zero, #0x305, a0 +csrrs zero, #0x340, a0 +csrrs zero, #0x341, a0 +csrrs zero, #0xfff, a0 +csrrs zero, #0x0, a5 +csrrs zero, #0x1, a5 +csrrs zero, #0x2, a5 +csrrs zero, #0x300, a5 +csrrs zero, #0x301, a5 +csrrs zero, #0x304, a5 +csrrs zero, #0x305, a5 +csrrs zero, #0x340, a5 +csrrs zero, #0x341, a5 +csrrs zero, #0xfff, a5 +csrrs zero, #0x0, s4 +csrrs zero, #0x1, s4 +csrrs zero, #0x2, s4 +csrrs zero, #0x300, s4 +csrrs zero, #0x301, s4 +csrrs zero, #0x304, s4 +csrrs zero, #0x305, s4 +csrrs zero, #0x340, s4 +csrrs zero, #0x341, s4 +csrrs zero, #0xfff, s4 +csrrs zero, #0x0, s9 +csrrs zero, #0x1, s9 +csrrs zero, #0x2, s9 +csrrs zero, #0x300, s9 +csrrs zero, #0x301, s9 +csrrs zero, #0x304, s9 +csrrs zero, #0x305, s9 +csrrs zero, #0x340, s9 +csrrs zero, #0x341, s9 +csrrs zero, #0xfff, s9 +csrrs zero, #0x0, t6 +csrrs zero, #0x1, t6 +csrrs zero, #0x2, t6 +csrrs zero, #0x300, t6 +csrrs zero, #0x301, t6 +csrrs zero, #0x304, t6 +csrrs zero, #0x305, t6 +csrrs zero, #0x340, t6 +csrrs zero, #0x341, t6 +csrrs zero, #0xfff, t6 +csrrs ra, #0x0, zero +csrrs ra, #0x1, zero +csrrs ra, #0x2, zero +csrrs ra, #0x300, zero +csrrs ra, #0x301, zero +csrrs ra, #0x304, zero +csrrs ra, #0x305, zero +csrrs ra, #0x340, zero +csrrs ra, #0x341, zero +csrrs ra, #0xfff, zero +csrrs ra, #0x0, ra +csrrs ra, #0x1, ra +csrrs ra, #0x2, ra +csrrs ra, #0x300, ra +csrrs ra, #0x301, ra +csrrs ra, #0x304, ra +csrrs ra, #0x305, ra +csrrs ra, #0x340, ra +csrrs ra, #0x341, ra +csrrs ra, #0xfff, ra +csrrs ra, #0x0, t0 +csrrs ra, #0x1, t0 +csrrs ra, #0x2, t0 +csrrs ra, #0x300, t0 +csrrs ra, #0x301, t0 +csrrs ra, #0x304, t0 +csrrs ra, #0x305, t0 +csrrs ra, #0x340, t0 +csrrs ra, #0x341, t0 +csrrs ra, #0xfff, t0 +csrrs ra, #0x0, a0 +csrrs ra, #0x1, a0 +csrrs ra, #0x2, a0 +csrrs ra, #0x300, a0 +csrrs ra, #0x301, a0 +csrrs ra, #0x304, a0 +csrrs ra, #0x305, a0 +csrrs ra, #0x340, a0 +csrrs ra, #0x341, a0 +csrrs ra, #0xfff, a0 +csrrs ra, #0x0, a5 +csrrs ra, #0x1, a5 +csrrs ra, #0x2, a5 +csrrs ra, #0x300, a5 +csrrs ra, #0x301, a5 +csrrs ra, #0x304, a5 +csrrs ra, #0x305, a5 +csrrs ra, #0x340, a5 +csrrs ra, #0x341, a5 +csrrs ra, #0xfff, a5 +csrrs ra, #0x0, s4 +csrrs ra, #0x1, s4 +csrrs ra, #0x2, s4 +csrrs ra, #0x300, s4 +csrrs ra, #0x301, s4 +csrrs ra, #0x304, s4 +csrrs ra, #0x305, s4 +csrrs ra, #0x340, s4 +csrrs ra, #0x341, s4 +csrrs ra, #0xfff, s4 +csrrs ra, #0x0, s9 +csrrs ra, #0x1, s9 +csrrs ra, #0x2, s9 +csrrs ra, #0x300, s9 +csrrs ra, #0x301, s9 +csrrs ra, #0x304, s9 +csrrs ra, #0x305, s9 +csrrs ra, #0x340, s9 +csrrs ra, #0x341, s9 +csrrs ra, #0xfff, s9 +csrrs ra, #0x0, t6 +csrrs ra, #0x1, t6 +csrrs ra, #0x2, t6 +csrrs ra, #0x300, t6 +csrrs ra, #0x301, t6 +csrrs ra, #0x304, t6 +csrrs ra, #0x305, t6 +csrrs ra, #0x340, t6 +csrrs ra, #0x341, t6 +csrrs ra, #0xfff, t6 +csrrs t0, #0x0, zero +csrrs t0, #0x1, zero +csrrs t0, #0x2, zero +csrrs t0, #0x300, zero +csrrs t0, #0x301, zero +csrrs t0, #0x304, zero +csrrs t0, #0x305, zero +csrrs t0, #0x340, zero +csrrs t0, #0x341, zero +csrrs t0, #0xfff, zero +csrrs t0, #0x0, ra +csrrs t0, #0x1, ra +csrrs t0, #0x2, ra +csrrs t0, #0x300, ra +csrrs t0, #0x301, ra +csrrs t0, #0x304, ra +csrrs t0, #0x305, ra +csrrs t0, #0x340, ra +csrrs t0, #0x341, ra +csrrs t0, #0xfff, ra +csrrs t0, #0x0, t0 +csrrs t0, #0x1, t0 +csrrs t0, #0x2, t0 +csrrs t0, #0x300, t0 +csrrs t0, #0x301, t0 +csrrs t0, #0x304, t0 +csrrs t0, #0x305, t0 +csrrs t0, #0x340, t0 +csrrs t0, #0x341, t0 +csrrs t0, #0xfff, t0 +csrrs t0, #0x0, a0 +csrrs t0, #0x1, a0 +csrrs t0, #0x2, a0 +csrrs t0, #0x300, a0 +csrrs t0, #0x301, a0 +csrrs t0, #0x304, a0 +csrrs t0, #0x305, a0 +csrrs t0, #0x340, a0 +csrrs t0, #0x341, a0 +csrrs t0, #0xfff, a0 +csrrs t0, #0x0, a5 +csrrs t0, #0x1, a5 +csrrs t0, #0x2, a5 +csrrs t0, #0x300, a5 +csrrs t0, #0x301, a5 +csrrs t0, #0x304, a5 +csrrs t0, #0x305, a5 +csrrs t0, #0x340, a5 +csrrs t0, #0x341, a5 +csrrs t0, #0xfff, a5 +csrrs t0, #0x0, s4 +csrrs t0, #0x1, s4 +csrrs t0, #0x2, s4 +csrrs t0, #0x300, s4 +csrrs t0, #0x301, s4 +csrrs t0, #0x304, s4 +csrrs t0, #0x305, s4 +csrrs t0, #0x340, s4 +csrrs t0, #0x341, s4 +csrrs t0, #0xfff, s4 +csrrs t0, #0x0, s9 +csrrs t0, #0x1, s9 +csrrs t0, #0x2, s9 +csrrs t0, #0x300, s9 +csrrs t0, #0x301, s9 +csrrs t0, #0x304, s9 +csrrs t0, #0x305, s9 +csrrs t0, #0x340, s9 +csrrs t0, #0x341, s9 +csrrs t0, #0xfff, s9 +csrrs t0, #0x0, t6 +csrrs t0, #0x1, t6 +csrrs t0, #0x2, t6 +csrrs t0, #0x300, t6 +csrrs t0, #0x301, t6 +csrrs t0, #0x304, t6 +csrrs t0, #0x305, t6 +csrrs t0, #0x340, t6 +csrrs t0, #0x341, t6 +csrrs t0, #0xfff, t6 +csrrs a0, #0x0, zero +csrrs a0, #0x1, zero +csrrs a0, #0x2, zero +csrrs a0, #0x300, zero +csrrs a0, #0x301, zero +csrrs a0, #0x304, zero +csrrs a0, #0x305, zero +csrrs a0, #0x340, zero +csrrs a0, #0x341, zero +csrrs a0, #0xfff, zero +csrrs a0, #0x0, ra +csrrs a0, #0x1, ra +csrrs a0, #0x2, ra +csrrs a0, #0x300, ra +csrrs a0, #0x301, ra +csrrs a0, #0x304, ra +csrrs a0, #0x305, ra +csrrs a0, #0x340, ra +csrrs a0, #0x341, ra +csrrs a0, #0xfff, ra +csrrs a0, #0x0, t0 +csrrs a0, #0x1, t0 +csrrs a0, #0x2, t0 +csrrs a0, #0x300, t0 +csrrs a0, #0x301, t0 +csrrs a0, #0x304, t0 +csrrs a0, #0x305, t0 +csrrs a0, #0x340, t0 +csrrs a0, #0x341, t0 +csrrs a0, #0xfff, t0 +csrrs a0, #0x0, a0 +csrrs a0, #0x1, a0 +csrrs a0, #0x2, a0 +csrrs a0, #0x300, a0 +csrrs a0, #0x301, a0 +csrrs a0, #0x304, a0 +csrrs a0, #0x305, a0 +csrrs a0, #0x340, a0 +csrrs a0, #0x341, a0 +csrrs a0, #0xfff, a0 +csrrs a0, #0x0, a5 +csrrs a0, #0x1, a5 +csrrs a0, #0x2, a5 +csrrs a0, #0x300, a5 +csrrs a0, #0x301, a5 +csrrs a0, #0x304, a5 +csrrs a0, #0x305, a5 +csrrs a0, #0x340, a5 +csrrs a0, #0x341, a5 +csrrs a0, #0xfff, a5 +csrrs a0, #0x0, s4 +csrrs a0, #0x1, s4 +csrrs a0, #0x2, s4 +csrrs a0, #0x300, s4 +csrrs a0, #0x301, s4 +csrrs a0, #0x304, s4 +csrrs a0, #0x305, s4 +csrrs a0, #0x340, s4 +csrrs a0, #0x341, s4 +csrrs a0, #0xfff, s4 +csrrs a0, #0x0, s9 +csrrs a0, #0x1, s9 +csrrs a0, #0x2, s9 +csrrs a0, #0x300, s9 +csrrs a0, #0x301, s9 +csrrs a0, #0x304, s9 +csrrs a0, #0x305, s9 +csrrs a0, #0x340, s9 +csrrs a0, #0x341, s9 +csrrs a0, #0xfff, s9 +csrrs a0, #0x0, t6 +csrrs a0, #0x1, t6 +csrrs a0, #0x2, t6 +csrrs a0, #0x300, t6 +csrrs a0, #0x301, t6 +csrrs a0, #0x304, t6 +csrrs a0, #0x305, t6 +csrrs a0, #0x340, t6 +csrrs a0, #0x341, t6 +csrrs a0, #0xfff, t6 +csrrs a5, #0x0, zero +csrrs a5, #0x1, zero +csrrs a5, #0x2, zero +csrrs a5, #0x300, zero +csrrs a5, #0x301, zero +csrrs a5, #0x304, zero +csrrs a5, #0x305, zero +csrrs a5, #0x340, zero +csrrs a5, #0x341, zero +csrrs a5, #0xfff, zero +csrrs a5, #0x0, ra +csrrs a5, #0x1, ra +csrrs a5, #0x2, ra +csrrs a5, #0x300, ra +csrrs a5, #0x301, ra +csrrs a5, #0x304, ra +csrrs a5, #0x305, ra +csrrs a5, #0x340, ra +csrrs a5, #0x341, ra +csrrs a5, #0xfff, ra +csrrs a5, #0x0, t0 +csrrs a5, #0x1, t0 +csrrs a5, #0x2, t0 +csrrs a5, #0x300, t0 +csrrs a5, #0x301, t0 +csrrs a5, #0x304, t0 +csrrs a5, #0x305, t0 +csrrs a5, #0x340, t0 +csrrs a5, #0x341, t0 +csrrs a5, #0xfff, t0 +csrrs a5, #0x0, a0 +csrrs a5, #0x1, a0 +csrrs a5, #0x2, a0 +csrrs a5, #0x300, a0 +csrrs a5, #0x301, a0 +csrrs a5, #0x304, a0 +csrrs a5, #0x305, a0 +csrrs a5, #0x340, a0 +csrrs a5, #0x341, a0 +csrrs a5, #0xfff, a0 +csrrs a5, #0x0, a5 +csrrs a5, #0x1, a5 +csrrs a5, #0x2, a5 +csrrs a5, #0x300, a5 +csrrs a5, #0x301, a5 +csrrs a5, #0x304, a5 +csrrs a5, #0x305, a5 +csrrs a5, #0x340, a5 +csrrs a5, #0x341, a5 +csrrs a5, #0xfff, a5 +csrrs a5, #0x0, s4 +csrrs a5, #0x1, s4 +csrrs a5, #0x2, s4 +csrrs a5, #0x300, s4 +csrrs a5, #0x301, s4 +csrrs a5, #0x304, s4 +csrrs a5, #0x305, s4 +csrrs a5, #0x340, s4 +csrrs a5, #0x341, s4 +csrrs a5, #0xfff, s4 +csrrs a5, #0x0, s9 +csrrs a5, #0x1, s9 +csrrs a5, #0x2, s9 +csrrs a5, #0x300, s9 +csrrs a5, #0x301, s9 +csrrs a5, #0x304, s9 +csrrs a5, #0x305, s9 +csrrs a5, #0x340, s9 +csrrs a5, #0x341, s9 +csrrs a5, #0xfff, s9 +csrrs a5, #0x0, t6 +csrrs a5, #0x1, t6 +csrrs a5, #0x2, t6 +csrrs a5, #0x300, t6 +csrrs a5, #0x301, t6 +csrrs a5, #0x304, t6 +csrrs a5, #0x305, t6 +csrrs a5, #0x340, t6 +csrrs a5, #0x341, t6 +csrrs a5, #0xfff, t6 +csrrs s4, #0x0, zero +csrrs s4, #0x1, zero +csrrs s4, #0x2, zero +csrrs s4, #0x300, zero +csrrs s4, #0x301, zero +csrrs s4, #0x304, zero +csrrs s4, #0x305, zero +csrrs s4, #0x340, zero +csrrs s4, #0x341, zero +csrrs s4, #0xfff, zero +csrrs s4, #0x0, ra +csrrs s4, #0x1, ra +csrrs s4, #0x2, ra +csrrs s4, #0x300, ra +csrrs s4, #0x301, ra +csrrs s4, #0x304, ra +csrrs s4, #0x305, ra +csrrs s4, #0x340, ra +csrrs s4, #0x341, ra +csrrs s4, #0xfff, ra +csrrs s4, #0x0, t0 +csrrs s4, #0x1, t0 +csrrs s4, #0x2, t0 +csrrs s4, #0x300, t0 +csrrs s4, #0x301, t0 +csrrs s4, #0x304, t0 +csrrs s4, #0x305, t0 +csrrs s4, #0x340, t0 +csrrs s4, #0x341, t0 +csrrs s4, #0xfff, t0 +csrrs s4, #0x0, a0 +csrrs s4, #0x1, a0 +csrrs s4, #0x2, a0 +csrrs s4, #0x300, a0 +csrrs s4, #0x301, a0 +csrrs s4, #0x304, a0 +csrrs s4, #0x305, a0 +csrrs s4, #0x340, a0 +csrrs s4, #0x341, a0 +csrrs s4, #0xfff, a0 +csrrs s4, #0x0, a5 +csrrs s4, #0x1, a5 +csrrs s4, #0x2, a5 +csrrs s4, #0x300, a5 +csrrs s4, #0x301, a5 +csrrs s4, #0x304, a5 +csrrs s4, #0x305, a5 +csrrs s4, #0x340, a5 +csrrs s4, #0x341, a5 +csrrs s4, #0xfff, a5 +csrrs s4, #0x0, s4 +csrrs s4, #0x1, s4 +csrrs s4, #0x2, s4 +csrrs s4, #0x300, s4 +csrrs s4, #0x301, s4 +csrrs s4, #0x304, s4 +csrrs s4, #0x305, s4 +csrrs s4, #0x340, s4 +csrrs s4, #0x341, s4 +csrrs s4, #0xfff, s4 +csrrs s4, #0x0, s9 +csrrs s4, #0x1, s9 +csrrs s4, #0x2, s9 +csrrs s4, #0x300, s9 +csrrs s4, #0x301, s9 +csrrs s4, #0x304, s9 +csrrs s4, #0x305, s9 +csrrs s4, #0x340, s9 +csrrs s4, #0x341, s9 +csrrs s4, #0xfff, s9 +csrrs s4, #0x0, t6 +csrrs s4, #0x1, t6 +csrrs s4, #0x2, t6 +csrrs s4, #0x300, t6 +csrrs s4, #0x301, t6 +csrrs s4, #0x304, t6 +csrrs s4, #0x305, t6 +csrrs s4, #0x340, t6 +csrrs s4, #0x341, t6 +csrrs s4, #0xfff, t6 +csrrs s9, #0x0, zero +csrrs s9, #0x1, zero +csrrs s9, #0x2, zero +csrrs s9, #0x300, zero +csrrs s9, #0x301, zero +csrrs s9, #0x304, zero +csrrs s9, #0x305, zero +csrrs s9, #0x340, zero +csrrs s9, #0x341, zero +csrrs s9, #0xfff, zero +csrrs s9, #0x0, ra +csrrs s9, #0x1, ra +csrrs s9, #0x2, ra +csrrs s9, #0x300, ra +csrrs s9, #0x301, ra +csrrs s9, #0x304, ra +csrrs s9, #0x305, ra +csrrs s9, #0x340, ra +csrrs s9, #0x341, ra +csrrs s9, #0xfff, ra +csrrs s9, #0x0, t0 +csrrs s9, #0x1, t0 +csrrs s9, #0x2, t0 +csrrs s9, #0x300, t0 +csrrs s9, #0x301, t0 +csrrs s9, #0x304, t0 +csrrs s9, #0x305, t0 +csrrs s9, #0x340, t0 +csrrs s9, #0x341, t0 +csrrs s9, #0xfff, t0 +csrrs s9, #0x0, a0 +csrrs s9, #0x1, a0 +csrrs s9, #0x2, a0 +csrrs s9, #0x300, a0 +csrrs s9, #0x301, a0 +csrrs s9, #0x304, a0 +csrrs s9, #0x305, a0 +csrrs s9, #0x340, a0 +csrrs s9, #0x341, a0 +csrrs s9, #0xfff, a0 +csrrs s9, #0x0, a5 +csrrs s9, #0x1, a5 +csrrs s9, #0x2, a5 +csrrs s9, #0x300, a5 +csrrs s9, #0x301, a5 +csrrs s9, #0x304, a5 +csrrs s9, #0x305, a5 +csrrs s9, #0x340, a5 +csrrs s9, #0x341, a5 +csrrs s9, #0xfff, a5 +csrrs s9, #0x0, s4 +csrrs s9, #0x1, s4 +csrrs s9, #0x2, s4 +csrrs s9, #0x300, s4 +csrrs s9, #0x301, s4 +csrrs s9, #0x304, s4 +csrrs s9, #0x305, s4 +csrrs s9, #0x340, s4 +csrrs s9, #0x341, s4 +csrrs s9, #0xfff, s4 +csrrs s9, #0x0, s9 +csrrs s9, #0x1, s9 +csrrs s9, #0x2, s9 +csrrs s9, #0x300, s9 +csrrs s9, #0x301, s9 +csrrs s9, #0x304, s9 +csrrs s9, #0x305, s9 +csrrs s9, #0x340, s9 +csrrs s9, #0x341, s9 +csrrs s9, #0xfff, s9 +csrrs s9, #0x0, t6 +csrrs s9, #0x1, t6 +csrrs s9, #0x2, t6 +csrrs s9, #0x300, t6 +csrrs s9, #0x301, t6 +csrrs s9, #0x304, t6 +csrrs s9, #0x305, t6 +csrrs s9, #0x340, t6 +csrrs s9, #0x341, t6 +csrrs s9, #0xfff, t6 +csrrs t6, #0x0, zero +csrrs t6, #0x1, zero +csrrs t6, #0x2, zero +csrrs t6, #0x300, zero +csrrs t6, #0x301, zero +csrrs t6, #0x304, zero +csrrs t6, #0x305, zero +csrrs t6, #0x340, zero +csrrs t6, #0x341, zero +csrrs t6, #0xfff, zero +csrrs t6, #0x0, ra +csrrs t6, #0x1, ra +csrrs t6, #0x2, ra +csrrs t6, #0x300, ra +csrrs t6, #0x301, ra +csrrs t6, #0x304, ra +csrrs t6, #0x305, ra +csrrs t6, #0x340, ra +csrrs t6, #0x341, ra +csrrs t6, #0xfff, ra +csrrs t6, #0x0, t0 +csrrs t6, #0x1, t0 +csrrs t6, #0x2, t0 +csrrs t6, #0x300, t0 +csrrs t6, #0x301, t0 +csrrs t6, #0x304, t0 +csrrs t6, #0x305, t0 +csrrs t6, #0x340, t0 +csrrs t6, #0x341, t0 +csrrs t6, #0xfff, t0 +csrrs t6, #0x0, a0 +csrrs t6, #0x1, a0 +csrrs t6, #0x2, a0 +csrrs t6, #0x300, a0 +csrrs t6, #0x301, a0 +csrrs t6, #0x304, a0 +csrrs t6, #0x305, a0 +csrrs t6, #0x340, a0 +csrrs t6, #0x341, a0 +csrrs t6, #0xfff, a0 +csrrs t6, #0x0, a5 +csrrs t6, #0x1, a5 +csrrs t6, #0x2, a5 +csrrs t6, #0x300, a5 +csrrs t6, #0x301, a5 +csrrs t6, #0x304, a5 +csrrs t6, #0x305, a5 +csrrs t6, #0x340, a5 +csrrs t6, #0x341, a5 +csrrs t6, #0xfff, a5 +csrrs t6, #0x0, s4 +csrrs t6, #0x1, s4 +csrrs t6, #0x2, s4 +csrrs t6, #0x300, s4 +csrrs t6, #0x301, s4 +csrrs t6, #0x304, s4 +csrrs t6, #0x305, s4 +csrrs t6, #0x340, s4 +csrrs t6, #0x341, s4 +csrrs t6, #0xfff, s4 +csrrs t6, #0x0, s9 +csrrs t6, #0x1, s9 +csrrs t6, #0x2, s9 +csrrs t6, #0x300, s9 +csrrs t6, #0x301, s9 +csrrs t6, #0x304, s9 +csrrs t6, #0x305, s9 +csrrs t6, #0x340, s9 +csrrs t6, #0x341, s9 +csrrs t6, #0xfff, s9 +csrrs t6, #0x0, t6 +csrrs t6, #0x1, t6 +csrrs t6, #0x2, t6 +csrrs t6, #0x300, t6 +csrrs t6, #0x301, t6 +csrrs t6, #0x304, t6 +csrrs t6, #0x305, t6 +csrrs t6, #0x340, t6 +csrrs t6, #0x341, t6 +csrrs t6, #0xfff, t6 + diff --git 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#10 +csrrsi a0, #0x305, #10 +csrrsi a0, #0x340, #10 +csrrsi a0, #0x341, #10 +csrrsi a0, #0xFFF, #10 +csrrsi a0, #0x000, #15 +csrrsi a0, #0x001, #15 +csrrsi a0, #0x002, #15 +csrrsi a0, #0x300, #15 +csrrsi a0, #0x301, #15 +csrrsi a0, #0x304, #15 +csrrsi a0, #0x305, #15 +csrrsi a0, #0x340, #15 +csrrsi a0, #0x341, #15 +csrrsi a0, #0xFFF, #15 +csrrsi a0, #0x000, #20 +csrrsi a0, #0x001, #20 +csrrsi a0, #0x002, #20 +csrrsi a0, #0x300, #20 +csrrsi a0, #0x301, #20 +csrrsi a0, #0x304, #20 +csrrsi a0, #0x305, #20 +csrrsi a0, #0x340, #20 +csrrsi a0, #0x341, #20 +csrrsi a0, #0xFFF, #20 +csrrsi a0, #0x000, #25 +csrrsi a0, #0x001, #25 +csrrsi a0, #0x002, #25 +csrrsi a0, #0x300, #25 +csrrsi a0, #0x301, #25 +csrrsi a0, #0x304, #25 +csrrsi a0, #0x305, #25 +csrrsi a0, #0x340, #25 +csrrsi a0, #0x341, #25 +csrrsi a0, #0xFFF, #25 +csrrsi a0, #0x000, #31 +csrrsi a0, #0x001, #31 +csrrsi a0, #0x002, #31 +csrrsi a0, #0x300, #31 +csrrsi a0, #0x301, #31 +csrrsi a0, #0x304, #31 +csrrsi a0, #0x305, #31 +csrrsi a0, #0x340, #31 +csrrsi a0, #0x341, #31 +csrrsi a0, #0xFFF, #31 +csrrsi a5, #0x000, #0 +csrrsi a5, #0x001, #0 +csrrsi a5, #0x002, #0 +csrrsi a5, #0x300, #0 +csrrsi a5, #0x301, #0 +csrrsi a5, #0x304, #0 +csrrsi a5, #0x305, #0 +csrrsi a5, #0x340, #0 +csrrsi a5, #0x341, #0 +csrrsi a5, #0xFFF, #0 +csrrsi a5, #0x000, #1 +csrrsi a5, #0x001, #1 +csrrsi a5, #0x002, #1 +csrrsi a5, #0x300, #1 +csrrsi a5, #0x301, #1 +csrrsi a5, #0x304, #1 +csrrsi a5, #0x305, #1 +csrrsi a5, #0x340, #1 +csrrsi a5, #0x341, #1 +csrrsi a5, #0xFFF, #1 +csrrsi a5, #0x000, #5 +csrrsi a5, #0x001, #5 +csrrsi a5, #0x002, #5 +csrrsi a5, #0x300, #5 +csrrsi a5, #0x301, #5 +csrrsi a5, #0x304, #5 +csrrsi a5, #0x305, #5 +csrrsi a5, #0x340, #5 +csrrsi a5, #0x341, #5 +csrrsi a5, #0xFFF, #5 +csrrsi a5, #0x000, #10 +csrrsi a5, #0x001, #10 +csrrsi a5, #0x002, #10 +csrrsi a5, #0x300, #10 +csrrsi a5, #0x301, #10 +csrrsi a5, #0x304, #10 +csrrsi a5, #0x305, #10 +csrrsi a5, #0x340, #10 +csrrsi a5, #0x341, #10 +csrrsi a5, #0xFFF, #10 +csrrsi a5, #0x000, #15 +csrrsi a5, #0x001, #15 +csrrsi a5, #0x002, #15 +csrrsi a5, #0x300, #15 +csrrsi a5, #0x301, #15 +csrrsi a5, #0x304, #15 +csrrsi a5, #0x305, #15 +csrrsi a5, #0x340, #15 +csrrsi a5, #0x341, #15 +csrrsi a5, #0xFFF, #15 +csrrsi a5, #0x000, #20 +csrrsi a5, #0x001, #20 +csrrsi a5, #0x002, #20 +csrrsi a5, #0x300, #20 +csrrsi a5, #0x301, #20 +csrrsi a5, #0x304, #20 +csrrsi a5, #0x305, #20 +csrrsi a5, #0x340, #20 +csrrsi a5, #0x341, #20 +csrrsi a5, #0xFFF, #20 +csrrsi a5, #0x000, #25 +csrrsi a5, #0x001, #25 +csrrsi a5, #0x002, #25 +csrrsi a5, #0x300, #25 +csrrsi a5, #0x301, #25 +csrrsi a5, #0x304, #25 +csrrsi a5, #0x305, #25 +csrrsi a5, #0x340, #25 +csrrsi a5, #0x341, #25 +csrrsi a5, #0xFFF, #25 +csrrsi a5, #0x000, #31 +csrrsi a5, #0x001, #31 +csrrsi a5, #0x002, #31 +csrrsi a5, #0x300, #31 +csrrsi a5, #0x301, #31 +csrrsi a5, #0x304, #31 +csrrsi a5, #0x305, #31 +csrrsi a5, #0x340, #31 +csrrsi a5, #0x341, #31 +csrrsi a5, #0xFFF, #31 +csrrsi s4, #0x000, #0 +csrrsi s4, #0x001, #0 +csrrsi s4, #0x002, #0 +csrrsi s4, #0x300, #0 +csrrsi s4, #0x301, #0 +csrrsi s4, #0x304, #0 +csrrsi s4, #0x305, #0 +csrrsi s4, #0x340, #0 +csrrsi s4, #0x341, #0 +csrrsi s4, #0xFFF, #0 +csrrsi s4, #0x000, #1 +csrrsi s4, #0x001, #1 +csrrsi s4, #0x002, #1 +csrrsi s4, #0x300, #1 +csrrsi s4, #0x301, #1 +csrrsi s4, #0x304, #1 +csrrsi s4, #0x305, #1 +csrrsi s4, #0x340, #1 +csrrsi s4, #0x341, #1 +csrrsi s4, #0xFFF, #1 +csrrsi s4, #0x000, #5 +csrrsi s4, #0x001, #5 +csrrsi s4, #0x002, #5 +csrrsi s4, #0x300, #5 +csrrsi s4, #0x301, #5 +csrrsi s4, #0x304, #5 +csrrsi s4, #0x305, #5 +csrrsi s4, #0x340, #5 +csrrsi s4, #0x341, #5 +csrrsi s4, #0xFFF, #5 +csrrsi s4, #0x000, #10 +csrrsi s4, #0x001, #10 +csrrsi s4, #0x002, #10 +csrrsi s4, #0x300, #10 +csrrsi s4, #0x301, #10 +csrrsi s4, #0x304, #10 +csrrsi s4, #0x305, #10 +csrrsi s4, #0x340, #10 +csrrsi s4, #0x341, #10 +csrrsi s4, #0xFFF, #10 +csrrsi s4, #0x000, #15 +csrrsi s4, #0x001, #15 +csrrsi s4, #0x002, #15 +csrrsi s4, #0x300, #15 +csrrsi s4, #0x301, #15 +csrrsi s4, #0x304, #15 +csrrsi s4, #0x305, #15 +csrrsi s4, #0x340, #15 +csrrsi s4, #0x341, #15 +csrrsi s4, #0xFFF, #15 +csrrsi s4, #0x000, #20 +csrrsi s4, #0x001, #20 +csrrsi s4, #0x002, #20 +csrrsi s4, #0x300, #20 +csrrsi s4, #0x301, #20 +csrrsi s4, #0x304, #20 +csrrsi s4, #0x305, #20 +csrrsi s4, #0x340, #20 +csrrsi s4, #0x341, #20 +csrrsi s4, #0xFFF, #20 +csrrsi s4, #0x000, #25 +csrrsi s4, #0x001, #25 +csrrsi s4, #0x002, #25 +csrrsi s4, #0x300, #25 +csrrsi s4, #0x301, #25 +csrrsi s4, #0x304, #25 +csrrsi s4, #0x305, #25 +csrrsi s4, #0x340, #25 +csrrsi s4, #0x341, #25 +csrrsi s4, #0xFFF, #25 +csrrsi s4, #0x000, #31 +csrrsi s4, #0x001, #31 +csrrsi s4, #0x002, #31 +csrrsi s4, #0x300, #31 +csrrsi s4, #0x301, #31 +csrrsi s4, #0x304, #31 +csrrsi s4, #0x305, #31 +csrrsi s4, #0x340, #31 +csrrsi s4, #0x341, #31 +csrrsi s4, #0xFFF, #31 +csrrsi s9, #0x000, #0 +csrrsi s9, #0x001, #0 +csrrsi s9, #0x002, #0 +csrrsi s9, #0x300, #0 +csrrsi s9, #0x301, #0 +csrrsi s9, #0x304, #0 +csrrsi s9, #0x305, #0 +csrrsi s9, #0x340, #0 +csrrsi s9, #0x341, #0 +csrrsi s9, #0xFFF, #0 +csrrsi s9, #0x000, #1 +csrrsi s9, #0x001, #1 +csrrsi s9, #0x002, #1 +csrrsi s9, #0x300, #1 +csrrsi s9, #0x301, #1 +csrrsi s9, #0x304, #1 +csrrsi s9, #0x305, #1 +csrrsi s9, #0x340, #1 +csrrsi s9, #0x341, #1 +csrrsi s9, #0xFFF, #1 +csrrsi s9, #0x000, #5 +csrrsi s9, #0x001, #5 +csrrsi s9, #0x002, #5 +csrrsi s9, #0x300, #5 +csrrsi s9, #0x301, #5 +csrrsi s9, #0x304, #5 +csrrsi s9, #0x305, #5 +csrrsi s9, #0x340, #5 +csrrsi s9, #0x341, #5 +csrrsi s9, #0xFFF, #5 +csrrsi s9, #0x000, #10 +csrrsi s9, #0x001, #10 +csrrsi s9, #0x002, #10 +csrrsi s9, #0x300, #10 +csrrsi s9, #0x301, #10 +csrrsi s9, #0x304, #10 +csrrsi s9, #0x305, #10 +csrrsi s9, #0x340, #10 +csrrsi s9, #0x341, #10 +csrrsi s9, #0xFFF, #10 +csrrsi s9, #0x000, #15 +csrrsi s9, #0x001, #15 +csrrsi s9, #0x002, #15 +csrrsi s9, #0x300, #15 +csrrsi s9, #0x301, #15 +csrrsi s9, #0x304, #15 +csrrsi s9, #0x305, #15 +csrrsi s9, #0x340, #15 +csrrsi s9, #0x341, #15 +csrrsi s9, #0xFFF, #15 +csrrsi s9, #0x000, #20 +csrrsi s9, #0x001, #20 +csrrsi s9, #0x002, #20 +csrrsi s9, #0x300, #20 +csrrsi s9, #0x301, #20 +csrrsi s9, #0x304, #20 +csrrsi s9, #0x305, #20 +csrrsi s9, #0x340, #20 +csrrsi s9, #0x341, #20 +csrrsi s9, #0xFFF, #20 +csrrsi s9, #0x000, #25 +csrrsi s9, #0x001, #25 +csrrsi s9, #0x002, #25 +csrrsi s9, #0x300, #25 +csrrsi s9, #0x301, #25 +csrrsi s9, #0x304, #25 +csrrsi s9, #0x305, #25 +csrrsi s9, #0x340, #25 +csrrsi s9, #0x341, #25 +csrrsi s9, #0xFFF, #25 +csrrsi s9, #0x000, #31 +csrrsi s9, #0x001, #31 +csrrsi s9, #0x002, #31 +csrrsi s9, #0x300, #31 +csrrsi s9, #0x301, #31 +csrrsi s9, #0x304, #31 +csrrsi s9, #0x305, #31 +csrrsi s9, #0x340, #31 +csrrsi s9, #0x341, #31 +csrrsi s9, #0xFFF, #31 +csrrsi t6, #0x000, #0 +csrrsi t6, #0x001, #0 +csrrsi t6, #0x002, #0 +csrrsi t6, #0x300, #0 +csrrsi t6, #0x301, #0 +csrrsi t6, #0x304, #0 +csrrsi t6, #0x305, #0 +csrrsi t6, #0x340, #0 +csrrsi t6, #0x341, #0 +csrrsi t6, #0xFFF, #0 +csrrsi t6, #0x000, #1 +csrrsi t6, #0x001, #1 +csrrsi t6, #0x002, #1 +csrrsi t6, #0x300, #1 +csrrsi t6, #0x301, #1 +csrrsi t6, #0x304, #1 +csrrsi t6, #0x305, #1 +csrrsi t6, #0x340, #1 +csrrsi t6, #0x341, #1 +csrrsi t6, #0xFFF, #1 +csrrsi t6, #0x000, #5 +csrrsi t6, #0x001, #5 +csrrsi t6, #0x002, #5 +csrrsi t6, #0x300, #5 +csrrsi t6, #0x301, #5 +csrrsi t6, #0x304, #5 +csrrsi t6, #0x305, #5 +csrrsi t6, #0x340, #5 +csrrsi t6, #0x341, #5 +csrrsi t6, #0xFFF, #5 +csrrsi t6, #0x000, #10 +csrrsi t6, #0x001, #10 +csrrsi t6, #0x002, #10 +csrrsi t6, #0x300, #10 +csrrsi t6, #0x301, #10 +csrrsi t6, #0x304, #10 +csrrsi t6, #0x305, #10 +csrrsi t6, #0x340, #10 +csrrsi t6, #0x341, #10 +csrrsi t6, #0xFFF, #10 +csrrsi t6, #0x000, #15 +csrrsi t6, #0x001, #15 +csrrsi t6, #0x002, #15 +csrrsi t6, #0x300, #15 +csrrsi t6, #0x301, #15 +csrrsi t6, #0x304, #15 +csrrsi t6, #0x305, #15 +csrrsi t6, #0x340, #15 +csrrsi t6, #0x341, #15 +csrrsi t6, #0xFFF, #15 +csrrsi t6, #0x000, #20 +csrrsi t6, #0x001, #20 +csrrsi t6, #0x002, #20 +csrrsi t6, #0x300, #20 +csrrsi t6, #0x301, #20 +csrrsi t6, #0x304, #20 +csrrsi t6, #0x305, #20 +csrrsi t6, #0x340, #20 +csrrsi t6, #0x341, #20 +csrrsi t6, #0xFFF, #20 +csrrsi t6, #0x000, #25 +csrrsi t6, #0x001, #25 +csrrsi t6, #0x002, #25 +csrrsi t6, #0x300, #25 +csrrsi t6, #0x301, #25 +csrrsi t6, #0x304, #25 +csrrsi t6, #0x305, #25 +csrrsi t6, #0x340, #25 +csrrsi t6, #0x341, #25 +csrrsi t6, #0xFFF, #25 +csrrsi t6, #0x000, #31 +csrrsi t6, #0x001, #31 +csrrsi t6, #0x002, #31 +csrrsi t6, #0x300, #31 +csrrsi t6, #0x301, #31 +csrrsi t6, #0x304, #31 +csrrsi t6, #0x305, #31 +csrrsi t6, #0x340, #31 +csrrsi t6, #0x341, #31 +csrrsi t6, #0xFFF, #31 diff --git a/tests/riscv/zicsr-extension/csrrw.asm b/tests/riscv/zicsr-extension/csrrw.asm new file mode 100644 index 0000000..4c397f6 --- /dev/null +++ b/tests/riscv/zicsr-extension/csrrw.asm @@ -0,0 +1,644 @@ +.lang riscv32 +.org 0x0 + +csrrw zero, #0x0, zero +csrrw zero, #0x1, zero +csrrw zero, #0x2, zero +csrrw zero, #0x300, zero +csrrw zero, #0x301, zero +csrrw zero, #0x304, zero +csrrw zero, #0x305, zero +csrrw zero, #0x340, zero +csrrw zero, #0x341, zero +csrrw zero, #0xfff, zero +csrrw zero, #0x0, ra +csrrw zero, #0x1, ra +csrrw zero, #0x2, ra +csrrw zero, #0x300, ra +csrrw zero, #0x301, ra +csrrw zero, #0x304, ra +csrrw zero, #0x305, ra +csrrw zero, #0x340, ra +csrrw zero, #0x341, ra +csrrw zero, #0xfff, ra +csrrw zero, #0x0, t0 +csrrw zero, #0x1, t0 +csrrw zero, #0x2, t0 +csrrw zero, #0x300, t0 +csrrw zero, #0x301, t0 +csrrw zero, #0x304, t0 +csrrw zero, #0x305, t0 +csrrw zero, #0x340, t0 +csrrw zero, #0x341, t0 +csrrw zero, #0xfff, t0 +csrrw zero, #0x0, a0 +csrrw zero, #0x1, a0 +csrrw zero, #0x2, a0 +csrrw zero, #0x300, a0 +csrrw zero, #0x301, a0 +csrrw zero, #0x304, a0 +csrrw zero, #0x305, a0 +csrrw zero, #0x340, a0 +csrrw zero, #0x341, a0 +csrrw zero, #0xfff, a0 +csrrw zero, #0x0, a5 +csrrw zero, #0x1, a5 +csrrw zero, #0x2, a5 +csrrw zero, #0x300, a5 +csrrw zero, #0x301, a5 +csrrw zero, #0x304, a5 +csrrw zero, #0x305, a5 +csrrw zero, #0x340, a5 +csrrw zero, #0x341, a5 +csrrw zero, #0xfff, a5 +csrrw zero, #0x0, s4 +csrrw zero, #0x1, s4 +csrrw zero, #0x2, s4 +csrrw zero, #0x300, s4 +csrrw zero, #0x301, s4 +csrrw zero, #0x304, s4 +csrrw zero, #0x305, s4 +csrrw zero, #0x340, s4 +csrrw zero, #0x341, s4 +csrrw zero, #0xfff, s4 +csrrw zero, #0x0, s9 +csrrw zero, #0x1, s9 +csrrw zero, #0x2, s9 +csrrw zero, #0x300, s9 +csrrw zero, #0x301, s9 +csrrw zero, #0x304, s9 +csrrw zero, #0x305, s9 +csrrw zero, #0x340, s9 +csrrw zero, #0x341, s9 +csrrw zero, #0xfff, s9 +csrrw zero, #0x0, t6 +csrrw zero, #0x1, t6 +csrrw zero, #0x2, t6 +csrrw zero, #0x300, t6 +csrrw zero, #0x301, t6 +csrrw zero, #0x304, t6 +csrrw zero, #0x305, t6 +csrrw zero, #0x340, t6 +csrrw zero, #0x341, t6 +csrrw zero, #0xfff, t6 +csrrw ra, #0x0, zero +csrrw ra, #0x1, zero +csrrw ra, #0x2, zero +csrrw ra, #0x300, zero +csrrw ra, #0x301, zero +csrrw ra, #0x304, zero +csrrw ra, #0x305, zero +csrrw ra, #0x340, zero +csrrw ra, #0x341, zero +csrrw ra, #0xfff, zero +csrrw ra, #0x0, ra +csrrw ra, #0x1, ra +csrrw ra, #0x2, ra +csrrw ra, #0x300, ra +csrrw ra, #0x301, ra +csrrw ra, #0x304, ra +csrrw ra, #0x305, ra +csrrw ra, #0x340, ra +csrrw ra, #0x341, ra +csrrw ra, #0xfff, ra +csrrw ra, #0x0, t0 +csrrw ra, #0x1, t0 +csrrw ra, #0x2, t0 +csrrw ra, #0x300, t0 +csrrw ra, #0x301, t0 +csrrw ra, #0x304, t0 +csrrw ra, #0x305, t0 +csrrw ra, #0x340, t0 +csrrw ra, #0x341, t0 +csrrw ra, #0xfff, t0 +csrrw ra, #0x0, a0 +csrrw ra, #0x1, a0 +csrrw ra, #0x2, a0 +csrrw ra, #0x300, a0 +csrrw ra, #0x301, a0 +csrrw ra, #0x304, a0 +csrrw ra, #0x305, a0 +csrrw ra, #0x340, a0 +csrrw ra, #0x341, a0 +csrrw ra, #0xfff, a0 +csrrw ra, #0x0, a5 +csrrw ra, #0x1, a5 +csrrw ra, #0x2, a5 +csrrw ra, #0x300, a5 +csrrw ra, #0x301, a5 +csrrw ra, #0x304, a5 +csrrw ra, #0x305, a5 +csrrw ra, #0x340, a5 +csrrw ra, #0x341, a5 +csrrw ra, #0xfff, a5 +csrrw ra, #0x0, s4 +csrrw ra, #0x1, s4 +csrrw ra, #0x2, s4 +csrrw ra, #0x300, s4 +csrrw ra, #0x301, s4 +csrrw ra, #0x304, s4 +csrrw ra, #0x305, s4 +csrrw ra, #0x340, s4 +csrrw ra, #0x341, s4 +csrrw ra, #0xfff, s4 +csrrw ra, #0x0, s9 +csrrw ra, #0x1, s9 +csrrw ra, #0x2, s9 +csrrw ra, #0x300, s9 +csrrw ra, #0x301, s9 +csrrw ra, #0x304, s9 +csrrw ra, #0x305, s9 +csrrw ra, #0x340, s9 +csrrw ra, #0x341, s9 +csrrw ra, #0xfff, s9 +csrrw ra, #0x0, t6 +csrrw ra, #0x1, t6 +csrrw ra, #0x2, t6 +csrrw ra, #0x300, t6 +csrrw ra, #0x301, t6 +csrrw ra, #0x304, t6 +csrrw ra, #0x305, t6 +csrrw ra, #0x340, t6 +csrrw ra, #0x341, t6 +csrrw ra, #0xfff, t6 +csrrw t0, #0x0, zero +csrrw t0, #0x1, zero +csrrw t0, #0x2, zero +csrrw t0, #0x300, zero +csrrw t0, #0x301, zero +csrrw t0, #0x304, zero +csrrw t0, #0x305, zero +csrrw t0, #0x340, zero +csrrw t0, #0x341, zero +csrrw t0, #0xfff, zero +csrrw t0, #0x0, ra +csrrw t0, #0x1, ra +csrrw t0, #0x2, ra +csrrw t0, #0x300, ra +csrrw t0, #0x301, ra +csrrw t0, #0x304, ra +csrrw t0, #0x305, ra +csrrw t0, #0x340, ra +csrrw t0, #0x341, ra +csrrw t0, #0xfff, ra +csrrw t0, #0x0, t0 +csrrw t0, #0x1, t0 +csrrw t0, #0x2, t0 +csrrw t0, #0x300, t0 +csrrw t0, #0x301, t0 +csrrw t0, #0x304, t0 +csrrw t0, #0x305, t0 +csrrw t0, #0x340, t0 +csrrw t0, #0x341, t0 +csrrw t0, #0xfff, t0 +csrrw t0, #0x0, a0 +csrrw t0, #0x1, a0 +csrrw t0, #0x2, a0 +csrrw t0, #0x300, a0 +csrrw t0, #0x301, a0 +csrrw t0, #0x304, a0 +csrrw t0, #0x305, a0 +csrrw t0, #0x340, a0 +csrrw t0, #0x341, a0 +csrrw t0, #0xfff, a0 +csrrw t0, #0x0, a5 +csrrw t0, #0x1, a5 +csrrw t0, #0x2, a5 +csrrw t0, #0x300, a5 +csrrw t0, #0x301, a5 +csrrw t0, #0x304, a5 +csrrw t0, #0x305, a5 +csrrw t0, #0x340, a5 +csrrw t0, #0x341, a5 +csrrw t0, #0xfff, a5 +csrrw t0, #0x0, s4 +csrrw t0, #0x1, s4 +csrrw t0, #0x2, s4 +csrrw t0, #0x300, s4 +csrrw t0, #0x301, s4 +csrrw t0, #0x304, s4 +csrrw t0, #0x305, s4 +csrrw t0, #0x340, s4 +csrrw t0, #0x341, s4 +csrrw t0, #0xfff, s4 +csrrw t0, #0x0, s9 +csrrw t0, #0x1, s9 +csrrw t0, #0x2, s9 +csrrw t0, #0x300, s9 +csrrw t0, #0x301, s9 +csrrw t0, #0x304, s9 +csrrw t0, #0x305, s9 +csrrw t0, #0x340, s9 +csrrw t0, #0x341, s9 +csrrw t0, #0xfff, s9 +csrrw t0, #0x0, t6 +csrrw t0, #0x1, t6 +csrrw t0, #0x2, t6 +csrrw t0, #0x300, t6 +csrrw t0, #0x301, t6 +csrrw t0, #0x304, t6 +csrrw t0, #0x305, t6 +csrrw t0, #0x340, t6 +csrrw t0, #0x341, t6 +csrrw t0, #0xfff, t6 +csrrw a0, #0x0, zero +csrrw a0, #0x1, zero +csrrw a0, #0x2, zero +csrrw a0, #0x300, zero +csrrw a0, #0x301, zero +csrrw a0, #0x304, zero +csrrw a0, #0x305, zero +csrrw a0, #0x340, zero +csrrw a0, #0x341, zero +csrrw a0, #0xfff, zero +csrrw a0, #0x0, ra +csrrw a0, #0x1, ra +csrrw a0, #0x2, ra +csrrw a0, #0x300, ra +csrrw a0, #0x301, ra +csrrw a0, #0x304, ra +csrrw a0, #0x305, ra +csrrw a0, #0x340, ra +csrrw a0, #0x341, ra +csrrw a0, #0xfff, ra +csrrw a0, #0x0, t0 +csrrw a0, #0x1, t0 +csrrw a0, #0x2, t0 +csrrw a0, #0x300, t0 +csrrw a0, #0x301, t0 +csrrw a0, #0x304, t0 +csrrw a0, #0x305, t0 +csrrw a0, #0x340, t0 +csrrw a0, #0x341, t0 +csrrw a0, #0xfff, t0 +csrrw a0, #0x0, a0 +csrrw a0, #0x1, a0 +csrrw a0, #0x2, a0 +csrrw a0, #0x300, a0 +csrrw a0, #0x301, a0 +csrrw a0, #0x304, a0 +csrrw a0, #0x305, a0 +csrrw a0, #0x340, a0 +csrrw a0, #0x341, a0 +csrrw a0, #0xfff, a0 +csrrw a0, #0x0, a5 +csrrw a0, #0x1, a5 +csrrw a0, #0x2, a5 +csrrw a0, #0x300, a5 +csrrw a0, #0x301, a5 +csrrw a0, #0x304, a5 +csrrw a0, #0x305, a5 +csrrw a0, #0x340, a5 +csrrw a0, #0x341, a5 +csrrw a0, #0xfff, a5 +csrrw a0, #0x0, s4 +csrrw a0, #0x1, s4 +csrrw a0, #0x2, s4 +csrrw a0, #0x300, s4 +csrrw a0, #0x301, s4 +csrrw a0, #0x304, s4 +csrrw a0, #0x305, s4 +csrrw a0, #0x340, s4 +csrrw a0, #0x341, s4 +csrrw a0, #0xfff, s4 +csrrw a0, #0x0, s9 +csrrw a0, #0x1, s9 +csrrw a0, #0x2, s9 +csrrw a0, #0x300, s9 +csrrw a0, #0x301, s9 +csrrw a0, #0x304, s9 +csrrw a0, #0x305, s9 +csrrw a0, #0x340, s9 +csrrw a0, #0x341, s9 +csrrw a0, #0xfff, s9 +csrrw a0, #0x0, t6 +csrrw a0, #0x1, t6 +csrrw a0, #0x2, t6 +csrrw a0, #0x300, t6 +csrrw a0, #0x301, t6 +csrrw a0, #0x304, t6 +csrrw a0, #0x305, t6 +csrrw a0, #0x340, t6 +csrrw a0, #0x341, t6 +csrrw a0, #0xfff, t6 +csrrw a5, #0x0, zero +csrrw a5, #0x1, zero +csrrw a5, #0x2, zero +csrrw a5, #0x300, zero +csrrw a5, #0x301, zero +csrrw a5, #0x304, zero +csrrw a5, #0x305, zero +csrrw a5, #0x340, zero +csrrw a5, #0x341, zero +csrrw a5, #0xfff, zero +csrrw a5, #0x0, ra +csrrw a5, #0x1, ra +csrrw a5, #0x2, ra +csrrw a5, #0x300, ra +csrrw a5, #0x301, ra +csrrw a5, #0x304, ra +csrrw a5, #0x305, ra +csrrw a5, #0x340, ra +csrrw a5, #0x341, ra +csrrw a5, #0xfff, ra +csrrw a5, #0x0, t0 +csrrw a5, #0x1, t0 +csrrw a5, #0x2, t0 +csrrw a5, #0x300, t0 +csrrw a5, #0x301, t0 +csrrw a5, #0x304, t0 +csrrw a5, #0x305, t0 +csrrw a5, #0x340, t0 +csrrw a5, #0x341, t0 +csrrw a5, #0xfff, t0 +csrrw a5, #0x0, a0 +csrrw a5, #0x1, a0 +csrrw a5, #0x2, a0 +csrrw a5, #0x300, a0 +csrrw a5, #0x301, a0 +csrrw a5, #0x304, a0 +csrrw a5, #0x305, a0 +csrrw a5, #0x340, a0 +csrrw a5, #0x341, a0 +csrrw a5, #0xfff, a0 +csrrw a5, #0x0, a5 +csrrw a5, #0x1, a5 +csrrw a5, #0x2, a5 +csrrw a5, #0x300, a5 +csrrw a5, #0x301, a5 +csrrw a5, #0x304, a5 +csrrw a5, #0x305, a5 +csrrw a5, #0x340, a5 +csrrw a5, #0x341, a5 +csrrw a5, #0xfff, a5 +csrrw a5, #0x0, s4 +csrrw a5, #0x1, s4 +csrrw a5, #0x2, s4 +csrrw a5, #0x300, s4 +csrrw a5, #0x301, s4 +csrrw a5, #0x304, s4 +csrrw a5, #0x305, s4 +csrrw a5, #0x340, s4 +csrrw a5, #0x341, s4 +csrrw a5, #0xfff, s4 +csrrw a5, #0x0, s9 +csrrw a5, #0x1, s9 +csrrw a5, #0x2, s9 +csrrw a5, #0x300, s9 +csrrw a5, #0x301, s9 +csrrw a5, #0x304, s9 +csrrw a5, #0x305, s9 +csrrw a5, #0x340, s9 +csrrw a5, #0x341, s9 +csrrw a5, #0xfff, s9 +csrrw a5, #0x0, t6 +csrrw a5, #0x1, t6 +csrrw a5, #0x2, t6 +csrrw a5, #0x300, t6 +csrrw a5, #0x301, t6 +csrrw a5, #0x304, t6 +csrrw a5, #0x305, t6 +csrrw a5, #0x340, t6 +csrrw a5, #0x341, t6 +csrrw a5, #0xfff, t6 +csrrw s4, #0x0, zero +csrrw s4, #0x1, zero +csrrw s4, #0x2, zero +csrrw s4, #0x300, zero +csrrw s4, #0x301, zero +csrrw s4, #0x304, zero +csrrw s4, #0x305, zero +csrrw s4, #0x340, zero +csrrw s4, #0x341, zero +csrrw s4, #0xfff, zero +csrrw s4, #0x0, ra +csrrw s4, #0x1, ra +csrrw s4, #0x2, ra +csrrw s4, #0x300, ra +csrrw s4, #0x301, ra +csrrw s4, #0x304, ra +csrrw s4, #0x305, ra +csrrw s4, #0x340, ra +csrrw s4, #0x341, ra +csrrw s4, #0xfff, ra +csrrw s4, #0x0, t0 +csrrw s4, #0x1, t0 +csrrw s4, #0x2, t0 +csrrw s4, #0x300, t0 +csrrw s4, #0x301, t0 +csrrw s4, #0x304, t0 +csrrw s4, #0x305, t0 +csrrw s4, #0x340, t0 +csrrw s4, #0x341, t0 +csrrw s4, #0xfff, t0 +csrrw s4, #0x0, a0 +csrrw s4, #0x1, a0 +csrrw s4, #0x2, a0 +csrrw s4, #0x300, a0 +csrrw s4, #0x301, a0 +csrrw s4, #0x304, a0 +csrrw s4, #0x305, a0 +csrrw s4, #0x340, a0 +csrrw s4, #0x341, a0 +csrrw s4, #0xfff, a0 +csrrw s4, #0x0, a5 +csrrw s4, #0x1, a5 +csrrw s4, #0x2, a5 +csrrw s4, #0x300, a5 +csrrw s4, #0x301, a5 +csrrw s4, #0x304, a5 +csrrw s4, #0x305, a5 +csrrw s4, #0x340, a5 +csrrw s4, #0x341, a5 +csrrw s4, #0xfff, a5 +csrrw s4, #0x0, s4 +csrrw s4, #0x1, s4 +csrrw s4, #0x2, s4 +csrrw s4, #0x300, s4 +csrrw s4, #0x301, s4 +csrrw s4, #0x304, s4 +csrrw s4, #0x305, s4 +csrrw s4, #0x340, s4 +csrrw s4, #0x341, s4 +csrrw s4, #0xfff, s4 +csrrw s4, #0x0, s9 +csrrw s4, #0x1, s9 +csrrw s4, #0x2, s9 +csrrw s4, #0x300, s9 +csrrw s4, #0x301, s9 +csrrw s4, #0x304, s9 +csrrw s4, #0x305, s9 +csrrw s4, #0x340, s9 +csrrw s4, #0x341, s9 +csrrw s4, #0xfff, s9 +csrrw s4, #0x0, t6 +csrrw s4, #0x1, t6 +csrrw s4, #0x2, t6 +csrrw s4, #0x300, t6 +csrrw s4, #0x301, t6 +csrrw s4, #0x304, t6 +csrrw s4, #0x305, t6 +csrrw s4, #0x340, t6 +csrrw s4, #0x341, t6 +csrrw s4, #0xfff, t6 +csrrw s9, #0x0, zero +csrrw s9, #0x1, zero +csrrw s9, #0x2, zero +csrrw s9, #0x300, zero +csrrw s9, #0x301, zero +csrrw s9, #0x304, zero +csrrw s9, #0x305, zero +csrrw s9, #0x340, zero +csrrw s9, #0x341, zero +csrrw s9, #0xfff, zero +csrrw s9, #0x0, ra +csrrw s9, #0x1, ra +csrrw s9, #0x2, ra +csrrw s9, #0x300, ra +csrrw s9, #0x301, ra +csrrw s9, #0x304, ra +csrrw s9, #0x305, ra +csrrw s9, #0x340, ra +csrrw s9, #0x341, ra +csrrw s9, #0xfff, ra +csrrw s9, #0x0, t0 +csrrw s9, #0x1, t0 +csrrw s9, #0x2, t0 +csrrw s9, #0x300, t0 +csrrw s9, #0x301, t0 +csrrw s9, #0x304, t0 +csrrw s9, #0x305, t0 +csrrw s9, #0x340, t0 +csrrw s9, #0x341, t0 +csrrw s9, #0xfff, t0 +csrrw s9, #0x0, a0 +csrrw s9, #0x1, a0 +csrrw s9, #0x2, a0 +csrrw s9, #0x300, a0 +csrrw s9, #0x301, a0 +csrrw s9, #0x304, a0 +csrrw s9, #0x305, a0 +csrrw s9, #0x340, a0 +csrrw s9, #0x341, a0 +csrrw s9, #0xfff, a0 +csrrw s9, #0x0, a5 +csrrw s9, #0x1, a5 +csrrw s9, #0x2, a5 +csrrw s9, #0x300, a5 +csrrw s9, #0x301, a5 +csrrw s9, #0x304, a5 +csrrw s9, #0x305, a5 +csrrw s9, #0x340, a5 +csrrw s9, #0x341, a5 +csrrw s9, #0xfff, a5 +csrrw s9, #0x0, s4 +csrrw s9, #0x1, s4 +csrrw s9, #0x2, s4 +csrrw s9, #0x300, s4 +csrrw s9, #0x301, s4 +csrrw s9, #0x304, s4 +csrrw s9, #0x305, s4 +csrrw s9, #0x340, s4 +csrrw s9, #0x341, s4 +csrrw s9, #0xfff, s4 +csrrw s9, #0x0, s9 +csrrw s9, #0x1, s9 +csrrw s9, #0x2, s9 +csrrw s9, #0x300, s9 +csrrw s9, #0x301, s9 +csrrw s9, #0x304, s9 +csrrw s9, #0x305, s9 +csrrw s9, #0x340, s9 +csrrw s9, #0x341, s9 +csrrw s9, #0xfff, s9 +csrrw s9, #0x0, t6 +csrrw s9, #0x1, t6 +csrrw s9, #0x2, t6 +csrrw s9, #0x300, t6 +csrrw s9, #0x301, t6 +csrrw s9, #0x304, t6 +csrrw s9, #0x305, t6 +csrrw s9, #0x340, t6 +csrrw s9, #0x341, t6 +csrrw s9, #0xfff, t6 +csrrw t6, #0x0, zero +csrrw t6, #0x1, zero +csrrw t6, #0x2, zero +csrrw t6, #0x300, zero +csrrw t6, #0x301, zero +csrrw t6, #0x304, zero +csrrw t6, #0x305, zero +csrrw t6, #0x340, zero +csrrw t6, #0x341, zero +csrrw t6, #0xfff, zero +csrrw t6, #0x0, ra +csrrw t6, #0x1, ra +csrrw t6, #0x2, ra +csrrw t6, #0x300, ra +csrrw t6, #0x301, ra +csrrw t6, #0x304, ra +csrrw t6, #0x305, ra +csrrw t6, #0x340, ra +csrrw t6, #0x341, ra +csrrw t6, #0xfff, ra +csrrw t6, #0x0, t0 +csrrw t6, #0x1, t0 +csrrw t6, #0x2, t0 +csrrw t6, #0x300, t0 +csrrw t6, #0x301, t0 +csrrw t6, #0x304, t0 +csrrw t6, #0x305, t0 +csrrw t6, #0x340, t0 +csrrw t6, #0x341, t0 +csrrw t6, #0xfff, t0 +csrrw t6, #0x0, a0 +csrrw t6, #0x1, a0 +csrrw t6, #0x2, a0 +csrrw t6, #0x300, a0 +csrrw t6, #0x301, a0 +csrrw t6, #0x304, a0 +csrrw t6, #0x305, a0 +csrrw t6, #0x340, a0 +csrrw t6, #0x341, a0 +csrrw t6, #0xfff, a0 +csrrw t6, #0x0, a5 +csrrw t6, #0x1, a5 +csrrw t6, #0x2, a5 +csrrw t6, #0x300, a5 +csrrw t6, #0x301, a5 +csrrw t6, #0x304, a5 +csrrw t6, #0x305, a5 +csrrw t6, #0x340, a5 +csrrw t6, #0x341, a5 +csrrw t6, #0xfff, a5 +csrrw t6, #0x0, s4 +csrrw t6, #0x1, s4 +csrrw t6, #0x2, s4 +csrrw t6, #0x300, s4 +csrrw t6, #0x301, s4 +csrrw t6, #0x304, s4 +csrrw t6, #0x305, s4 +csrrw t6, #0x340, s4 +csrrw t6, #0x341, s4 +csrrw t6, #0xfff, s4 +csrrw t6, #0x0, s9 +csrrw t6, #0x1, s9 +csrrw t6, #0x2, s9 +csrrw t6, #0x300, s9 +csrrw t6, #0x301, s9 +csrrw t6, #0x304, s9 +csrrw t6, #0x305, s9 +csrrw t6, #0x340, s9 +csrrw t6, #0x341, s9 +csrrw t6, #0xfff, s9 +csrrw t6, #0x0, t6 +csrrw t6, #0x1, t6 +csrrw t6, #0x2, t6 +csrrw t6, #0x300, t6 +csrrw t6, #0x301, t6 +csrrw t6, #0x304, t6 +csrrw t6, #0x305, t6 +csrrw t6, #0x340, t6 +csrrw t6, #0x341, t6 +csrrw t6, #0xfff, t6 + diff --git a/tests/riscv/zicsr-extension/csrrw.bin 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zero, #0x305, ra +csrrw zero, #0x340, ra +csrrw zero, #0x341, ra +csrrw zero, #0xFFF, ra +csrrw zero, #0x000, t0 +csrrw zero, #0x001, t0 +csrrw zero, #0x002, t0 +csrrw zero, #0x300, t0 +csrrw zero, #0x301, t0 +csrrw zero, #0x304, t0 +csrrw zero, #0x305, t0 +csrrw zero, #0x340, t0 +csrrw zero, #0x341, t0 +csrrw zero, #0xFFF, t0 +csrrw zero, #0x000, a0 +csrrw zero, #0x001, a0 +csrrw zero, #0x002, a0 +csrrw zero, #0x300, a0 +csrrw zero, #0x301, a0 +csrrw zero, #0x304, a0 +csrrw zero, #0x305, a0 +csrrw zero, #0x340, a0 +csrrw zero, #0x341, a0 +csrrw zero, #0xFFF, a0 +csrrw zero, #0x000, a5 +csrrw zero, #0x001, a5 +csrrw zero, #0x002, a5 +csrrw zero, #0x300, a5 +csrrw zero, #0x301, a5 +csrrw zero, #0x304, a5 +csrrw zero, #0x305, a5 +csrrw zero, #0x340, a5 +csrrw zero, #0x341, a5 +csrrw zero, #0xFFF, a5 +csrrw zero, #0x000, s4 +csrrw zero, #0x001, s4 +csrrw zero, #0x002, s4 +csrrw zero, #0x300, s4 +csrrw zero, #0x301, s4 +csrrw zero, #0x304, s4 +csrrw zero, #0x305, s4 +csrrw zero, #0x340, s4 +csrrw zero, #0x341, s4 +csrrw zero, #0xFFF, s4 +csrrw zero, #0x000, s9 +csrrw zero, #0x001, s9 +csrrw zero, #0x002, s9 +csrrw zero, #0x300, s9 +csrrw zero, #0x301, s9 +csrrw zero, #0x304, s9 +csrrw zero, #0x305, s9 +csrrw zero, #0x340, s9 +csrrw zero, #0x341, s9 +csrrw zero, #0xFFF, s9 +csrrw zero, #0x000, t6 +csrrw zero, #0x001, t6 +csrrw zero, #0x002, t6 +csrrw zero, #0x300, t6 +csrrw zero, #0x301, t6 +csrrw zero, #0x304, t6 +csrrw zero, #0x305, t6 +csrrw zero, #0x340, t6 +csrrw zero, #0x341, t6 +csrrw zero, #0xFFF, t6 +csrrw ra, #0x000, zero +csrrw ra, #0x001, zero +csrrw ra, #0x002, zero +csrrw ra, #0x300, zero +csrrw ra, #0x301, zero +csrrw ra, #0x304, zero +csrrw ra, #0x305, zero +csrrw ra, #0x340, zero +csrrw ra, #0x341, zero +csrrw ra, #0xFFF, zero +csrrw ra, #0x000, ra +csrrw ra, #0x001, ra +csrrw ra, #0x002, ra +csrrw ra, #0x300, ra +csrrw ra, #0x301, ra +csrrw ra, #0x304, ra +csrrw ra, #0x305, ra +csrrw ra, #0x340, ra +csrrw ra, #0x341, ra +csrrw ra, #0xFFF, ra +csrrw ra, #0x000, t0 +csrrw ra, #0x001, t0 +csrrw ra, #0x002, t0 +csrrw ra, #0x300, t0 +csrrw ra, #0x301, t0 +csrrw ra, #0x304, t0 +csrrw ra, #0x305, t0 +csrrw ra, #0x340, t0 +csrrw ra, #0x341, t0 +csrrw ra, #0xFFF, t0 +csrrw ra, #0x000, a0 +csrrw ra, #0x001, a0 +csrrw ra, #0x002, a0 +csrrw ra, #0x300, a0 +csrrw ra, #0x301, a0 +csrrw ra, #0x304, a0 +csrrw ra, #0x305, a0 +csrrw ra, #0x340, a0 +csrrw ra, #0x341, a0 +csrrw ra, #0xFFF, a0 +csrrw ra, #0x000, a5 +csrrw ra, #0x001, a5 +csrrw ra, #0x002, a5 +csrrw ra, #0x300, a5 +csrrw ra, #0x301, a5 +csrrw ra, #0x304, a5 +csrrw ra, #0x305, a5 +csrrw ra, #0x340, a5 +csrrw ra, #0x341, a5 +csrrw ra, #0xFFF, a5 +csrrw ra, #0x000, s4 +csrrw ra, #0x001, s4 +csrrw ra, #0x002, s4 +csrrw ra, #0x300, s4 +csrrw ra, #0x301, s4 +csrrw ra, #0x304, s4 +csrrw ra, #0x305, s4 +csrrw ra, #0x340, s4 +csrrw ra, #0x341, s4 +csrrw ra, #0xFFF, s4 +csrrw ra, #0x000, s9 +csrrw ra, #0x001, s9 +csrrw ra, #0x002, s9 +csrrw ra, #0x300, s9 +csrrw ra, #0x301, s9 +csrrw ra, #0x304, s9 +csrrw ra, #0x305, s9 +csrrw ra, #0x340, s9 +csrrw ra, #0x341, s9 +csrrw ra, #0xFFF, s9 +csrrw ra, #0x000, t6 +csrrw ra, #0x001, t6 +csrrw ra, #0x002, t6 +csrrw ra, #0x300, t6 +csrrw ra, #0x301, t6 +csrrw ra, #0x304, t6 +csrrw ra, #0x305, t6 +csrrw ra, #0x340, t6 +csrrw ra, #0x341, t6 +csrrw ra, #0xFFF, t6 +csrrw t0, #0x000, zero +csrrw t0, #0x001, zero +csrrw t0, #0x002, zero +csrrw t0, #0x300, zero +csrrw t0, #0x301, zero +csrrw t0, #0x304, zero +csrrw t0, #0x305, zero +csrrw t0, #0x340, zero +csrrw t0, #0x341, zero +csrrw t0, #0xFFF, zero +csrrw t0, #0x000, ra +csrrw t0, #0x001, ra +csrrw t0, #0x002, ra +csrrw t0, #0x300, ra +csrrw t0, #0x301, ra +csrrw t0, #0x304, ra +csrrw t0, #0x305, ra +csrrw t0, #0x340, ra +csrrw t0, #0x341, ra +csrrw t0, #0xFFF, ra +csrrw t0, #0x000, t0 +csrrw t0, #0x001, t0 +csrrw t0, #0x002, t0 +csrrw t0, #0x300, t0 +csrrw t0, #0x301, t0 +csrrw t0, #0x304, t0 +csrrw t0, #0x305, t0 +csrrw t0, #0x340, t0 +csrrw t0, #0x341, t0 +csrrw t0, #0xFFF, t0 +csrrw t0, #0x000, a0 +csrrw t0, #0x001, a0 +csrrw t0, #0x002, a0 +csrrw t0, #0x300, a0 +csrrw t0, #0x301, a0 +csrrw t0, #0x304, a0 +csrrw t0, #0x305, a0 +csrrw t0, #0x340, a0 +csrrw t0, #0x341, a0 +csrrw t0, #0xFFF, a0 +csrrw t0, #0x000, a5 +csrrw t0, #0x001, a5 +csrrw t0, #0x002, a5 +csrrw t0, #0x300, a5 +csrrw t0, #0x301, a5 +csrrw t0, #0x304, a5 +csrrw t0, #0x305, a5 +csrrw t0, #0x340, a5 +csrrw t0, #0x341, a5 +csrrw t0, #0xFFF, a5 +csrrw t0, #0x000, s4 +csrrw t0, #0x001, s4 +csrrw t0, #0x002, s4 +csrrw t0, #0x300, s4 +csrrw t0, #0x301, s4 +csrrw t0, #0x304, s4 +csrrw t0, #0x305, s4 +csrrw t0, #0x340, s4 +csrrw t0, #0x341, s4 +csrrw t0, #0xFFF, s4 +csrrw t0, #0x000, s9 +csrrw t0, #0x001, s9 +csrrw t0, #0x002, s9 +csrrw t0, #0x300, s9 +csrrw t0, #0x301, s9 +csrrw t0, #0x304, s9 +csrrw t0, #0x305, s9 +csrrw t0, #0x340, s9 +csrrw t0, #0x341, s9 +csrrw t0, #0xFFF, s9 +csrrw t0, #0x000, t6 +csrrw t0, #0x001, t6 +csrrw t0, #0x002, t6 +csrrw t0, #0x300, t6 +csrrw t0, #0x301, t6 +csrrw t0, #0x304, t6 +csrrw t0, #0x305, t6 +csrrw t0, #0x340, t6 +csrrw t0, #0x341, t6 +csrrw t0, #0xFFF, t6 +csrrw a0, #0x000, zero +csrrw a0, #0x001, zero +csrrw a0, #0x002, zero +csrrw a0, #0x300, zero +csrrw a0, #0x301, zero +csrrw a0, #0x304, zero +csrrw a0, #0x305, zero +csrrw a0, #0x340, zero +csrrw a0, #0x341, zero +csrrw a0, #0xFFF, zero +csrrw a0, #0x000, ra +csrrw a0, #0x001, ra +csrrw a0, #0x002, ra +csrrw a0, #0x300, ra +csrrw a0, #0x301, ra +csrrw a0, #0x304, ra +csrrw a0, #0x305, ra +csrrw a0, #0x340, ra +csrrw a0, #0x341, ra +csrrw a0, #0xFFF, ra +csrrw a0, #0x000, t0 +csrrw a0, #0x001, t0 +csrrw a0, #0x002, t0 +csrrw a0, #0x300, t0 +csrrw a0, #0x301, t0 +csrrw a0, #0x304, t0 +csrrw a0, #0x305, t0 +csrrw a0, #0x340, t0 +csrrw a0, #0x341, t0 +csrrw a0, #0xFFF, t0 +csrrw a0, #0x000, a0 +csrrw a0, #0x001, a0 +csrrw a0, #0x002, a0 +csrrw a0, #0x300, a0 +csrrw a0, #0x301, a0 +csrrw a0, #0x304, a0 +csrrw a0, #0x305, a0 +csrrw a0, #0x340, a0 +csrrw a0, #0x341, a0 +csrrw a0, #0xFFF, a0 +csrrw a0, #0x000, a5 +csrrw a0, #0x001, a5 +csrrw a0, #0x002, a5 +csrrw a0, #0x300, a5 +csrrw a0, #0x301, a5 +csrrw a0, #0x304, a5 +csrrw a0, #0x305, a5 +csrrw a0, #0x340, a5 +csrrw a0, #0x341, a5 +csrrw a0, #0xFFF, a5 +csrrw a0, #0x000, s4 +csrrw a0, #0x001, s4 +csrrw a0, #0x002, s4 +csrrw a0, #0x300, s4 +csrrw a0, #0x301, s4 +csrrw a0, #0x304, s4 +csrrw a0, #0x305, s4 +csrrw a0, #0x340, s4 +csrrw a0, #0x341, s4 +csrrw a0, #0xFFF, s4 +csrrw a0, #0x000, s9 +csrrw a0, #0x001, s9 +csrrw a0, #0x002, s9 +csrrw a0, #0x300, s9 +csrrw a0, #0x301, s9 +csrrw a0, #0x304, s9 +csrrw a0, #0x305, s9 +csrrw a0, #0x340, s9 +csrrw a0, #0x341, s9 +csrrw a0, #0xFFF, s9 +csrrw a0, #0x000, t6 +csrrw a0, #0x001, t6 +csrrw a0, #0x002, t6 +csrrw a0, #0x300, t6 +csrrw a0, #0x301, t6 +csrrw a0, #0x304, t6 +csrrw a0, #0x305, t6 +csrrw a0, #0x340, t6 +csrrw a0, #0x341, t6 +csrrw a0, #0xFFF, t6 +csrrw a5, #0x000, zero +csrrw a5, #0x001, zero +csrrw a5, #0x002, zero +csrrw a5, #0x300, zero +csrrw a5, #0x301, zero +csrrw a5, #0x304, zero +csrrw a5, #0x305, zero +csrrw a5, #0x340, zero +csrrw a5, #0x341, zero +csrrw a5, #0xFFF, zero +csrrw a5, #0x000, ra +csrrw a5, #0x001, ra +csrrw a5, #0x002, ra +csrrw a5, #0x300, ra +csrrw a5, #0x301, ra +csrrw a5, #0x304, ra +csrrw a5, #0x305, ra +csrrw a5, #0x340, ra +csrrw a5, #0x341, ra +csrrw a5, #0xFFF, ra +csrrw a5, #0x000, t0 +csrrw a5, #0x001, t0 +csrrw a5, #0x002, t0 +csrrw a5, #0x300, t0 +csrrw a5, #0x301, t0 +csrrw a5, #0x304, t0 +csrrw a5, #0x305, t0 +csrrw a5, #0x340, t0 +csrrw a5, #0x341, t0 +csrrw a5, #0xFFF, t0 +csrrw a5, #0x000, a0 +csrrw a5, #0x001, a0 +csrrw a5, #0x002, a0 +csrrw a5, #0x300, a0 +csrrw a5, #0x301, a0 +csrrw a5, #0x304, a0 +csrrw a5, #0x305, a0 +csrrw a5, #0x340, a0 +csrrw a5, #0x341, a0 +csrrw a5, #0xFFF, a0 +csrrw a5, #0x000, a5 +csrrw a5, #0x001, a5 +csrrw a5, #0x002, a5 +csrrw a5, #0x300, a5 +csrrw a5, #0x301, a5 +csrrw a5, #0x304, a5 +csrrw a5, #0x305, a5 +csrrw a5, #0x340, a5 +csrrw a5, #0x341, a5 +csrrw a5, #0xFFF, a5 +csrrw a5, #0x000, s4 +csrrw a5, #0x001, s4 +csrrw a5, #0x002, s4 +csrrw a5, #0x300, s4 +csrrw a5, #0x301, s4 +csrrw a5, #0x304, s4 +csrrw a5, #0x305, s4 +csrrw a5, #0x340, s4 +csrrw a5, #0x341, s4 +csrrw a5, #0xFFF, s4 +csrrw a5, #0x000, s9 +csrrw a5, #0x001, s9 +csrrw a5, #0x002, s9 +csrrw a5, #0x300, s9 +csrrw a5, #0x301, s9 +csrrw a5, #0x304, s9 +csrrw a5, #0x305, s9 +csrrw a5, #0x340, s9 +csrrw a5, #0x341, s9 +csrrw a5, #0xFFF, s9 +csrrw a5, #0x000, t6 +csrrw a5, #0x001, t6 +csrrw a5, #0x002, t6 +csrrw a5, #0x300, t6 +csrrw a5, #0x301, t6 +csrrw a5, #0x304, t6 +csrrw a5, #0x305, t6 +csrrw a5, #0x340, t6 +csrrw a5, #0x341, t6 +csrrw a5, #0xFFF, t6 +csrrw s4, #0x000, zero +csrrw s4, #0x001, zero +csrrw s4, #0x002, zero +csrrw s4, #0x300, zero +csrrw s4, #0x301, zero +csrrw s4, #0x304, zero +csrrw s4, #0x305, zero +csrrw s4, #0x340, zero +csrrw s4, #0x341, zero +csrrw s4, #0xFFF, zero +csrrw s4, #0x000, ra +csrrw s4, #0x001, ra +csrrw s4, #0x002, ra +csrrw s4, #0x300, ra +csrrw s4, #0x301, ra +csrrw s4, #0x304, ra +csrrw s4, #0x305, ra +csrrw s4, #0x340, ra +csrrw s4, #0x341, ra +csrrw s4, #0xFFF, ra +csrrw s4, #0x000, t0 +csrrw s4, #0x001, t0 +csrrw s4, #0x002, t0 +csrrw s4, #0x300, t0 +csrrw s4, #0x301, t0 +csrrw s4, #0x304, t0 +csrrw s4, #0x305, t0 +csrrw s4, #0x340, t0 +csrrw s4, #0x341, t0 +csrrw s4, #0xFFF, t0 +csrrw s4, #0x000, a0 +csrrw s4, #0x001, a0 +csrrw s4, #0x002, a0 +csrrw s4, #0x300, a0 +csrrw s4, #0x301, a0 +csrrw s4, #0x304, a0 +csrrw s4, #0x305, a0 +csrrw s4, #0x340, a0 +csrrw s4, #0x341, a0 +csrrw s4, #0xFFF, a0 +csrrw s4, #0x000, a5 +csrrw s4, #0x001, a5 +csrrw s4, #0x002, a5 +csrrw s4, #0x300, a5 +csrrw s4, #0x301, a5 +csrrw s4, #0x304, a5 +csrrw s4, #0x305, a5 +csrrw s4, #0x340, a5 +csrrw s4, #0x341, a5 +csrrw s4, #0xFFF, a5 +csrrw s4, #0x000, s4 +csrrw s4, #0x001, s4 +csrrw s4, #0x002, s4 +csrrw s4, #0x300, s4 +csrrw s4, #0x301, s4 +csrrw s4, #0x304, s4 +csrrw s4, #0x305, s4 +csrrw s4, #0x340, s4 +csrrw s4, #0x341, s4 +csrrw s4, #0xFFF, s4 +csrrw s4, #0x000, s9 +csrrw s4, #0x001, s9 +csrrw s4, #0x002, s9 +csrrw s4, #0x300, s9 +csrrw s4, #0x301, s9 +csrrw s4, #0x304, s9 +csrrw s4, #0x305, s9 +csrrw s4, #0x340, s9 +csrrw s4, #0x341, s9 +csrrw s4, #0xFFF, s9 +csrrw s4, #0x000, t6 +csrrw s4, #0x001, t6 +csrrw s4, #0x002, t6 +csrrw s4, #0x300, t6 +csrrw s4, #0x301, t6 +csrrw s4, #0x304, t6 +csrrw s4, #0x305, t6 +csrrw s4, #0x340, t6 +csrrw s4, #0x341, t6 +csrrw s4, #0xFFF, t6 +csrrw s9, #0x000, zero +csrrw s9, #0x001, zero +csrrw s9, #0x002, zero +csrrw s9, #0x300, zero +csrrw s9, #0x301, zero +csrrw s9, #0x304, zero +csrrw s9, #0x305, zero +csrrw s9, #0x340, zero +csrrw s9, #0x341, zero +csrrw s9, #0xFFF, zero +csrrw s9, #0x000, ra +csrrw s9, #0x001, ra +csrrw s9, #0x002, ra +csrrw s9, #0x300, ra +csrrw s9, #0x301, ra +csrrw s9, #0x304, ra +csrrw s9, #0x305, ra +csrrw s9, #0x340, ra +csrrw s9, #0x341, ra +csrrw s9, #0xFFF, ra +csrrw s9, #0x000, t0 +csrrw s9, #0x001, t0 +csrrw s9, #0x002, t0 +csrrw s9, #0x300, t0 +csrrw s9, #0x301, t0 +csrrw s9, #0x304, t0 +csrrw s9, #0x305, t0 +csrrw s9, #0x340, t0 +csrrw s9, #0x341, t0 +csrrw s9, #0xFFF, t0 +csrrw s9, #0x000, a0 +csrrw s9, #0x001, a0 +csrrw s9, #0x002, a0 +csrrw s9, #0x300, a0 +csrrw s9, #0x301, a0 +csrrw s9, #0x304, a0 +csrrw s9, #0x305, a0 +csrrw s9, #0x340, a0 +csrrw s9, #0x341, a0 +csrrw s9, #0xFFF, a0 +csrrw s9, #0x000, a5 +csrrw s9, #0x001, a5 +csrrw s9, #0x002, a5 +csrrw s9, #0x300, a5 +csrrw s9, #0x301, a5 +csrrw s9, #0x304, a5 +csrrw s9, #0x305, a5 +csrrw s9, #0x340, a5 +csrrw s9, #0x341, a5 +csrrw s9, #0xFFF, a5 +csrrw s9, #0x000, s4 +csrrw s9, #0x001, s4 +csrrw s9, #0x002, s4 +csrrw s9, #0x300, s4 +csrrw s9, #0x301, s4 +csrrw s9, #0x304, s4 +csrrw s9, #0x305, s4 +csrrw s9, #0x340, s4 +csrrw s9, #0x341, s4 +csrrw s9, #0xFFF, s4 +csrrw s9, #0x000, s9 +csrrw s9, #0x001, s9 +csrrw s9, #0x002, s9 +csrrw s9, #0x300, s9 +csrrw s9, #0x301, s9 +csrrw s9, #0x304, s9 +csrrw s9, #0x305, s9 +csrrw s9, #0x340, s9 +csrrw s9, #0x341, s9 +csrrw s9, #0xFFF, s9 +csrrw s9, #0x000, t6 +csrrw s9, #0x001, t6 +csrrw s9, #0x002, t6 +csrrw s9, #0x300, t6 +csrrw s9, #0x301, t6 +csrrw s9, #0x304, t6 +csrrw s9, #0x305, t6 +csrrw s9, #0x340, t6 +csrrw s9, #0x341, t6 +csrrw s9, #0xFFF, t6 +csrrw t6, #0x000, zero +csrrw t6, #0x001, zero +csrrw t6, #0x002, zero +csrrw t6, #0x300, zero +csrrw t6, #0x301, zero +csrrw t6, #0x304, zero +csrrw t6, #0x305, zero +csrrw t6, #0x340, zero +csrrw t6, #0x341, zero +csrrw t6, #0xFFF, zero +csrrw t6, #0x000, ra +csrrw t6, #0x001, ra +csrrw t6, #0x002, ra +csrrw t6, #0x300, ra +csrrw t6, #0x301, ra +csrrw t6, #0x304, ra +csrrw t6, #0x305, ra +csrrw t6, #0x340, ra +csrrw t6, #0x341, ra +csrrw t6, #0xFFF, ra +csrrw t6, #0x000, t0 +csrrw t6, #0x001, t0 +csrrw t6, #0x002, t0 +csrrw t6, #0x300, t0 +csrrw t6, #0x301, t0 +csrrw t6, #0x304, t0 +csrrw t6, #0x305, t0 +csrrw t6, #0x340, t0 +csrrw t6, #0x341, t0 +csrrw t6, #0xFFF, t0 +csrrw t6, #0x000, a0 +csrrw t6, #0x001, a0 +csrrw t6, #0x002, a0 +csrrw t6, #0x300, a0 +csrrw t6, #0x301, a0 +csrrw t6, #0x304, a0 +csrrw t6, #0x305, a0 +csrrw t6, #0x340, a0 +csrrw t6, #0x341, a0 +csrrw t6, #0xFFF, a0 +csrrw t6, #0x000, a5 +csrrw t6, #0x001, a5 +csrrw t6, #0x002, a5 +csrrw t6, #0x300, a5 +csrrw t6, #0x301, a5 +csrrw t6, #0x304, a5 +csrrw t6, #0x305, a5 +csrrw t6, #0x340, a5 +csrrw t6, #0x341, a5 +csrrw t6, #0xFFF, a5 +csrrw t6, #0x000, s4 +csrrw t6, #0x001, s4 +csrrw t6, #0x002, s4 +csrrw t6, #0x300, s4 +csrrw t6, #0x301, s4 +csrrw t6, #0x304, s4 +csrrw t6, #0x305, s4 +csrrw t6, #0x340, s4 +csrrw t6, #0x341, s4 +csrrw t6, #0xFFF, s4 +csrrw t6, #0x000, s9 +csrrw t6, #0x001, s9 +csrrw t6, #0x002, s9 +csrrw t6, #0x300, s9 +csrrw t6, #0x301, s9 +csrrw t6, #0x304, s9 +csrrw t6, #0x305, s9 +csrrw t6, #0x340, s9 +csrrw t6, #0x341, s9 +csrrw t6, #0xFFF, s9 +csrrw t6, #0x000, t6 +csrrw t6, #0x001, t6 +csrrw t6, #0x002, t6 +csrrw t6, #0x300, t6 +csrrw t6, #0x301, t6 +csrrw t6, #0x304, t6 +csrrw t6, #0x305, t6 +csrrw t6, #0x340, t6 +csrrw t6, #0x341, t6 +csrrw t6, #0xFFF, t6 diff --git a/tests/riscv/zicsr-extension/csrrwi.asm b/tests/riscv/zicsr-extension/csrrwi.asm new file mode 100644 index 0000000..ea7f5b8 --- /dev/null +++ b/tests/riscv/zicsr-extension/csrrwi.asm @@ -0,0 +1,644 @@ +.lang riscv32 +.org 0x0 + +csrrwi zero, #0x0, #0 +csrrwi zero, #0x1, #0 +csrrwi zero, #0x2, #0 +csrrwi zero, #0x300, #0 +csrrwi zero, #0x301, #0 +csrrwi zero, #0x304, #0 +csrrwi zero, #0x305, #0 +csrrwi zero, #0x340, #0 +csrrwi zero, #0x341, #0 +csrrwi zero, #0xfff, #0 +csrrwi zero, #0x0, #1 +csrrwi zero, #0x1, #1 +csrrwi zero, #0x2, #1 +csrrwi zero, #0x300, #1 +csrrwi zero, #0x301, #1 +csrrwi zero, #0x304, #1 +csrrwi zero, #0x305, #1 +csrrwi zero, #0x340, #1 +csrrwi zero, #0x341, #1 +csrrwi zero, #0xfff, #1 +csrrwi zero, #0x0, #5 +csrrwi zero, #0x1, #5 +csrrwi zero, #0x2, #5 +csrrwi zero, #0x300, #5 +csrrwi zero, #0x301, #5 +csrrwi zero, #0x304, #5 +csrrwi zero, #0x305, #5 +csrrwi zero, #0x340, #5 +csrrwi zero, #0x341, #5 +csrrwi zero, #0xfff, #5 +csrrwi zero, #0x0, #10 +csrrwi zero, #0x1, #10 +csrrwi zero, #0x2, #10 +csrrwi zero, #0x300, #10 +csrrwi zero, #0x301, #10 +csrrwi zero, #0x304, #10 +csrrwi zero, #0x305, #10 +csrrwi zero, #0x340, #10 +csrrwi zero, #0x341, #10 +csrrwi zero, #0xfff, #10 +csrrwi zero, #0x0, #15 +csrrwi zero, #0x1, #15 +csrrwi zero, #0x2, #15 +csrrwi zero, #0x300, #15 +csrrwi zero, #0x301, #15 +csrrwi zero, #0x304, #15 +csrrwi zero, #0x305, #15 +csrrwi zero, #0x340, #15 +csrrwi zero, #0x341, #15 +csrrwi zero, #0xfff, #15 +csrrwi zero, #0x0, #20 +csrrwi zero, #0x1, #20 +csrrwi zero, #0x2, #20 +csrrwi zero, #0x300, #20 +csrrwi zero, #0x301, #20 +csrrwi zero, #0x304, #20 +csrrwi zero, #0x305, #20 +csrrwi zero, #0x340, #20 +csrrwi zero, #0x341, #20 +csrrwi zero, #0xfff, #20 +csrrwi zero, #0x0, #25 +csrrwi zero, #0x1, #25 +csrrwi zero, #0x2, #25 +csrrwi zero, #0x300, #25 +csrrwi zero, #0x301, #25 +csrrwi zero, #0x304, #25 +csrrwi zero, #0x305, #25 +csrrwi zero, #0x340, #25 +csrrwi zero, #0x341, #25 +csrrwi zero, #0xfff, #25 +csrrwi zero, #0x0, #31 +csrrwi zero, #0x1, #31 +csrrwi zero, #0x2, #31 +csrrwi zero, #0x300, #31 +csrrwi zero, #0x301, #31 +csrrwi zero, #0x304, #31 +csrrwi zero, #0x305, #31 +csrrwi zero, #0x340, #31 +csrrwi zero, #0x341, #31 +csrrwi zero, #0xfff, #31 +csrrwi ra, #0x0, #0 +csrrwi ra, #0x1, #0 +csrrwi ra, #0x2, #0 +csrrwi ra, #0x300, #0 +csrrwi ra, #0x301, #0 +csrrwi ra, #0x304, #0 +csrrwi ra, #0x305, #0 +csrrwi ra, #0x340, #0 +csrrwi ra, #0x341, #0 +csrrwi ra, #0xfff, #0 +csrrwi ra, #0x0, #1 +csrrwi ra, #0x1, #1 +csrrwi ra, #0x2, #1 +csrrwi ra, #0x300, #1 +csrrwi ra, #0x301, #1 +csrrwi ra, #0x304, #1 +csrrwi ra, #0x305, #1 +csrrwi ra, #0x340, #1 +csrrwi ra, #0x341, #1 +csrrwi ra, #0xfff, #1 +csrrwi ra, #0x0, #5 +csrrwi ra, #0x1, #5 +csrrwi ra, #0x2, #5 +csrrwi ra, #0x300, #5 +csrrwi ra, #0x301, #5 +csrrwi ra, #0x304, #5 +csrrwi ra, #0x305, #5 +csrrwi ra, #0x340, #5 +csrrwi ra, #0x341, #5 +csrrwi ra, #0xfff, #5 +csrrwi ra, #0x0, #10 +csrrwi ra, #0x1, #10 +csrrwi ra, #0x2, #10 +csrrwi ra, #0x300, #10 +csrrwi ra, #0x301, #10 +csrrwi ra, #0x304, #10 +csrrwi ra, #0x305, #10 +csrrwi ra, #0x340, #10 +csrrwi ra, #0x341, #10 +csrrwi ra, #0xfff, #10 +csrrwi ra, #0x0, #15 +csrrwi ra, #0x1, #15 +csrrwi ra, #0x2, #15 +csrrwi ra, #0x300, #15 +csrrwi ra, #0x301, #15 +csrrwi ra, #0x304, #15 +csrrwi ra, #0x305, #15 +csrrwi ra, #0x340, #15 +csrrwi ra, #0x341, #15 +csrrwi ra, #0xfff, #15 +csrrwi ra, #0x0, #20 +csrrwi ra, #0x1, #20 +csrrwi ra, #0x2, #20 +csrrwi ra, #0x300, #20 +csrrwi ra, #0x301, #20 +csrrwi ra, #0x304, #20 +csrrwi ra, #0x305, #20 +csrrwi ra, #0x340, #20 +csrrwi ra, #0x341, #20 +csrrwi ra, #0xfff, #20 +csrrwi ra, #0x0, #25 +csrrwi ra, #0x1, #25 +csrrwi ra, #0x2, #25 +csrrwi ra, #0x300, #25 +csrrwi ra, #0x301, #25 +csrrwi ra, #0x304, #25 +csrrwi ra, #0x305, #25 +csrrwi ra, #0x340, #25 +csrrwi ra, #0x341, #25 +csrrwi ra, #0xfff, #25 +csrrwi ra, #0x0, #31 +csrrwi ra, #0x1, #31 +csrrwi ra, #0x2, #31 +csrrwi ra, #0x300, #31 +csrrwi ra, #0x301, #31 +csrrwi ra, #0x304, #31 +csrrwi ra, #0x305, #31 +csrrwi ra, #0x340, #31 +csrrwi ra, #0x341, #31 +csrrwi ra, #0xfff, #31 +csrrwi t0, #0x0, #0 +csrrwi t0, #0x1, #0 +csrrwi t0, #0x2, #0 +csrrwi t0, #0x300, #0 +csrrwi t0, #0x301, #0 +csrrwi t0, #0x304, #0 +csrrwi t0, #0x305, #0 +csrrwi t0, #0x340, #0 +csrrwi t0, #0x341, #0 +csrrwi t0, #0xfff, #0 +csrrwi t0, #0x0, #1 +csrrwi t0, #0x1, #1 +csrrwi t0, #0x2, #1 +csrrwi t0, #0x300, #1 +csrrwi t0, #0x301, #1 +csrrwi t0, #0x304, #1 +csrrwi t0, #0x305, #1 +csrrwi t0, #0x340, #1 +csrrwi t0, #0x341, #1 +csrrwi t0, #0xfff, #1 +csrrwi t0, #0x0, #5 +csrrwi t0, #0x1, #5 +csrrwi t0, #0x2, #5 +csrrwi t0, #0x300, #5 +csrrwi t0, #0x301, #5 +csrrwi t0, #0x304, #5 +csrrwi t0, #0x305, #5 +csrrwi t0, #0x340, #5 +csrrwi t0, #0x341, #5 +csrrwi t0, #0xfff, #5 +csrrwi t0, #0x0, #10 +csrrwi t0, #0x1, #10 +csrrwi t0, #0x2, #10 +csrrwi t0, #0x300, #10 +csrrwi t0, #0x301, #10 +csrrwi t0, #0x304, #10 +csrrwi t0, #0x305, #10 +csrrwi t0, #0x340, #10 +csrrwi t0, #0x341, #10 +csrrwi t0, #0xfff, #10 +csrrwi t0, #0x0, #15 +csrrwi t0, #0x1, #15 +csrrwi t0, #0x2, #15 +csrrwi t0, #0x300, #15 +csrrwi t0, #0x301, #15 +csrrwi t0, #0x304, #15 +csrrwi t0, #0x305, #15 +csrrwi t0, #0x340, #15 +csrrwi t0, #0x341, #15 +csrrwi t0, #0xfff, #15 +csrrwi t0, #0x0, #20 +csrrwi t0, #0x1, #20 +csrrwi t0, #0x2, #20 +csrrwi t0, #0x300, #20 +csrrwi t0, #0x301, #20 +csrrwi t0, #0x304, #20 +csrrwi t0, #0x305, #20 +csrrwi t0, #0x340, #20 +csrrwi t0, #0x341, #20 +csrrwi t0, #0xfff, #20 +csrrwi t0, #0x0, #25 +csrrwi t0, #0x1, #25 +csrrwi t0, #0x2, #25 +csrrwi t0, #0x300, #25 +csrrwi t0, #0x301, #25 +csrrwi t0, #0x304, #25 +csrrwi t0, #0x305, #25 +csrrwi t0, #0x340, #25 +csrrwi t0, #0x341, #25 +csrrwi t0, #0xfff, #25 +csrrwi t0, #0x0, #31 +csrrwi t0, #0x1, #31 +csrrwi t0, #0x2, #31 +csrrwi t0, #0x300, #31 +csrrwi t0, #0x301, #31 +csrrwi t0, #0x304, #31 +csrrwi t0, #0x305, #31 +csrrwi t0, #0x340, #31 +csrrwi t0, #0x341, #31 +csrrwi t0, #0xfff, #31 +csrrwi a0, #0x0, #0 +csrrwi a0, #0x1, #0 +csrrwi a0, #0x2, #0 +csrrwi a0, #0x300, #0 +csrrwi a0, #0x301, #0 +csrrwi a0, #0x304, #0 +csrrwi a0, #0x305, #0 +csrrwi a0, #0x340, #0 +csrrwi a0, #0x341, #0 +csrrwi a0, #0xfff, #0 +csrrwi a0, #0x0, #1 +csrrwi a0, #0x1, #1 +csrrwi a0, #0x2, #1 +csrrwi a0, #0x300, #1 +csrrwi a0, #0x301, #1 +csrrwi a0, #0x304, #1 +csrrwi a0, #0x305, #1 +csrrwi a0, #0x340, #1 +csrrwi a0, #0x341, #1 +csrrwi a0, #0xfff, #1 +csrrwi a0, #0x0, #5 +csrrwi a0, #0x1, #5 +csrrwi a0, #0x2, #5 +csrrwi a0, #0x300, #5 +csrrwi a0, #0x301, #5 +csrrwi a0, #0x304, #5 +csrrwi a0, #0x305, #5 +csrrwi a0, #0x340, #5 +csrrwi a0, #0x341, #5 +csrrwi a0, #0xfff, #5 +csrrwi a0, #0x0, #10 +csrrwi a0, #0x1, #10 +csrrwi a0, #0x2, #10 +csrrwi a0, #0x300, #10 +csrrwi a0, #0x301, #10 +csrrwi a0, #0x304, #10 +csrrwi a0, #0x305, #10 +csrrwi a0, #0x340, #10 +csrrwi a0, #0x341, #10 +csrrwi a0, #0xfff, #10 +csrrwi a0, #0x0, #15 +csrrwi a0, #0x1, #15 +csrrwi a0, #0x2, #15 +csrrwi a0, #0x300, #15 +csrrwi a0, #0x301, #15 +csrrwi a0, #0x304, #15 +csrrwi a0, #0x305, #15 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#0x300, #31 +csrrwi t6, #0x301, #31 +csrrwi t6, #0x304, #31 +csrrwi t6, #0x305, #31 +csrrwi t6, #0x340, #31 +csrrwi t6, #0x341, #31 +csrrwi t6, #0xfff, #31 + diff --git a/tests/riscv/zicsr-extension/csrrwi.bin b/tests/riscv/zicsr-extension/csrrwi.bin new file mode 100644 index 0000000000000000000000000000000000000000..bd39cfc270b23da7f1280c3d308898c88f8bb183 GIT binary patch literal 2560 zcmWmD;bvV+9ER~N#3n+H5FtX2Ql(1sAs0}kN|h7CGK^s^A~(7XV;IBSLN%&X+2^-E zysTxt{)@-+zC7=CFVFwTzp{JuET80Ac2C~r$MNN$chEcN9rO-*2fc&dLGPe(l)YQG^4q-&ckbl9T)1&3 z-z3R}TX*uuy-RoQ<%3+haWCH`%cWcQ@>lQ5_XqhXSH3;Se^TU1=RxobxCC4RE&-Q- zOTZ=I5^xE)1YD|K)vJ0{uj*C3s#o=@UOn~jtN2y?Dt;BeieJUA;#cvj_yzm|egVIL zU%)Tm7w`-C1^fbj6~BsK#joO5@vHb%{3?DGzlvYLFW?vO3-|^60)7F%fM38b;8*dh z_*MKWeigrpU&XKDSMjU(Rs1S`6~BsK#joO5@vHb%{Oa-evf1Tkmz!N~yGPIRNuFi* zt%znlGT_Pg2d zX1|;LZs-1aBlg?ux7lyA-)6tfew+O^`)zx-ZpD5#``zq!v)|2rH~Zb}ceCH^!mT^8 z-)6tfew+O^`)&5y?6=u(yL9Vb?6=u(v)^XF&3>ExHv4V%+pcsTgnyA&kynvdkynvd zkynvdarfk1c-8f~Uf1h-U9anPy{^~w`l-ji&cDvT&cDvT&cDvT&cDvT&cDdN$iK+H z$iK+H$iK+H$iK+H$iL3N&cDvT&cDvT&cDvT&cDvT&cDdN$iK+H$iK+H$iK+H$iK+H z$iL3N&cDvT&cDvT&cDvT&cDvT&cDvT&cDvT&cDvT&cDvT&cDvT&cDQ~#H+-s#H+-s z#H+-sw0rU{yc&8#Z|DuZp*Qq~-q0I*fyKWTlg*f7JduAh2O$&;kWQB_!ayLeg(gR zU%{{7SMV$N75o-{3%`Zm!f)ZX@LTvT{1$!-zk*-Eui#hkEBF=s3VsE@f?vUJ;kWQx m_$~Yveha^a-@ Date: Mon, 16 Feb 2026 09:23:13 -0800 Subject: [PATCH 2/4] Fix kludge with RV32I v. RISCV base implementation --- CMakeLists.txt | 1 + galangriscv.cpp | 4540 +-------------------------------------------- galangriscv.h | 341 +--- galangriscv32.cpp | 2 +- galangriscv32.h | 11 +- goodasm.cpp | 2 + main.cpp | 2 +- 7 files changed, 20 insertions(+), 4879 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f2d8e8b..4c1bedc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,6 +74,7 @@ set(GOODASM_SOURCES galangtms320c28x.h galangtms320c28x.cpp galangti80.h galangti80.cpp galangriscv32.h galangriscv32.cpp + galangriscv.h galangriscv.cpp ) diff --git a/galangriscv.cpp b/galangriscv.cpp index ca2e0ba..c59d784 100644 --- a/galangriscv.cpp +++ b/galangriscv.cpp @@ -1,4543 +1,5 @@ -#include "goodasm.h" - #include "galangriscv.h" -#include "gamnemonic.h" - -#define mnem new GAMnemonic - -// https://riscv.org/specifications/ratified/ -// https://msyksphinz-self.github.io/riscv-isadoc/ -// Follow RISC-V Instruction Organization from the ISA Manual - -GALangRISCV::GALangRISCV() { - endian = LITTLE; +GALangRISCV::GALangRISCV() : GALangRISCV32() { name = "riscv"; - maxbytes = 4; // Maximum instruction length (32-bit or 16-bit compressed) - - // Register names. - regnames.clear(); - regnames - <<"zero"<<"ra"<<"sp"<<"gp"<<"tp" - <<"t0"<<"t1"<<"t2" - <<"s0"<<"s1" - <<"a0"<<"a1"<<"a2"<<"a3"<<"a4"<<"a5"<<"a6"<<"a7" - <<"s2"<<"s3"<<"s4"<<"s5"<<"s6"<<"s7"<<"s8"<<"s9"<<"s10"<<"s11" - <<"t3"<<"t4"<<"t5"<<"t6" - // Floating point registers f0-f31 - <<"f0"<<"f1"<<"f2"<<"f3"<<"f4"<<"f5"<<"f6"<<"f7" - <<"f8"<<"f9"<<"f10"<<"f11"<<"f12"<<"f13"<<"f14"<<"f15" - <<"f16"<<"f17"<<"f18"<<"f19"<<"f20"<<"f21"<<"f22"<<"f23" - <<"f24"<<"f25"<<"f26"<<"f27"<<"f28"<<"f29"<<"f30"<<"f31"; - - threshold = 0.0; - - /* Integer Computational Instructions (RV32I Base) */ - - /* R-Type Instructions */ - - /* - * Example: ADD rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00000033 (funct7=0x00, funct3=000 + opcode=0x33) - */ - insert( - mnem("add", 4, - "\x33\x00\x00\x00", // pattern 32-bit LE: 0x00000033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Add: rd = rs1 + rs2") - ->example("add a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: SUB rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x40000033 (funct7=0x20=bit30, funct3=000 + opcode=0x33) - */ - insert( - mnem("sub", 4, - "\x33\x00\x00\x40", // pattern 32-bit LE: 0x40000033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Subtract: rd = rs1 - rs2") - ->example("sub a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: SLL rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00100033 (funct7=0x00, funct3=001 + opcode=0x33) - */ - insert( - mnem("sll", 4, - "\x33\x10\x00\x00", // pattern 32-bit LE: 0x00100033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Shift Left Logical: rd = rs1 << rs2[4:0]") - ->example("sll a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: SLT rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00200033 (funct7=0x00, funct3=010 + opcode=0x33) - */ - insert( - mnem("slt", 4, - "\x33\x20\x00\x00", // pattern 32-bit LE: 0x00200033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Set Less Than: rd = (rs1 < rs2) ? 1 : 0 (signed)") - ->example("slt a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: SLTU rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00300033 (funct7=0x00, funct3=011 + opcode=0x33) - */ - insert( - mnem("sltu", 4, - "\x33\x30\x00\x00", // pattern 32-bit LE: 0x00300033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Set Less Than Unsigned: rd = (rs1 < rs2) ? 1 : 0 (unsigned)") - ->example("sltu a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: XOR rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00400033 (funct7=0x00, funct3=100 + opcode=0x33) - */ - insert( - mnem("xor", 4, - "\x33\x40\x00\x00", // pattern 32-bit LE: 0x00400033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Bitwise XOR: rd = rs1 ^ rs2") - ->example("xor a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: SRL rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00500033 (funct7=0x00, funct3=101 + opcode=0x33) - */ - insert( - mnem("srl", 4, - "\x33\x50\x00\x00", // pattern 32-bit LE: 0x00500033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Shift Right Logical: rd = rs1 >> rs2[4:0]") - ->example("srl a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: SRA rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x40500033 (funct7=0x20=bit30, funct3=101 + opcode=0x33) - */ - insert( - mnem("sra", 4, - "\x33\x50\x00\x40", // pattern 32-bit LE: 0x40500033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Shift Right Arithmetic: rd = rs1 >> rs2[4:0] (sign-extended)") - ->example("sra a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: OR rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00600033 (funct7=0x00, funct3=110 + opcode=0x33) - */ - insert( - mnem("or", 4, - "\x33\x60\x00\x00", // pattern 32-bit LE: 0x00600033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Bitwise OR: rd = rs1 | rs2") - ->example("or a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* - * Example: AND rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00700033 (funct7=0x00, funct3=111 + opcode=0x33) - */ - insert( - mnem("and", 4, - "\x33\x70\x00\x00", // pattern 32-bit LE: 0x00700033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Bitwise AND: rd = rs1 & rs2") - ->example("and a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - bits 20-24 in bytes 2-3 - - /* I-Type Instructions */ - - /* - * Example: ADDI rd, rs1, imm12 - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00000013 (funct3=000 + opcode=0x13) - */ - insert( - mnem("addi", 4, - "\x13\x00\x00\x00", // pattern 32-bit LE: 0x00000013 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Add immediate: rd = rs1 + imm") - ->example("addi a0, a0, #1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 - - /* - * Example: SLTI rd, rs1, imm12 - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00002013 (funct3=010 + opcode=0x13) - */ - insert( - mnem("slti", 4, - "\x13\x20\x00\x00", // pattern 32-bit LE: 0x00002013 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Set Less Than Immediate: rd = (rs1 < imm) ? 1 : 0 (signed)") - ->example("slti a0, a1, #10") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 - - /* - * Example: SLTIU rd, rs1, imm12 - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00003013 (funct3=011 + opcode=0x13) - */ - insert( - mnem("sltiu", 4, - "\x13\x30\x00\x00", // pattern 32-bit LE: 0x00003013 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Set Less Than Immediate Unsigned: rd = (rs1 < imm) ? 1 : 0 (unsigned)") - ->example("sltiu a0, a1, #10") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 - - /* - * Example: XORI rd, rs1, imm12 - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00004013 (funct3=100 + opcode=0x13) - */ - insert( - mnem("xori", 4, - "\x13\x40\x00\x00", // pattern 32-bit LE: 0x00004013 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("XOR Immediate: rd = rs1 ^ imm") - ->example("xori a0, a1, #0xFF") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 - - /* - * Example: ORI rd, rs1, imm12 - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00006013 (funct3=110 + opcode=0x13) - */ - insert( - mnem("ori", 4, - "\x13\x60\x00\x00", // pattern 32-bit LE: 0x00006013 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("OR Immediate: rd = rs1 | imm") - ->example("ori a0, a1, #0xFF") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 - - /* - * Example: ANDI rd, rs1, imm12 - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00007013 (funct3=111 + opcode=0x13) - */ - insert( - mnem("andi", 4, - "\x13\x70\x00\x00", // pattern 32-bit LE: 0x00007013 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("AND Immediate: rd = rs1 & imm") - ->example("andi a0, a1, #0xFF") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - bit 7 in byte 0, bits 8-11 in byte 1 - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - bit 15 in byte 1, bits 16-19 in byte 2 - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - bit 20-23 in byte 2, bits 24-31 in byte 3 - - /* I-type Shift Immediate Instructions */ - - /* - * Example: SLLI rd, rs1, shamt5 - * - * Encoding: - * shamt[4:0] rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00100013 (funct7=0x00, funct3=001 + opcode=0x13) - * - * shamt[4:0] is in bits [24:20] - */ - insert( - mnem("slli", 4, - "\x13\x10\x00\x00", // pattern 32-bit LE: 0x00100013 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Shift Left Logical Immediate: rd = rs1 << shamt") - ->example("slli a0, a1, #5") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] - - /* - * Example: SRLI rd, rs1, shamt5 - * - * Encoding: - * shamt[4:0] rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00500013 (funct7=0x00, funct3=101 + opcode=0x13) - */ - insert( - mnem("srli", 4, - "\x13\x50\x00\x00", // pattern 32-bit LE: 0x00500013 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Shift Right Logical Immediate: rd = rs1 >> shamt") - ->example("srli a0, a1, #5") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] - - /* - * Example: SRAI rd, rs1, shamt5 - * - * Encoding: - * shamt[4:0] rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x40500013 (funct7=0x20, funct3=101 + opcode=0x13) - */ - insert( - mnem("srai", 4, - "\x13\x50\x00\x40", // pattern 32-bit LE: 0x40500013 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Shift Right Arithmetic Immediate: rd = rs1 >> shamt (sign-extended)") - ->example("srai a0, a1, #5") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvShamt5("\x00\x00\xF0\x01")); // shamt[4:0] bits [24:20] - - /* Control Transfer Instructions */ - - /* U-Type Control Transfer Instructions */ - - /* - * Example: LUI rd, imm20 - * - * Encoding: - * imm[31:12] rd opcode - * - * Mask : 0x0000007F (mask opcode) - * Value : 0x00000037 (opcode=0x37) - */ - insert( - mnem("lui", 4, - "\x37\x00\x00\x00", // pattern 32-bit LE: 0x00000037 - "\x7F\x00\x00\x00")) // mask: opcode only - ->help("Load Upper Immediate: rd = imm << 12") - ->example("lui a0, #0x12345000") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvUtypeImm20("\x00\xF0\xFF\xFF")); // imm[31:12] bits [31:12] - - /* - * Example: AUIPC rd, imm20 - * - * Encoding: - * imm[31:12] rd opcode - * - * Mask : 0x0000007F (mask opcode) - * Value : 0x00000017 (opcode=0x17) - */ - insert( - mnem("auipc", 4, - "\x17\x00\x00\x00", // pattern 32-bit LE: 0x00000017 - "\x7F\x00\x00\x00")) // mask: opcode only - ->help("Add Upper Immediate to PC: rd = PC + (imm << 12)") - ->example("auipc a0, #0x12345000") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvUtypeImm20("\x00\xF0\xFF\xFF")); // imm[31:12] bits [31:12] - - /* J-Type Control Transfer Instructions */ - - /* - * Example: JAL rd, imm21 - * - * Encoding: - * imm[20|10:1|11|19:12] rd opcode - * - * Mask : 0x0000007F (mask opcode) - * Value : 0x0000006F (opcode=0x6F) - */ - insert( - mnem("jal", 4, - "\x6F\x00\x00\x00", // pattern 32-bit LE: 0x0000006F - "\x7F\x00\x00\x00")) // mask: opcode only - ->help("Jump and Link: rd = PC + 4; PC += imm") - ->example("jal ra, #8") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvJtypeImm21("\x00\xF0\xFF\xFF")); // imm[20:1] in bits [31:12] - - /* I-Type Control Transfer Instructions */ - - /* - * Example: JALR rd, rs1, imm12 - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00000067 (funct3=000 + opcode=0x67) - */ - insert( - mnem("jalr", 4, - "\x67\x00\x00\x00", // pattern 32-bit LE: 0x00000067 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Jump and Link Register: rd = PC + 4; PC = (rs1 + imm) & ~1") - ->example("jalr ra, a1, #0") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")); // imm[11:0] bits [31:20] - - /* B-Type Control Transfer Instructions */ - - /* - * Example: BEQ rs1, rs2, imm13 - * - * Encoding: - * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00000063 (funct3=000 + opcode=0x63) - */ - insert( - mnem("beq", 4, - "\x63\x00\x00\x00", // pattern 32-bit LE: 0x00000063 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Branch if Equal: if (rs1 == rs2) PC += imm") - ->example("beq a0, a1, #8") - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding - - /* - * Example: BNE rs1, rs2, imm13 - * - * Encoding: - * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00001063 (funct3=001 + opcode=0x63) - */ - insert( - mnem("bne", 4, - "\x63\x10\x00\x00", // pattern 32-bit LE: 0x00100063 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Branch if Not Equal: if (rs1 != rs2) PC += imm") - ->example("bne a0, a1, #8") - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding - - /* - * Example: BLT rs1, rs2, imm13 - * - * Encoding: - * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00004063 (funct3=100 + opcode=0x63) - */ - insert( - mnem("blt", 4, - "\x63\x40\x00\x00", // pattern 32-bit LE: 0x00004063 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Branch if Less Than: if (rs1 < rs2) PC += imm (signed)") - ->example("blt a0, a1, #8") - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding - - /* - * Example: BGE rs1, rs2, imm13 - * - * Encoding: - * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00005063 (funct3=101 + opcode=0x63) - */ - insert( - mnem("bge", 4, - "\x63\x50\x00\x00", // pattern 32-bit LE: 0x00005063 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Branch if Greater or Equal: if (rs1 >= rs2) PC += imm (signed)") - ->example("bge a0, a1, #8") - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding - - /* - * Example: BLTU rs1, rs2, imm13 - * - * Encoding: - * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00006063 (funct3=110 + opcode=0x63) - */ - insert( - mnem("bltu", 4, - "\x63\x60\x00\x00", // pattern 32-bit LE: 0x00006063 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Branch if Less Than Unsigned: if (rs1 < rs2) PC += imm (unsigned)") - ->example("bltu a0, a1, #8") - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding - - /* - * Example: BGEU rs1, rs2, imm13 - * - * Encoding: - * imm[12|10:5] rs2 rs1 funct3 imm[4:1|11] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00007063 (funct3=111 + opcode=0x63) - */ - insert( - mnem("bgeu", 4, - "\x63\x70\x00\x00", // pattern 32-bit LE: 0x00007063 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Branch if Greater or Equal Unsigned: if (rs1 >= rs2) PC += imm (unsigned)") - ->example("bgeu a0, a1, #8") - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvBtypeImm13("\x80\x0F\x00\xFE")); // imm[12:1] split encoding - - /* Load Instructions */ - - /* - * Example: LB rd, imm(rs1) - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00000003 (funct3=000 + opcode=0x03) - */ - insert( - mnem("lb", 4, - "\x03\x00\x00\x00", // pattern 32-bit LE: 0x00000003 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Load Byte (signed): rd = sign-extend(M[rs1 + imm][7:0])") - ->example("lb a0, (#4, a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: LH rd, imm(rs1) - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00001003 (funct3=001 + opcode=0x03) - */ - insert( - mnem("lh", 4, - "\x03\x10\x00\x00", // pattern 32-bit LE: 0x00001003 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Load Halfword (signed): rd = sign-extend(M[rs1 + imm][15:0])") - ->example("lh a0, (#4, a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: LW rd, imm(rs1) - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00002003 (funct3=010 + opcode=0x03) - */ - insert( - mnem("lw", 4, - "\x03\x20\x00\x00", // pattern 32-bit LE: 0x00002003 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Load Word: rd = M[rs1 + imm][31:0]") - ->example("lw a0, (#4, a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: LBU rd, imm(rs1) - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00004003 (funct3=100 + opcode=0x03) - */ - insert( - mnem("lbu", 4, - "\x03\x40\x00\x00", // pattern 32-bit LE: 0x00004003 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Load Byte Unsigned: rd = zero-extend(M[rs1 + imm][7:0])") - ->example("lbu a0, (#4, a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: LHU rd, imm(rs1) - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00005003 (funct3=101 + opcode=0x03) - */ - insert( - mnem("lhu", 4, - "\x03\x50\x00\x00", // pattern 32-bit LE: 0x00005003 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Load Halfword Unsigned: rd = zero-extend(M[rs1 + imm][15:0])") - ->example("lhu a0, (#4, a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0] bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* Store Instructions */ - - /* - * Example: SB rs2, imm(rs1) - * - * Encoding: - * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00000023 (funct3=000 + opcode=0x23) - */ - insert( - mnem("sb", 4, - "\x23\x00\x00\x00", // pattern 32-bit LE: 0x00000023 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Store Byte: M[rs1 + imm] = rs2[7:0]") - ->example("sb a1, (#4, a0)") - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: SH rs2, imm(rs1) - * - * Encoding: - * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00001023 (funct3=001 + opcode=0x23) - */ - insert( - mnem("sh", 4, - "\x23\x10\x00\x00", // pattern 32-bit LE: 0x00001023 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Store Halfword: M[rs1 + imm] = rs2[15:0]") - ->example("sh a1, (#4, a0)") - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: SW rs2, imm(rs1) - * - * Encoding: - * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00002023 (funct3=010 + opcode=0x23) - */ - insert( - mnem("sw", 4, - "\x23\x20\x00\x00", // pattern 32-bit LE: 0x00002023 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Store Word: M[rs1 + imm] = rs2[31:0]") - ->example("sw a1, (#4, a0)") - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* System Instructions */ - - /* Memory Ordering Instructions (RV32I Base) */ - - /* - * Example: FENCE pred, succ - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x0000000F (funct3=000 + opcode=0x0F) - * - * pred[3:0] in imm[3:0] (bits [23:20]) - * succ[3:0] in imm[7:4] (bits [27:24]) - * rs1 and rd are typically zero but can be non-zero - */ - // Simple fence (no arguments) - defaults to fence iorw, iorw (full barrier) - // Encoding: 0x0FF0000F - pred=1111, succ=1111, rs1=x0, rd=x0 - insert( - mnem("fence", 4, - "\x0F\x00\xF0\x0F", // pattern 32-bit LE: 0x0FF0000F (fence iorw, iorw) - "\xFF\xFF\xFF\xFF")) // exact match - no variable bits - ->help("Memory Ordering Fence (full barrier): fence iorw, iorw") - ->example("fence"); - - // Fence with explicit pred/succ and registers - insert( - mnem("fence", 4, - "\x0F\x00\x00\x00", // pattern 32-bit LE: 0x0000000F - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Memory Ordering Fence: orders memory operations") - ->example("fence #0xFF, zero, zero") - ->insert(new GAParameterRiscvFencePredSucc("\x00\x00\xF0\x0F")) // pred/succ in imm[7:0] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] (typically zero) - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] (typically zero) - - /* - * Example: FENCE.I - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x0000100F (funct3=001 + opcode=0x0F) - * - * All fields except funct3 and opcode are zero - */ - insert( - mnem("fence.i", 4, - "\x0F\x10\x00\x00", // pattern 32-bit LE: 0x0000100F - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Instruction Fence: synchronizes instruction and data streams") - ->example("fence.i"); - - /* Environment Call and Breakpoints */ - - /* - * Example: ECALL - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00000073 (funct3=000 + opcode=0x73) - * - * All fields except funct3 and opcode are zero - * Note: imm[0]=0, so no mask needed for byte 2 (unlike EBREAK) - */ - insert( - mnem("ecall", 4, - "\x73\x00\x00\x00", // pattern 32-bit LE: 0x00000073 - "\x7F\x70\x10\x00")) // mask: opcode + funct3 + imm[0] (bit 20 = byte 2 bit 4, must be 0) - ->help("Environment Call: makes a request to the execution environment") - ->example("ecall"); - - /* - * Example: EBREAK - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00100073 (funct3=000 + opcode=0x73 + imm[0]=1) - * - * imm[0]=1 (bit 20), all other fields except funct3 and opcode are zero - */ - insert( - mnem("ebreak", 4, - "\x73\x00\x10\x00", // pattern 32-bit LE: 0x00100073 (imm[0]=1 in bit 20) - "\x7F\x70\x10\x00")) // mask: opcode + funct3 + imm[0] (bit 20 = byte 2 bit 4) - ->help("Environment Break: causes a breakpoint exception") - ->example("ebreak"); - - /* M Extension Instructions */ - - /* - * Example: MUL rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02000033 (funct7=0x01, funct3=000 + opcode=0x33) - */ - insert( - mnem("mul", 4, - "\x33\x00\x00\x02", // pattern 32-bit LE: 0x02000033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Multiply: rd = (rs1 * rs2)[XLEN-1:0] (lower XLEN bits)") - ->example("mul a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) - - /* - * Example: MULH rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02001033 (funct7=0x01, funct3=001 + opcode=0x33) - */ - insert( - mnem("mulh", 4, - "\x33\x10\x00\x02", // pattern 32-bit LE: 0x02001033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Multiply High (signed × signed): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") - ->example("mulh a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) - - /* - * Example: MULHSU rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02002033 (funct7=0x01, funct3=010 + opcode=0x33) - */ - insert( - mnem("mulhsu", 4, - "\x33\x20\x00\x02", // pattern 32-bit LE: 0x02002033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Multiply High (signed × unsigned): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") - ->example("mulhsu a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) - - /* - * Example: MULHU rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02003033 (funct7=0x01, funct3=011 + opcode=0x33) - */ - insert( - mnem("mulhu", 4, - "\x33\x30\x00\x02", // pattern 32-bit LE: 0x02003033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Multiply High (unsigned × unsigned): rd = (rs1 * rs2)[2*XLEN-1:XLEN]") - ->example("mulhu a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) - - /* - * Example: DIV rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02004033 (funct7=0x01, funct3=100 + opcode=0x33) - */ - insert( - mnem("div", 4, - "\x33\x40\x00\x02", // pattern 32-bit LE: 0x02004033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Divide (signed): rd = rs1 / rs2") - ->example("div a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) - - /* - * Example: DIVU rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02005033 (funct7=0x01, funct3=101 + opcode=0x33) - */ - insert( - mnem("divu", 4, - "\x33\x50\x00\x02", // pattern 32-bit LE: 0x02005033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Divide (unsigned): rd = rs1 / rs2") - ->example("divu a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) - - /* - * Example: REM rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02006033 (funct7=0x01, funct3=110 + opcode=0x33) - */ - insert( - mnem("rem", 4, - "\x33\x60\x00\x02", // pattern 32-bit LE: 0x02006033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Remainder (signed): rd = rs1 % rs2") - ->example("rem a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) - - /* - * Example: REMU rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02007033 (funct7=0x01, funct3=111 + opcode=0x33) - */ - insert( - mnem("remu", 4, - "\x33\x70\x00\x02", // pattern 32-bit LE: 0x02007033 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Remainder (unsigned): rd = rs1 % rs2") - ->example("remu a0, a1, a2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - only bit 0 of byte 3 (bit 24) - - /* Atomic Memory Instructions Extension (RV32A) */ - - /* - * Example: LR.W rd, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode, rs2 must be 0) - * Value : 0x1000202F (funct5=00010, aq=0, rl=0, rs2=00000, funct3=010, opcode=0x2F) - * - * funct5[4:0] = 00010 (0x02) in bits [31:27] - * aq = 0 in bit [26] - * rl = 0 in bit [25] - * rs2 = 00000 (reserved, must be zero) in bits [24:20] - */ - insert( - mnem("lr.w", 4, - "\x2F\x20\x00\x10", // pattern 32-bit LE: 0x1000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 (aq/rl default to 0) - ->help("Load Reserved Word: rd = M[rs1]; reserve address") - ->example("lr.w a0, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: SC.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0x1800202F (funct5=00011, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("sc.w", 4, - "\x2F\x20\x00\x18", // pattern 32-bit LE: 0x1800202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Store Conditional Word: if reserved, M[rs1] = rs2, rd = 0; else rd != 0") - ->example("sc.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOSWAP.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0x0800202F (funct5=00001, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amoswap.w", 4, - "\x2F\x20\x00\x08", // pattern 32-bit LE: 0x0800202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Swap Word: temp = M[rs1]; M[rs1] = rs2; rd = temp") - ->example("amoswap.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOADD.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0x0000202F (funct5=00000, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amoadd.w", 4, - "\x2F\x20\x00\x00", // pattern 32-bit LE: 0x0000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Add Word: temp = M[rs1]; M[rs1] = temp + rs2; rd = temp") - ->example("amoadd.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOXOR.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0x2000202F (funct5=00100, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amoxor.w", 4, - "\x2F\x20\x00\x20", // pattern 32-bit LE: 0x2000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory XOR Word: temp = M[rs1]; M[rs1] = temp ^ rs2; rd = temp") - ->example("amoxor.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOAND.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0x6000202F (funct5=01100, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amoand.w", 4, - "\x2F\x20\x00\x60", // pattern 32-bit LE: 0x6000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory AND Word: temp = M[rs1]; M[rs1] = temp & rs2; rd = temp") - ->example("amoand.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOOR.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0x4000202F (funct5=01000, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amoor.w", 4, - "\x2F\x20\x00\x40", // pattern 32-bit LE: 0x4000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory OR Word: temp = M[rs1]; M[rs1] = temp | rs2; rd = temp") - ->example("amoor.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOMIN.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0x8000202F (funct5=10000, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amomin.w", 4, - "\x2F\x20\x00\x80", // pattern 32-bit LE: 0x8000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Minimum Word (signed): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp") - ->example("amomin.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOMAX.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0xA000202F (funct5=10100, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amomax.w", 4, - "\x2F\x20\x00\xA0", // pattern 32-bit LE: 0xA000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Maximum Word (signed): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp") - ->example("amomax.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOMINU.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0xC000202F (funct5=11000, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amominu.w", 4, - "\x2F\x20\x00\xC0", // pattern 32-bit LE: 0xC000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Minimum Word (unsigned): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp") - ->example("amominu.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: AMOMAXU.W rd, rs2, (rs1) - * - * Encoding: - * funct5 aq rl rs2 rs1 funct3 rd opcode - * - * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) - * Value : 0xE000202F (funct5=11100, aq=0, rl=0, funct3=010, opcode=0x2F) - */ - insert( - mnem("amomaxu.w", 4, - "\x2F\x20\x00\xE0", // pattern 32-bit LE: 0xE000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Maximum Word (unsigned): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp") - ->example("amomaxu.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* ZICSR Instructions Extension */ - - /* - * Example: CSRRW rd, csr, rs1 - * - * Encoding: - * csr[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00001073 (funct3=001 + opcode=0x73) - * - * Atomic Read/Write CSR: rd = CSR; CSR = rs1 - */ - insert( - mnem("csrrw", 4, - "\x73\x10\x00\x00", // pattern 32-bit LE: 0x00001073 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("CSR Read/Write: rd = CSR; CSR = rs1") - ->example("csrrw a0, #0x300, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: CSRRS rd, csr, rs1 - * - * Encoding: - * csr[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00002073 (funct3=010 + opcode=0x73) - * - * Atomic Read and Set Bits in CSR: rd = CSR; CSR = CSR | rs1 - */ - insert( - mnem("csrrs", 4, - "\x73\x20\x00\x00", // pattern 32-bit LE: 0x00002073 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("CSR Read and Set Bits: rd = CSR; CSR = CSR | rs1") - ->example("csrrs a0, #0x300, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: CSRRC rd, csr, rs1 - * - * Encoding: - * csr[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00003073 (funct3=011 + opcode=0x73) - * - * Atomic Read and Clear Bits in CSR: rd = CSR; CSR = CSR & ~rs1 - */ - insert( - mnem("csrrc", 4, - "\x73\x30\x00\x00", // pattern 32-bit LE: 0x00003073 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("CSR Read and Clear Bits: rd = CSR; CSR = CSR & ~rs1") - ->example("csrrc a0, #0x300, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: CSRRWI rd, csr, uimm5 - * - * Encoding: - * csr[11:0] uimm[4:0] funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00005073 (funct3=101 + opcode=0x73) - * - * Atomic Read/Write CSR Immediate: rd = CSR; CSR = uimm[4:0] - */ - insert( - mnem("csrrwi", 4, - "\x73\x50\x00\x00", // pattern 32-bit LE: 0x00005073 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("CSR Read/Write Immediate: rd = CSR; CSR = uimm[4:0]") - ->example("csrrwi a0, #0x300, #5") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] - ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] - - /* - * Example: CSRRSI rd, csr, uimm5 - * - * Encoding: - * csr[11:0] uimm[4:0] funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00006073 (funct3=110 + opcode=0x73) - * - * Atomic Read and Set Bits in CSR Immediate: rd = CSR; CSR = CSR | uimm[4:0] - */ - insert( - mnem("csrrsi", 4, - "\x73\x60\x00\x00", // pattern 32-bit LE: 0x00006073 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("CSR Read and Set Bits Immediate: rd = CSR; CSR = CSR | uimm[4:0]") - ->example("csrrsi a0, #0x300, #5") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] - ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] - - /* - * Example: CSRRCI rd, csr, uimm5 - * - * Encoding: - * csr[11:0] uimm[4:0] funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00007073 (funct3=111 + opcode=0x73) - * - * Atomic Read and Clear Bits in CSR Immediate: rd = CSR; CSR = CSR & ~uimm[4:0] - */ - insert( - mnem("csrrci", 4, - "\x73\x70\x00\x00", // pattern 32-bit LE: 0x00007073 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("CSR Read and Clear Bits Immediate: rd = CSR; CSR = CSR & ~uimm[4:0]") - ->example("csrrci a0, #0x300, #5") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvCsr12("\x00\x00\xF0\xFF")) // CSR: bits [31:20] - ->insert(new GAParameterRiscvUimm5("\x00\x80\x0F\x00")); // uimm[4:0]: bits [19:15] - - /* F Extension Instructions */ - - /* - * Example: FLW rd, imm12(rs1) - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00002007 (funct3=010 + opcode=0x07) - */ - insert( - mnem("flw", 4, - "\x07\x20\x00\x00", // pattern 32-bit LE: 0x00002007 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Floating-Point Load Word: rd = M[rs1 + imm12]") - ->example("flw f0, (#4, a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0]: bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FSW rs2, imm12(rs1) - * - * Encoding: - * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00002027 (funct3=010 + opcode=0x27) - */ - insert( - mnem("fsw", 4, - "\x27\x20\x00\x00", // pattern 32-bit LE: 0x00002027 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Floating-Point Store Word: M[rs1 + imm12] = rs2") - ->example("fsw f0, (#4, a1)") - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvStypeImm12("\x00\x00\xF0\xFE")) // imm[11:0]: split encoding - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FMADD.S rd, rs1, rs2, rs3 - * - * Encoding: - * rs3 funct2 rs2 rs1 funct3 rd opcode - * - * Mask : 0x6000707F (mask funct2 + funct3 + opcode) - * Value : 0x00000043 (funct2=00, funct3=000 + opcode=0x43) - */ - insert( - mnem("fmadd.s", 4, - "\x43\x00\x00\x00", // pattern 32-bit LE: 0x00000043 - "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 - ->help("Floating-Point Fused Multiply-Add: rd = rs1 * rs2 + rs3") - ->example("fmadd.s f0, f1, f2, f3") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] - - /* - * Example: FMSUB.S rd, rs1, rs2, rs3 - * - * Encoding: - * rs3 funct2 rs2 rs1 funct3 rd opcode - * - * Mask : 0x6000707F (mask funct2 + funct3 + opcode) - * Value : 0x00000047 (funct2=00, funct3=000 + opcode=0x47) - */ - insert( - mnem("fmsub.s", 4, - "\x47\x00\x00\x00", // pattern 32-bit LE: 0x00000047 - "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 - ->help("Floating-Point Fused Multiply-Subtract: rd = rs1 * rs2 - rs3") - ->example("fmsub.s f0, f1, f2, f3") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] - - /* - * Example: FNMSUB.S rd, rs1, rs2, rs3 - * - * Encoding: - * rs3 funct2 rs2 rs1 funct3 rd opcode - * - * Mask : 0x6000707F (mask funct2 + funct3 + opcode) - * Value : 0x0000004B (funct2=00, funct3=000 + opcode=0x4B) - */ - insert( - mnem("fnmsub.s", 4, - "\x4B\x00\x00\x00", // pattern 32-bit LE: 0x0000004B - "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 - ->help("Floating-Point Negative Fused Multiply-Subtract: rd = -(rs1 * rs2) + rs3") - ->example("fnmsub.s f0, f1, f2, f3") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] - - /* - * Example: FNMADD.S rd, rs1, rs2, rs3 - * - * Encoding: - * rs3 funct2 rs2 rs1 funct3 rd opcode - * - * Mask : 0x6000707F (mask funct2 + funct3 + opcode) - * Value : 0x0000004F (funct2=00, funct3=000 + opcode=0x4F) - */ - insert( - mnem("fnmadd.s", 4, - "\x4F\x00\x00\x00", // pattern 32-bit LE: 0x0000004F - "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 - ->help("Floating-Point Negative Fused Multiply-Add: rd = -(rs1 * rs2) - rs3") - ->example("fnmadd.s f0, f1, f2, f3") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - byte 3 bits [7:3] - - /* - * Example: FADD.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x00000053 (funct7=0x00, funct3=000 + opcode=0x53) - */ - insert( - mnem("fadd.s", 4, - "\x53\x00\x00\x00", // pattern 32-bit LE: 0x00000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Add: rd = rs1 + rs2") - ->example("fadd.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FSUB.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x08000053 (funct7=0x08, funct3=000 + opcode=0x53) - */ - insert( - mnem("fsub.s", 4, - "\x53\x00\x00\x08", // pattern 32-bit LE: 0x08000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Subtract: rd = rs1 - rs2") - ->example("fsub.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FMUL.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x10000053 (funct7=0x10, funct3=000 + opcode=0x53) - */ - insert( - mnem("fmul.s", 4, - "\x53\x00\x00\x10", // pattern 32-bit LE: 0x10000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Multiply: rd = rs1 * rs2") - ->example("fmul.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FDIV.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x18000053 (funct7=0x18, funct3=000 + opcode=0x53) - */ - insert( - mnem("fdiv.s", 4, - "\x53\x00\x00\x18", // pattern 32-bit LE: 0x18000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Divide: rd = rs1 / rs2") - ->example("fdiv.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FSQRT.S rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0x58000053 (funct7=0x2C, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fsqrt.s", 4, - "\x53\x00\x00\x58", // pattern 32-bit LE: 0x58000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Square Root: rd = sqrt(rs1)") - ->example("fsqrt.s f0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FSGNJ.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x20000053 (funct7=0x20, funct3=000 + opcode=0x53) - */ - insert( - mnem("fsgnj.s", 4, - "\x53\x00\x00\x20", // pattern 32-bit LE: 0x20000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Sign Injection: rd = {rs2[31], rs1[30:0]}") - ->example("fsgnj.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FSGNJN.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x20001053 (funct7=0x20, funct3=001 + opcode=0x53) - */ - insert( - mnem("fsgnjn.s", 4, - "\x53\x10\x00\x20", // pattern 32-bit LE: 0x20001053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Sign Injection Negative: rd = {~rs2[31], rs1[30:0]}") - ->example("fsgnjn.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FSGNJX.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x20002053 (funct7=0x20, funct3=010 + opcode=0x53) - */ - insert( - mnem("fsgnjx.s", 4, - "\x53\x20\x00\x20", // pattern 32-bit LE: 0x20002053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Sign Injection XOR: rd = {rs2[31]^rs1[31], rs1[30:0]}") - ->example("fsgnjx.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FMIN.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x28000053 (funct7=0x28, funct3=000 + opcode=0x53) - */ - insert( - mnem("fmin.s", 4, - "\x53\x00\x00\x28", // pattern 32-bit LE: 0x28000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Minimum: rd = min(rs1, rs2)") - ->example("fmin.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FMAX.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x28001053 (funct7=0x28, funct3=001 + opcode=0x53) - */ - insert( - mnem("fmax.s", 4, - "\x53\x10\x00\x28", // pattern 32-bit LE: 0x28001053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Maximum: rd = max(rs1, rs2)") - ->example("fmax.s f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FEQ.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0xA0002053 (funct7=0x50, funct3=010 + opcode=0x53) - */ - insert( - mnem("feq.s", 4, - "\x53\x20\x00\xA0", // pattern 32-bit LE: 0xA0002053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Equal Compare: rd = (rs1 == rs2) ? 1 : 0") - ->example("feq.s a0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FLT.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0xA0001053 (funct7=0x50, funct3=001 + opcode=0x53) - */ - insert( - mnem("flt.s", 4, - "\x53\x10\x00\xA0", // pattern 32-bit LE: 0xA0001053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Less Than Compare: rd = (rs1 < rs2) ? 1 : 0") - ->example("flt.s a0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FLE.S rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0xA0000053 (funct7=0x50, funct3=000 + opcode=0x53) - */ - insert( - mnem("fle.s", 4, - "\x53\x00\x00\xA0", // pattern 32-bit LE: 0xA0000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Less Than or Equal Compare: rd = (rs1 <= rs2) ? 1 : 0") - ->example("fle.s a0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - - /* - * Example: FCVT.W.S rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xC0000053 (funct7=0x60, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.w.s", 4, - "\x53\x00\x00\xC0", // pattern 32-bit LE: 0xC0000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert to Word: rd = (int32_t)rs1") - ->example("fcvt.w.s a0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCVT.WU.S rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xC0001053 (funct7=0x60, rs2=1, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.wu.s", 4, - "\x53\x10\x00\xC0", // pattern 32-bit LE: 0xC0001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert to Word Unsigned: rd = (uint32_t)rs1") - ->example("fcvt.wu.s a0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCVT.S.W rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xD0000053 (funct7=0x68, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.s.w", 4, - "\x53\x00\x00\xD0", // pattern 32-bit LE: 0xD0000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert from Word: rd = (float)rs1") - ->example("fcvt.s.w f0, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCVT.S.WU rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xD0001053 (funct7=0x68, rs2=1, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.s.wu", 4, - "\x53\x10\x00\xD0", // pattern 32-bit LE: 0xD0001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert from Word Unsigned: rd = (float)(uint32_t)rs1") - ->example("fcvt.s.wu f0, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FMV.X.W rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xE0000053 (funct7=0x70, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fmv.x.w", 4, - "\x53\x00\x00\xE0", // pattern 32-bit LE: 0xE0000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Move to Integer: rd = rs1 (bitwise copy)") - ->example("fmv.x.w a0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FMV.W.X rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xF0000053 (funct7=0x78, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fmv.w.x", 4, - "\x53\x00\x00\xF0", // pattern 32-bit LE: 0xF0000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Move from Integer: rd = rs1 (bitwise copy)") - ->example("fmv.w.x f0, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCLASS.S rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xE0001053 (funct7=0x70, rs2=1, funct3=000 + opcode=0x53) - */ - insert( - mnem("fclass.s", 4, - "\x53\x10\x00\xE0", // pattern 32-bit LE: 0xE0001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Classify: rd = classification bits for rs1") - ->example("fclass.s a0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* D Extension Instructions (Double-Precision Floating-Point) */ - - /* - * Example: FLD rd, imm12(rs1) - * - * Encoding: - * imm[11:0] rs1 funct3 rd opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00003007 (funct3=011 + opcode=0x07) - */ - insert( - mnem("fld", 4, - "\x07\x30\x00\x00", // pattern 32-bit LE: 0x00003007 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Floating-Point Load Double: rd = M[rs1 + imm12]") - ->example("fld f0, (#8, a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvImm12("\x00\x00\xF0\xFF")) // imm[11:0]: bits [31:20] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FSD rs2, imm12(rs1) - * - * Encoding: - * imm[11:5] rs2 rs1 funct3 imm[4:0] opcode - * - * Mask : 0x0000707F (mask funct3 + opcode) - * Value : 0x00003027 (funct3=011 + opcode=0x27) - */ - insert( - mnem("fsd", 4, - "\x27\x30\x00\x00", // pattern 32-bit LE: 0x00003027 - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Floating-Point Store Double: M[rs1 + imm12] = rs2") - ->example("fsd f0, (#8, a1)") - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvStypeImm12("\x00\x00\xF0\xFE")) // imm[11:0]: split encoding - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FMADD.D rd, rs1, rs2, rs3 - * - * Encoding: - * rs3 funct2 rs2 rs1 funct3 rd opcode - * - * Mask : 0x6000707F (mask funct2 + funct3 + opcode) - * Value : 0x04000043 (funct2=01, funct3=000 + opcode=0x43) - */ - insert( - mnem("fmadd.d", 4, - "\x43\x00\x00\x04", // pattern 32-bit LE: 0x04000043 - "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 - ->help("Floating-Point Fused Multiply-Add Double: rd = rs1 * rs2 + rs3") - ->example("fmadd.d f0, f1, f2, f3") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - - /* - * Example: FMSUB.D rd, rs1, rs2, rs3 - * - * Encoding: - * rs3 funct2 rs2 rs1 funct3 rd opcode - * - * Mask : 0x6000707F (mask funct2 + funct3 + opcode) - * Value : 0x04000047 (funct2=01, funct3=000 + opcode=0x47) - */ - insert( - mnem("fmsub.d", 4, - "\x47\x00\x00\x04", // pattern 32-bit LE: 0x04000047 - "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 - ->help("Floating-Point Fused Multiply-Subtract Double: rd = rs1 * rs2 - rs3") - ->example("fmsub.d f0, f1, f2, f3") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - - /* - * Example: FNMSUB.D rd, rs1, rs2, rs3 - * - * Encoding: - * rs3 funct2 rs2 rs1 funct3 rd opcode - * - * Mask : 0x6000707F (mask funct2 + funct3 + opcode) - * Value : 0x0400004B (funct2=01, funct3=000 + opcode=0x4B) - */ - insert( - mnem("fnmsub.d", 4, - "\x4B\x00\x00\x04", // pattern 32-bit LE: 0x0400004B - "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 - ->help("Floating-Point Negative Fused Multiply-Subtract Double: rd = -(rs1 * rs2) + rs3") - ->example("fnmsub.d f0, f1, f2, f3") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - - /* - * Example: FNMADD.D rd, rs1, rs2, rs3 - * - * Encoding: - * rs3 funct2 rs2 rs1 funct3 rd opcode - * - * Mask : 0x6000707F (mask funct2 + funct3 + opcode) - * Value : 0x0400004F (funct2=01, funct3=000 + opcode=0x4F) - */ - insert( - mnem("fnmadd.d", 4, - "\x4F\x00\x00\x04", // pattern 32-bit LE: 0x0400004F - "\x7F\x70\x00\x06")) // mask: opcode + funct3 + funct2 - ->help("Floating-Point Negative Fused Multiply-Add Double: rd = -(rs1 * rs2) - rs3") - ->example("fnmadd.d f0, f1, f2, f3") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->insert(new GAParameterRiscvReg("\x00\x00\x00\xF8")); // RS3: bits [31:27] - - /* - * Example: FADD.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x02000053 (funct7=0x01, funct3=000 + opcode=0x53) - */ - insert( - mnem("fadd.d", 4, - "\x53\x00\x00\x02", // pattern 32-bit LE: 0x02000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Add Double: rd = rs1 + rs2") - ->example("fadd.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FSUB.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x0A000053 (funct7=0x05, funct3=000 + opcode=0x53) - */ - insert( - mnem("fsub.d", 4, - "\x53\x00\x00\x0A", // pattern 32-bit LE: 0x0A000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Subtract Double: rd = rs1 - rs2") - ->example("fsub.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FMUL.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x12000053 (funct7=0x09, funct3=000 + opcode=0x53) - */ - insert( - mnem("fmul.d", 4, - "\x53\x00\x00\x12", // pattern 32-bit LE: 0x12000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Multiply Double: rd = rs1 * rs2") - ->example("fmul.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FDIV.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x1A000053 (funct7=0x0D, funct3=000 + opcode=0x53) - */ - insert( - mnem("fdiv.d", 4, - "\x53\x00\x00\x1A", // pattern 32-bit LE: 0x1A000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Divide Double: rd = rs1 / rs2") - ->example("fdiv.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FSQRT.D rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0x5A000053 (funct7=0x2D, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fsqrt.d", 4, - "\x53\x00\x00\x5A", // pattern 32-bit LE: 0x5A000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Square Root Double: rd = sqrt(rs1)") - ->example("fsqrt.d f0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FSGNJ.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x22000053 (funct7=0x11, funct3=000 + opcode=0x53) - */ - insert( - mnem("fsgnj.d", 4, - "\x53\x00\x00\x22", // pattern 32-bit LE: 0x22000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Sign Injection Double: rd = {rs2[63], rs1[62:0]}") - ->example("fsgnj.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FSGNJN.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x22001053 (funct7=0x11, funct3=001 + opcode=0x53) - */ - insert( - mnem("fsgnjn.d", 4, - "\x53\x10\x00\x22", // pattern 32-bit LE: 0x22001053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Sign Injection Negative Double: rd = {~rs2[63], rs1[62:0]}") - ->example("fsgnjn.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FSGNJX.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x22002053 (funct7=0x11, funct3=010 + opcode=0x53) - */ - insert( - mnem("fsgnjx.d", 4, - "\x53\x20\x00\x22", // pattern 32-bit LE: 0x22002053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Sign Injection XOR Double: rd = {rs2[63]^rs1[63], rs1[62:0]}") - ->example("fsgnjx.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FMIN.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x2A000053 (funct7=0x15, funct3=000 + opcode=0x53) - */ - insert( - mnem("fmin.d", 4, - "\x53\x00\x00\x2A", // pattern 32-bit LE: 0x2A000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Minimum Double: rd = min(rs1, rs2)") - ->example("fmin.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FMAX.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0x2A001053 (funct7=0x15, funct3=001 + opcode=0x53) - */ - insert( - mnem("fmax.d", 4, - "\x53\x10\x00\x2A", // pattern 32-bit LE: 0x2A001053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Maximum Double: rd = max(rs1, rs2)") - ->example("fmax.d f0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FCVT.S.D rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0x40000053 (funct7=0x20, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.s.d", 4, - "\x53\x00\x00\x40", // pattern 32-bit LE: 0x40000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert Single from Double: rd = (float)rs1") - ->example("fcvt.s.d f0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCVT.D.S rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0x42000053 (funct7=0x21, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.d.s", 4, - "\x53\x00\x00\x42", // pattern 32-bit LE: 0x42000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert Double from Single: rd = (double)rs1") - ->example("fcvt.d.s f0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FEQ.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0xA2002053 (funct7=0x51, funct3=010 + opcode=0x53) - */ - insert( - mnem("feq.d", 4, - "\x53\x20\x00\xA2", // pattern 32-bit LE: 0xA2002053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Equal Compare Double: rd = (rs1 == rs2) ? 1 : 0") - ->example("feq.d a0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FLT.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0xA2001053 (funct7=0x51, funct3=001 + opcode=0x53) - */ - insert( - mnem("flt.d", 4, - "\x53\x10\x00\xA2", // pattern 32-bit LE: 0xA2001053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Less Than Compare Double: rd = (rs1 < rs2) ? 1 : 0") - ->example("flt.d a0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FLE.D rd, rs1, rs2 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFE00707F (mask funct7 + funct3 + opcode) - * Value : 0xA2000053 (funct7=0x51, funct3=000 + opcode=0x53) - */ - insert( - mnem("fle.d", 4, - "\x53\x00\x00\xA2", // pattern 32-bit LE: 0xA2000053 - "\x7F\x70\x00\xFE")) // mask: opcode + funct3 + funct7 - ->help("Floating-Point Less Than or Equal Compare Double: rd = (rs1 <= rs2) ? 1 : 0") - ->example("fle.d a0, f1, f2") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] - - /* - * Example: FCVT.W.D rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xC2000053 (funct7=0x61, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.w.d", 4, - "\x53\x00\x00\xC2", // pattern 32-bit LE: 0xC2000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert to Word from Double: rd = (int32_t)rs1") - ->example("fcvt.w.d a0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCVT.WU.D rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xC2001053 (funct7=0x61, rs2=1, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.wu.d", 4, - "\x53\x10\x00\xC2", // pattern 32-bit LE: 0xC2001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert to Word Unsigned from Double: rd = (uint32_t)rs1") - ->example("fcvt.wu.d a0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCVT.D.W rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xD2000053 (funct7=0x69, rs2=0, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.d.w", 4, - "\x53\x00\x00\xD2", // pattern 32-bit LE: 0xD2000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert from Word to Double: rd = (double)rs1") - ->example("fcvt.d.w f0, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCVT.D.WU rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xD2001053 (funct7=0x69, rs2=1, funct3=000 + opcode=0x53) - */ - insert( - mnem("fcvt.d.wu", 4, - "\x53\x10\x00\xD2", // pattern 32-bit LE: 0xD2001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Convert from Word Unsigned to Double: rd = (double)(uint32_t)rs1") - ->example("fcvt.d.wu f0, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* - * Example: FCLASS.D rd, rs1 - * - * Encoding: - * funct7 rs2 rs1 funct3 rd opcode - * - * Mask : 0xFFF0707F (mask funct7 + funct3 + opcode + rs2) - * Value : 0xE2001053 (funct7=0x71, rs2=1, funct3=000 + opcode=0x53) - */ - insert( - mnem("fclass.d", 4, - "\x53\x10\x00\xE2", // pattern 32-bit LE: 0xE2001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 - ->help("Floating-Point Classify Double: rd = classification bits for rs1") - ->example("fclass.d a0, f1") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] - - /* C-Extension - Compressed Instructions (16-bit) */ - - // Quadrant 0 (opcode [1:0] = 00) - - /* - * C.ADDI4SPN - Add Immediate to Stack Pointer (4-byte aligned) - * Format: CIW - * Encoding: 000|imm[9:2]|rd'[4:2]|00 - * Opcode: 0x00 (bits [1:0] = 00, bits [15:13] = 000) - */ - insert( - mnem("c.addi4spn", 2, - "\x00\x00", // pattern 16-bit LE: bits [1:0]=00, [15:13]=000 - "\x03\xE0")) // mask: opcode bits - ->help("Compressed Add Immediate to SP: rd' = sp + (uimm << 2)") - ->example("c.addi4spn a0, #16") - ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rd': bits [4:2] in byte 0 - ->insert(new GAParameterRiscvCIWimm9("\xE0\x1F")); // imm[9:2]: bits [7:5] in byte 0, bits [4:0] in byte 1 = instruction bits [12:5] - - /* - * C.LW - Compressed Load Word - * Format: CL - * Encoding: 010|imm[5|4:3|8:6]|rs1'[2:0]|imm[2|6]|rd'[2:0]|00 - * Opcode: 0x4000 (bits [1:0] = 00, bits [15:13] = 010) - */ - insert( - mnem("c.lw", 2, - "\x00\x40", // pattern 16-bit LE: bits [1:0]=00, [15:13]=010 - "\x03\xE0")) // mask: opcode bits - ->help("Compressed Load Word: rd' = M[rs1' + (uimm << 2)][31:0]") - ->example("c.lw a0, (#4, a1)") - ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rd': bits [4:2] in byte 0 - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvCLimm5("\x60\x1C")) // imm[6:2]: imm[6] in bit 5, imm[2] in bit 6, imm[5:3] in bits [12:10] - ->insert(new GAParameterRiscvCompReg("\x80\x03")); // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - - /* - * C.SW - Compressed Store Word - * Format: CS - * Encoding: 110|imm[5|4:3|8:6]|rs1'[2:0]|imm[2|6]|rs2'[2:0]|00 - * Opcode: 0xC000 (bits [1:0] = 00, bits [15:13] = 110) - */ - insert( - mnem("c.sw", 2, - "\x00\xC0", // pattern 16-bit LE: bits [1:0]=00, [15:13]=110 - "\x03\xE0")) // mask: opcode bits - ->help("Compressed Store Word: M[rs1' + (uimm << 2)] = rs2'[31:0]") - ->example("c.sw a0, (#4, a1)") - ->insert(new GAParameterRiscvCompReg("\x1C\x00")) // rs2': bits [4:2] in byte 0 - ->group('(') // imm(rs1) group - ->insert(new GAParameterRiscvCSimm5("\x60\x1C")) // imm[6:2]: imm[6] in bit 5, imm[2] in bit 6, imm[5:3] in bits [12:10] - ->insert(new GAParameterRiscvCompReg("\x80\x03")); // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - - // Quadrant 1 (opcode [1:0] = 01) - - /* - * C.NOP - Compressed No Operation / C.ADDI - * Format: CI - * Encoding: 000|imm[5:0]|rd[4:0]|01 - * Opcode: 0x0001 (bits [1:0] = 01, bits [15:13] = 000, rd=0 for NOP) - * Note: Inserted before c.addi so it's checked first (more specific pattern with rd=0) - */ - insert( - mnem("c.nop", 2, - "\x01\x00", // pattern 16-bit LE: bits [1:0]=01, [15:13]=000, rd=0 - "\x83\xEF")) // mask: opcode + rd (byte0: bits [7] and [1:0]=0x83, byte1: bits [15:13] and [11:8]=0xEF) - ->help("Compressed No Operation") - ->example("c.nop"); - - /* - * C.ADDI - Compressed Add Immediate - * Format: CI - * Encoding: 000|imm[5:0]|rd[4:0]|01 - * Opcode: 0x0001 (bits [1:0] = 01, bits [15:13] = 000, rd != 0) - * Note: Uses rejectWhenZero to check rd != 0, eliminating collision with c.nop - */ - insert( - mnem("c.addi", 2, - "\x01\x00", // pattern 16-bit LE: bits [1:0]=01, [15:13]=000 - "\x03\xE0")) // mask: opcode bits only - ->rejectWhenZero("\x80\x0F") // rd (bits [11:7]) must be non-zero - ->help("Compressed Add Immediate: rd = rd + imm") - ->example("c.addi a0, #5") - ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 - ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 - - /* - * C.LI - Compressed Load Immediate - * Format: CI - * Encoding: 010|imm[5:0]|rd[4:0]|01 - * Opcode: 0x4001 (bits [1:0] = 01, bits [15:13] = 010) - */ - insert( - mnem("c.li", 2, - "\x01\x40", // pattern 16-bit LE: bits [1:0]=01, [15:13]=010 - "\x03\xE0")) // mask: opcode bits - ->help("Compressed Load Immediate: rd = imm (rd != 0, rd != 2)") - ->example("c.li a0, #5") - ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 - ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 - - /* - * C.ADDI16SP - Compressed Add Immediate to SP (16-byte aligned) - * Format: CI - * Encoding: 011|imm[9|4|6|8:7|5]|01010|01 - * Opcode: 0x6101 (bits [1:0] = 01, bits [15:13] = 011, rd = 2 (sp)) - * Note: Pattern includes rd=2 (bits [11:7]=00010) to distinguish from c.lui - * rd[4:1]=0001 in bits [11:8], rd[0]=0 in bit [7] - * Inserted before c.lui so it's checked first (more specific pattern) - */ - insert( - mnem("c.addi16sp", 2, - "\x01\x61", // pattern 16-bit LE: bits [1:0]=01, [15:13]=011, rd=2 (bits [11:8]=0001, bit [7]=0) - "\x83\xEF")) // mask: opcode + rd (byte0: bits [7] and [1:0]=0x83, byte1: bits [15:13] and [11:8]=0xEF) - ->help("Compressed Add Immediate to SP: sp = sp + (imm << 4)") - ->example("c.addi16sp #-32") - ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[9|4|6|8:7|5]: split encoding (special format) - same mask as CI but different encoding logic - - /* - * C.LUI - Compressed Load Upper Immediate - * Format: CI - * Encoding: 011|imm[17:12]|rd[4:0]|01 - * Opcode: 0x6001 (bits [1:0] = 01, bits [15:13] = 011, rd != 0, rd != 2) - * Note: Inserted after c.addi16sp so c.addi16sp (more specific) is checked first - */ - insert( - mnem("c.lui", 2, - "\x01\x60", // pattern 16-bit LE: bits [1:0]=01, [15:13]=011 (rd != 0 and != 2 is checked in parameter decode to distinguish from c.addi16sp) - "\x03\xE0")) // mask: opcode only (rd != 0 and != 2 is checked in parameter decode to distinguish from c.addi16sp) - ->help("Compressed Load Upper Immediate: rd = (imm << 12)") - ->example("c.lui a0, #0x10000") - ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 (must be != 0 and != 2) - ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[17:12]: encoded in imm[5:0] position - same mask as CI but represents imm[17:12] - - /* - * C.SRAI - Compressed Shift Right Arithmetic Immediate - * Format: CB - * Encoding: 100|imm[5:0]|rd'[2:0]|01 - * Opcode: 0x8401 (bits [1:0] = 01, bits [15:13] = 100, bits [11:10] = 01) - * Note: C.SRAI is in quadrant 01, distinct from C.MV which is in quadrant 10 - */ - { - auto m = mnem("c.srai", 2, - "\x01\x84", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=01 (only fixed opcode bits) - "\x03\xEC"); // mask: bits [1:0] + [15:13] + [11:10] = 0x03 in byte 0, 0xEC in byte 1 (exclude bit [6] and [12] - they're data!) - m->help("Compressed Shift Right Arithmetic Immediate: rd' = rd' >> uimm (arithmetic)"); - m->example("c.srai a0, #3"); - m->insert(new GAParameterRiscvCompReg("\x80\x03")); // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - m->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 - insert(m); - } - - // Quadrant 2 (opcode [1:0] = 10) - - /* - * C.EBREAK - Compressed Environment Break - * Format: CR - * Encoding: 100|00000|00000|10 - * Opcode: 0x9002 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 001, rd=0, rs1=0) - * Note: Inserted first to ensure it's checked first (has most specific mask 0xFFFF) - */ - insert( - mnem("c.ebreak", 2, - "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=001, rd=0, rs1=0 - "\xFF\xFF")) // mask: all bits (0xFFFF) - c.ebreak is an exact encoding with rd=0, rs2=0 - // Removed priority - full mask 0xFFFF ensures c.ebreak matches only its exact encoding 0x9002 - ->help("Compressed Environment Break"); - - /* - * C.ANDI - Compressed AND Immediate - * Format: CB - * Encoding: 100|imm[5]|10|rd'[2:0]|imm[4:0]|01 - * Opcode: 0x8801 (bits [1:0] = 01, bits [15:13] = 100, bits [11:10] = 10) - * Note: bits [12] and [6:2] are part of immediate data, so they are NOT in the mask - */ - // Using standard mnemonic - c.andi is in quadrant 01 (bits[1:0]=01), - // distinct from c.jr/c.jalr which are in quadrant 10 (bits[1:0]=10) - // The mask already distinguishes them by checking bits[1:0] and bits[11:10]=10 - insert( - mnem("c.andi", 2, - "\x01\x88", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=10 - "\x03\xEC")) // mask: bits [1:0] in byte 0, bits [15:13] + [11:10] in byte 1 - ->help("Compressed AND Immediate: rd' = rd' & imm") - ->example("c.andi a0, #7") - ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - ->insert(new GAParameterRiscvCBimm6Andi("\x7C\x10")); // imm[5:0]: split encoding - bits [6:2] from byte 0, bit [12] from byte 1 - - /* - * C.SRLI - Compressed Shift Right Logical Immediate - * Format: CB - * Encoding: 100|imm[5]|00|rd'[2:0]|imm[4:0]|01 - * Opcode: bits [1:0] = 01 (quadrant 1), bits [15:13] = 100, bits [11:10] = 00 - * Note: bit [12] is imm[5], bits [6:2] are imm[4:0] (parameters) - * Pattern: 0x8001 (bits [1:0]=01, [15:13]=100, [11:10]=00) - */ - // Using standard mnemonic - c.srli is in quadrant 01 (bits[1:0]=01), - // distinct from c.jr/c.jalr/c.mv which are in quadrant 10 (bits[1:0]=10) - // The mask checks bits[11:10]=00 to distinguish from c.srai (01) and c.andi (10) - insert( - mnem("c.srli", 2, - "\x01\x80", // pattern 16-bit LE: bits [1:0]=01, [15:13]=100, [11:10]=00 - "\x03\xEC")) // mask: bits [1:0] in byte 0, bits [15:13] + [11:10] in byte 1 - ->help("Compressed Shift Right Logical Immediate: rd' = rd' >> uimm") - ->example("c.srli a0, #3") - ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - ->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 - - /* - * C.JR - Compressed Jump Register - * Format: CR - * Encoding: 100|rs1[4:0]|00000|10 - * Opcode: bits [15:13] = 100, bits [12:10] = 000, bits [6:2] = 00000 (rd=0), bits [1:0] = 10 - * Note: [11:10] are part of rs1 register field, not opcode bits, so mask doesn't check them - * Note: rs1 must be non-zero (rs1=0 with rd=0 is reserved) - */ - insert( - mnem("c.jr", 2, - "\x02\x80", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12]=0 (funct4), [6:2]=00000 (rs2=0) - "\x7F\xF0")) // mask: bits [1:0] + [6:2] in byte 0 (0x7F), bits [15:12] in byte 1 (0xF0) - ->rejectWhenZero("\x80\x0F") // rs1 (bits [11:7]) must be non-zero - ->help("Compressed Jump Register: pc = rs1") - ->example("c.jr a0") - ->insert(new GAParameterRiscvReg("\x80\x0F")); // rs1: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 - - /* - * C.JALR - Compressed Jump and Link Register - * Format: CR - * Encoding: 1001|rs1[4:0]|00000|10 - * Opcode: bits [15:12] = 1001 (funct4), bits [6:2] = 00000 (rs2=0), bits [1:0] = 10 - * Note: rd is implicitly ra (x1), rs1 must be non-zero (rs1=0 with rs2=0 is c.ebreak) - */ - insert( - mnem("c.jalr", 2, - "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1001 (funct4), [6:2]=00000 (rs2=0) - "\x7F\xF0")) // mask: bits [6:0] in byte 0 (check rs2=0, op=10), bits [15:12] in byte 1 (check funct4) - ->rejectWhenZero("\x80\x0F") // rs1 (bits [11:7]) must be non-zero - ->help("Compressed Jump and Link Register: ra = pc + 2; pc = rs1") - ->example("c.jalr a0") - ->insert(new GAParameterRiscvReg("\x80\x0F")); // rs1: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 - - /* - * C.SUB - Compressed Subtract - * Format: CA - * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|00|10 - * Opcode: 0x8C02 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 00) - */ - insert( - mnem("c.sub", 2, - "\x02\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=00 - "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 - // Removed priority - mask correctly checks [6:5]=00 to distinguish from other CA format instructions - ->help("Compressed Subtract: rd' = rd' - rs2'") - ->example("c.sub a0, a1") - ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 - - /* - * C.XOR - Compressed XOR - * Format: CA - * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|01|10 - * Opcode: 0x8C22 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 01) - */ - insert( - mnem("c.xor", 2, - "\x22\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=01 - "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 - // Removed priority - mask correctly checks [6:5]=01 to distinguish from other CA format instructions - ->help("Compressed XOR: rd' = rd' ^ rs2'") - ->example("c.xor a0, a1") - ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 - - /* - * C.OR - Compressed OR - * Format: CA - * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|10|10 - * Opcode: 0x8C42 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 10) - */ - insert( - mnem("c.or", 2, - "\x42\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=10 - "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 - // Removed priority - mask correctly checks [6:5]=10 to distinguish from other CA format instructions - ->help("Compressed OR: rd' = rd' | rs2'") - ->example("c.or a0, a1") - ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 - - /* - * C.AND - Compressed AND - * Format: CA - * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|11|10 - * Opcode: 0x8C62 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 11) - */ - insert( - mnem("c.and", 2, - "\x62\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=11 - "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 - // Removed priority - mask correctly checks [6:5]=11 to distinguish from other CA format instructions - ->help("Compressed AND: rd' = rd' & rs2'") - ->example("c.and a0, a1") - ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - ->insert(new GAParameterRiscvCompReg("\x1C\x00")); // rs2': bits [4:2] in byte 0 - - /* - * C.J - Compressed Jump - * Format: CJ - * Encoding: 101|imm[11|4|9:8|10|6|7|3:1|5]|01 - * Opcode: 0xA001 (bits [1:0] = 01, bits [15:13] = 101) - */ - insert( - mnem("c.j", 2, - "\x01\xA0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=101 - "\x03\xE0")) // mask: opcode bits - ->help("Compressed Jump: pc = pc + imm") - ->example("c.j #8") - ->insert(new GAParameterRiscvCJimm12("\xFC\x1F")); // imm[11:1]: split encoding - bits [7:2] from byte 0, bits [12:8] from byte 1 - - /* - * C.BEQZ - Compressed Branch if Equal to Zero - * Format: CB - * Encoding: 110|imm[8|4:3|7:6|2:1|5]|rs1'[2:0]|01 - * Opcode: 0xC001 (bits [1:0] = 01, bits [15:13] = 110) - * Note: bits [9:7] contain rs1' (compressed register), not regular rs2 - * Note: Distinguished from c.swsp by op field: c.beqz has [1:0]=01, c.swsp has [1:0]=10 - */ - insert( - mnem("c.beqz", 2, - "\x01\xC0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=110 - "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 - ->help("Compressed Branch if Equal to Zero: if (rs1' == 0) pc = pc + imm") - ->example("c.beqz a0, #8") - ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - ->insert(new GAParameterRiscvCBimm9("\x7C\x1C")); // imm[8:1]: split encoding - bits [6:2] from byte 0, bits [12] and [11:10] from byte 1 - - /* - * C.BNEZ - Compressed Branch if Not Equal to Zero - * Format: CB - * Encoding: 111|imm[8|4:3|7:6|2:1|5]|rs1'[2:0]|01 - * Opcode: 0xE001 (bits [1:0] = 01, bits [15:13] = 111) - */ - insert( - mnem("c.bnez", 2, - "\x01\xE0", // pattern 16-bit LE: bits [1:0]=01, [15:13]=111 - "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 - ->help("Compressed Branch if Not Equal to Zero: if (rs1' != 0) pc = pc + imm") - ->example("c.bnez a0, #8") - ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rs1': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 - ->insert(new GAParameterRiscvCBimm9("\x7C\x1C")); // imm[8:1]: split encoding - bits [6:2] from byte 0, bits [12] and [11:10] from byte 1 - - // Quadrant 2 special instructions (rd != 0) - - /* - * C.SLLI - Compressed Shift Left Logical Immediate - * Format: CI - * Encoding: 000|imm[5:0]|rd[4:0]|10 - * Opcode: 0x0002 (bits [1:0] = 10, bits [15:13] = 000, rd != 0) - */ - insert( - mnem("c.slli", 2, - "\x02\x00", // pattern 16-bit LE: bits [1:0]=10, [15:13]=000 - "\x03\xE0")) // mask: opcode bits - ->help("Compressed Shift Left Logical Immediate: rd = rd << uimm") - ->example("c.slli a0, #3") - ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 - ->insert(new GAParameterRiscvCIUimm6("\x7C\x10")); // imm[5:0]: split encoding (unsigned) - bits [6:2] from byte 0, bit [12] from byte 1 - - /* - * C.LWSP - Compressed Load Word from Stack Pointer - * Format: CI - * Encoding: 010|imm[7:2]|rd[4:0]|10 - * Opcode: 0x4002 (bits [1:0] = 10, bits [15:13] = 010, rd != 0) - */ - insert( - mnem("c.lwsp", 2, - "\x02\x40", // pattern 16-bit LE: bits [1:0]=10, [15:13]=010 - "\x03\xE0")) // mask: opcode bits - ->help("Compressed Load Word from SP: rd = M[sp + (uimm << 2)][31:0]") - ->example("c.lwsp a0, #4") - ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 - ->insert(new GAParameterRiscvCIimm7("\x7C\x10")); // imm[7:2]: imm[5] in bit [12], imm[4:2] in bits [6:4], imm[7:6] in bits [3:2] - - /* - * C.MV - Compressed Move - * Format: CR - * Encoding: 1000|rs2[4:0]|rd[4:0]|10 - * Opcode: funct4 = 1000, so bits [15:12] = 1000, bits [1:0] = 10 - * Note: bit [12] = 0 distinguishes from c.add (funct4 = 1001, bit [12] = 1) - * Note: C.MV is in quadrant 10, distinct from C.SRAI which is in quadrant 01 - * Note: both rd != 0 and rs2 != 0 required (rs2=0 would be c.jr, rd=0 invalid) - */ - insert( - mnem("c.mv", 2, - "\x02\x80", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1000 (funct4) - "\x03\xF0")) // mask: bits [1:0] + [15:12] = 0x03 in byte 0, 0xF0 in byte 1 - ->rejectWhenZero("\x80\x0F") // rd (bits [11:7]) must be non-zero - ->rejectWhenZero("\x7C\x00") // rs2 (bits [6:2]) must be non-zero - ->help("Compressed Move: rd = rs2") - ->example("c.mv a0, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 - ->insert(new GAParameterRiscvReg("\x7C\x00")); // rs2: bits [6:2] - bits [6:2] in byte 0 - - /* - * C.ADD - Compressed Add - * Format: CR - * Encoding: 100|rs2[4:0]/rs1[4:0]|rd[4:0]|10 - * Opcode: 0x9002 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 000, rd != 0, rd != 1) - */ - insert( - mnem("c.add", 2, - "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1001 (funct4), rd=0 (template) - "\x03\xF0")) // mask: bits [1:0] + [15:12] = 0x03 in byte 0, 0xF0 in byte 1 (don't check rd or rs2) - // Removed priority - c.ebreak (inserted before this) has more specific mask (0x03FF) and will match first - ->help("Compressed Add: rd = rd + rs2") - ->example("c.add a0, a1") - ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 - ->insert(new GAParameterRiscvReg("\x7C\x00")); // rs2: bits [6:2] - bits [6:2] in byte 0 - - /* - * C.SWSP - Compressed Store Word to Stack Pointer - * Format: CSS - * Encoding: 110|imm[7:2]|rs2[4:0]|10 - * Opcode: 0xC002 (bits [1:0] = 10, bits [15:13] = 110) - * Note: bits [6:2] contain regular rs2 register, not compressed rs1' - * Note: Distinguished from c.beqz by op field: c.swsp has [1:0]=10, c.beqz has [1:0]=01 - */ - insert( - mnem("c.swsp", 2, - "\x02\xC0", // pattern 16-bit LE: bits [1:0]=10, [15:13]=110 - "\x03\xE0")) // mask: bits [1:0] + [15:13] = 0x03 in byte 0, 0xE0 in byte 1 - ->help("Compressed Store Word to SP: M[sp + (uimm << 2)] = rs2[31:0]") - ->example("c.swsp a0, #4") - ->insert(new GAParameterRiscvReg("\x7C\x00")) // rs2: bits [6:2] - bits [6:2] in byte 0 - ->insert(new GAParameterRiscvCSSimm7("\x80\x1F")); // imm[7:2]: bits [12:7] - bit [7] from byte 0, bits [12:8] from byte 1 -} - -/* RISC-V Parameter Types */ - -// RISC-V Reg Parameter - -GAParameterRiscvReg::GAParameterRiscvReg(const char* mask){ - setMask(mask); -} - -int GAParameterRiscvReg::match(GAParserOperand *op, int len){ - if(op->prefix!=this->prefix) - return 0; - - // Check if it is a valid RISC-V register name. - QString name = op->value; - if(name == "zero" || name == "ra" || name == "sp" || name == "gp" || name == "tp" || - name == "t0" || name == "t1" || name == "t2" || - name == "s0" || name == "s1" || - name == "a0" || name == "a1" || name == "a2" || name == "a3" || - name == "a4" || name == "a5" || name == "a6" || name == "a7" || - name == "s2" || name == "s3" || name == "s4" || name == "s5" || - name == "s6" || name == "s7" || name == "s8" || name == "s9" || - name == "s10" || name == "s11" || - name == "t3" || name == "t4" || name == "t5" || name == "t6" || - // Floating point registers f0-f31 - name == "f0" || name == "f1" || name == "f2" || name == "f3" || - name == "f4" || name == "f5" || name == "f6" || name == "f7" || - name == "f8" || name == "f9" || name == "f10" || name == "f11" || - name == "f12" || name == "f13" || name == "f14" || name == "f15" || - name == "f16" || name == "f17" || name == "f18" || name == "f19" || - name == "f20" || name == "f21" || name == "f22" || name == "f23" || - name == "f24" || name == "f25" || name == "f26" || name == "f27" || - name == "f28" || name == "f29" || name == "f30" || name == "f31") { - return 1; - } - return 0; -} - -QString GAParameterRiscvReg::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t regnum = rawdecode(lang, adr, bytes, inslen); - // Clamp register number to valid range (0-31 for both integer and floating point) - if(regnum > 31) { - return QString::asprintf("r%llu", (unsigned long long) regnum); - } - - // Check if this is a C-Extension instruction (16-bit, mask "\x80\x0F" for bits [11:7]) - // For 16-bit instructions, mask is 2 bytes; for 32-bit, it's 4 bytes - bool isCExtension = (inslen == 2 && (unsigned char)mask[0] == 0x80 && (unsigned char)mask[1] == 0x0F); - - // Determine which register field this is by checking the mask - // For 32-bit instructions: - // RD: bits [11:7] - mask "\x80\x0F\x00\x00" - // RS1: bits [19:15] - mask "\x00\x80\x0F\x00" - // RS2: bits [24:20] - mask "\x00\x00\xF0\x01" or "\x00\x00\xF0\x1F" - // RS3: bits [31:27] - mask "\x00\x00\x00\xF8" - // For 16-bit C-Extension: - // RD/RS1/RS2: bits [11:7] - mask "\x80\x0F" - bool isRD = false; - bool isRS1 = false; - bool isRS2 = false; - bool isRS3 = false; - - if(isCExtension) { - // For C-Extension, bits [11:7] can be RD, RS1, or RS2 depending on instruction - // We can't determine from mask alone, so assume it's RD (most common) - isRD = true; - } else { - isRD = ((unsigned char)mask[0] == 0x80 && (unsigned char)mask[1] == 0x0F && (unsigned char)mask[2] == 0x00 && (unsigned char)mask[3] == 0x00); - isRS1 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x80 && (unsigned char)mask[2] == 0x0F && (unsigned char)mask[3] == 0x00); - isRS2 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x00 && ((unsigned char)mask[2] == 0xF0) && ((unsigned char)mask[3] == 0x01 || (unsigned char)mask[3] == 0x1F)); - isRS3 = ((unsigned char)mask[0] == 0x00 && (unsigned char)mask[1] == 0x00 && (unsigned char)mask[2] == 0x00 && (unsigned char)mask[3] == 0xF8); - } - - // Check instruction encoding to determine register type for F extension instructions - bool useFPReg = false; - if(inslen >= 4) { - uint8_t opcode = bytes[0] & 0x7F; // Opcode is in bits [6:0] of first byte - - if(opcode == 0x07 || opcode == 0x27) { - // FLW, FSW: rd/rs2 are FP, rs1 is integer (base address) - useFPReg = (isRD || isRS2); - } else if(opcode == 0x43 || opcode == 0x47 || opcode == 0x4B || opcode == 0x4F) { - // FMADD/FMSUB/FNMSUB/FNMADD: all registers are FP - useFPReg = true; - } else if(opcode == 0x53) { - // F extension arithmetic/comparison/conversion instructions - // Extract funct7 from byte 3 (bits [31:25] = byte 3 bits [7:1]) - // funct7 is 7 bits, so we shift right by 1 and mask with 0x7F - uint8_t funct7 = (bytes[3] >> 1) & 0x7F; - uint8_t funct3 = (bytes[1] >> 4) & 0x07; // funct3 is in bits [14:12] = byte 1 bits [6:4] - - if(funct7 == 0x60) { // fcvt.w.s, fcvt.wu.s - useFPReg = isRS1; // rs1 is FP, rd is integer - } else if(funct7 == 0x68) { // fcvt.s.w, fcvt.s.wu - useFPReg = isRD; // rd is FP, rs1 is integer - } else if(funct7 == 0x70) { // fmv.x.w, fclass.s - useFPReg = isRS1; // rs1 is FP, rd is integer - } else if(funct7 == 0x78) { // fmv.w.x - useFPReg = isRD; // rd is FP, rs1 is integer - } else if(funct7 == 0x50) { // feq.s, flt.s, fle.s - useFPReg = (isRS1 || isRS2); // rs1 and rs2 are FP, rd is integer - } else if(funct7 == 0x51) { // feq.d, flt.d, fle.d - useFPReg = (isRS1 || isRS2); // rs1 and rs2 are FP, rd is integer - } else if(funct7 == 0x61) { // fcvt.w.d, fcvt.wu.d - useFPReg = isRS1; // rs1 is FP, rd is integer - } else if(funct7 == 0x69) { // fcvt.d.w, fcvt.d.wu - useFPReg = isRD; // rd is FP, rs1 is integer - } else if(funct7 == 0x71) { // fclass.d - useFPReg = isRS1; // rs1 is FP, rd is integer - } else { - // All other F/D extension instructions: all registers are FP - useFPReg = true; - } - } - } - - // Use the determined register type - if(useFPReg && regnum + 32 < lang->regnames.size()) { - QString fpname = lang->regnames[regnum + 32]; - if(fpname.startsWith("f")) { - return fpname; - } - } - - // Prefer integer registers for non-FP or when useFPReg is false - if(regnum < 32 && regnum < lang->regnames.size()) { - QString intname = lang->regnames[regnum]; - // If it's not a floating point register name, use it - if(!intname.startsWith("f")) { - return intname; - } - } - - // Fallback to floating point register if integer register wasn't found - if(regnum + 32 < lang->regnames.size()) { - QString fpname = lang->regnames[regnum + 32]; - if(fpname.startsWith("f")) { - return fpname; - } - } - - // Final fallback - if(regnum < lang->regnames.size()) { - return lang->regnames[regnum]; - } - return QString::asprintf("r%llu", (unsigned long long) regnum); -} - -void GAParameterRiscvReg::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int regnum = lang->regnames.indexOf(op.value); - if(regnum == -1) { - op.goodasm->error("Unknown RISC-V register: " + op.value); - return; - } - // Floating point registers f0-f31 are at indices 32-63, but encode as 0-31 - if(regnum >= 32 && regnum < 64) { - regnum -= 32; - } - rawencode(lang, adr, bytes, op, inslen, regnum); -} - -// RISC-V Imm12 (imm[11:0]) parameter - -GAParameterRiscvImm12::GAParameterRiscvImm12(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvImm12::match(GAParserOperand *op, int len){ - int64_t val=op->int64(false); //False on a match, int64 handles negative prefix. - - // must fit signed 12-bit immediate - if (val < -2048 || val > 2047) { - op->goodasm->error("RISC-V imm12 is out of range (-2048 to 2047)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvImm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - int32_t val = (raw & 0x800) ? (raw | ~0xFFF) : (raw & 0xFFF); - // Format as hex if value is >= 0x10 or negative, otherwise decimal - if (val < 0 || (uint32_t)val >= 0x10) { - return prefix + QString::asprintf("0x%x", (uint32_t)val); - } - return prefix + QString::number(val); -} - -void GAParameterRiscvImm12::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.int64(true); - - if (val < -2048 || val > 2047) { - op.goodasm->error("RISC-V imm12 is out of range (-2048 to 2047)."); - return; - } - - rawencode(lang,adr,bytes,op,inslen,val); -} - -// RISC-V U-type Imm20 (imm[31:12]) parameter - -GAParameterRiscvUtypeImm20::GAParameterRiscvUtypeImm20(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvUtypeImm20::match(GAParserOperand *op, int len){ - // Try parsing as unsigned first, then signed if that fails - uint64_t val=op->uint64(false); // False on a match - - // If uint64 parsing failed, try int64 (for negative values, though U-type shouldn't have them) - if (val == (uint64_t)-1) { - int64_t sval = op->int64(false); - if (sval == -1) { - return 0; // Parsing failed, let other parameter types try - } - // If negative, reject (U-type immediates are unsigned) - if (sval < 0) { - return 0; - } - val = (uint64_t)sval; - } - - // U-type immediate: the value is the result value (what should be in rd) - // Must be <= 0xFFFFF000 and a multiple of 0x1000 (lower 12 bits must be zero) - - // Check if value is out of range - if (val > 0xFFFFF000) { - op->goodasm->error("RISC-V U-type instruction imm20 is out of range (0 to 0xFFFFF000, must be multiple of 0x1000)"); - return 0; - } - - // Check if value is a multiple of 0x1000 - if ((val & 0xFFF) != 0) { - op->goodasm->error("RISC-V U-type instruction imm20 must be a multiple of 0x1000 (lower 12 bits must be zero)"); - return 0; - } - - return 1; // valid value -} - -QString GAParameterRiscvUtypeImm20::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode extracts bits [31:12] which is the immediate field - // lui sets rd = imm[31:12] << 12, so we need to left-shift to show the result value - uint32_t imm_field = raw & 0xFFFFF; - uint64_t result = ((uint64_t)imm_field) << 12; - return prefix + QString::asprintf("0x%llx", (unsigned long long)result); -} - -void GAParameterRiscvUtypeImm20::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.int64(true); - uint32_t imm_field; - - // lui/auipc: rd = imm[31:12] << 12 - // The immediate value provided is the result value (what should be in rd) - // Extract the immediate field: imm[31:12] = val >> 12 - - // Check if value is out of range (max 32-bit value with lower 12 bits zero) - if (val > 0xFFFFF000) { - op.goodasm->error("RISC-V U-type imm20 is out of range (0 to 0xFFFFF000, must be multiple of 0x1000)."); - return; - } - - // Check if value is a multiple of 0x1000 (lower 12 bits must be zero) - if ((val & 0xFFF) != 0) { - op.goodasm->error("RISC-V U-type imm20 must be a multiple of 0x1000 (lower 12 bits must be zero)."); - return; - } - - // Right-shift by 12 to get the immediate field value that goes in bits [31:12] - imm_field = (val >> 12) & 0xFFFFF; - - rawencode(lang,adr,bytes,op,inslen,imm_field); -} - -// RISC-V B-type Imm13 (imm[12:1]) parameter -// Encoding: imm[12] in bit [31], imm[11] in bit [7], imm[10:5] in bits [30:25], imm[4:1] in bits [11:8] -// Mask: "\x80\x8F\xF0\xBF" - combined from: imm[12] (0x80 in byte 3), imm[11] (0x80 in byte 1), imm[10:5] (0xF0 in byte 2, 0x3F in byte 3), imm[4:1] (0x0F in byte 1) - -GAParameterRiscvBtypeImm13::GAParameterRiscvBtypeImm13(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvBtypeImm13::match(GAParserOperand *op, int len){ - int64_t val=op->int64(false); // False on a match - - // must fit signed 13-bit immediate, and must be even (imm[0] = 0) - if (val < -4096 || val > 4094) { - op->goodasm->error("RISC-V B-type imm13 is out of range (-4096 to 4094)"); - return 0; - } - if ((val & 1) != 0) { - op->goodasm->error("RISC-V B-type imm13 must be even (target address must be 2-byte aligned)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvBtypeImm13::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode packs bits in mask order: bit7(imm[11]), bits8-11(imm[4:1]), bits25-30(imm[10:5]), bit31(imm[12]) - int32_t imm11 = raw & 1; - int32_t imm4_1 = (raw >> 1) & 0xF; - int32_t imm10_5 = (raw >> 5) & 0x3F; - int32_t imm12 = (raw >> 11) & 1; - int32_t imm = (imm12 << 12) | (imm11 << 11) | (imm10_5 << 5) | (imm4_1 << 1); - // Sign extend from 13 bits - if (imm & 0x1000) { - imm |= ~0x1FFF; - } - return prefix + QString::number(imm); -} - -void GAParameterRiscvBtypeImm13::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.int64(true); - - if (val < -4096 || val > 4094) { - op.goodasm->error("RISC-V B-type imm13 is out of range (-4096 to 4094)."); - return; - } - if ((val & 1) != 0) { - op.goodasm->error("RISC-V B-type imm13 must be even (target address must be 2-byte aligned)."); - return; - } - - // Pack imm[12:1] in mask order: imm[11], imm[4:1], imm[10:5], imm[12] - uint32_t imm = val & 0x1FFE; - uint32_t raw = ((imm >> 11) & 1) | - ((imm >> 1) & 0xF) << 1 | - ((imm >> 5) & 0x3F) << 5 | - ((imm >> 12) & 1) << 11; - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V J-type Imm21 (imm[20:1]) parameter -// Encoding: imm[20] in bit [31], imm[19:12] in bits [19:12], imm[11] in bit [20], imm[10:1] in bits [30:21] -// Mask: "\x00\xFF\x10\xFF" - combined from: imm[20] (0x80 in byte 3), imm[19:12] (0xFF in byte 1), imm[11] (0x10 in byte 2), imm[10:1] (0x7F in byte 3) - -GAParameterRiscvJtypeImm21::GAParameterRiscvJtypeImm21(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvJtypeImm21::match(GAParserOperand *op, int len){ - int64_t val=op->int64(false); // False on a match - - // must fit signed 21-bit immediate, and must be even (imm[0] = 0) - if (val < -1048576 || val > 1048574) { - op->goodasm->error("RISC-V J-type imm21 is out of range (-1048576 to 1048574)"); - return 0; - } - if ((val & 1) != 0) { - op->goodasm->error("RISC-V J-type imm21 must be even (target address must be 2-byte aligned)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvJtypeImm21::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // Reconstruct imm[20:1] from mask-ordered bits - // Mask "\x00\xF0\xFF\xFF" extracts bits in this order: - // raw[3:0] = inst[15:12] = imm[19:16] - // raw[7:4] = inst[19:16] = imm[15:12] - // raw[8] = inst[20] = imm[11] - // raw[11:9] = inst[23:21] = imm[10:8] - // raw[18:12] = inst[30:24] = imm[7:1] - // raw[19] = inst[31] = imm[20] - int32_t imm20 = (raw >> 19) & 1; - int32_t imm19_16 = raw & 0xF; - int32_t imm15_12 = (raw >> 4) & 0xF; - int32_t imm11 = (raw >> 8) & 1; - int32_t imm10_8 = (raw >> 9) & 0x7; - int32_t imm7_1 = (raw >> 12) & 0x7F; - int32_t imm = (imm20 << 20) | (imm19_16 << 16) | (imm15_12 << 12) | (imm11 << 11) | (imm10_8 << 8) | (imm7_1 << 1); - // Sign extend from 21 bits - if (imm & 0x100000) { - imm |= ~0x1FFFFF; - } - return prefix + QString::number(imm); -} - -void GAParameterRiscvJtypeImm21::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.int64(true); - - if (val < -1048576 || val > 1048574) { - op.goodasm->error("RISC-V J-type imm21 is out of range (-1048576 to 1048574)."); - return; - } - if ((val & 1) != 0) { - op.goodasm->error("RISC-V J-type imm21 must be even (target address must be 2-byte aligned)."); - return; - } - - // Pack imm[20:1] into mask order - // raw[3:0] = imm[19:16] - // raw[7:4] = imm[15:12] - // raw[8] = imm[11] - // raw[11:9] = imm[10:8] - // raw[18:12] = imm[7:1] - // raw[19] = imm[20] - uint32_t imm = val & 0x1FFFFE; // imm[20:1], clear imm[0] - uint32_t raw = (((imm >> 20) & 1) << 19) | // imm[20] -> raw[19] - (((imm >> 1) & 0x7F) << 12) | // imm[7:1] -> raw[18:12] - (((imm >> 8) & 0x7) << 9) | // imm[10:8] -> raw[11:9] - (((imm >> 11) & 1) << 8) | // imm[11] -> raw[8] - (((imm >> 12) & 0xF) << 4) | // imm[15:12] -> raw[7:4] - ((imm >> 16) & 0xF); // imm[19:16] -> raw[3:0] - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V S-type Imm12 (imm[11:0]) parameter -// Encoding: imm[11:5] in bits [31:25], imm[4:0] in bits [11:7] -// Mask: "\x80\x0F\x00\xFE" - imm[4:0] in bits [11:7] (byte 0 bit 7 + byte 1 bits 0-3), imm[11:5] in bits [31:25] (byte 3 bits 1-7) - -GAParameterRiscvStypeImm12::GAParameterRiscvStypeImm12(const char* mask){ - setMask(mask); - prefix = "#"; - isSigned = true; // 12-bit signed immediate -} - -int GAParameterRiscvStypeImm12::match(GAParserOperand *op, int len){ - int64_t val=op->int64(false); // False on a match - - // must fit signed 12-bit immediate - if (val < -2048 || val > 2047) { - op->goodasm->error("RISC-V S-type imm12 is out of range (-2048 to 2047)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvStypeImm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode already extracts and packs imm[11:0] from the split encoding via the mask - int32_t imm = raw & 0xFFF; - // Sign extend from 12 bits - if (imm & 0x800) { - imm |= ~0xFFF; - } - return prefix + QString::number(imm); -} - -void GAParameterRiscvStypeImm12::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.int64(true); - - if (val < -2048 || val > 2047) { - op.goodasm->error("RISC-V S-type imm12 is out of range (-2048 to 2047)."); - return; - } - - // rawencode expects the immediate value directly (in mask bit order, not instruction bit positions) - // The mask will distribute the bits to the correct instruction positions - uint32_t imm = val & 0xFFF; // imm[11:0] - mask to 12 bits - rawencode(lang, adr, bytes, op, inslen, imm); -} - -// RISC-V FENCE pred/succ parameter -// Encoding: pred[3:0] in imm[3:0] (bits [23:20], byte 2 bits [7:4]) -// succ[3:0] in imm[7:4] (bits [27:24], byte 3 bits [3:0]) -// Mask: "\x00\x00\xF0\x0F" - pred in byte 2 bits [7:4], succ in byte 3 bits [3:0] - -GAParameterRiscvFencePredSucc::GAParameterRiscvFencePredSucc(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvFencePredSucc::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit 8-bit value (0-255) where lower 4 bits are pred and upper 4 bits are succ - if (val < 0 || val > 255) { - op->goodasm->error("RISC-V FENCE pred/succ is out of range (0 to 255)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvFencePredSucc::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - // Extract pred[3:0] from imm[3:0] (bits [23:20], byte 2 bits [7:4]) - // Extract succ[3:0] from imm[7:4] (bits [27:24], byte 3 bits [3:0]) - // For little-endian: byte 2 is bytes[2], byte 3 is bytes[3] - uint32_t pred = (bytes[2] >> 4) & 0x0F; // byte 2 bits [7:4] -> pred[3:0] - uint32_t succ = bytes[3] & 0x0F; // byte 3 bits [3:0] -> succ[3:0] - uint32_t val = (succ << 4) | pred; - return QString::asprintf("#0x%02X", val); -} - -void GAParameterRiscvFencePredSucc::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 255) { - op.goodasm->error("RISC-V FENCE pred/succ is out of range (0 to 255)."); - return; - } - - // Split into pred[3:0] and succ[3:0] - uint32_t pred = val & 0x0F; // lower 4 bits - uint32_t succ = (val >> 4) & 0x0F; // upper 4 bits - - // Encode directly into bytes: pred in byte 2 bits [7:4], succ in byte 3 bits [3:0] - // For little-endian: byte 2 is bytes[2], byte 3 is bytes[3] - bytes[2] = (bytes[2] & 0x0F) | (pred << 4); // Set byte 2 bits [7:4] to pred - bytes[3] = (bytes[3] & 0xF0) | succ; // Set byte 3 bits [3:0] to succ -} - -// RISC-V Shamt5 (shamt[4:0]) parameter -// Encoding: shamt[4:0] in bits [24:20] -// Mask: "\x00\x00\xF0\x01" - bits [24:20] in bytes 2-3 (byte 2 bits 7-4, byte 3 bit 0) - -GAParameterRiscvShamt5::GAParameterRiscvShamt5(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvShamt5::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit 5-bit shift amount (0 to 31) - if (val < 0 || val > 31) { - op->goodasm->error("RISC-V shamt5 is out of range (0 to 31)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvShamt5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode already extracts bits [24:20] into the value, so just return it - uint32_t shamt = raw & 0x1F; // Mask to 5 bits just to be safe - return prefix + QString::number(shamt); -} - -void GAParameterRiscvShamt5::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.int64(true); - - if (val < 0 || val > 31) { - op.goodasm->error("RISC-V shamt5 is out of range (0 to 31)."); - return; - } - - // Encode shamt[4:0] into bits [24:20] - rawencode(lang,adr,bytes,op,inslen,val); -} - -// RISC-V CSR12 (csr[11:0]) parameter -// Encoding: csr[11:0] in bits [31:20] -// Mask: "\x00\x00\xF0\xFF" - bits [31:20] in bytes 2-3 - -GAParameterRiscvCsr12::GAParameterRiscvCsr12(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCsr12::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit unsigned 12-bit CSR address (0 to 4095) - if (val < 0 || val > 4095) { - op->goodasm->error("RISC-V CSR12 is out of range (0 to 4095)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCsr12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode already extracts bits [31:20] into the lower bits - uint32_t csr = raw & 0xFFF; - return QString::asprintf("#0x%03X", csr); -} - -void GAParameterRiscvCsr12::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 4095) { - op.goodasm->error("RISC-V CSR12 is out of range (0 to 4095)."); - return; - } - - // Encode csr[11:0] into bits [31:20] - rawencode(lang,adr,bytes,op,inslen,val); -} - -// RISC-V Uimm5 (uimm[4:0]) parameter -// Encoding: uimm[4:0] in bits [19:15] -// Mask: "\x00\x80\x0F\x00" - bits [19:15] in byte 1-2 - -GAParameterRiscvUimm5::GAParameterRiscvUimm5(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvUimm5::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit 5-bit unsigned immediate (0 to 31) - if (val < 0 || val > 31) { - op->goodasm->error("RISC-V uimm5 is out of range (0 to 31)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvUimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode already extracts bits [19:15] into the lower bits - uint32_t uimm = raw & 0x1F; - return prefix + QString::number(uimm); -} - -void GAParameterRiscvUimm5::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 31) { - op.goodasm->error("RISC-V uimm5 is out of range (0 to 31)."); - return; - } - - // Encode uimm[4:0] into bits [19:15] - rawencode(lang,adr,bytes,op,inslen,val); -} - -// C Extension parameter types for compressed 16-bit instructions - -// RISC-V Compressed Register (rd'/rs1'/rs2') parameter -// Encoding: 3-bit field for registers x8-x15 (encoded as 0-7) -// rd' in bits [4:2] (CIW format) or bits [9:7] (most formats) -// rs1' in bits [9:7] -// rs2' in bits [4:2] -// Mask depends on specific format - -GAParameterRiscvCompReg::GAParameterRiscvCompReg(const char* mask){ - setMask(mask); -} - -int GAParameterRiscvCompReg::match(GAParserOperand *op, int len){ - if(op->prefix!=this->prefix) - return 0; - - // Check if it is a valid RISC-V register name. - QString name = op->value; - // Compressed registers are x8-x15 (s0-s1, a0-a7) - if(name == "s0" || name == "s1" || - name == "a0" || name == "a1" || name == "a2" || name == "a3" || - name == "a4" || name == "a5" || name == "a6" || name == "a7") { - return 1; - } - return 0; -} - -QString GAParameterRiscvCompReg::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t regnum = rawdecode(lang, adr, bytes, inslen); - // Compressed register encoding: 0-7 maps to x8-x15 - if(regnum > 7) { - return QString::asprintf("r%llu", (unsigned long long)(regnum + 8)); - } - // Map 0-7 to x8-x15 (s0, s1, a0-a7) - int regnames_idx = 8 + regnum; // x8 = s0, x9 = s1, x10 = a0, etc. - if(regnames_idx < lang->regnames.size()) { - return lang->regnames[regnames_idx]; - } - return QString::asprintf("r%llu", (unsigned long long)(regnum + 8)); -} - -void GAParameterRiscvCompReg::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int regnum = lang->regnames.indexOf(op.value); - if(regnum == -1) { - op.goodasm->error("Unknown RISC-V register: " + op.value); - return; - } - // Compressed registers must be x8-x15 - if(regnum < 8 || regnum > 15) { - op.goodasm->error("RISC-V compressed register must be x8-x15 (s0, s1, a0-a7): " + op.value); - return; - } - // Map x8-x15 (8-15) to compressed encoding (0-7) - int compressed = regnum - 8; - rawencode(lang, adr, bytes, op, inslen, compressed); -} - -// RISC-V CI Format Immediate (imm[5:0]) parameter -// Encoding: imm[5] in bit [12], imm[4:0] in bits [6:2] -// Mask depends on specific instruction - -GAParameterRiscvCIimm6::GAParameterRiscvCIimm6(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCIimm6::match(GAParserOperand *op, int len){ - int64_t val=op->int64(false); // False on a match - - // Standard CI format: must fit signed 6-bit immediate (-32 to 31) - if (val >= -32 && val <= 31) { - return 1; // valid for standard CI - } - - // c.lui: accepts values 0-63 (imm[17:12]) or shifted values (imm << 12) - // where imm[17:12] is in range 0-63 - // This means values that are multiples of 0x1000 in range 0x0 to 0x3F000 - if (val >= 0) { - if (val <= 63) { - return 1; // valid for c.lui (direct imm[17:12]) - } - // Check if it's a valid shifted value for c.lui - if ((val & 0xFFF) == 0) { // Must be multiple of 0x1000 - uint32_t imm_upper = (val >> 12) & 0x3F; - if (imm_upper >= 1 && imm_upper <= 63) { // c.lui cannot be 0 (reserved for c.addi16sp) - return 1; // valid for c.lui (shifted value) - } - } - } - - // c.addi16sp: accepts multiples of 16 in range -512 to 496 - if ((val & 0xF) == 0) { // Must be multiple of 16 - if (val >= -512 && val <= 496) { - return 1; // valid for c.addi16sp - } - } - - // Value doesn't fit any CI format - op->goodasm->error("RISC-V CI imm6 is out of range (-32 to 31 for standard CI, 0-63 or multiples of 0x1000 up to 0x3F000 for c.lui, or multiples of 16 in -512 to 496 for c.addi16sp)"); - return 0; -} - -QString GAParameterRiscvCIimm6::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - - // Check if this is c.addi16sp (rd=2, bits [1:0]=01, [15:13]=011) or c.lui (bits [1:0]=01, [15:13]=011, rd!=0,2) - // rd is the definitive distinguisher - c.addi16sp has rd=2, c.lui has rd != 0 and rd != 2 - bool is_addi16sp = false; - bool is_lui = false; - if(inslen >= 2) { - uint8_t byte0 = bytes[0]; - uint8_t byte1 = bytes[1]; - uint8_t opcode_low = byte0 & 0x03; // bits [1:0] - uint8_t opcode_high = (byte1 >> 5) & 0x07; // bits [15:13] - - // Extract rd from bits [11:7]: - // bit [7] is in byte0 bit 7 - // bits [11:8] are in byte1 bits [3:0] - // So rd = (bits [11:8] << 1) | bit [7] - uint8_t rd_high = (byte1 & 0x0F); // bits [11:8] - uint8_t rd_low = (byte0 >> 7) & 0x01; // bit [7] - uint8_t rd = (rd_high << 1) | rd_low; - - if(opcode_low == 0x01 && opcode_high == 0x03) { // bits [1:0]=01, [15:13]=011 - if(rd == 2) { - is_addi16sp = true; // rd=2 definitively indicates c.addi16sp - } else if(rd != 0 && rd != 2) { - is_lui = true; // rd != 0,2 definitively indicates c.lui - } - // rd == 0 is invalid for both c.addi16sp and c.lui (reserved) - } - } - - if(is_addi16sp) { - // c.addi16sp: nzimm[9:4] encoded in bits [12|6|5:2] - // According to RISC-V spec and rawencode order: - // rawencode processes mask 0x7C10 in order: - // val[0]->bit[2] (nzimm[6]) - // val[1]->bit[3] (nzimm[7]) - // val[2]->bit[4] (nzimm[8]) - // val[3]->bit[5] (nzimm[9]) - // val[4]->bit[6] (nzimm[4]) - // val[5]->bit[12] (nzimm[5]) - // So rawdecode extracts in the same order: - // raw[0] = nzimm[6] - // raw[1] = nzimm[7] - // raw[2] = nzimm[8] - // raw[3] = nzimm[9] - // raw[4] = nzimm[4] - // raw[5] = nzimm[5] - // The instruction does: sp = sp + sext(nzimm[9:4] << 4) - if(inslen >= 2) { - // Extract individual bits from raw value (already decoded by rawdecode) - uint32_t nzimm6 = (raw >> 0) & 1; // raw[0] = nzimm[6] - uint32_t nzimm7 = (raw >> 1) & 1; // raw[1] = nzimm[7] - uint32_t nzimm8 = (raw >> 2) & 1; // raw[2] = nzimm[8] - uint32_t nzimm9 = (raw >> 3) & 1; // raw[3] = nzimm[9] - uint32_t nzimm4 = (raw >> 4) & 1; // raw[4] = nzimm[4] - uint32_t nzimm5 = (raw >> 5) & 1; // raw[5] = nzimm[5] - // Reconstruct nzimm[9:4] (6 bits): nzimm[9] is MSB, nzimm[4] is LSB - uint32_t nzimm_6bit = (nzimm9 << 5) | (nzimm8 << 4) | (nzimm7 << 3) | (nzimm6 << 2) | (nzimm5 << 1) | nzimm4; - // Sign extend from 6 bits (nzimm[9] is the sign bit) - // Convert to signed 6-bit value: if bit 5 is set, it's negative - int32_t signed_nzimm_6bit; - if(nzimm_6bit & 0x20) { // Check bit 5 (nzimm[9] when in position) - negative - signed_nzimm_6bit = (int32_t)(nzimm_6bit | 0xFFFFFFC0); // Sign extend to 32 bits - } else { - signed_nzimm_6bit = (int32_t)nzimm_6bit; // Positive, no sign extension needed - } - // The instruction does: sp = sp + sext(nzimm[9:4] << 4) - int32_t result = signed_nzimm_6bit << 4; - return prefix + QString::number(result); - } - return prefix + QString::number(0); - } else if(is_lui) { - // c.lui: imm[17:12] in bits [12|6:2] (same positions as CI format) - // The instruction does: rd = imm << 12 - // Extract directly from bytes - if(inslen >= 2) { - uint8_t byte0 = bytes[0]; - uint8_t byte1 = bytes[1]; - uint32_t imm17 = (byte1 >> 4) & 1; // bit [12] = byte1 bit 4 - uint32_t imm16_12 = (byte0 >> 2) & 0x1F; // bits [6:2] = byte0 bits 6:2 - uint32_t imm_upper = (imm17 << 5) | imm16_12; // imm[17:12] - // Return the full shifted value (imm << 12) for display - uint32_t imm_full = imm_upper << 12; - return prefix + QString::asprintf("0x%x", imm_full); - } - return QString::number(0); - } - - // Standard CI format: rawdecode packs bits in mask order - // Mask 0x7C10: bits [6:2] -> raw[4:0], bit [12] -> raw[5] - uint32_t imm4_0 = raw & 0x1F; // raw[4:0] = imm[4:0] - uint32_t imm5 = (raw >> 5) & 1; // raw[5] = imm[5] - int32_t imm = (imm5 << 5) | imm4_0; - // Sign extend from 6 bits - if (imm & 0x20) { - imm |= ~0x3F; - } - return prefix + QString::number(imm); -} - -void GAParameterRiscvCIimm6::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.int64(true); - - // Check if this might be c.addi16sp (value is multiple of 16, range -512 to 496) - // or c.lui (value represents upper 6 bits, typically 0-63 but represents imm << 12) - // We detect by checking opcode, rd value, and value constraints - bool is_addi16sp = false; - bool is_lui = false; - if(inslen >= 2 && bytes.length() >= 2) { - uint8_t byte0 = bytes[0]; - uint8_t byte1 = bytes[1]; - uint8_t opcode_low = byte0 & 0x03; - uint8_t opcode_high = (byte1 >> 5) & 0x07; - - if(opcode_low == 0x01 && opcode_high == 0x03) { - // Extract rd from bits [11:7]: - // bit [7] is in byte0 bit 7 - // bits [11:8] are in byte1 bits [3:0] - // So rd = (bits [11:8] << 1) | bit [7] - uint8_t rd_high = (byte1 & 0x0F); // bits [11:8] - uint8_t rd_low = (byte0 >> 7) & 0x01; // bit [7] - uint8_t rd = (rd_high << 1) | rd_low; - - // Check value constraints - bool val_is_multiple_of_16 = ((val & 0xF) == 0) && (val >= -512) && (val <= 496); - bool val_is_lui_range = (val >= 0 && val <= 63) || ((val & 0xFFF) == 0 && (val >> 12) >= 1 && (val >> 12) <= 63); - - // Check value constraints first - if value can only be one instruction, use that - if(val_is_lui_range && !val_is_multiple_of_16) { - // Value only matches c.lui range - is_lui = true; - } else if(val_is_multiple_of_16 && !val_is_lui_range) { - // Value only matches c.addi16sp range - is_addi16sp = true; - } else { - // Value matches both or neither - use rd as definitive distinguisher - if(rd == 2) { - is_addi16sp = true; // rd=2 definitively indicates c.addi16sp - } else if(rd != 0 && rd != 2) { - is_lui = true; // rd != 0,2 definitively indicates c.lui - } else { - // rd is 0 or not yet set - value matches both ranges - // If value is a multiple of 0x1000 (c.lui format), prefer c.lui - if((val & 0xFFF) == 0 && (val >> 12) >= 1 && (val >> 12) <= 63) { - is_lui = true; - } else if(val_is_multiple_of_16) { - // Value is multiple of 16 but not 0x1000 - prefer c.addi16sp - is_addi16sp = true; - } - // If neither matches, neither will be set and standard CI encoding will be used - } - } - } - } - - if(is_addi16sp) { - // c.addi16sp: encode imm[9|4|6|8:7|5] where imm is the actual value (not shifted) - // The instruction does: sp = sp + (imm << 4), so we need to divide by 16 - // Also ensure rd=2 (sp) is set in the instruction - if((val & 0xF) != 0) { - op.goodasm->error("RISC-V c.addi16sp immediate must be a multiple of 16."); - return; - } - if(val < -512 || val > 496) { - op.goodasm->error("RISC-V c.addi16sp immediate is out of range (-512 to 496)."); - return; - } - // Set rd=2 (sp) in the instruction: rd bits [11:7] = 2 = 00010 - // bit [7] is in byte0 bit 7, bits [11:8] are in byte1 bits [3:0] - if(inslen >= 2 && bytes.length() >= 2) { - bytes[0] = (bytes[0] & ~0x80) | (0 << 7); // bit [7] = 0 (from rd bit 0) - bytes[1] = (bytes[1] & ~0x0F) | (1 << 0); // bits [11:8] = 0001 (from rd bits [4:1]) - } - int32_t imm_shifted = (int32_t)(val >> 4); // Divide by 16 (signed) - // Convert to 6-bit two's complement for encoding - // Mask to 6 bits - this automatically handles two's complement for negative values - uint32_t nzimm_6bit = (uint32_t)(imm_shifted & 0x3F); // Get lower 6 bits (handles negative correctly) - // Now extract the individual bits for the scrambled encoding - // According to RISC-V spec: - // nzimm[5] goes to bit [12] - // nzimm[4] goes to bit [6] - // nzimm[9:6] go to bits [5:2] - uint32_t nzimm9 = (nzimm_6bit >> 5) & 1; // nzimm[9] -> bit [5] - uint32_t nzimm8 = (nzimm_6bit >> 4) & 1; // nzimm[8] -> bit [4] - uint32_t nzimm7 = (nzimm_6bit >> 3) & 1; // nzimm[7] -> bit [3] - uint32_t nzimm6 = (nzimm_6bit >> 2) & 1; // nzimm[6] -> bit [2] - uint32_t nzimm5 = (nzimm_6bit >> 1) & 1; // nzimm[5] -> bit [12] - uint32_t nzimm4 = (nzimm_6bit >> 0) & 1; // nzimm[4] -> bit [6] - // Encode according to c.addi16sp format - // rawencode processes mask 0x7C10 (little-endian) in this order: - // Byte 0: bits [6:2] = 0x7C, processes j=2,3,4,5,6 in order - // Byte 1: bit [12] = 0x10, processes j=4 in byte1 - // So the order is: val[0]->bit[2], val[1]->bit[3], val[2]->bit[4], val[3]->bit[5], val[4]->bit[6], val[5]->bit[12] - // Which means: nzimm[6]->bit[2], nzimm[7]->bit[3], nzimm[8]->bit[4], nzimm[9]->bit[5], nzimm[4]->bit[6], nzimm[5]->bit[12] - uint32_t raw = (nzimm6 << 0) | // val[0] -> bit [2] (nzimm[6]) - (nzimm7 << 1) | // val[1] -> bit [3] (nzimm[7]) - (nzimm8 << 2) | // val[2] -> bit [4] (nzimm[8]) - (nzimm9 << 3) | // val[3] -> bit [5] (nzimm[9]) - (nzimm4 << 4) | // val[4] -> bit [6] (nzimm[4]) - (nzimm5 << 5); // val[5] -> bit [12] (nzimm[5]) - rawencode(lang,adr,bytes,op,inslen,raw); - } else if(is_lui) { - // c.lui: encode imm[17:12] where the value represents the upper 6 bits - // The instruction does: rd = imm << 12 - // If val is already the shifted value (like 0x10000), extract upper bits - // Otherwise, if val is 0-63, treat it as imm[17:12] directly - uint32_t imm_upper; - if(val >= 0 && val <= 63) { - imm_upper = val; // Direct value 0-63 - } else { - imm_upper = (val >> 12) & 0x3F; // Extract upper 6 bits from shifted value - } - if(imm_upper == 0) { - op.goodasm->error("RISC-V c.lui immediate cannot be 0 (reserved for c.addi16sp)."); - return; - } - // Note: imm_upper == 1 is technically reserved per spec, but some implementations allow it - // rawencode processes mask 0x7C10 in order: val[0]->bit[2], val[1]->bit[3], val[2]->bit[4], val[3]->bit[5], val[4]->bit[6], val[5]->bit[12] - // For c.lui: imm[17:12] maps to bits [12|6:2] - // So: imm[12]->bit[2], imm[13]->bit[3], imm[14]->bit[4], imm[15]->bit[5], imm[16]->bit[6], imm[17]->bit[12] - uint32_t imm12 = (imm_upper >> 0) & 1; - uint32_t imm13 = (imm_upper >> 1) & 1; - uint32_t imm14 = (imm_upper >> 2) & 1; - uint32_t imm15 = (imm_upper >> 3) & 1; - uint32_t imm16 = (imm_upper >> 4) & 1; - uint32_t imm17 = (imm_upper >> 5) & 1; - uint32_t raw = (imm12 << 0) | // val[0] -> bit [2] - (imm13 << 1) | // val[1] -> bit [3] - (imm14 << 2) | // val[2] -> bit [4] - (imm15 << 3) | // val[3] -> bit [5] - (imm16 << 4) | // val[4] -> bit [6] - (imm17 << 5); // val[5] -> bit [12] - rawencode(lang,adr,bytes,op,inslen,raw); - } else { - // Standard CI format - if (val < -32 || val > 31) { - op.goodasm->error("RISC-V CI imm6 is out of range (-32 to 31)."); - return; - } - - // rawencode packs bits in mask order: raw[4:0]->inst[6:2], raw[5]->inst[12] - // This matches imm[4:0] and imm[5] directly - uint32_t raw = val & 0x3F; // imm[5:0] directly - - rawencode(lang,adr,bytes,op,inslen,raw); - } -} - -// RISC-V CI Format Immediate Unsigned (uimm[5:0]) parameter -// Encoding: Same as CI format but unsigned (0-31) -// Used in C.SLLI, C.SRLI, C.SRAI - -GAParameterRiscvCIUimm6::GAParameterRiscvCIUimm6(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCIUimm6::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit unsigned 6-bit immediate (0 to 31) - if (val < 0 || val > 31) { - op->goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCIUimm6::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode extracts bits in order: [12] (byte 1 bit 4), then [6:2] (byte 0 bits [6:2]) - // So the result has: [12] at bit 5, [6] at bit 4, [5] at bit 3, [4] at bit 2, [3] at bit 1, [2] at bit 0 - // This gives us: imm[5]|imm[4]|imm[3]|imm[2]|imm[1]|imm[0] - uint32_t imm5 = (raw >> 5) & 1; // imm[5] from bit [12] (at position 5 in raw) - uint32_t imm4 = (raw >> 4) & 1; // imm[4] from bit [6] (at position 4 in raw) - uint32_t imm3_0 = raw & 0xF; // imm[3:0] from bits [5:2] (at positions [3:0] in raw) - uint32_t imm = (imm5 << 5) | (imm4 << 4) | imm3_0; - return prefix + QString::number(imm); -} - -void GAParameterRiscvCIUimm6::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 31) { - op.goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)."); - return; - } - - // Encode uimm[5] into bit [12] and uimm[4:0] into bits [6:2] - // rawencode expects the value in the same order as rawdecode extracts it: - // - imm[5] at bit position 5 (encodes to [12]) - // - imm[4] at bit position 4 (encodes to [6]) - // - imm[3:0] at bit positions [3:0] (encodes to [5:2]) - uint32_t imm = val & 0x3F; // uimm[5:0] - uint32_t raw = ((imm >> 5) & 1) << 5 | // uimm[5] -> position 5 (encodes to bit [12]) - ((imm >> 4) & 1) << 4 | // uimm[4] -> position 4 (encodes to bit [6]) - ((imm >> 0) & 0xF); // uimm[3:0] -> positions [3:0] (encodes to bits [5:2]) - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V CI Format Immediate Unsigned (uimm[5:0]) parameter for C.SRAI -// Encoding: Same as CIUimm6 but bit [6] is part of opcode (must be 1) -// Used in C.SRAI only (C.SLLI and C.SRLI use GAParameterRiscvCIUimm6) - -GAParameterRiscvCIUimm6Srai::GAParameterRiscvCIUimm6Srai(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCIUimm6Srai::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit unsigned 6-bit immediate (0 to 31) - if (val < 0 || val > 31) { - op->goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCIUimm6Srai::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - // Use the same logic as GAParameterRiscvCIUimm6 - the encoding is the same - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode extracts bits in order: [12] (byte 1 bit 4), then [6:2] (byte 0 bits [6:2]) - // So the result has: [12] at bit 5, [6] at bit 4, [5] at bit 3, [4] at bit 2, [3] at bit 1, [2] at bit 0 - uint32_t imm5 = (raw >> 5) & 1; // imm[5] from bit [12] (at position 5 in raw) - uint32_t imm4 = (raw >> 4) & 1; // imm[4] from bit [6] (at position 4 in raw) - uint32_t imm3_0 = raw & 0xF; // imm[3:0] from bits [5:2] (at positions [3:0] in raw) - uint32_t imm = (imm5 << 5) | (imm4 << 4) | imm3_0; - return prefix + QString::number(imm); -} - -void GAParameterRiscvCIUimm6Srai::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 31) { - op.goodasm->error("RISC-V CI uimm6 is out of range (0 to 31)."); - return; - } - - // Encode uimm[5] into bit [12] and uimm[4:0] into bits [6:2] - // rawencode expects the value in the same order as rawdecode extracts it: - // - imm[5] at bit position 5 (encodes to [12]) - // - imm[4] at bit position 4 (encodes to [6]) - // - imm[3:0] at bit positions [3:0] (encodes to [5:2]) - uint32_t imm = val & 0x3F; // uimm[5:0] - uint32_t raw = ((imm >> 5) & 1) << 5 | // uimm[5] -> position 5 (encodes to bit [12]) - ((imm >> 4) & 1) << 4 | // uimm[4] -> position 4 (encodes to bit [6]) - ((imm >> 0) & 0xF); // uimm[3:0] -> positions [3:0] (encodes to bits [5:2]) - - // Clear bits [6:5] first since they're part of the opcode pattern but also encode imm[4:3] - // The mask 0x7C covers bits [6:2], so we need to clear bits [6:5] before encoding - bytes[0] &= ~0x60; // Clear bits [6:5] in byte 0 - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V CI Format Immediate (imm[7:2]) parameter for c.lwsp -// Encoding: imm[5] in bit [12], imm[4:2] in bits [6:4], imm[7:6] in bits [3:2] -// Used in C.LWSP - -GAParameterRiscvCIimm7::GAParameterRiscvCIimm7(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCIimm7::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit unsigned 8-bit immediate, 4-byte aligned (imm[1:0] = 0) - // Range: 0, 4, 8, 12, ..., 252 (must be multiple of 4, 0-252) - if (val < 0 || val > 252 || (val & 3) != 0) { - op->goodasm->error("RISC-V CI imm7 is out of range (0 to 252, must be multiple of 4)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCIimm7::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // Mask "\x7C\x10" captures instruction bits [6:4], [3:2], [12] - // rawdecode packs bits sequentially by mask position: - // raw bit 0 = instruction bit 2 = imm[6] - // raw bit 1 = instruction bit 3 = imm[7] - // raw bit 2 = instruction bit 4 = imm[2] - // raw bit 3 = instruction bit 5 = imm[3] - // raw bit 4 = instruction bit 6 = imm[4] - // raw bit 5 = instruction bit 12 = imm[5] - uint32_t imm6 = (raw >> 0) & 1; - uint32_t imm7 = (raw >> 1) & 1; - uint32_t imm2 = (raw >> 2) & 1; - uint32_t imm3 = (raw >> 3) & 1; - uint32_t imm4 = (raw >> 4) & 1; - uint32_t imm5 = (raw >> 5) & 1; - uint32_t imm = (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); - return prefix + QString::number(imm); -} - -void GAParameterRiscvCIimm7::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 252 || (val & 3) != 0) { - op.goodasm->error("RISC-V CI imm7 is out of range (0 to 252, must be multiple of 4)."); - return; - } - - // Encode imm[7:2] into sequential raw bits (matching mask bit order) - // raw bit 0 = imm[6] - // raw bit 1 = imm[7] - // raw bit 2 = imm[2] - // raw bit 3 = imm[3] - // raw bit 4 = imm[4] - // raw bit 5 = imm[5] - uint32_t imm = val; - uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 - ((imm >> 7) & 1) << 1 | // imm[7] -> raw bit 1 - ((imm >> 2) & 1) << 2 | // imm[2] -> raw bit 2 - ((imm >> 3) & 1) << 3 | // imm[3] -> raw bit 3 - ((imm >> 4) & 1) << 4 | // imm[4] -> raw bit 4 - ((imm >> 5) & 1) << 5; // imm[5] -> raw bit 5 - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V CIW Format Immediate (imm[9:2]) parameter -// Encoding: imm[9:2] in bits [10:7|12:11|5|6] (split across instruction) -// Used in C.ADDI4SPN - -GAParameterRiscvCIWimm9::GAParameterRiscvCIWimm9(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCIWimm9::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit unsigned 9-bit immediate, 4-byte aligned (imm[1:0] = 0) - // Range: 0 to 1020 (must be multiple of 4) - if (val < 0 || val > 1020 || (val & 3) != 0) { - op->goodasm->error("RISC-V CIW imm9 is out of range (0 to 1020, must be multiple of 4)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCIWimm9::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // Extract imm[9:2] from split encoding - // Mask "\xE0\x1F" captures instruction bits [12:5] - // rawdecode packs bits sequentially: - // raw bit 0 = instruction bit 5 = nzuimm[3] - // raw bit 1 = instruction bit 6 = nzuimm[2] - // raw bit 2 = instruction bit 7 = nzuimm[6] - // raw bit 3 = instruction bit 8 = nzuimm[7] - // raw bit 4 = instruction bit 9 = nzuimm[8] - // raw bit 5 = instruction bit 10 = nzuimm[9] - // raw bit 6 = instruction bit 11 = nzuimm[4] - // raw bit 7 = instruction bit 12 = nzuimm[5] - uint32_t imm3 = (raw >> 0) & 1; // raw bit 0 - uint32_t imm2 = (raw >> 1) & 1; // raw bit 1 - uint32_t imm6 = (raw >> 2) & 1; // raw bit 2 - uint32_t imm7 = (raw >> 3) & 1; // raw bit 3 - uint32_t imm8 = (raw >> 4) & 1; // raw bit 4 - uint32_t imm9 = (raw >> 5) & 1; // raw bit 5 - uint32_t imm4 = (raw >> 6) & 1; // raw bit 6 - uint32_t imm5 = (raw >> 7) & 1; // raw bit 7 - uint32_t imm = (imm9 << 9) | (imm8 << 8) | (imm7 << 7) | (imm6 << 6) | - (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); - return prefix + QString::number(imm); -} - -void GAParameterRiscvCIWimm9::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 1020 || (val & 3) != 0) { - op.goodasm->error("RISC-V CIW imm9 is out of range (0 to 1020, must be multiple of 4)."); - return; - } - - // Encode imm[9:2] into sequential raw bits (matching mask bit order) - // raw bit 0 = nzuimm[3] - // raw bit 1 = nzuimm[2] - // raw bit 2 = nzuimm[6] - // raw bit 3 = nzuimm[7] - // raw bit 4 = nzuimm[8] - // raw bit 5 = nzuimm[9] - // raw bit 6 = nzuimm[4] - // raw bit 7 = nzuimm[5] - uint32_t imm = val; - uint32_t raw = ((imm >> 3) & 1) << 0 | // nzuimm[3] -> raw bit 0 - ((imm >> 2) & 1) << 1 | // nzuimm[2] -> raw bit 1 - ((imm >> 6) & 1) << 2 | // nzuimm[6] -> raw bit 2 - ((imm >> 7) & 1) << 3 | // nzuimm[7] -> raw bit 3 - ((imm >> 8) & 1) << 4 | // nzuimm[8] -> raw bit 4 - ((imm >> 9) & 1) << 5 | // nzuimm[9] -> raw bit 5 - ((imm >> 4) & 1) << 6 | // nzuimm[4] -> raw bit 6 - ((imm >> 5) & 1) << 7; // nzuimm[5] -> raw bit 7 - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V CL Format Immediate (imm[5:2]) parameter -// Encoding: imm[5] in bit [12], imm[4:2] in bits [6:5|2] -// Used in C.LW - -GAParameterRiscvCLimm5::GAParameterRiscvCLimm5(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCLimm5::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit unsigned 4-bit immediate, 4-byte aligned (imm[1:0] = 0) - // Range: 0, 4, 8, 12, ..., 124 (must be multiple of 4, 0-124) - if (val < 0 || val > 124 || (val & 3) != 0) { - op->goodasm->error("RISC-V CL imm5 is out of range (0 to 124, must be multiple of 4)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCLimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // Mask "\x60\x1C" captures instruction bits [6:5], [12:10] - // rawdecode packs bits sequentially by mask position: - // raw bit 0 = instruction bit 5 = imm[6] - // raw bit 1 = instruction bit 6 = imm[2] - // raw bit 2 = instruction bit 10 = imm[3] - // raw bit 3 = instruction bit 11 = imm[4] - // raw bit 4 = instruction bit 12 = imm[5] - uint32_t imm6 = (raw >> 0) & 1; - uint32_t imm2 = (raw >> 1) & 1; - uint32_t imm3 = (raw >> 2) & 1; - uint32_t imm4 = (raw >> 3) & 1; - uint32_t imm5 = (raw >> 4) & 1; - uint32_t imm = (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); - return prefix + QString::number(imm); -} - -void GAParameterRiscvCLimm5::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 124 || (val & 3) != 0) { - op.goodasm->error("RISC-V CL imm5 is out of range (0 to 124, must be multiple of 4)."); - return; - } - - // Encode imm[6:2] into sequential raw bits (matching mask bit order) - // raw bit 0 = imm[6] - // raw bit 1 = imm[2] - // raw bit 2 = imm[3] - // raw bit 3 = imm[4] - // raw bit 4 = imm[5] - uint32_t imm = val; - uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 - ((imm >> 2) & 1) << 1 | // imm[2] -> raw bit 1 - ((imm >> 3) & 1) << 2 | // imm[3] -> raw bit 2 - ((imm >> 4) & 1) << 3 | // imm[4] -> raw bit 3 - ((imm >> 5) & 1) << 4; // imm[5] -> raw bit 4 - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V CS Format Immediate (imm[5:2]) parameter -// Encoding: Same as CL format -// Used in C.SW - -GAParameterRiscvCSimm5::GAParameterRiscvCSimm5(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCSimm5::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit unsigned 4-bit immediate, 4-byte aligned (imm[1:0] = 0) - // Range: 0, 4, 8, 12, ..., 124 (must be multiple of 4, 0-124) - if (val < 0 || val > 124 || (val & 3) != 0) { - op->goodasm->error("RISC-V CS imm5 is out of range (0 to 124, must be multiple of 4)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCSimm5::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // Mask "\x60\x1C" captures instruction bits [6:5], [12:10] - // rawdecode packs bits sequentially by mask position: - // raw bit 0 = instruction bit 5 = imm[6] - // raw bit 1 = instruction bit 6 = imm[2] - // raw bit 2 = instruction bit 10 = imm[3] - // raw bit 3 = instruction bit 11 = imm[4] - // raw bit 4 = instruction bit 12 = imm[5] - uint32_t imm6 = (raw >> 0) & 1; - uint32_t imm2 = (raw >> 1) & 1; - uint32_t imm3 = (raw >> 2) & 1; - uint32_t imm4 = (raw >> 3) & 1; - uint32_t imm5 = (raw >> 4) & 1; - uint32_t imm = (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | (imm3 << 3) | (imm2 << 2); - return prefix + QString::number(imm); -} - -void GAParameterRiscvCSimm5::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 124 || (val & 3) != 0) { - op.goodasm->error("RISC-V CS imm5 is out of range (0 to 124, must be multiple of 4)."); - return; - } - - // Encode imm[6:2] into sequential raw bits (matching mask bit order) - // raw bit 0 = imm[6] - // raw bit 1 = imm[2] - // raw bit 2 = imm[3] - // raw bit 3 = imm[4] - // raw bit 4 = imm[5] - uint32_t imm = val; - uint32_t raw = ((imm >> 6) & 1) << 0 | // imm[6] -> raw bit 0 - ((imm >> 2) & 1) << 1 | // imm[2] -> raw bit 1 - ((imm >> 3) & 1) << 2 | // imm[3] -> raw bit 2 - ((imm >> 4) & 1) << 3 | // imm[4] -> raw bit 3 - ((imm >> 5) & 1) << 4; // imm[5] -> raw bit 4 - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V CSS Format Immediate (imm[7:2]) parameter -// Encoding: imm[7:2] in bits [12:7] -// Used in C.SWSP - -GAParameterRiscvCSSimm7::GAParameterRiscvCSSimm7(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCSSimm7::match(GAParserOperand *op, int len){ - int64_t val=op->uint64(false); // False on a match - - // must fit unsigned 6-bit immediate, 4-byte aligned (imm[1:0] = 0) - // Range: 0, 4, 8, 12, ..., 252 (must be multiple of 4, 0-252) - if (val < 0 || val > 252 || (val & 3) != 0) { - op->goodasm->error("RISC-V CSS imm7 is out of range (0 to 252, must be multiple of 4)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCSSimm7::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // rawdecode with mask 0x80 0x1F extracts bits [12:7] in the order: - // Byte 1 (last): bits [12:8] (mask 0x1F = bits [4:0] of byte 1) - // Byte 0 (first): bit 7 (mask 0x80 = bit 7 of byte 0) - // rawdecode processes bits from highest byte to lowest, highest bit to lowest bit: - // Byte 1, bit 4 (bit 12) → raw bit 5 (MSB of imm[7:2]) - // Byte 1, bit 3 (bit 11) → raw bit 4 - // Byte 1, bit 2 (bit 10) → raw bit 3 - // Byte 1, bit 1 (bit 9) → raw bit 2 - // Byte 1, bit 0 (bit 8) → raw bit 1 - // Byte 0, bit 7 (bit 7) → raw bit 0 (LSB of imm[7:2]) - // So raw already contains imm[7:2] in the correct order! - uint32_t imm = raw << 2; // Shift left by 2 (imm[1:0] are always 0) - return prefix + QString::number(imm); -} - -void GAParameterRiscvCSSimm7::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.uint64(true); - - if (val < 0 || val > 252 || (val & 3) != 0) { - op.goodasm->error("RISC-V CSS imm7 is out of range (0 to 252, must be multiple of 4)."); - return; - } - - // Encode imm[7:2] into bits [12:7] - // rawencode processes bits from lowest bit to highest, placing them into mask positions - // in order (highest byte first, highest bit first): - // raw bit 0 → Byte 0, bit 7 (bit 7) - LSB - // raw bit 1 → Byte 1, bit 0 (bit 8) - // raw bit 2 → Byte 1, bit 1 (bit 9) - // raw bit 3 → Byte 1, bit 2 (bit 10) - // raw bit 4 → Byte 1, bit 3 (bit 11) - // raw bit 5 → Byte 1, bit 4 (bit 12) - MSB - // So raw should be imm[7:2] directly (no rearrangement needed) - uint32_t imm = (val >> 2) & 0x3F; // imm[7:2] - rawencode(lang,adr,bytes,op,inslen,imm); -} - -// RISC-V CB Format Immediate (imm[8|4:3|7:6|2:1|5]) parameter -// Encoding: Split across instruction bits -// Used in C.BEQZ, C.BNEZ - -GAParameterRiscvCBimm9::GAParameterRiscvCBimm9(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCBimm9::match(GAParserOperand *op, int len){ - // Accept any label or integer - range check will happen in encode with PC-relative calculation - // This allows labels to be matched and resolved during encoding - return 1; // valid -} - -QString GAParameterRiscvCBimm9::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // Mask 0x7C1C: inst[6:2] -> raw[4:0], inst[12:10] -> raw[7:5] - // CB format immediate mapping in instruction bits: - // inst[2]=imm[5], inst[3]=imm[1], inst[4]=imm[2], inst[5]=imm[6] - // inst[6]=imm[7], inst[10]=imm[3], inst[11]=imm[4], inst[12]=imm[8] - // So in raw: - // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[6] - // raw[4]=imm[7], raw[5]=imm[3], raw[6]=imm[4], raw[7]=imm[8] - int32_t imm1 = (raw >> 1) & 1; - int32_t imm2 = (raw >> 2) & 1; - int32_t imm3 = (raw >> 5) & 1; - int32_t imm4 = (raw >> 6) & 1; - int32_t imm5 = raw & 1; - int32_t imm6 = (raw >> 3) & 1; - int32_t imm7 = (raw >> 4) & 1; - int32_t imm8 = (raw >> 7) & 1; - int32_t imm = (imm8 << 8) | (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | - (imm4 << 4) | (imm3 << 3) | (imm2 << 2) | (imm1 << 1); - // Sign extend from 9 bits - if (imm & 0x100) { - imm |= ~0x1FF; - } - return prefix + QString::number(imm); -} - -void GAParameterRiscvCBimm9::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - // PC-relative addressing: calculate offset from current address - int64_t target = op.int64(true); - int64_t val = target - adr; // PC-relative offset - - // Range check: -256 to 254 bytes (signed 9-bit, even addresses only) - if (val < -256 || val > 254) { - op.goodasm->error("RISC-V CB imm9 is out of range (-256 to 254 bytes from PC)."); - return; - } - if ((val & 1) != 0) { - op.goodasm->error("RISC-V CB imm9 must be even (target address must be 2-byte aligned)."); - return; - } - - // Pack into raw in mask order: - // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[6] - // raw[4]=imm[7], raw[5]=imm[3], raw[6]=imm[4], raw[7]=imm[8] - uint32_t imm = val & 0x1FE; // imm[8:1], clear imm[0] - uint32_t raw = (((imm >> 5) & 1) << 0) | // imm[5] -> raw[0] - (((imm >> 1) & 1) << 1) | // imm[1] -> raw[1] - (((imm >> 2) & 1) << 2) | // imm[2] -> raw[2] - (((imm >> 6) & 1) << 3) | // imm[6] -> raw[3] - (((imm >> 7) & 1) << 4) | // imm[7] -> raw[4] - (((imm >> 3) & 1) << 5) | // imm[3] -> raw[5] - (((imm >> 4) & 1) << 6) | // imm[4] -> raw[6] - (((imm >> 8) & 1) << 7); // imm[8] -> raw[7] - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V CJ Format Immediate (imm[11|4|9:8|10|6|7|3:1|5]) parameter -// Encoding: Split across instruction bits -// Used in C.J - -GAParameterRiscvCJimm12::GAParameterRiscvCJimm12(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCJimm12::match(GAParserOperand *op, int len){ - // Accept any label or integer - range check will happen in encode with PC-relative calculation - // This allows labels to be matched and resolved during encoding - return 1; // valid -} - -QString GAParameterRiscvCJimm12::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - // Mask 0xFC1F: inst[7:2] -> raw[5:0], inst[12:8] -> raw[10:6] - // CJ format immediate mapping in instruction bits: - // inst[2]=imm[5], inst[3]=imm[1], inst[4]=imm[2], inst[5]=imm[3] - // inst[6]=imm[7], inst[7]=imm[6], inst[8]=imm[10], inst[9]=imm[9] - // inst[10]=imm[8], inst[11]=imm[4], inst[12]=imm[11] - // So in raw: - // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[3] - // raw[4]=imm[7], raw[5]=imm[6], raw[6]=imm[10], raw[7]=imm[9] - // raw[8]=imm[8], raw[9]=imm[4], raw[10]=imm[11] - int32_t imm1 = (raw >> 1) & 1; - int32_t imm2 = (raw >> 2) & 1; - int32_t imm3 = (raw >> 3) & 1; - int32_t imm4 = (raw >> 9) & 1; - int32_t imm5 = raw & 1; - int32_t imm6 = (raw >> 5) & 1; - int32_t imm7 = (raw >> 4) & 1; - int32_t imm8 = (raw >> 8) & 1; - int32_t imm9 = (raw >> 7) & 1; - int32_t imm10 = (raw >> 6) & 1; - int32_t imm11 = (raw >> 10) & 1; - int32_t imm = (imm11 << 11) | (imm10 << 10) | (imm9 << 9) | (imm8 << 8) | - (imm7 << 7) | (imm6 << 6) | (imm5 << 5) | (imm4 << 4) | - (imm3 << 3) | (imm2 << 2) | (imm1 << 1); - // Sign extend from 12 bits - if (imm & 0x800) { - imm |= ~0xFFF; - } - return prefix + QString::number(imm); -} - -void GAParameterRiscvCJimm12::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - // PC-relative addressing: calculate offset from current address - int64_t target = op.int64(true); - int64_t val = target - adr; // PC-relative offset - - // Range check: -2048 to 2046 bytes (signed 12-bit, even addresses only) - if (val < -2048 || val > 2046) { - op.goodasm->error("RISC-V CJ imm12 is out of range (-2048 to 2046 bytes from PC)."); - return; - } - if ((val & 1) != 0) { - op.goodasm->error("RISC-V CJ imm12 must be even (target address must be 2-byte aligned)."); - return; - } - - // Pack into raw in mask order: - // raw[0]=imm[5], raw[1]=imm[1], raw[2]=imm[2], raw[3]=imm[3] - // raw[4]=imm[7], raw[5]=imm[6], raw[6]=imm[10], raw[7]=imm[9] - // raw[8]=imm[8], raw[9]=imm[4], raw[10]=imm[11] - uint32_t imm = val & 0xFFE; // imm[11:1], clear imm[0] - uint32_t raw = (((imm >> 5) & 1) << 0) | // imm[5] -> raw[0] - (((imm >> 1) & 1) << 1) | // imm[1] -> raw[1] - (((imm >> 2) & 1) << 2) | // imm[2] -> raw[2] - (((imm >> 3) & 1) << 3) | // imm[3] -> raw[3] - (((imm >> 7) & 1) << 4) | // imm[7] -> raw[4] - (((imm >> 6) & 1) << 5) | // imm[6] -> raw[5] - (((imm >> 10) & 1) << 6) | // imm[10] -> raw[6] - (((imm >> 9) & 1) << 7) | // imm[9] -> raw[7] - (((imm >> 8) & 1) << 8) | // imm[8] -> raw[8] - (((imm >> 4) & 1) << 9) | // imm[4] -> raw[9] - (((imm >> 11) & 1) << 10); // imm[11] -> raw[10] - - rawencode(lang,adr,bytes,op,inslen,raw); -} - -// RISC-V CB Format Immediate for C.ANDI (imm[5:0]) parameter -// Encoding: Standard CB format: imm[5] in bit [12], imm[4:0] in bits [6:2] -// - imm[5] in bit [12] -// - imm[4:0] in bits [6:2] -// Note: bits [6:5] are part of the immediate encoding, not the opcode pattern -// Range: -32 to 31 (6-bit signed) - -GAParameterRiscvCBimm6Andi::GAParameterRiscvCBimm6Andi(const char* mask){ - setMask(mask); - prefix = "#"; -} - -int GAParameterRiscvCBimm6Andi::match(GAParserOperand *op, int len){ - int64_t val = op->int64(false); // False on a match - - // must fit signed 6-bit immediate (-32 to 31) - if (val < -32 || val > 31) { - op->goodasm->error("RISC-V CB imm6 (c.andi) is out of range (-32 to 31)"); - return 0; - } - - return 1; // valid -} - -QString GAParameterRiscvCBimm6Andi::decode(GALanguage *lang, uint64_t adr, const char *bytes, int inslen){ - uint64_t raw = rawdecode(lang,adr,bytes,inslen); - - // rawdecode extracts bits according to mask 0x7C10: - // - bits [6:2] from byte 0 → bits 0-4 of raw = imm[4:0] - // - bit [12] from byte 1 → bit 5 of raw = imm[5] - // So raw already has: imm[4:0] in bits 0-4, imm[5] in bit 5 - uint32_t imm5 = (raw >> 5) & 1; // bit 5 of raw = imm[5] - uint32_t imm4_0 = raw & 0x1F; // bits 0-4 of raw = imm[4:0] - - // Reconstruct imm[5:0] = imm[5] << 5 | imm[4:0] - uint32_t imm = (imm5 << 5) | imm4_0; - - // Sign extend from 6 bits - if (imm & 0x20) { - imm |= ~0x3F; - } - int32_t signed_imm = (int32_t)imm; - return prefix + QString::number(signed_imm); -} - -void GAParameterRiscvCBimm6Andi::encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ){ - int64_t val = op.int64(true); - - if (val < -32 || val > 31) { - op.goodasm->error("RISC-V CB imm6 (c.andi) is out of range (-32 to 31)."); - return; - } - - // Convert to 6-bit signed value - int32_t imm_signed = val & 0x3F; - if (imm_signed & 0x20) { - imm_signed |= ~0x3F; // Sign extend - } - - // Extract imm[5] and imm[4:0] as unsigned for encoding - // Mask 0x7C10 encodes: imm[4:0] in bits [6:2], imm[5] in bit [12] - // rawencode processes mask bits in order: first bits [6:2] (5 bits), then bit [12] (1 bit) - // So the raw value should have: imm[4:0] in bits 0-4, imm[5] in bit 5 - uint32_t imm = (uint32_t)(imm_signed & 0x3F); // Get 6-bit value as unsigned - uint32_t imm5 = (imm >> 5) & 1; - uint32_t imm4_0 = imm & 0x1F; - - // rawencode processes mask 0x7C10 in order: - // - Byte 0 bits [6:2] (5 bits) = imm[4:0] - // - Byte 1 bit [12] (1 bit) = imm[5] - // So raw value: imm[4:0] in lower 5 bits, imm[5] in bit 5 - uint32_t raw = imm4_0 | (imm5 << 5); - - rawencode(lang,adr,bytes,op,inslen,raw); } diff --git a/galangriscv.h b/galangriscv.h index e0cb4ea..1cb9701 100644 --- a/galangriscv.h +++ b/galangriscv.h @@ -1,341 +1,12 @@ -#include "galanguage.h" -#include "gaparameter.h" -#include "gamnemonic.h" +#ifndef GALANGRISCV_H +#define GALANGRISCV_H -class GALangRISCV : public GALanguage +#include "galangriscv32.h" + +class GALangRISCV : public GALangRISCV32 { public: GALangRISCV(); }; -class GAParameterRiscvReg : public GAParameter { - public: - GAParameterRiscvReg(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - - -class GAParameterRiscvImm12 : public GAParameter { -public: - GAParameterRiscvImm12(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvUtypeImm20 : public GAParameter { -public: - GAParameterRiscvUtypeImm20(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvBtypeImm13 : public GAParameter { -public: - GAParameterRiscvBtypeImm13(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvJtypeImm21 : public GAParameter { -public: - GAParameterRiscvJtypeImm21(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvStypeImm12 : public GAParameter { -public: - GAParameterRiscvStypeImm12(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvFencePredSucc : public GAParameter { -public: - GAParameterRiscvFencePredSucc(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvShamt5 : public GAParameter { -public: - GAParameterRiscvShamt5(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCsr12 : public GAParameter { -public: - GAParameterRiscvCsr12(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvUimm5 : public GAParameter { -public: - GAParameterRiscvUimm5(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -// C Extension parameter types for compressed 16-bit instructions - -class GAParameterRiscvCompReg : public GAParameter { -public: - GAParameterRiscvCompReg(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCIimm6 : public GAParameter { -public: - GAParameterRiscvCIimm6(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCIUimm6 : public GAParameter { -public: - GAParameterRiscvCIUimm6(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCIUimm6Srai : public GAParameter { -public: - GAParameterRiscvCIUimm6Srai(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCIimm7 : public GAParameter { -public: - GAParameterRiscvCIimm7(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCIWimm9 : public GAParameter { -public: - GAParameterRiscvCIWimm9(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCLimm5 : public GAParameter { -public: - GAParameterRiscvCLimm5(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCSimm5 : public GAParameter { -public: - GAParameterRiscvCSimm5(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCSSimm7 : public GAParameter { -public: - GAParameterRiscvCSSimm7(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCBimm9 : public GAParameter { -public: - GAParameterRiscvCBimm9(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCJimm12 : public GAParameter { -public: - GAParameterRiscvCJimm12(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; - -class GAParameterRiscvCBimm6Andi : public GAParameter { -public: - GAParameterRiscvCBimm6Andi(const char* mask); - int match(GAParserOperand *op, int len) override; - - QString decode(GALanguage *lang, uint64_t adr, - const char *bytes, int inslen) override; - - void encode(GALanguage *lang, - uint64_t adr, QByteArray &bytes, - GAParserOperand op, - int inslen - ) override; -}; \ No newline at end of file +#endif // GALANGRISCV_H diff --git a/galangriscv32.cpp b/galangriscv32.cpp index 9a66824..ee32a63 100644 --- a/galangriscv32.cpp +++ b/galangriscv32.cpp @@ -10,7 +10,7 @@ // https://msyksphinz-self.github.io/riscv-isadoc/ // Follow RISC-V Instruction Organization from the ISA Manual -GALangRISCV::GALangRISCV() { +GALangRISCV32::GALangRISCV32() { endian = LITTLE; name = "riscv32"; maxbytes = 4; // Maximum instruction length (32-bit or 16-bit compressed) diff --git a/galangriscv32.h b/galangriscv32.h index e0cb4ea..30cb971 100644 --- a/galangriscv32.h +++ b/galangriscv32.h @@ -1,11 +1,14 @@ +#ifndef GALANGRISCV32_H +#define GALANGRISCV32_H + #include "galanguage.h" #include "gaparameter.h" #include "gamnemonic.h" -class GALangRISCV : public GALanguage +class GALangRISCV32 : public GALanguage { public: - GALangRISCV(); + GALangRISCV32(); }; class GAParameterRiscvReg : public GAParameter { @@ -338,4 +341,6 @@ class GAParameterRiscvCBimm6Andi : public GAParameter { GAParserOperand op, int inslen ) override; -}; \ No newline at end of file +}; + +#endif // GALANGRISCV32_H \ No newline at end of file diff --git a/goodasm.cpp b/goodasm.cpp index e176b3a..c639d22 100644 --- a/goodasm.cpp +++ b/goodasm.cpp @@ -32,6 +32,7 @@ #include "galangtms320c28x.h" #include "galangti80.h" #include "galangriscv32.h" +#include "galangriscv.h" //Listings #include "galistingdefault.h" @@ -79,6 +80,7 @@ bool GoodASM::setLanguage(QString language){ languages.append(new GALangARM7TDMI()); languages.append(new GALangTMS320C28x()); languages.append(new GALangTI80()); + languages.append(new GALangRISCV32()); languages.append(new GALangRISCV()); } diff --git a/main.cpp b/main.cpp index 5c3e9d4..0ed1cf6 100644 --- a/main.cpp +++ b/main.cpp @@ -313,7 +313,7 @@ int main(int argc, char *argv[]){ else if(parser.isSet(langTI80)) language="ti80"; else if(parser.isSet(langRISCV)) - language="riscv32"; + language="riscv"; else if(parser.isSet(langRISCV32)) language="riscv32"; From 57af7c008a6b005369c65a5318de6ddadbdf2a96 Mon Sep 17 00:00:00 2001 From: Nick Peluso <10912027+nap32@users.noreply.github.com> Date: Mon, 16 Feb 2026 10:04:08 -0800 Subject: [PATCH 3/4] Self-test passes. --- galangriscv32.cpp | 339 ++++++++++++++++++++++++++-------------------- 1 file changed, 189 insertions(+), 150 deletions(-) diff --git a/galangriscv32.cpp b/galangriscv32.cpp index ee32a63..f7dcbe3 100644 --- a/galangriscv32.cpp +++ b/galangriscv32.cpp @@ -787,19 +787,23 @@ GALangRISCV32::GALangRISCV32() { mnem("fence", 4, "\x0F\x00\xF0\x0F", // pattern 32-bit LE: 0x0FF0000F (fence iorw, iorw) "\xFF\xFF\xFF\xFF")) // exact match - no variable bits + ->prioritize() // Wins over parameterized fence during disassembly ->help("Memory Ordering Fence (full barrier): fence iorw, iorw") ->example("fence"); // Fence with explicit pred/succ and registers - insert( - mnem("fence", 4, - "\x0F\x00\x00\x00", // pattern 32-bit LE: 0x0000000F - "\x7F\x70\x00\x00")) // mask: opcode + funct3 - ->help("Memory Ordering Fence: orders memory operations") - ->example("fence #0xFF, zero, zero") - ->insert(new GAParameterRiscvFencePredSucc("\x00\x00\xF0\x0F")) // pred/succ in imm[7:0] - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")) // RS1: bits [19:15] (typically zero) - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] (typically zero) + { + auto m = mnem("fence", 4, + "\x0F\x00\x00\x00", // pattern 32-bit LE: 0x0000000F + "\x7F\x70\x00\x00"); // mask: opcode + funct3 + m->help("Memory Ordering Fence: orders memory operations"); + m->example("fence #0xFF, zero, zero"); + m->insert(new GAParameterRiscvFencePredSucc("\x00\x00\xF0\x0F")); // pred/succ in imm[7:0] + m->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] (typically zero) + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] (typically zero) + m->dontcare("\x00\x00\x00\xF0"); // fm field (bits [31:28]) - fence mode, not used in standard fence + insert(m); + } /* * Example: FENCE.I @@ -815,7 +819,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fence.i", 4, "\x0F\x10\x00\x00", // pattern 32-bit LE: 0x0000100F - "\x7F\x70\x00\x00")) // mask: opcode + funct3 + "\xFF\xFF\xFF\xFF")) // exact match - no variable bits (imm, rs1, rd all zero per spec) ->help("Instruction Fence: synchronizes instruction and data streams") ->example("fence.i"); @@ -836,25 +840,24 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("ecall", 4, "\x73\x00\x00\x00", // pattern 32-bit LE: 0x00000073 - "\x7F\x70\x10\x00")) // mask: opcode + funct3 + imm[0] (bit 20 = byte 2 bit 4, must be 0) + "\xFF\xFF\xFF\xFF")) // exact match - no variable bits (all fields zero per spec) ->help("Environment Call: makes a request to the execution environment") ->example("ecall"); /* * Example: EBREAK - * + * * Encoding: * imm[11:0] rs1 funct3 rd opcode * - * Mask : 0x0000707F (mask funct3 + opcode) * Value : 0x00100073 (funct3=000 + opcode=0x73 + imm[0]=1) - * + * * imm[0]=1 (bit 20), all other fields except funct3 and opcode are zero */ insert( mnem("ebreak", 4, "\x73\x00\x10\x00", // pattern 32-bit LE: 0x00100073 (imm[0]=1 in bit 20) - "\x7F\x70\x10\x00")) // mask: opcode + funct3 + imm[0] (bit 20 = byte 2 bit 4) + "\xFF\xFF\xFF\xFF")) // exact match - no variable bits (all fields zero per spec) ->help("Environment Break: causes a breakpoint exception") ->example("ebreak"); @@ -1028,15 +1031,18 @@ GALangRISCV32::GALangRISCV32() { * rl = 0 in bit [25] * rs2 = 00000 (reserved, must be zero) in bits [24:20] */ - insert( - mnem("lr.w", 4, - "\x2F\x20\x00\x10", // pattern 32-bit LE: 0x1000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 (aq/rl default to 0) - ->help("Load Reserved Word: rd = M[rs1]; reserve address") - ->example("lr.w a0, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("lr.w", 4, + "\x2F\x20\x00\x10", // pattern 32-bit LE: 0x1000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Load Reserved Word: rd = M[rs1]; reserve address"); + m->example("lr.w a0, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\xF0\x07"); // rs2[4:0] + aq + rl (bits [26:20]) unused in lr.w + insert(m); + } /* * Example: SC.W rd, rs2, (rs1) @@ -1047,16 +1053,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0x1800202F (funct5=00011, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("sc.w", 4, - "\x2F\x20\x00\x18", // pattern 32-bit LE: 0x1800202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Store Conditional Word: if reserved, M[rs1] = rs2, rd = 0; else rd != 0") - ->example("sc.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("sc.w", 4, + "\x2F\x20\x00\x18", // pattern 32-bit LE: 0x1800202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Store Conditional Word: if reserved, M[rs1] = rs2, rd = 0; else rd != 0"); + m->example("sc.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOSWAP.W rd, rs2, (rs1) @@ -1067,16 +1076,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0x0800202F (funct5=00001, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amoswap.w", 4, - "\x2F\x20\x00\x08", // pattern 32-bit LE: 0x0800202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Swap Word: temp = M[rs1]; M[rs1] = rs2; rd = temp") - ->example("amoswap.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amoswap.w", 4, + "\x2F\x20\x00\x08", // pattern 32-bit LE: 0x0800202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory Swap Word: temp = M[rs1]; M[rs1] = rs2; rd = temp"); + m->example("amoswap.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOADD.W rd, rs2, (rs1) @@ -1087,16 +1099,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0x0000202F (funct5=00000, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amoadd.w", 4, - "\x2F\x20\x00\x00", // pattern 32-bit LE: 0x0000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Add Word: temp = M[rs1]; M[rs1] = temp + rs2; rd = temp") - ->example("amoadd.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amoadd.w", 4, + "\x2F\x20\x00\x00", // pattern 32-bit LE: 0x0000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory Add Word: temp = M[rs1]; M[rs1] = temp + rs2; rd = temp"); + m->example("amoadd.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOXOR.W rd, rs2, (rs1) @@ -1107,16 +1122,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0x2000202F (funct5=00100, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amoxor.w", 4, - "\x2F\x20\x00\x20", // pattern 32-bit LE: 0x2000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory XOR Word: temp = M[rs1]; M[rs1] = temp ^ rs2; rd = temp") - ->example("amoxor.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amoxor.w", 4, + "\x2F\x20\x00\x20", // pattern 32-bit LE: 0x2000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory XOR Word: temp = M[rs1]; M[rs1] = temp ^ rs2; rd = temp"); + m->example("amoxor.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOAND.W rd, rs2, (rs1) @@ -1127,16 +1145,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0x6000202F (funct5=01100, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amoand.w", 4, - "\x2F\x20\x00\x60", // pattern 32-bit LE: 0x6000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory AND Word: temp = M[rs1]; M[rs1] = temp & rs2; rd = temp") - ->example("amoand.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amoand.w", 4, + "\x2F\x20\x00\x60", // pattern 32-bit LE: 0x6000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory AND Word: temp = M[rs1]; M[rs1] = temp & rs2; rd = temp"); + m->example("amoand.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOOR.W rd, rs2, (rs1) @@ -1147,16 +1168,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0x4000202F (funct5=01000, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amoor.w", 4, - "\x2F\x20\x00\x40", // pattern 32-bit LE: 0x4000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory OR Word: temp = M[rs1]; M[rs1] = temp | rs2; rd = temp") - ->example("amoor.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amoor.w", 4, + "\x2F\x20\x00\x40", // pattern 32-bit LE: 0x4000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory OR Word: temp = M[rs1]; M[rs1] = temp | rs2; rd = temp"); + m->example("amoor.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOMIN.W rd, rs2, (rs1) @@ -1167,16 +1191,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0x8000202F (funct5=10000, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amomin.w", 4, - "\x2F\x20\x00\x80", // pattern 32-bit LE: 0x8000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Minimum Word (signed): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp") - ->example("amomin.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amomin.w", 4, + "\x2F\x20\x00\x80", // pattern 32-bit LE: 0x8000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory Minimum Word (signed): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp"); + m->example("amomin.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOMAX.W rd, rs2, (rs1) @@ -1187,16 +1214,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0xA000202F (funct5=10100, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amomax.w", 4, - "\x2F\x20\x00\xA0", // pattern 32-bit LE: 0xA000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Maximum Word (signed): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp") - ->example("amomax.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amomax.w", 4, + "\x2F\x20\x00\xA0", // pattern 32-bit LE: 0xA000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory Maximum Word (signed): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp"); + m->example("amomax.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOMINU.W rd, rs2, (rs1) @@ -1207,16 +1237,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0xC000202F (funct5=11000, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amominu.w", 4, - "\x2F\x20\x00\xC0", // pattern 32-bit LE: 0xC000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Minimum Word (unsigned): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp") - ->example("amominu.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amominu.w", 4, + "\x2F\x20\x00\xC0", // pattern 32-bit LE: 0xC000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory Minimum Word (unsigned): temp = M[rs1]; M[rs1] = min(temp, rs2); rd = temp"); + m->example("amominu.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* * Example: AMOMAXU.W rd, rs2, (rs1) @@ -1227,16 +1260,19 @@ GALangRISCV32::GALangRISCV32() { * Mask : 0xF8F0707F (mask funct5 + aq + rl + funct3 + opcode) * Value : 0xE000202F (funct5=11100, aq=0, rl=0, funct3=010, opcode=0x2F) */ - insert( - mnem("amomaxu.w", 4, - "\x2F\x20\x00\xE0", // pattern 32-bit LE: 0xE000202F - "\x7F\x70\x00\xF8")) // mask: opcode + funct3 + funct5 - ->help("Atomic Memory Maximum Word (unsigned): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp") - ->example("amomaxu.w a0, a2, (a1)") - ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] - ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - ->group('(') // (rs1) group - ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + { + auto m = mnem("amomaxu.w", 4, + "\x2F\x20\x00\xE0", // pattern 32-bit LE: 0xE000202F + "\x7F\x70\x00\xF8"); // mask: opcode + funct3 + funct5 + m->help("Atomic Memory Maximum Word (unsigned): temp = M[rs1]; M[rs1] = max(temp, rs2); rd = temp"); + m->example("amomaxu.w a0, a2, (a1)"); + m->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")); // RD: bits [11:7] + m->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")); // RS2: bits [24:20] + m->group('(') // (rs1) group + ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] + m->dontcare("\x00\x00\x00\x06"); // aq + rl (bits [26:25]) unused + insert(m); + } /* ZICSR Instructions Extension */ @@ -1405,7 +1441,7 @@ GALangRISCV32::GALangRISCV32() { ->example("fsw f0, (#4, a1)") ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] ->group('(') // (rs1) group - ->insert(new GAParameterRiscvStypeImm12("\x00\x00\xF0\xFE")) // imm[11:0]: split encoding + ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] /* @@ -1576,7 +1612,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fsqrt.s", 4, "\x53\x00\x00\x58", // pattern 32-bit LE: 0x58000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Square Root: rd = sqrt(rs1)") ->example("fsqrt.s f0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -1746,7 +1782,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.w.s", 4, "\x53\x00\x00\xC0", // pattern 32-bit LE: 0xC0000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert to Word: rd = (int32_t)rs1") ->example("fcvt.w.s a0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -1764,7 +1800,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.wu.s", 4, "\x53\x10\x00\xC0", // pattern 32-bit LE: 0xC0001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert to Word Unsigned: rd = (uint32_t)rs1") ->example("fcvt.wu.s a0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -1782,7 +1818,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.s.w", 4, "\x53\x00\x00\xD0", // pattern 32-bit LE: 0xD0000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert from Word: rd = (float)rs1") ->example("fcvt.s.w f0, a1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -1800,7 +1836,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.s.wu", 4, "\x53\x10\x00\xD0", // pattern 32-bit LE: 0xD0001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert from Word Unsigned: rd = (float)(uint32_t)rs1") ->example("fcvt.s.wu f0, a1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -1818,7 +1854,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fmv.x.w", 4, "\x53\x00\x00\xE0", // pattern 32-bit LE: 0xE0000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Move to Integer: rd = rs1 (bitwise copy)") ->example("fmv.x.w a0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -1836,7 +1872,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fmv.w.x", 4, "\x53\x00\x00\xF0", // pattern 32-bit LE: 0xF0000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Move from Integer: rd = rs1 (bitwise copy)") ->example("fmv.w.x f0, a1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -1854,7 +1890,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fclass.s", 4, "\x53\x10\x00\xE0", // pattern 32-bit LE: 0xE0001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Classify: rd = classification bits for rs1") ->example("fclass.s a0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -1899,7 +1935,7 @@ GALangRISCV32::GALangRISCV32() { ->example("fsd f0, (#8, a1)") ->insert(new GAParameterRiscvReg("\x00\x00\xF0\x01")) // RS2: bits [24:20] - byte 2 bits [7:4] + byte 3 bit [0] ->group('(') // (rs1) group - ->insert(new GAParameterRiscvStypeImm12("\x00\x00\xF0\xFE")) // imm[11:0]: split encoding + ->insert(new GAParameterRiscvStypeImm12("\x80\x0F\x00\xFE")) // imm[11:0] split encoding ->insert(new GAParameterRiscvReg("\x00\x80\x0F\x00")); // RS1: bits [19:15] /* @@ -2070,7 +2106,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fsqrt.d", 4, "\x53\x00\x00\x5A", // pattern 32-bit LE: 0x5A000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Square Root Double: rd = sqrt(rs1)") ->example("fsqrt.d f0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -2183,7 +2219,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.s.d", 4, "\x53\x00\x00\x40", // pattern 32-bit LE: 0x40000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert Single from Double: rd = (float)rs1") ->example("fcvt.s.d f0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -2201,7 +2237,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.d.s", 4, "\x53\x00\x00\x42", // pattern 32-bit LE: 0x42000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert Double from Single: rd = (double)rs1") ->example("fcvt.d.s f0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -2276,7 +2312,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.w.d", 4, "\x53\x00\x00\xC2", // pattern 32-bit LE: 0xC2000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert to Word from Double: rd = (int32_t)rs1") ->example("fcvt.w.d a0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -2294,7 +2330,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.wu.d", 4, "\x53\x10\x00\xC2", // pattern 32-bit LE: 0xC2001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert to Word Unsigned from Double: rd = (uint32_t)rs1") ->example("fcvt.wu.d a0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -2312,7 +2348,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.d.w", 4, "\x53\x00\x00\xD2", // pattern 32-bit LE: 0xD2000053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert from Word to Double: rd = (double)rs1") ->example("fcvt.d.w f0, a1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -2330,7 +2366,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fcvt.d.wu", 4, "\x53\x10\x00\xD2", // pattern 32-bit LE: 0xD2001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Convert from Word Unsigned to Double: rd = (double)(uint32_t)rs1") ->example("fcvt.d.wu f0, a1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -2348,7 +2384,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("fclass.d", 4, "\x53\x10\x00\xE2", // pattern 32-bit LE: 0xE2001053 - "\x7F\x70\x00\xFF")) // mask: opcode + funct3 + funct7 + rs2 + "\x7F\x70\xF0\xFF")) // mask: opcode + funct3 + funct7 + rs2[4:0] ->help("Floating-Point Classify Double: rd = classification bits for rs1") ->example("fclass.d a0, f1") ->insert(new GAParameterRiscvReg("\x80\x0F\x00\x00")) // RD: bits [11:7] @@ -2419,7 +2455,7 @@ GALangRISCV32::GALangRISCV32() { insert( mnem("c.nop", 2, "\x01\x00", // pattern 16-bit LE: bits [1:0]=01, [15:13]=000, rd=0 - "\x83\xEF")) // mask: opcode + rd (byte0: bits [7] and [1:0]=0x83, byte1: bits [15:13] and [11:8]=0xEF) + "\xFF\xFF")) // exact match - no variable bits (imm=0, rd=0 per spec) ->help("Compressed No Operation") ->example("c.nop"); @@ -2468,6 +2504,7 @@ GALangRISCV32::GALangRISCV32() { mnem("c.addi16sp", 2, "\x01\x61", // pattern 16-bit LE: bits [1:0]=01, [15:13]=011, rd=2 (bits [11:8]=0001, bit [7]=0) "\x83\xEF")) // mask: opcode + rd (byte0: bits [7] and [1:0]=0x83, byte1: bits [15:13] and [11:8]=0xEF) + ->prioritize() // More specific than c.lui (mask checks rd=2) ->help("Compressed Add Immediate to SP: sp = sp + (imm << 4)") ->example("c.addi16sp #-32") ->insert(new GAParameterRiscvCIimm6("\x7C\x10")); // imm[9|4|6|8:7|5]: split encoding (special format) - same mask as CI but different encoding logic @@ -2519,8 +2556,9 @@ GALangRISCV32::GALangRISCV32() { mnem("c.ebreak", 2, "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=001, rd=0, rs1=0 "\xFF\xFF")) // mask: all bits (0xFFFF) - c.ebreak is an exact encoding with rd=0, rs2=0 - // Removed priority - full mask 0xFFFF ensures c.ebreak matches only its exact encoding 0x9002 - ->help("Compressed Environment Break"); + ->prioritize() // Exact match wins over c.add/c.jalr + ->help("Compressed Environment Break") + ->example("c.ebreak"); /* * C.ANDI - Compressed AND Immediate @@ -2590,6 +2628,7 @@ GALangRISCV32::GALangRISCV32() { "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1001 (funct4), [6:2]=00000 (rs2=0) "\x7F\xF0")) // mask: bits [6:0] in byte 0 (check rs2=0, op=10), bits [15:12] in byte 1 (check funct4) ->rejectWhenZero("\x80\x0F") // rs1 (bits [11:7]) must be non-zero + ->prioritize() // More specific than c.add (mask checks rs2=0) ->help("Compressed Jump and Link Register: ra = pc + 2; pc = rs1") ->example("c.jalr a0") ->insert(new GAParameterRiscvReg("\x80\x0F")); // rs1: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 @@ -2604,7 +2643,7 @@ GALangRISCV32::GALangRISCV32() { mnem("c.sub", 2, "\x02\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=00 "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 - // Removed priority - mask correctly checks [6:5]=00 to distinguish from other CA format instructions + ->prioritize() // More specific than c.mv (mask checks funct6+funct2) ->help("Compressed Subtract: rd' = rd' - rs2'") ->example("c.sub a0, a1") ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 @@ -2620,7 +2659,7 @@ GALangRISCV32::GALangRISCV32() { mnem("c.xor", 2, "\x22\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=01 "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 - // Removed priority - mask correctly checks [6:5]=01 to distinguish from other CA format instructions + ->prioritize() // More specific than c.mv (mask checks funct6+funct2) ->help("Compressed XOR: rd' = rd' ^ rs2'") ->example("c.xor a0, a1") ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 @@ -2636,7 +2675,7 @@ GALangRISCV32::GALangRISCV32() { mnem("c.or", 2, "\x42\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=10 "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 - // Removed priority - mask correctly checks [6:5]=10 to distinguish from other CA format instructions + ->prioritize() // More specific than c.mv (mask checks funct6+funct2) ->help("Compressed OR: rd' = rd' | rs2'") ->example("c.or a0, a1") ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 @@ -2652,7 +2691,7 @@ GALangRISCV32::GALangRISCV32() { mnem("c.and", 2, "\x62\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=11 "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 - // Removed priority - mask correctly checks [6:5]=11 to distinguish from other CA format instructions + ->prioritize() // More specific than c.mv (mask checks funct6+funct2) ->help("Compressed AND: rd' = rd' & rs2'") ->example("c.and a0, a1") ->insert(new GAParameterRiscvCompReg("\x80\x03")) // rd': bits [9:7] - bit [7] from byte 0, bits [9:8] from byte 1 @@ -2766,7 +2805,7 @@ GALangRISCV32::GALangRISCV32() { mnem("c.add", 2, "\x02\x90", // pattern 16-bit LE: bits [1:0]=10, [15:12]=1001 (funct4), rd=0 (template) "\x03\xF0")) // mask: bits [1:0] + [15:12] = 0x03 in byte 0, 0xF0 in byte 1 (don't check rd or rs2) - // Removed priority - c.ebreak (inserted before this) has more specific mask (0x03FF) and will match first + ->rejectWhenZero("\x7C\x00") // rs2 (bits [6:2]) must be non-zero (rs2=0 is c.jalr or c.ebreak) ->help("Compressed Add: rd = rd + rs2") ->example("c.add a0, a1") ->insert(new GAParameterRiscvReg("\x80\x0F")) // rd: bits [11:7] - bit [7] from byte 0, bits [11:8] from byte 1 From 5b2edbf732d4fbdd243cd236cf71f99039348535 Mon Sep 17 00:00:00 2001 From: Nick Peluso <10912027+nap32@users.noreply.github.com> Date: Tue, 17 Feb 2026 18:29:58 -0800 Subject: [PATCH 4/4] Fix compressed instruction issues cjr and cmv still had a few failures when invoking test_all_riscv_parallel.sh - addressed through exact matches and ignore/reject semantic expressions. --- galangriscv32.cpp | 32 +++++------ tests/riscv/c-extension/c.addi16sp.disasm | 36 ------------ tests/riscv/c-extension/c.ebreak.disasm | 9 --- tests/riscv/c-extension/c.jalr.disasm | 27 --------- tests/riscv/c-extension/c_addi16sp.disasm | 9 --- tests/riscv/c-extension/c_ebreak.disasm | 9 --- tests/riscv/c-extension/c_jalr.disasm | 9 --- .../c-extension/c_jalr_edge_cases.disasm | 57 ------------------- tests/riscv/rv32i/fence.disasm | 3 - 9 files changed, 16 insertions(+), 175 deletions(-) diff --git a/galangriscv32.cpp b/galangriscv32.cpp index f7dcbe3..2b8de1b 100644 --- a/galangriscv32.cpp +++ b/galangriscv32.cpp @@ -2636,13 +2636,13 @@ GALangRISCV32::GALangRISCV32() { /* * C.SUB - Compressed Subtract * Format: CA - * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|00|10 - * Opcode: 0x8C02 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 00) + * Encoding: 100011|rd'[2:0]|00|rs2'[2:0]|01 + * Opcode: 0x8C01 (bits [1:0] = 01 (Q1), bits [15:10] = 100011 (funct6), bits [6:5] = 00 (funct2)) */ insert( mnem("c.sub", 2, - "\x02\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=00 - "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + "\x01\x8C", // pattern 16-bit LE: bits [1:0]=01 (Q1), [15:10]=100011 (funct6), [6:5]=00 (funct2) + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:10] = 0x63 in byte 0, 0xFC in byte 1 ->prioritize() // More specific than c.mv (mask checks funct6+funct2) ->help("Compressed Subtract: rd' = rd' - rs2'") ->example("c.sub a0, a1") @@ -2652,13 +2652,13 @@ GALangRISCV32::GALangRISCV32() { /* * C.XOR - Compressed XOR * Format: CA - * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|01|10 - * Opcode: 0x8C22 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 01) + * Encoding: 100011|rd'[2:0]|01|rs2'[2:0]|01 + * Opcode: 0x8C21 (bits [1:0] = 01 (Q1), bits [15:10] = 100011 (funct6), bits [6:5] = 01 (funct2)) */ insert( mnem("c.xor", 2, - "\x22\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=01 - "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + "\x21\x8C", // pattern 16-bit LE: bits [1:0]=01 (Q1), [15:10]=100011 (funct6), [6:5]=01 (funct2) + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:10] = 0x63 in byte 0, 0xFC in byte 1 ->prioritize() // More specific than c.mv (mask checks funct6+funct2) ->help("Compressed XOR: rd' = rd' ^ rs2'") ->example("c.xor a0, a1") @@ -2668,13 +2668,13 @@ GALangRISCV32::GALangRISCV32() { /* * C.OR - Compressed OR * Format: CA - * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|10|10 - * Opcode: 0x8C42 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 10) + * Encoding: 100011|rd'[2:0]|10|rs2'[2:0]|01 + * Opcode: 0x8C41 (bits [1:0] = 01 (Q1), bits [15:10] = 100011 (funct6), bits [6:5] = 10 (funct2)) */ insert( mnem("c.or", 2, - "\x42\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=10 - "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + "\x41\x8C", // pattern 16-bit LE: bits [1:0]=01 (Q1), [15:10]=100011 (funct6), [6:5]=10 (funct2) + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:10] = 0x63 in byte 0, 0xFC in byte 1 ->prioritize() // More specific than c.mv (mask checks funct6+funct2) ->help("Compressed OR: rd' = rd' | rs2'") ->example("c.or a0, a1") @@ -2684,13 +2684,13 @@ GALangRISCV32::GALangRISCV32() { /* * C.AND - Compressed AND * Format: CA - * Encoding: 100|rs2'[2:0]|rs2'[2:0]|11|rd'[2:0]|11|10 - * Opcode: 0x8C62 (bits [1:0] = 10, bits [15:13] = 100, bits [12:10] = 111, bits [6:5] = 11) + * Encoding: 100011|rd'[2:0]|11|rs2'[2:0]|01 + * Opcode: 0x8C61 (bits [1:0] = 01 (Q1), bits [15:10] = 100011 (funct6), bits [6:5] = 11 (funct2)) */ insert( mnem("c.and", 2, - "\x62\x8C", // pattern 16-bit LE: bits [1:0]=10, [15:13]=100, [12:10]=111, [6:5]=11 - "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:13] + [12:10] = 0x63 in byte 0, 0xFC in byte 1 + "\x61\x8C", // pattern 16-bit LE: bits [1:0]=01 (Q1), [15:10]=100011 (funct6), [6:5]=11 (funct2) + "\x63\xFC")) // mask: bits [1:0] + [6:5] + [15:10] = 0x63 in byte 0, 0xFC in byte 1 ->prioritize() // More specific than c.mv (mask checks funct6+funct2) ->help("Compressed AND: rd' = rd' & rs2'") ->example("c.and a0, a1") diff --git a/tests/riscv/c-extension/c.addi16sp.disasm b/tests/riscv/c-extension/c.addi16sp.disasm index 51bb5f0..34f8286 100644 --- a/tests/riscv/c-extension/c.addi16sp.disasm +++ b/tests/riscv/c-extension/c.addi16sp.disasm @@ -1,39 +1,3 @@ -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" c.addi16sp #-512 c.addi16sp #-256 c.addi16sp #-128 diff --git a/tests/riscv/c-extension/c.ebreak.disasm b/tests/riscv/c-extension/c.ebreak.disasm index d1cda2d..5d4005f 100644 --- a/tests/riscv/c-extension/c.ebreak.disasm +++ b/tests/riscv/c-extension/c.ebreak.disasm @@ -1,10 +1 @@ -Colliding matches: "c.ebreak c.add " -1: "c.ebreak" -2: "c.add a0, a1" -Colliding matches: "c.ebreak c.add " -1: "c.ebreak" -2: "c.add a0, a1" -Colliding matches: "c.ebreak c.add " -1: "c.ebreak" -2: "c.add a0, a1" c.ebreak diff --git a/tests/riscv/c-extension/c.jalr.disasm b/tests/riscv/c-extension/c.jalr.disasm index 024cc30..2f32f5d 100644 --- a/tests/riscv/c-extension/c.jalr.disasm +++ b/tests/riscv/c-extension/c.jalr.disasm @@ -1,30 +1,3 @@ -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" c.jalr ra c.jalr t0 c.jalr a0 diff --git a/tests/riscv/c-extension/c_addi16sp.disasm b/tests/riscv/c-extension/c_addi16sp.disasm index 0942c5d..72ffe43 100644 --- a/tests/riscv/c-extension/c_addi16sp.disasm +++ b/tests/riscv/c-extension/c_addi16sp.disasm @@ -1,10 +1 @@ -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" -Colliding matches: "c.addi16sp c.lui " -1: "c.addi16sp #-32" -2: "c.lui a0, #0x10000" c.addi16sp #-32 diff --git a/tests/riscv/c-extension/c_ebreak.disasm b/tests/riscv/c-extension/c_ebreak.disasm index d1cda2d..5d4005f 100644 --- a/tests/riscv/c-extension/c_ebreak.disasm +++ b/tests/riscv/c-extension/c_ebreak.disasm @@ -1,10 +1 @@ -Colliding matches: "c.ebreak c.add " -1: "c.ebreak" -2: "c.add a0, a1" -Colliding matches: "c.ebreak c.add " -1: "c.ebreak" -2: "c.add a0, a1" -Colliding matches: "c.ebreak c.add " -1: "c.ebreak" -2: "c.add a0, a1" c.ebreak diff --git a/tests/riscv/c-extension/c_jalr.disasm b/tests/riscv/c-extension/c_jalr.disasm index 1cd5a45..dbeb4d9 100644 --- a/tests/riscv/c-extension/c_jalr.disasm +++ b/tests/riscv/c-extension/c_jalr.disasm @@ -1,10 +1 @@ -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" c.jalr a0 diff --git a/tests/riscv/c-extension/c_jalr_edge_cases.disasm b/tests/riscv/c-extension/c_jalr_edge_cases.disasm index da8cda6..1604962 100644 --- a/tests/riscv/c-extension/c_jalr_edge_cases.disasm +++ b/tests/riscv/c-extension/c_jalr_edge_cases.disasm @@ -1,60 +1,3 @@ -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" -Colliding matches: "c.jalr c.add " -1: "c.jalr a0" -2: "c.add a0, a1" c.jalr a0 c.jalr a1 c.jalr a2 diff --git a/tests/riscv/rv32i/fence.disasm b/tests/riscv/rv32i/fence.disasm index 63ed775..81f587e 100644 --- a/tests/riscv/rv32i/fence.disasm +++ b/tests/riscv/rv32i/fence.disasm @@ -1,6 +1,3 @@ -Colliding matches: "fence fence " -1: "fence" -2: "fence #0xFF, zero, zero" fence #0x00, zero, zero fence #0x0F, zero, zero fence