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openroad
Here are 45 public repositories matching this topic...
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Dec 13, 2024 - Verilog
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds
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Oct 20, 2024 - Python
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Dec 12, 2024 - Verilog
Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.
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Nov 28, 2024 - Python
7 track standard cells for GF180MCU provided by GlobalFoundries.
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Dec 1, 2022 - Verilog
9 track standard cells for GF180MCU provided by GlobalFoundries.
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Dec 5, 2022 - Verilog
"High density" digital standard cells for SKY130 provided by SkyWater.
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Feb 22, 2023 - Verilog
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
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Jul 7, 2021
The source code that empowers OpenROAD Cloud
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Jun 29, 2020
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Feb 22, 2024 - Verilog
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