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The **Visual Layout Inference** tool automatically generates visual diagrams that illustrate the mapping between logical indices, thread IDs, and register file locations.
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When TileLang performs layout inference, it determines how fragment buffers are distributed across threads. The visual layout tool captures this information and generates:
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1. **Textual output**: A human-readable description of the layout mapping
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2. **Visual diagrams**: Color-coded plots showing the thread-to-data mapping
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The visual layout inference tool is controlled through the `TL_LAYOUT_VISUALIZATION_ENABLE` and `TL_LAYOUT_VISUALIZATION_FORMATS` pass configuration. By default, `TL_LAYOUT_VISUALIZATION_ENABLE` is **disabled** to avoid performance overhead during compilation.
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When enabled, `TL_LAYOUT_VISUALIZATION_FORMATS` accepts string values to control output formats:
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- "txt": Text output only (same as default)
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- "all": Generates all formats (TXT, PDF, PNG, SVG)
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- "png": Generate PNG format only
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- "pdf": Generate PDF format only
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- "svg": Generate SVG format only
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- "txt,svg": Generate multiple formats (comma-separated) in addition to text output
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The output messages of "txt" will include something like:
By carefully examining intermediate representations (IR) before final code generation—and by leveraging runtime printing through `T.print`—one can quickly diagnose where index calculations, copy logic, or other kernel operations deviate from the intended behavior. This two-pronged approach (inspecting IR transformations and using runtime prints) is often sufficient for resolving generation and correctness issues in TileLang programs.
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