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Mark1626Quasorglow
Mark1626
and
Quasorglow
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feat: Add Calyx bindings (#11)
Co-authored-by: Swethaa <[email protected]>
1 parent 9605ec0 commit 86f143b

25 files changed

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-21
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‎.gitignore

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@@ -14,3 +14,7 @@ test-*/
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test_generator/build
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PositTestGenerator
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lib/P16
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lib/P32
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lib/P64
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lib/posit_*.sv

‎Makefile

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@@ -84,7 +84,7 @@ P64toP32 \
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define test_template
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test-$(1)/Eval_$(1).v: src/main/scala/*.scala
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sbt "run $(1) -td test-$(1)"
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sbt "run tb $(1) -td test-$(1)"
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test-$(1)/dut.mk: test-$(1)/Eval_$(1).v
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$(VERILATOR) -cc --prefix dut --Mdir test-$(1) -CFLAGS "$(VERILATOR_CFLAGS) -include ../csrc/test-$(1).h" test-$(1)/Eval_Posit$(1).v --exe csrc/test-$(3).cpp

‎README.md

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@@ -21,6 +21,12 @@ For more information about Universal numbers and Posit arithmetic and to follow
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[Posit Hub] \
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[Unum-computing Google group]
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## Calyx Binding
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Calyx is an infrastructure for accelerator design. This repo has bindings for Calyx Native. These bindings can allow Posit arithmetic for Calyx frontends such as Dahlia.
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More information about the Calyx binding and it's usage is in the [lib directory](./lib/README.md)
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## Unit Testing
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The posit arithmetic modules have been unit tested using Chisel IO testers. For better coverage a random test generator is also available enabled by the [universal] C++ template library. The test generator supplies tests to the hardware units which are simulated using [verilator].

‎lib/Makefile

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all: posit_16.sv posit_32.sv posit_64.sv
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posit_%.sv: P%
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rm -f $@
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cat $</*.sv > $@
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.PHONY = posit_16.sv posit_32.sv posit_64.sv

‎lib/README.md

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# Calyx Bindings for Hardposit
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## Build Instructions
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1. To generate the System Verilog from the Chisel modules, from the root folder run
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```
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# From the root folder of the project
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sbt run gen P32 full
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# For 64 bit posit and 16 bit posit
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sbt run gen P32 full
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```
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For Posit 32, this will create a folder `P32` with one SV file per module.
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2. Combine all the SV modules to create a single SV
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```
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# From lib/
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make
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```
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## Examples
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The examples folder contains examples of using the binding in Calyx Native
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```
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fud e --to dat vector_add.futil -s verilog.data vector_add.fuse.data --through verilog
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```
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## Frontends
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Calyx frontends will have to emit these primitive to use the Hardposit modules.

‎lib/examples/vector_add.fuse.data

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{
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"a": {
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"data": [
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0,
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1,
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2,
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3,
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0,
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1,
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2,
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3
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],
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"format": {
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"numeric_type": "bitnum",
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"is_signed": false,
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"width": 32
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}
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},
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"b": {
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"data": [
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1,
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2,
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2,
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3,
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1,
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2,
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2,
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3
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],
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"format": {
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"numeric_type": "bitnum",
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"is_signed": false,
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"width": 32
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}
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},
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"c": {
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"data": [
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0
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],
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"format": {
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"numeric_type": "bitnum",
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"is_signed": false,
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"width": 32
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}
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}
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}

‎lib/examples/vector_add.futil

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import "primitives/core.futil";
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import "primitives/memories/seq.futil";
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import "primitives/binary_operators.futil";
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import "../posit_32.futil";
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component main() -> () {
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cells {
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@external(1) a = seq_mem_d1(32,8,4);
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a_read0_0 = std_reg(32);
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add0 = posit_32_add();
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add1 = std_add(4);
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@external(1) b = seq_mem_d1(32,8,4);
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b_read0_0 = std_reg(32);
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@external(1) c = seq_mem_d1(32,8,4);
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const0 = std_const(4,0);
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const1 = std_const(4,7);
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const2 = std_const(4,1);
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i0 = std_reg(4);
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le0 = std_le(4);
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}
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wires {
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comb group cond0 {
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le0.left = i0.out;
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le0.right = const1.out;
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}
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group let0<"promotable"=1> {
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i0.in = const0.out;
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i0.write_en = 1'd1;
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let0[done] = i0.done;
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}
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group let1<"promotable"=2> {
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a_read0_0.in = a.read_data;
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a_read0_0.write_en = a.done;
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let1[done] = a_read0_0.done;
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a.content_en = 1'd1;
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a.addr0 = i0.out;
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}
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group let2<"promotable"=2> {
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b_read0_0.in = b.read_data;
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b_read0_0.write_en = b.done;
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let2[done] = b_read0_0.done;
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b.content_en = 1'd1;
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b.addr0 = i0.out;
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}
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group upd0<"promotable"=1> {
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c.content_en = 1'd1;
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c.addr0 = i0.out;
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c.write_en = 1'd1;
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add0.io_num1 = a_read0_0.out;
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add0.io_num2 = b_read0_0.out;
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add0.io_sub = 1'd0;
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c.write_data = add0.io_out;
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upd0[done] = c.done;
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}
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group upd1<"promotable"=1> {
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i0.write_en = 1'd1;
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add1.left = i0.out;
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add1.right = const2.out;
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i0.in = add1.out;
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upd1[done] = i0.done;
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}
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}
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control {
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seq {
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@pos(0) let0;
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@bound(8) while le0.out with cond0 {
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seq {
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par {
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@pos(1) let1;
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@pos(2) let2;
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}
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@pos(3) upd0;
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@pos(0) upd1;
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}
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}
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}
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}
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}
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metadata #{
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0: for (let i: ubit<4> = 0..8) {
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1: c[i] := a[i] + b[i];
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2: c[i] := a[i] + b[i];
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3: c[i] := a[i] + b[i];
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}#

‎lib/posit_16.futil

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extern "posit_16.sv" {
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comb primitive posit_16_add[](
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@write_together(1) io_num1: 16,
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@write_together(1) io_num2: 16,
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@write_together(1) io_sub: 1,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_isZero: 1,
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io_isNaR : 1,
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io_out: 16
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);
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comb primitive posit_16_mul[](
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@write_together(1) io_num1: 16,
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@write_together(1) io_num2: 16,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_isZero: 1,
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io_isNaR : 1,
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io_out: 16
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);
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comb primitive posit_16_compare[](
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@write_together(1) io_num1: 16,
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@write_together(1) io_num2: 16,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_lt: 1,
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io_eq : 1,
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io_gt: 1
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);
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primitive posit_16_divsqrt[](
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@write_together(1) io_num1: 16,
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@write_together(1) io_num2: 16,
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@write_together(1) @interval(1) @go(1) io_validIn: 1,
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@write_together(1) io_sqrtOp: 1,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_readyIn: 1,
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io_out: 16,
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io_isZero: 1,
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io_isNaR : 1,
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@done io_validOut_div: 1,
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@done io_validOut_sqrt: 1,
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io_exceptions: 4,
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);
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}

‎lib/posit_32.futil

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extern "posit_32.sv" {
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comb primitive posit_32_add[](
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@write_together(1) io_num1: 32,
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@write_together(1) io_num2: 32,
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@write_together(1) io_sub: 1,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_isZero: 1,
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io_isNaR : 1,
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io_out: 32
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);
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comb primitive posit_32_mul[](
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@write_together(1) io_num1: 32,
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@write_together(1) io_num2: 32,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_isZero: 1,
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io_isNaR : 1,
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io_out: 32
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);
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comb primitive posit_32_compare[](
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@write_together(1) io_num1: 32,
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@write_together(1) io_num2: 32,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_lt: 1,
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io_eq : 1,
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io_gt: 1
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);
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primitive posit_32_divsqrt[](
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@write_together(1) io_num1: 32,
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@write_together(1) io_num2: 32,
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@write_together(1) @interval(1) @go(1) io_validIn: 1,
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@write_together(1) io_sqrtOp: 1,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_readyIn: 1,
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io_out: 32,
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io_isZero: 1,
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io_isNaR : 1,
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@done io_validOut_div: 1,
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@done io_validOut_sqrt: 1,
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io_exceptions: 4,
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);
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}

‎lib/posit_64.futil

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extern "posit_64.sv" {
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comb primitive posit_64_add[](
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@write_together(1) io_num1: 64,
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@write_together(1) io_num2: 64,
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@write_together(1) io_sub: 1,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_isZero: 1,
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io_isNaR : 1,
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io_out: 64
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);
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comb primitive posit_64_mul[](
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@write_together(1) io_num1: 64,
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@write_together(1) io_num2: 64,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_isZero: 1,
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io_isNaR : 1,
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io_out: 64
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);
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comb primitive posit_64_compare[](
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@write_together(1) io_num1: 64,
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@write_together(1) io_num2: 64,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_lt: 1,
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io_eq : 1,
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io_gt: 1
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);
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primitive posit_64_divsqrt[](
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@write_together(1) io_num1: 64,
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@write_together(1) io_num2: 64,
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@write_together(1) @interval(1) @go(1) io_validIn: 1,
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@write_together(1) io_sqrtOp: 1,
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@clk clock: 1,
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@reset reset: 1
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) -> (
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io_readyIn: 1,
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io_out: 64,
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io_isZero: 1,
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io_isNaR : 1,
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@done io_validOut_div: 1,
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@done io_validOut_sqrt: 1,
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io_exceptions: 4,
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);
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}

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