The RISC-V 2.0 instruction set was heavily followed during building the instruction set. Each instruction is of fixed size - 29 bits.
| Name | Size | Range |
|---|---|---|
| Opcodes | 6 | 0-5 |
| Destination Register (rd) | 5 | 5-9 |
| Register Select (rs1) | 5 | 10-14 |
| Register Select (rs2) | 5 | 15-19 |
| Immediate | 14 | 17-28 |
| Immediate UP | 17 | 12-28 |
| Load Address | 16 | 13-28 |
| Store Address | 16 | 5-15,22-28 |
| Jump Relative | 13 | 5-9,20-28 |
As designed in hardware , doesn't resemble software instruction set
| Type | Format |
|---|---|
| ALU | op rd,rs1,rs2 |
| ALU Immediate | op rd,rs1,immediate |
| Jump | op rs1,rs2,immediate |
| Jump linked | op rd,immediate |
| Load | load rd,rs1 |
| Store | store rs1,rs2 |
| Load (Immediate) | load rd,load address |
| Store (Immediate) | store store address,rs2 |
| In | in rd,rs2 |
| Out | out rs2,rs1 |
| In (Immediate) | in rd,load address |
| Out (Immediate) | out rs2,store address |
Control signals - click to zoom
Stages are volatile states for each units. These hold the value of necessary information to use multiple operational units process in parallel (not execution - this system has one execution unit, it is meant for fetch,decode,execute,memory,write back units parallel operation on different instructions)
Fetch from Program Memory -> Store to Intermediate Registers (IFID)
Save values of registers from Register file to Intermediate Registers (IFEX)
Perform ALU operation,and, calculate branch. Save Results to Intermediate Registers (EXMEM)
Read/Write to memory or IO,Jump , Save Results to Intermediate Registers (MEMWB)
Write back to register File. End of cycle.
This unit extracts data arranged in 29 bit instruction.
It's a arithmetic and logic unit capable of performing 29 bit arithmetic and logical operations. The Adder is a carry look ahead adder. Multiplicator and Dividers are hardwired logisim asynchronous unit (supports vhdl)
This unit does a clever optimization by setting the opcodes similar to comparator result.
Requires a Single line (As RISC)
The register r0 is hardwired to 0 and r16 is a random generator. The Register file facilitates 2 read and 1 write at a single clock pulse.
Register File A
Register File B
It decodes the instruction and send it though
Read the Registers and gives to execution unit
Hold addresses and data
Hold received data
| Address | IO |
|---|---|
| 000 | TTY |
| 001 | 7 Segment |
| 010 | Display |
| 100 | KeyBoard |
| 101 | Immediate |
| 110 | Joystick |
