diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m5.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m5.c new file mode 100644 index 0000000000000..ae8923287b2e3 --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m5.c @@ -0,0 +1,71 @@ +// REQUIRES: aarch64-registered-target +// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=apple-m5 | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s + +// CHECK: Extensions enabled for the given AArch64 target +// CHECK-EMPTY: +// CHECK-NEXT: Architecture Feature(s) Description +// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support +// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension +// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support +// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions +// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension +// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification +// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions +// CHECK-NEXT: FEAT_CSSC Enable Common Short Sequence Compression (CSSC) instructions +// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction +// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions +// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence +// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence +// CHECK-NEXT: FEAT_DotProd Enable dot product support +// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension +// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support +// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension +// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions +// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions +// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing +// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement +// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int +// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions +// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons +// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension +// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register +// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension +// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions +// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension +// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension +// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets +// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions +// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules +// FIXME: Apple M5 does not have FEAT_MPAM, but it is currently marked as +// non-optional in llvm's understanding of Armv8.4-A +// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension +// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension +// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement +// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension +// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants +// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension +// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension +// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions +// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions +// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier +// FIXME: Apple M5 does not have FEAT_SEL2, but it is currently marked as +// non-optional in llvm's understanding of Armv8.4-A +// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension +// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support +// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support +// CHECK-NEXT: FEAT_SME Enable Scalable Matrix Extension (SME) +// CHECK-NEXT: FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions +// CHECK-NEXT: FEAT_SME2p1 Enable Scalable Matrix Extension 2.1 instructions +// CHECK-NEXT: FEAT_SME_B16B16 Enable SME2.1 ZA-targeting non-widening BFloat16 instructions +// CHECK-NEXT: FEAT_SME_F16F16 Enable SME non-widening Float16 instructions +// CHECK-NEXT: FEAT_SME_F64F64 Enable Scalable Matrix Extension (SME) F64F64 instructions +// CHECK-NEXT: FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions +// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions +// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction +// CHECK-NEXT: FEAT_SVE_B16B16 Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions +// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions +// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension +// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState +// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension +// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction +// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction diff --git a/clang/test/Driver/print-supported-cpus-aarch64.c b/clang/test/Driver/print-supported-cpus-aarch64.c index 3a0ccaf015428..0649181ca39f8 100644 --- a/clang/test/Driver/print-supported-cpus-aarch64.c +++ b/clang/test/Driver/print-supported-cpus-aarch64.c @@ -15,6 +15,7 @@ // CHECK: apple-a16 // CHECK: apple-a17 // CHECK: apple-a18 +// CHECK: apple-a19 // CHECK: apple-a7 // CHECK: apple-a8 // CHECK: apple-a9 @@ -22,6 +23,7 @@ // CHECK: apple-m2 // CHECK: apple-m3 // CHECK: apple-m4 +// CHECK: apple-m5 // CHECK: apple-s10 // CHECK: apple-s4 // CHECK: apple-s5 diff --git a/clang/test/Misc/target-invalid-cpu-note/aarch64.c b/clang/test/Misc/target-invalid-cpu-note/aarch64.c index 0346ab2bb6b13..a84486da807ad 100644 --- a/clang/test/Misc/target-invalid-cpu-note/aarch64.c +++ b/clang/test/Misc/target-invalid-cpu-note/aarch64.c @@ -20,6 +20,7 @@ // CHECK-SAME: {{^}}, apple-a16 // CHECK-SAME: {{^}}, apple-a17 // CHECK-SAME: {{^}}, apple-a18 +// CHECK-SAME: {{^}}, apple-a19 // CHECK-SAME: {{^}}, apple-a7 // CHECK-SAME: {{^}}, apple-a8 // CHECK-SAME: {{^}}, apple-a9 @@ -27,6 +28,7 @@ // CHECK-SAME: {{^}}, apple-m2 // CHECK-SAME: {{^}}, apple-m3 // CHECK-SAME: {{^}}, apple-m4 +// CHECK-SAME: {{^}}, apple-m5 // CHECK-SAME: {{^}}, apple-s10 // CHECK-SAME: {{^}}, apple-s4 // CHECK-SAME: {{^}}, apple-s5 diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index d760ae2ef409b..ed00b55eefa07 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -487,6 +487,26 @@ def TuneAppleM4 : SubtargetFeature<"apple-m4", "ARMProcFamily", "AppleM4", FeatureNoZCZeroingFPR64, FeatureZCZeroingFPR128]>; +def TuneAppleM5 : SubtargetFeature<"apple-m5", "ARMProcFamily", "AppleM5", + "Apple M5", [ + FeatureAlternateSExtLoadCVTF32Pattern, + FeatureArithmeticBccFusion, + FeatureArithmeticCbzFusion, + FeatureDisableLatencySchedHeuristic, + FeatureFuseAddress, + FeatureFuseAdrpAdd, + FeatureFuseAES, + FeatureFuseArithmeticLogic, + FeatureFuseCCSelect, + FeatureFuseCryptoEOR, + FeatureFuseLiterals, + FeatureZCRegMoveGPR64, + FeatureZCRegMoveFPR128, + FeatureZCZeroingGPR32, + FeatureZCZeroingGPR64, + FeatureNoZCZeroingFPR64, + FeatureZCZeroingFPR128]>; + def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", "Samsung Exynos-M3 processors", [FeatureExynosCheapAsMoveHandling, @@ -1019,6 +1039,21 @@ def ProcessorFeatures { FeatureLSE, FeaturePAuth, FeatureFPAC, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureDotProd, FeatureMatMulInt8]; + + list AppleM5 = [HasV8_7aOps, FeatureSHA2, FeatureFPARMv8, + FeatureNEON, FeaturePerfMon, FeatureSHA3, + FeatureFullFP16, FeatureFP16FML, + FeatureAES, FeatureBF16, + FeatureSME, FeatureSME2, + FeatureSMEF64F64, FeatureSMEI16I64, + FeatureComplxNum, FeatureCRC, FeatureJS, + FeatureLSE, FeaturePAuth, FeatureFPAC, + FeatureRAS, FeatureRCPC, FeatureRDM, + FeatureDotProd, FeatureMatMulInt8, + FeatureMTE, FeatureCSSC, FeatureHBC, + FeatureSME2p1, FeatureSMEB16B16, FeatureSMEF16F16, + FeatureSPECRES2]; + list ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES, FeaturePerfMon, FeatureNEON, FeatureFPARMv8]; list ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd, @@ -1338,8 +1373,12 @@ def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4, [TuneAppleM4]>; def : ProcessorAlias<"apple-a18", "apple-m4">; +def : ProcessorModel<"apple-m5", CycloneModel, ProcessorFeatures.AppleM5, + [TuneAppleM5]>; +def : ProcessorAlias<"apple-a19", "apple-m5">; + // Alias for the latest Apple processor model supported by LLVM. -def : ProcessorAlias<"apple-latest", "apple-m4">; +def : ProcessorAlias<"apple-latest", "apple-m5">; // Fujitsu A64FX diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index a6ae7f8da2121..96dfd781d045d 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -219,6 +219,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { case AppleA16: case AppleA17: case AppleM4: + case AppleM5: CacheLineSize = 64; PrefetchDistance = 280; MinPrefetchStride = 2048; @@ -229,6 +230,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { case AppleA16: case AppleA17: case AppleM4: + case AppleM5: MaxInterleaveFactor = 4; break; default: diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 193be62b28ad6..fc8bacbe1c25d 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -4929,6 +4929,7 @@ void AArch64TTIImpl::getUnrollingPreferences( case AArch64Subtarget::AppleA15: case AArch64Subtarget::AppleA16: case AArch64Subtarget::AppleM4: + case AArch64Subtarget::AppleM5: getAppleRuntimeUnrollPreferences(L, SE, UP, *this); break; case AArch64Subtarget::Falkor: diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index aeeea0a391ba9..b283113c2b27f 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1141,6 +1141,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64CPUTestParams("apple-a17", "armv8.6-a"), AArch64CPUTestParams("apple-m4", "armv8.7-a"), AArch64CPUTestParams("apple-a18", "armv8.7-a"), + AArch64CPUTestParams("apple-m5", "armv8.7-a"), AArch64CPUTestParams("exynos-m3", "armv8-a"), AArch64CPUTestParams("exynos-m4", "armv8.2-a"), AArch64CPUTestParams("exynos-m5", "armv8.2-a"), @@ -1257,11 +1258,12 @@ INSTANTIATE_TEST_SUITE_P( AArch64CPUAliasTestParams({"apple-a15", "apple-m2"}), AArch64CPUAliasTestParams({"apple-a16", "apple-m3", "apple-s9", "apple-s10"}), - AArch64CPUAliasTestParams({"apple-m4", "apple-a18"})), + AArch64CPUAliasTestParams({"apple-m4", "apple-a18"}), + AArch64CPUAliasTestParams({"apple-m5", "apple-a19"})), AArch64CPUAliasTestParams::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 91; +static constexpr unsigned NumAArch64CPUArchs = 93; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector List;