infallible

Author: burrbull

CHANGELOG.md

@@ -20,6 +20,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - DMA traits now require AsSlice instead of AsRef
 
+- `void::Void` replaced with `Infallible` where it is possible
+
 ## [v0.4.0] - 2019-08-09
 
 ### Added

README.md

@@ -49,7 +49,7 @@ be specified as part of the `Cargo.toml` definition.
 
 ```toml
 [dependencies.stm32f1xx-hal]
-version = "0.3.0"
+version = "0.4.0"
 features = ["stm32f100", "rt"]
 ```
 
@@ -99,14 +99,15 @@ fn main() -> ! {
     // in order to configure the port. For pins 0-7, crl should be passed instead.
     let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
     // Configure the syst timer to trigger an update every second
-    let mut timer = Timer::syst(cp.SYST, 1.hz(), clocks);
+    let mut timer = Timer::syst(cp.SYST, clocks)
+        .start_count_down(1.hz());
 
     // Wait for the timer to trigger an update and change the state of the LED
     loop {
         block!(timer.wait()).unwrap();
-        led.set_high();
+        led.set_high().unwrap();
         block!(timer.wait()).unwrap();
-        led.set_low();
+        led.set_low().unwrap();
     }
 }
 ```

examples/pwm_input.rs

@@ -32,7 +32,7 @@ fn main() -> ! {
     let (_pa15, _pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4);
     let pb5 = gpiob.pb5;
 
-    let mut pwm_input = Timer::tim3(p.TIM3, &clocks, &mut rcc.apb1)
+    let pwm_input = Timer::tim3(p.TIM3, &clocks, &mut rcc.apb1)
         .pwm_input(
             (pb4, pb5),
             &mut afio.mapr,

examples/serial_config.rs

@@ -14,7 +14,6 @@ use stm32f1xx_hal::{
     prelude::*,
     pac,
     serial::{self, Serial},
-    timer::Timer,
 };
 use cortex_m_rt::entry;
 

src/gpio.rs

@@ -77,7 +77,7 @@ macro_rules! gpio {
     ]) => {
         /// GPIO
         pub mod $gpiox {
-            use void::Void;
+            use core::convert::Infallible;
             use core::marker::PhantomData;
 
             use crate::hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin, toggleable};
@@ -157,7 +157,7 @@ macro_rules! gpio {
             }
 
             impl<MODE> OutputPin for $PXx<Output<MODE>> {
-                type Error = Void;
+                type Error = Infallible;
                 fn set_high(&mut self) -> Result<(), Self::Error> {
                     // NOTE(unsafe) atomic write to a stateless register
                     Ok(unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << self.i)) })
@@ -170,7 +170,7 @@ macro_rules! gpio {
             }
 
             impl<MODE> InputPin for $PXx<Input<MODE>> {
-                type Error = Void;
+                type Error = Infallible;
                 fn is_high(&self) -> Result<bool, Self::Error> {
                     self.is_low().map(|b| !b)
                 }
@@ -195,7 +195,7 @@ macro_rules! gpio {
             impl <MODE> toggleable::Default for $PXx<Output<MODE>> {}
 
             impl InputPin for $PXx<Output<OpenDrain>> {
-                type Error = Void;
+                type Error = Infallible;
                 fn is_high(&self) -> Result<bool, Self::Error> {
                     self.is_low().map(|b| !b)
                 }
@@ -454,7 +454,7 @@ macro_rules! gpio {
                 }
 
                 impl<MODE> OutputPin for $PXi<Output<MODE>> {
-                    type Error = Void;
+                    type Error = Infallible;
                     fn set_high(&mut self) -> Result<(), Self::Error> {
                         // NOTE(unsafe) atomic write to a stateless register
                         Ok(unsafe { (*$GPIOX::ptr()).bsrr.write(|w| w.bits(1 << $i)) })
@@ -480,7 +480,7 @@ macro_rules! gpio {
                 impl<MODE> toggleable::Default for $PXi<Output<MODE>> {}
 
                 impl<MODE> InputPin for $PXi<Input<MODE>> {
-                    type Error = Void;
+                    type Error = Infallible;
                     fn is_high(&self) -> Result<bool, Self::Error> {
                         self.is_low().map(|b| !b)
                     }
@@ -492,7 +492,7 @@ macro_rules! gpio {
                 }
 
                 impl InputPin for $PXi<Output<OpenDrain>> {
-                    type Error = Void;
+                    type Error = Infallible;
                     fn is_high(&self) -> Result<bool, Self::Error> {
                         self.is_low().map(|b| !b)
                     }

src/rtc.rs

@@ -17,7 +17,7 @@ use crate::pac::{RTC, RCC};
 use crate::backup_domain::BackupDomain;
 
 use nb;
-use void::Void;
+use core::convert::Infallible;
 
 // The LSE runs at at 32 768 hertz unless an external clock is provided
 const LSE_HERTZ: u32 = 32_768;
@@ -154,11 +154,11 @@ impl Rtc {
       use nb::block;
 
       rtc.set_alarm(rtc.read_counts() + 5);
-      // NOTE: Safe unwrap because Void can't be returned
+      // NOTE: Safe unwrap because Infallible can't be returned
       block!(rtc.wait_alarm()).unwrap();
       ```
     */
-    pub fn wait_alarm(&mut self) -> nb::Result<(), Void> {
+    pub fn wait_alarm(&mut self) -> nb::Result<(), Infallible> {
         if self.regs.crl.read().alrf().bit() == true {
             self.regs.crl.modify(|_, w| w.alrf().clear_bit());
             Ok(())

src/serial.rs

@@ -42,7 +42,7 @@ use core::sync::atomic::{self, Ordering};
 
 use nb;
 use crate::pac::{USART1, USART2, USART3};
-use void::Void;
+use core::convert::Infallible;
 
 use crate::afio::MAPR;
 use crate::dma::{dma1, CircBuffer, Static, Transfer, R, W, RxDma, TxDma};
@@ -388,7 +388,7 @@ macro_rules! hal {
             }
 
             impl crate::hal::serial::Write<u8> for Tx<$USARTX> {
-                type Error = Void;
+                type Error = Infallible;
 
                 fn flush(&mut self) -> nb::Result<(), Self::Error> {
                     // NOTE(unsafe) atomic read with no side effects