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| 1 | +#define MICROPY_HW_BOARD_NAME "iMX_RT1011_Nano_Kit" |
| 2 | +#define MICROPY_HW_MCU_NAME "MIMXRT1011DAE5A" |
| 3 | +#define MICROPY_HW_USB_MANUFACTURER_STRING "Makerdiary" |
| 4 | +#define MICROPY_HW_USB_VID 0xf055 |
| 5 | +#define MICROPY_HW_USB_PID 0x9802 |
| 6 | +#define MICROPY_PY_OS_DUPTERM_BUILTIN_STREAM (0) |
| 7 | + |
| 8 | +// RT1011-Nanokit has 1 board LED |
| 9 | +#define MICROPY_HW_LED1_PIN (pin_GPIO_SD_04) |
| 10 | +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin)) |
| 11 | +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin)) |
| 12 | + |
| 13 | +#define MICROPY_HW_NUM_PIN_IRQS (2 * 32) |
| 14 | +#define MICROPY_PY_MACHINE_SDCARD (0) |
| 15 | + |
| 16 | + |
| 17 | +#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0]) |
| 18 | +#define MICROPY_HW_UART_INDEX { 0, 1, 2, 3, 4 } |
| 19 | + |
| 20 | +#define IOMUX_TABLE_UART \ |
| 21 | + { IOMUXC_GPIO_10_LPUART1_TXD }, { IOMUXC_GPIO_09_LPUART1_RXD }, \ |
| 22 | + { IOMUXC_GPIO_AD_00_LPUART2_TXD }, { IOMUXC_GPIO_13_LPUART2_RXD }, \ |
| 23 | + { IOMUXC_GPIO_12_LPUART3_TXD }, { IOMUXC_GPIO_11_LPUART3_RXD }, \ |
| 24 | + { IOMUXC_GPIO_AD_02_LPUART4_TXD }, { IOMUXC_GPIO_AD_01_LPUART4_RXD }, |
| 25 | + |
| 26 | +#define IOMUX_TABLE_UART_CTS_RTS \ |
| 27 | + { IOMUXC_GPIO_08_LPUART1_CTS_B }, { IOMUXC_GPIO_07_LPUART1_RTS_B }, \ |
| 28 | + { IOMUXC_GPIO_AD_08_LPUART2_CTS_B }, { IOMUXC_GPIO_AD_07_LPUART2_RTS_B }, \ |
| 29 | + { IOMUXC_GPIO_AD_14_LPUART3_CTS_B }, { IOMUXC_GPIO_AD_13_LPUART3_RTS_B }, \ |
| 30 | + { IOMUXC_GPIO_AD_14_LPUART4_CTS_B }, { IOMUXC_GPIO_AD_13_LPUART4_RTS_B }, |
| 31 | + |
| 32 | +#define MICROPY_HW_SPI_INDEX { 1, 2 } |
| 33 | + |
| 34 | +#define IOMUX_TABLE_SPI \ |
| 35 | + { IOMUXC_GPIO_AD_06_LPSPI1_SCK }, { IOMUXC_GPIO_AD_05_LPSPI1_PCS0 }, \ |
| 36 | + { IOMUXC_GPIO_AD_04_LPSPI1_SDO }, { IOMUXC_GPIO_AD_03_LPSPI1_SDI }, \ |
| 37 | + { IOMUXC_GPIO_AD_02_LPSPI1_PCS1 }, \ |
| 38 | + { IOMUXC_GPIO_AD_12_LPSPI2_SCK }, { IOMUXC_GPIO_AD_11_LPSPI2_PCS0 }, \ |
| 39 | + { IOMUXC_GPIO_AD_10_LPSPI2_SDO }, { IOMUXC_GPIO_AD_09_LPSPI2_SDI }, \ |
| 40 | + { IOMUXC_GPIO_AD_01_LPSPI2_PCS1 } |
| 41 | + |
| 42 | +#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx } |
| 43 | +#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx } |
| 44 | + |
| 45 | +// Define mapping hardware I2C # to logical I2C # |
| 46 | +// SDA/SCL HW-I2C Logical I2C |
| 47 | +// SDA1/SCL1 LPI2C1 -> 0 |
| 48 | +// SDA2/SCL2 LPI2C2 -> 1 |
| 49 | + |
| 50 | +#define MICROPY_HW_I2C_INDEX { 1, 2 } |
| 51 | + |
| 52 | +#define IOMUX_TABLE_I2C \ |
| 53 | + { IOMUXC_GPIO_02_LPI2C1_SCL }, { IOMUXC_GPIO_01_LPI2C1_SDA }, \ |
| 54 | + { IOMUXC_GPIO_AD_08_LPI2C2_SCL }, { IOMUXC_GPIO_AD_07_LPI2C2_SDA }, |
| 55 | + |
| 56 | +#define MICROPY_PY_MACHINE_I2S (1) |
| 57 | +#define MICROPY_HW_I2S_NUM (3) |
| 58 | +#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, 0, kCLOCK_Sai3Mux } |
| 59 | +#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv, 0, kCLOCK_Sai3PreDiv } |
| 60 | +#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div, 0, kCLOCK_Sai3Div } |
| 61 | +#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, 0, kIOMUXC_GPR_SAI3MClkOutputDir } |
| 62 | +#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, 0, kDmaRequestMuxSai3Rx } |
| 63 | +#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, 0, kDmaRequestMuxSai3Tx } |
| 64 | +#define I2S_AUDIO_PLL_CLOCK (2U) |
| 65 | + |
| 66 | +#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ |
| 67 | + { \ |
| 68 | + .hw_id = _hwid, \ |
| 69 | + .fn = _fn, \ |
| 70 | + .mode = _mode, \ |
| 71 | + .name = MP_QSTR_##_pin, \ |
| 72 | + .iomux = {_iomux}, \ |
| 73 | + } |
| 74 | + |
| 75 | +#define I2S_GPIO_MAP \ |
| 76 | + { \ |
| 77 | + I2S_GPIO(1, MCK, TX, GPIO_08, IOMUXC_GPIO_08_SAI1_MCLK), /* pin D8 */ \ |
| 78 | + I2S_GPIO(1, SCK, RX, GPIO_01, IOMUXC_GPIO_01_SAI1_RX_BCLK), /* pin D1 */ \ |
| 79 | + I2S_GPIO(1, WS, RX, GPIO_02, IOMUXC_GPIO_02_SAI1_RX_SYNC), /* pin D2 */ \ |
| 80 | + I2S_GPIO(1, SD, RX, GPIO_03, IOMUXC_GPIO_03_SAI1_RX_DATA00), /* pin D3 */ \ |
| 81 | + I2S_GPIO(1, SCK, TX, GPIO_06, IOMUXC_GPIO_06_SAI1_TX_BCLK), /* pin D6 */ \ |
| 82 | + I2S_GPIO(1, WS, TX, GPIO_07, IOMUXC_GPIO_07_SAI1_TX_SYNC), /* pin D7 */ \ |
| 83 | + I2S_GPIO(1, SD, TX, GPIO_04, IOMUXC_GPIO_04_SAI1_TX_DATA00), /* pin D4 */ \ |
| 84 | + I2S_GPIO(3, SCK, TX, GPIO_SD_01, IOMUXC_GPIO_SD_01_SAI3_TX_BCLK), /* pin SD1 */ \ |
| 85 | + I2S_GPIO(3, WS, TX, GPIO_SD_00, IOMUXC_GPIO_SD_00_SAI3_TX_SYNC), /* pin SD0 */ \ |
| 86 | + I2S_GPIO(3, SD, TX, GPIO_SD_02, IOMUXC_GPIO_SD_02_SAI3_TX_DATA) /* pin SD2 */ \ |
| 87 | + } |
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