Gigabit Transceivers connections

[tprzywoz]

In the current design we have:

4 x GTY Quad

• 3 x GTY Quad routed to RTM
• 1 x GTY Quad routed to AMC Fatpipe 1 with an option to route 1 channel to Artix and 1 channel to PORT 1

1 x GTR Quad routed to RTM

1 x GTP Quad

• 1 channel routed to SoC GTY
• 2 channel routed to ''Sayma AFE''
• 1 channel routed to SATA connector

Are there any suggestions for changes?
If we change AFE (#3) we will have 2 free GTP channels. I also want to remove SATA connector to reduce the number of large components on PCB.

Does Artix need a direct connection to AMC (DRTIO) to be able to ensure synchronization or is GTP - GTY connection sufficient (DRTIO to ARTIX through SoC)?

Does our basic application need 3 GTY Quads connected to RTM? Because we can move PORT 1 and Artix channels to one of these Quads (as an option).

[gkasprow]

We have following use cases:

• SC qubits, we need both fast PCIe/10GBE (FP1 x4 lanes) + DRTIO for sync(FP2 x1 lane). It requires a large crate with dual MCH
• ions, we need only DRTIO over FP1 (1 lane). It may work in small crates with single MCH
• SDR applications. we need a lot of bandwidth via RTM board. x8 link to two QSFPs is minimum.
  GTR have limited applications - they can ony work as USB3.0, SATA, PCIe gen 2 or SGMII. I'd route them all to RTM for future connectivity.
  SoC needs to have at least one, maybe two links routed to Artix. Artix serves as DRTIO router.
  PORT0 needs to be connected to PHY chip and then via RGMII to SOC. Use same PHY as we use on other boards.

Artix needs a dedicated connection to Metlino. Either by Fat Pipe 1 or Fat Pipe 2
When Artix is connected to Fat Pipe 2, SoC will be connected to Fat Pipe 1.

[tprzywoz]

Artix needs a dedicated connection to Metlino. Either by Fat Pipe 1 or Fat Pipe 2

All 4 lanes or 1-2 is enough? Our Artix has only one GTP Quad.