diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index fd9a78fd..4192ecff 100644
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -100,6 +100,8 @@ class Decoder(srd.Decoder):
             'values': (0, 1)},
         {'id': 'bitorder', 'desc': 'Bit order',
             'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
+        {'id': 'skipbits', 'desc': 'Skip bits from start',
+            'default': 0},
         {'id': 'wordsize', 'desc': 'Word size', 'default': 8},
     )
     annotations = (
@@ -131,6 +133,7 @@ def __init__(self):
     def reset(self):
         self.samplerate = None
         self.bitcount = 0
+        self.bitsskipped = 0
         self.misodata = self.mosidata = 0
         self.misobits = []
         self.mosibits = []
@@ -200,6 +203,7 @@ def reset_decoder_state(self):
         self.misobits = [] if self.have_miso else None
         self.mosibits = [] if self.have_mosi else None
         self.bitcount = 0
+        #self.bitsskipped = 0
 
     def cs_asserted(self, cs):
         active_low = (self.options['cs_polarity'] == 'active-low')
@@ -310,6 +314,10 @@ def find_clk_edge(self, miso, mosi, clk, cs, first):
         elif mode == 3 and clk == 0: # Sample on rising clock edge
             return
 
+        if self.bitsskipped < self.options["skipbits"]:
+            self.bitsskipped += 1
+            return
+
         # Found the correct clock edge, now get the SPI bit(s).
         self.handle_bit(miso, mosi, clk, cs)