Verilog jmp to program from bootsequence complete

Author: scopeInfinity

emulator/chipset.v

@@ -3,11 +3,10 @@
 `include "emulator/com/stage1.v"
 `include "emulator/com/stage2.v"
 `include "emulator/com/stage3.v"
-`include "emulator/com/input_devices.v"
 `include "emulator/com/rom.v"
 `include "emulator/seq/clock.v"
 `include "emulator/seq/register.v"
-`include "emulator/seq/output_devices.v"
+`include "emulator/seq/io_devices.v"
 `include "emulator/seq/ram.v"
 
 module CHIPSET(
@@ -30,7 +29,8 @@ module CHIPSET(
     // BROM
     wire[15:0] brom_address;
     wire[31:0] brom_value;
-    ROM_BOOT brom(.out(brom_value), .address(brom_address));
+    ROM_BOOT #(.filename("output/programs/boot_sequence.bin"))
+        brom(.out(brom_value), .address(brom_address));
 
     // RAM
     wire ram_is_write;
@@ -55,34 +55,33 @@ module CHIPSET(
       .A2(ram_address_stage2),
       .A3(ram_address_stage3),
       .S(clk_stage));
-
-    // TODO: Updated ram_address
-    assign ram_address = ram_address_stage0;
-
-    // Input Devices
-    wire[7:0] input_devices_address;
+    // always @(ram_address, ram_address_stage0, ram_address_stage1, ram_address_stage2, ram_address_stage3, clk_stage)
+    // begin
+    // $display("add:%b, s0:%b, s1:%b, s2:%b, s3:%b, stage:%b", ram_address, ram_address_stage0, ram_address_stage1, ram_address_stage2, ram_address_stage3, clk_stage);
+    // end
+
+    // IO Devices
+    wire[7:0] io_device_id_s1;
+    wire[7:0] io_device_id_s3;
+    wire[7:0] io_device_id;
     wire[31:0] input_devices_value;
-
-    InputDevices idevices(
-        .value(input_devices_value),
-        .address(input_devices_address)
-        // .device0_values(2),
-        // .device1_values(3)
-        );
-
-    // Output Devices
     wire[31:0] output_devices_value;
-    wire[7:0] output_devices_address;
     wire output_is_write;
 
-    OutputDevices odevices(
-        // .device0_values(device0_values),
-        // .device1_values(device1_values),
-        .address(output_devices_address),
-        .value(output_devices_value),
+    IODevices io_devices(
+        .value_out(input_devices_value),
+        .device_id(io_device_id),
+        .value_in(output_devices_value),
         .is_write(output_is_write),
         .clk(clk[3]));
 
+    wire[7:0] unused2;
+    MUX_1_16b io_device_id_selector(
+      .value({unused2, io_device_id}),
+      .A0({unused2, io_device_id_s1}),
+      .A1({unused2, io_device_id_s3}),
+      .S(clk_stage[1]));
+
     // STAGE0
     wire[31:0] _instruction_binary;
     STAGE0 stage0(
@@ -115,8 +114,8 @@ module CHIPSET(
     wire[31:0] _vr_value;
     STAGE1 stage1(
         .vr_value(_vr_value),
-        .input_devices_address(input_devices_address),
-        .ram_address(ram_address),
+        .io_device_id(io_device_id_s1),
+        .ram_address(ram_address_stage1),
         .mblock_s1(mblock_s1),
         .vr_source(vr_source),
         .input_devices_value(input_devices_value),
@@ -137,10 +136,10 @@ module CHIPSET(
     wire[31:0] _vw_value;
     wire _alu_is_zero;
     STAGE2 stage2(
-        .vrw_value(vrw_value),
-        .vw_value(vw_value),
+        .vrw_value(_vrw_value),
+        .vw_value(_vw_value),
         .ram_address(ram_address_stage2),
-        .alu_is_zero(alu_is_zero),
+        .alu_is_zero(_alu_is_zero),
         .mblock_s2(mblock_s2),
         .vr_source(vr_source),
         .vr_value(vr_value),
@@ -182,7 +181,7 @@ module CHIPSET(
 
     STAGE3 stage3(
         .output_devices_value(output_devices_value),
-        .output_devices_address(output_devices_address),
+        .io_device_id(io_device_id_s3),
         .ram_address(ram_address_stage3),
         .ram_in(ram_in),
         .ram_is_write(ram_is_write),
@@ -211,26 +210,24 @@ module CHIPSET(
         .in(pc_next),
         .clk(clk[3]));
 
-    always @(negedge clk[0]) begin
-        $display("Stage0: power=%b pc=%b ins=%b eram=%b",
-            is_powered_on_new, pc, _instruction_binary, flag_execute_from_ram);
-    end
-    always @(negedge clk[1]) begin
-        $display("Stage1: alu=%b s1=%b s2=%b s3=%b vrw_source=%b vr_source=%b",
-            mblock_alu_op, mblock_s1, mblock_s2, mblock_s3, vrw_source, vr_source);
-    end
-    always @(negedge clk[2]) begin
-        $display("Stage2: vr_value=%b",
-            vr_value);
-    end
-    always @(negedge clk[3]) begin
-        $display("Stage3: vrw_value=%b, vw_value=%b is_zero=%b",
-            vrw_value, vw_value, alu_is_zero);
-    end
-    always @(posedge clk[0]) begin
-        $display("StageE: power=%b, f_zero=%b, f_eram=%b pc=%b",
-            is_powered_on, flag_last_zero, flag_execute_from_ram, pc);
-    end
-
-
+    // always @(negedge clk[0]) begin
+    //     $display("Stage0: power=%b pc=%x ins=%b eram=%b",
+    //         is_powered_on_new, pc, _instruction_binary, flag_execute_from_ram);
+    // end
+    // always @(negedge clk[1]) begin
+    //     $display("Stage1: alu=%b s1=%b s2=%b s3=%b vrw_source=%x vr_source=%x",
+    //         mblock_alu_op, mblock_s1, mblock_s2, mblock_s3, vrw_source, vr_source);
+    // end
+    // always @(negedge clk[2]) begin
+    //     $display("Stage2: vr_value=%x",
+    //         vr_value);
+    // end
+    // always @(negedge clk[3]) begin
+    //     $display("Stage3: vrw_value=%x, vw_value=%x is_zero=%b",
+    //         vrw_value, vw_value, alu_is_zero);
+    // end
+    // always @(posedge clk[0]) begin
+    //     $display("StageE: power=%b, f_zero=%b, f_eram=%b pc=%x write_ram=%b wrire_io=%b",
+    //         is_powered_on, flag_last_zero, flag_execute_from_ram, pc, ram_is_write, output_is_write);
+    // end
 endmodule

emulator/chipset_test.v

@@ -18,7 +18,7 @@ module chipset_test;
         reset_button = 1;
         # 80
         reset_button = 0;
-        # 100
+        # 200000
         if (reset_button !== 0) begin
             $error("chipset failed");
             $fatal(1);

emulator/com/alu.v

@@ -13,9 +13,9 @@ module ALU (
     always @(op, in_r, in_rw) begin
         case(op)
         4'b0000: mem = in_r+in_rw;
-        4'b0001: mem = in_r-in_rw;
-        4'b0010: mem = (in_r<<in_rw);
-        4'b0011: mem = (in_r>>in_rw);
+        4'b0001: mem = in_rw-in_r;
+        4'b0010: mem = (in_rw<<in_r);
+        4'b0011: mem = (in_rw>>in_r);
         4'b0100: mem = (in_r);
         4'b0101: mem = (in_rw);
         4'b0110: mem = (in_r&in_rw);

emulator/com/alu_test.v

@@ -27,8 +27,8 @@ module alu_test;
 
         // SUB
         op = 4'b0001;
-        in_r = 2536;
-        in_rw = 113;
+        in_r = 113;
+        in_rw = 2536;
         # 10
         $display("ALU_TEST: op=%b in_r=%b in_rw=%b", op, in_r, in_rw);
         if (out !== 2423 || is_zero !== 0) begin
@@ -38,8 +38,8 @@ module alu_test;
 
         // LSR
         op = 4'b0010;
-        in_r = 2536;
-        in_rw = 2;
+        in_r = 2;
+        in_rw = 2536;
         # 10
         $display("ALU_TEST: op=%b in_r=%b in_rw=%b", op, in_r, in_rw);
         if (out !== 10144 || is_zero !== 0) begin
@@ -49,8 +49,8 @@ module alu_test;
 
         // RSR
         op = 4'b0011;
-        in_r = 2536;
-        in_rw = 4;
+        in_r = 4;
+        in_rw = 2536;
         # 10
         $display("ALU_TEST: op=%b in_r=%b in_rw=%b", op, in_r, in_rw);
         if (out !== 158 || is_zero !== 0) begin

emulator/com/input_devices.v

@@ -6,7 +6,7 @@ module MUX_1_16b(
     input [15:0] A0, A1,
     input S);
 
-    always @(*) begin
+    always @(S, A0, A1) begin
         if (S) begin
             value = A1;
         end else begin
@@ -20,7 +20,7 @@ module MUX_2_16b(
     input [15:0] A0, A1, A2, A3,
     input [1:0] S);
 
-    always @(*) begin
+    always @(S, A0, A1, A2, A3) begin
         case (S)
             2'b00: value = A0;
             2'b01: value = A1;

emulator/com/input_devices_test.v

@@ -1,3 +1,6 @@
+`ifndef INCLUDED_ROM
+`define INCLUDED_ROM
+
 module _ROM_32bit_16aline(
         output[31:0] out,
         input[15:0] address);
@@ -19,12 +22,23 @@ endmodule
 module ROM_BOOT(
         output[31:0] out,
         input[15:0] address);
-    // 4 * 64KB ROM
+    parameter filename = "emulator/com/rom_boot.bin";
     reg[15:0] eaddress;
     always @(address) begin
         eaddress = address - 'h40;
     end
-    _ROM_32bit_16aline #(.filename("emulator/com/rom_boot.bin"))
-        dut(.out(out),
+    _ROM_32bit_16aline #(.filename(filename))
+        _rom(.out(out),
         .address(eaddress));
 endmodule
+
+module ROM_PINGPONG(
+        output[31:0] out,
+        input[15:0] address);
+    parameter filename = "output/programs/ping_pong.bin";
+    _ROM_32bit_16aline #(.filename(filename))
+        _rom(.out(out),
+        .address(address));
+endmodule
+
+`endif

emulator/com/mux.v

@@ -2,7 +2,7 @@
 
 module STAGE1(
     output[31:0] vr_value,
-    output[7:0] input_devices_address,
+    output[7:0] io_device_id,
     output[15:0] ram_address,
     input[1:0] mblock_s1,
     input[7:0] vr_source,
@@ -11,7 +11,7 @@ module STAGE1(
 
     wire[31:0] _const_value;
 
-    assign input_devices_address = vr_source;
+    assign io_device_id = vr_source;
     assign _const_value[7:0] = vr_source;
     assign _const_value[31:8] = 24'b000000000000000000000000;
     assign ram_address[7:0] = vr_source;

emulator/com/rom.v

@@ -2,7 +2,7 @@
 
 module stage1_test;
     wire[31:0] vr_value;
-    wire[7:0] input_devices_address;
+    wire[7:0] io_device_id;
     wire[15:0] ram_address;
 
     reg[1:0] mblock_s1;
@@ -12,7 +12,7 @@ module stage1_test;
 
     STAGE1 dut(
         .vr_value(vr_value),
-        .input_devices_address(input_devices_address),
+        .io_device_id(io_device_id),
         .ram_address(ram_address),
         .mblock_s1(mblock_s1),
         .vr_source(vr_source),
@@ -34,8 +34,8 @@ module stage1_test;
         # 10
         mblock_s1 = 2;
         # 10
-        $display("STAGE1_TEST: vr_value=%b input_devices_address=%b", vr_value, input_devices_address);
-        if (vr_value !== 22 || input_devices_address !== 33) begin
+        $display("STAGE1_TEST: vr_value=%b io_device_id=%b", vr_value, io_device_id);
+        if (vr_value !== 22 || io_device_id !== 33) begin
             $error("stage1 failed");
             $fatal(1);
         end