@@ -7,6 +7,7 @@ pub const PIN_BASED_NMI : uint64_t = 1 << 3;
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pub const PIN_BASED_VIRTUAL_NMI : uint64_t = 1 << 5 ;
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pub const PIN_BASED_PREEMPTION_TIMER : uint64_t = 1 << 6 ;
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pub const PIN_BASED_POSTED_INTR : uint64_t = 1 << 7 ;
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pub const CPU_BASED_IRQ_WND : uint64_t = 1 << 2 ;
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pub const CPU_BASED_TSC_OFFSET : uint64_t = 1 << 3 ;
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pub const CPU_BASED_HLT : uint64_t = 1 << 7 ;
@@ -28,6 +29,7 @@ pub const CPU_BASED_MSR_BITMAPS : uint64_t = 1 << 28;
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pub const CPU_BASED_MONITOR : uint64_t = 1 << 29 ;
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pub const CPU_BASED_PAUSE : uint64_t = 1 << 30 ;
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pub const CPU_BASED_SECONDARY_CTLS : uint64_t = 1 << 31 ;
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pub const CPU_BASED2_VIRTUAL_APIC : uint64_t = 1 << 0 ;
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pub const CPU_BASED2_EPT : uint64_t = 1 << 1 ;
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pub const CPU_BASED2_DESC_TABLE : uint64_t = 1 << 2 ;
@@ -46,8 +48,10 @@ pub const CPU_BASED2_VMCS_SHADOW : uint64_t = 1 << 14;
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pub const CPU_BASED2_RDSEED : uint64_t = 1 << 16 ;
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pub const CPU_BASED2_EPT_VE : uint64_t = 1 << 18 ;
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pub const CPU_BASED2_XSAVES_XRSTORS : uint64_t = 1 << 20 ;
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pub const VMX_EPT_VPID_SUPPORT_AD : uint64_t = 1 << 21 ;
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pub const VMX_EPT_VPID_SUPPORT_EXONLY : uint64_t = 1 << 0 ;
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pub const VMEXIT_SAVE_DBG_CONTROLS : uint64_t = 1 << 2 ;
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pub const VMEXIT_HOST_IA32E : uint64_t = 1 << 9 ;
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pub const VMEXIT_LOAD_IA32_PERF_GLOBAL_CTRL : uint64_t = 1 << 12 ;
@@ -57,6 +61,7 @@ pub const VMEXIT_LOAD_IA32_PAT : uint64_t = 1 << 19;
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pub const VMEXIT_SAVE_EFER : uint64_t = 1 << 20 ;
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pub const VMEXIT_LOAD_EFER : uint64_t = 1 << 21 ;
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pub const VMEXIT_SAVE_VMX_TIMER : uint64_t = 1 << 22 ;
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pub const VMENTRY_LOAD_DBG_CONTROLS : uint64_t = 1 << 2 ;
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pub const VMENTRY_GUEST_IA32E : uint64_t = 1 << 9 ;
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pub const VMENTRY_SMM : uint64_t = 1 << 10 ;
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