-
Notifications
You must be signed in to change notification settings - Fork 4
/
clem_mmio.c
1871 lines (1781 loc) · 73.8 KB
/
clem_mmio.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#include "clem_mmio.h"
#include "clem_debug.h"
#include "clem_drive.h"
#include "clem_mem.h"
#include "clem_mmio_defs.h"
#include "clem_device.h"
#include "clem_mmio_types.h"
#include "clem_scc.h"
#include "clem_types.h"
#include "clem_util.h"
#include "clem_vgc.h"
#include <string.h>
/**
* Video Memory layout
*
* High Level:
* FPI memory in banks $00 - $7F (practically up to 8MB RAM) and
* ROM ($F0-$FF) - runs at clock speed
* Mega 2 memory in banks $E0, $E1
* - memory accesses here are always at 1mhz (reads AND writes)
*
* Shadowing keeps select pages from $00, $01 in sync with $e0, $e1
* - writes must occur at Mega 2 speed (1mhz)
* - reads for I/O shadowing occur at 1mhz (reads from $E0, E1)
* - reads for display shadowing occur at FPI speed (reading from $00,$01)
*
*
* Bank 00/01
* 0400-07FF Text Page 1
* 0800-0BFF Text Page 2
* 2000-3FFF HGR Page 1
* 4000-5FFF HGR Page 2
* * note there are quirks addressed in the "Alternate Display Mode" IIgs
* feature, which turns on shadowing for text page 2 (required for Apple II
* text page compatilbility)
*
* Bank 00/01
* C000-CFFF IO + slot expansions (mirrored), shadowing from bank $e0
* D000-DFFF contains 2 banks of 4K RAM
* E000-FFFF contains 1 bank 12K RAM
*
* Oddities
* C07X bank 0 contains code for interrupts, which relies on the shadowing
* to work a certain way. Account for this when debugging/testing
* interrupts from the ROM
* Generally speaking, access in the $C000 page is slow, but certain FPI
* registers can be read/write fast, including interrupt rom at $C071-7F
* RAM refresh delays in FPI memory 8 when instructions/data accessed
* from RAM
*
*
*/
/**
* Memory R/W access
*
* FPI ROM - 2.864mhz
* FPI RAM - 8% reduction from 2.8mhz (TPD?) - 2.6mhz approx
* Mega2 RAM - 1.023 mhz
*
* - Map Bank:Address to its actual Bank:Address inside either its FPI or Mega2
* Memory
* - Shadowed reads outside of I/O are handled by reading the FPI memory
* - Shadowed writes outside of I/O are handled by writing to both FPI and
* Mega2
* - I/O is a special case
* - Softswitches alter the mapping of bank 00 reads/writes
* - For now, always allow address bit 17 to access auxillary memory where
* c029 bit 0 is on (TODO: handle off cases when they come up)
* - For now, assume Bank 00, 01 shadowing (bit 4 of c029 is off) until we
* need to run the ninja force demo for testing shadowing for all banks
*
* - Bank 01, E1 access will override softswitch main/aux setting
* - Bank 00, E0 access will set the target bank bit 1 based on softswitch
* main/aux
* - 00, E0 special case page 00, 01, D0-DF, etc based on softswitches
* - Solution seems to have a page map that maps access to main or aux memory
* - Page map should include shadowing instructions for writes
* - There only needs to be three page maps - 00/E0, 01/E1, and the 1:1
* direct mapping version (or add a compare/branch each read/write)
* - Each bank has a page map template
* Each page has a 'target' (0 or 1 bank) and page (many will map 1:1)
* Each page has a shadow-bit to shadow writes to the Mega2 bank
*/
static void _clem_mmio_memory_map(ClemensMMIO *mmio, uint32_t memory_flags);
static void _clem_mmio_shadow_map(ClemensMMIO *mmio, uint32_t shadow_flags);
static void _clem_mmio_create_page_direct_mapping(struct ClemensMemoryPageInfo *page,
uint8_t page_idx) {
page->read = page_idx;
page->write = page_idx;
page->flags = CLEM_MEM_PAGE_WRITEOK_FLAG | CLEM_MEM_PAGE_DIRECT_FLAG;
}
static void _clem_mmio_create_page_mainaux_mapping(struct ClemensMemoryPageInfo *page,
uint8_t page_idx, uint8_t bank_idx) {
page->bank_read = bank_idx;
page->bank_write = bank_idx;
page->read = page_idx;
page->write = page_idx;
page->flags = CLEM_MEM_PAGE_WRITEOK_FLAG | CLEM_MEM_PAGE_MAINAUX_FLAG;
}
static void _clem_mmio_clear_irq(ClemensMMIO *mmio, unsigned irq_flags) {
if (irq_flags & CLEM_IRQ_VGC_MASK) {
mmio->vgc.irq_line &= ~(irq_flags & CLEM_IRQ_VGC_MASK);
mmio->irq_line &= ~(irq_flags & CLEM_IRQ_VGC_MASK);
}
if (irq_flags & CLEM_IRQ_TIMER_MASK) {
mmio->dev_timer.irq_line &= ~(irq_flags & CLEM_IRQ_TIMER_MASK);
mmio->irq_line &= ~(irq_flags & CLEM_IRQ_TIMER_MASK);
}
if (irq_flags & CLEM_IRQ_ADB_MASK) {
mmio->dev_adb.irq_line &= ~(irq_flags & CLEM_IRQ_ADB_MASK);
mmio->irq_line &= ~(irq_flags & CLEM_IRQ_ADB_MASK);
}
}
static inline uint8_t _clem_mmio_newvideo_c029(ClemensMMIO *mmio) { return mmio->new_video_c029; }
static inline void _clem_mmio_newvideo_c029_set(ClemensMMIO *mmio, uint8_t value) {
uint8_t setflags = mmio->new_video_c029 ^ value;
if (setflags & CLEM_MMIO_NEWVIDEO_BANKLATCH_INHIBIT) {
if (!(value & CLEM_MMIO_NEWVIDEO_BANKLATCH_INHIBIT)) {
CLEM_UNIMPLEMENTED("ioreg %02X : %02X", CLEM_MMIO_REG_NEWVIDEO, value);
}
setflags ^= CLEM_MMIO_NEWVIDEO_BANKLATCH_INHIBIT;
}
if (setflags & CLEM_MMIO_NEWVIDEO_SUPERHIRES_ENABLE) {
if (value & CLEM_MMIO_NEWVIDEO_SUPERHIRES_ENABLE) {
clem_vgc_set_mode(&mmio->vgc, CLEM_VGC_SUPER_HIRES);
} else {
clem_vgc_clear_mode(&mmio->vgc, CLEM_VGC_SUPER_HIRES);
}
CLEM_DEBUG("clem_mem: c029 super hires = %u",
(value & CLEM_MMIO_NEWVIDEO_SUPERHIRES_ENABLE) != 0);
setflags ^= CLEM_MMIO_NEWVIDEO_SUPERHIRES_ENABLE;
}
/* TODO: what happens if this is set with super hires turned off,
this behvaior is assumed when in super-hires mode by
implementation
*/
if (setflags & CLEM_MMIO_NEWVIDEO_LINEARIZE_MEMORY) {
setflags ^= CLEM_MMIO_NEWVIDEO_LINEARIZE_MEMORY;
}
CLEM_ASSERT(setflags == 0);
mmio->new_video_c029 = value & ~0x1e; /* bits 1-4 are not used */
}
static void _clem_mmio_slotrom_select_c02d(ClemensMMIO *mmio, uint8_t data) {
int i;
unsigned slot_mask =
CLEM_MEM_IO_MMAP_CROM & (~(CLEM_MEM_IO_MMAP_CXROM | CLEM_MEM_IO_MMAP_C3ROM));
unsigned mmap_register = mmio->mmap_register & ~slot_mask;
slot_mask = 0;
for (i = 1; i < 8; ++i) {
if (i == 3)
continue;
slot_mask = CLEM_MEM_IO_MMAP_C1ROM << (i - 1);
if (data & (1 << i)) {
mmap_register |= slot_mask;
} else {
mmap_register &= ~slot_mask;
}
}
_clem_mmio_memory_map(mmio, mmap_register);
}
static uint8_t _clem_mmio_slotromsel_c02d(ClemensMMIO *mmio) {
uint8_t mask = 0;
for (int i = 1; i < 8; ++i) {
if (i == 3)
continue;
if (mmio->mmap_register & (CLEM_MEM_IO_MMAP_C1ROM << (i - 1))) {
mask |= (1 << i);
} else {
mask &= ~(1 << i);
}
}
return mask;
}
static inline uint8_t _clem_mmio_shadow_c035(ClemensMMIO *mmio) {
uint8_t result = 0;
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_NSHADOW_TXT1)
result |= 0x01;
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_NSHADOW_HGR1)
result |= 0x02;
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_NSHADOW_HGR2)
result |= 0x04;
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_NSHADOW_SHGR)
result |= 0x08;
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_NSHADOW_AUX)
result |= 0x10;
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_NSHADOW_TXT2)
result |= 0x20;
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_NIOLC)
result |= 0x40;
return result;
}
static void _clem_mmio_shadow_c035_set(ClemensMMIO *mmio, uint8_t value) {
unsigned mmap = mmio->mmap_register;
if (value & 0x01)
mmap |= CLEM_MEM_IO_MMAP_NSHADOW_TXT1;
else
mmap &= ~CLEM_MEM_IO_MMAP_NSHADOW_TXT1;
if (value & 0x02)
mmap |= CLEM_MEM_IO_MMAP_NSHADOW_HGR1;
else
mmap &= ~CLEM_MEM_IO_MMAP_NSHADOW_HGR1;
if (value & 0x04)
mmap |= CLEM_MEM_IO_MMAP_NSHADOW_HGR2;
else
mmap &= ~CLEM_MEM_IO_MMAP_NSHADOW_HGR2;
if (value & 0x08)
mmap |= CLEM_MEM_IO_MMAP_NSHADOW_SHGR;
else
mmap &= ~CLEM_MEM_IO_MMAP_NSHADOW_SHGR;
if (value & 0x10)
mmap |= CLEM_MEM_IO_MMAP_NSHADOW_AUX;
else
mmap &= ~CLEM_MEM_IO_MMAP_NSHADOW_AUX;
if (value & 0x20)
mmap |= CLEM_MEM_IO_MMAP_NSHADOW_TXT2;
else
mmap &= ~CLEM_MEM_IO_MMAP_NSHADOW_TXT2;
if (value & 0x40)
mmap |= CLEM_MEM_IO_MMAP_NIOLC;
else
mmap &= ~CLEM_MEM_IO_MMAP_NIOLC;
_clem_mmio_memory_map(mmio, mmap);
}
static void _clem_mmio_speed_c036_set(ClemensMMIO *mmio, struct ClemensTimeSpec *tspec,
uint8_t value) {
uint8_t setflags = mmio->speed_c036 ^ value;
if (setflags & CLEM_MMIO_SPEED_FAST_ENABLED) {
if (value & CLEM_MMIO_SPEED_FAST_ENABLED && !mmio->dev_iwm.disk_motor_on) {
// CLEM_LOG("C036: Fast Mode");
tspec->clocks_step = tspec->clocks_step_fast;
} else {
// CLEM_LOG("C036: Slow Mode");
tspec->clocks_step = CLEM_CLOCKS_PHI0_CYCLE;
}
}
if (setflags & CLEM_MMIO_SPEED_POWERED_ON) {
if (value & CLEM_MMIO_SPEED_POWERED_ON) {
CLEM_DEBUG("C036: Powered On SET");
} else {
CLEM_DEBUG("C036: Powered On CLEARED");
}
}
/*
if (setflags & CLEM_MMIO_SPEED_DISK_FLAGS) {
CLEM_LOG("C036: Disk motor detect mask: %02X",
value & CLEM_MMIO_SPEED_DISK_FLAGS);
}
*/
/* bit 5 should always be 0 */
/* for ROM 3, bit 6 can be on or off - for ROM 1, must be off */
mmio->speed_c036 = (value & 0xdf);
}
static void _clem_mmio_mega2_inten_set(ClemensMMIO *mmio, uint8_t data) {
if (data & 0xe0) {
CLEM_WARN("clem_mmio: invalid inten set %02X", data);
}
if (data & 0x10) {
mmio->dev_timer.flags |= CLEM_MMIO_TIMER_QSEC_ENABLED;
} else {
mmio->dev_timer.flags &= ~CLEM_MMIO_TIMER_QSEC_ENABLED;
_clem_mmio_clear_irq(mmio, CLEM_IRQ_TIMER_QSEC);
}
if (data & 0x08) {
clem_vgc_set_mode(&mmio->vgc, CLEM_VGC_ENABLE_VBL_IRQ);
} else {
clem_vgc_clear_mode(&mmio->vgc, CLEM_VGC_ENABLE_VBL_IRQ);
_clem_mmio_clear_irq(mmio, CLEM_IRQ_VGC_BLANK);
}
if (data & 0x07) {
CLEM_WARN("clem_mmio: mega2 mouse not impl - set %02X", data);
}
}
static uint8_t _clem_mmio_mega2_inten_get(ClemensMMIO *mmio) {
uint8_t res = 0x00;
if (mmio->dev_timer.flags & CLEM_MMIO_TIMER_QSEC_ENABLED) {
res |= 0x10;
}
if (mmio->vgc.mode_flags & CLEM_VGC_ENABLE_VBL_IRQ) {
res |= 0x08;
}
return res;
}
static uint8_t _clem_mmio_inttype_c046(ClemensMMIO *mmio) {
uint8_t result = 0x0; // mmio->irq_line ? CLEM_MMIO_INTTYPE_IRQ : 0;
if (mmio->dev_timer.flags & CLEM_MMIO_TIMER_QSEC_IRQ) {
result |= CLEM_MMIO_INTTYPE_QSEC;
}
if (mmio->vgc.irq_vbl) {
result |= CLEM_MMIO_INTTYPE_VBL;
}
/* TODO: AN3, Mouse */
return result;
}
static void _clem_mmio_clrvblint_c047(ClemensMMIO *mmio) {
mmio->vgc.irq_vbl = false;
mmio->dev_timer.flags &= ~CLEM_MMIO_TIMER_QSEC_IRQ;
_clem_mmio_clear_irq(mmio, CLEM_IRQ_TIMER_QSEC | CLEM_IRQ_VGC_BLANK);
}
static void _clem_mmio_vgc_irq_c023_set(ClemensMMIO *mmio, uint8_t data) {
if (data & 0x4) {
mmio->dev_timer.flags |= CLEM_MMIO_TIMER_1SEC_ENABLED;
} else {
mmio->dev_timer.flags &= ~CLEM_MMIO_TIMER_1SEC_ENABLED;
_clem_mmio_clear_irq(mmio, CLEM_IRQ_TIMER_RTC_1SEC);
}
if (data & 0x2) {
clem_vgc_scanline_enable_int(&mmio->vgc, true);
} else {
clem_vgc_scanline_enable_int(&mmio->vgc, false);
}
}
static uint8_t _clem_mmio_vgc_irq_c023_get(ClemensMMIO *mmio) {
uint8_t res = 0x00;
if (mmio->irq_line & (CLEM_IRQ_VGC_SCAN_LINE + CLEM_IRQ_TIMER_RTC_1SEC)) {
res |= 0x80;
if (mmio->irq_line & CLEM_IRQ_TIMER_RTC_1SEC) {
res |= 0x40;
}
if (mmio->irq_line & CLEM_IRQ_VGC_SCAN_LINE) {
res |= 0x20;
}
}
if (mmio->dev_timer.flags & CLEM_MMIO_TIMER_1SEC_ENABLED) {
res |= 0x04;
}
if (mmio->vgc.scanline_irq_enable) {
res |= 0x02;
}
return res;
}
/* For why we don't follow the HW Ref, see important changes documented for
STATEREG here:
http://www.1000bit.it/support/manuali/apple/technotes/iigs/tn.iigs.030.html
*/
static inline uint8_t _clem_mmio_statereg_c068(ClemensMMIO *mmio) {
uint8_t value = 0x00;
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_ALTZPLC) {
value |= 0x80;
}
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_TXTPAGE2) {
value |= 0x40;
}
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_RAMRD) {
value |= 0x20;
}
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_RAMWRT) {
value |= 0x10;
}
if (!(mmio->mmap_register & CLEM_MEM_IO_MMAP_RDLCRAM)) {
value |= 0x08;
}
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_LCBANK2) {
value |= 0x04;
}
if (!(mmio->mmap_register & CLEM_MEM_IO_MMAP_CXROM)) {
value |= 0x01;
}
return value;
}
static uint8_t _clem_mmio_statereg_c068_set(ClemensMMIO *mmio, uint8_t value) {
uint32_t mmap_register = mmio->mmap_register;
/* ALTZP */
if (value & 0x80) {
mmap_register |= CLEM_MEM_IO_MMAP_ALTZPLC;
} else {
mmap_register &= ~CLEM_MEM_IO_MMAP_ALTZPLC;
}
/* PAGE2 text - TODO when video options are fleshed out */
if (value & 0x40) {
mmap_register |= CLEM_MEM_IO_MMAP_TXTPAGE2;
} else {
mmap_register &= ~CLEM_MEM_IO_MMAP_TXTPAGE2;
}
/* RAMRD */
if (value & 0x20) {
mmap_register |= CLEM_MEM_IO_MMAP_RAMRD;
} else {
mmap_register &= ~CLEM_MEM_IO_MMAP_RAMRD;
}
/* RAMWRT */
if (value & 0x10) {
mmap_register |= CLEM_MEM_IO_MMAP_RAMWRT;
} else {
mmap_register &= ~CLEM_MEM_IO_MMAP_RAMWRT;
}
/* RDROM */
if (value & 0x08) {
mmap_register &= ~CLEM_MEM_IO_MMAP_RDLCRAM;
} else {
mmap_register |= CLEM_MEM_IO_MMAP_RDLCRAM;
}
/* LCBNK2 */
if (value & 0x04) {
mmap_register |= CLEM_MEM_IO_MMAP_LCBANK2;
} else {
mmap_register &= ~CLEM_MEM_IO_MMAP_LCBANK2;
}
/* ROMBANK always 0 */
if (value & 0x02) {
/* do not set */
CLEM_WARN("c068 %02X not allowed", value);
} else {
/* only valid value */
}
/* INTCXROM */
if (value & 0x01) {
mmap_register &= ~CLEM_MEM_IO_MMAP_CXROM;
} else {
mmap_register |= CLEM_MEM_IO_MMAP_CXROM;
}
_clem_mmio_memory_map(mmio, mmap_register);
return 0;
}
static void _clem_mmio_rw_bank_select(ClemensMMIO *mmio, uint16_t address) {
uint32_t memory_flags = mmio->mmap_register;
uint16_t last_data_address = mmio->last_data_address & 0xffff;
uint8_t ioreg = (address & 0xff);
/* odd address access will enable ram writes first before their other ops
which handles applications that perform single reads on the odd
addressed softswitches after a prior write-enable double read switch.
this seems to jive with the documentation on these softswitches, which
assumes that the dual write is to perform */
switch (ioreg) {
case CLEM_MMIO_REG_LC2_RAM_WP:
case CLEM_MMIO_REG_LC2_RAM_WP2:
memory_flags |= (CLEM_MEM_IO_MMAP_RDLCRAM + CLEM_MEM_IO_MMAP_LCBANK2);
if (last_data_address == address) {
memory_flags &= ~CLEM_MEM_IO_MMAP_WRLCRAM;
}
break;
case CLEM_MMIO_REG_LC2_ROM_WE:
case CLEM_MMIO_REG_LC2_ROM_WE2:
memory_flags |= CLEM_MEM_IO_MMAP_LCBANK2;
memory_flags &= ~CLEM_MEM_IO_MMAP_RDLCRAM;
if (last_data_address == address) {
memory_flags |= CLEM_MEM_IO_MMAP_WRLCRAM;
}
break;
case CLEM_MMIO_REG_LC2_ROM_WP:
case CLEM_MMIO_REG_LC2_ROM_WP2:
memory_flags &= ~(CLEM_MEM_IO_MMAP_RDLCRAM);
memory_flags |= CLEM_MEM_IO_MMAP_LCBANK2;
if (last_data_address == address) {
memory_flags &= ~CLEM_MEM_IO_MMAP_WRLCRAM;
}
break;
case CLEM_MMIO_REG_LC2_RAM_WE:
case CLEM_MMIO_REG_LC2_RAM_WE2:
memory_flags |= (CLEM_MEM_IO_MMAP_RDLCRAM + CLEM_MEM_IO_MMAP_LCBANK2);
if (last_data_address == address) {
memory_flags |= CLEM_MEM_IO_MMAP_WRLCRAM;
}
break;
case CLEM_MMIO_REG_LC1_RAM_WP:
case CLEM_MMIO_REG_LC1_RAM_WP2:
memory_flags &= ~(CLEM_MEM_IO_MMAP_LCBANK2);
memory_flags |= CLEM_MEM_IO_MMAP_RDLCRAM;
if (last_data_address == address) {
memory_flags &= ~CLEM_MEM_IO_MMAP_WRLCRAM;
}
break;
case CLEM_MMIO_REG_LC1_ROM_WE:
case CLEM_MMIO_REG_LC1_ROM_WE2:
memory_flags &= ~(CLEM_MEM_IO_MMAP_RDLCRAM + CLEM_MEM_IO_MMAP_LCBANK2);
if (last_data_address == address) {
memory_flags |= CLEM_MEM_IO_MMAP_WRLCRAM;
}
break;
case CLEM_MMIO_REG_LC1_ROM_WP:
case CLEM_MMIO_REG_LC1_ROM_WP2:
memory_flags &= ~(CLEM_MEM_IO_MMAP_LCBANK2 + CLEM_MEM_IO_MMAP_RDLCRAM);
if (last_data_address == address) {
memory_flags &= ~CLEM_MEM_IO_MMAP_WRLCRAM;
}
break;
case CLEM_MMIO_REG_LC1_RAM_WE:
case CLEM_MMIO_REG_LC1_RAM_WE2:
memory_flags |= CLEM_MEM_IO_MMAP_RDLCRAM;
memory_flags &= ~CLEM_MEM_IO_MMAP_LCBANK2;
if (last_data_address == address) {
memory_flags |= CLEM_MEM_IO_MMAP_WRLCRAM;
}
break;
}
if (memory_flags != mmio->mmap_register) {
_clem_mmio_memory_map(mmio, memory_flags);
}
}
static uint8_t _clem_mmio_card_io_read(ClemensCard *card, struct ClemensClock *clock, uint8_t addr,
uint8_t flags) {
uint8_t result = 0;
if (card) {
if (!(flags & CLEM_OP_IO_NO_OP)) {
(*card->io_sync)(clock, card->context);
}
(*card->io_read)(clock, &result, addr, flags, card->context);
}
return result;
}
static uint8_t _clem_mmio_floating_bus(ClemensMMIO *mmio, struct ClemensTimeSpec *tspec) {
// The floating bus is basically data that is read from video memory given no other
// source (I/O, FPI RAM). This occurs on the 2nd half of a 1mhz cycle in hardware.
// Here, the clem_mmio_read() function will selectively pick up this data if reading
// an I/O register that acts as a switch but doesn't return data.
//
// Its unknown if Super-hires counts. (edit) The floating bus emulation here
// works like it did on the Apple II
//
// http://www.deater.net/weave/vmwprod/megademo/vapor_lock.html
//
// TODO: The implementation here likely isn't accurate as pointed out on
// the Apple 2 slack channel for the Mega II (i.e. what happens with SHR mode
// as I believe that mode overrides any Apple II video mode switches.)
// A good test would be to try the vapor lock tests on a real GS and
// witness if they work. That still doesn't answer the SHR mode
// question.
struct ClemensClock clock;
struct ClemensScanline *scanline;
enum ClemensVideoFormat video_type;
unsigned h_counter, v_counter;
clock.ts = tspec->clocks_spent;
clock.ref_step = CLEM_CLOCKS_PHI0_CYCLE;
clem_vgc_calc_counters(&mmio->vgc, &clock, &v_counter, &h_counter);
if (v_counter >= CLEM_VGC_HGR_SCANLINE_COUNT) {
// bus has no values during a blank - no real way to illustrate this beyond
// returning 0
return 0;
}
if (h_counter < 25) {
// HBLANK no video data
return 0;
}
h_counter -= 25; // point to start of visible data on line
// video_type will direct us to scanline type where:
// lores or text use text scanlines
// hires uses hires scanlines
if (mmio->vgc.mode_flags & CLEM_VGC_HIRES) {
video_type = kClemensVideoFormat_Hires;
if (mmio->vgc.mode_flags & CLEM_VGC_MIXED_TEXT) {
if (v_counter >= 160) {
video_type = kClemensVideoFormat_Text;
}
}
} else {
video_type = kClemensVideoFormat_Text;
}
// read from PAGE1, PAGE2?
if (video_type == kClemensVideoFormat_Text) {
// 80 column only supports page 1
// TODO: re-read from main memory? or point to aux if in 80-column mode?
v_counter >>= 3;
if ((mmio->mmap_register & CLEM_MEM_IO_MMAP_TXTPAGE2) &&
!(mmio->mmap_register & CLEM_MEM_IO_MMAP_80COLSTORE)) {
scanline = mmio->vgc.text_2_scanlines;
} else {
scanline = mmio->vgc.text_1_scanlines;
}
} else {
if (mmio->mmap_register & CLEM_MEM_IO_MMAP_TXTPAGE2) {
scanline = mmio->vgc.hgr_2_scanlines;
} else {
scanline = mmio->vgc.hgr_1_scanlines;
}
}
scanline = &scanline[v_counter];
return mmio->e0_bank[scanline->offset + h_counter];
}
uint8_t clem_mmio_read(ClemensMMIO *mmio, struct ClemensTimeSpec *tspec, uint16_t addr,
uint8_t flags, bool *mega2_access) {
struct ClemensClock ref_clock;
uint8_t result = 0x00;
uint8_t ioreg = addr & 0xff;
bool is_noop = (flags & CLEM_OP_IO_NO_OP) != 0;
// SHADOW, CYA, DMA are fast
// SLOT, STATE are fast (read-only)
*mega2_access = true;
ref_clock.ts = tspec->clocks_spent;
ref_clock.ref_step = *mega2_access ? CLEM_CLOCKS_PHI0_CYCLE : tspec->clocks_step;
if (flags & CLEM_OP_IO_CARD) {
uint8_t slot_idx;
if (addr == 0xCFFF) {
/* TODO: CFFF access */
} else if (addr < 0xCFFF && addr >= 0xC800) {
slot_idx = (uint8_t)(mmio->card_expansion_rom_index & 0xff);
if (slot_idx > 0 && slot_idx <= 7) {
result = mmio->card_slot_expansion_memory[slot_idx - 1][addr - 0xc800];
}
} else if (addr >= 0xC100) {
slot_idx = (uint8_t)(addr >> 8) - 0xc0 - 1;
if (mmio->card_slot[slot_idx]) {
result = _clem_mmio_card_io_read(mmio->card_slot[slot_idx], &ref_clock, ioreg,
flags | CLEM_OP_IO_DEVSEL);
}
}
return result;
}
switch (ioreg) {
case CLEM_MMIO_REG_KEYB_READ:
case CLEM_MMIO_REG_KEYB_READ + 1:
case CLEM_MMIO_REG_KEYB_READ + 2:
case CLEM_MMIO_REG_KEYB_READ + 3:
case CLEM_MMIO_REG_KEYB_READ + 4:
case CLEM_MMIO_REG_KEYB_READ + 5:
case CLEM_MMIO_REG_KEYB_READ + 6:
case CLEM_MMIO_REG_KEYB_READ + 7:
case CLEM_MMIO_REG_KEYB_READ + 8:
case CLEM_MMIO_REG_KEYB_READ + 9:
case CLEM_MMIO_REG_KEYB_READ + 10:
case CLEM_MMIO_REG_KEYB_READ + 11:
case CLEM_MMIO_REG_KEYB_READ + 12:
case CLEM_MMIO_REG_KEYB_READ + 13:
case CLEM_MMIO_REG_KEYB_READ + 14:
case CLEM_MMIO_REG_KEYB_READ + 15:
case CLEM_MMIO_REG_ANYKEY_STROBE:
result = clem_adb_read_mega2_switch(&mmio->dev_adb, ioreg, flags);
break;
case CLEM_MMIO_REG_ADB_MOUSE_DATA:
case CLEM_MMIO_REG_ADB_MODKEY:
case CLEM_MMIO_REG_ADB_CMD_DATA:
case CLEM_MMIO_REG_ADB_STATUS:
result = clem_adb_read_switch(&mmio->dev_adb, ioreg, flags);
break;
case CLEM_MMIO_REG_LC_BANK_TEST:
result = (mmio->mmap_register & CLEM_MEM_IO_MMAP_LCBANK2) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_ROM_RAM_TEST:
result = (mmio->mmap_register & CLEM_MEM_IO_MMAP_RDLCRAM) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_RAMRD_TEST:
result = (mmio->mmap_register & CLEM_MEM_IO_MMAP_RAMRD) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_RAMWRT_TEST:
result = (mmio->mmap_register & CLEM_MEM_IO_MMAP_RAMWRT) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_READCXROM:
result = !(mmio->mmap_register & CLEM_MEM_IO_MMAP_CXROM) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_RDALTZP_TEST:
result = (mmio->mmap_register & CLEM_MEM_IO_MMAP_ALTZPLC) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_READC3ROM:
result = (mmio->mmap_register & CLEM_MEM_IO_MMAP_C3ROM) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_80COLSTORE_TEST:
result = (mmio->mmap_register & CLEM_MEM_IO_MMAP_80COLSTORE) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_VBLBAR:
case CLEM_MMIO_REG_VGC_VERTCNT:
case CLEM_MMIO_REG_VGC_HORIZCNT:
result = clem_vgc_read_switch(&mmio->vgc, &ref_clock, ioreg, flags);
break;
case CLEM_MMIO_REG_TXT_TEST:
result = (mmio->vgc.mode_flags & CLEM_VGC_GRAPHICS_MODE) ? 0x00 : 0x80;
break;
case CLEM_MMIO_REG_MIXED_TEST:
result = (mmio->vgc.mode_flags & CLEM_VGC_MIXED_TEXT) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_TXTPAGE2_TEST:
result = (mmio->mmap_register & CLEM_MEM_IO_MMAP_TXTPAGE2) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_ALTCHARSET_TEST:
result = (mmio->vgc.mode_flags & CLEM_VGC_ALTCHARSET) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_HIRES_TEST:
result = (mmio->vgc.mode_flags & CLEM_VGC_HIRES) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_80COLUMN_TEST:
result = (mmio->vgc.mode_flags & CLEM_VGC_80COLUMN_TEXT) ? 0x80 : 0x00;
break;
case CLEM_MMIO_REG_CASSETTE_PORT_NOP:
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_VGC_TEXT_COLOR:
result = (uint8_t)((mmio->vgc.text_fg_color << 4) | mmio->vgc.text_bg_color);
break;
case CLEM_MMIO_REG_VGC_IRQ_BYTE:
result = _clem_mmio_vgc_irq_c023_get(mmio);
break;
case CLEM_MMIO_REG_NEWVIDEO:
result = _clem_mmio_newvideo_c029(mmio);
break;
case CLEM_MMIO_REG_NEWVIDEO + 1:
// to avoid the uimpl read warning since GS/OS will often set/query NEWVIDEO as a 16-bit (2
// byte) operation
break;
case CLEM_MMIO_REG_LANGSEL:
result = clem_vgc_get_region(&mmio->vgc);
break;
case CLEM_MMIO_REG_CHARROM_TEST:
result = 0x00; // TODO: unsure what to do unless we store the character ROM in memory vs font files
break;
case CLEM_MMIO_REG_SLOTROMSEL:
result = _clem_mmio_slotromsel_c02d(mmio);
*mega2_access = false;
break;
case CLEM_MMIO_REG_SPKR:
clem_sound_read_switch(&mmio->dev_audio, ioreg, flags);
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_DISK_INTERFACE:
result = clem_iwm_read_switch(&mmio->dev_iwm, &mmio->active_drives, tspec, ioreg, flags);
break;
case CLEM_MMIO_REG_RTC_VGC_SCANINT:
result = clem_vgc_read_switch(&mmio->vgc, &ref_clock, ioreg, flags);
break;
case CLEM_MMIO_REG_SHADOW:
result = _clem_mmio_shadow_c035(mmio);
*mega2_access = false;
break;
case CLEM_MMIO_REG_SPEED:
result = mmio->speed_c036;
*mega2_access = false;
break;
// TODO: DMA? fast access as well
case CLEM_MMIO_REG_RTC_CTL:
if (!is_noop) {
clem_rtc_command(&mmio->dev_rtc, tspec->clocks_spent, CLEM_IO_READ);
}
result = mmio->dev_rtc.ctl_c034;
break;
case CLEM_MMIO_REG_RTC_DATA:
result = mmio->dev_rtc.data_c033;
break;
case CLEM_MMIO_REG_SCC_B_CMD:
case CLEM_MMIO_REG_SCC_A_CMD:
case CLEM_MMIO_REG_SCC_B_DATA:
case CLEM_MMIO_REG_SCC_A_DATA:
result = clem_scc_read_switch(&mmio->dev_scc, ioreg, flags);
break;
case CLEM_MMIO_REG_AUDIO_CTL:
result = clem_sound_read_switch(&mmio->dev_audio, ioreg, flags);
break;
case CLEM_MMIO_REG_AUDIO_DATA:
result = clem_sound_read_switch(&mmio->dev_audio, ioreg, flags);
break;
case CLEM_MMIO_REG_AUDIO_ADRLO:
result = clem_sound_read_switch(&mmio->dev_audio, ioreg, flags);
break;
case CLEM_MMIO_REG_AUDIO_ADRHI:
result = clem_sound_read_switch(&mmio->dev_audio, ioreg, flags);
break;
case CLEM_MMIO_REG_MEGA2_INTEN:
result = _clem_mmio_mega2_inten_get(mmio);
break;
case CLEM_MMIO_REG_MEGA2_MOUSE_DX:
case CLEM_MMIO_REG_MEGA2_MOUSE_DY:
result = clem_adb_read_mega2_switch(&mmio->dev_adb, ioreg, flags);
break;
case CLEM_MMIO_REG_DIAG_INTTYPE:
result = _clem_mmio_inttype_c046(mmio);
break;
case CLEM_MMIO_REG_CLRVBLINT:
if (!(flags & CLEM_OP_IO_NO_OP)) {
_clem_mmio_clrvblint_c047(mmio);
}
break;
case CLEM_MMIO_REG_EMULATOR:
if (mmio->emulator_detect == CLEM_MMIO_EMULATOR_DETECT_START) {
result = CLEM_EMULATOR_ID;
mmio->emulator_detect = CLEM_MMIO_EMULATOR_DETECT_VERSION;
} else if (mmio->emulator_detect == CLEM_MMIO_EMULATOR_DETECT_VERSION) {
result = CLEM_EMULATOR_VER;
mmio->emulator_detect = CLEM_MMIO_EMULATOR_DETECT_IDLE;
}
break;
case CLEM_MMIO_REG_TXTCLR:
if (!(flags & CLEM_OP_IO_NO_OP)) {
clem_vgc_set_mode(&mmio->vgc, CLEM_VGC_GRAPHICS_MODE);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_TXTSET:
if (!(flags & CLEM_OP_IO_NO_OP)) {
clem_vgc_clear_mode(&mmio->vgc, CLEM_VGC_GRAPHICS_MODE);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_MIXCLR:
if (!(flags & CLEM_OP_IO_NO_OP)) {
clem_vgc_clear_mode(&mmio->vgc, CLEM_VGC_MIXED_TEXT);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_MIXSET:
if (!(flags & CLEM_OP_IO_NO_OP)) {
clem_vgc_set_mode(&mmio->vgc, CLEM_VGC_MIXED_TEXT);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_TXTPAGE1:
if (!(flags & CLEM_OP_IO_NO_OP)) {
_clem_mmio_memory_map(mmio, mmio->mmap_register & ~CLEM_MEM_IO_MMAP_TXTPAGE2);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_TXTPAGE2:
if (!(flags & CLEM_OP_IO_NO_OP)) {
_clem_mmio_memory_map(mmio, mmio->mmap_register | CLEM_MEM_IO_MMAP_TXTPAGE2);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_LORES:
/* implicitly clears hires */
if (!(flags & CLEM_OP_IO_NO_OP)) {
clem_vgc_set_mode(&mmio->vgc, CLEM_VGC_LORES);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_HIRES:
/* implicitly clears lores */
if (!(flags & CLEM_OP_IO_NO_OP)) {
clem_vgc_set_mode(&mmio->vgc, CLEM_VGC_HIRES);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_AN0_OFF:
case CLEM_MMIO_REG_AN0_ON:
case CLEM_MMIO_REG_AN1_OFF:
case CLEM_MMIO_REG_AN1_ON:
case CLEM_MMIO_REG_AN2_OFF:
case CLEM_MMIO_REG_AN2_ON:
case CLEM_MMIO_REG_SW0:
case CLEM_MMIO_REG_SW1:
case CLEM_MMIO_REG_SW2:
case CLEM_MMIO_REG_SW3:
result = clem_adb_read_switch(&mmio->dev_adb, ioreg, flags);
break;
case CLEM_MMIO_REG_AN3_OFF:
case CLEM_MMIO_REG_AN3_ON:
/* AN3 used for double hires graphics */
if (!is_noop) {
if (ioreg == CLEM_MMIO_REG_AN3_ON) {
clem_vgc_clear_mode(&mmio->vgc, CLEM_VGC_DISABLE_AN3);
} else {
clem_vgc_set_mode(&mmio->vgc, CLEM_VGC_DISABLE_AN3);
}
}
result = clem_adb_read_switch(&mmio->dev_adb, ioreg, flags);
break;
case CLEM_MMIO_REG_PADDL0:
case CLEM_MMIO_REG_PADDL1:
case CLEM_MMIO_REG_PADDL2:
case CLEM_MMIO_REG_PADDL3:
case CLEM_MMIO_REG_PTRIG:
/* note c071 - 7f are reserved for ROM access - used for the
BRK interrupt */
result = clem_adb_read_switch(&mmio->dev_adb, ioreg, flags);
break;
case CLEM_MMIO_REG_STATEREG:
result = _clem_mmio_statereg_c068(mmio);
*mega2_access = false;
break;
case CLEM_MMIO_REG_STATEREG+1:
*mega2_access = false;
break;
case CLEM_MMIO_REG_LC2_RAM_WP:
case CLEM_MMIO_REG_LC2_RAM_WP2:
case CLEM_MMIO_REG_LC2_ROM_WE:
case CLEM_MMIO_REG_LC2_ROM_WE2:
case CLEM_MMIO_REG_LC2_ROM_WP:
case CLEM_MMIO_REG_LC2_ROM_WP2:
case CLEM_MMIO_REG_LC2_RAM_WE:
case CLEM_MMIO_REG_LC2_RAM_WE2:
case CLEM_MMIO_REG_LC1_RAM_WP:
case CLEM_MMIO_REG_LC1_RAM_WP2:
case CLEM_MMIO_REG_LC1_ROM_WE:
case CLEM_MMIO_REG_LC1_ROM_WE2:
case CLEM_MMIO_REG_LC1_ROM_WP:
case CLEM_MMIO_REG_LC1_ROM_WP2:
case CLEM_MMIO_REG_LC1_RAM_WE:
case CLEM_MMIO_REG_LC1_RAM_WE2:
if (!(flags & CLEM_OP_IO_NO_OP)) {
_clem_mmio_rw_bank_select(mmio, addr);
}
result = _clem_mmio_floating_bus(mmio, tspec);
break;
case CLEM_MMIO_REG_IWM_PHASE0_LO:
case CLEM_MMIO_REG_IWM_PHASE0_HI:
case CLEM_MMIO_REG_IWM_PHASE1_LO:
case CLEM_MMIO_REG_IWM_PHASE1_HI:
case CLEM_MMIO_REG_IWM_PHASE2_LO:
case CLEM_MMIO_REG_IWM_PHASE2_HI:
case CLEM_MMIO_REG_IWM_PHASE3_LO:
case CLEM_MMIO_REG_IWM_PHASE3_HI:
case CLEM_MMIO_REG_IWM_DRIVE_DISABLE:
case CLEM_MMIO_REG_IWM_DRIVE_ENABLE:
case CLEM_MMIO_REG_IWM_DRIVE_0:
case CLEM_MMIO_REG_IWM_DRIVE_1:
case CLEM_MMIO_REG_IWM_Q6_LO:
case CLEM_MMIO_REG_IWM_Q6_HI:
case CLEM_MMIO_REG_IWM_Q7_LO:
case CLEM_MMIO_REG_IWM_Q7_HI:
result = clem_iwm_read_switch(&mmio->dev_iwm, &mmio->active_drives, tspec, ioreg, flags);
break;
default:
if (ioreg >= 0x90) {
result = _clem_mmio_card_io_read(mmio->card_slot[(ioreg - 0x90) >> 4], &ref_clock,
ioreg & 0xf, flags);
} else if (!is_noop) {
clem_debug_break(mmio->dev_debug, CLEM_DEBUG_BREAK_UNIMPL_IOREAD, addr, 0x0000);
}
break;
}
return result;
}
static void _clem_mmio_card_io_write(ClemensCard *card, struct ClemensClock *clock, uint8_t data,
uint8_t addr, uint8_t flags) {
if (card) {
if (!(flags & CLEM_OP_IO_NO_OP)) {
(*card->io_sync)(clock, card->context);
}
(*card->io_write)(clock, data, addr, flags, card->context);
}
}
void clem_mmio_write(ClemensMMIO *mmio, struct ClemensTimeSpec *tspec, uint8_t data, uint16_t addr,
uint8_t flags, bool *mega2_access) {
struct ClemensClock ref_clock;
bool is_noop = (flags & CLEM_OP_IO_NO_OP) != 0;
uint8_t ioreg = (addr & 0xff);
// SHADOW, SPEED and DMA are fast
*mega2_access = true;
ref_clock.ts = tspec->clocks_spent;
ref_clock.ref_step = *mega2_access ? CLEM_CLOCKS_PHI0_CYCLE : tspec->clocks_step;
if ((flags & CLEM_OP_IO_CARD) && addr >= 0xC100) {
uint8_t slot_idx = (uint8_t)(addr >> 8) - 0xc0 - 1;
if (mmio->card_slot[slot_idx]) {
_clem_mmio_card_io_write(mmio->card_slot[slot_idx], &ref_clock, data, ioreg,
flags | CLEM_OP_IO_DEVSEL);
}
return;
}
switch (ioreg) {
case CLEM_MMIO_REG_80STOREOFF_WRITE:
_clem_mmio_memory_map(mmio, mmio->mmap_register & ~CLEM_MEM_IO_MMAP_80COLSTORE);
break;
case CLEM_MMIO_REG_80STOREON_WRITE:
_clem_mmio_memory_map(mmio, mmio->mmap_register | CLEM_MEM_IO_MMAP_80COLSTORE);
break;
case CLEM_MMIO_REG_RDMAINRAM:
_clem_mmio_memory_map(mmio, mmio->mmap_register & ~CLEM_MEM_IO_MMAP_RAMRD);
break;
case CLEM_MMIO_REG_RDCARDRAM:
_clem_mmio_memory_map(mmio, mmio->mmap_register | CLEM_MEM_IO_MMAP_RAMRD);
break;
case CLEM_MMIO_REG_WRMAINRAM:
_clem_mmio_memory_map(mmio, mmio->mmap_register & ~CLEM_MEM_IO_MMAP_RAMWRT);
break;