diff --git a/crates/core_arch/src/x86/avx512bf16.rs b/crates/core_arch/src/x86/avx512bf16.rs index 940d3bbd67..85afd91fba 100644 --- a/crates/core_arch/src/x86/avx512bf16.rs +++ b/crates/core_arch/src/x86/avx512bf16.rs @@ -35,7 +35,7 @@ unsafe extern "C" { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651&avx512techs=AVX512_BF16&text=_mm_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm_cvtne2ps_pbh(a: __m128, b: __m128) -> __m128bh { unsafe { transmute(cvtne2ps2bf16(a.as_f32x4(), b.as_f32x4())) } @@ -48,7 +48,7 @@ pub fn _mm_cvtne2ps_pbh(a: __m128, b: __m128) -> __m128bh { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651&avx512techs=AVX512_BF16&text=_mm_mask_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm_mask_cvtne2ps_pbh(src: __m128bh, k: __mmask8, a: __m128, b: __m128) -> __m128bh { unsafe { @@ -64,7 +64,7 @@ pub fn _mm_mask_cvtne2ps_pbh(src: __m128bh, k: __mmask8, a: __m128, b: __m128) - /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651&avx512techs=AVX512_BF16&text=_mm_maskz_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm_maskz_cvtne2ps_pbh(k: __mmask8, a: __m128, b: __m128) -> __m128bh { unsafe { @@ -79,7 +79,7 @@ pub fn _mm_maskz_cvtne2ps_pbh(k: __mmask8, a: __m128, b: __m128) -> __m128bh { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654&avx512techs=AVX512_BF16&text=_mm256_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm256_cvtne2ps_pbh(a: __m256, b: __m256) -> __m256bh { unsafe { transmute(cvtne2ps2bf16_256(a.as_f32x8(), b.as_f32x8())) } @@ -91,7 +91,7 @@ pub fn _mm256_cvtne2ps_pbh(a: __m256, b: __m256) -> __m256bh { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654&avx512techs=AVX512_BF16&text=_mm256_mask_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm256_mask_cvtne2ps_pbh(src: __m256bh, k: __mmask16, a: __m256, b: __m256) -> __m256bh { unsafe { @@ -106,7 +106,7 @@ pub fn _mm256_mask_cvtne2ps_pbh(src: __m256bh, k: __mmask16, a: __m256, b: __m25 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654&avx512techs=AVX512_BF16&text=_mm256_maskz_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm256_maskz_cvtne2ps_pbh(k: __mmask16, a: __m256, b: __m256) -> __m256bh { unsafe { @@ -121,7 +121,7 @@ pub fn _mm256_maskz_cvtne2ps_pbh(k: __mmask16, a: __m256, b: __m256) -> __m256bh /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657&avx512techs=AVX512_BF16&text=_mm512_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm512_cvtne2ps_pbh(a: __m512, b: __m512) -> __m512bh { unsafe { transmute(cvtne2ps2bf16_512(a.as_f32x16(), b.as_f32x16())) } @@ -134,7 +134,7 @@ pub fn _mm512_cvtne2ps_pbh(a: __m512, b: __m512) -> __m512bh { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657&avx512techs=AVX512_BF16&text=_mm512_mask_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm512_mask_cvtne2ps_pbh(src: __m512bh, k: __mmask32, a: __m512, b: __m512) -> __m512bh { unsafe { @@ -150,7 +150,7 @@ pub fn _mm512_mask_cvtne2ps_pbh(src: __m512bh, k: __mmask32, a: __m512, b: __m51 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657&avx512techs=AVX512_BF16&text=_mm512_maskz_cvtne2ps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtne2ps2bf16"))] pub fn _mm512_maskz_cvtne2ps_pbh(k: __mmask32, a: __m512, b: __m512) -> __m512bh { unsafe { @@ -164,7 +164,7 @@ pub fn _mm512_maskz_cvtne2ps_pbh(k: __mmask32, a: __m512, b: __m512) -> __m512bh /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm256_cvtneps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] pub fn _mm256_cvtneps_pbh(a: __m256) -> __m128bh { unsafe { transmute(cvtneps2bf16_256(a.as_f32x8())) } @@ -176,7 +176,7 @@ pub fn _mm256_cvtneps_pbh(a: __m256) -> __m128bh { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm256_mask_cvtneps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] pub fn _mm256_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m256) -> __m128bh { unsafe { @@ -191,7 +191,7 @@ pub fn _mm256_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m256) -> __m128b /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm256_maskz_cvtneps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] pub fn _mm256_maskz_cvtneps_pbh(k: __mmask8, a: __m256) -> __m128bh { unsafe { @@ -205,7 +205,7 @@ pub fn _mm256_maskz_cvtneps_pbh(k: __mmask8, a: __m256) -> __m128bh { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm512_cvtneps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] pub fn _mm512_cvtneps_pbh(a: __m512) -> __m256bh { unsafe { transmute(cvtneps2bf16_512(a.as_f32x16())) } @@ -217,7 +217,7 @@ pub fn _mm512_cvtneps_pbh(a: __m512) -> __m256bh { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm512_mask_cvtneps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] pub fn _mm512_mask_cvtneps_pbh(src: __m256bh, k: __mmask16, a: __m512) -> __m256bh { unsafe { @@ -232,7 +232,7 @@ pub fn _mm512_mask_cvtneps_pbh(src: __m256bh, k: __mmask16, a: __m512) -> __m256 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm512_maskz_cvtneps_pbh) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] pub fn _mm512_maskz_cvtneps_pbh(k: __mmask16, a: __m512) -> __m256bh { unsafe { @@ -247,7 +247,7 @@ pub fn _mm512_maskz_cvtneps_pbh(k: __mmask16, a: __m512) -> __m256bh { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm_dpbf16_ps(src: __m128, a: __m128bh, b: __m128bh) -> __m128 { unsafe { transmute(dpbf16ps(src.as_f32x4(), a.as_i16x8(), b.as_i16x8())) } @@ -260,7 +260,7 @@ pub fn _mm_dpbf16_ps(src: __m128, a: __m128bh, b: __m128bh) -> __m128 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm_mask_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm_mask_dpbf16_ps(src: __m128, k: __mmask8, a: __m128bh, b: __m128bh) -> __m128 { unsafe { @@ -276,7 +276,7 @@ pub fn _mm_mask_dpbf16_ps(src: __m128, k: __mmask8, a: __m128bh, b: __m128bh) -> /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm_maskz_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm_maskz_dpbf16_ps(k: __mmask8, src: __m128, a: __m128bh, b: __m128bh) -> __m128 { unsafe { @@ -292,7 +292,7 @@ pub fn _mm_maskz_dpbf16_ps(k: __mmask8, src: __m128, a: __m128bh, b: __m128bh) - /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm256_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm256_dpbf16_ps(src: __m256, a: __m256bh, b: __m256bh) -> __m256 { unsafe { transmute(dpbf16ps_256(src.as_f32x8(), a.as_i16x16(), b.as_i16x16())) } @@ -305,7 +305,7 @@ pub fn _mm256_dpbf16_ps(src: __m256, a: __m256bh, b: __m256bh) -> __m256 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm256_mask_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm256_mask_dpbf16_ps(src: __m256, k: __mmask8, a: __m256bh, b: __m256bh) -> __m256 { unsafe { @@ -321,7 +321,7 @@ pub fn _mm256_mask_dpbf16_ps(src: __m256, k: __mmask8, a: __m256bh, b: __m256bh) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm256_maskz_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm256_maskz_dpbf16_ps(k: __mmask8, src: __m256, a: __m256bh, b: __m256bh) -> __m256 { unsafe { @@ -338,7 +338,7 @@ pub fn _mm256_maskz_dpbf16_ps(k: __mmask8, src: __m256, a: __m256bh, b: __m256bh /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm512_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm512_dpbf16_ps(src: __m512, a: __m512bh, b: __m512bh) -> __m512 { unsafe { transmute(dpbf16ps_512(src.as_f32x16(), a.as_i16x32(), b.as_i16x32())) } @@ -351,7 +351,7 @@ pub fn _mm512_dpbf16_ps(src: __m512, a: __m512bh, b: __m512bh) -> __m512 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm512_mask_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm512_mask_dpbf16_ps(src: __m512, k: __mmask16, a: __m512bh, b: __m512bh) -> __m512 { unsafe { @@ -367,7 +367,7 @@ pub fn _mm512_mask_dpbf16_ps(src: __m512, k: __mmask16, a: __m512bh, b: __m512bh /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=1769,1651,1654,1657,1660&avx512techs=AVX512_BF16&text=_mm512_maskz_dpbf16_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr("vdpbf16ps"))] pub fn _mm512_maskz_dpbf16_ps(k: __mmask16, src: __m512, a: __m512bh, b: __m512bh) -> __m512 { unsafe { @@ -382,7 +382,7 @@ pub fn _mm512_maskz_dpbf16_ps(k: __mmask16, src: __m512, a: __m512bh, b: __m512b /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtpbh_ps(a: __m256bh) -> __m512 { unsafe { _mm512_castsi512_ps(_mm512_slli_epi32::<16>(_mm512_cvtepi16_epi32(transmute(a)))) } } @@ -394,7 +394,7 @@ pub fn _mm512_cvtpbh_ps(a: __m256bh) -> __m512 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtpbh_ps(src: __m512, k: __mmask16, a: __m256bh) -> __m512 { unsafe { let cvt = _mm512_cvtpbh_ps(a); @@ -409,7 +409,7 @@ pub fn _mm512_mask_cvtpbh_ps(src: __m512, k: __mmask16, a: __m256bh) -> __m512 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtpbh_ps(k: __mmask16, a: __m256bh) -> __m512 { unsafe { let cvt = _mm512_cvtpbh_ps(a); @@ -423,7 +423,7 @@ pub fn _mm512_maskz_cvtpbh_ps(k: __mmask16, a: __m256bh) -> __m512 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtpbh_ps(a: __m128bh) -> __m256 { unsafe { _mm256_castsi256_ps(_mm256_slli_epi32::<16>(_mm256_cvtepi16_epi32(transmute(a)))) } } @@ -435,7 +435,7 @@ pub fn _mm256_cvtpbh_ps(a: __m128bh) -> __m256 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtpbh_ps(src: __m256, k: __mmask8, a: __m128bh) -> __m256 { unsafe { let cvt = _mm256_cvtpbh_ps(a); @@ -450,7 +450,7 @@ pub fn _mm256_mask_cvtpbh_ps(src: __m256, k: __mmask8, a: __m128bh) -> __m256 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtpbh_ps(k: __mmask8, a: __m128bh) -> __m256 { unsafe { let cvt = _mm256_cvtpbh_ps(a); @@ -464,7 +464,7 @@ pub fn _mm256_maskz_cvtpbh_ps(k: __mmask8, a: __m128bh) -> __m256 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtpbh_ps(a: __m128bh) -> __m128 { unsafe { _mm_castsi128_ps(_mm_slli_epi32::<16>(_mm_cvtepi16_epi32(transmute(a)))) } } @@ -476,7 +476,7 @@ pub fn _mm_cvtpbh_ps(a: __m128bh) -> __m128 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtpbh_ps(src: __m128, k: __mmask8, a: __m128bh) -> __m128 { unsafe { let cvt = _mm_cvtpbh_ps(a); @@ -491,7 +491,7 @@ pub fn _mm_mask_cvtpbh_ps(src: __m128, k: __mmask8, a: __m128bh) -> __m128 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_cvtpbh_ps) #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtpbh_ps(k: __mmask8, a: __m128bh) -> __m128 { unsafe { let cvt = _mm_cvtpbh_ps(a); @@ -517,7 +517,7 @@ pub fn _mm_cvtsbh_ss(a: bf16) -> f32 { #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtneps_pbh(a: __m128) -> __m128bh { unsafe { let mut dst: __m128bh; @@ -539,7 +539,7 @@ pub fn _mm_cvtneps_pbh(a: __m128) -> __m128bh { #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh { unsafe { let mut dst = src; @@ -562,7 +562,7 @@ pub fn _mm_mask_cvtneps_pbh(src: __m128bh, k: __mmask8, a: __m128) -> __m128bh { #[inline] #[target_feature(enable = "avx512bf16,avx512vl")] #[cfg_attr(test, assert_instr("vcvtneps2bf16"))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtneps_pbh(k: __mmask8, a: __m128) -> __m128bh { unsafe { let mut dst: __m128bh; diff --git a/crates/core_arch/src/x86/avx512bitalg.rs b/crates/core_arch/src/x86/avx512bitalg.rs index e27b737870..1cbf0faea0 100644 --- a/crates/core_arch/src/x86/avx512bitalg.rs +++ b/crates/core_arch/src/x86/avx512bitalg.rs @@ -41,7 +41,7 @@ unsafe extern "C" { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm512_popcnt_epi16(a: __m512i) -> __m512i { unsafe { transmute(simd_ctpop(a.as_i16x32())) } @@ -55,7 +55,7 @@ pub fn _mm512_popcnt_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm512_maskz_popcnt_epi16(k: __mmask32, a: __m512i) -> __m512i { unsafe { @@ -75,7 +75,7 @@ pub fn _mm512_maskz_popcnt_epi16(k: __mmask32, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm512_mask_popcnt_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { unsafe { @@ -92,7 +92,7 @@ pub fn _mm512_mask_popcnt_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm256_popcnt_epi16(a: __m256i) -> __m256i { unsafe { transmute(simd_ctpop(a.as_i16x16())) } @@ -106,7 +106,7 @@ pub fn _mm256_popcnt_epi16(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm256_maskz_popcnt_epi16(k: __mmask16, a: __m256i) -> __m256i { unsafe { @@ -126,7 +126,7 @@ pub fn _mm256_maskz_popcnt_epi16(k: __mmask16, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm256_mask_popcnt_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i { unsafe { @@ -143,7 +143,7 @@ pub fn _mm256_mask_popcnt_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm_popcnt_epi16(a: __m128i) -> __m128i { unsafe { transmute(simd_ctpop(a.as_i16x8())) } @@ -157,7 +157,7 @@ pub fn _mm_popcnt_epi16(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm_maskz_popcnt_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -177,7 +177,7 @@ pub fn _mm_maskz_popcnt_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_popcnt_epi16) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntw))] pub fn _mm_mask_popcnt_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -194,7 +194,7 @@ pub fn _mm_mask_popcnt_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm512_popcnt_epi8(a: __m512i) -> __m512i { unsafe { transmute(simd_ctpop(a.as_i8x64())) } @@ -208,7 +208,7 @@ pub fn _mm512_popcnt_epi8(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm512_maskz_popcnt_epi8(k: __mmask64, a: __m512i) -> __m512i { unsafe { @@ -228,7 +228,7 @@ pub fn _mm512_maskz_popcnt_epi8(k: __mmask64, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm512_mask_popcnt_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i { unsafe { @@ -245,7 +245,7 @@ pub fn _mm512_mask_popcnt_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm256_popcnt_epi8(a: __m256i) -> __m256i { unsafe { transmute(simd_ctpop(a.as_i8x32())) } @@ -259,7 +259,7 @@ pub fn _mm256_popcnt_epi8(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm256_maskz_popcnt_epi8(k: __mmask32, a: __m256i) -> __m256i { unsafe { @@ -279,7 +279,7 @@ pub fn _mm256_maskz_popcnt_epi8(k: __mmask32, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm256_mask_popcnt_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i { unsafe { @@ -296,7 +296,7 @@ pub fn _mm256_mask_popcnt_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm_popcnt_epi8(a: __m128i) -> __m128i { unsafe { transmute(simd_ctpop(a.as_i8x16())) } @@ -310,7 +310,7 @@ pub fn _mm_popcnt_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm_maskz_popcnt_epi8(k: __mmask16, a: __m128i) -> __m128i { unsafe { @@ -330,7 +330,7 @@ pub fn _mm_maskz_popcnt_epi8(k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_popcnt_epi8) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntb))] pub fn _mm_mask_popcnt_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { unsafe { @@ -349,7 +349,7 @@ pub fn _mm_mask_popcnt_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_bitshuffle_epi64_mask) #[inline] #[target_feature(enable = "avx512bitalg")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm512_bitshuffle_epi64_mask(b: __m512i, c: __m512i) -> __mmask64 { unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64(), !0) } @@ -365,7 +365,7 @@ pub fn _mm512_bitshuffle_epi64_mask(b: __m512i, c: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_bitshuffle_epi64_mask) #[inline] #[target_feature(enable = "avx512bitalg")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm512_mask_bitshuffle_epi64_mask(k: __mmask64, b: __m512i, c: __m512i) -> __mmask64 { unsafe { bitshuffle_512(b.as_i8x64(), c.as_i8x64(), k) } @@ -378,7 +378,7 @@ pub fn _mm512_mask_bitshuffle_epi64_mask(k: __mmask64, b: __m512i, c: __m512i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_bitshuffle_epi64_mask) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm256_bitshuffle_epi64_mask(b: __m256i, c: __m256i) -> __mmask32 { unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32(), !0) } @@ -394,7 +394,7 @@ pub fn _mm256_bitshuffle_epi64_mask(b: __m256i, c: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_bitshuffle_epi64_mask) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm256_mask_bitshuffle_epi64_mask(k: __mmask32, b: __m256i, c: __m256i) -> __mmask32 { unsafe { bitshuffle_256(b.as_i8x32(), c.as_i8x32(), k) } @@ -407,7 +407,7 @@ pub fn _mm256_mask_bitshuffle_epi64_mask(k: __mmask32, b: __m256i, c: __m256i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_bitshuffle_epi64_mask) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm_bitshuffle_epi64_mask(b: __m128i, c: __m128i) -> __mmask16 { unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16(), !0) } @@ -423,7 +423,7 @@ pub fn _mm_bitshuffle_epi64_mask(b: __m128i, c: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_bitshuffle_epi64_mask) #[inline] #[target_feature(enable = "avx512bitalg,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufbitqmb))] pub fn _mm_mask_bitshuffle_epi64_mask(k: __mmask16, b: __m128i, c: __m128i) -> __mmask16 { unsafe { bitshuffle_128(b.as_i8x16(), c.as_i8x16(), k) } diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 11d1f93f37..b60b0b7079 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -14,7 +14,7 @@ use stdarch_test::assert_instr; /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_abs_epi16&expand=30) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsw))] pub fn _mm512_abs_epi16(a: __m512i) -> __m512i { unsafe { @@ -29,7 +29,7 @@ pub fn _mm512_abs_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_abs_epi16&expand=31) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsw))] pub fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { unsafe { @@ -43,7 +43,7 @@ pub fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_abs_epi16&expand=32) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsw))] pub fn _mm512_maskz_abs_epi16(k: __mmask32, a: __m512i) -> __m512i { unsafe { @@ -57,7 +57,7 @@ pub fn _mm512_maskz_abs_epi16(k: __mmask32, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_abs_epi16&expand=28) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsw))] pub fn _mm256_mask_abs_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i { unsafe { @@ -71,7 +71,7 @@ pub fn _mm256_mask_abs_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_abs_epi16&expand=29) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsw))] pub fn _mm256_maskz_abs_epi16(k: __mmask16, a: __m256i) -> __m256i { unsafe { @@ -85,7 +85,7 @@ pub fn _mm256_maskz_abs_epi16(k: __mmask16, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_abs_epi16&expand=25) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsw))] pub fn _mm_mask_abs_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -99,7 +99,7 @@ pub fn _mm_mask_abs_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_abs_epi16&expand=26) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsw))] pub fn _mm_maskz_abs_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -113,7 +113,7 @@ pub fn _mm_maskz_abs_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_abs_epi8&expand=57) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsb))] pub fn _mm512_abs_epi8(a: __m512i) -> __m512i { unsafe { @@ -128,7 +128,7 @@ pub fn _mm512_abs_epi8(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_abs_epi8&expand=58) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsb))] pub fn _mm512_mask_abs_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i { unsafe { @@ -142,7 +142,7 @@ pub fn _mm512_mask_abs_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_abs_epi8&expand=59) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsb))] pub fn _mm512_maskz_abs_epi8(k: __mmask64, a: __m512i) -> __m512i { unsafe { @@ -156,7 +156,7 @@ pub fn _mm512_maskz_abs_epi8(k: __mmask64, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_abs_epi8&expand=55) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsb))] pub fn _mm256_mask_abs_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i { unsafe { @@ -170,7 +170,7 @@ pub fn _mm256_mask_abs_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_abs_epi8&expand=56) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsb))] pub fn _mm256_maskz_abs_epi8(k: __mmask32, a: __m256i) -> __m256i { unsafe { @@ -184,7 +184,7 @@ pub fn _mm256_maskz_abs_epi8(k: __mmask32, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_abs_epi8&expand=52) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsb))] pub fn _mm_mask_abs_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { unsafe { @@ -198,7 +198,7 @@ pub fn _mm_mask_abs_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_abs_epi8&expand=53) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsb))] pub fn _mm_maskz_abs_epi8(k: __mmask16, a: __m128i) -> __m128i { unsafe { @@ -212,7 +212,7 @@ pub fn _mm_maskz_abs_epi8(k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_epi16&expand=91) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddw))] pub fn _mm512_add_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_add(a.as_i16x32(), b.as_i16x32())) } @@ -223,7 +223,7 @@ pub fn _mm512_add_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_epi16&expand=92) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddw))] pub fn _mm512_mask_add_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -237,7 +237,7 @@ pub fn _mm512_mask_add_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_epi16&expand=93) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddw))] pub fn _mm512_maskz_add_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -251,7 +251,7 @@ pub fn _mm512_maskz_add_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_add_epi16&expand=89) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddw))] pub fn _mm256_mask_add_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -265,7 +265,7 @@ pub fn _mm256_mask_add_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_add_epi16&expand=90) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddw))] pub fn _mm256_maskz_add_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -279,7 +279,7 @@ pub fn _mm256_maskz_add_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_add_epi16&expand=86) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddw))] pub fn _mm_mask_add_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -293,7 +293,7 @@ pub fn _mm_mask_add_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_epi16&expand=87) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddw))] pub fn _mm_maskz_add_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -307,7 +307,7 @@ pub fn _mm_maskz_add_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_epi8&expand=118) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddb))] pub fn _mm512_add_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_add(a.as_i8x64(), b.as_i8x64())) } @@ -318,7 +318,7 @@ pub fn _mm512_add_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_epi8&expand=119) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddb))] pub fn _mm512_mask_add_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -332,7 +332,7 @@ pub fn _mm512_mask_add_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_epi8&expand=120) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddb))] pub fn _mm512_maskz_add_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -346,7 +346,7 @@ pub fn _mm512_maskz_add_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_add_epi8&expand=116) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddb))] pub fn _mm256_mask_add_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -360,7 +360,7 @@ pub fn _mm256_mask_add_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_add_epi8&expand=117) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddb))] pub fn _mm256_maskz_add_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -374,7 +374,7 @@ pub fn _mm256_maskz_add_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_add_epi8&expand=113) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddb))] pub fn _mm_mask_add_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -388,7 +388,7 @@ pub fn _mm_mask_add_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_epi8&expand=114) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddb))] pub fn _mm_maskz_add_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -402,7 +402,7 @@ pub fn _mm_maskz_add_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_adds_epu16&expand=197) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusw))] pub fn _mm512_adds_epu16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_saturating_add(a.as_u16x32(), b.as_u16x32())) } @@ -413,7 +413,7 @@ pub fn _mm512_adds_epu16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_adds_epu16&expand=198) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusw))] pub fn _mm512_mask_adds_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -427,7 +427,7 @@ pub fn _mm512_mask_adds_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_adds_epu16&expand=199) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusw))] pub fn _mm512_maskz_adds_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -441,7 +441,7 @@ pub fn _mm512_maskz_adds_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_adds_epu16&expand=195) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusw))] pub fn _mm256_mask_adds_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -455,7 +455,7 @@ pub fn _mm256_mask_adds_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_adds_epu16&expand=196) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusw))] pub fn _mm256_maskz_adds_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -469,7 +469,7 @@ pub fn _mm256_maskz_adds_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_adds_epu16&expand=192) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusw))] pub fn _mm_mask_adds_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -483,7 +483,7 @@ pub fn _mm_mask_adds_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_adds_epu16&expand=193) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusw))] pub fn _mm_maskz_adds_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -497,7 +497,7 @@ pub fn _mm_maskz_adds_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_adds_epu8&expand=206) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusb))] pub fn _mm512_adds_epu8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_saturating_add(a.as_u8x64(), b.as_u8x64())) } @@ -508,7 +508,7 @@ pub fn _mm512_adds_epu8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_adds_epu8&expand=207) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusb))] pub fn _mm512_mask_adds_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -522,7 +522,7 @@ pub fn _mm512_mask_adds_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_adds_epu8&expand=208) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusb))] pub fn _mm512_maskz_adds_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -536,7 +536,7 @@ pub fn _mm512_maskz_adds_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_adds_epu8&expand=204) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusb))] pub fn _mm256_mask_adds_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -550,7 +550,7 @@ pub fn _mm256_mask_adds_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_adds_epu8&expand=205) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusb))] pub fn _mm256_maskz_adds_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -564,7 +564,7 @@ pub fn _mm256_maskz_adds_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_adds_epu8&expand=201) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusb))] pub fn _mm_mask_adds_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -578,7 +578,7 @@ pub fn _mm_mask_adds_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_adds_epu8&expand=202) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddusb))] pub fn _mm_maskz_adds_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -592,7 +592,7 @@ pub fn _mm_maskz_adds_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_adds_epi16&expand=179) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsw))] pub fn _mm512_adds_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_saturating_add(a.as_i16x32(), b.as_i16x32())) } @@ -603,7 +603,7 @@ pub fn _mm512_adds_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_adds_epi16&expand=180) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsw))] pub fn _mm512_mask_adds_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -617,7 +617,7 @@ pub fn _mm512_mask_adds_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_adds_epi16&expand=181) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsw))] pub fn _mm512_maskz_adds_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -631,7 +631,7 @@ pub fn _mm512_maskz_adds_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_adds_epi16&expand=177) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsw))] pub fn _mm256_mask_adds_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -645,7 +645,7 @@ pub fn _mm256_mask_adds_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_adds_epi16&expand=178) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsw))] pub fn _mm256_maskz_adds_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -659,7 +659,7 @@ pub fn _mm256_maskz_adds_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_adds_epi16&expand=174) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsw))] pub fn _mm_mask_adds_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -673,7 +673,7 @@ pub fn _mm_mask_adds_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_adds_epi16&expand=175) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsw))] pub fn _mm_maskz_adds_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -687,7 +687,7 @@ pub fn _mm_maskz_adds_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_adds_epi8&expand=188) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsb))] pub fn _mm512_adds_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_saturating_add(a.as_i8x64(), b.as_i8x64())) } @@ -698,7 +698,7 @@ pub fn _mm512_adds_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_adds_epi8&expand=189) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsb))] pub fn _mm512_mask_adds_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -712,7 +712,7 @@ pub fn _mm512_mask_adds_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_adds_epi8&expand=190) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsb))] pub fn _mm512_maskz_adds_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -726,7 +726,7 @@ pub fn _mm512_maskz_adds_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_adds_epi8&expand=186) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsb))] pub fn _mm256_mask_adds_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -740,7 +740,7 @@ pub fn _mm256_mask_adds_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_adds_epi8&expand=187) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsb))] pub fn _mm256_maskz_adds_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -754,7 +754,7 @@ pub fn _mm256_maskz_adds_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_adds_epi8&expand=183) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsb))] pub fn _mm_mask_adds_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -768,7 +768,7 @@ pub fn _mm_mask_adds_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_adds_epi8&expand=184) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddsb))] pub fn _mm_maskz_adds_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -782,7 +782,7 @@ pub fn _mm_maskz_adds_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_epi16&expand=5685) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubw))] pub fn _mm512_sub_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_sub(a.as_i16x32(), b.as_i16x32())) } @@ -793,7 +793,7 @@ pub fn _mm512_sub_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_epi16&expand=5683) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubw))] pub fn _mm512_mask_sub_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -807,7 +807,7 @@ pub fn _mm512_mask_sub_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_epi16&expand=5684) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubw))] pub fn _mm512_maskz_sub_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -821,7 +821,7 @@ pub fn _mm512_maskz_sub_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sub_epi16&expand=5680) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubw))] pub fn _mm256_mask_sub_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -835,7 +835,7 @@ pub fn _mm256_mask_sub_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sub_epi16&expand=5681) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubw))] pub fn _mm256_maskz_sub_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -849,7 +849,7 @@ pub fn _mm256_maskz_sub_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sub_epi16&expand=5677) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubw))] pub fn _mm_mask_sub_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -863,7 +863,7 @@ pub fn _mm_mask_sub_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sub_epi16&expand=5678) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubw))] pub fn _mm_maskz_sub_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -877,7 +877,7 @@ pub fn _mm_maskz_sub_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_epi8&expand=5712) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubb))] pub fn _mm512_sub_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_sub(a.as_i8x64(), b.as_i8x64())) } @@ -888,7 +888,7 @@ pub fn _mm512_sub_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_epi8&expand=5710) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubb))] pub fn _mm512_mask_sub_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -902,7 +902,7 @@ pub fn _mm512_mask_sub_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_epi8&expand=5711) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubb))] pub fn _mm512_maskz_sub_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -916,7 +916,7 @@ pub fn _mm512_maskz_sub_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sub_epi8&expand=5707) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubb))] pub fn _mm256_mask_sub_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -930,7 +930,7 @@ pub fn _mm256_mask_sub_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sub_epi8&expand=5708) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubb))] pub fn _mm256_maskz_sub_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -944,7 +944,7 @@ pub fn _mm256_maskz_sub_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sub_epi8&expand=5704) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubb))] pub fn _mm_mask_sub_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -958,7 +958,7 @@ pub fn _mm_mask_sub_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sub_epi8&expand=5705) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubb))] pub fn _mm_maskz_sub_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -972,7 +972,7 @@ pub fn _mm_maskz_sub_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_subs_epu16&expand=5793) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusw))] pub fn _mm512_subs_epu16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_saturating_sub(a.as_u16x32(), b.as_u16x32())) } @@ -983,7 +983,7 @@ pub fn _mm512_subs_epu16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_subs_epu16&expand=5791) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusw))] pub fn _mm512_mask_subs_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -997,7 +997,7 @@ pub fn _mm512_mask_subs_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_subs_epu16&expand=5792) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusw))] pub fn _mm512_maskz_subs_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1011,7 +1011,7 @@ pub fn _mm512_maskz_subs_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_subs_epu16&expand=5788) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusw))] pub fn _mm256_mask_subs_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1025,7 +1025,7 @@ pub fn _mm256_mask_subs_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_subs_epu16&expand=5789) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusw))] pub fn _mm256_maskz_subs_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1039,7 +1039,7 @@ pub fn _mm256_maskz_subs_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_subs_epu16&expand=5785) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusw))] pub fn _mm_mask_subs_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1053,7 +1053,7 @@ pub fn _mm_mask_subs_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_subs_epu16&expand=5786) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusw))] pub fn _mm_maskz_subs_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1067,7 +1067,7 @@ pub fn _mm_maskz_subs_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_subs_epu8&expand=5802) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusb))] pub fn _mm512_subs_epu8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_saturating_sub(a.as_u8x64(), b.as_u8x64())) } @@ -1078,7 +1078,7 @@ pub fn _mm512_subs_epu8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_subs_epu8&expand=5800) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusb))] pub fn _mm512_mask_subs_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1092,7 +1092,7 @@ pub fn _mm512_mask_subs_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_subs_epu8&expand=5801) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusb))] pub fn _mm512_maskz_subs_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1106,7 +1106,7 @@ pub fn _mm512_maskz_subs_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_subs_epu8&expand=5797) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusb))] pub fn _mm256_mask_subs_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1120,7 +1120,7 @@ pub fn _mm256_mask_subs_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_subs_epu8&expand=5798) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusb))] pub fn _mm256_maskz_subs_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1134,7 +1134,7 @@ pub fn _mm256_maskz_subs_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_subs_epu8&expand=5794) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusb))] pub fn _mm_mask_subs_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1148,7 +1148,7 @@ pub fn _mm_mask_subs_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_subs_epu8&expand=5795) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubusb))] pub fn _mm_maskz_subs_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1162,7 +1162,7 @@ pub fn _mm_maskz_subs_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_subs_epi16&expand=5775) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsw))] pub fn _mm512_subs_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_saturating_sub(a.as_i16x32(), b.as_i16x32())) } @@ -1173,7 +1173,7 @@ pub fn _mm512_subs_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_subs_epi16&expand=5773) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsw))] pub fn _mm512_mask_subs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1187,7 +1187,7 @@ pub fn _mm512_mask_subs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_subs_epi16&expand=5774) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsw))] pub fn _mm512_maskz_subs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1201,7 +1201,7 @@ pub fn _mm512_maskz_subs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_subs_epi16&expand=5770) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsw))] pub fn _mm256_mask_subs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1215,7 +1215,7 @@ pub fn _mm256_mask_subs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_subs_epi16&expand=5771) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsw))] pub fn _mm256_maskz_subs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1229,7 +1229,7 @@ pub fn _mm256_maskz_subs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_subs_epi16&expand=5767) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsw))] pub fn _mm_mask_subs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1243,7 +1243,7 @@ pub fn _mm_mask_subs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_subs_epi16&expand=5768) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsw))] pub fn _mm_maskz_subs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1257,7 +1257,7 @@ pub fn _mm_maskz_subs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_subs_epi8&expand=5784) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsb))] pub fn _mm512_subs_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_saturating_sub(a.as_i8x64(), b.as_i8x64())) } @@ -1268,7 +1268,7 @@ pub fn _mm512_subs_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_subs_epi8&expand=5782) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsb))] pub fn _mm512_mask_subs_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1282,7 +1282,7 @@ pub fn _mm512_mask_subs_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_subs_epi8&expand=5783) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsb))] pub fn _mm512_maskz_subs_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1296,7 +1296,7 @@ pub fn _mm512_maskz_subs_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_subs_epi8&expand=5779) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsb))] pub fn _mm256_mask_subs_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1310,7 +1310,7 @@ pub fn _mm256_mask_subs_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_subs_epi8&expand=5780) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsb))] pub fn _mm256_maskz_subs_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1324,7 +1324,7 @@ pub fn _mm256_maskz_subs_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_subs_epi8&expand=5776) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsb))] pub fn _mm_mask_subs_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1338,7 +1338,7 @@ pub fn _mm_mask_subs_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_subs_epi8&expand=5777) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubsb))] pub fn _mm_maskz_subs_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1352,7 +1352,7 @@ pub fn _mm_maskz_subs_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mulhi_epu16&expand=3973) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhuw))] pub fn _mm512_mulhi_epu16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1368,7 +1368,7 @@ pub fn _mm512_mulhi_epu16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mulhi_epu16&expand=3971) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhuw))] pub fn _mm512_mask_mulhi_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1382,7 +1382,7 @@ pub fn _mm512_mask_mulhi_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mulhi_epu16&expand=3972) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhuw))] pub fn _mm512_maskz_mulhi_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1396,7 +1396,7 @@ pub fn _mm512_maskz_mulhi_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mulhi_epu16&expand=3968) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhuw))] pub fn _mm256_mask_mulhi_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1410,7 +1410,7 @@ pub fn _mm256_mask_mulhi_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mulhi_epu16&expand=3969) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhuw))] pub fn _mm256_maskz_mulhi_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1424,7 +1424,7 @@ pub fn _mm256_maskz_mulhi_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mulhi_epu16&expand=3965) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhuw))] pub fn _mm_mask_mulhi_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1438,7 +1438,7 @@ pub fn _mm_mask_mulhi_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mulhi_epu16&expand=3966) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhuw))] pub fn _mm_maskz_mulhi_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1452,7 +1452,7 @@ pub fn _mm_maskz_mulhi_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mulhi_epi16&expand=3962) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhw))] pub fn _mm512_mulhi_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1468,7 +1468,7 @@ pub fn _mm512_mulhi_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mulhi_epi16&expand=3960) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhw))] pub fn _mm512_mask_mulhi_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1482,7 +1482,7 @@ pub fn _mm512_mask_mulhi_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mulhi_epi16&expand=3961) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhw))] pub fn _mm512_maskz_mulhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1496,7 +1496,7 @@ pub fn _mm512_maskz_mulhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mulhi_epi16&expand=3957) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhw))] pub fn _mm256_mask_mulhi_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1510,7 +1510,7 @@ pub fn _mm256_mask_mulhi_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mulhi_epi16&expand=3958) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhw))] pub fn _mm256_maskz_mulhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1524,7 +1524,7 @@ pub fn _mm256_maskz_mulhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mulhi_epi16&expand=3954) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhw))] pub fn _mm_mask_mulhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1538,7 +1538,7 @@ pub fn _mm_mask_mulhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mulhi_epi16&expand=3955) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhw))] pub fn _mm_maskz_mulhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1552,7 +1552,7 @@ pub fn _mm_maskz_mulhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mulhrs_epi16&expand=3986) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhrsw))] pub fn _mm512_mulhrs_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpmulhrsw(a.as_i16x32(), b.as_i16x32())) } @@ -1563,7 +1563,7 @@ pub fn _mm512_mulhrs_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mulhrs_epi16&expand=3984) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhrsw))] pub fn _mm512_mask_mulhrs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1577,7 +1577,7 @@ pub fn _mm512_mask_mulhrs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mulhrs_epi16&expand=3985) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhrsw))] pub fn _mm512_maskz_mulhrs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1591,7 +1591,7 @@ pub fn _mm512_maskz_mulhrs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mulhrs_epi16&expand=3981) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhrsw))] pub fn _mm256_mask_mulhrs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1605,7 +1605,7 @@ pub fn _mm256_mask_mulhrs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mulhrs_epi16&expand=3982) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhrsw))] pub fn _mm256_maskz_mulhrs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1619,7 +1619,7 @@ pub fn _mm256_maskz_mulhrs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mulhrs_epi16&expand=3978) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhrsw))] pub fn _mm_mask_mulhrs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1633,7 +1633,7 @@ pub fn _mm_mask_mulhrs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mulhrs_epi16&expand=3979) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulhrsw))] pub fn _mm_maskz_mulhrs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1647,7 +1647,7 @@ pub fn _mm_maskz_mulhrs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mullo_epi16&expand=3996) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmullw))] pub fn _mm512_mullo_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_mul(a.as_i16x32(), b.as_i16x32())) } @@ -1658,7 +1658,7 @@ pub fn _mm512_mullo_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mullo_epi16&expand=3994) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmullw))] pub fn _mm512_mask_mullo_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1672,7 +1672,7 @@ pub fn _mm512_mask_mullo_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mullo_epi16&expand=3995) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmullw))] pub fn _mm512_maskz_mullo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1686,7 +1686,7 @@ pub fn _mm512_maskz_mullo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mullo_epi16&expand=3991) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmullw))] pub fn _mm256_mask_mullo_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1700,7 +1700,7 @@ pub fn _mm256_mask_mullo_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mullo_epi16&expand=3992) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmullw))] pub fn _mm256_maskz_mullo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1714,7 +1714,7 @@ pub fn _mm256_maskz_mullo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mullo_epi16&expand=3988) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmullw))] pub fn _mm_mask_mullo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1728,7 +1728,7 @@ pub fn _mm_mask_mullo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mullo_epi16&expand=3989) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmullw))] pub fn _mm_maskz_mullo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1742,7 +1742,7 @@ pub fn _mm_maskz_mullo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epu16&expand=3609) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuw))] pub fn _mm512_max_epu16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1757,7 +1757,7 @@ pub fn _mm512_max_epu16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epu16&expand=3607) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuw))] pub fn _mm512_mask_max_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1771,7 +1771,7 @@ pub fn _mm512_mask_max_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epu16&expand=3608) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuw))] pub fn _mm512_maskz_max_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1785,7 +1785,7 @@ pub fn _mm512_maskz_max_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epu16&expand=3604) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuw))] pub fn _mm256_mask_max_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1799,7 +1799,7 @@ pub fn _mm256_mask_max_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epu16&expand=3605) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuw))] pub fn _mm256_maskz_max_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1813,7 +1813,7 @@ pub fn _mm256_maskz_max_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epu16&expand=3601) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuw))] pub fn _mm_mask_max_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1827,7 +1827,7 @@ pub fn _mm_mask_max_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epu16&expand=3602) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuw))] pub fn _mm_maskz_max_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1841,7 +1841,7 @@ pub fn _mm_maskz_max_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epu8&expand=3636) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxub))] pub fn _mm512_max_epu8(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1856,7 +1856,7 @@ pub fn _mm512_max_epu8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epu8&expand=3634) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxub))] pub fn _mm512_mask_max_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1870,7 +1870,7 @@ pub fn _mm512_mask_max_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epu8&expand=3635) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxub))] pub fn _mm512_maskz_max_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1884,7 +1884,7 @@ pub fn _mm512_maskz_max_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epu8&expand=3631) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxub))] pub fn _mm256_mask_max_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1898,7 +1898,7 @@ pub fn _mm256_mask_max_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epu8&expand=3632) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxub))] pub fn _mm256_maskz_max_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1912,7 +1912,7 @@ pub fn _mm256_maskz_max_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epu8&expand=3628) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxub))] pub fn _mm_mask_max_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1926,7 +1926,7 @@ pub fn _mm_mask_max_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epu8&expand=3629) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxub))] pub fn _mm_maskz_max_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1940,7 +1940,7 @@ pub fn _mm_maskz_max_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epi16&expand=3573) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsw))] pub fn _mm512_max_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1955,7 +1955,7 @@ pub fn _mm512_max_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epi16&expand=3571) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsw))] pub fn _mm512_mask_max_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1969,7 +1969,7 @@ pub fn _mm512_mask_max_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epi16&expand=3572) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsw))] pub fn _mm512_maskz_max_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1983,7 +1983,7 @@ pub fn _mm512_maskz_max_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epi16&expand=3568) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsw))] pub fn _mm256_mask_max_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1997,7 +1997,7 @@ pub fn _mm256_mask_max_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epi16&expand=3569) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsw))] pub fn _mm256_maskz_max_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2011,7 +2011,7 @@ pub fn _mm256_maskz_max_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epi16&expand=3565) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsw))] pub fn _mm_mask_max_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2025,7 +2025,7 @@ pub fn _mm_mask_max_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epi16&expand=3566) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsw))] pub fn _mm_maskz_max_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2039,7 +2039,7 @@ pub fn _mm_maskz_max_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epi8&expand=3600) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsb))] pub fn _mm512_max_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2054,7 +2054,7 @@ pub fn _mm512_max_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epi8&expand=3598) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsb))] pub fn _mm512_mask_max_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2068,7 +2068,7 @@ pub fn _mm512_mask_max_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epi8&expand=3599) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsb))] pub fn _mm512_maskz_max_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2082,7 +2082,7 @@ pub fn _mm512_maskz_max_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epi8&expand=3595) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsb))] pub fn _mm256_mask_max_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2096,7 +2096,7 @@ pub fn _mm256_mask_max_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epi8&expand=3596) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsb))] pub fn _mm256_maskz_max_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2110,7 +2110,7 @@ pub fn _mm256_maskz_max_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epi8&expand=3592) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsb))] pub fn _mm_mask_max_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2124,7 +2124,7 @@ pub fn _mm_mask_max_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epi8&expand=3593) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsb))] pub fn _mm_maskz_max_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2138,7 +2138,7 @@ pub fn _mm_maskz_max_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epu16&expand=3723) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuw))] pub fn _mm512_min_epu16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2153,7 +2153,7 @@ pub fn _mm512_min_epu16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epu16&expand=3721) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuw))] pub fn _mm512_mask_min_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2167,7 +2167,7 @@ pub fn _mm512_mask_min_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epu16&expand=3722) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuw))] pub fn _mm512_maskz_min_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2181,7 +2181,7 @@ pub fn _mm512_maskz_min_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epu16&expand=3718) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuw))] pub fn _mm256_mask_min_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2195,7 +2195,7 @@ pub fn _mm256_mask_min_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epu16&expand=3719) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuw))] pub fn _mm256_maskz_min_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2209,7 +2209,7 @@ pub fn _mm256_maskz_min_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epu16&expand=3715) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuw))] pub fn _mm_mask_min_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2223,7 +2223,7 @@ pub fn _mm_mask_min_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epu16&expand=3716) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuw))] pub fn _mm_maskz_min_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2237,7 +2237,7 @@ pub fn _mm_maskz_min_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epu8&expand=3750) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminub))] pub fn _mm512_min_epu8(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2252,7 +2252,7 @@ pub fn _mm512_min_epu8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epu8&expand=3748) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminub))] pub fn _mm512_mask_min_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2266,7 +2266,7 @@ pub fn _mm512_mask_min_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epu8&expand=3749) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminub))] pub fn _mm512_maskz_min_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2280,7 +2280,7 @@ pub fn _mm512_maskz_min_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epu8&expand=3745) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminub))] pub fn _mm256_mask_min_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2294,7 +2294,7 @@ pub fn _mm256_mask_min_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epu8&expand=3746) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminub))] pub fn _mm256_maskz_min_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2308,7 +2308,7 @@ pub fn _mm256_maskz_min_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epu8&expand=3742) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminub))] pub fn _mm_mask_min_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2322,7 +2322,7 @@ pub fn _mm_mask_min_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epu8&expand=3743) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminub))] pub fn _mm_maskz_min_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2336,7 +2336,7 @@ pub fn _mm_maskz_min_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epi16&expand=3687) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsw))] pub fn _mm512_min_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2351,7 +2351,7 @@ pub fn _mm512_min_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epi16&expand=3685) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsw))] pub fn _mm512_mask_min_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2365,7 +2365,7 @@ pub fn _mm512_mask_min_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epi16&expand=3686) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsw))] pub fn _mm512_maskz_min_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2379,7 +2379,7 @@ pub fn _mm512_maskz_min_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epi16&expand=3682) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsw))] pub fn _mm256_mask_min_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2393,7 +2393,7 @@ pub fn _mm256_mask_min_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epi16&expand=3683) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsw))] pub fn _mm256_maskz_min_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2407,7 +2407,7 @@ pub fn _mm256_maskz_min_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epi16&expand=3679) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsw))] pub fn _mm_mask_min_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2421,7 +2421,7 @@ pub fn _mm_mask_min_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epi16&expand=3680) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsw))] pub fn _mm_maskz_min_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2435,7 +2435,7 @@ pub fn _mm_maskz_min_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epi8&expand=3714) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsb))] pub fn _mm512_min_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2450,7 +2450,7 @@ pub fn _mm512_min_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epi8&expand=3712) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsb))] pub fn _mm512_mask_min_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2464,7 +2464,7 @@ pub fn _mm512_mask_min_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epi8&expand=3713) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsb))] pub fn _mm512_maskz_min_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2478,7 +2478,7 @@ pub fn _mm512_maskz_min_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epi8&expand=3709) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsb))] pub fn _mm256_mask_min_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2492,7 +2492,7 @@ pub fn _mm256_mask_min_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epi8&expand=3710) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsb))] pub fn _mm256_maskz_min_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2506,7 +2506,7 @@ pub fn _mm256_maskz_min_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epi8&expand=3706) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsb))] pub fn _mm_mask_min_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2520,7 +2520,7 @@ pub fn _mm_mask_min_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epi8&expand=3707) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsb))] pub fn _mm_maskz_min_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2534,7 +2534,7 @@ pub fn _mm_maskz_min_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epu16_mask&expand=1050) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmplt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_lt(a.as_u16x32(), b.as_u16x32())) } @@ -2545,7 +2545,7 @@ pub fn _mm512_cmplt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epu16_mask&expand=1051) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmplt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2556,7 +2556,7 @@ pub fn _mm512_mask_cmplt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epu16_mask&expand=1050) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmplt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_lt(a.as_u16x16(), b.as_u16x16())) } @@ -2567,7 +2567,7 @@ pub fn _mm256_cmplt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epu16_mask&expand=1049) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmplt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2578,7 +2578,7 @@ pub fn _mm256_mask_cmplt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epu16_mask&expand=1018) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmplt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_lt(a.as_u16x8(), b.as_u16x8())) } @@ -2589,7 +2589,7 @@ pub fn _mm_cmplt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epu16_mask&expand=1019) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmplt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2600,7 +2600,7 @@ pub fn _mm_mask_cmplt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm512_cmplt_epu8_mask&expand=1068) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmplt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_lt(a.as_u8x64(), b.as_u8x64())) } @@ -2611,7 +2611,7 @@ pub fn _mm512_cmplt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epu8_mask&expand=1069) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmplt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2622,7 +2622,7 @@ pub fn _mm512_mask_cmplt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epu8_mask&expand=1066) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmplt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_lt(a.as_u8x32(), b.as_u8x32())) } @@ -2633,7 +2633,7 @@ pub fn _mm256_cmplt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epu8_mask&expand=1067) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmplt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2644,7 +2644,7 @@ pub fn _mm256_mask_cmplt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epu8_mask&expand=1064) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmplt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_lt(a.as_u8x16(), b.as_u8x16())) } @@ -2655,7 +2655,7 @@ pub fn _mm_cmplt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epu8_mask&expand=1065) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmplt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2666,7 +2666,7 @@ pub fn _mm_mask_cmplt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epi16_mask&expand=1022) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmplt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_lt(a.as_i16x32(), b.as_i16x32())) } @@ -2677,7 +2677,7 @@ pub fn _mm512_cmplt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epi16_mask&expand=1023) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmplt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2688,7 +2688,7 @@ pub fn _mm512_mask_cmplt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epi16_mask&expand=1020) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmplt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_lt(a.as_i16x16(), b.as_i16x16())) } @@ -2699,7 +2699,7 @@ pub fn _mm256_cmplt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epi16_mask&expand=1021) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmplt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2710,7 +2710,7 @@ pub fn _mm256_mask_cmplt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi16_mask&expand=1018) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmplt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_lt(a.as_i16x8(), b.as_i16x8())) } @@ -2721,7 +2721,7 @@ pub fn _mm_cmplt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epi16_mask&expand=1019) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmplt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2732,7 +2732,7 @@ pub fn _mm_mask_cmplt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epi8_mask&expand=1044) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmplt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_lt(a.as_i8x64(), b.as_i8x64())) } @@ -2743,7 +2743,7 @@ pub fn _mm512_cmplt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epi8_mask&expand=1045) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmplt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2754,7 +2754,7 @@ pub fn _mm512_mask_cmplt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epi8_mask&expand=1042) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmplt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_lt(a.as_i8x32(), b.as_i8x32())) } @@ -2765,7 +2765,7 @@ pub fn _mm256_cmplt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epi8_mask&expand=1043) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmplt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2776,7 +2776,7 @@ pub fn _mm256_mask_cmplt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi8_mask&expand=1040) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmplt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_lt(a.as_i8x16(), b.as_i8x16())) } @@ -2787,7 +2787,7 @@ pub fn _mm_cmplt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epi8_mask&expand=1041) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmplt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -2798,7 +2798,7 @@ pub fn _mm_mask_cmplt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epu16_mask&expand=927) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpgt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_gt(a.as_u16x32(), b.as_u16x32())) } @@ -2809,7 +2809,7 @@ pub fn _mm512_cmpgt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epu16_mask&expand=928) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpgt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2820,7 +2820,7 @@ pub fn _mm512_mask_cmpgt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epu16_mask&expand=925) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpgt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_gt(a.as_u16x16(), b.as_u16x16())) } @@ -2831,7 +2831,7 @@ pub fn _mm256_cmpgt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epu16_mask&expand=926) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpgt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2842,7 +2842,7 @@ pub fn _mm256_mask_cmpgt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epu16_mask&expand=923) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpgt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_gt(a.as_u16x8(), b.as_u16x8())) } @@ -2853,7 +2853,7 @@ pub fn _mm_cmpgt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epu16_mask&expand=924) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpgt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu16_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2864,7 +2864,7 @@ pub fn _mm_mask_cmpgt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epu8_mask&expand=945) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpgt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_gt(a.as_u8x64(), b.as_u8x64())) } @@ -2875,7 +2875,7 @@ pub fn _mm512_cmpgt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epu8_mask&expand=946) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpgt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2886,7 +2886,7 @@ pub fn _mm512_mask_cmpgt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epu8_mask&expand=943) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpgt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_gt(a.as_u8x32(), b.as_u8x32())) } @@ -2897,7 +2897,7 @@ pub fn _mm256_cmpgt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epu8_mask&expand=944) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpgt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2908,7 +2908,7 @@ pub fn _mm256_mask_cmpgt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epu8_mask&expand=941) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpgt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_gt(a.as_u8x16(), b.as_u8x16())) } @@ -2919,7 +2919,7 @@ pub fn _mm_cmpgt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epu8_mask&expand=942) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpgt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epu8_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2930,7 +2930,7 @@ pub fn _mm_mask_cmpgt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epi16_mask&expand=897) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpgt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_gt(a.as_i16x32(), b.as_i16x32())) } @@ -2941,7 +2941,7 @@ pub fn _mm512_cmpgt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epi16_mask&expand=898) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpgt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2952,7 +2952,7 @@ pub fn _mm512_mask_cmpgt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epi16_mask&expand=895) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpgt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_gt(a.as_i16x16(), b.as_i16x16())) } @@ -2963,7 +2963,7 @@ pub fn _mm256_cmpgt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epi16_mask&expand=896) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpgt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2974,7 +2974,7 @@ pub fn _mm256_mask_cmpgt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi16_mask&expand=893) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpgt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_gt(a.as_i16x8(), b.as_i16x8())) } @@ -2985,7 +2985,7 @@ pub fn _mm_cmpgt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epi16_mask&expand=894) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpgt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi16_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -2996,7 +2996,7 @@ pub fn _mm_mask_cmpgt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epi8_mask&expand=921) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpgt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_gt(a.as_i8x64(), b.as_i8x64())) } @@ -3007,7 +3007,7 @@ pub fn _mm512_cmpgt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epi8_mask&expand=922) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpgt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -3018,7 +3018,7 @@ pub fn _mm512_mask_cmpgt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epi8_mask&expand=919) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpgt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_gt(a.as_i8x32(), b.as_i8x32())) } @@ -3029,7 +3029,7 @@ pub fn _mm256_cmpgt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epi8_mask&expand=920) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpgt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -3040,7 +3040,7 @@ pub fn _mm256_mask_cmpgt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi8_mask&expand=917) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpgt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_gt(a.as_i8x16(), b.as_i8x16())) } @@ -3051,7 +3051,7 @@ pub fn _mm_cmpgt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epi8_mask&expand=918) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpgt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epi8_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -3062,7 +3062,7 @@ pub fn _mm_mask_cmpgt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epu16_mask&expand=989) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmple_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_le(a.as_u16x32(), b.as_u16x32())) } @@ -3073,7 +3073,7 @@ pub fn _mm512_cmple_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epu16_mask&expand=990) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmple_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3084,7 +3084,7 @@ pub fn _mm512_mask_cmple_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epu16_mask&expand=987) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmple_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_le(a.as_u16x16(), b.as_u16x16())) } @@ -3095,7 +3095,7 @@ pub fn _mm256_cmple_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epu16_mask&expand=988) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmple_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3106,7 +3106,7 @@ pub fn _mm256_mask_cmple_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epu16_mask&expand=985) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmple_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_le(a.as_u16x8(), b.as_u16x8())) } @@ -3117,7 +3117,7 @@ pub fn _mm_cmple_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epu16_mask&expand=986) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmple_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu16_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3128,7 +3128,7 @@ pub fn _mm_mask_cmple_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epu8_mask&expand=1007) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmple_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_le(a.as_u8x64(), b.as_u8x64())) } @@ -3139,7 +3139,7 @@ pub fn _mm512_cmple_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epu8_mask&expand=1008) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmple_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3150,7 +3150,7 @@ pub fn _mm512_mask_cmple_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epu8_mask&expand=1005) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmple_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_le(a.as_u8x32(), b.as_u8x32())) } @@ -3161,7 +3161,7 @@ pub fn _mm256_cmple_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epu8_mask&expand=1006) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmple_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3172,7 +3172,7 @@ pub fn _mm256_mask_cmple_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epu8_mask&expand=1003) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmple_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_le(a.as_u8x16(), b.as_u8x16())) } @@ -3183,7 +3183,7 @@ pub fn _mm_cmple_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epu8_mask&expand=1004) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmple_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epu8_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3194,7 +3194,7 @@ pub fn _mm_mask_cmple_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epi16_mask&expand=965) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmple_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_le(a.as_i16x32(), b.as_i16x32())) } @@ -3205,7 +3205,7 @@ pub fn _mm512_cmple_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epi16_mask&expand=966) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmple_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3216,7 +3216,7 @@ pub fn _mm512_mask_cmple_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epi16_mask&expand=963) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmple_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_le(a.as_i16x16(), b.as_i16x16())) } @@ -3227,7 +3227,7 @@ pub fn _mm256_cmple_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epi16_mask&expand=964) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmple_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3238,7 +3238,7 @@ pub fn _mm256_mask_cmple_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epi16_mask&expand=961) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmple_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_le(a.as_i16x8(), b.as_i16x8())) } @@ -3249,7 +3249,7 @@ pub fn _mm_cmple_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epi16_mask&expand=962) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmple_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi16_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3260,7 +3260,7 @@ pub fn _mm_mask_cmple_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epi8_mask&expand=983) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmple_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_le(a.as_i8x64(), b.as_i8x64())) } @@ -3271,7 +3271,7 @@ pub fn _mm512_cmple_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epi8_mask&expand=984) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmple_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3282,7 +3282,7 @@ pub fn _mm512_mask_cmple_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epi8_mask&expand=981) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmple_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_le(a.as_i8x32(), b.as_i8x32())) } @@ -3293,7 +3293,7 @@ pub fn _mm256_cmple_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epi8_mask&expand=982) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmple_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3304,7 +3304,7 @@ pub fn _mm256_mask_cmple_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epi8_mask&expand=979) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmple_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_le(a.as_i8x16(), b.as_i8x16())) } @@ -3315,7 +3315,7 @@ pub fn _mm_cmple_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epi8_mask&expand=980) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmple_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epi8_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -3326,7 +3326,7 @@ pub fn _mm_mask_cmple_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epu16_mask&expand=867) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpge_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_ge(a.as_u16x32(), b.as_u16x32())) } @@ -3337,7 +3337,7 @@ pub fn _mm512_cmpge_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epu16_mask&expand=868) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpge_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3348,7 +3348,7 @@ pub fn _mm512_mask_cmpge_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epu16_mask&expand=865) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpge_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_ge(a.as_u16x16(), b.as_u16x16())) } @@ -3359,7 +3359,7 @@ pub fn _mm256_cmpge_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epu16_mask&expand=866) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpge_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3370,7 +3370,7 @@ pub fn _mm256_mask_cmpge_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epu16_mask&expand=863) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpge_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_ge(a.as_u16x8(), b.as_u16x8())) } @@ -3381,7 +3381,7 @@ pub fn _mm_cmpge_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epu16_mask&expand=864) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpge_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu16_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3392,7 +3392,7 @@ pub fn _mm_mask_cmpge_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epu8_mask&expand=885) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpge_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_ge(a.as_u8x64(), b.as_u8x64())) } @@ -3403,7 +3403,7 @@ pub fn _mm512_cmpge_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epu8_mask&expand=886) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpge_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3414,7 +3414,7 @@ pub fn _mm512_mask_cmpge_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epu8_mask&expand=883) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpge_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_ge(a.as_u8x32(), b.as_u8x32())) } @@ -3425,7 +3425,7 @@ pub fn _mm256_cmpge_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epu8_mask&expand=884) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpge_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3436,7 +3436,7 @@ pub fn _mm256_mask_cmpge_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epu8_mask&expand=881) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpge_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_ge(a.as_u8x16(), b.as_u8x16())) } @@ -3447,7 +3447,7 @@ pub fn _mm_cmpge_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epu8_mask&expand=882) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpge_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epu8_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3458,7 +3458,7 @@ pub fn _mm_mask_cmpge_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epi16_mask&expand=843) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpge_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_ge(a.as_i16x32(), b.as_i16x32())) } @@ -3469,7 +3469,7 @@ pub fn _mm512_cmpge_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epi16_mask&expand=844) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpge_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3480,7 +3480,7 @@ pub fn _mm512_mask_cmpge_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epi16_mask&expand=841) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpge_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_ge(a.as_i16x16(), b.as_i16x16())) } @@ -3491,7 +3491,7 @@ pub fn _mm256_cmpge_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epi16_mask&expand=842) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpge_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3502,7 +3502,7 @@ pub fn _mm256_mask_cmpge_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epi16_mask&expand=839) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpge_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_ge(a.as_i16x8(), b.as_i16x8())) } @@ -3513,7 +3513,7 @@ pub fn _mm_cmpge_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epi16_mask&expand=840) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpge_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi16_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3524,7 +3524,7 @@ pub fn _mm_mask_cmpge_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epi8_mask&expand=861) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpge_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_ge(a.as_i8x64(), b.as_i8x64())) } @@ -3535,7 +3535,7 @@ pub fn _mm512_cmpge_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epi8_mask&expand=862) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpge_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3546,7 +3546,7 @@ pub fn _mm512_mask_cmpge_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epi8_mask&expand=859) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpge_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_ge(a.as_i8x32(), b.as_i8x32())) } @@ -3557,7 +3557,7 @@ pub fn _mm256_cmpge_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epi8_mask&expand=860) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpge_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3568,7 +3568,7 @@ pub fn _mm256_mask_cmpge_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epi8_mask&expand=857) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpge_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_ge(a.as_i8x16(), b.as_i8x16())) } @@ -3579,7 +3579,7 @@ pub fn _mm_cmpge_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epi8_mask&expand=858) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpge_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epi8_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -3590,7 +3590,7 @@ pub fn _mm_mask_cmpge_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epu16_mask&expand=801) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpeq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_eq(a.as_u16x32(), b.as_u16x32())) } @@ -3601,7 +3601,7 @@ pub fn _mm512_cmpeq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epu16_mask&expand=802) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpeq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3612,7 +3612,7 @@ pub fn _mm512_mask_cmpeq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epu16_mask&expand=799) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpeq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_eq(a.as_u16x16(), b.as_u16x16())) } @@ -3623,7 +3623,7 @@ pub fn _mm256_cmpeq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epu16_mask&expand=800) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpeq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3634,7 +3634,7 @@ pub fn _mm256_mask_cmpeq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epu16_mask&expand=797) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpeq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_eq(a.as_u16x8(), b.as_u16x8())) } @@ -3645,7 +3645,7 @@ pub fn _mm_cmpeq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epu16_mask&expand=798) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpeq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu16_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3656,7 +3656,7 @@ pub fn _mm_mask_cmpeq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epu8_mask&expand=819) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpeq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_eq(a.as_u8x64(), b.as_u8x64())) } @@ -3667,7 +3667,7 @@ pub fn _mm512_cmpeq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epu8_mask&expand=820) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpeq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3678,7 +3678,7 @@ pub fn _mm512_mask_cmpeq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epu8_mask&expand=817) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpeq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_eq(a.as_u8x32(), b.as_u8x32())) } @@ -3689,7 +3689,7 @@ pub fn _mm256_cmpeq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epu8_mask&expand=818) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpeq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3700,7 +3700,7 @@ pub fn _mm256_mask_cmpeq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epu8_mask&expand=815) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpeq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_eq(a.as_u8x16(), b.as_u8x16())) } @@ -3711,7 +3711,7 @@ pub fn _mm_cmpeq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epu8_mask&expand=816) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpeq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epu8_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3722,7 +3722,7 @@ pub fn _mm_mask_cmpeq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epi16_mask&expand=771) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpeq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_eq(a.as_i16x32(), b.as_i16x32())) } @@ -3733,7 +3733,7 @@ pub fn _mm512_cmpeq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epi16_mask&expand=772) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpeq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3744,7 +3744,7 @@ pub fn _mm512_mask_cmpeq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epi16_mask&expand=769) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpeq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_eq(a.as_i16x16(), b.as_i16x16())) } @@ -3755,7 +3755,7 @@ pub fn _mm256_cmpeq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epi16_mask&expand=770) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpeq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3766,7 +3766,7 @@ pub fn _mm256_mask_cmpeq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi16_mask&expand=767) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpeq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_eq(a.as_i16x8(), b.as_i16x8())) } @@ -3777,7 +3777,7 @@ pub fn _mm_cmpeq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epi16_mask&expand=768) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpeq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi16_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3788,7 +3788,7 @@ pub fn _mm_mask_cmpeq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epi8_mask&expand=795) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpeq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_eq(a.as_i8x64(), b.as_i8x64())) } @@ -3799,7 +3799,7 @@ pub fn _mm512_cmpeq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epi8_mask&expand=796) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpeq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3810,7 +3810,7 @@ pub fn _mm512_mask_cmpeq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epi8_mask&expand=793) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpeq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_eq(a.as_i8x32(), b.as_i8x32())) } @@ -3821,7 +3821,7 @@ pub fn _mm256_cmpeq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epi8_mask&expand=794) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpeq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3832,7 +3832,7 @@ pub fn _mm256_mask_cmpeq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi8_mask&expand=791) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpeq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_eq(a.as_i8x16(), b.as_i8x16())) } @@ -3843,7 +3843,7 @@ pub fn _mm_cmpeq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epi8_mask&expand=792) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpeq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epi8_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -3854,7 +3854,7 @@ pub fn _mm_mask_cmpeq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epu16_mask&expand=1106) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpneq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_ne(a.as_u16x32(), b.as_u16x32())) } @@ -3865,7 +3865,7 @@ pub fn _mm512_cmpneq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epu16_mask&expand=1107) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpneq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -3876,7 +3876,7 @@ pub fn _mm512_mask_cmpneq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epu16_mask&expand=1104) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpneq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_ne(a.as_u16x16(), b.as_u16x16())) } @@ -3887,7 +3887,7 @@ pub fn _mm256_cmpneq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epu16_mask&expand=1105) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpneq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -3898,7 +3898,7 @@ pub fn _mm256_mask_cmpneq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epu16_mask&expand=1102) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpneq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_ne(a.as_u16x8(), b.as_u16x8())) } @@ -3909,7 +3909,7 @@ pub fn _mm_cmpneq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epu16_mask&expand=1103) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpneq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu16_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -3920,7 +3920,7 @@ pub fn _mm_mask_cmpneq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epu8_mask&expand=1124) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpneq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_ne(a.as_u8x64(), b.as_u8x64())) } @@ -3931,7 +3931,7 @@ pub fn _mm512_cmpneq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epu8_mask&expand=1125) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpneq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -3942,7 +3942,7 @@ pub fn _mm512_mask_cmpneq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epu8_mask&expand=1122) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpneq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_ne(a.as_u8x32(), b.as_u8x32())) } @@ -3953,7 +3953,7 @@ pub fn _mm256_cmpneq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epu8_mask&expand=1123) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpneq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -3964,7 +3964,7 @@ pub fn _mm256_mask_cmpneq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epu8_mask&expand=1120) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpneq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_ne(a.as_u8x16(), b.as_u8x16())) } @@ -3975,7 +3975,7 @@ pub fn _mm_cmpneq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epu8_mask&expand=1121) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpneq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epu8_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -3986,7 +3986,7 @@ pub fn _mm_mask_cmpneq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epi16_mask&expand=1082) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpneq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { unsafe { simd_bitmask::(simd_ne(a.as_i16x32(), b.as_i16x32())) } @@ -3997,7 +3997,7 @@ pub fn _mm512_cmpneq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epi16_mask&expand=1083) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpneq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -4008,7 +4008,7 @@ pub fn _mm512_mask_cmpneq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epi16_mask&expand=1080) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpneq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { unsafe { simd_bitmask::(simd_ne(a.as_i16x16(), b.as_i16x16())) } @@ -4019,7 +4019,7 @@ pub fn _mm256_cmpneq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epi16_mask&expand=1081) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpneq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -4030,7 +4030,7 @@ pub fn _mm256_mask_cmpneq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epi16_mask&expand=1078) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpneq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_ne(a.as_i16x8(), b.as_i16x8())) } @@ -4041,7 +4041,7 @@ pub fn _mm_cmpneq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epi16_mask&expand=1079) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpneq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi16_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -4052,7 +4052,7 @@ pub fn _mm_mask_cmpneq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epi8_mask&expand=1100) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_cmpneq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { unsafe { simd_bitmask::(simd_ne(a.as_i8x64(), b.as_i8x64())) } @@ -4063,7 +4063,7 @@ pub fn _mm512_cmpneq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epi8_mask&expand=1101) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm512_mask_cmpneq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -4074,7 +4074,7 @@ pub fn _mm512_mask_cmpneq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epi8_mask&expand=1098) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_cmpneq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { unsafe { simd_bitmask::(simd_ne(a.as_i8x32(), b.as_i8x32())) } @@ -4085,7 +4085,7 @@ pub fn _mm256_cmpneq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epi8_mask&expand=1099) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm256_mask_cmpneq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -4096,7 +4096,7 @@ pub fn _mm256_mask_cmpneq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epi8_mask&expand=1096) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_cmpneq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { unsafe { simd_bitmask::(simd_ne(a.as_i8x16(), b.as_i8x16())) } @@ -4107,7 +4107,7 @@ pub fn _mm_cmpneq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epi8_mask&expand=1097) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] pub fn _mm_mask_cmpneq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { _mm_mask_cmp_epi8_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -4118,7 +4118,7 @@ pub fn _mm_mask_cmpneq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epu16_mask&expand=715) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm512_cmp_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { @@ -4145,7 +4145,7 @@ pub fn _mm512_cmp_epu16_mask(a: __m512i, b: __m512i) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epu16_mask&expand=716) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm512_mask_cmp_epu16_mask( @@ -4177,7 +4177,7 @@ pub fn _mm512_mask_cmp_epu16_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epu16_mask&expand=713) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm256_cmp_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { @@ -4204,7 +4204,7 @@ pub fn _mm256_cmp_epu16_mask(a: __m256i, b: __m256i) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epu16_mask&expand=714) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm256_mask_cmp_epu16_mask( @@ -4236,7 +4236,7 @@ pub fn _mm256_mask_cmp_epu16_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epu16_mask&expand=711) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm_cmp_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { @@ -4263,7 +4263,7 @@ pub fn _mm_cmp_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epu16_mask&expand=712) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm_mask_cmp_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { @@ -4291,7 +4291,7 @@ pub fn _mm_mask_cmp_epu16_mask(k1: __mmask8, a: __m128i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epu8_mask&expand=733) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm512_cmp_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { @@ -4318,7 +4318,7 @@ pub fn _mm512_cmp_epu8_mask(a: __m512i, b: __m512i) -> __mmask6 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epu8_mask&expand=734) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm512_mask_cmp_epu8_mask( @@ -4350,7 +4350,7 @@ pub fn _mm512_mask_cmp_epu8_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epu8_mask&expand=731) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm256_cmp_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { @@ -4377,7 +4377,7 @@ pub fn _mm256_cmp_epu8_mask(a: __m256i, b: __m256i) -> __mmask3 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epu8_mask&expand=732) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm256_mask_cmp_epu8_mask( @@ -4409,7 +4409,7 @@ pub fn _mm256_mask_cmp_epu8_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epu8_mask&expand=729) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm_cmp_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { @@ -4436,7 +4436,7 @@ pub fn _mm_cmp_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epu8_mask&expand=730) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm_mask_cmp_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { @@ -4464,7 +4464,7 @@ pub fn _mm_mask_cmp_epu8_mask(k1: __mmask16, a: __m128i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epi16_mask&expand=691) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm512_cmp_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { @@ -4491,7 +4491,7 @@ pub fn _mm512_cmp_epi16_mask(a: __m512i, b: __m512i) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epi16_mask&expand=692) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm512_mask_cmp_epi16_mask( @@ -4523,7 +4523,7 @@ pub fn _mm512_mask_cmp_epi16_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epi16_mask&expand=689) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm256_cmp_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { @@ -4550,7 +4550,7 @@ pub fn _mm256_cmp_epi16_mask(a: __m256i, b: __m256i) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epi16_mask&expand=690) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm256_mask_cmp_epi16_mask( @@ -4582,7 +4582,7 @@ pub fn _mm256_mask_cmp_epi16_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epi16_mask&expand=687) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm_cmp_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { @@ -4609,7 +4609,7 @@ pub fn _mm_cmp_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epi16_mask&expand=688) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm_mask_cmp_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { @@ -4637,7 +4637,7 @@ pub fn _mm_mask_cmp_epi16_mask(k1: __mmask8, a: __m128i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epi8_mask&expand=709) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm512_cmp_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { @@ -4664,7 +4664,7 @@ pub fn _mm512_cmp_epi8_mask(a: __m512i, b: __m512i) -> __mmask6 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epi8_mask&expand=710) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm512_mask_cmp_epi8_mask( @@ -4696,7 +4696,7 @@ pub fn _mm512_mask_cmp_epi8_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epi8_mask&expand=707) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm256_cmp_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { @@ -4723,7 +4723,7 @@ pub fn _mm256_cmp_epi8_mask(a: __m256i, b: __m256i) -> __mmask3 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epi8_mask&expand=708) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm256_mask_cmp_epi8_mask( @@ -4755,7 +4755,7 @@ pub fn _mm256_mask_cmp_epi8_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epi8_mask&expand=705) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm_cmp_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { @@ -4782,7 +4782,7 @@ pub fn _mm_cmp_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epi8_mask&expand=706) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] pub fn _mm_mask_cmp_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { @@ -4810,7 +4810,7 @@ pub fn _mm_mask_cmp_epi8_mask(k1: __mmask16, a: __m128i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_add_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_add_epi16(a: __m256i) -> i16 { unsafe { simd_reduce_add_unordered(a.as_i16x16()) } } @@ -4820,7 +4820,7 @@ pub fn _mm256_reduce_add_epi16(a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_add_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_add_epi16(k: __mmask16, a: __m256i) -> i16 { unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i16x16(), i16x16::ZERO)) } } @@ -4830,7 +4830,7 @@ pub fn _mm256_mask_reduce_add_epi16(k: __mmask16, a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_add_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_add_epi16(a: __m128i) -> i16 { unsafe { simd_reduce_add_unordered(a.as_i16x8()) } } @@ -4840,7 +4840,7 @@ pub fn _mm_reduce_add_epi16(a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_add_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_add_epi16(k: __mmask8, a: __m128i) -> i16 { unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i16x8(), i16x8::ZERO)) } } @@ -4850,7 +4850,7 @@ pub fn _mm_mask_reduce_add_epi16(k: __mmask8, a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_add_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_add_epi8(a: __m256i) -> i8 { unsafe { simd_reduce_add_unordered(a.as_i8x32()) } } @@ -4860,7 +4860,7 @@ pub fn _mm256_reduce_add_epi8(a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_add_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_add_epi8(k: __mmask32, a: __m256i) -> i8 { unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i8x32(), i8x32::ZERO)) } } @@ -4870,7 +4870,7 @@ pub fn _mm256_mask_reduce_add_epi8(k: __mmask32, a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_add_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_add_epi8(a: __m128i) -> i8 { unsafe { simd_reduce_add_unordered(a.as_i8x16()) } } @@ -4880,7 +4880,7 @@ pub fn _mm_reduce_add_epi8(a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_add_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_add_epi8(k: __mmask16, a: __m128i) -> i8 { unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i8x16(), i8x16::ZERO)) } } @@ -4890,7 +4890,7 @@ pub fn _mm_mask_reduce_add_epi8(k: __mmask16, a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_and_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_and_epi16(a: __m256i) -> i16 { unsafe { simd_reduce_and(a.as_i16x16()) } } @@ -4900,7 +4900,7 @@ pub fn _mm256_reduce_and_epi16(a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_and_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_and_epi16(k: __mmask16, a: __m256i) -> i16 { unsafe { simd_reduce_and(simd_select_bitmask( @@ -4916,7 +4916,7 @@ pub fn _mm256_mask_reduce_and_epi16(k: __mmask16, a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_and_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_and_epi16(a: __m128i) -> i16 { unsafe { simd_reduce_and(a.as_i16x8()) } } @@ -4926,7 +4926,7 @@ pub fn _mm_reduce_and_epi16(a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_and_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_and_epi16(k: __mmask8, a: __m128i) -> i16 { unsafe { simd_reduce_and(simd_select_bitmask( @@ -4942,7 +4942,7 @@ pub fn _mm_mask_reduce_and_epi16(k: __mmask8, a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_and_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_and_epi8(a: __m256i) -> i8 { unsafe { simd_reduce_and(a.as_i8x32()) } } @@ -4952,7 +4952,7 @@ pub fn _mm256_reduce_and_epi8(a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_and_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_and_epi8(k: __mmask32, a: __m256i) -> i8 { unsafe { simd_reduce_and(simd_select_bitmask( @@ -4968,7 +4968,7 @@ pub fn _mm256_mask_reduce_and_epi8(k: __mmask32, a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_and_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_and_epi8(a: __m128i) -> i8 { unsafe { simd_reduce_and(a.as_i8x16()) } } @@ -4978,7 +4978,7 @@ pub fn _mm_reduce_and_epi8(a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_and_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_and_epi8(k: __mmask16, a: __m128i) -> i8 { unsafe { simd_reduce_and(simd_select_bitmask( @@ -4994,7 +4994,7 @@ pub fn _mm_mask_reduce_and_epi8(k: __mmask16, a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_max_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_max_epi16(a: __m256i) -> i16 { unsafe { simd_reduce_max(a.as_i16x16()) } } @@ -5004,7 +5004,7 @@ pub fn _mm256_reduce_max_epi16(a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_max_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_max_epi16(k: __mmask16, a: __m256i) -> i16 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i16x16(), i16x16::splat(-32768))) } } @@ -5014,7 +5014,7 @@ pub fn _mm256_mask_reduce_max_epi16(k: __mmask16, a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_max_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_max_epi16(a: __m128i) -> i16 { unsafe { simd_reduce_max(a.as_i16x8()) } } @@ -5024,7 +5024,7 @@ pub fn _mm_reduce_max_epi16(a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_max_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_max_epi16(k: __mmask8, a: __m128i) -> i16 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i16x8(), i16x8::splat(-32768))) } } @@ -5034,7 +5034,7 @@ pub fn _mm_mask_reduce_max_epi16(k: __mmask8, a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_max_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_max_epi8(a: __m256i) -> i8 { unsafe { simd_reduce_max(a.as_i8x32()) } } @@ -5044,7 +5044,7 @@ pub fn _mm256_reduce_max_epi8(a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_max_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_max_epi8(k: __mmask32, a: __m256i) -> i8 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i8x32(), i8x32::splat(-128))) } } @@ -5054,7 +5054,7 @@ pub fn _mm256_mask_reduce_max_epi8(k: __mmask32, a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_max_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_max_epi8(a: __m128i) -> i8 { unsafe { simd_reduce_max(a.as_i8x16()) } } @@ -5064,7 +5064,7 @@ pub fn _mm_reduce_max_epi8(a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_max_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_max_epi8(k: __mmask16, a: __m128i) -> i8 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i8x16(), i8x16::splat(-128))) } } @@ -5074,7 +5074,7 @@ pub fn _mm_mask_reduce_max_epi8(k: __mmask16, a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_max_epu16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_max_epu16(a: __m256i) -> u16 { unsafe { simd_reduce_max(a.as_u16x16()) } } @@ -5084,7 +5084,7 @@ pub fn _mm256_reduce_max_epu16(a: __m256i) -> u16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_max_epu16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_max_epu16(k: __mmask16, a: __m256i) -> u16 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u16x16(), u16x16::ZERO)) } } @@ -5094,7 +5094,7 @@ pub fn _mm256_mask_reduce_max_epu16(k: __mmask16, a: __m256i) -> u16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_max_epu16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_max_epu16(a: __m128i) -> u16 { unsafe { simd_reduce_max(a.as_u16x8()) } } @@ -5104,7 +5104,7 @@ pub fn _mm_reduce_max_epu16(a: __m128i) -> u16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_max_epu16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_max_epu16(k: __mmask8, a: __m128i) -> u16 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u16x8(), u16x8::ZERO)) } } @@ -5114,7 +5114,7 @@ pub fn _mm_mask_reduce_max_epu16(k: __mmask8, a: __m128i) -> u16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_max_epu8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_max_epu8(a: __m256i) -> u8 { unsafe { simd_reduce_max(a.as_u8x32()) } } @@ -5124,7 +5124,7 @@ pub fn _mm256_reduce_max_epu8(a: __m256i) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_max_epu8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_max_epu8(k: __mmask32, a: __m256i) -> u8 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u8x32(), u8x32::ZERO)) } } @@ -5134,7 +5134,7 @@ pub fn _mm256_mask_reduce_max_epu8(k: __mmask32, a: __m256i) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_max_epu8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_max_epu8(a: __m128i) -> u8 { unsafe { simd_reduce_max(a.as_u8x16()) } } @@ -5144,7 +5144,7 @@ pub fn _mm_reduce_max_epu8(a: __m128i) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_max_epu8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_max_epu8(k: __mmask16, a: __m128i) -> u8 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u8x16(), u8x16::ZERO)) } } @@ -5154,7 +5154,7 @@ pub fn _mm_mask_reduce_max_epu8(k: __mmask16, a: __m128i) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_min_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_min_epi16(a: __m256i) -> i16 { unsafe { simd_reduce_min(a.as_i16x16()) } } @@ -5164,7 +5164,7 @@ pub fn _mm256_reduce_min_epi16(a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_min_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_min_epi16(k: __mmask16, a: __m256i) -> i16 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i16x16(), i16x16::splat(0x7fff))) } } @@ -5174,7 +5174,7 @@ pub fn _mm256_mask_reduce_min_epi16(k: __mmask16, a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_min_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_min_epi16(a: __m128i) -> i16 { unsafe { simd_reduce_min(a.as_i16x8()) } } @@ -5184,7 +5184,7 @@ pub fn _mm_reduce_min_epi16(a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_min_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_min_epi16(k: __mmask8, a: __m128i) -> i16 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i16x8(), i16x8::splat(0x7fff))) } } @@ -5194,7 +5194,7 @@ pub fn _mm_mask_reduce_min_epi16(k: __mmask8, a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_min_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_min_epi8(a: __m256i) -> i8 { unsafe { simd_reduce_min(a.as_i8x32()) } } @@ -5204,7 +5204,7 @@ pub fn _mm256_reduce_min_epi8(a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_min_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_min_epi8(k: __mmask32, a: __m256i) -> i8 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i8x32(), i8x32::splat(0x7f))) } } @@ -5214,7 +5214,7 @@ pub fn _mm256_mask_reduce_min_epi8(k: __mmask32, a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_min_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_min_epi8(a: __m128i) -> i8 { unsafe { simd_reduce_min(a.as_i8x16()) } } @@ -5224,7 +5224,7 @@ pub fn _mm_reduce_min_epi8(a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_min_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_min_epi8(k: __mmask16, a: __m128i) -> i8 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i8x16(), i8x16::splat(0x7f))) } } @@ -5234,7 +5234,7 @@ pub fn _mm_mask_reduce_min_epi8(k: __mmask16, a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_min_epu16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_min_epu16(a: __m256i) -> u16 { unsafe { simd_reduce_min(a.as_u16x16()) } } @@ -5244,7 +5244,7 @@ pub fn _mm256_reduce_min_epu16(a: __m256i) -> u16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_min_epu16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_min_epu16(k: __mmask16, a: __m256i) -> u16 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u16x16(), u16x16::splat(0xffff))) } } @@ -5254,7 +5254,7 @@ pub fn _mm256_mask_reduce_min_epu16(k: __mmask16, a: __m256i) -> u16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_min_epu16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_min_epu16(a: __m128i) -> u16 { unsafe { simd_reduce_min(a.as_u16x8()) } } @@ -5264,7 +5264,7 @@ pub fn _mm_reduce_min_epu16(a: __m128i) -> u16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_min_epu16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_min_epu16(k: __mmask8, a: __m128i) -> u16 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u16x8(), u16x8::splat(0xffff))) } } @@ -5274,7 +5274,7 @@ pub fn _mm_mask_reduce_min_epu16(k: __mmask8, a: __m128i) -> u16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_min_epu8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_min_epu8(a: __m256i) -> u8 { unsafe { simd_reduce_min(a.as_u8x32()) } } @@ -5284,7 +5284,7 @@ pub fn _mm256_reduce_min_epu8(a: __m256i) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_min_epu8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_min_epu8(k: __mmask32, a: __m256i) -> u8 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u8x32(), u8x32::splat(0xff))) } } @@ -5294,7 +5294,7 @@ pub fn _mm256_mask_reduce_min_epu8(k: __mmask32, a: __m256i) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_min_epu8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_min_epu8(a: __m128i) -> u8 { unsafe { simd_reduce_min(a.as_u8x16()) } } @@ -5304,7 +5304,7 @@ pub fn _mm_reduce_min_epu8(a: __m128i) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_min_epu8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_min_epu8(k: __mmask16, a: __m128i) -> u8 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u8x16(), u8x16::splat(0xff))) } } @@ -5314,7 +5314,7 @@ pub fn _mm_mask_reduce_min_epu8(k: __mmask16, a: __m128i) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_mul_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_mul_epi16(a: __m256i) -> i16 { unsafe { simd_reduce_mul_unordered(a.as_i16x16()) } } @@ -5324,7 +5324,7 @@ pub fn _mm256_reduce_mul_epi16(a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_mul_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_mul_epi16(k: __mmask16, a: __m256i) -> i16 { unsafe { simd_reduce_mul_unordered(simd_select_bitmask(k, a.as_i16x16(), i16x16::splat(1))) } } @@ -5334,7 +5334,7 @@ pub fn _mm256_mask_reduce_mul_epi16(k: __mmask16, a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_mul_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_mul_epi16(a: __m128i) -> i16 { unsafe { simd_reduce_mul_unordered(a.as_i16x8()) } } @@ -5344,7 +5344,7 @@ pub fn _mm_reduce_mul_epi16(a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_mul_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_mul_epi16(k: __mmask8, a: __m128i) -> i16 { unsafe { simd_reduce_mul_unordered(simd_select_bitmask(k, a.as_i16x8(), i16x8::splat(1))) } } @@ -5354,7 +5354,7 @@ pub fn _mm_mask_reduce_mul_epi16(k: __mmask8, a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_mul_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_mul_epi8(a: __m256i) -> i8 { unsafe { simd_reduce_mul_unordered(a.as_i8x32()) } } @@ -5364,7 +5364,7 @@ pub fn _mm256_reduce_mul_epi8(a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_mul_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_mul_epi8(k: __mmask32, a: __m256i) -> i8 { unsafe { simd_reduce_mul_unordered(simd_select_bitmask(k, a.as_i8x32(), i8x32::splat(1))) } } @@ -5374,7 +5374,7 @@ pub fn _mm256_mask_reduce_mul_epi8(k: __mmask32, a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_mul_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_mul_epi8(a: __m128i) -> i8 { unsafe { simd_reduce_mul_unordered(a.as_i8x16()) } } @@ -5384,7 +5384,7 @@ pub fn _mm_reduce_mul_epi8(a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_mul_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_mul_epi8(k: __mmask16, a: __m128i) -> i8 { unsafe { simd_reduce_mul_unordered(simd_select_bitmask(k, a.as_i8x16(), i8x16::splat(1))) } } @@ -5394,7 +5394,7 @@ pub fn _mm_mask_reduce_mul_epi8(k: __mmask16, a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_or_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_or_epi16(a: __m256i) -> i16 { unsafe { simd_reduce_or(a.as_i16x16()) } } @@ -5404,7 +5404,7 @@ pub fn _mm256_reduce_or_epi16(a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_or_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_or_epi16(k: __mmask16, a: __m256i) -> i16 { unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i16x16(), i16x16::ZERO)) } } @@ -5414,7 +5414,7 @@ pub fn _mm256_mask_reduce_or_epi16(k: __mmask16, a: __m256i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_or_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_or_epi16(a: __m128i) -> i16 { unsafe { simd_reduce_or(a.as_i16x8()) } } @@ -5424,7 +5424,7 @@ pub fn _mm_reduce_or_epi16(a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_or_epi16) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_or_epi16(k: __mmask8, a: __m128i) -> i16 { unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i16x8(), i16x8::ZERO)) } } @@ -5434,7 +5434,7 @@ pub fn _mm_mask_reduce_or_epi16(k: __mmask8, a: __m128i) -> i16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_reduce_or_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_or_epi8(a: __m256i) -> i8 { unsafe { simd_reduce_or(a.as_i8x32()) } } @@ -5444,7 +5444,7 @@ pub fn _mm256_reduce_or_epi8(a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_reduce_or_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_or_epi8(k: __mmask32, a: __m256i) -> i8 { unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i8x32(), i8x32::ZERO)) } } @@ -5454,7 +5454,7 @@ pub fn _mm256_mask_reduce_or_epi8(k: __mmask32, a: __m256i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_reduce_or_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_or_epi8(a: __m128i) -> i8 { unsafe { simd_reduce_or(a.as_i8x16()) } } @@ -5464,7 +5464,7 @@ pub fn _mm_reduce_or_epi8(a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_reduce_or_epi8) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_or_epi8(k: __mmask16, a: __m128i) -> i8 { unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i8x16(), i8x16::ZERO)) } } @@ -5474,7 +5474,7 @@ pub fn _mm_mask_reduce_or_epi8(k: __mmask16, a: __m128i) -> i8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_epi16&expand=3368) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16 pub unsafe fn _mm512_loadu_epi16(mem_addr: *const i16) -> __m512i { ptr::read_unaligned(mem_addr as *const __m512i) @@ -5485,7 +5485,7 @@ pub unsafe fn _mm512_loadu_epi16(mem_addr: *const i16) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_loadu_epi16&expand=3365) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16 pub unsafe fn _mm256_loadu_epi16(mem_addr: *const i16) -> __m256i { ptr::read_unaligned(mem_addr as *const __m256i) @@ -5496,7 +5496,7 @@ pub unsafe fn _mm256_loadu_epi16(mem_addr: *const i16) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadu_epi16&expand=3362) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16 pub unsafe fn _mm_loadu_epi16(mem_addr: *const i16) -> __m128i { ptr::read_unaligned(mem_addr as *const __m128i) @@ -5507,7 +5507,7 @@ pub unsafe fn _mm_loadu_epi16(mem_addr: *const i16) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_epi8&expand=3395) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8 pub unsafe fn _mm512_loadu_epi8(mem_addr: *const i8) -> __m512i { ptr::read_unaligned(mem_addr as *const __m512i) @@ -5518,7 +5518,7 @@ pub unsafe fn _mm512_loadu_epi8(mem_addr: *const i8) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_loadu_epi8&expand=3392) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8 pub unsafe fn _mm256_loadu_epi8(mem_addr: *const i8) -> __m256i { ptr::read_unaligned(mem_addr as *const __m256i) @@ -5529,7 +5529,7 @@ pub unsafe fn _mm256_loadu_epi8(mem_addr: *const i8) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadu_epi8&expand=3389) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8 pub unsafe fn _mm_loadu_epi8(mem_addr: *const i8) -> __m128i { ptr::read_unaligned(mem_addr as *const __m128i) @@ -5540,7 +5540,7 @@ pub unsafe fn _mm_loadu_epi8(mem_addr: *const i8) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_epi16&expand=5622) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16 pub unsafe fn _mm512_storeu_epi16(mem_addr: *mut i16, a: __m512i) { ptr::write_unaligned(mem_addr as *mut __m512i, a); @@ -5551,7 +5551,7 @@ pub unsafe fn _mm512_storeu_epi16(mem_addr: *mut i16, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_storeu_epi16&expand=5620) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16 pub unsafe fn _mm256_storeu_epi16(mem_addr: *mut i16, a: __m256i) { ptr::write_unaligned(mem_addr as *mut __m256i, a); @@ -5562,7 +5562,7 @@ pub unsafe fn _mm256_storeu_epi16(mem_addr: *mut i16, a: __m256i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeu_epi16&expand=5618) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16 pub unsafe fn _mm_storeu_epi16(mem_addr: *mut i16, a: __m128i) { ptr::write_unaligned(mem_addr as *mut __m128i, a); @@ -5573,7 +5573,7 @@ pub unsafe fn _mm_storeu_epi16(mem_addr: *mut i16, a: __m128i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_epi8&expand=5640) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8 pub unsafe fn _mm512_storeu_epi8(mem_addr: *mut i8, a: __m512i) { ptr::write_unaligned(mem_addr as *mut __m512i, a); @@ -5584,7 +5584,7 @@ pub unsafe fn _mm512_storeu_epi8(mem_addr: *mut i8, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_storeu_epi8&expand=5638) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8 pub unsafe fn _mm256_storeu_epi8(mem_addr: *mut i8, a: __m256i) { ptr::write_unaligned(mem_addr as *mut __m256i, a); @@ -5595,7 +5595,7 @@ pub unsafe fn _mm256_storeu_epi8(mem_addr: *mut i8, a: __m256i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeu_epi8&expand=5636) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8 pub unsafe fn _mm_storeu_epi8(mem_addr: *mut i8, a: __m128i) { ptr::write_unaligned(mem_addr as *mut __m128i, a); @@ -5609,7 +5609,7 @@ pub unsafe fn _mm_storeu_epi8(mem_addr: *mut i8, a: __m128i) { #[inline] #[target_feature(enable = "avx512bw")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_loadu_epi16(src: __m512i, k: __mmask32, mem_addr: *const i16) -> __m512i { transmute(loaddqu16_512(mem_addr, src.as_i16x32(), k)) } @@ -5622,7 +5622,7 @@ pub unsafe fn _mm512_mask_loadu_epi16(src: __m512i, k: __mmask32, mem_addr: *con #[inline] #[target_feature(enable = "avx512bw")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_loadu_epi16(k: __mmask32, mem_addr: *const i16) -> __m512i { _mm512_mask_loadu_epi16(_mm512_setzero_si512(), k, mem_addr) } @@ -5635,7 +5635,7 @@ pub unsafe fn _mm512_maskz_loadu_epi16(k: __mmask32, mem_addr: *const i16) -> __ #[inline] #[target_feature(enable = "avx512bw")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_loadu_epi8(src: __m512i, k: __mmask64, mem_addr: *const i8) -> __m512i { transmute(loaddqu8_512(mem_addr, src.as_i8x64(), k)) } @@ -5648,7 +5648,7 @@ pub unsafe fn _mm512_mask_loadu_epi8(src: __m512i, k: __mmask64, mem_addr: *cons #[inline] #[target_feature(enable = "avx512bw")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_loadu_epi8(k: __mmask64, mem_addr: *const i8) -> __m512i { _mm512_mask_loadu_epi8(_mm512_setzero_si512(), k, mem_addr) } @@ -5661,7 +5661,7 @@ pub unsafe fn _mm512_maskz_loadu_epi8(k: __mmask64, mem_addr: *const i8) -> __m5 #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_loadu_epi16(src: __m256i, k: __mmask16, mem_addr: *const i16) -> __m256i { transmute(loaddqu16_256(mem_addr, src.as_i16x16(), k)) } @@ -5674,7 +5674,7 @@ pub unsafe fn _mm256_mask_loadu_epi16(src: __m256i, k: __mmask16, mem_addr: *con #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_loadu_epi16(k: __mmask16, mem_addr: *const i16) -> __m256i { _mm256_mask_loadu_epi16(_mm256_setzero_si256(), k, mem_addr) } @@ -5687,7 +5687,7 @@ pub unsafe fn _mm256_maskz_loadu_epi16(k: __mmask16, mem_addr: *const i16) -> __ #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_loadu_epi8(src: __m256i, k: __mmask32, mem_addr: *const i8) -> __m256i { transmute(loaddqu8_256(mem_addr, src.as_i8x32(), k)) } @@ -5700,7 +5700,7 @@ pub unsafe fn _mm256_mask_loadu_epi8(src: __m256i, k: __mmask32, mem_addr: *cons #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_loadu_epi8(k: __mmask32, mem_addr: *const i8) -> __m256i { _mm256_mask_loadu_epi8(_mm256_setzero_si256(), k, mem_addr) } @@ -5713,7 +5713,7 @@ pub unsafe fn _mm256_maskz_loadu_epi8(k: __mmask32, mem_addr: *const i8) -> __m2 #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_loadu_epi16(src: __m128i, k: __mmask8, mem_addr: *const i16) -> __m128i { transmute(loaddqu16_128(mem_addr, src.as_i16x8(), k)) } @@ -5726,7 +5726,7 @@ pub unsafe fn _mm_mask_loadu_epi16(src: __m128i, k: __mmask8, mem_addr: *const i #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_loadu_epi16(k: __mmask8, mem_addr: *const i16) -> __m128i { _mm_mask_loadu_epi16(_mm_setzero_si128(), k, mem_addr) } @@ -5739,7 +5739,7 @@ pub unsafe fn _mm_maskz_loadu_epi16(k: __mmask8, mem_addr: *const i16) -> __m128 #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_loadu_epi8(src: __m128i, k: __mmask16, mem_addr: *const i8) -> __m128i { transmute(loaddqu8_128(mem_addr, src.as_i8x16(), k)) } @@ -5752,7 +5752,7 @@ pub unsafe fn _mm_mask_loadu_epi8(src: __m128i, k: __mmask16, mem_addr: *const i #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_loadu_epi8(k: __mmask16, mem_addr: *const i8) -> __m128i { _mm_mask_loadu_epi8(_mm_setzero_si128(), k, mem_addr) } @@ -5764,7 +5764,7 @@ pub unsafe fn _mm_maskz_loadu_epi8(k: __mmask16, mem_addr: *const i8) -> __m128i #[inline] #[target_feature(enable = "avx512bw")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask32, a: __m512i) { storedqu16_512(mem_addr, a.as_i16x32(), mask) } @@ -5776,7 +5776,7 @@ pub unsafe fn _mm512_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask32, a: _ #[inline] #[target_feature(enable = "avx512bw")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask64, a: __m512i) { storedqu8_512(mem_addr, a.as_i8x64(), mask) } @@ -5788,7 +5788,7 @@ pub unsafe fn _mm512_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask64, a: __m #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask16, a: __m256i) { storedqu16_256(mem_addr, a.as_i16x16(), mask) } @@ -5800,7 +5800,7 @@ pub unsafe fn _mm256_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask16, a: _ #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask32, a: __m256i) { storedqu8_256(mem_addr, a.as_i8x32(), mask) } @@ -5812,7 +5812,7 @@ pub unsafe fn _mm256_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask32, a: __m #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask8, a: __m128i) { storedqu16_128(mem_addr, a.as_i16x8(), mask) } @@ -5824,7 +5824,7 @@ pub unsafe fn _mm_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu8))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a: __m128i) { storedqu8_128(mem_addr, a.as_i8x16(), mask) } @@ -5834,7 +5834,7 @@ pub unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_madd_epi16&expand=3511) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddwd))] pub fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpmaddwd(a.as_i16x32(), b.as_i16x32())) } @@ -5845,7 +5845,7 @@ pub fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_madd_epi16&expand=3512) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddwd))] pub fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -5859,7 +5859,7 @@ pub fn _mm512_mask_madd_epi16(src: __m512i, k: __mmask16, a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_madd_epi16&expand=3513) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddwd))] pub fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -5873,7 +5873,7 @@ pub fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_madd_epi16&expand=3509) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddwd))] pub fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -5887,7 +5887,7 @@ pub fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_madd_epi16&expand=3510) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddwd))] pub fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -5901,7 +5901,7 @@ pub fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_madd_epi16&expand=3506) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddwd))] pub fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -5915,7 +5915,7 @@ pub fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_madd_epi16&expand=3507) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddwd))] pub fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -5929,7 +5929,7 @@ pub fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maddubs_epi16&expand=3539) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddubsw))] pub fn _mm512_maddubs_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpmaddubsw(a.as_i8x64(), b.as_i8x64())) } @@ -5940,7 +5940,7 @@ pub fn _mm512_maddubs_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_maddubs_epi16&expand=3540) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddubsw))] pub fn _mm512_mask_maddubs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -5954,7 +5954,7 @@ pub fn _mm512_mask_maddubs_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_maddubs_epi16&expand=3541) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddubsw))] pub fn _mm512_maskz_maddubs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -5968,7 +5968,7 @@ pub fn _mm512_maskz_maddubs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_maddubs_epi16&expand=3537) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddubsw))] pub fn _mm256_mask_maddubs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -5982,7 +5982,7 @@ pub fn _mm256_mask_maddubs_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_maddubs_epi16&expand=3538) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddubsw))] pub fn _mm256_maskz_maddubs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -5996,7 +5996,7 @@ pub fn _mm256_maskz_maddubs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_maddubs_epi16&expand=3534) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddubsw))] pub fn _mm_mask_maddubs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6010,7 +6010,7 @@ pub fn _mm_mask_maddubs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_maddubs_epi16&expand=3535) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaddubsw))] pub fn _mm_maskz_maddubs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6024,7 +6024,7 @@ pub fn _mm_maskz_maddubs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_packs_epi32&expand=4091) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpackssdw(a.as_i32x16(), b.as_i32x16())) } @@ -6035,7 +6035,7 @@ pub fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_packs_epi32&expand=4089) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] pub fn _mm512_mask_packs_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6049,7 +6049,7 @@ pub fn _mm512_mask_packs_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_packs_epi32&expand=4090) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] pub fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6063,7 +6063,7 @@ pub fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_packs_epi32&expand=4086) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] pub fn _mm256_mask_packs_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6077,7 +6077,7 @@ pub fn _mm256_mask_packs_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_packs_epi32&expand=4087) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] pub fn _mm256_maskz_packs_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6091,7 +6091,7 @@ pub fn _mm256_maskz_packs_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_packs_epi32&expand=4083) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] pub fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6105,7 +6105,7 @@ pub fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_packs_epi32&expand=4084) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackssdw))] pub fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6119,7 +6119,7 @@ pub fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_packs_epi16&expand=4082) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpacksswb(a.as_i16x32(), b.as_i16x32())) } @@ -6130,7 +6130,7 @@ pub fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_packs_epi16&expand=4080) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] pub fn _mm512_mask_packs_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6144,7 +6144,7 @@ pub fn _mm512_mask_packs_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_packs_epi16&expand=4081) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] pub fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6158,7 +6158,7 @@ pub fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_packs_epi16&expand=4077) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] pub fn _mm256_mask_packs_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6172,7 +6172,7 @@ pub fn _mm256_mask_packs_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm256_maskz_packs_epi16&expand=4078) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] pub fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6186,7 +6186,7 @@ pub fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_packs_epi16&expand=4074) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] pub fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6200,7 +6200,7 @@ pub fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_packs_epi16&expand=4075) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpacksswb))] pub fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6214,7 +6214,7 @@ pub fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_packus_epi32&expand=4130) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpackusdw(a.as_i32x16(), b.as_i32x16())) } @@ -6225,7 +6225,7 @@ pub fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_packus_epi32&expand=4128) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] pub fn _mm512_mask_packus_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6239,7 +6239,7 @@ pub fn _mm512_mask_packus_epi32(src: __m512i, k: __mmask32, a: __m512i, b: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_packus_epi32&expand=4129) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] pub fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6253,7 +6253,7 @@ pub fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_packus_epi32&expand=4125) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] pub fn _mm256_mask_packus_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6267,7 +6267,7 @@ pub fn _mm256_mask_packus_epi32(src: __m256i, k: __mmask16, a: __m256i, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_packus_epi32&expand=4126) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] pub fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6281,7 +6281,7 @@ pub fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_packus_epi32&expand=4122) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] pub fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6295,7 +6295,7 @@ pub fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_packus_epi32&expand=4123) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackusdw))] pub fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6309,7 +6309,7 @@ pub fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_packus_epi16&expand=4121) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpackuswb(a.as_i16x32(), b.as_i16x32())) } @@ -6320,7 +6320,7 @@ pub fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_packus_epi16&expand=4119) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] pub fn _mm512_mask_packus_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6334,7 +6334,7 @@ pub fn _mm512_mask_packus_epi16(src: __m512i, k: __mmask64, a: __m512i, b: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_packus_epi16&expand=4120) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] pub fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6348,7 +6348,7 @@ pub fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_packus_epi16&expand=4116) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] pub fn _mm256_mask_packus_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6362,7 +6362,7 @@ pub fn _mm256_mask_packus_epi16(src: __m256i, k: __mmask32, a: __m256i, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_packus_epi16&expand=4117) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] pub fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6376,7 +6376,7 @@ pub fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_packus_epi16&expand=4113) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] pub fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6390,7 +6390,7 @@ pub fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_packus_epi16&expand=4114) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpackuswb))] pub fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6404,7 +6404,7 @@ pub fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_avg_epu16&expand=388) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgw))] pub fn _mm512_avg_epu16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6420,7 +6420,7 @@ pub fn _mm512_avg_epu16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_avg_epu16&expand=389) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgw))] pub fn _mm512_mask_avg_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6434,7 +6434,7 @@ pub fn _mm512_mask_avg_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_avg_epu16&expand=390) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgw))] pub fn _mm512_maskz_avg_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6448,7 +6448,7 @@ pub fn _mm512_maskz_avg_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_avg_epu16&expand=386) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgw))] pub fn _mm256_mask_avg_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6462,7 +6462,7 @@ pub fn _mm256_mask_avg_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_avg_epu16&expand=387) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgw))] pub fn _mm256_maskz_avg_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6476,7 +6476,7 @@ pub fn _mm256_maskz_avg_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_avg_epu16&expand=383) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgw))] pub fn _mm_mask_avg_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6490,7 +6490,7 @@ pub fn _mm_mask_avg_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_avg_epu16&expand=384) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgw))] pub fn _mm_maskz_avg_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6504,7 +6504,7 @@ pub fn _mm_maskz_avg_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_avg_epu8&expand=397) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgb))] pub fn _mm512_avg_epu8(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6520,7 +6520,7 @@ pub fn _mm512_avg_epu8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_avg_epu8&expand=398) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgb))] pub fn _mm512_mask_avg_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6534,7 +6534,7 @@ pub fn _mm512_mask_avg_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_avg_epu8&expand=399) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgb))] pub fn _mm512_maskz_avg_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -6548,7 +6548,7 @@ pub fn _mm512_maskz_avg_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_avg_epu8&expand=395) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgb))] pub fn _mm256_mask_avg_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6562,7 +6562,7 @@ pub fn _mm256_mask_avg_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_avg_epu8&expand=396) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgb))] pub fn _mm256_maskz_avg_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -6576,7 +6576,7 @@ pub fn _mm256_maskz_avg_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_avg_epu8&expand=392) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgb))] pub fn _mm_mask_avg_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6590,7 +6590,7 @@ pub fn _mm_mask_avg_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_avg_epu8&expand=393) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpavgb))] pub fn _mm_maskz_avg_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -6604,7 +6604,7 @@ pub fn _mm_maskz_avg_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sll_epi16&expand=5271) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw))] pub fn _mm512_sll_epi16(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpsllw(a.as_i16x32(), count.as_i16x8())) } @@ -6615,7 +6615,7 @@ pub fn _mm512_sll_epi16(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sll_epi16&expand=5269) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw))] pub fn _mm512_mask_sll_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -6629,7 +6629,7 @@ pub fn _mm512_mask_sll_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sll_epi16&expand=5270) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw))] pub fn _mm512_maskz_sll_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -6643,7 +6643,7 @@ pub fn _mm512_maskz_sll_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sll_epi16&expand=5266) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw))] pub fn _mm256_mask_sll_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -6657,7 +6657,7 @@ pub fn _mm256_mask_sll_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sll_epi16&expand=5267) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw))] pub fn _mm256_maskz_sll_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -6671,7 +6671,7 @@ pub fn _mm256_maskz_sll_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sll_epi16&expand=5263) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw))] pub fn _mm_mask_sll_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -6685,7 +6685,7 @@ pub fn _mm_mask_sll_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sll_epi16&expand=5264) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw))] pub fn _mm_maskz_sll_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -6699,7 +6699,7 @@ pub fn _mm_maskz_sll_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_slli_epi16&expand=5301) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] #[rustc_legacy_const_generics(1)] pub fn _mm512_slli_epi16(a: __m512i) -> __m512i { @@ -6718,7 +6718,7 @@ pub fn _mm512_slli_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_slli_epi16&expand=5299) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_slli_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { @@ -6738,7 +6738,7 @@ pub fn _mm512_mask_slli_epi16(src: __m512i, k: __mmask32, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_slli_epi16&expand=5300) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_slli_epi16(k: __mmask32, a: __m512i) -> __m512i { @@ -6758,7 +6758,7 @@ pub fn _mm512_maskz_slli_epi16(k: __mmask32, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_slli_epi16&expand=5296) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_slli_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i { @@ -6778,7 +6778,7 @@ pub fn _mm256_mask_slli_epi16(src: __m256i, k: __mmask16, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_slli_epi16&expand=5297) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_slli_epi16(k: __mmask16, a: __m256i) -> __m256i { @@ -6798,7 +6798,7 @@ pub fn _mm256_maskz_slli_epi16(k: __mmask16, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_slli_epi16&expand=5293) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_slli_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -6818,7 +6818,7 @@ pub fn _mm_mask_slli_epi16(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_slli_epi16&expand=5294) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_slli_epi16(k: __mmask8, a: __m128i) -> __m128i { @@ -6838,7 +6838,7 @@ pub fn _mm_maskz_slli_epi16(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sllv_epi16&expand=5333) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsllvw(a.as_i16x32(), count.as_i16x32())) } @@ -6849,7 +6849,7 @@ pub fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sllv_epi16&expand=5331) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm512_mask_sllv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -6863,7 +6863,7 @@ pub fn _mm512_mask_sllv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sllv_epi16&expand=5332) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -6877,7 +6877,7 @@ pub fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_sllv_epi16&expand=5330) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i { unsafe { transmute(vpsllvw256(a.as_i16x16(), count.as_i16x16())) } @@ -6888,7 +6888,7 @@ pub fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sllv_epi16&expand=5328) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm256_mask_sllv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -6902,7 +6902,7 @@ pub fn _mm256_mask_sllv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sllv_epi16&expand=5329) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -6916,7 +6916,7 @@ pub fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sllv_epi16&expand=5327) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i { unsafe { transmute(vpsllvw128(a.as_i16x8(), count.as_i16x8())) } @@ -6927,7 +6927,7 @@ pub fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sllv_epi16&expand=5325) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm_mask_sllv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -6941,7 +6941,7 @@ pub fn _mm_mask_sllv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sllv_epi16&expand=5326) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvw))] pub fn _mm_maskz_sllv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -6955,7 +6955,7 @@ pub fn _mm_maskz_sllv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srl_epi16&expand=5483) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw))] pub fn _mm512_srl_epi16(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpsrlw(a.as_i16x32(), count.as_i16x8())) } @@ -6966,7 +6966,7 @@ pub fn _mm512_srl_epi16(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srl_epi16&expand=5481) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw))] pub fn _mm512_mask_srl_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -6980,7 +6980,7 @@ pub fn _mm512_mask_srl_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srl_epi16&expand=5482) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw))] pub fn _mm512_maskz_srl_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -6994,7 +6994,7 @@ pub fn _mm512_maskz_srl_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srl_epi16&expand=5478) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw))] pub fn _mm256_mask_srl_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -7008,7 +7008,7 @@ pub fn _mm256_mask_srl_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srl_epi16&expand=5479) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw))] pub fn _mm256_maskz_srl_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -7022,7 +7022,7 @@ pub fn _mm256_maskz_srl_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srl_epi16&expand=5475) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw))] pub fn _mm_mask_srl_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -7036,7 +7036,7 @@ pub fn _mm_mask_srl_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srl_epi16&expand=5476) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw))] pub fn _mm_maskz_srl_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -7050,7 +7050,7 @@ pub fn _mm_maskz_srl_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srli_epi16&expand=5513) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] #[rustc_legacy_const_generics(1)] pub fn _mm512_srli_epi16(a: __m512i) -> __m512i { @@ -7069,7 +7069,7 @@ pub fn _mm512_srli_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srli_epi16&expand=5511) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_srli_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { @@ -7089,7 +7089,7 @@ pub fn _mm512_mask_srli_epi16(src: __m512i, k: __mmask32, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srli_epi16&expand=5512) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_srli_epi16(k: __mmask32, a: __m512i) -> __m512i { @@ -7110,7 +7110,7 @@ pub fn _mm512_maskz_srli_epi16(k: __mmask32, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srli_epi16&expand=5508) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_srli_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i { @@ -7126,7 +7126,7 @@ pub fn _mm256_mask_srli_epi16(src: __m256i, k: __mmask16, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srli_epi16&expand=5509) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_srli_epi16(k: __mmask16, a: __m256i) -> __m256i { @@ -7142,7 +7142,7 @@ pub fn _mm256_maskz_srli_epi16(k: __mmask16, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srli_epi16&expand=5505) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_srli_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -7158,7 +7158,7 @@ pub fn _mm_mask_srli_epi16(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srli_epi16&expand=5506) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_srli_epi16(k: __mmask8, a: __m128i) -> __m128i { @@ -7174,7 +7174,7 @@ pub fn _mm_maskz_srli_epi16(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srlv_epi16&expand=5545) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsrlvw(a.as_i16x32(), count.as_i16x32())) } @@ -7185,7 +7185,7 @@ pub fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srlv_epi16&expand=5543) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm512_mask_srlv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -7199,7 +7199,7 @@ pub fn _mm512_mask_srlv_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srlv_epi16&expand=5544) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -7213,7 +7213,7 @@ pub fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_srlv_epi16&expand=5542) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i { unsafe { transmute(vpsrlvw256(a.as_i16x16(), count.as_i16x16())) } @@ -7224,7 +7224,7 @@ pub fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srlv_epi16&expand=5540) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm256_mask_srlv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -7238,7 +7238,7 @@ pub fn _mm256_mask_srlv_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srlv_epi16&expand=5541) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -7252,7 +7252,7 @@ pub fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srlv_epi16&expand=5539) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i { unsafe { transmute(vpsrlvw128(a.as_i16x8(), count.as_i16x8())) } @@ -7263,7 +7263,7 @@ pub fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srlv_epi16&expand=5537) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm_mask_srlv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -7277,7 +7277,7 @@ pub fn _mm_mask_srlv_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srlv_epi16&expand=5538) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvw))] pub fn _mm_maskz_srlv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -7291,7 +7291,7 @@ pub fn _mm_maskz_srlv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sra_epi16&expand=5398) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw))] pub fn _mm512_sra_epi16(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpsraw(a.as_i16x32(), count.as_i16x8())) } @@ -7302,7 +7302,7 @@ pub fn _mm512_sra_epi16(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sra_epi16&expand=5396) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw))] pub fn _mm512_mask_sra_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -7316,7 +7316,7 @@ pub fn _mm512_mask_sra_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sra_epi16&expand=5397) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw))] pub fn _mm512_maskz_sra_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -7330,7 +7330,7 @@ pub fn _mm512_maskz_sra_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sra_epi16&expand=5393) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw))] pub fn _mm256_mask_sra_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -7344,7 +7344,7 @@ pub fn _mm256_mask_sra_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sra_epi16&expand=5394) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw))] pub fn _mm256_maskz_sra_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -7358,7 +7358,7 @@ pub fn _mm256_maskz_sra_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sra_epi16&expand=5390) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw))] pub fn _mm_mask_sra_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -7372,7 +7372,7 @@ pub fn _mm_mask_sra_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sra_epi16&expand=5391) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw))] pub fn _mm_maskz_sra_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -7386,7 +7386,7 @@ pub fn _mm_maskz_sra_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srai_epi16&expand=5427) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_srai_epi16(a: __m512i) -> __m512i { @@ -7401,7 +7401,7 @@ pub fn _mm512_srai_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srai_epi16&expand=5425) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_srai_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { @@ -7417,7 +7417,7 @@ pub fn _mm512_mask_srai_epi16(src: __m512i, k: __mmask32, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srai_epi16&expand=5426) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_srai_epi16(k: __mmask32, a: __m512i) -> __m512i { @@ -7433,7 +7433,7 @@ pub fn _mm512_maskz_srai_epi16(k: __mmask32, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srai_epi16&expand=5422) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_srai_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i { @@ -7449,7 +7449,7 @@ pub fn _mm256_mask_srai_epi16(src: __m256i, k: __mmask16, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srai_epi16&expand=5423) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_srai_epi16(k: __mmask16, a: __m256i) -> __m256i { @@ -7465,7 +7465,7 @@ pub fn _mm256_maskz_srai_epi16(k: __mmask16, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srai_epi16&expand=5419) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_srai_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -7481,7 +7481,7 @@ pub fn _mm_mask_srai_epi16(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srai_epi16&expand=5420) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_srai_epi16(k: __mmask8, a: __m128i) -> __m128i { @@ -7497,7 +7497,7 @@ pub fn _mm_maskz_srai_epi16(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srav_epi16&expand=5456) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsravw(a.as_i16x32(), count.as_i16x32())) } @@ -7508,7 +7508,7 @@ pub fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srav_epi16&expand=5454) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm512_mask_srav_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -7522,7 +7522,7 @@ pub fn _mm512_mask_srav_epi16(src: __m512i, k: __mmask32, a: __m512i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srav_epi16&expand=5455) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -7536,7 +7536,7 @@ pub fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_srav_epi16&expand=5453) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i { unsafe { transmute(vpsravw256(a.as_i16x16(), count.as_i16x16())) } @@ -7547,7 +7547,7 @@ pub fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srav_epi16&expand=5451) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm256_mask_srav_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -7561,7 +7561,7 @@ pub fn _mm256_mask_srav_epi16(src: __m256i, k: __mmask16, a: __m256i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srav_epi16&expand=5452) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -7575,7 +7575,7 @@ pub fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srav_epi16&expand=5450) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i { unsafe { transmute(vpsravw128(a.as_i16x8(), count.as_i16x8())) } @@ -7586,7 +7586,7 @@ pub fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srav_epi16&expand=5448) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm_mask_srav_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -7600,7 +7600,7 @@ pub fn _mm_mask_srav_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srav_epi16&expand=5449) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravw))] pub fn _mm_maskz_srav_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -7614,7 +7614,7 @@ pub fn _mm_maskz_srav_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex2var_epi16&expand=4226) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w pub fn _mm512_permutex2var_epi16(a: __m512i, idx: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpermi2w(a.as_i16x32(), idx.as_i16x32(), b.as_i16x32())) } @@ -7625,7 +7625,7 @@ pub fn _mm512_permutex2var_epi16(a: __m512i, idx: __m512i, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex2var_epi16&expand=4223) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2w))] pub fn _mm512_mask_permutex2var_epi16( a: __m512i, @@ -7644,7 +7644,7 @@ pub fn _mm512_mask_permutex2var_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex2var_epi16&expand=4225) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w pub fn _mm512_maskz_permutex2var_epi16( k: __mmask32, @@ -7663,7 +7663,7 @@ pub fn _mm512_maskz_permutex2var_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask2_permutex2var_epi16&expand=4224) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2w))] pub fn _mm512_mask2_permutex2var_epi16( a: __m512i, @@ -7682,7 +7682,7 @@ pub fn _mm512_mask2_permutex2var_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex2var_epi16&expand=4222) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w pub fn _mm256_permutex2var_epi16(a: __m256i, idx: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpermi2w256(a.as_i16x16(), idx.as_i16x16(), b.as_i16x16())) } @@ -7693,7 +7693,7 @@ pub fn _mm256_permutex2var_epi16(a: __m256i, idx: __m256i, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex2var_epi16&expand=4219) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2w))] pub fn _mm256_mask_permutex2var_epi16( a: __m256i, @@ -7712,7 +7712,7 @@ pub fn _mm256_mask_permutex2var_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex2var_epi16&expand=4221) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w pub fn _mm256_maskz_permutex2var_epi16( k: __mmask16, @@ -7731,7 +7731,7 @@ pub fn _mm256_maskz_permutex2var_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask2_permutex2var_epi16&expand=4220) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2w))] pub fn _mm256_mask2_permutex2var_epi16( a: __m256i, @@ -7750,7 +7750,7 @@ pub fn _mm256_mask2_permutex2var_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutex2var_epi16&expand=4218) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w pub fn _mm_permutex2var_epi16(a: __m128i, idx: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpermi2w128(a.as_i16x8(), idx.as_i16x8(), b.as_i16x8())) } @@ -7761,7 +7761,7 @@ pub fn _mm_permutex2var_epi16(a: __m128i, idx: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutex2var_epi16&expand=4215) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2w))] pub fn _mm_mask_permutex2var_epi16(a: __m128i, k: __mmask8, idx: __m128i, b: __m128i) -> __m128i { unsafe { @@ -7775,7 +7775,7 @@ pub fn _mm_mask_permutex2var_epi16(a: __m128i, k: __mmask8, idx: __m128i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutex2var_epi16&expand=4217) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w pub fn _mm_maskz_permutex2var_epi16(k: __mmask8, a: __m128i, idx: __m128i, b: __m128i) -> __m128i { unsafe { @@ -7789,7 +7789,7 @@ pub fn _mm_maskz_permutex2var_epi16(k: __mmask8, a: __m128i, idx: __m128i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask2_permutex2var_epi16&expand=4216) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2w))] pub fn _mm_mask2_permutex2var_epi16(a: __m128i, idx: __m128i, k: __mmask8, b: __m128i) -> __m128i { unsafe { @@ -7803,7 +7803,7 @@ pub fn _mm_mask2_permutex2var_epi16(a: __m128i, idx: __m128i, k: __mmask8, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutexvar_epi16&expand=4295) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm512_permutexvar_epi16(idx: __m512i, a: __m512i) -> __m512i { unsafe { transmute(vpermw(a.as_i16x32(), idx.as_i16x32())) } @@ -7814,7 +7814,7 @@ pub fn _mm512_permutexvar_epi16(idx: __m512i, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutexvar_epi16&expand=4293) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm512_mask_permutexvar_epi16( src: __m512i, @@ -7833,7 +7833,7 @@ pub fn _mm512_mask_permutexvar_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutexvar_epi16&expand=4294) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm512_maskz_permutexvar_epi16(k: __mmask32, idx: __m512i, a: __m512i) -> __m512i { unsafe { @@ -7847,7 +7847,7 @@ pub fn _mm512_maskz_permutexvar_epi16(k: __mmask32, idx: __m512i, a: __m512i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutexvar_epi16&expand=4292) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm256_permutexvar_epi16(idx: __m256i, a: __m256i) -> __m256i { unsafe { transmute(vpermw256(a.as_i16x16(), idx.as_i16x16())) } @@ -7858,7 +7858,7 @@ pub fn _mm256_permutexvar_epi16(idx: __m256i, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutexvar_epi16&expand=4290) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm256_mask_permutexvar_epi16( src: __m256i, @@ -7877,7 +7877,7 @@ pub fn _mm256_mask_permutexvar_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutexvar_epi16&expand=4291) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm256_maskz_permutexvar_epi16(k: __mmask16, idx: __m256i, a: __m256i) -> __m256i { unsafe { @@ -7891,7 +7891,7 @@ pub fn _mm256_maskz_permutexvar_epi16(k: __mmask16, idx: __m256i, a: __m256i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutexvar_epi16&expand=4289) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm_permutexvar_epi16(idx: __m128i, a: __m128i) -> __m128i { unsafe { transmute(vpermw128(a.as_i16x8(), idx.as_i16x8())) } @@ -7902,7 +7902,7 @@ pub fn _mm_permutexvar_epi16(idx: __m128i, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutexvar_epi16&expand=4287) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm_mask_permutexvar_epi16(src: __m128i, k: __mmask8, idx: __m128i, a: __m128i) -> __m128i { unsafe { @@ -7916,7 +7916,7 @@ pub fn _mm_mask_permutexvar_epi16(src: __m128i, k: __mmask8, idx: __m128i, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutexvar_epi16&expand=4288) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermw))] pub fn _mm_maskz_permutexvar_epi16(k: __mmask8, idx: __m128i, a: __m128i) -> __m128i { unsafe { @@ -7930,7 +7930,7 @@ pub fn _mm_maskz_permutexvar_epi16(k: __mmask8, idx: __m128i, a: __m128i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_blend_epi16&expand=430) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw pub fn _mm512_mask_blend_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_select_bitmask(k, b.as_i16x32(), a.as_i16x32())) } @@ -7941,7 +7941,7 @@ pub fn _mm512_mask_blend_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_blend_epi16&expand=429) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw pub fn _mm256_mask_blend_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_select_bitmask(k, b.as_i16x16(), a.as_i16x16())) } @@ -7952,7 +7952,7 @@ pub fn _mm256_mask_blend_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_blend_epi16&expand=427) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw pub fn _mm_mask_blend_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_select_bitmask(k, b.as_i16x8(), a.as_i16x8())) } @@ -7963,7 +7963,7 @@ pub fn _mm_mask_blend_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_blend_epi8&expand=441) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb pub fn _mm512_mask_blend_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_select_bitmask(k, b.as_i8x64(), a.as_i8x64())) } @@ -7974,7 +7974,7 @@ pub fn _mm512_mask_blend_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_blend_epi8&expand=440) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb pub fn _mm256_mask_blend_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_select_bitmask(k, b.as_i8x32(), a.as_i8x32())) } @@ -7985,7 +7985,7 @@ pub fn _mm256_mask_blend_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_blend_epi8&expand=439) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb pub fn _mm_mask_blend_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_select_bitmask(k, b.as_i8x16(), a.as_i8x16())) } @@ -7996,7 +7996,7 @@ pub fn _mm_mask_blend_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastw_epi16&expand=587) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm512_broadcastw_epi16(a: __m128i) -> __m512i { unsafe { @@ -8018,7 +8018,7 @@ pub fn _mm512_broadcastw_epi16(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcastw_epi16&expand=588) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm512_mask_broadcastw_epi16(src: __m512i, k: __mmask32, a: __m128i) -> __m512i { unsafe { @@ -8032,7 +8032,7 @@ pub fn _mm512_mask_broadcastw_epi16(src: __m512i, k: __mmask32, a: __m128i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcastw_epi16&expand=589) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm512_maskz_broadcastw_epi16(k: __mmask32, a: __m128i) -> __m512i { unsafe { @@ -8046,7 +8046,7 @@ pub fn _mm512_maskz_broadcastw_epi16(k: __mmask32, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcastw_epi16&expand=585) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm256_mask_broadcastw_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i { unsafe { @@ -8060,7 +8060,7 @@ pub fn _mm256_mask_broadcastw_epi16(src: __m256i, k: __mmask16, a: __m128i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcastw_epi16&expand=586) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm256_maskz_broadcastw_epi16(k: __mmask16, a: __m128i) -> __m256i { unsafe { @@ -8074,7 +8074,7 @@ pub fn _mm256_maskz_broadcastw_epi16(k: __mmask16, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_broadcastw_epi16&expand=582) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm_mask_broadcastw_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -8088,7 +8088,7 @@ pub fn _mm_mask_broadcastw_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_broadcastw_epi16&expand=583) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm_maskz_broadcastw_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -8102,7 +8102,7 @@ pub fn _mm_maskz_broadcastw_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastb_epi8&expand=536) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastb))] pub fn _mm512_broadcastb_epi8(a: __m128i) -> __m512i { unsafe { @@ -8125,7 +8125,7 @@ pub fn _mm512_broadcastb_epi8(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcastb_epi8&expand=537) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastb))] pub fn _mm512_mask_broadcastb_epi8(src: __m512i, k: __mmask64, a: __m128i) -> __m512i { unsafe { @@ -8139,7 +8139,7 @@ pub fn _mm512_mask_broadcastb_epi8(src: __m512i, k: __mmask64, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcastb_epi8&expand=538) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastb))] pub fn _mm512_maskz_broadcastb_epi8(k: __mmask64, a: __m128i) -> __m512i { unsafe { @@ -8153,7 +8153,7 @@ pub fn _mm512_maskz_broadcastb_epi8(k: __mmask64, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcastb_epi8&expand=534) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastb))] pub fn _mm256_mask_broadcastb_epi8(src: __m256i, k: __mmask32, a: __m128i) -> __m256i { unsafe { @@ -8167,7 +8167,7 @@ pub fn _mm256_mask_broadcastb_epi8(src: __m256i, k: __mmask32, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcastb_epi8&expand=535) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastb))] pub fn _mm256_maskz_broadcastb_epi8(k: __mmask32, a: __m128i) -> __m256i { unsafe { @@ -8181,7 +8181,7 @@ pub fn _mm256_maskz_broadcastb_epi8(k: __mmask32, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_broadcastb_epi8&expand=531) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastb))] pub fn _mm_mask_broadcastb_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { unsafe { @@ -8195,7 +8195,7 @@ pub fn _mm_mask_broadcastb_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_broadcastb_epi8&expand=532) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastb))] pub fn _mm_maskz_broadcastb_epi8(k: __mmask16, a: __m128i) -> __m128i { unsafe { @@ -8209,7 +8209,7 @@ pub fn _mm_maskz_broadcastb_epi8(k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpackhi_epi16&expand=6012) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhwd))] pub fn _mm512_unpackhi_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8239,7 +8239,7 @@ pub fn _mm512_unpackhi_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpackhi_epi16&expand=6010) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhwd))] pub fn _mm512_mask_unpackhi_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8253,7 +8253,7 @@ pub fn _mm512_mask_unpackhi_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpackhi_epi16&expand=6011) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhwd))] pub fn _mm512_maskz_unpackhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8267,7 +8267,7 @@ pub fn _mm512_maskz_unpackhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpackhi_epi16&expand=6007) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhwd))] pub fn _mm256_mask_unpackhi_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -8281,7 +8281,7 @@ pub fn _mm256_mask_unpackhi_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpackhi_epi16&expand=6008) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhwd))] pub fn _mm256_maskz_unpackhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -8295,7 +8295,7 @@ pub fn _mm256_maskz_unpackhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpackhi_epi16&expand=6004) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhwd))] pub fn _mm_mask_unpackhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -8309,7 +8309,7 @@ pub fn _mm_mask_unpackhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpackhi_epi16&expand=6005) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhwd))] pub fn _mm_maskz_unpackhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -8323,7 +8323,7 @@ pub fn _mm_maskz_unpackhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpackhi_epi8&expand=6039) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhbw))] pub fn _mm512_unpackhi_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8361,7 +8361,7 @@ pub fn _mm512_unpackhi_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpackhi_epi8&expand=6037) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhbw))] pub fn _mm512_mask_unpackhi_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8375,7 +8375,7 @@ pub fn _mm512_mask_unpackhi_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpackhi_epi8&expand=6038) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhbw))] pub fn _mm512_maskz_unpackhi_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8389,7 +8389,7 @@ pub fn _mm512_maskz_unpackhi_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpackhi_epi8&expand=6034) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhbw))] pub fn _mm256_mask_unpackhi_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -8403,7 +8403,7 @@ pub fn _mm256_mask_unpackhi_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpackhi_epi8&expand=6035) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhbw))] pub fn _mm256_maskz_unpackhi_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -8417,7 +8417,7 @@ pub fn _mm256_maskz_unpackhi_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpackhi_epi8&expand=6031) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhbw))] pub fn _mm_mask_unpackhi_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -8431,7 +8431,7 @@ pub fn _mm_mask_unpackhi_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpackhi_epi8&expand=6032) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhbw))] pub fn _mm_maskz_unpackhi_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -8445,7 +8445,7 @@ pub fn _mm_maskz_unpackhi_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpacklo_epi16&expand=6069) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklwd))] pub fn _mm512_unpacklo_epi16(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8475,7 +8475,7 @@ pub fn _mm512_unpacklo_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpacklo_epi16&expand=6067) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklwd))] pub fn _mm512_mask_unpacklo_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8489,7 +8489,7 @@ pub fn _mm512_mask_unpacklo_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpacklo_epi16&expand=6068) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklwd))] pub fn _mm512_maskz_unpacklo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8503,7 +8503,7 @@ pub fn _mm512_maskz_unpacklo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpacklo_epi16&expand=6064) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklwd))] pub fn _mm256_mask_unpacklo_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -8517,7 +8517,7 @@ pub fn _mm256_mask_unpacklo_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpacklo_epi16&expand=6065) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklwd))] pub fn _mm256_maskz_unpacklo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -8531,7 +8531,7 @@ pub fn _mm256_maskz_unpacklo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpacklo_epi16&expand=6061) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklwd))] pub fn _mm_mask_unpacklo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -8545,7 +8545,7 @@ pub fn _mm_mask_unpacklo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpacklo_epi16&expand=6062) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklwd))] pub fn _mm_maskz_unpacklo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -8559,7 +8559,7 @@ pub fn _mm_maskz_unpacklo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpacklo_epi8&expand=6096) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklbw))] pub fn _mm512_unpacklo_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8597,7 +8597,7 @@ pub fn _mm512_unpacklo_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpacklo_epi8&expand=6094) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklbw))] pub fn _mm512_mask_unpacklo_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8611,7 +8611,7 @@ pub fn _mm512_mask_unpacklo_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpacklo_epi8&expand=6095) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklbw))] pub fn _mm512_maskz_unpacklo_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -8625,7 +8625,7 @@ pub fn _mm512_maskz_unpacklo_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpacklo_epi8&expand=6091) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklbw))] pub fn _mm256_mask_unpacklo_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -8639,7 +8639,7 @@ pub fn _mm256_mask_unpacklo_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpacklo_epi8&expand=6092) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklbw))] pub fn _mm256_maskz_unpacklo_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -8653,7 +8653,7 @@ pub fn _mm256_maskz_unpacklo_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpacklo_epi8&expand=6088) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklbw))] pub fn _mm_mask_unpacklo_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -8667,7 +8667,7 @@ pub fn _mm_mask_unpacklo_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpacklo_epi8&expand=6089) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklbw))] pub fn _mm_maskz_unpacklo_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -8681,7 +8681,7 @@ pub fn _mm_maskz_unpacklo_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mov_epi16&expand=3795) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] pub fn _mm512_mask_mov_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { unsafe { @@ -8695,7 +8695,7 @@ pub fn _mm512_mask_mov_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mov_epi16&expand=3796) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] pub fn _mm512_maskz_mov_epi16(k: __mmask32, a: __m512i) -> __m512i { unsafe { @@ -8709,7 +8709,7 @@ pub fn _mm512_maskz_mov_epi16(k: __mmask32, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mov_epi16&expand=3793) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] pub fn _mm256_mask_mov_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i { unsafe { @@ -8723,7 +8723,7 @@ pub fn _mm256_mask_mov_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mov_epi16&expand=3794) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] pub fn _mm256_maskz_mov_epi16(k: __mmask16, a: __m256i) -> __m256i { unsafe { @@ -8737,7 +8737,7 @@ pub fn _mm256_maskz_mov_epi16(k: __mmask16, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mov_epi16&expand=3791) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] pub fn _mm_mask_mov_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -8751,7 +8751,7 @@ pub fn _mm_mask_mov_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mov_epi16&expand=3792) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu16))] pub fn _mm_maskz_mov_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -8765,7 +8765,7 @@ pub fn _mm_maskz_mov_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mov_epi8&expand=3813) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] pub fn _mm512_mask_mov_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i { unsafe { @@ -8779,7 +8779,7 @@ pub fn _mm512_mask_mov_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mov_epi8&expand=3814) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] pub fn _mm512_maskz_mov_epi8(k: __mmask64, a: __m512i) -> __m512i { unsafe { @@ -8793,7 +8793,7 @@ pub fn _mm512_maskz_mov_epi8(k: __mmask64, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mov_epi8&expand=3811) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] pub fn _mm256_mask_mov_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i { unsafe { @@ -8807,7 +8807,7 @@ pub fn _mm256_mask_mov_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mov_epi8&expand=3812) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] pub fn _mm256_maskz_mov_epi8(k: __mmask32, a: __m256i) -> __m256i { unsafe { @@ -8821,7 +8821,7 @@ pub fn _mm256_maskz_mov_epi8(k: __mmask32, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mov_epi8&expand=3809) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] pub fn _mm_mask_mov_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { unsafe { @@ -8835,7 +8835,7 @@ pub fn _mm_mask_mov_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mov_epi8&expand=3810) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqu8))] pub fn _mm_maskz_mov_epi8(k: __mmask16, a: __m128i) -> __m128i { unsafe { @@ -8849,7 +8849,7 @@ pub fn _mm_maskz_mov_epi8(k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_set1_epi16&expand=4942) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm512_mask_set1_epi16(src: __m512i, k: __mmask32, a: i16) -> __m512i { unsafe { @@ -8863,7 +8863,7 @@ pub fn _mm512_mask_set1_epi16(src: __m512i, k: __mmask32, a: i16) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_set1_epi16&expand=4943) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm512_maskz_set1_epi16(k: __mmask32, a: i16) -> __m512i { unsafe { @@ -8877,7 +8877,7 @@ pub fn _mm512_maskz_set1_epi16(k: __mmask32, a: i16) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_set1_epi16&expand=4939) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm256_mask_set1_epi16(src: __m256i, k: __mmask16, a: i16) -> __m256i { unsafe { @@ -8891,7 +8891,7 @@ pub fn _mm256_mask_set1_epi16(src: __m256i, k: __mmask16, a: i16) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_set1_epi16&expand=4940) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm256_maskz_set1_epi16(k: __mmask16, a: i16) -> __m256i { unsafe { @@ -8905,7 +8905,7 @@ pub fn _mm256_maskz_set1_epi16(k: __mmask16, a: i16) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_set1_epi16&expand=4936) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm_mask_set1_epi16(src: __m128i, k: __mmask8, a: i16) -> __m128i { unsafe { @@ -8919,7 +8919,7 @@ pub fn _mm_mask_set1_epi16(src: __m128i, k: __mmask8, a: i16) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_set1_epi16&expand=4937) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastw))] pub fn _mm_maskz_set1_epi16(k: __mmask8, a: i16) -> __m128i { unsafe { @@ -8933,7 +8933,7 @@ pub fn _mm_maskz_set1_epi16(k: __mmask8, a: i16) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_set1_epi8&expand=4970) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] pub fn _mm512_mask_set1_epi8(src: __m512i, k: __mmask64, a: i8) -> __m512i { unsafe { @@ -8947,7 +8947,7 @@ pub fn _mm512_mask_set1_epi8(src: __m512i, k: __mmask64, a: i8) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_set1_epi8&expand=4971) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] pub fn _mm512_maskz_set1_epi8(k: __mmask64, a: i8) -> __m512i { unsafe { @@ -8961,7 +8961,7 @@ pub fn _mm512_maskz_set1_epi8(k: __mmask64, a: i8) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_set1_epi8&expand=4967) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] pub fn _mm256_mask_set1_epi8(src: __m256i, k: __mmask32, a: i8) -> __m256i { unsafe { @@ -8975,7 +8975,7 @@ pub fn _mm256_mask_set1_epi8(src: __m256i, k: __mmask32, a: i8) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_set1_epi8&expand=4968) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] pub fn _mm256_maskz_set1_epi8(k: __mmask32, a: i8) -> __m256i { unsafe { @@ -8989,7 +8989,7 @@ pub fn _mm256_maskz_set1_epi8(k: __mmask32, a: i8) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_set1_epi8&expand=4964) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] pub fn _mm_mask_set1_epi8(src: __m128i, k: __mmask16, a: i8) -> __m128i { unsafe { @@ -9003,7 +9003,7 @@ pub fn _mm_mask_set1_epi8(src: __m128i, k: __mmask16, a: i8) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_set1_epi8&expand=4965) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] pub fn _mm_maskz_set1_epi8(k: __mmask16, a: i8) -> __m128i { unsafe { @@ -9017,7 +9017,7 @@ pub fn _mm_maskz_set1_epi8(k: __mmask16, a: i8) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shufflelo_epi16&expand=5221) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))] #[rustc_legacy_const_generics(1)] pub fn _mm512_shufflelo_epi16(a: __m512i) -> __m512i { @@ -9071,7 +9071,7 @@ pub fn _mm512_shufflelo_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shufflelo_epi16&expand=5219) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_shufflelo_epi16( @@ -9091,7 +9091,7 @@ pub fn _mm512_mask_shufflelo_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shufflelo_epi16&expand=5220) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_shufflelo_epi16(k: __mmask32, a: __m512i) -> __m512i { @@ -9107,7 +9107,7 @@ pub fn _mm512_maskz_shufflelo_epi16(k: __mmask32, a: __m512i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shufflelo_epi16&expand=5216) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_shufflelo_epi16( @@ -9127,7 +9127,7 @@ pub fn _mm256_mask_shufflelo_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shufflelo_epi16&expand=5217) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_shufflelo_epi16(k: __mmask16, a: __m256i) -> __m256i { @@ -9143,7 +9143,7 @@ pub fn _mm256_maskz_shufflelo_epi16(k: __mmask16, a: __m256i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shufflelo_epi16&expand=5213) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_shufflelo_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -9159,7 +9159,7 @@ pub fn _mm_mask_shufflelo_epi16(src: __m128i, k: __mmask8, a: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shufflelo_epi16&expand=5214) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_shufflelo_epi16(k: __mmask8, a: __m128i) -> __m128i { @@ -9175,7 +9175,7 @@ pub fn _mm_maskz_shufflelo_epi16(k: __mmask8, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shufflehi_epi16&expand=5212) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))] #[rustc_legacy_const_generics(1)] pub fn _mm512_shufflehi_epi16(a: __m512i) -> __m512i { @@ -9229,7 +9229,7 @@ pub fn _mm512_shufflehi_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shufflehi_epi16&expand=5210) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_shufflehi_epi16( @@ -9249,7 +9249,7 @@ pub fn _mm512_mask_shufflehi_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shufflehi_epi16&expand=5211) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_shufflehi_epi16(k: __mmask32, a: __m512i) -> __m512i { @@ -9265,7 +9265,7 @@ pub fn _mm512_maskz_shufflehi_epi16(k: __mmask32, a: __m512i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shufflehi_epi16&expand=5207) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_shufflehi_epi16( @@ -9285,7 +9285,7 @@ pub fn _mm256_mask_shufflehi_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shufflehi_epi16&expand=5208) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_shufflehi_epi16(k: __mmask16, a: __m256i) -> __m256i { @@ -9301,7 +9301,7 @@ pub fn _mm256_maskz_shufflehi_epi16(k: __mmask16, a: __m256i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shufflehi_epi16&expand=5204) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_shufflehi_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -9317,7 +9317,7 @@ pub fn _mm_mask_shufflehi_epi16(src: __m128i, k: __mmask8, a: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shufflehi_epi16&expand=5205) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_shufflehi_epi16(k: __mmask8, a: __m128i) -> __m128i { @@ -9333,7 +9333,7 @@ pub fn _mm_maskz_shufflehi_epi16(k: __mmask8, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_epi8&expand=5159) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufb))] pub fn _mm512_shuffle_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpshufb(a.as_i8x64(), b.as_i8x64())) } @@ -9344,7 +9344,7 @@ pub fn _mm512_shuffle_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_epi8&expand=5157) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufb))] pub fn _mm512_mask_shuffle_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -9358,7 +9358,7 @@ pub fn _mm512_mask_shuffle_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_epi8&expand=5158) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufb))] pub fn _mm512_maskz_shuffle_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -9372,7 +9372,7 @@ pub fn _mm512_maskz_shuffle_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_epi8&expand=5154) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufb))] pub fn _mm256_mask_shuffle_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -9386,7 +9386,7 @@ pub fn _mm256_mask_shuffle_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_epi8&expand=5155) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufb))] pub fn _mm256_maskz_shuffle_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -9400,7 +9400,7 @@ pub fn _mm256_maskz_shuffle_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shuffle_epi8&expand=5151) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufb))] pub fn _mm_mask_shuffle_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -9414,7 +9414,7 @@ pub fn _mm_mask_shuffle_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shuffle_epi8&expand=5152) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufb))] pub fn _mm_maskz_shuffle_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -9428,7 +9428,7 @@ pub fn _mm_maskz_shuffle_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_test_epi16_mask&expand=5884) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmw))] pub fn _mm512_test_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { let and = _mm512_and_si512(a, b); @@ -9441,7 +9441,7 @@ pub fn _mm512_test_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_test_epi16_mask&expand=5883) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmw))] pub fn _mm512_mask_test_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { let and = _mm512_and_si512(a, b); @@ -9454,7 +9454,7 @@ pub fn _mm512_mask_test_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_test_epi16_mask&expand=5882) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmw))] pub fn _mm256_test_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { let and = _mm256_and_si256(a, b); @@ -9467,7 +9467,7 @@ pub fn _mm256_test_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_test_epi16_mask&expand=5881) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmw))] pub fn _mm256_mask_test_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { let and = _mm256_and_si256(a, b); @@ -9480,7 +9480,7 @@ pub fn _mm256_mask_test_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_test_epi16_mask&expand=5880) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmw))] pub fn _mm_test_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -9493,7 +9493,7 @@ pub fn _mm_test_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_test_epi16_mask&expand=5879) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmw))] pub fn _mm_mask_test_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -9506,7 +9506,7 @@ pub fn _mm_mask_test_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_test_epi8_mask&expand=5902) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmb))] pub fn _mm512_test_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { let and = _mm512_and_si512(a, b); @@ -9519,7 +9519,7 @@ pub fn _mm512_test_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_test_epi8_mask&expand=5901) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmb))] pub fn _mm512_mask_test_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { let and = _mm512_and_si512(a, b); @@ -9532,7 +9532,7 @@ pub fn _mm512_mask_test_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_test_epi8_mask&expand=5900) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmb))] pub fn _mm256_test_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { let and = _mm256_and_si256(a, b); @@ -9545,7 +9545,7 @@ pub fn _mm256_test_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_test_epi8_mask&expand=5899) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmb))] pub fn _mm256_mask_test_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { let and = _mm256_and_si256(a, b); @@ -9558,7 +9558,7 @@ pub fn _mm256_mask_test_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_test_epi8_mask&expand=5898) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmb))] pub fn _mm_test_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { let and = _mm_and_si128(a, b); @@ -9571,7 +9571,7 @@ pub fn _mm_test_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_test_epi8_mask&expand=5897) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmb))] pub fn _mm_mask_test_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { let and = _mm_and_si128(a, b); @@ -9584,7 +9584,7 @@ pub fn _mm_mask_test_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_testn_epi16_mask&expand=5915) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmw))] pub fn _mm512_testn_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { let and = _mm512_and_si512(a, b); @@ -9597,7 +9597,7 @@ pub fn _mm512_testn_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_testn_epi16_mask&expand=5914) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmw))] pub fn _mm512_mask_testn_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mmask32 { let and = _mm512_and_si512(a, b); @@ -9610,7 +9610,7 @@ pub fn _mm512_mask_testn_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testn_epi16_mask&expand=5913) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmw))] pub fn _mm256_testn_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { let and = _mm256_and_si256(a, b); @@ -9623,7 +9623,7 @@ pub fn _mm256_testn_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_testn_epi16_mask&expand=5912) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmw))] pub fn _mm256_mask_testn_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mmask16 { let and = _mm256_and_si256(a, b); @@ -9636,7 +9636,7 @@ pub fn _mm256_mask_testn_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_testn_epi16_mask&expand=5911) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmw))] pub fn _mm_testn_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -9649,7 +9649,7 @@ pub fn _mm_testn_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_testn_epi16_mask&expand=5910) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmw))] pub fn _mm_mask_testn_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -9662,7 +9662,7 @@ pub fn _mm_mask_testn_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_testn_epi8_mask&expand=5933) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmb))] pub fn _mm512_testn_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { let and = _mm512_and_si512(a, b); @@ -9675,7 +9675,7 @@ pub fn _mm512_testn_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_testn_epi8_mask&expand=5932) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmb))] pub fn _mm512_mask_testn_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mmask64 { let and = _mm512_and_si512(a, b); @@ -9688,7 +9688,7 @@ pub fn _mm512_mask_testn_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testn_epi8_mask&expand=5931) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmb))] pub fn _mm256_testn_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { let and = _mm256_and_si256(a, b); @@ -9701,7 +9701,7 @@ pub fn _mm256_testn_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_testn_epi8_mask&expand=5930) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmb))] pub fn _mm256_mask_testn_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mmask32 { let and = _mm256_and_si256(a, b); @@ -9714,7 +9714,7 @@ pub fn _mm256_mask_testn_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_testn_epi8_mask&expand=5929) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmb))] pub fn _mm_testn_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { let and = _mm_and_si128(a, b); @@ -9727,7 +9727,7 @@ pub fn _mm_testn_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_testn_epi8_mask&expand=5928) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmb))] pub fn _mm_mask_testn_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask16 { let and = _mm_and_si128(a, b); @@ -9740,7 +9740,7 @@ pub fn _mm_mask_testn_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_store_mask64&expand=5578) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] //should be kmovq pub unsafe fn _store_mask64(mem_addr: *mut __mmask64, a: __mmask64) { ptr::write(mem_addr as *mut __mmask64, a); @@ -9751,7 +9751,7 @@ pub unsafe fn _store_mask64(mem_addr: *mut __mmask64, a: __mmask64) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_store_mask32&expand=5577) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] //should be kmovd pub unsafe fn _store_mask32(mem_addr: *mut __mmask32, a: __mmask32) { ptr::write(mem_addr as *mut __mmask32, a); @@ -9762,7 +9762,7 @@ pub unsafe fn _store_mask32(mem_addr: *mut __mmask32, a: __mmask32) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_load_mask64&expand=3318) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] //should be kmovq pub unsafe fn _load_mask64(mem_addr: *const __mmask64) -> __mmask64 { ptr::read(mem_addr as *const __mmask64) @@ -9773,7 +9773,7 @@ pub unsafe fn _load_mask64(mem_addr: *const __mmask64) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_load_mask32&expand=3317) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] //should be kmovd pub unsafe fn _load_mask32(mem_addr: *const __mmask32) -> __mmask32 { ptr::read(mem_addr as *const __mmask32) @@ -9784,7 +9784,7 @@ pub unsafe fn _load_mask32(mem_addr: *const __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sad_epu8&expand=4855) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsadbw))] pub fn _mm512_sad_epu8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpsadbw(a.as_u8x64(), b.as_u8x64())) } @@ -9795,7 +9795,7 @@ pub fn _mm512_sad_epu8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_dbsad_epu8&expand=2114) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm512_dbsad_epu8(a: __m512i, b: __m512i) -> __m512i { @@ -9813,7 +9813,7 @@ pub fn _mm512_dbsad_epu8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_dbsad_epu8&expand=2115) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(4)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm512_mask_dbsad_epu8( @@ -9836,7 +9836,7 @@ pub fn _mm512_mask_dbsad_epu8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_dbsad_epu8&expand=2116) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm512_maskz_dbsad_epu8(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { @@ -9854,7 +9854,7 @@ pub fn _mm512_maskz_dbsad_epu8(k: __mmask32, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dbsad_epu8&expand=2111) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm256_dbsad_epu8(a: __m256i, b: __m256i) -> __m256i { @@ -9872,7 +9872,7 @@ pub fn _mm256_dbsad_epu8(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_dbsad_epu8&expand=2112) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(4)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm256_mask_dbsad_epu8( @@ -9895,7 +9895,7 @@ pub fn _mm256_mask_dbsad_epu8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_dbsad_epu8&expand=2113) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm256_maskz_dbsad_epu8(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { @@ -9913,7 +9913,7 @@ pub fn _mm256_maskz_dbsad_epu8(k: __mmask16, a: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dbsad_epu8&expand=2108) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm_dbsad_epu8(a: __m128i, b: __m128i) -> __m128i { @@ -9931,7 +9931,7 @@ pub fn _mm_dbsad_epu8(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_dbsad_epu8&expand=2109) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(4)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm_mask_dbsad_epu8( @@ -9954,7 +9954,7 @@ pub fn _mm_mask_dbsad_epu8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_dbsad_epu8&expand=2110) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] pub fn _mm_maskz_dbsad_epu8(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { @@ -9972,7 +9972,7 @@ pub fn _mm_maskz_dbsad_epu8(k: __mmask8, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movepi16_mask&expand=3873) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovw2m))] pub fn _mm512_movepi16_mask(a: __m512i) -> __mmask32 { let filter = _mm512_set1_epi16(1 << 15); @@ -9985,7 +9985,7 @@ pub fn _mm512_movepi16_mask(a: __m512i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movepi16_mask&expand=3872) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovw2m))] pub fn _mm256_movepi16_mask(a: __m256i) -> __mmask16 { let filter = _mm256_set1_epi16(1 << 15); @@ -9998,7 +9998,7 @@ pub fn _mm256_movepi16_mask(a: __m256i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movepi16_mask&expand=3871) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovw2m))] pub fn _mm_movepi16_mask(a: __m128i) -> __mmask8 { let filter = _mm_set1_epi16(1 << 15); @@ -10011,7 +10011,7 @@ pub fn _mm_movepi16_mask(a: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movepi8_mask&expand=3883) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovb2m))] pub fn _mm512_movepi8_mask(a: __m512i) -> __mmask64 { let filter = _mm512_set1_epi8(1 << 7); @@ -10024,7 +10024,7 @@ pub fn _mm512_movepi8_mask(a: __m512i) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movepi8_mask&expand=3882) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovmskb))] // should be vpmovb2m but compiled to vpmovmskb in the test shim because that takes less cycles than // using vpmovb2m plus converting the mask register to a standard register. pub fn _mm256_movepi8_mask(a: __m256i) -> __mmask32 { @@ -10038,7 +10038,7 @@ pub fn _mm256_movepi8_mask(a: __m256i) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movepi8_mask&expand=3881) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovmskb))] // should be vpmovb2m but compiled to vpmovmskb in the test shim because that takes less cycles than // using vpmovb2m plus converting the mask register to a standard register. pub fn _mm_movepi8_mask(a: __m128i) -> __mmask16 { @@ -10052,7 +10052,7 @@ pub fn _mm_movepi8_mask(a: __m128i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movm_epi16&expand=3886) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovm2w))] pub fn _mm512_movm_epi16(k: __mmask32) -> __m512i { unsafe { @@ -10084,7 +10084,7 @@ pub fn _mm512_movm_epi16(k: __mmask32) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movm_epi16&expand=3885) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovm2w))] pub fn _mm256_movm_epi16(k: __mmask16) -> __m256i { unsafe { @@ -10116,7 +10116,7 @@ pub fn _mm256_movm_epi16(k: __mmask16) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movm_epi16&expand=3884) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovm2w))] pub fn _mm_movm_epi16(k: __mmask8) -> __m128i { unsafe { @@ -10148,7 +10148,7 @@ pub fn _mm_movm_epi16(k: __mmask8) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movm_epi8&expand=3895) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovm2b))] pub fn _mm512_movm_epi8(k: __mmask64) -> __m512i { unsafe { @@ -10164,7 +10164,7 @@ pub fn _mm512_movm_epi8(k: __mmask64) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movm_epi8&expand=3894) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovm2b))] pub fn _mm256_movm_epi8(k: __mmask32) -> __m256i { unsafe { @@ -10180,7 +10180,7 @@ pub fn _mm256_movm_epi8(k: __mmask32) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movm_epi8&expand=3893) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovm2b))] pub fn _mm_movm_epi8(k: __mmask16) -> __m128i { unsafe { @@ -10196,7 +10196,7 @@ pub fn _mm_movm_epi8(k: __mmask16) -> __m128i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#_cvtmask32_u32) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _cvtmask32_u32(a: __mmask32) -> u32 { a } @@ -10206,7 +10206,7 @@ pub fn _cvtmask32_u32(a: __mmask32) -> u32 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtu32_mask32) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _cvtu32_mask32(a: u32) -> __mmask32 { a } @@ -10216,7 +10216,7 @@ pub fn _cvtu32_mask32(a: u32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kadd_mask32&expand=3207) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kadd_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { a + b } @@ -10226,7 +10226,7 @@ pub fn _kadd_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kadd_mask64&expand=3208) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kadd_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { a + b } @@ -10236,7 +10236,7 @@ pub fn _kadd_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kand_mask32&expand=3213) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kand_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { a & b } @@ -10246,7 +10246,7 @@ pub fn _kand_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kand_mask64&expand=3214) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kand_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { a & b } @@ -10256,7 +10256,7 @@ pub fn _kand_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_knot_mask32&expand=3234) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _knot_mask32(a: __mmask32) -> __mmask32 { !a } @@ -10266,7 +10266,7 @@ pub fn _knot_mask32(a: __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_knot_mask64&expand=3235) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _knot_mask64(a: __mmask64) -> __mmask64 { !a } @@ -10276,7 +10276,7 @@ pub fn _knot_mask64(a: __mmask64) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kandn_mask32&expand=3219) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kandn_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { _knot_mask32(a) & b } @@ -10286,7 +10286,7 @@ pub fn _kandn_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kandn_mask64&expand=3220) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kandn_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { _knot_mask64(a) & b } @@ -10296,7 +10296,7 @@ pub fn _kandn_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kor_mask32&expand=3240) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { a | b } @@ -10306,7 +10306,7 @@ pub fn _kor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kor_mask64&expand=3241) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { a | b } @@ -10316,7 +10316,7 @@ pub fn _kor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxor_mask32&expand=3292) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kxor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { a ^ b } @@ -10326,7 +10326,7 @@ pub fn _kxor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxor_mask64&expand=3293) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kxor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { a ^ b } @@ -10336,7 +10336,7 @@ pub fn _kxor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxnor_mask32&expand=3286) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kxnor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { _knot_mask32(a ^ b) } @@ -10346,7 +10346,7 @@ pub fn _kxnor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxnor_mask64&expand=3287) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kxnor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { _knot_mask64(a ^ b) } @@ -10357,7 +10357,7 @@ pub fn _kxnor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortest_mask32_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _kortest_mask32_u8(a: __mmask32, b: __mmask32, all_ones: *mut u8) -> u8 { let tmp = _kor_mask32(a, b); *all_ones = (tmp == 0xffffffff) as u8; @@ -10370,7 +10370,7 @@ pub unsafe fn _kortest_mask32_u8(a: __mmask32, b: __mmask32, all_ones: *mut u8) /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortest_mask64_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _kortest_mask64_u8(a: __mmask64, b: __mmask64, all_ones: *mut u8) -> u8 { let tmp = _kor_mask64(a, b); *all_ones = (tmp == 0xffffffff_ffffffff) as u8; @@ -10383,7 +10383,7 @@ pub unsafe fn _kortest_mask64_u8(a: __mmask64, b: __mmask64, all_ones: *mut u8) /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortestc_mask32_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kortestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 { (_kor_mask32(a, b) == 0xffffffff) as u8 } @@ -10394,7 +10394,7 @@ pub fn _kortestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortestc_mask64_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kortestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 { (_kor_mask64(a, b) == 0xffffffff_ffffffff) as u8 } @@ -10405,7 +10405,7 @@ pub fn _kortestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortestz_mask32_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kortestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 { (_kor_mask32(a, b) == 0) as u8 } @@ -10416,7 +10416,7 @@ pub fn _kortestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortestz_mask64_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kortestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 { (_kor_mask64(a, b) == 0) as u8 } @@ -10427,7 +10427,7 @@ pub fn _kortestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 { #[inline] #[target_feature(enable = "avx512bw")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kshiftli_mask32(a: __mmask32) -> __mmask32 { a << COUNT } @@ -10438,7 +10438,7 @@ pub fn _kshiftli_mask32(a: __mmask32) -> __mmask32 { #[inline] #[target_feature(enable = "avx512bw")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kshiftli_mask64(a: __mmask64) -> __mmask64 { a << COUNT } @@ -10449,7 +10449,7 @@ pub fn _kshiftli_mask64(a: __mmask64) -> __mmask64 { #[inline] #[target_feature(enable = "avx512bw")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kshiftri_mask32(a: __mmask32) -> __mmask32 { a >> COUNT } @@ -10460,7 +10460,7 @@ pub fn _kshiftri_mask32(a: __mmask32) -> __mmask32 { #[inline] #[target_feature(enable = "avx512bw")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kshiftri_mask64(a: __mmask64) -> __mmask64 { a >> COUNT } @@ -10472,7 +10472,7 @@ pub fn _kshiftri_mask64(a: __mmask64) -> __mmask64 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktest_mask32_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _ktest_mask32_u8(a: __mmask32, b: __mmask32, and_not: *mut u8) -> u8 { *and_not = (_kandn_mask32(a, b) == 0) as u8; (_kand_mask32(a, b) == 0) as u8 @@ -10485,7 +10485,7 @@ pub unsafe fn _ktest_mask32_u8(a: __mmask32, b: __mmask32, and_not: *mut u8) -> /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktest_mask64_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _ktest_mask64_u8(a: __mmask64, b: __mmask64, and_not: *mut u8) -> u8 { *and_not = (_kandn_mask64(a, b) == 0) as u8; (_kand_mask64(a, b) == 0) as u8 @@ -10497,7 +10497,7 @@ pub unsafe fn _ktest_mask64_u8(a: __mmask64, b: __mmask64, and_not: *mut u8) -> /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktestc_mask32_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _ktestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 { (_kandn_mask32(a, b) == 0) as u8 } @@ -10508,7 +10508,7 @@ pub fn _ktestc_mask32_u8(a: __mmask32, b: __mmask32) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktestc_mask64_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _ktestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 { (_kandn_mask64(a, b) == 0) as u8 } @@ -10519,7 +10519,7 @@ pub fn _ktestc_mask64_u8(a: __mmask64, b: __mmask64) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktestz_mask32_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _ktestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 { (_kand_mask32(a, b) == 0) as u8 } @@ -10530,7 +10530,7 @@ pub fn _ktestz_mask32_u8(a: __mmask32, b: __mmask32) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktestz_mask64_u8) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _ktestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 { (_kand_mask64(a, b) == 0) as u8 } @@ -10540,7 +10540,7 @@ pub fn _ktestz_mask64_u8(a: __mmask64, b: __mmask64) -> u8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kunpackw) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kunpckwd pub fn _mm512_kunpackw(a: __mmask32, b: __mmask32) -> __mmask32 { ((a & 0xffff) << 16) | (b & 0xffff) @@ -10551,7 +10551,7 @@ pub fn _mm512_kunpackw(a: __mmask32, b: __mmask32) -> __mmask32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kunpackd) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kunpckdq pub fn _mm512_kunpackd(a: __mmask64, b: __mmask64) -> __mmask64 { ((a & 0xffffffff) << 32) | (b & 0xffffffff) @@ -10562,7 +10562,7 @@ pub fn _mm512_kunpackd(a: __mmask64, b: __mmask64) -> __mmask64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi16_epi8&expand=1407) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm512_cvtepi16_epi8(a: __m512i) -> __m256i { unsafe { @@ -10576,7 +10576,7 @@ pub fn _mm512_cvtepi16_epi8(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi16_epi8&expand=1408) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm512_mask_cvtepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i { unsafe { @@ -10590,7 +10590,7 @@ pub fn _mm512_mask_cvtepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi16_epi8&expand=1409) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm512_maskz_cvtepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { unsafe { @@ -10604,7 +10604,7 @@ pub fn _mm512_maskz_cvtepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtepi16_epi8&expand=1404) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm256_cvtepi16_epi8(a: __m256i) -> __m128i { unsafe { @@ -10618,7 +10618,7 @@ pub fn _mm256_cvtepi16_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi16_epi8&expand=1405) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm256_mask_cvtepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i { unsafe { @@ -10632,7 +10632,7 @@ pub fn _mm256_mask_cvtepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi16_epi8&expand=1406) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm256_maskz_cvtepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { unsafe { @@ -10646,7 +10646,7 @@ pub fn _mm256_maskz_cvtepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi16_epi8&expand=1401) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm_cvtepi16_epi8(a: __m128i) -> __m128i { unsafe { @@ -10665,7 +10665,7 @@ pub fn _mm_cvtepi16_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi16_epi8&expand=1402) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm_mask_cvtepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -10680,7 +10680,7 @@ pub fn _mm_mask_cvtepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi16_epi8&expand=1403) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -10695,7 +10695,7 @@ pub fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsepi16_epi8&expand=1807) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i { unsafe { @@ -10712,7 +10712,7 @@ pub fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi16_epi8&expand=1808) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i { unsafe { transmute(vpmovswb(a.as_i16x32(), src.as_i8x32(), k)) } @@ -10723,7 +10723,7 @@ pub fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtsepi16_epi8&expand=1809) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { unsafe { transmute(vpmovswb(a.as_i16x32(), i8x32::ZERO, k)) } @@ -10734,7 +10734,7 @@ pub fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsepi16_epi8&expand=1804) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i { unsafe { transmute(vpmovswb256(a.as_i16x16(), i8x16::ZERO, 0b11111111_11111111)) } @@ -10745,7 +10745,7 @@ pub fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi16_epi8&expand=1805) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i { unsafe { transmute(vpmovswb256(a.as_i16x16(), src.as_i8x16(), k)) } @@ -10756,7 +10756,7 @@ pub fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtsepi16_epi8&expand=1806) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { unsafe { transmute(vpmovswb256(a.as_i16x16(), i8x16::ZERO, k)) } @@ -10767,7 +10767,7 @@ pub fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsepi16_epi8&expand=1801) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm_cvtsepi16_epi8(a: __m128i) -> __m128i { unsafe { transmute(vpmovswb128(a.as_i16x8(), i8x16::ZERO, 0b11111111)) } @@ -10778,7 +10778,7 @@ pub fn _mm_cvtsepi16_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi16_epi8&expand=1802) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm_mask_cvtsepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovswb128(a.as_i16x8(), src.as_i8x16(), k)) } @@ -10789,7 +10789,7 @@ pub fn _mm_mask_cvtsepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtsepi16_epi8&expand=1803) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub fn _mm_maskz_cvtsepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovswb128(a.as_i16x8(), i8x16::ZERO, k)) } @@ -10800,7 +10800,7 @@ pub fn _mm_maskz_cvtsepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtusepi16_epi8&expand=2042) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i { unsafe { @@ -10817,7 +10817,7 @@ pub fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi16_epi8&expand=2043) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i { unsafe { transmute(vpmovuswb(a.as_u16x32(), src.as_u8x32(), k)) } @@ -10828,7 +10828,7 @@ pub fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtusepi16_epi8&expand=2044) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { unsafe { transmute(vpmovuswb(a.as_u16x32(), u8x32::ZERO, k)) } @@ -10839,7 +10839,7 @@ pub fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtusepi16_epi8&expand=2039) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i { unsafe { @@ -10856,7 +10856,7 @@ pub fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi16_epi8&expand=2040) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i { unsafe { transmute(vpmovuswb256(a.as_u16x16(), src.as_u8x16(), k)) } @@ -10867,7 +10867,7 @@ pub fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtusepi16_epi8&expand=2041) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { unsafe { transmute(vpmovuswb256(a.as_u16x16(), u8x16::ZERO, k)) } @@ -10878,7 +10878,7 @@ pub fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtusepi16_epi8&expand=2036) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm_cvtusepi16_epi8(a: __m128i) -> __m128i { unsafe { transmute(vpmovuswb128(a.as_u16x8(), u8x16::ZERO, 0b11111111)) } @@ -10889,7 +10889,7 @@ pub fn _mm_cvtusepi16_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi16_epi8&expand=2037) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm_mask_cvtusepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovuswb128(a.as_u16x8(), src.as_u8x16(), k)) } @@ -10900,7 +10900,7 @@ pub fn _mm_mask_cvtusepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtusepi16_epi8&expand=2038) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub fn _mm_maskz_cvtusepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovuswb128(a.as_u16x8(), u8x16::ZERO, k)) } @@ -10911,7 +10911,7 @@ pub fn _mm_maskz_cvtusepi16_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi8_epi16&expand=1526) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbw))] pub fn _mm512_cvtepi8_epi16(a: __m256i) -> __m512i { unsafe { @@ -10925,7 +10925,7 @@ pub fn _mm512_cvtepi8_epi16(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi8_epi16&expand=1527) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbw))] pub fn _mm512_mask_cvtepi8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m512i { unsafe { @@ -10939,7 +10939,7 @@ pub fn _mm512_mask_cvtepi8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi8_epi16&expand=1528) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbw))] pub fn _mm512_maskz_cvtepi8_epi16(k: __mmask32, a: __m256i) -> __m512i { unsafe { @@ -10953,7 +10953,7 @@ pub fn _mm512_maskz_cvtepi8_epi16(k: __mmask32, a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi8_epi16&expand=1524) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbw))] pub fn _mm256_mask_cvtepi8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i { unsafe { @@ -10967,7 +10967,7 @@ pub fn _mm256_mask_cvtepi8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi8_epi16&expand=1525) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbw))] pub fn _mm256_maskz_cvtepi8_epi16(k: __mmask16, a: __m128i) -> __m256i { unsafe { @@ -10981,7 +10981,7 @@ pub fn _mm256_maskz_cvtepi8_epi16(k: __mmask16, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi8_epi16&expand=1521) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbw))] pub fn _mm_mask_cvtepi8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -10995,7 +10995,7 @@ pub fn _mm_mask_cvtepi8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi8_epi16&expand=1522) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbw))] pub fn _mm_maskz_cvtepi8_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11009,7 +11009,7 @@ pub fn _mm_maskz_cvtepi8_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu8_epi16&expand=1612) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbw))] pub fn _mm512_cvtepu8_epi16(a: __m256i) -> __m512i { unsafe { @@ -11023,7 +11023,7 @@ pub fn _mm512_cvtepu8_epi16(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu8_epi16&expand=1613) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbw))] pub fn _mm512_mask_cvtepu8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m512i { unsafe { @@ -11037,7 +11037,7 @@ pub fn _mm512_mask_cvtepu8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu8_epi16&expand=1614) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbw))] pub fn _mm512_maskz_cvtepu8_epi16(k: __mmask32, a: __m256i) -> __m512i { unsafe { @@ -11051,7 +11051,7 @@ pub fn _mm512_maskz_cvtepu8_epi16(k: __mmask32, a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepu8_epi16&expand=1610) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbw))] pub fn _mm256_mask_cvtepu8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i { unsafe { @@ -11065,7 +11065,7 @@ pub fn _mm256_mask_cvtepu8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepu8_epi16&expand=1611) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbw))] pub fn _mm256_maskz_cvtepu8_epi16(k: __mmask16, a: __m128i) -> __m256i { unsafe { @@ -11079,7 +11079,7 @@ pub fn _mm256_maskz_cvtepu8_epi16(k: __mmask16, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepu8_epi16&expand=1607) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbw))] pub fn _mm_mask_cvtepu8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11093,7 +11093,7 @@ pub fn _mm_mask_cvtepu8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepu8_epi16&expand=1608) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbw))] pub fn _mm_maskz_cvtepu8_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11107,7 +11107,7 @@ pub fn _mm_maskz_cvtepu8_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_bslli_epi128&expand=591) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslldq, IMM8 = 3))] #[rustc_legacy_const_generics(1)] pub fn _mm512_bslli_epi128(a: __m512i) -> __m512i { @@ -11202,7 +11202,7 @@ pub fn _mm512_bslli_epi128(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_bsrli_epi128&expand=594) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrldq, IMM8 = 3))] #[rustc_legacy_const_generics(1)] pub fn _mm512_bsrli_epi128(a: __m512i) -> __m512i { @@ -11416,7 +11416,7 @@ pub fn _mm512_bsrli_epi128(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_alignr_epi8&expand=263) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_alignr_epi8(a: __m512i, b: __m512i) -> __m512i { @@ -11642,7 +11642,7 @@ pub fn _mm512_alignr_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_alignr_epi8&expand=264) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_alignr_epi8( @@ -11663,7 +11663,7 @@ pub fn _mm512_mask_alignr_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_alignr_epi8&expand=265) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_alignr_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { @@ -11679,7 +11679,7 @@ pub fn _mm512_maskz_alignr_epi8(k: __mmask64, a: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_alignr_epi8&expand=261) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(4)] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))] pub fn _mm256_mask_alignr_epi8( @@ -11700,7 +11700,7 @@ pub fn _mm256_mask_alignr_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_alignr_epi8&expand=262) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))] pub fn _mm256_maskz_alignr_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { @@ -11716,7 +11716,7 @@ pub fn _mm256_maskz_alignr_epi8(k: __mmask32, a: __m256i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_alignr_epi8&expand=258) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(4)] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))] pub fn _mm_mask_alignr_epi8( @@ -11737,7 +11737,7 @@ pub fn _mm_mask_alignr_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_alignr_epi8&expand=259) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))] pub fn _mm_maskz_alignr_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { @@ -11753,7 +11753,7 @@ pub fn _mm_maskz_alignr_epi8(k: __mmask16, a: __m128i, b: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi16_storeu_epi8&expand=1812) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm512_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) { vpmovswbmem(mem_addr, a.as_i16x32(), k); @@ -11764,7 +11764,7 @@ pub unsafe fn _mm512_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi16_storeu_epi8&expand=1811) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { vpmovswbmem256(mem_addr, a.as_i16x16(), k); @@ -11775,7 +11775,7 @@ pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi16_storeu_epi8&expand=1810) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovswbmem128(mem_addr, a.as_i16x8(), k); @@ -11786,7 +11786,7 @@ pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi16_storeu_epi8&expand=1412) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) { vpmovwbmem(mem_addr, a.as_i16x32(), k); @@ -11797,7 +11797,7 @@ pub unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi16_storeu_epi8&expand=1411) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { vpmovwbmem256(mem_addr, a.as_i16x16(), k); @@ -11808,7 +11808,7 @@ pub unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi16_storeu_epi8&expand=1410) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovwb))] pub unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovwbmem128(mem_addr, a.as_i16x8(), k); @@ -11819,7 +11819,7 @@ pub unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi16_storeu_epi8&expand=2047) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm512_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) { vpmovuswbmem(mem_addr, a.as_i16x32(), k); @@ -11830,7 +11830,7 @@ pub unsafe fn _mm512_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi16_storeu_epi8&expand=2046) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { vpmovuswbmem256(mem_addr, a.as_i16x16(), k); @@ -11841,7 +11841,7 @@ pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi16_storeu_epi8&expand=2045) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovuswbmem128(mem_addr, a.as_i16x8(), k); diff --git a/crates/core_arch/src/x86/avx512cd.rs b/crates/core_arch/src/x86/avx512cd.rs index 3982c55fa6..78735fcc90 100644 --- a/crates/core_arch/src/x86/avx512cd.rs +++ b/crates/core_arch/src/x86/avx512cd.rs @@ -9,7 +9,7 @@ use stdarch_test::assert_instr; /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastmw_epi32&expand=553) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d pub fn _mm512_broadcastmw_epi32(k: __mmask16) -> __m512i { _mm512_set1_epi32(k as i32) @@ -20,7 +20,7 @@ pub fn _mm512_broadcastmw_epi32(k: __mmask16) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcastmw_epi32&expand=552) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d pub fn _mm256_broadcastmw_epi32(k: __mmask16) -> __m256i { _mm256_set1_epi32(k as i32) @@ -31,7 +31,7 @@ pub fn _mm256_broadcastmw_epi32(k: __mmask16) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcastmw_epi32&expand=551) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmw2d pub fn _mm_broadcastmw_epi32(k: __mmask16) -> __m128i { _mm_set1_epi32(k as i32) @@ -42,7 +42,7 @@ pub fn _mm_broadcastmw_epi32(k: __mmask16) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastmb_epi64&expand=550) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q pub fn _mm512_broadcastmb_epi64(k: __mmask8) -> __m512i { _mm512_set1_epi64(k as i64) @@ -53,7 +53,7 @@ pub fn _mm512_broadcastmb_epi64(k: __mmask8) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcastmb_epi64&expand=549) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q pub fn _mm256_broadcastmb_epi64(k: __mmask8) -> __m256i { _mm256_set1_epi64x(k as i64) @@ -64,7 +64,7 @@ pub fn _mm256_broadcastmb_epi64(k: __mmask8) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcastmb_epi64&expand=548) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] // should be vpbroadcastmb2q pub fn _mm_broadcastmb_epi64(k: __mmask8) -> __m128i { _mm_set1_epi64x(k as i64) @@ -75,7 +75,7 @@ pub fn _mm_broadcastmb_epi64(k: __mmask8) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_conflict_epi32&expand=1248) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm512_conflict_epi32(a: __m512i) -> __m512i { unsafe { transmute(vpconflictd(a.as_i32x16())) } @@ -86,7 +86,7 @@ pub fn _mm512_conflict_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_conflict_epi32&expand=1249) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm512_mask_conflict_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -100,7 +100,7 @@ pub fn _mm512_mask_conflict_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_conflict_epi32&expand=1250) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm512_maskz_conflict_epi32(k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -114,7 +114,7 @@ pub fn _mm512_maskz_conflict_epi32(k: __mmask16, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_conflict_epi32&expand=1245) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm256_conflict_epi32(a: __m256i) -> __m256i { unsafe { transmute(vpconflictd256(a.as_i32x8())) } @@ -125,7 +125,7 @@ pub fn _mm256_conflict_epi32(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_conflict_epi32&expand=1246) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm256_mask_conflict_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -139,7 +139,7 @@ pub fn _mm256_mask_conflict_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_conflict_epi32&expand=1247) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm256_maskz_conflict_epi32(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -153,7 +153,7 @@ pub fn _mm256_maskz_conflict_epi32(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_conflict_epi32&expand=1242) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm_conflict_epi32(a: __m128i) -> __m128i { unsafe { transmute(vpconflictd128(a.as_i32x4())) } @@ -164,7 +164,7 @@ pub fn _mm_conflict_epi32(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_conflict_epi32&expand=1243) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm_mask_conflict_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -178,7 +178,7 @@ pub fn _mm_mask_conflict_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_conflict_epi32&expand=1244) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictd))] pub fn _mm_maskz_conflict_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -192,7 +192,7 @@ pub fn _mm_maskz_conflict_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_conflict_epi64&expand=1257) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm512_conflict_epi64(a: __m512i) -> __m512i { unsafe { transmute(vpconflictq(a.as_i64x8())) } @@ -203,7 +203,7 @@ pub fn _mm512_conflict_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_conflict_epi64&expand=1258) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm512_mask_conflict_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -217,7 +217,7 @@ pub fn _mm512_mask_conflict_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_conflict_epi64&expand=1259) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm512_maskz_conflict_epi64(k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -231,7 +231,7 @@ pub fn _mm512_maskz_conflict_epi64(k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_conflict_epi64&expand=1254) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm256_conflict_epi64(a: __m256i) -> __m256i { unsafe { transmute(vpconflictq256(a.as_i64x4())) } @@ -242,7 +242,7 @@ pub fn _mm256_conflict_epi64(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_conflict_epi64&expand=1255) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm256_mask_conflict_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -256,7 +256,7 @@ pub fn _mm256_mask_conflict_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_conflict_epi64&expand=1256) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm256_maskz_conflict_epi64(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -270,7 +270,7 @@ pub fn _mm256_maskz_conflict_epi64(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_conflict_epi64&expand=1251) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm_conflict_epi64(a: __m128i) -> __m128i { unsafe { transmute(vpconflictq128(a.as_i64x2())) } @@ -281,7 +281,7 @@ pub fn _mm_conflict_epi64(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_conflict_epi64&expand=1252) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm_mask_conflict_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -295,7 +295,7 @@ pub fn _mm_mask_conflict_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_conflict_epi64&expand=1253) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpconflictq))] pub fn _mm_maskz_conflict_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -309,7 +309,7 @@ pub fn _mm_maskz_conflict_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_lzcnt_epi32&expand=3491) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm512_lzcnt_epi32(a: __m512i) -> __m512i { unsafe { transmute(simd_ctlz(a.as_i32x16())) } @@ -320,7 +320,7 @@ pub fn _mm512_lzcnt_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_lzcnt_epi32&expand=3492) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm512_mask_lzcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -334,7 +334,7 @@ pub fn _mm512_mask_lzcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_lzcnt_epi32&expand=3493) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm512_maskz_lzcnt_epi32(k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -348,7 +348,7 @@ pub fn _mm512_maskz_lzcnt_epi32(k: __mmask16, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lzcnt_epi32&expand=3488) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm256_lzcnt_epi32(a: __m256i) -> __m256i { unsafe { transmute(simd_ctlz(a.as_i32x8())) } @@ -359,7 +359,7 @@ pub fn _mm256_lzcnt_epi32(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_lzcnt_epi32&expand=3489) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm256_mask_lzcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -373,7 +373,7 @@ pub fn _mm256_mask_lzcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_lzcnt_epi32&expand=3490) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm256_maskz_lzcnt_epi32(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -387,7 +387,7 @@ pub fn _mm256_maskz_lzcnt_epi32(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lzcnt_epi32&expand=3485) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm_lzcnt_epi32(a: __m128i) -> __m128i { unsafe { transmute(simd_ctlz(a.as_i32x4())) } @@ -398,7 +398,7 @@ pub fn _mm_lzcnt_epi32(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_lzcnt_epi32&expand=3486) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm_mask_lzcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -412,7 +412,7 @@ pub fn _mm_mask_lzcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_lzcnt_epi32&expand=3487) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntd))] pub fn _mm_maskz_lzcnt_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -426,7 +426,7 @@ pub fn _mm_maskz_lzcnt_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_lzcnt_epi64&expand=3500) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm512_lzcnt_epi64(a: __m512i) -> __m512i { unsafe { transmute(simd_ctlz(a.as_i64x8())) } @@ -437,7 +437,7 @@ pub fn _mm512_lzcnt_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_lzcnt_epi64&expand=3501) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm512_mask_lzcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -451,7 +451,7 @@ pub fn _mm512_mask_lzcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_lzcnt_epi64&expand=3502) #[inline] #[target_feature(enable = "avx512cd")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm512_maskz_lzcnt_epi64(k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -465,7 +465,7 @@ pub fn _mm512_maskz_lzcnt_epi64(k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lzcnt_epi64&expand=3497) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm256_lzcnt_epi64(a: __m256i) -> __m256i { unsafe { transmute(simd_ctlz(a.as_i64x4())) } @@ -476,7 +476,7 @@ pub fn _mm256_lzcnt_epi64(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_lzcnt_epi64&expand=3498) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm256_mask_lzcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -490,7 +490,7 @@ pub fn _mm256_mask_lzcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_lzcnt_epi64&expand=3499) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm256_maskz_lzcnt_epi64(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -504,7 +504,7 @@ pub fn _mm256_maskz_lzcnt_epi64(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lzcnt_epi64&expand=3494) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm_lzcnt_epi64(a: __m128i) -> __m128i { unsafe { transmute(simd_ctlz(a.as_i64x2())) } @@ -515,7 +515,7 @@ pub fn _mm_lzcnt_epi64(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_lzcnt_epi64&expand=3495) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm_mask_lzcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -529,7 +529,7 @@ pub fn _mm_mask_lzcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_lzcnt_epi64&expand=3496) #[inline] #[target_feature(enable = "avx512cd,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vplzcntq))] pub fn _mm_maskz_lzcnt_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { diff --git a/crates/core_arch/src/x86/avx512dq.rs b/crates/core_arch/src/x86/avx512dq.rs index 20ae01b393..7ab3691fc4 100644 --- a/crates/core_arch/src/x86/avx512dq.rs +++ b/crates/core_arch/src/x86/avx512dq.rs @@ -14,7 +14,7 @@ use crate::{ #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_and_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { let and = _mm_and_pd(a, b).as_f64x2(); @@ -29,7 +29,7 @@ pub fn _mm_mask_and_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_and_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { let and = _mm_and_pd(a, b).as_f64x2(); @@ -45,7 +45,7 @@ pub fn _mm_maskz_and_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_and_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { let and = _mm256_and_pd(a, b).as_f64x4(); @@ -60,7 +60,7 @@ pub fn _mm256_mask_and_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_and_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { let and = _mm256_and_pd(a, b).as_f64x4(); @@ -75,7 +75,7 @@ pub fn _mm256_maskz_and_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandp))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_and_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(simd_and(transmute::<_, u64x8>(a), transmute::<_, u64x8>(b))) } } @@ -88,7 +88,7 @@ pub fn _mm512_and_pd(a: __m512d, b: __m512d) -> __m512d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_and_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { let and = _mm512_and_pd(a, b).as_f64x8(); @@ -103,7 +103,7 @@ pub fn _mm512_mask_and_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_and_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { let and = _mm512_and_pd(a, b).as_f64x8(); @@ -119,7 +119,7 @@ pub fn _mm512_maskz_and_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_and_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { let and = _mm_and_ps(a, b).as_f32x4(); @@ -134,7 +134,7 @@ pub fn _mm_mask_and_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_and_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { let and = _mm_and_ps(a, b).as_f32x4(); @@ -150,7 +150,7 @@ pub fn _mm_maskz_and_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_and_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { let and = _mm256_and_ps(a, b).as_f32x8(); @@ -165,7 +165,7 @@ pub fn _mm256_mask_and_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_and_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { let and = _mm256_and_ps(a, b).as_f32x8(); @@ -180,7 +180,7 @@ pub fn _mm256_maskz_and_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_and_ps(a: __m512, b: __m512) -> __m512 { unsafe { transmute(simd_and( @@ -198,7 +198,7 @@ pub fn _mm512_and_ps(a: __m512, b: __m512) -> __m512 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_and_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { let and = _mm512_and_ps(a, b).as_f32x16(); @@ -213,7 +213,7 @@ pub fn _mm512_mask_and_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __ #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_and_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { let and = _mm512_and_ps(a, b).as_f32x16(); @@ -231,7 +231,7 @@ pub fn _mm512_maskz_and_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandnpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_andnot_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { let andnot = _mm_andnot_pd(a, b).as_f64x2(); @@ -247,7 +247,7 @@ pub fn _mm_mask_andnot_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandnpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_andnot_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { let andnot = _mm_andnot_pd(a, b).as_f64x2(); @@ -263,7 +263,7 @@ pub fn _mm_maskz_andnot_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandnpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_andnot_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { let andnot = _mm256_andnot_pd(a, b).as_f64x4(); @@ -279,7 +279,7 @@ pub fn _mm256_mask_andnot_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandnpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_andnot_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { let andnot = _mm256_andnot_pd(a, b).as_f64x4(); @@ -294,7 +294,7 @@ pub fn _mm256_maskz_andnot_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandnp))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_andnot_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { _mm512_and_pd(_mm512_xor_pd(a, transmute(_mm512_set1_epi64(-1))), b) } } @@ -307,7 +307,7 @@ pub fn _mm512_andnot_pd(a: __m512d, b: __m512d) -> __m512d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandnpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_andnot_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { let andnot = _mm512_andnot_pd(a, b).as_f64x8(); @@ -323,7 +323,7 @@ pub fn _mm512_mask_andnot_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandnpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_andnot_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { let andnot = _mm512_andnot_pd(a, b).as_f64x8(); @@ -339,7 +339,7 @@ pub fn _mm512_maskz_andnot_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandnps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_andnot_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { let andnot = _mm_andnot_ps(a, b).as_f32x4(); @@ -355,7 +355,7 @@ pub fn _mm_mask_andnot_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandnps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_andnot_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { let andnot = _mm_andnot_ps(a, b).as_f32x4(); @@ -371,7 +371,7 @@ pub fn _mm_maskz_andnot_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandnps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_andnot_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { let andnot = _mm256_andnot_ps(a, b).as_f32x8(); @@ -387,7 +387,7 @@ pub fn _mm256_mask_andnot_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vandnps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_andnot_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { let andnot = _mm256_andnot_ps(a, b).as_f32x8(); @@ -402,7 +402,7 @@ pub fn _mm256_maskz_andnot_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandnps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_andnot_ps(a: __m512, b: __m512) -> __m512 { unsafe { _mm512_and_ps(_mm512_xor_ps(a, transmute(_mm512_set1_epi32(-1))), b) } } @@ -415,7 +415,7 @@ pub fn _mm512_andnot_ps(a: __m512, b: __m512) -> __m512 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandnps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_andnot_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { let andnot = _mm512_andnot_ps(a, b).as_f32x16(); @@ -431,7 +431,7 @@ pub fn _mm512_mask_andnot_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vandnps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_andnot_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { let andnot = _mm512_andnot_ps(a, b).as_f32x16(); @@ -449,7 +449,7 @@ pub fn _mm512_maskz_andnot_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_or_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { let or = _mm_or_pd(a, b).as_f64x2(); @@ -464,7 +464,7 @@ pub fn _mm_mask_or_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m1 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_or_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { let or = _mm_or_pd(a, b).as_f64x2(); @@ -480,7 +480,7 @@ pub fn _mm_maskz_or_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_or_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { let or = _mm256_or_pd(a, b).as_f64x4(); @@ -495,7 +495,7 @@ pub fn _mm256_mask_or_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> _ #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_or_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { let or = _mm256_or_pd(a, b).as_f64x4(); @@ -510,7 +510,7 @@ pub fn _mm256_maskz_or_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vorp))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_or_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(simd_or(transmute::<_, u64x8>(a), transmute::<_, u64x8>(b))) } } @@ -523,7 +523,7 @@ pub fn _mm512_or_pd(a: __m512d, b: __m512d) -> __m512d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_or_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { let or = _mm512_or_pd(a, b).as_f64x8(); @@ -538,7 +538,7 @@ pub fn _mm512_mask_or_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> _ #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_or_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { let or = _mm512_or_pd(a, b).as_f64x8(); @@ -554,7 +554,7 @@ pub fn _mm512_maskz_or_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_or_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { let or = _mm_or_ps(a, b).as_f32x4(); @@ -569,7 +569,7 @@ pub fn _mm_mask_or_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_or_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { let or = _mm_or_ps(a, b).as_f32x4(); @@ -585,7 +585,7 @@ pub fn _mm_maskz_or_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_or_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { let or = _mm256_or_ps(a, b).as_f32x8(); @@ -600,7 +600,7 @@ pub fn _mm256_mask_or_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m2 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_or_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { let or = _mm256_or_ps(a, b).as_f32x8(); @@ -615,7 +615,7 @@ pub fn _mm256_maskz_or_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_or_ps(a: __m512, b: __m512) -> __m512 { unsafe { transmute(simd_or( @@ -633,7 +633,7 @@ pub fn _mm512_or_ps(a: __m512, b: __m512) -> __m512 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_or_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { let or = _mm512_or_ps(a, b).as_f32x16(); @@ -648,7 +648,7 @@ pub fn _mm512_mask_or_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_or_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { let or = _mm512_or_ps(a, b).as_f32x16(); @@ -666,7 +666,7 @@ pub fn _mm512_maskz_or_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vxorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_xor_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { let xor = _mm_xor_pd(a, b).as_f64x2(); @@ -681,7 +681,7 @@ pub fn _mm_mask_xor_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vxorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_xor_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { let xor = _mm_xor_pd(a, b).as_f64x2(); @@ -697,7 +697,7 @@ pub fn _mm_maskz_xor_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vxorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_xor_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { let xor = _mm256_xor_pd(a, b).as_f64x4(); @@ -712,7 +712,7 @@ pub fn _mm256_mask_xor_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vxorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_xor_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { let xor = _mm256_xor_pd(a, b).as_f64x4(); @@ -727,7 +727,7 @@ pub fn _mm256_maskz_xor_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vxorp))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_xor_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(simd_xor(transmute::<_, u64x8>(a), transmute::<_, u64x8>(b))) } } @@ -740,7 +740,7 @@ pub fn _mm512_xor_pd(a: __m512d, b: __m512d) -> __m512d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vxorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_xor_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { let xor = _mm512_xor_pd(a, b).as_f64x8(); @@ -755,7 +755,7 @@ pub fn _mm512_mask_xor_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vxorpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_xor_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { let xor = _mm512_xor_pd(a, b).as_f64x8(); @@ -771,7 +771,7 @@ pub fn _mm512_maskz_xor_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vxorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_xor_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { let xor = _mm_xor_ps(a, b).as_f32x4(); @@ -786,7 +786,7 @@ pub fn _mm_mask_xor_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vxorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_xor_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { let xor = _mm_xor_ps(a, b).as_f32x4(); @@ -802,7 +802,7 @@ pub fn _mm_maskz_xor_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vxorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_xor_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { let xor = _mm256_xor_ps(a, b).as_f32x8(); @@ -817,7 +817,7 @@ pub fn _mm256_mask_xor_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vxorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_xor_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { let xor = _mm256_xor_ps(a, b).as_f32x8(); @@ -832,7 +832,7 @@ pub fn _mm256_maskz_xor_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vxorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_xor_ps(a: __m512, b: __m512) -> __m512 { unsafe { transmute(simd_xor( @@ -850,7 +850,7 @@ pub fn _mm512_xor_ps(a: __m512, b: __m512) -> __m512 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vxorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_xor_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { let xor = _mm512_xor_ps(a, b).as_f32x16(); @@ -865,7 +865,7 @@ pub fn _mm512_mask_xor_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __ #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vxorps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_xor_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { let xor = _mm512_xor_ps(a, b).as_f32x16(); @@ -881,7 +881,7 @@ pub fn _mm512_maskz_xor_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcast_f32x2&ig_expand=509) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_broadcast_f32x2(a: __m128) -> __m256 { unsafe { let b: f32x8 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1]); @@ -896,7 +896,7 @@ pub fn _mm256_broadcast_f32x2(a: __m128) -> __m256 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vbroadcastf32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_broadcast_f32x2(src: __m256, k: __mmask8, a: __m128) -> __m256 { unsafe { let b = _mm256_broadcast_f32x2(a).as_f32x8(); @@ -911,7 +911,7 @@ pub fn _mm256_mask_broadcast_f32x2(src: __m256, k: __mmask8, a: __m128) -> __m25 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vbroadcastf32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_broadcast_f32x2(k: __mmask8, a: __m128) -> __m256 { unsafe { let b = _mm256_broadcast_f32x2(a).as_f32x8(); @@ -925,7 +925,7 @@ pub fn _mm256_maskz_broadcast_f32x2(k: __mmask8, a: __m128) -> __m256 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_f32x2&ig_expand=512) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_f32x2(a: __m128) -> __m512 { unsafe { let b: f32x16 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1]); @@ -940,7 +940,7 @@ pub fn _mm512_broadcast_f32x2(a: __m128) -> __m512 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vbroadcastf32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_f32x2(src: __m512, k: __mmask16, a: __m128) -> __m512 { unsafe { let b = _mm512_broadcast_f32x2(a).as_f32x16(); @@ -955,7 +955,7 @@ pub fn _mm512_mask_broadcast_f32x2(src: __m512, k: __mmask16, a: __m128) -> __m5 #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vbroadcastf32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_f32x2(k: __mmask16, a: __m128) -> __m512 { unsafe { let b = _mm512_broadcast_f32x2(a).as_f32x16(); @@ -969,7 +969,7 @@ pub fn _mm512_maskz_broadcast_f32x2(k: __mmask16, a: __m128) -> __m512 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_f32x8&ig_expand=521) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_f32x8(a: __m256) -> __m512 { unsafe { let b: f32x16 = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7]); @@ -983,7 +983,7 @@ pub fn _mm512_broadcast_f32x8(a: __m256) -> __m512 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcast_f32x8&ig_expand=522) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_f32x8(src: __m512, k: __mmask16, a: __m256) -> __m512 { unsafe { let b = _mm512_broadcast_f32x8(a).as_f32x16(); @@ -997,7 +997,7 @@ pub fn _mm512_mask_broadcast_f32x8(src: __m512, k: __mmask16, a: __m256) -> __m5 /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcast_f32x8&ig_expand=523) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_f32x8(k: __mmask16, a: __m256) -> __m512 { unsafe { let b = _mm512_broadcast_f32x8(a).as_f32x16(); @@ -1011,7 +1011,7 @@ pub fn _mm512_maskz_broadcast_f32x8(k: __mmask16, a: __m256) -> __m512 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcast_f64x2&ig_expand=524) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_broadcast_f64x2(a: __m128d) -> __m256d { unsafe { let b: f64x4 = simd_shuffle!(a, a, [0, 1, 0, 1]); @@ -1025,7 +1025,7 @@ pub fn _mm256_broadcast_f64x2(a: __m128d) -> __m256d { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcast_f64x2&ig_expand=525) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_broadcast_f64x2(src: __m256d, k: __mmask8, a: __m128d) -> __m256d { unsafe { let b = _mm256_broadcast_f64x2(a).as_f64x4(); @@ -1039,7 +1039,7 @@ pub fn _mm256_mask_broadcast_f64x2(src: __m256d, k: __mmask8, a: __m128d) -> __m /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcast_f64x2&ig_expand=526) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m256d { unsafe { let b = _mm256_broadcast_f64x2(a).as_f64x4(); @@ -1053,7 +1053,7 @@ pub fn _mm256_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m256d { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_f64x2&ig_expand=527) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_f64x2(a: __m128d) -> __m512d { unsafe { let b: f64x8 = simd_shuffle!(a, a, [0, 1, 0, 1, 0, 1, 0, 1]); @@ -1067,7 +1067,7 @@ pub fn _mm512_broadcast_f64x2(a: __m128d) -> __m512d { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcast_f64x2&ig_expand=528) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_f64x2(src: __m512d, k: __mmask8, a: __m128d) -> __m512d { unsafe { let b = _mm512_broadcast_f64x2(a).as_f64x8(); @@ -1081,7 +1081,7 @@ pub fn _mm512_mask_broadcast_f64x2(src: __m512d, k: __mmask8, a: __m128d) -> __m /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcast_f64x2&ig_expand=529) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m512d { unsafe { let b = _mm512_broadcast_f64x2(a).as_f64x8(); @@ -1094,7 +1094,7 @@ pub fn _mm512_maskz_broadcast_f64x2(k: __mmask8, a: __m128d) -> __m512d { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_broadcast_i32x2&ig_expand=533) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_broadcast_i32x2(a: __m128i) -> __m128i { unsafe { let a = a.as_i32x4(); @@ -1110,7 +1110,7 @@ pub fn _mm_broadcast_i32x2(a: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vbroadcasti32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_broadcast_i32x2(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { let b = _mm_broadcast_i32x2(a).as_i32x4(); @@ -1125,7 +1125,7 @@ pub fn _mm_mask_broadcast_i32x2(src: __m128i, k: __mmask8, a: __m128i) -> __m128 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vbroadcasti32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m128i { unsafe { let b = _mm_broadcast_i32x2(a).as_i32x4(); @@ -1138,7 +1138,7 @@ pub fn _mm_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcast_i32x2&ig_expand=536) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_broadcast_i32x2(a: __m128i) -> __m256i { unsafe { let a = a.as_i32x4(); @@ -1154,7 +1154,7 @@ pub fn _mm256_broadcast_i32x2(a: __m128i) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vbroadcasti32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_broadcast_i32x2(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { let b = _mm256_broadcast_i32x2(a).as_i32x8(); @@ -1169,7 +1169,7 @@ pub fn _mm256_mask_broadcast_i32x2(src: __m256i, k: __mmask8, a: __m128i) -> __m #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vbroadcasti32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m256i { unsafe { let b = _mm256_broadcast_i32x2(a).as_i32x8(); @@ -1182,7 +1182,7 @@ pub fn _mm256_maskz_broadcast_i32x2(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_i32x2&ig_expand=539) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_i32x2(a: __m128i) -> __m512i { unsafe { let a = a.as_i32x4(); @@ -1198,7 +1198,7 @@ pub fn _mm512_broadcast_i32x2(a: __m128i) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vbroadcasti32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_i32x2(src: __m512i, k: __mmask16, a: __m128i) -> __m512i { unsafe { let b = _mm512_broadcast_i32x2(a).as_i32x16(); @@ -1213,7 +1213,7 @@ pub fn _mm512_mask_broadcast_i32x2(src: __m512i, k: __mmask16, a: __m128i) -> __ #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vbroadcasti32x2))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_i32x2(k: __mmask16, a: __m128i) -> __m512i { unsafe { let b = _mm512_broadcast_i32x2(a).as_i32x16(); @@ -1226,7 +1226,7 @@ pub fn _mm512_maskz_broadcast_i32x2(k: __mmask16, a: __m128i) -> __m512i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_i32x8&ig_expand=548) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_i32x8(a: __m256i) -> __m512i { unsafe { let a = a.as_i32x8(); @@ -1241,7 +1241,7 @@ pub fn _mm512_broadcast_i32x8(a: __m256i) -> __m512i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcast_i32x8&ig_expand=549) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_i32x8(src: __m512i, k: __mmask16, a: __m256i) -> __m512i { unsafe { let b = _mm512_broadcast_i32x8(a).as_i32x16(); @@ -1255,7 +1255,7 @@ pub fn _mm512_mask_broadcast_i32x8(src: __m512i, k: __mmask16, a: __m256i) -> __ /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcast_i32x8&ig_expand=550) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_i32x8(k: __mmask16, a: __m256i) -> __m512i { unsafe { let b = _mm512_broadcast_i32x8(a).as_i32x16(); @@ -1268,7 +1268,7 @@ pub fn _mm512_maskz_broadcast_i32x8(k: __mmask16, a: __m256i) -> __m512i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcast_i64x2&ig_expand=551) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_broadcast_i64x2(a: __m128i) -> __m256i { unsafe { let a = a.as_i64x2(); @@ -1283,7 +1283,7 @@ pub fn _mm256_broadcast_i64x2(a: __m128i) -> __m256i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcast_i64x2&ig_expand=552) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_broadcast_i64x2(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { let b = _mm256_broadcast_i64x2(a).as_i64x4(); @@ -1297,7 +1297,7 @@ pub fn _mm256_mask_broadcast_i64x2(src: __m256i, k: __mmask8, a: __m128i) -> __m /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcast_i64x2&ig_expand=553) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m256i { unsafe { let b = _mm256_broadcast_i64x2(a).as_i64x4(); @@ -1310,7 +1310,7 @@ pub fn _mm256_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_i64x2&ig_expand=554) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_i64x2(a: __m128i) -> __m512i { unsafe { let a = a.as_i64x2(); @@ -1325,7 +1325,7 @@ pub fn _mm512_broadcast_i64x2(a: __m128i) -> __m512i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcast_i64x2&ig_expand=555) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_i64x2(src: __m512i, k: __mmask8, a: __m128i) -> __m512i { unsafe { let b = _mm512_broadcast_i64x2(a).as_i64x8(); @@ -1339,7 +1339,7 @@ pub fn _mm512_mask_broadcast_i64x2(src: __m512i, k: __mmask8, a: __m128i) -> __m /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcast_i64x2&ig_expand=556) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m512i { unsafe { let b = _mm512_broadcast_i64x2(a).as_i64x8(); @@ -1356,7 +1356,7 @@ pub fn _mm512_maskz_broadcast_i64x2(k: __mmask8, a: __m128i) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_extractf32x8_ps(a: __m512) -> __m256 { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1376,7 +1376,7 @@ pub fn _mm512_extractf32x8_ps(a: __m512) -> __m256 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vextractf32x8, IMM8 = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_extractf32x8_ps(src: __m256, k: __mmask8, a: __m512) -> __m256 { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1394,7 +1394,7 @@ pub fn _mm512_mask_extractf32x8_ps(src: __m256, k: __mmask8, a: #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vextractf32x8, IMM8 = 1))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_extractf32x8_ps(k: __mmask8, a: __m512) -> __m256 { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1410,7 +1410,7 @@ pub fn _mm512_maskz_extractf32x8_ps(k: __mmask8, a: __m512) -> #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_extractf64x2_pd(a: __m256d) -> __m128d { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1430,7 +1430,7 @@ pub fn _mm256_extractf64x2_pd(a: __m256d) -> __m128d { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vextractf64x2, IMM8 = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_extractf64x2_pd( src: __m128d, k: __mmask8, @@ -1452,7 +1452,7 @@ pub fn _mm256_mask_extractf64x2_pd( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vextractf64x2, IMM8 = 1))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_extractf64x2_pd(k: __mmask8, a: __m256d) -> __m128d { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1468,7 +1468,7 @@ pub fn _mm256_maskz_extractf64x2_pd(k: __mmask8, a: __m256d) -> #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_extractf64x2_pd(a: __m512d) -> __m128d { unsafe { static_assert_uimm_bits!(IMM8, 2); @@ -1490,7 +1490,7 @@ pub fn _mm512_extractf64x2_pd(a: __m512d) -> __m128d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vextractf64x2, IMM8 = 3))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_extractf64x2_pd( src: __m128d, k: __mmask8, @@ -1512,7 +1512,7 @@ pub fn _mm512_mask_extractf64x2_pd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vextractf64x2, IMM8 = 3))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_extractf64x2_pd(k: __mmask8, a: __m512d) -> __m128d { unsafe { static_assert_uimm_bits!(IMM8, 2); @@ -1528,7 +1528,7 @@ pub fn _mm512_maskz_extractf64x2_pd(k: __mmask8, a: __m512d) -> #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_extracti32x8_epi32(a: __m512i) -> __m256i { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1549,7 +1549,7 @@ pub fn _mm512_extracti32x8_epi32(a: __m512i) -> __m256i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vextracti32x8, IMM8 = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_extracti32x8_epi32( src: __m256i, k: __mmask8, @@ -1570,7 +1570,7 @@ pub fn _mm512_mask_extracti32x8_epi32( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vextracti32x8, IMM8 = 1))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_extracti32x8_epi32(k: __mmask8, a: __m512i) -> __m256i { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1586,7 +1586,7 @@ pub fn _mm512_maskz_extracti32x8_epi32(k: __mmask8, a: __m512i) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_extracti64x2_epi64(a: __m256i) -> __m128i { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1606,7 +1606,7 @@ pub fn _mm256_extracti64x2_epi64(a: __m256i) -> __m128i { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vextracti64x2, IMM8 = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_extracti64x2_epi64( src: __m128i, k: __mmask8, @@ -1627,7 +1627,7 @@ pub fn _mm256_mask_extracti64x2_epi64( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vextracti64x2, IMM8 = 1))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_extracti64x2_epi64(k: __mmask8, a: __m256i) -> __m128i { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1643,7 +1643,7 @@ pub fn _mm256_maskz_extracti64x2_epi64(k: __mmask8, a: __m256i) #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_extracti64x2_epi64(a: __m512i) -> __m128i { unsafe { static_assert_uimm_bits!(IMM8, 2); @@ -1665,7 +1665,7 @@ pub fn _mm512_extracti64x2_epi64(a: __m512i) -> __m128i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vextracti64x2, IMM8 = 3))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_extracti64x2_epi64( src: __m128i, k: __mmask8, @@ -1686,7 +1686,7 @@ pub fn _mm512_mask_extracti64x2_epi64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vextracti64x2, IMM8 = 3))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_extracti64x2_epi64(k: __mmask8, a: __m512i) -> __m128i { unsafe { static_assert_uimm_bits!(IMM8, 2); @@ -1704,7 +1704,7 @@ pub fn _mm512_maskz_extracti64x2_epi64(k: __mmask8, a: __m512i) #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_insertf32x8(a: __m512, b: __m256) -> __m512 { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1737,7 +1737,7 @@ pub fn _mm512_insertf32x8(a: __m512, b: __m256) -> __m512 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vinsertf32x8, IMM8 = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_insertf32x8( src: __m512, k: __mmask16, @@ -1760,7 +1760,7 @@ pub fn _mm512_mask_insertf32x8( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vinsertf32x8, IMM8 = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_insertf32x8(k: __mmask16, a: __m512, b: __m256) -> __m512 { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1776,7 +1776,7 @@ pub fn _mm512_maskz_insertf32x8(k: __mmask16, a: __m512, b: __m #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_insertf64x2(a: __m256d, b: __m128d) -> __m256d { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1797,7 +1797,7 @@ pub fn _mm256_insertf64x2(a: __m256d, b: __m128d) -> __m256d { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vinsertf64x2, IMM8 = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_insertf64x2( src: __m256d, k: __mmask8, @@ -1820,7 +1820,7 @@ pub fn _mm256_mask_insertf64x2( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vinsertf64x2, IMM8 = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_insertf64x2(k: __mmask8, a: __m256d, b: __m128d) -> __m256d { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1836,7 +1836,7 @@ pub fn _mm256_maskz_insertf64x2(k: __mmask8, a: __m256d, b: __m #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_insertf64x2(a: __m512d, b: __m128d) -> __m512d { unsafe { static_assert_uimm_bits!(IMM8, 2); @@ -1859,7 +1859,7 @@ pub fn _mm512_insertf64x2(a: __m512d, b: __m128d) -> __m512d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vinsertf64x2, IMM8 = 3))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_insertf64x2( src: __m512d, k: __mmask8, @@ -1882,7 +1882,7 @@ pub fn _mm512_mask_insertf64x2( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vinsertf64x2, IMM8 = 3))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_insertf64x2(k: __mmask8, a: __m512d, b: __m128d) -> __m512d { unsafe { static_assert_uimm_bits!(IMM8, 2); @@ -1898,7 +1898,7 @@ pub fn _mm512_maskz_insertf64x2(k: __mmask8, a: __m512d, b: __m #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_inserti32x8(a: __m512i, b: __m256i) -> __m512i { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1933,7 +1933,7 @@ pub fn _mm512_inserti32x8(a: __m512i, b: __m256i) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vinserti32x8, IMM8 = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_inserti32x8( src: __m512i, k: __mmask16, @@ -1956,7 +1956,7 @@ pub fn _mm512_mask_inserti32x8( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vinserti32x8, IMM8 = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_inserti32x8(k: __mmask16, a: __m512i, b: __m256i) -> __m512i { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1972,7 +1972,7 @@ pub fn _mm512_maskz_inserti32x8(k: __mmask16, a: __m512i, b: __ #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_inserti64x2(a: __m256i, b: __m128i) -> __m256i { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -1994,7 +1994,7 @@ pub fn _mm256_inserti64x2(a: __m256i, b: __m128i) -> __m256i { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vinserti64x2, IMM8 = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_inserti64x2( src: __m256i, k: __mmask8, @@ -2017,7 +2017,7 @@ pub fn _mm256_mask_inserti64x2( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vinserti64x2, IMM8 = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_inserti64x2(k: __mmask8, a: __m256i, b: __m128i) -> __m256i { unsafe { static_assert_uimm_bits!(IMM8, 1); @@ -2033,7 +2033,7 @@ pub fn _mm256_maskz_inserti64x2(k: __mmask8, a: __m256i, b: __m #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_inserti64x2(a: __m512i, b: __m128i) -> __m512i { unsafe { static_assert_uimm_bits!(IMM8, 2); @@ -2057,7 +2057,7 @@ pub fn _mm512_inserti64x2(a: __m512i, b: __m128i) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vinserti64x2, IMM8 = 3))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_inserti64x2( src: __m512i, k: __mmask8, @@ -2080,7 +2080,7 @@ pub fn _mm512_mask_inserti64x2( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vinserti64x2, IMM8 = 3))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_inserti64x2(k: __mmask8, a: __m512i, b: __m128i) -> __m512i { unsafe { static_assert_uimm_bits!(IMM8, 2); @@ -2105,7 +2105,7 @@ pub fn _mm512_maskz_inserti64x2(k: __mmask8, a: __m512i, b: __m #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2pd, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvt_roundepi64_pd(a: __m512i) -> __m512d { unsafe { static_assert_rounding!(ROUNDING); @@ -2128,7 +2128,7 @@ pub fn _mm512_cvt_roundepi64_pd(a: __m512i) -> __m512d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2pd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvt_roundepi64_pd( src: __m512d, k: __mmask8, @@ -2156,7 +2156,7 @@ pub fn _mm512_mask_cvt_roundepi64_pd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2pd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvt_roundepi64_pd(k: __mmask8, a: __m512i) -> __m512d { unsafe { static_assert_rounding!(ROUNDING); @@ -2172,7 +2172,7 @@ pub fn _mm512_maskz_cvt_roundepi64_pd(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtepi64_pd(a: __m128i) -> __m128d { unsafe { transmute(vcvtqq2pd_128(a.as_i64x2(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2185,7 +2185,7 @@ pub fn _mm_cvtepi64_pd(a: __m128i) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtepi64_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d { unsafe { let b = _mm_cvtepi64_pd(a).as_f64x2(); @@ -2200,7 +2200,7 @@ pub fn _mm_mask_cvtepi64_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtepi64_pd(k: __mmask8, a: __m128i) -> __m128d { unsafe { let b = _mm_cvtepi64_pd(a).as_f64x2(); @@ -2215,7 +2215,7 @@ pub fn _mm_maskz_cvtepi64_pd(k: __mmask8, a: __m128i) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtepi64_pd(a: __m256i) -> __m256d { unsafe { transmute(vcvtqq2pd_256(a.as_i64x4(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2228,7 +2228,7 @@ pub fn _mm256_cvtepi64_pd(a: __m256i) -> __m256d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtepi64_pd(src: __m256d, k: __mmask8, a: __m256i) -> __m256d { unsafe { let b = _mm256_cvtepi64_pd(a).as_f64x4(); @@ -2243,7 +2243,7 @@ pub fn _mm256_mask_cvtepi64_pd(src: __m256d, k: __mmask8, a: __m256i) -> __m256d #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtepi64_pd(k: __mmask8, a: __m256i) -> __m256d { unsafe { let b = _mm256_cvtepi64_pd(a).as_f64x4(); @@ -2258,7 +2258,7 @@ pub fn _mm256_maskz_cvtepi64_pd(k: __mmask8, a: __m256i) -> __m256d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtepi64_pd(a: __m512i) -> __m512d { unsafe { transmute(vcvtqq2pd_512(a.as_i64x8(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2271,7 +2271,7 @@ pub fn _mm512_cvtepi64_pd(a: __m512i) -> __m512d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtepi64_pd(src: __m512d, k: __mmask8, a: __m512i) -> __m512d { unsafe { let b = _mm512_cvtepi64_pd(a).as_f64x8(); @@ -2286,7 +2286,7 @@ pub fn _mm512_mask_cvtepi64_pd(src: __m512d, k: __mmask8, a: __m512i) -> __m512d #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtepi64_pd(k: __mmask8, a: __m512i) -> __m512d { unsafe { let b = _mm512_cvtepi64_pd(a).as_f64x8(); @@ -2308,7 +2308,7 @@ pub fn _mm512_maskz_cvtepi64_pd(k: __mmask8, a: __m512i) -> __m512d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvt_roundepi64_ps(a: __m512i) -> __m256 { unsafe { static_assert_rounding!(ROUNDING); @@ -2331,7 +2331,7 @@ pub fn _mm512_cvt_roundepi64_ps(a: __m512i) -> __m256 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvt_roundepi64_ps( src: __m256, k: __mmask8, @@ -2359,7 +2359,7 @@ pub fn _mm512_mask_cvt_roundepi64_ps( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvt_roundepi64_ps(k: __mmask8, a: __m512i) -> __m256 { unsafe { static_assert_rounding!(ROUNDING); @@ -2375,7 +2375,7 @@ pub fn _mm512_maskz_cvt_roundepi64_ps(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtepi64_ps(a: __m128i) -> __m128 { _mm_mask_cvtepi64_ps(_mm_undefined_ps(), 0xff, a) } @@ -2388,7 +2388,7 @@ pub fn _mm_cvtepi64_ps(a: __m128i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtepi64_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 { unsafe { transmute(vcvtqq2ps_128(a.as_i64x2(), src.as_f32x4(), k)) } } @@ -2400,7 +2400,7 @@ pub fn _mm_mask_cvtepi64_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtepi64_ps(k: __mmask8, a: __m128i) -> __m128 { _mm_mask_cvtepi64_ps(_mm_setzero_ps(), k, a) } @@ -2412,7 +2412,7 @@ pub fn _mm_maskz_cvtepi64_ps(k: __mmask8, a: __m128i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtepi64_ps(a: __m256i) -> __m128 { unsafe { transmute(vcvtqq2ps_256(a.as_i64x4(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2425,7 +2425,7 @@ pub fn _mm256_cvtepi64_ps(a: __m256i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtepi64_ps(src: __m128, k: __mmask8, a: __m256i) -> __m128 { unsafe { let b = _mm256_cvtepi64_ps(a).as_f32x4(); @@ -2440,7 +2440,7 @@ pub fn _mm256_mask_cvtepi64_ps(src: __m128, k: __mmask8, a: __m256i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtepi64_ps(k: __mmask8, a: __m256i) -> __m128 { unsafe { let b = _mm256_cvtepi64_ps(a).as_f32x4(); @@ -2455,7 +2455,7 @@ pub fn _mm256_maskz_cvtepi64_ps(k: __mmask8, a: __m256i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtepi64_ps(a: __m512i) -> __m256 { unsafe { transmute(vcvtqq2ps_512(a.as_i64x8(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2468,7 +2468,7 @@ pub fn _mm512_cvtepi64_ps(a: __m512i) -> __m256 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtepi64_ps(src: __m256, k: __mmask8, a: __m512i) -> __m256 { unsafe { let b = _mm512_cvtepi64_ps(a).as_f32x8(); @@ -2483,7 +2483,7 @@ pub fn _mm512_mask_cvtepi64_ps(src: __m256, k: __mmask8, a: __m512i) -> __m256 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtepi64_ps(k: __mmask8, a: __m512i) -> __m256 { unsafe { let b = _mm512_cvtepi64_ps(a).as_f32x8(); @@ -2505,7 +2505,7 @@ pub fn _mm512_maskz_cvtepi64_ps(k: __mmask8, a: __m512i) -> __m256 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2pd, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvt_roundepu64_pd(a: __m512i) -> __m512d { unsafe { static_assert_rounding!(ROUNDING); @@ -2528,7 +2528,7 @@ pub fn _mm512_cvt_roundepu64_pd(a: __m512i) -> __m512d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2pd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvt_roundepu64_pd( src: __m512d, k: __mmask8, @@ -2556,7 +2556,7 @@ pub fn _mm512_mask_cvt_roundepu64_pd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2pd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvt_roundepu64_pd(k: __mmask8, a: __m512i) -> __m512d { unsafe { static_assert_rounding!(ROUNDING); @@ -2572,7 +2572,7 @@ pub fn _mm512_maskz_cvt_roundepu64_pd(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtepu64_pd(a: __m128i) -> __m128d { unsafe { transmute(vcvtuqq2pd_128(a.as_u64x2(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2585,7 +2585,7 @@ pub fn _mm_cvtepu64_pd(a: __m128i) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtepu64_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d { unsafe { let b = _mm_cvtepu64_pd(a).as_f64x2(); @@ -2600,7 +2600,7 @@ pub fn _mm_mask_cvtepu64_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtepu64_pd(k: __mmask8, a: __m128i) -> __m128d { unsafe { let b = _mm_cvtepu64_pd(a).as_f64x2(); @@ -2615,7 +2615,7 @@ pub fn _mm_maskz_cvtepu64_pd(k: __mmask8, a: __m128i) -> __m128d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtepu64_pd(a: __m256i) -> __m256d { unsafe { transmute(vcvtuqq2pd_256(a.as_u64x4(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2628,7 +2628,7 @@ pub fn _mm256_cvtepu64_pd(a: __m256i) -> __m256d { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtepu64_pd(src: __m256d, k: __mmask8, a: __m256i) -> __m256d { unsafe { let b = _mm256_cvtepu64_pd(a).as_f64x4(); @@ -2643,7 +2643,7 @@ pub fn _mm256_mask_cvtepu64_pd(src: __m256d, k: __mmask8, a: __m256i) -> __m256d #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtepu64_pd(k: __mmask8, a: __m256i) -> __m256d { unsafe { let b = _mm256_cvtepu64_pd(a).as_f64x4(); @@ -2658,7 +2658,7 @@ pub fn _mm256_maskz_cvtepu64_pd(k: __mmask8, a: __m256i) -> __m256d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtepu64_pd(a: __m512i) -> __m512d { unsafe { transmute(vcvtuqq2pd_512(a.as_u64x8(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2671,7 +2671,7 @@ pub fn _mm512_cvtepu64_pd(a: __m512i) -> __m512d { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtepu64_pd(src: __m512d, k: __mmask8, a: __m512i) -> __m512d { unsafe { let b = _mm512_cvtepu64_pd(a).as_f64x8(); @@ -2686,7 +2686,7 @@ pub fn _mm512_mask_cvtepu64_pd(src: __m512d, k: __mmask8, a: __m512i) -> __m512d #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2pd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtepu64_pd(k: __mmask8, a: __m512i) -> __m512d { unsafe { let b = _mm512_cvtepu64_pd(a).as_f64x8(); @@ -2708,7 +2708,7 @@ pub fn _mm512_maskz_cvtepu64_pd(k: __mmask8, a: __m512i) -> __m512d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvt_roundepu64_ps(a: __m512i) -> __m256 { unsafe { static_assert_rounding!(ROUNDING); @@ -2731,7 +2731,7 @@ pub fn _mm512_cvt_roundepu64_ps(a: __m512i) -> __m256 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvt_roundepu64_ps( src: __m256, k: __mmask8, @@ -2759,7 +2759,7 @@ pub fn _mm512_mask_cvt_roundepu64_ps( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvt_roundepu64_ps(k: __mmask8, a: __m512i) -> __m256 { unsafe { static_assert_rounding!(ROUNDING); @@ -2775,7 +2775,7 @@ pub fn _mm512_maskz_cvt_roundepu64_ps(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtepu64_ps(a: __m128i) -> __m128 { _mm_mask_cvtepu64_ps(_mm_undefined_ps(), 0xff, a) } @@ -2788,7 +2788,7 @@ pub fn _mm_cvtepu64_ps(a: __m128i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtepu64_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 { unsafe { transmute(vcvtuqq2ps_128(a.as_u64x2(), src.as_f32x4(), k)) } } @@ -2800,7 +2800,7 @@ pub fn _mm_mask_cvtepu64_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtepu64_ps(k: __mmask8, a: __m128i) -> __m128 { _mm_mask_cvtepu64_ps(_mm_setzero_ps(), k, a) } @@ -2812,7 +2812,7 @@ pub fn _mm_maskz_cvtepu64_ps(k: __mmask8, a: __m128i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtepu64_ps(a: __m256i) -> __m128 { unsafe { transmute(vcvtuqq2ps_256(a.as_u64x4(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2825,7 +2825,7 @@ pub fn _mm256_cvtepu64_ps(a: __m256i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtepu64_ps(src: __m128, k: __mmask8, a: __m256i) -> __m128 { unsafe { let b = _mm256_cvtepu64_ps(a).as_f32x4(); @@ -2840,7 +2840,7 @@ pub fn _mm256_mask_cvtepu64_ps(src: __m128, k: __mmask8, a: __m256i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtepu64_ps(k: __mmask8, a: __m256i) -> __m128 { unsafe { let b = _mm256_cvtepu64_ps(a).as_f32x4(); @@ -2855,7 +2855,7 @@ pub fn _mm256_maskz_cvtepu64_ps(k: __mmask8, a: __m256i) -> __m128 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtepu64_ps(a: __m512i) -> __m256 { unsafe { transmute(vcvtuqq2ps_512(a.as_u64x8(), _MM_FROUND_CUR_DIRECTION)) } } @@ -2868,7 +2868,7 @@ pub fn _mm512_cvtepu64_ps(a: __m512i) -> __m256 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtepu64_ps(src: __m256, k: __mmask8, a: __m512i) -> __m256 { unsafe { let b = _mm512_cvtepu64_ps(a).as_f32x8(); @@ -2883,7 +2883,7 @@ pub fn _mm512_mask_cvtepu64_ps(src: __m256, k: __mmask8, a: __m512i) -> __m256 { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtuqq2ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtepu64_ps(k: __mmask8, a: __m512i) -> __m256 { unsafe { let b = _mm512_cvtepu64_ps(a).as_f32x8(); @@ -2905,7 +2905,7 @@ pub fn _mm512_maskz_cvtepu64_ps(k: __mmask8, a: __m512i) -> __m256 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvt_roundpd_epi64(a: __m512d) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -2926,7 +2926,7 @@ pub fn _mm512_cvt_roundpd_epi64(a: __m512d) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvt_roundpd_epi64( src: __m512i, k: __mmask8, @@ -2953,7 +2953,7 @@ pub fn _mm512_mask_cvt_roundpd_epi64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvt_roundpd_epi64(k: __mmask8, a: __m512d) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_epi64::(_mm512_setzero_si512(), k, a) @@ -2966,7 +2966,7 @@ pub fn _mm512_maskz_cvt_roundpd_epi64(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtpd_epi64(a: __m128d) -> __m128i { _mm_mask_cvtpd_epi64(_mm_undefined_si128(), 0xff, a) } @@ -2979,7 +2979,7 @@ pub fn _mm_cvtpd_epi64(a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtpd_epi64(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvtpd2qq_128(a.as_f64x2(), src.as_i64x2(), k)) } } @@ -2991,7 +2991,7 @@ pub fn _mm_mask_cvtpd_epi64(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtpd_epi64(k: __mmask8, a: __m128d) -> __m128i { _mm_mask_cvtpd_epi64(_mm_setzero_si128(), k, a) } @@ -3003,7 +3003,7 @@ pub fn _mm_maskz_cvtpd_epi64(k: __mmask8, a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtpd_epi64(a: __m256d) -> __m256i { _mm256_mask_cvtpd_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -3016,7 +3016,7 @@ pub fn _mm256_cvtpd_epi64(a: __m256d) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtpd_epi64(src: __m256i, k: __mmask8, a: __m256d) -> __m256i { unsafe { transmute(vcvtpd2qq_256(a.as_f64x4(), src.as_i64x4(), k)) } } @@ -3028,7 +3028,7 @@ pub fn _mm256_mask_cvtpd_epi64(src: __m256i, k: __mmask8, a: __m256d) -> __m256i #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtpd_epi64(k: __mmask8, a: __m256d) -> __m256i { _mm256_mask_cvtpd_epi64(_mm256_setzero_si256(), k, a) } @@ -3040,7 +3040,7 @@ pub fn _mm256_maskz_cvtpd_epi64(k: __mmask8, a: __m256d) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtpd_epi64(a: __m512d) -> __m512i { _mm512_mask_cvtpd_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -3053,7 +3053,7 @@ pub fn _mm512_cvtpd_epi64(a: __m512d) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtpd_epi64(src: __m512i, k: __mmask8, a: __m512d) -> __m512i { unsafe { transmute(vcvtpd2qq_512( @@ -3072,7 +3072,7 @@ pub fn _mm512_mask_cvtpd_epi64(src: __m512i, k: __mmask8, a: __m512d) -> __m512i #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtpd_epi64(k: __mmask8, a: __m512d) -> __m512i { _mm512_mask_cvtpd_epi64(_mm512_setzero_si512(), k, a) } @@ -3091,7 +3091,7 @@ pub fn _mm512_maskz_cvtpd_epi64(k: __mmask8, a: __m512d) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvt_roundps_epi64(a: __m256) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundps_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -3112,7 +3112,7 @@ pub fn _mm512_cvt_roundps_epi64(a: __m256) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvt_roundps_epi64( src: __m512i, k: __mmask8, @@ -3139,7 +3139,7 @@ pub fn _mm512_mask_cvt_roundps_epi64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvt_roundps_epi64(k: __mmask8, a: __m256) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundps_epi64::(_mm512_setzero_si512(), k, a) @@ -3152,7 +3152,7 @@ pub fn _mm512_maskz_cvt_roundps_epi64(k: __mmask8, a: __m25 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtps_epi64(a: __m128) -> __m128i { _mm_mask_cvtps_epi64(_mm_undefined_si128(), 0xff, a) } @@ -3165,7 +3165,7 @@ pub fn _mm_cvtps_epi64(a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtps_epi64(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvtps2qq_128(a.as_f32x4(), src.as_i64x2(), k)) } } @@ -3177,7 +3177,7 @@ pub fn _mm_mask_cvtps_epi64(src: __m128i, k: __mmask8, a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtps_epi64(k: __mmask8, a: __m128) -> __m128i { _mm_mask_cvtps_epi64(_mm_setzero_si128(), k, a) } @@ -3189,7 +3189,7 @@ pub fn _mm_maskz_cvtps_epi64(k: __mmask8, a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtps_epi64(a: __m128) -> __m256i { _mm256_mask_cvtps_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -3202,7 +3202,7 @@ pub fn _mm256_cvtps_epi64(a: __m128) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtps_epi64(src: __m256i, k: __mmask8, a: __m128) -> __m256i { unsafe { transmute(vcvtps2qq_256(a.as_f32x4(), src.as_i64x4(), k)) } } @@ -3214,7 +3214,7 @@ pub fn _mm256_mask_cvtps_epi64(src: __m256i, k: __mmask8, a: __m128) -> __m256i #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtps_epi64(k: __mmask8, a: __m128) -> __m256i { _mm256_mask_cvtps_epi64(_mm256_setzero_si256(), k, a) } @@ -3226,7 +3226,7 @@ pub fn _mm256_maskz_cvtps_epi64(k: __mmask8, a: __m128) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtps_epi64(a: __m256) -> __m512i { _mm512_mask_cvtps_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -3239,7 +3239,7 @@ pub fn _mm512_cvtps_epi64(a: __m256) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtps_epi64(src: __m512i, k: __mmask8, a: __m256) -> __m512i { unsafe { transmute(vcvtps2qq_512( @@ -3258,7 +3258,7 @@ pub fn _mm512_mask_cvtps_epi64(src: __m512i, k: __mmask8, a: __m256) -> __m512i #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtps_epi64(k: __mmask8, a: __m256) -> __m512i { _mm512_mask_cvtps_epi64(_mm512_setzero_si512(), k, a) } @@ -3277,7 +3277,7 @@ pub fn _mm512_maskz_cvtps_epi64(k: __mmask8, a: __m256) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvt_roundpd_epu64(a: __m512d) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -3298,7 +3298,7 @@ pub fn _mm512_cvt_roundpd_epu64(a: __m512d) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvt_roundpd_epu64( src: __m512i, k: __mmask8, @@ -3325,7 +3325,7 @@ pub fn _mm512_mask_cvt_roundpd_epu64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvt_roundpd_epu64(k: __mmask8, a: __m512d) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_epu64::(_mm512_setzero_si512(), k, a) @@ -3338,7 +3338,7 @@ pub fn _mm512_maskz_cvt_roundpd_epu64(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtpd_epu64(a: __m128d) -> __m128i { _mm_mask_cvtpd_epu64(_mm_undefined_si128(), 0xff, a) } @@ -3351,7 +3351,7 @@ pub fn _mm_cvtpd_epu64(a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtpd_epu64(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvtpd2uqq_128(a.as_f64x2(), src.as_u64x2(), k)) } } @@ -3363,7 +3363,7 @@ pub fn _mm_mask_cvtpd_epu64(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtpd_epu64(k: __mmask8, a: __m128d) -> __m128i { _mm_mask_cvtpd_epu64(_mm_setzero_si128(), k, a) } @@ -3375,7 +3375,7 @@ pub fn _mm_maskz_cvtpd_epu64(k: __mmask8, a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtpd_epu64(a: __m256d) -> __m256i { _mm256_mask_cvtpd_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -3388,7 +3388,7 @@ pub fn _mm256_cvtpd_epu64(a: __m256d) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtpd_epu64(src: __m256i, k: __mmask8, a: __m256d) -> __m256i { unsafe { transmute(vcvtpd2uqq_256(a.as_f64x4(), src.as_u64x4(), k)) } } @@ -3400,7 +3400,7 @@ pub fn _mm256_mask_cvtpd_epu64(src: __m256i, k: __mmask8, a: __m256d) -> __m256i #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtpd_epu64(k: __mmask8, a: __m256d) -> __m256i { _mm256_mask_cvtpd_epu64(_mm256_setzero_si256(), k, a) } @@ -3412,7 +3412,7 @@ pub fn _mm256_maskz_cvtpd_epu64(k: __mmask8, a: __m256d) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtpd_epu64(a: __m512d) -> __m512i { _mm512_mask_cvtpd_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -3425,7 +3425,7 @@ pub fn _mm512_cvtpd_epu64(a: __m512d) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtpd_epu64(src: __m512i, k: __mmask8, a: __m512d) -> __m512i { unsafe { transmute(vcvtpd2uqq_512( @@ -3444,7 +3444,7 @@ pub fn _mm512_mask_cvtpd_epu64(src: __m512i, k: __mmask8, a: __m512d) -> __m512i #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtpd_epu64(k: __mmask8, a: __m512d) -> __m512i { _mm512_mask_cvtpd_epu64(_mm512_setzero_si512(), k, a) } @@ -3463,7 +3463,7 @@ pub fn _mm512_maskz_cvtpd_epu64(k: __mmask8, a: __m512d) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvt_roundps_epu64(a: __m256) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundps_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -3484,7 +3484,7 @@ pub fn _mm512_cvt_roundps_epu64(a: __m256) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvt_roundps_epu64( src: __m512i, k: __mmask8, @@ -3511,7 +3511,7 @@ pub fn _mm512_mask_cvt_roundps_epu64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvt_roundps_epu64(k: __mmask8, a: __m256) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundps_epu64::(_mm512_setzero_si512(), k, a) @@ -3524,7 +3524,7 @@ pub fn _mm512_maskz_cvt_roundps_epu64(k: __mmask8, a: __m25 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtps_epu64(a: __m128) -> __m128i { _mm_mask_cvtps_epu64(_mm_undefined_si128(), 0xff, a) } @@ -3537,7 +3537,7 @@ pub fn _mm_cvtps_epu64(a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvtps_epu64(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvtps2uqq_128(a.as_f32x4(), src.as_u64x2(), k)) } } @@ -3549,7 +3549,7 @@ pub fn _mm_mask_cvtps_epu64(src: __m128i, k: __mmask8, a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvtps_epu64(k: __mmask8, a: __m128) -> __m128i { _mm_mask_cvtps_epu64(_mm_setzero_si128(), k, a) } @@ -3561,7 +3561,7 @@ pub fn _mm_maskz_cvtps_epu64(k: __mmask8, a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtps_epu64(a: __m128) -> __m256i { _mm256_mask_cvtps_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -3574,7 +3574,7 @@ pub fn _mm256_cvtps_epu64(a: __m128) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvtps_epu64(src: __m256i, k: __mmask8, a: __m128) -> __m256i { unsafe { transmute(vcvtps2uqq_256(a.as_f32x4(), src.as_u64x4(), k)) } } @@ -3586,7 +3586,7 @@ pub fn _mm256_mask_cvtps_epu64(src: __m256i, k: __mmask8, a: __m128) -> __m256i #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvtps_epu64(k: __mmask8, a: __m128) -> __m256i { _mm256_mask_cvtps_epu64(_mm256_setzero_si256(), k, a) } @@ -3598,7 +3598,7 @@ pub fn _mm256_maskz_cvtps_epu64(k: __mmask8, a: __m128) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtps_epu64(a: __m256) -> __m512i { _mm512_mask_cvtps_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -3611,7 +3611,7 @@ pub fn _mm512_cvtps_epu64(a: __m256) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtps_epu64(src: __m512i, k: __mmask8, a: __m256) -> __m512i { unsafe { transmute(vcvtps2uqq_512( @@ -3630,7 +3630,7 @@ pub fn _mm512_mask_cvtps_epu64(src: __m512i, k: __mmask8, a: __m256) -> __m512i #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvtps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtps_epu64(k: __mmask8, a: __m256) -> __m512i { _mm512_mask_cvtps_epu64(_mm512_setzero_si512(), k, a) } @@ -3644,7 +3644,7 @@ pub fn _mm512_maskz_cvtps_epu64(k: __mmask8, a: __m256) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2qq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtt_roundpd_epi64(a: __m512d) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundpd_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -3659,7 +3659,7 @@ pub fn _mm512_cvtt_roundpd_epi64(a: __m512d) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2qq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtt_roundpd_epi64( src: __m512i, k: __mmask8, @@ -3680,7 +3680,7 @@ pub fn _mm512_mask_cvtt_roundpd_epi64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2qq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtt_roundpd_epi64(k: __mmask8, a: __m512d) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundpd_epi64::(_mm512_setzero_si512(), k, a) @@ -3693,7 +3693,7 @@ pub fn _mm512_maskz_cvtt_roundpd_epi64(k: __mmask8, a: __m512d) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvttpd_epi64(a: __m128d) -> __m128i { _mm_mask_cvttpd_epi64(_mm_undefined_si128(), 0xff, a) } @@ -3706,7 +3706,7 @@ pub fn _mm_cvttpd_epi64(a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvttpd_epi64(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvttpd2qq_128(a.as_f64x2(), src.as_i64x2(), k)) } } @@ -3719,7 +3719,7 @@ pub fn _mm_mask_cvttpd_epi64(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvttpd_epi64(k: __mmask8, a: __m128d) -> __m128i { _mm_mask_cvttpd_epi64(_mm_setzero_si128(), k, a) } @@ -3731,7 +3731,7 @@ pub fn _mm_maskz_cvttpd_epi64(k: __mmask8, a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvttpd_epi64(a: __m256d) -> __m256i { _mm256_mask_cvttpd_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -3744,7 +3744,7 @@ pub fn _mm256_cvttpd_epi64(a: __m256d) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvttpd_epi64(src: __m256i, k: __mmask8, a: __m256d) -> __m256i { unsafe { transmute(vcvttpd2qq_256(a.as_f64x4(), src.as_i64x4(), k)) } } @@ -3757,7 +3757,7 @@ pub fn _mm256_mask_cvttpd_epi64(src: __m256i, k: __mmask8, a: __m256d) -> __m256 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvttpd_epi64(k: __mmask8, a: __m256d) -> __m256i { _mm256_mask_cvttpd_epi64(_mm256_setzero_si256(), k, a) } @@ -3769,7 +3769,7 @@ pub fn _mm256_maskz_cvttpd_epi64(k: __mmask8, a: __m256d) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvttpd_epi64(a: __m512d) -> __m512i { _mm512_mask_cvttpd_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -3782,7 +3782,7 @@ pub fn _mm512_cvttpd_epi64(a: __m512d) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvttpd_epi64(src: __m512i, k: __mmask8, a: __m512d) -> __m512i { unsafe { transmute(vcvttpd2qq_512( @@ -3802,7 +3802,7 @@ pub fn _mm512_mask_cvttpd_epi64(src: __m512i, k: __mmask8, a: __m512d) -> __m512 #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvttpd_epi64(k: __mmask8, a: __m512d) -> __m512i { _mm512_mask_cvttpd_epi64(_mm512_setzero_si512(), k, a) } @@ -3816,7 +3816,7 @@ pub fn _mm512_maskz_cvttpd_epi64(k: __mmask8, a: __m512d) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2qq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtt_roundps_epi64(a: __m256) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundps_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -3831,7 +3831,7 @@ pub fn _mm512_cvtt_roundps_epi64(a: __m256) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2qq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtt_roundps_epi64( src: __m512i, k: __mmask8, @@ -3852,7 +3852,7 @@ pub fn _mm512_mask_cvtt_roundps_epi64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2qq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtt_roundps_epi64(k: __mmask8, a: __m256) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundps_epi64::(_mm512_setzero_si512(), k, a) @@ -3865,7 +3865,7 @@ pub fn _mm512_maskz_cvtt_roundps_epi64(k: __mmask8, a: __m256) - #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvttps_epi64(a: __m128) -> __m128i { _mm_mask_cvttps_epi64(_mm_undefined_si128(), 0xff, a) } @@ -3878,7 +3878,7 @@ pub fn _mm_cvttps_epi64(a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvttps_epi64(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvttps2qq_128(a.as_f32x4(), src.as_i64x2(), k)) } } @@ -3891,7 +3891,7 @@ pub fn _mm_mask_cvttps_epi64(src: __m128i, k: __mmask8, a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvttps_epi64(k: __mmask8, a: __m128) -> __m128i { _mm_mask_cvttps_epi64(_mm_setzero_si128(), k, a) } @@ -3903,7 +3903,7 @@ pub fn _mm_maskz_cvttps_epi64(k: __mmask8, a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvttps_epi64(a: __m128) -> __m256i { _mm256_mask_cvttps_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -3916,7 +3916,7 @@ pub fn _mm256_cvttps_epi64(a: __m128) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvttps_epi64(src: __m256i, k: __mmask8, a: __m128) -> __m256i { unsafe { transmute(vcvttps2qq_256(a.as_f32x4(), src.as_i64x4(), k)) } } @@ -3929,7 +3929,7 @@ pub fn _mm256_mask_cvttps_epi64(src: __m256i, k: __mmask8, a: __m128) -> __m256i #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvttps_epi64(k: __mmask8, a: __m128) -> __m256i { _mm256_mask_cvttps_epi64(_mm256_setzero_si256(), k, a) } @@ -3941,7 +3941,7 @@ pub fn _mm256_maskz_cvttps_epi64(k: __mmask8, a: __m128) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvttps_epi64(a: __m256) -> __m512i { _mm512_mask_cvttps_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -3954,7 +3954,7 @@ pub fn _mm512_cvttps_epi64(a: __m256) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvttps_epi64(src: __m512i, k: __mmask8, a: __m256) -> __m512i { unsafe { transmute(vcvttps2qq_512( @@ -3974,7 +3974,7 @@ pub fn _mm512_mask_cvttps_epi64(src: __m512i, k: __mmask8, a: __m256) -> __m512i #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2qq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvttps_epi64(k: __mmask8, a: __m256) -> __m512i { _mm512_mask_cvttps_epi64(_mm512_setzero_si512(), k, a) } @@ -3988,7 +3988,7 @@ pub fn _mm512_maskz_cvttps_epi64(k: __mmask8, a: __m256) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2uqq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtt_roundpd_epu64(a: __m512d) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundpd_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -4003,7 +4003,7 @@ pub fn _mm512_cvtt_roundpd_epu64(a: __m512d) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2uqq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtt_roundpd_epu64( src: __m512i, k: __mmask8, @@ -4024,7 +4024,7 @@ pub fn _mm512_mask_cvtt_roundpd_epu64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2uqq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtt_roundpd_epu64(k: __mmask8, a: __m512d) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundpd_epu64::(_mm512_setzero_si512(), k, a) @@ -4037,7 +4037,7 @@ pub fn _mm512_maskz_cvtt_roundpd_epu64(k: __mmask8, a: __m512d) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvttpd_epu64(a: __m128d) -> __m128i { _mm_mask_cvttpd_epu64(_mm_undefined_si128(), 0xff, a) } @@ -4050,7 +4050,7 @@ pub fn _mm_cvttpd_epu64(a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvttpd_epu64(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvttpd2uqq_128(a.as_f64x2(), src.as_u64x2(), k)) } } @@ -4063,7 +4063,7 @@ pub fn _mm_mask_cvttpd_epu64(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvttpd_epu64(k: __mmask8, a: __m128d) -> __m128i { _mm_mask_cvttpd_epu64(_mm_setzero_si128(), k, a) } @@ -4075,7 +4075,7 @@ pub fn _mm_maskz_cvttpd_epu64(k: __mmask8, a: __m128d) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvttpd_epu64(a: __m256d) -> __m256i { _mm256_mask_cvttpd_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -4088,7 +4088,7 @@ pub fn _mm256_cvttpd_epu64(a: __m256d) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvttpd_epu64(src: __m256i, k: __mmask8, a: __m256d) -> __m256i { unsafe { transmute(vcvttpd2uqq_256(a.as_f64x4(), src.as_u64x4(), k)) } } @@ -4101,7 +4101,7 @@ pub fn _mm256_mask_cvttpd_epu64(src: __m256i, k: __mmask8, a: __m256d) -> __m256 #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvttpd_epu64(k: __mmask8, a: __m256d) -> __m256i { _mm256_mask_cvttpd_epu64(_mm256_setzero_si256(), k, a) } @@ -4113,7 +4113,7 @@ pub fn _mm256_maskz_cvttpd_epu64(k: __mmask8, a: __m256d) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvttpd_epu64(a: __m512d) -> __m512i { _mm512_mask_cvttpd_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -4126,7 +4126,7 @@ pub fn _mm512_cvttpd_epu64(a: __m512d) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvttpd_epu64(src: __m512i, k: __mmask8, a: __m512d) -> __m512i { unsafe { transmute(vcvttpd2uqq_512( @@ -4146,7 +4146,7 @@ pub fn _mm512_mask_cvttpd_epu64(src: __m512i, k: __mmask8, a: __m512d) -> __m512 #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttpd2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvttpd_epu64(k: __mmask8, a: __m512d) -> __m512i { _mm512_mask_cvttpd_epu64(_mm512_setzero_si512(), k, a) } @@ -4160,7 +4160,7 @@ pub fn _mm512_maskz_cvttpd_epu64(k: __mmask8, a: __m512d) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2uqq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtt_roundps_epu64(a: __m256) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundps_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -4175,7 +4175,7 @@ pub fn _mm512_cvtt_roundps_epu64(a: __m256) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2uqq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvtt_roundps_epu64( src: __m512i, k: __mmask8, @@ -4196,7 +4196,7 @@ pub fn _mm512_mask_cvtt_roundps_epu64( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2uqq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvtt_roundps_epu64(k: __mmask8, a: __m256) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundps_epu64::(_mm512_setzero_si512(), k, a) @@ -4209,7 +4209,7 @@ pub fn _mm512_maskz_cvtt_roundps_epu64(k: __mmask8, a: __m256) - #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvttps_epu64(a: __m128) -> __m128i { _mm_mask_cvttps_epu64(_mm_undefined_si128(), 0xff, a) } @@ -4222,7 +4222,7 @@ pub fn _mm_cvttps_epu64(a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_cvttps_epu64(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvttps2uqq_128(a.as_f32x4(), src.as_u64x2(), k)) } } @@ -4235,7 +4235,7 @@ pub fn _mm_mask_cvttps_epu64(src: __m128i, k: __mmask8, a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_cvttps_epu64(k: __mmask8, a: __m128) -> __m128i { _mm_mask_cvttps_epu64(_mm_setzero_si128(), k, a) } @@ -4247,7 +4247,7 @@ pub fn _mm_maskz_cvttps_epu64(k: __mmask8, a: __m128) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvttps_epu64(a: __m128) -> __m256i { _mm256_mask_cvttps_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -4260,7 +4260,7 @@ pub fn _mm256_cvttps_epu64(a: __m128) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_cvttps_epu64(src: __m256i, k: __mmask8, a: __m128) -> __m256i { unsafe { transmute(vcvttps2uqq_256(a.as_f32x4(), src.as_u64x4(), k)) } } @@ -4273,7 +4273,7 @@ pub fn _mm256_mask_cvttps_epu64(src: __m256i, k: __mmask8, a: __m128) -> __m256i #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_cvttps_epu64(k: __mmask8, a: __m128) -> __m256i { _mm256_mask_cvttps_epu64(_mm256_setzero_si256(), k, a) } @@ -4285,7 +4285,7 @@ pub fn _mm256_maskz_cvttps_epu64(k: __mmask8, a: __m128) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvttps_epu64(a: __m256) -> __m512i { _mm512_mask_cvttps_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -4298,7 +4298,7 @@ pub fn _mm512_cvttps_epu64(a: __m256) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_cvttps_epu64(src: __m512i, k: __mmask8, a: __m256) -> __m512i { unsafe { transmute(vcvttps2uqq_512( @@ -4318,7 +4318,7 @@ pub fn _mm512_mask_cvttps_epu64(src: __m512i, k: __mmask8, a: __m256) -> __m512i #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vcvttps2uqq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_cvttps_epu64(k: __mmask8, a: __m256) -> __m512i { _mm512_mask_cvttps_epu64(_mm512_setzero_si512(), k, a) } @@ -4332,7 +4332,7 @@ pub fn _mm512_maskz_cvttps_epu64(k: __mmask8, a: __m256) -> __m512i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mullo_epi64(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_mul(a.as_i64x2(), b.as_i64x2())) } } @@ -4345,7 +4345,7 @@ pub fn _mm_mullo_epi64(a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_mullo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let b = _mm_mullo_epi64(a, b).as_i64x2(); @@ -4361,7 +4361,7 @@ pub fn _mm_mask_mullo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) - #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_mullo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { let b = _mm_mullo_epi64(a, b).as_i64x2(); @@ -4376,7 +4376,7 @@ pub fn _mm_maskz_mullo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mullo_epi64(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_mul(a.as_i64x4(), b.as_i64x4())) } } @@ -4389,7 +4389,7 @@ pub fn _mm256_mullo_epi64(a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_mullo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { let b = _mm256_mullo_epi64(a, b).as_i64x4(); @@ -4405,7 +4405,7 @@ pub fn _mm256_mask_mullo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_mullo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { let b = _mm256_mullo_epi64(a, b).as_i64x4(); @@ -4420,7 +4420,7 @@ pub fn _mm256_maskz_mullo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mullo_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_mul(a.as_i64x8(), b.as_i64x8())) } } @@ -4433,7 +4433,7 @@ pub fn _mm512_mullo_epi64(a: __m512i, b: __m512i) -> __m512i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_mullo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { let b = _mm512_mullo_epi64(a, b).as_i64x8(); @@ -4449,7 +4449,7 @@ pub fn _mm512_mask_mullo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vpmullq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_mullo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { let b = _mm512_mullo_epi64(a, b).as_i64x8(); @@ -4464,7 +4464,7 @@ pub fn _mm512_maskz_mullo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtmask8_u32&ig_expand=1891) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _cvtmask8_u32(a: __mmask8) -> u32 { a as u32 } @@ -4474,7 +4474,7 @@ pub fn _cvtmask8_u32(a: __mmask8) -> u32 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtu32_mask8&ig_expand=2467) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _cvtu32_mask8(a: u32) -> __mmask8 { a as __mmask8 } @@ -4484,7 +4484,7 @@ pub fn _cvtu32_mask8(a: u32) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kadd_mask16&ig_expand=3903) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kadd_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { a + b } @@ -4494,7 +4494,7 @@ pub fn _kadd_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kadd_mask8&ig_expand=3906) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kadd_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { a + b } @@ -4504,7 +4504,7 @@ pub fn _kadd_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kand_mask8&ig_expand=3911) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kand_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { a & b } @@ -4514,7 +4514,7 @@ pub fn _kand_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kandn_mask8&ig_expand=3916) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kandn_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { _knot_mask8(a) & b } @@ -4524,7 +4524,7 @@ pub fn _kandn_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_knot_mask8&ig_expand=3922) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _knot_mask8(a: __mmask8) -> __mmask8 { a ^ 0b11111111 } @@ -4534,7 +4534,7 @@ pub fn _knot_mask8(a: __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kor_mask8&ig_expand=3927) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { a | b } @@ -4544,7 +4544,7 @@ pub fn _kor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxnor_mask8&ig_expand=3969) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kxnor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { _knot_mask8(_kxor_mask8(a, b)) } @@ -4554,7 +4554,7 @@ pub fn _kxnor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxor_mask8&ig_expand=3974) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kxor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { a ^ b } @@ -4565,7 +4565,7 @@ pub fn _kxor_mask8(a: __mmask8, b: __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortest_mask8_u8&ig_expand=3931) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _kortest_mask8_u8(a: __mmask8, b: __mmask8, all_ones: *mut u8) -> u8 { let tmp = _kor_mask8(a, b); *all_ones = (tmp == 0xff) as u8; @@ -4578,7 +4578,7 @@ pub unsafe fn _kortest_mask8_u8(a: __mmask8, b: __mmask8, all_ones: *mut u8) -> /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortestc_mask8_u8&ig_expand=3936) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kortestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 { (_kor_mask8(a, b) == 0xff) as u8 } @@ -4589,7 +4589,7 @@ pub fn _kortestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortestz_mask8_u8&ig_expand=3941) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kortestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 { (_kor_mask8(a, b) == 0) as u8 } @@ -4600,7 +4600,7 @@ pub fn _kortestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 { #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kshiftli_mask8(a: __mmask8) -> __mmask8 { a << COUNT } @@ -4611,7 +4611,7 @@ pub fn _kshiftli_mask8(a: __mmask8) -> __mmask8 { #[inline] #[target_feature(enable = "avx512dq")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kshiftri_mask8(a: __mmask8) -> __mmask8 { a >> COUNT } @@ -4623,7 +4623,7 @@ pub fn _kshiftri_mask8(a: __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktest_mask16_u8&ig_expand=3950) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _ktest_mask16_u8(a: __mmask16, b: __mmask16, and_not: *mut u8) -> u8 { *and_not = (_kandn_mask16(a, b) == 0) as u8; (_kand_mask16(a, b) == 0) as u8 @@ -4636,7 +4636,7 @@ pub unsafe fn _ktest_mask16_u8(a: __mmask16, b: __mmask16, and_not: *mut u8) -> /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktest_mask8_u8&ig_expand=3953) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _ktest_mask8_u8(a: __mmask8, b: __mmask8, and_not: *mut u8) -> u8 { *and_not = (_kandn_mask8(a, b) == 0) as u8; (_kand_mask8(a, b) == 0) as u8 @@ -4648,7 +4648,7 @@ pub unsafe fn _ktest_mask8_u8(a: __mmask8, b: __mmask8, and_not: *mut u8) -> u8 /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktestc_mask16_u8&ig_expand=3954) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _ktestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 { (_kandn_mask16(a, b) == 0) as u8 } @@ -4659,7 +4659,7 @@ pub fn _ktestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktestc_mask8_u8&ig_expand=3957) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _ktestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 { (_kandn_mask8(a, b) == 0) as u8 } @@ -4670,7 +4670,7 @@ pub fn _ktestc_mask8_u8(a: __mmask8, b: __mmask8) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktestz_mask16_u8&ig_expand=3958) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _ktestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 { (_kand_mask16(a, b) == 0) as u8 } @@ -4681,7 +4681,7 @@ pub fn _ktestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_ktestz_mask8_u8&ig_expand=3961) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _ktestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 { (_kand_mask8(a, b) == 0) as u8 } @@ -4691,7 +4691,7 @@ pub fn _ktestz_mask8_u8(a: __mmask8, b: __mmask8) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_load_mask8&ig_expand=3999) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _load_mask8(mem_addr: *const __mmask8) -> __mmask8 { *mem_addr } @@ -4701,7 +4701,7 @@ pub unsafe fn _load_mask8(mem_addr: *const __mmask8) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_store_mask8&ig_expand=6468) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _store_mask8(mem_addr: *mut __mmask8, a: __mmask8) { *mem_addr = a; } @@ -4712,7 +4712,7 @@ pub unsafe fn _store_mask8(mem_addr: *mut __mmask8, a: __mmask8) { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movepi32_mask&ig_expand=4612) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_movepi32_mask(a: __m128i) -> __mmask8 { let zero = _mm_setzero_si128(); _mm_cmplt_epi32_mask(a, zero) @@ -4724,7 +4724,7 @@ pub fn _mm_movepi32_mask(a: __m128i) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movepi32_mask&ig_expand=4613) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_movepi32_mask(a: __m256i) -> __mmask8 { let zero = _mm256_setzero_si256(); _mm256_cmplt_epi32_mask(a, zero) @@ -4736,7 +4736,7 @@ pub fn _mm256_movepi32_mask(a: __m256i) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movepi32_mask&ig_expand=4614) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_movepi32_mask(a: __m512i) -> __mmask16 { let zero = _mm512_setzero_si512(); _mm512_cmplt_epi32_mask(a, zero) @@ -4748,7 +4748,7 @@ pub fn _mm512_movepi32_mask(a: __m512i) -> __mmask16 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movepi64_mask&ig_expand=4615) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_movepi64_mask(a: __m128i) -> __mmask8 { let zero = _mm_setzero_si128(); _mm_cmplt_epi64_mask(a, zero) @@ -4760,7 +4760,7 @@ pub fn _mm_movepi64_mask(a: __m128i) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movepi64_mask&ig_expand=4616) #[inline] #[target_feature(enable = "avx512dq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_movepi64_mask(a: __m256i) -> __mmask8 { let zero = _mm256_setzero_si256(); _mm256_cmplt_epi64_mask(a, zero) @@ -4772,7 +4772,7 @@ pub fn _mm256_movepi64_mask(a: __m256i) -> __mmask8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movepi64_mask&ig_expand=4617) #[inline] #[target_feature(enable = "avx512dq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_movepi64_mask(a: __m512i) -> __mmask8 { let zero = _mm512_setzero_si512(); _mm512_cmplt_epi64_mask(a, zero) @@ -4785,7 +4785,7 @@ pub fn _mm512_movepi64_mask(a: __m512i) -> __mmask8 { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmovm2d))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_movm_epi32(k: __mmask8) -> __m128i { let ones = _mm_set1_epi32(-1); _mm_maskz_mov_epi32(k, ones) @@ -4798,7 +4798,7 @@ pub fn _mm_movm_epi32(k: __mmask8) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmovm2d))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_movm_epi32(k: __mmask8) -> __m256i { let ones = _mm256_set1_epi32(-1); _mm256_maskz_mov_epi32(k, ones) @@ -4811,7 +4811,7 @@ pub fn _mm256_movm_epi32(k: __mmask8) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vpmovm2d))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_movm_epi32(k: __mmask16) -> __m512i { let ones = _mm512_set1_epi32(-1); _mm512_maskz_mov_epi32(k, ones) @@ -4824,7 +4824,7 @@ pub fn _mm512_movm_epi32(k: __mmask16) -> __m512i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmovm2q))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_movm_epi64(k: __mmask8) -> __m128i { let ones = _mm_set1_epi64x(-1); _mm_maskz_mov_epi64(k, ones) @@ -4837,7 +4837,7 @@ pub fn _mm_movm_epi64(k: __mmask8) -> __m128i { #[inline] #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vpmovm2q))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_movm_epi64(k: __mmask8) -> __m256i { let ones = _mm256_set1_epi64x(-1); _mm256_maskz_mov_epi64(k, ones) @@ -4850,7 +4850,7 @@ pub fn _mm256_movm_epi64(k: __mmask8) -> __m256i { #[inline] #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vpmovm2q))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_movm_epi64(k: __mmask8) -> __m512i { let ones = _mm512_set1_epi64(-1); _mm512_maskz_mov_epi64(k, ones) @@ -4871,7 +4871,7 @@ pub fn _mm512_movm_epi64(k: __mmask8) -> __m512i { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_range_round_pd(a: __m512d, b: __m512d) -> __m512d { static_assert_uimm_bits!(IMM8, 4); static_assert_sae!(SAE); @@ -4892,7 +4892,7 @@ pub fn _mm512_range_round_pd(a: __m512d, b: __m #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_range_round_pd( src: __m512d, k: __mmask8, @@ -4927,7 +4927,7 @@ pub fn _mm512_mask_range_round_pd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_range_round_pd( k: __mmask8, a: __m512d, @@ -4950,7 +4950,7 @@ pub fn _mm512_maskz_range_round_pd( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_range_pd(a: __m128d, b: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 4); _mm_mask_range_pd::(_mm_setzero_pd(), 0xff, a, b) @@ -4969,7 +4969,7 @@ pub fn _mm_range_pd(a: __m128d, b: __m128d) -> __m128d { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_range_pd( src: __m128d, k: __mmask8, @@ -5001,7 +5001,7 @@ pub fn _mm_mask_range_pd( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_range_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 4); _mm_mask_range_pd::(_mm_setzero_pd(), k, a, b) @@ -5019,7 +5019,7 @@ pub fn _mm_maskz_range_pd(k: __mmask8, a: __m128d, b: __m128d) #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_range_pd(a: __m256d, b: __m256d) -> __m256d { static_assert_uimm_bits!(IMM8, 4); _mm256_mask_range_pd::(_mm256_setzero_pd(), 0xff, a, b) @@ -5038,7 +5038,7 @@ pub fn _mm256_range_pd(a: __m256d, b: __m256d) -> __m256d { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_range_pd( src: __m256d, k: __mmask8, @@ -5070,7 +5070,7 @@ pub fn _mm256_mask_range_pd( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_range_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { static_assert_uimm_bits!(IMM8, 4); _mm256_mask_range_pd::(_mm256_setzero_pd(), k, a, b) @@ -5088,7 +5088,7 @@ pub fn _mm256_maskz_range_pd(k: __mmask8, a: __m256d, b: __m256 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_range_pd(a: __m512d, b: __m512d) -> __m512d { static_assert_uimm_bits!(IMM8, 4); _mm512_mask_range_pd::(_mm512_setzero_pd(), 0xff, a, b) @@ -5107,7 +5107,7 @@ pub fn _mm512_range_pd(a: __m512d, b: __m512d) -> __m512d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_range_pd( src: __m512d, k: __mmask8, @@ -5140,7 +5140,7 @@ pub fn _mm512_mask_range_pd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangepd, IMM8 = 5))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_range_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { static_assert_uimm_bits!(IMM8, 4); _mm512_mask_range_pd::(_mm512_setzero_pd(), k, a, b) @@ -5159,7 +5159,7 @@ pub fn _mm512_maskz_range_pd(k: __mmask8, a: __m512d, b: __m512 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_range_round_ps(a: __m512, b: __m512) -> __m512 { static_assert_uimm_bits!(IMM8, 4); static_assert_sae!(SAE); @@ -5179,7 +5179,7 @@ pub fn _mm512_range_round_ps(a: __m512, b: __m5 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_range_round_ps( src: __m512, k: __mmask16, @@ -5213,7 +5213,7 @@ pub fn _mm512_mask_range_round_ps( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_range_round_ps( k: __mmask16, a: __m512, @@ -5236,7 +5236,7 @@ pub fn _mm512_maskz_range_round_ps( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_range_ps(a: __m128, b: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 4); _mm_mask_range_ps::(_mm_setzero_ps(), 0xff, a, b) @@ -5255,7 +5255,7 @@ pub fn _mm_range_ps(a: __m128, b: __m128) -> __m128 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_range_ps( src: __m128, k: __mmask8, @@ -5287,7 +5287,7 @@ pub fn _mm_mask_range_ps( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_range_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 4); _mm_mask_range_ps::(_mm_setzero_ps(), k, a, b) @@ -5305,7 +5305,7 @@ pub fn _mm_maskz_range_ps(k: __mmask8, a: __m128, b: __m128) -> #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_range_ps(a: __m256, b: __m256) -> __m256 { static_assert_uimm_bits!(IMM8, 4); _mm256_mask_range_ps::(_mm256_setzero_ps(), 0xff, a, b) @@ -5324,7 +5324,7 @@ pub fn _mm256_range_ps(a: __m256, b: __m256) -> __m256 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_range_ps( src: __m256, k: __mmask8, @@ -5356,7 +5356,7 @@ pub fn _mm256_mask_range_ps( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_range_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { static_assert_uimm_bits!(IMM8, 4); _mm256_mask_range_ps::(_mm256_setzero_ps(), k, a, b) @@ -5374,7 +5374,7 @@ pub fn _mm256_maskz_range_ps(k: __mmask8, a: __m256, b: __m256) #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_range_ps(a: __m512, b: __m512) -> __m512 { static_assert_uimm_bits!(IMM8, 4); _mm512_mask_range_ps::(_mm512_setzero_ps(), 0xffff, a, b) @@ -5393,7 +5393,7 @@ pub fn _mm512_range_ps(a: __m512, b: __m512) -> __m512 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_range_ps( src: __m512, k: __mmask16, @@ -5426,7 +5426,7 @@ pub fn _mm512_mask_range_ps( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangeps, IMM8 = 5))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_range_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { static_assert_uimm_bits!(IMM8, 4); _mm512_mask_range_ps::(_mm512_setzero_ps(), k, a, b) @@ -5446,7 +5446,7 @@ pub fn _mm512_maskz_range_ps(k: __mmask16, a: __m512, b: __m512 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangesd, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_range_round_sd(a: __m128d, b: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 4); static_assert_sae!(SAE); @@ -5468,7 +5468,7 @@ pub fn _mm_range_round_sd(a: __m128d, b: __m128 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangesd, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_range_round_sd( src: __m128d, k: __mmask8, @@ -5504,7 +5504,7 @@ pub fn _mm_mask_range_round_sd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangesd, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_range_round_sd( k: __mmask8, a: __m128d, @@ -5529,7 +5529,7 @@ pub fn _mm_maskz_range_round_sd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangesd, IMM8 = 5))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_range_sd( src: __m128d, k: __mmask8, @@ -5563,7 +5563,7 @@ pub fn _mm_mask_range_sd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangesd, IMM8 = 5))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_range_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 4); _mm_mask_range_sd::(_mm_setzero_pd(), k, a, b) @@ -5583,7 +5583,7 @@ pub fn _mm_maskz_range_sd(k: __mmask8, a: __m128d, b: __m128d) #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangess, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_range_round_ss(a: __m128, b: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 4); static_assert_sae!(SAE); @@ -5605,7 +5605,7 @@ pub fn _mm_range_round_ss(a: __m128, b: __m128) #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangess, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_range_round_ss( src: __m128, k: __mmask8, @@ -5641,7 +5641,7 @@ pub fn _mm_mask_range_round_ss( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangess, IMM8 = 5, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_range_round_ss( k: __mmask8, a: __m128, @@ -5666,7 +5666,7 @@ pub fn _mm_maskz_range_round_ss( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangess, IMM8 = 5))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_range_ss( src: __m128, k: __mmask8, @@ -5700,7 +5700,7 @@ pub fn _mm_mask_range_ss( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vrangess, IMM8 = 5))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_range_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 4); _mm_mask_range_ss::(_mm_setzero_ps(), k, a, b) @@ -5725,7 +5725,7 @@ pub fn _mm_maskz_range_ss(k: __mmask8, a: __m128, b: __m128) -> #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_round_pd(a: __m512d) -> __m512d { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -5750,7 +5750,7 @@ pub fn _mm512_reduce_round_pd(a: __m512d) -> __ #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_round_pd( src: __m512d, k: __mmask8, @@ -5781,7 +5781,7 @@ pub fn _mm512_mask_reduce_round_pd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_reduce_round_pd( k: __mmask8, a: __m512d, @@ -5806,7 +5806,7 @@ pub fn _mm512_maskz_reduce_round_pd( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_pd(a: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_pd::(_mm_undefined_pd(), 0xff, a) @@ -5828,7 +5828,7 @@ pub fn _mm_reduce_pd(a: __m128d) -> __m128d { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -5852,7 +5852,7 @@ pub fn _mm_mask_reduce_pd(src: __m128d, k: __mmask8, a: __m128d #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_reduce_pd(k: __mmask8, a: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_pd::(_mm_setzero_pd(), k, a) @@ -5873,7 +5873,7 @@ pub fn _mm_maskz_reduce_pd(k: __mmask8, a: __m128d) -> __m128d #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_pd(a: __m256d) -> __m256d { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_pd::(_mm256_undefined_pd(), 0xff, a) @@ -5895,7 +5895,7 @@ pub fn _mm256_reduce_pd(a: __m256d) -> __m256d { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -5919,7 +5919,7 @@ pub fn _mm256_mask_reduce_pd(src: __m256d, k: __mmask8, a: __m2 #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_reduce_pd(k: __mmask8, a: __m256d) -> __m256d { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_pd::(_mm256_setzero_pd(), k, a) @@ -5940,7 +5940,7 @@ pub fn _mm256_maskz_reduce_pd(k: __mmask8, a: __m256d) -> __m25 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_pd(a: __m512d) -> __m512d { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_pd::(_mm512_undefined_pd(), 0xff, a) @@ -5962,7 +5962,7 @@ pub fn _mm512_reduce_pd(a: __m512d) -> __m512d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -5992,7 +5992,7 @@ pub fn _mm512_mask_reduce_pd(src: __m512d, k: __mmask8, a: __m5 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducepd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_reduce_pd(k: __mmask8, a: __m512d) -> __m512d { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_pd::(_mm512_setzero_pd(), k, a) @@ -6015,7 +6015,7 @@ pub fn _mm512_maskz_reduce_pd(k: __mmask8, a: __m512d) -> __m51 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_round_ps(a: __m512) -> __m512 { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -6040,7 +6040,7 @@ pub fn _mm512_reduce_round_ps(a: __m512) -> __m #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_round_ps( src: __m512, k: __mmask16, @@ -6071,7 +6071,7 @@ pub fn _mm512_mask_reduce_round_ps( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_reduce_round_ps( k: __mmask16, a: __m512, @@ -6096,7 +6096,7 @@ pub fn _mm512_maskz_reduce_round_ps( #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_ps(a: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ps::(_mm_undefined_ps(), 0xff, a) @@ -6118,7 +6118,7 @@ pub fn _mm_reduce_ps(a: __m128) -> __m128 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6142,7 +6142,7 @@ pub fn _mm_mask_reduce_ps(src: __m128, k: __mmask8, a: __m128) #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_reduce_ps(k: __mmask8, a: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ps::(_mm_setzero_ps(), k, a) @@ -6163,7 +6163,7 @@ pub fn _mm_maskz_reduce_ps(k: __mmask8, a: __m128) -> __m128 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_reduce_ps(a: __m256) -> __m256 { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_ps::(_mm256_undefined_ps(), 0xff, a) @@ -6185,7 +6185,7 @@ pub fn _mm256_reduce_ps(a: __m256) -> __m256 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_reduce_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6209,7 +6209,7 @@ pub fn _mm256_mask_reduce_ps(src: __m256, k: __mmask8, a: __m25 #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_reduce_ps(k: __mmask8, a: __m256) -> __m256 { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_ps::(_mm256_setzero_ps(), k, a) @@ -6230,7 +6230,7 @@ pub fn _mm256_maskz_reduce_ps(k: __mmask8, a: __m256) -> __m256 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_ps(a: __m512) -> __m512 { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_ps::(_mm512_undefined_ps(), 0xffff, a) @@ -6252,7 +6252,7 @@ pub fn _mm512_reduce_ps(a: __m512) -> __m512 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6282,7 +6282,7 @@ pub fn _mm512_mask_reduce_ps(src: __m512, k: __mmask16, a: __m5 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreduceps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_reduce_ps(k: __mmask16, a: __m512) -> __m512 { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_ps::(_mm512_setzero_ps(), k, a) @@ -6306,7 +6306,7 @@ pub fn _mm512_maskz_reduce_ps(k: __mmask16, a: __m512) -> __m51 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducesd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_round_sd(a: __m128d, b: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -6332,7 +6332,7 @@ pub fn _mm_reduce_round_sd(a: __m128d, b: __m12 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducesd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_round_sd( src: __m128d, k: __mmask8, @@ -6372,7 +6372,7 @@ pub fn _mm_mask_reduce_round_sd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducesd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_reduce_round_sd( k: __mmask8, a: __m128d, @@ -6400,7 +6400,7 @@ pub fn _mm_maskz_reduce_round_sd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducesd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_sd(a: __m128d, b: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_sd::(_mm_undefined_pd(), 0xff, a, b) @@ -6423,7 +6423,7 @@ pub fn _mm_reduce_sd(a: __m128d, b: __m128d) -> __m128d { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducesd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_sd( src: __m128d, k: __mmask8, @@ -6460,7 +6460,7 @@ pub fn _mm_mask_reduce_sd( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducesd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_reduce_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_sd::(_mm_setzero_pd(), k, a, b) @@ -6485,7 +6485,7 @@ pub fn _mm_maskz_reduce_sd(k: __mmask8, a: __m128d, b: __m128d) #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducess, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_round_ss(a: __m128, b: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -6511,7 +6511,7 @@ pub fn _mm_reduce_round_ss(a: __m128, b: __m128 #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducess, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_round_ss( src: __m128, k: __mmask8, @@ -6551,7 +6551,7 @@ pub fn _mm_mask_reduce_round_ss( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducess, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_reduce_round_ss( k: __mmask8, a: __m128, @@ -6579,7 +6579,7 @@ pub fn _mm_maskz_reduce_round_ss( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducess, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_reduce_ss(a: __m128, b: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ss::(_mm_undefined_ps(), 0xff, a, b) @@ -6602,7 +6602,7 @@ pub fn _mm_reduce_ss(a: __m128, b: __m128) -> __m128 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducess, IMM8 = 0))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_reduce_ss( src: __m128, k: __mmask8, @@ -6639,7 +6639,7 @@ pub fn _mm_mask_reduce_ss( #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vreducess, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_maskz_reduce_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ss::(_mm_setzero_ps(), k, a, b) @@ -6665,7 +6665,7 @@ pub fn _mm_maskz_reduce_ss(k: __mmask8, a: __m128, b: __m128) - #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vfpclasspd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_fpclass_pd_mask(a: __m128d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); _mm_mask_fpclass_pd_mask::(0xff, a) @@ -6690,7 +6690,7 @@ pub fn _mm_fpclass_pd_mask(a: __m128d) -> __mmask8 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vfpclasspd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_fpclass_pd_mask(k1: __mmask8, a: __m128d) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6716,7 +6716,7 @@ pub fn _mm_mask_fpclass_pd_mask(k1: __mmask8, a: __m128d) -> __ #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vfpclasspd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_fpclass_pd_mask(a: __m256d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_fpclass_pd_mask::(0xff, a) @@ -6741,7 +6741,7 @@ pub fn _mm256_fpclass_pd_mask(a: __m256d) -> __mmask8 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vfpclasspd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_fpclass_pd_mask(k1: __mmask8, a: __m256d) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6767,7 +6767,7 @@ pub fn _mm256_mask_fpclass_pd_mask(k1: __mmask8, a: __m256d) -> #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vfpclasspd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_fpclass_pd_mask(a: __m512d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_fpclass_pd_mask::(0xff, a) @@ -6792,7 +6792,7 @@ pub fn _mm512_fpclass_pd_mask(a: __m512d) -> __mmask8 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vfpclasspd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_fpclass_pd_mask(k1: __mmask8, a: __m512d) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6818,7 +6818,7 @@ pub fn _mm512_mask_fpclass_pd_mask(k1: __mmask8, a: __m512d) -> #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassps, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_fpclass_ps_mask(a: __m128) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); _mm_mask_fpclass_ps_mask::(0xff, a) @@ -6843,7 +6843,7 @@ pub fn _mm_fpclass_ps_mask(a: __m128) -> __mmask8 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_fpclass_ps_mask(k1: __mmask8, a: __m128) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6869,7 +6869,7 @@ pub fn _mm_mask_fpclass_ps_mask(k1: __mmask8, a: __m128) -> __m #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassps, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_fpclass_ps_mask(a: __m256) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_fpclass_ps_mask::(0xff, a) @@ -6894,7 +6894,7 @@ pub fn _mm256_fpclass_ps_mask(a: __m256) -> __mmask8 { #[target_feature(enable = "avx512dq,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_fpclass_ps_mask(k1: __mmask8, a: __m256) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6920,7 +6920,7 @@ pub fn _mm256_mask_fpclass_ps_mask(k1: __mmask8, a: __m256) -> #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vfpclassps, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_fpclass_ps_mask(a: __m512) -> __mmask16 { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_fpclass_ps_mask::(0xffff, a) @@ -6945,7 +6945,7 @@ pub fn _mm512_fpclass_ps_mask(a: __m512) -> __mmask16 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vfpclassps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_fpclass_ps_mask(k1: __mmask16, a: __m512) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -6971,7 +6971,7 @@ pub fn _mm512_mask_fpclass_ps_mask(k1: __mmask16, a: __m512) -> #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vfpclasssd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_fpclass_sd_mask(a: __m128d) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); _mm_mask_fpclass_sd_mask::(0xff, a) @@ -6996,7 +6996,7 @@ pub fn _mm_fpclass_sd_mask(a: __m128d) -> __mmask8 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vfpclasssd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_fpclass_sd_mask(k1: __mmask8, a: __m128d) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -7022,7 +7022,7 @@ pub fn _mm_mask_fpclass_sd_mask(k1: __mmask8, a: __m128d) -> __ #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vfpclassss, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_fpclass_ss_mask(a: __m128) -> __mmask8 { static_assert_uimm_bits!(IMM8, 8); _mm_mask_fpclass_ss_mask::(0xff, a) @@ -7047,7 +7047,7 @@ pub fn _mm_fpclass_ss_mask(a: __m128) -> __mmask8 { #[target_feature(enable = "avx512dq")] #[cfg_attr(test, assert_instr(vfpclassss, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_mask_fpclass_ss_mask(k1: __mmask8, a: __m128) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); diff --git a/crates/core_arch/src/x86/avx512f.rs b/crates/core_arch/src/x86/avx512f.rs index e46086c087..dd22461676 100644 --- a/crates/core_arch/src/x86/avx512f.rs +++ b/crates/core_arch/src/x86/avx512f.rs @@ -15,7 +15,7 @@ use stdarch_test::assert_instr; /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_abs_epi32&expand=39) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsd))] pub fn _mm512_abs_epi32(a: __m512i) -> __m512i { unsafe { @@ -32,7 +32,7 @@ pub fn _mm512_abs_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_abs_epi32&expand=40) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsd))] pub fn _mm512_mask_abs_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -48,7 +48,7 @@ pub fn _mm512_mask_abs_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_abs_epi32&expand=41) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsd))] pub fn _mm512_maskz_abs_epi32(k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -62,7 +62,7 @@ pub fn _mm512_maskz_abs_epi32(k: __mmask16, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_abs_epi32&expand=37) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsd))] pub fn _mm256_mask_abs_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -76,7 +76,7 @@ pub fn _mm256_mask_abs_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_abs_epi32&expand=38) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsd))] pub fn _mm256_maskz_abs_epi32(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -90,7 +90,7 @@ pub fn _mm256_maskz_abs_epi32(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_abs_epi32&expand=34) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsd))] pub fn _mm_mask_abs_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -104,7 +104,7 @@ pub fn _mm_mask_abs_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_abs_epi32&expand=35) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsd))] pub fn _mm_maskz_abs_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -118,7 +118,7 @@ pub fn _mm_maskz_abs_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_abs_epi64&expand=48) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm512_abs_epi64(a: __m512i) -> __m512i { unsafe { @@ -133,7 +133,7 @@ pub fn _mm512_abs_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_abs_epi64&expand=49) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm512_mask_abs_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -147,7 +147,7 @@ pub fn _mm512_mask_abs_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_abs_epi64&expand=50) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm512_maskz_abs_epi64(k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -161,7 +161,7 @@ pub fn _mm512_maskz_abs_epi64(k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_abs_epi64&expand=45) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm256_abs_epi64(a: __m256i) -> __m256i { unsafe { @@ -176,7 +176,7 @@ pub fn _mm256_abs_epi64(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_abs_epi64&expand=46) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm256_mask_abs_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -190,7 +190,7 @@ pub fn _mm256_mask_abs_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_abs_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm256_maskz_abs_epi64(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -204,7 +204,7 @@ pub fn _mm256_maskz_abs_epi64(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_abs_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm_abs_epi64(a: __m128i) -> __m128i { unsafe { @@ -219,7 +219,7 @@ pub fn _mm_abs_epi64(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_abs_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm_mask_abs_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -233,7 +233,7 @@ pub fn _mm_mask_abs_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_abs_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpabsq))] pub fn _mm_maskz_abs_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -247,7 +247,7 @@ pub fn _mm_maskz_abs_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_abs_ps&expand=65) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandd))] pub fn _mm512_abs_ps(v2: __m512) -> __m512 { unsafe { simd_fabs(v2) } @@ -258,7 +258,7 @@ pub fn _mm512_abs_ps(v2: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_abs_ps&expand=66) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandd))] pub fn _mm512_mask_abs_ps(src: __m512, k: __mmask16, v2: __m512) -> __m512 { unsafe { simd_select_bitmask(k, simd_fabs(v2), src) } @@ -269,7 +269,7 @@ pub fn _mm512_mask_abs_ps(src: __m512, k: __mmask16, v2: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_abs_pd&expand=60) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm512_abs_pd(v2: __m512d) -> __m512d { unsafe { simd_fabs(v2) } @@ -280,7 +280,7 @@ pub fn _mm512_abs_pd(v2: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_abs_pd&expand=61) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm512_mask_abs_pd(src: __m512d, k: __mmask8, v2: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, simd_fabs(v2), src) } @@ -291,7 +291,7 @@ pub fn _mm512_mask_abs_pd(src: __m512d, k: __mmask8, v2: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mov_epi32&expand=3801) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] pub fn _mm512_mask_mov_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -305,7 +305,7 @@ pub fn _mm512_mask_mov_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mov_epi32&expand=3802) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] pub fn _mm512_maskz_mov_epi32(k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -319,7 +319,7 @@ pub fn _mm512_maskz_mov_epi32(k: __mmask16, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mov_epi32&expand=3799) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] pub fn _mm256_mask_mov_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -333,7 +333,7 @@ pub fn _mm256_mask_mov_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mov_epi32&expand=3800) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] pub fn _mm256_maskz_mov_epi32(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -347,7 +347,7 @@ pub fn _mm256_maskz_mov_epi32(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mov_epi32&expand=3797) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] pub fn _mm_mask_mov_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -361,7 +361,7 @@ pub fn _mm_mask_mov_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mov_epi32&expand=3798) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] pub fn _mm_maskz_mov_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -375,7 +375,7 @@ pub fn _mm_maskz_mov_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mov_epi64&expand=3807) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] pub fn _mm512_mask_mov_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -389,7 +389,7 @@ pub fn _mm512_mask_mov_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mov_epi64&expand=3808) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] pub fn _mm512_maskz_mov_epi64(k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -403,7 +403,7 @@ pub fn _mm512_maskz_mov_epi64(k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mov_epi64&expand=3805) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] pub fn _mm256_mask_mov_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -417,7 +417,7 @@ pub fn _mm256_mask_mov_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mov_epi64&expand=3806) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] pub fn _mm256_maskz_mov_epi64(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -431,7 +431,7 @@ pub fn _mm256_maskz_mov_epi64(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mov_epi64&expand=3803) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] pub fn _mm_mask_mov_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -445,7 +445,7 @@ pub fn _mm_mask_mov_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mov_epi64&expand=3804) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] pub fn _mm_maskz_mov_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -459,7 +459,7 @@ pub fn _mm_maskz_mov_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mov_ps&expand=3825) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] pub fn _mm512_mask_mov_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { @@ -473,7 +473,7 @@ pub fn _mm512_mask_mov_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mov_ps&expand=3826) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] pub fn _mm512_maskz_mov_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { @@ -487,7 +487,7 @@ pub fn _mm512_maskz_mov_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mov_ps&expand=3823) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] pub fn _mm256_mask_mov_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { @@ -501,7 +501,7 @@ pub fn _mm256_mask_mov_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mov_ps&expand=3824) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] pub fn _mm256_maskz_mov_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { @@ -515,7 +515,7 @@ pub fn _mm256_maskz_mov_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mov_ps&expand=3821) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] pub fn _mm_mask_mov_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { @@ -529,7 +529,7 @@ pub fn _mm_mask_mov_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mov_ps&expand=3822) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] pub fn _mm_maskz_mov_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { @@ -543,7 +543,7 @@ pub fn _mm_maskz_mov_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mov_pd&expand=3819) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] pub fn _mm512_mask_mov_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { @@ -557,7 +557,7 @@ pub fn _mm512_mask_mov_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mov_pd&expand=3820) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] pub fn _mm512_maskz_mov_pd(k: __mmask8, a: __m512d) -> __m512d { unsafe { @@ -571,7 +571,7 @@ pub fn _mm512_maskz_mov_pd(k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mov_pd&expand=3817) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] pub fn _mm256_mask_mov_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { @@ -585,7 +585,7 @@ pub fn _mm256_mask_mov_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mov_pd&expand=3818) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] pub fn _mm256_maskz_mov_pd(k: __mmask8, a: __m256d) -> __m256d { unsafe { @@ -599,7 +599,7 @@ pub fn _mm256_maskz_mov_pd(k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mov_pd&expand=3815) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] pub fn _mm_mask_mov_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { @@ -613,7 +613,7 @@ pub fn _mm_mask_mov_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mov_pd&expand=3816) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] pub fn _mm_maskz_mov_pd(k: __mmask8, a: __m128d) -> __m128d { unsafe { @@ -627,7 +627,7 @@ pub fn _mm_maskz_mov_pd(k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_epi32&expand=100) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddd))] pub fn _mm512_add_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_add(a.as_i32x16(), b.as_i32x16())) } @@ -638,7 +638,7 @@ pub fn _mm512_add_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_epi32&expand=101) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddd))] pub fn _mm512_mask_add_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -652,7 +652,7 @@ pub fn _mm512_mask_add_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_epi32&expand=102) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddd))] pub fn _mm512_maskz_add_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -666,7 +666,7 @@ pub fn _mm512_maskz_add_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_add_epi32&expand=98) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddd))] pub fn _mm256_mask_add_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -680,7 +680,7 @@ pub fn _mm256_mask_add_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_add_epi32&expand=99) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddd))] pub fn _mm256_maskz_add_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -694,7 +694,7 @@ pub fn _mm256_maskz_add_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_add_epi32&expand=95) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddd))] pub fn _mm_mask_add_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -708,7 +708,7 @@ pub fn _mm_mask_add_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_epi32&expand=96) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddd))] pub fn _mm_maskz_add_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -722,7 +722,7 @@ pub fn _mm_maskz_add_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_epi64&expand=109) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddq))] pub fn _mm512_add_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_add(a.as_i64x8(), b.as_i64x8())) } @@ -733,7 +733,7 @@ pub fn _mm512_add_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_epi64&expand=110) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddq))] pub fn _mm512_mask_add_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -747,7 +747,7 @@ pub fn _mm512_mask_add_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_epi64&expand=111) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddq))] pub fn _mm512_maskz_add_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -761,7 +761,7 @@ pub fn _mm512_maskz_add_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_add_epi64&expand=107) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddq))] pub fn _mm256_mask_add_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -775,7 +775,7 @@ pub fn _mm256_mask_add_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_add_epi64&expand=108) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddq))] pub fn _mm256_maskz_add_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -789,7 +789,7 @@ pub fn _mm256_maskz_add_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_add_epi64&expand=104) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddq))] pub fn _mm_mask_add_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -803,7 +803,7 @@ pub fn _mm_mask_add_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_epi64&expand=105) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpaddq))] pub fn _mm_maskz_add_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -817,7 +817,7 @@ pub fn _mm_maskz_add_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_ps&expand=139) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps))] pub fn _mm512_add_ps(a: __m512, b: __m512) -> __m512 { unsafe { transmute(simd_add(a.as_f32x16(), b.as_f32x16())) } @@ -828,7 +828,7 @@ pub fn _mm512_add_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_ps&expand=140) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps))] pub fn _mm512_mask_add_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -842,7 +842,7 @@ pub fn _mm512_mask_add_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_ps&expand=141) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps))] pub fn _mm512_maskz_add_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -856,7 +856,7 @@ pub fn _mm512_maskz_add_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_add_ps&expand=137) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps))] pub fn _mm256_mask_add_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -870,7 +870,7 @@ pub fn _mm256_mask_add_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_add_ps&expand=138) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps))] pub fn _mm256_maskz_add_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -884,7 +884,7 @@ pub fn _mm256_maskz_add_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_add_ps&expand=134) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps))] pub fn _mm_mask_add_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -898,7 +898,7 @@ pub fn _mm_mask_add_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_ps&expand=135) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps))] pub fn _mm_maskz_add_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -912,7 +912,7 @@ pub fn _mm_maskz_add_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_pd&expand=127) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd))] pub fn _mm512_add_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(simd_add(a.as_f64x8(), b.as_f64x8())) } @@ -923,7 +923,7 @@ pub fn _mm512_add_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_pd&expand=128) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd))] pub fn _mm512_mask_add_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -937,7 +937,7 @@ pub fn _mm512_mask_add_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_pd&expand=129) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd))] pub fn _mm512_maskz_add_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -951,7 +951,7 @@ pub fn _mm512_maskz_add_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_add_pd&expand=125) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd))] pub fn _mm256_mask_add_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -965,7 +965,7 @@ pub fn _mm256_mask_add_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_add_pd&expand=126) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd))] pub fn _mm256_maskz_add_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -979,7 +979,7 @@ pub fn _mm256_maskz_add_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_add_pd&expand=122) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd))] pub fn _mm_mask_add_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -993,7 +993,7 @@ pub fn _mm_mask_add_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_pd&expand=123) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd))] pub fn _mm_maskz_add_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -1007,7 +1007,7 @@ pub fn _mm_maskz_add_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_epi32&expand=5694) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubd))] pub fn _mm512_sub_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_sub(a.as_i32x16(), b.as_i32x16())) } @@ -1018,7 +1018,7 @@ pub fn _mm512_sub_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_epi32&expand=5692) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubd))] pub fn _mm512_mask_sub_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1032,7 +1032,7 @@ pub fn _mm512_mask_sub_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_epi32&expand=5693) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubd))] pub fn _mm512_maskz_sub_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1046,7 +1046,7 @@ pub fn _mm512_maskz_sub_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sub_epi32&expand=5689) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubd))] pub fn _mm256_mask_sub_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1060,7 +1060,7 @@ pub fn _mm256_mask_sub_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sub_epi32&expand=5690) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubd))] pub fn _mm256_maskz_sub_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1074,7 +1074,7 @@ pub fn _mm256_maskz_sub_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sub_epi32&expand=5686) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubd))] pub fn _mm_mask_sub_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1088,7 +1088,7 @@ pub fn _mm_mask_sub_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sub_epi32&expand=5687) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubd))] pub fn _mm_maskz_sub_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1102,7 +1102,7 @@ pub fn _mm_maskz_sub_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_epi64&expand=5703) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubq))] pub fn _mm512_sub_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_sub(a.as_i64x8(), b.as_i64x8())) } @@ -1113,7 +1113,7 @@ pub fn _mm512_sub_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_epi64&expand=5701) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubq))] pub fn _mm512_mask_sub_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1127,7 +1127,7 @@ pub fn _mm512_mask_sub_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_epi64&expand=5702) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubq))] pub fn _mm512_maskz_sub_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1141,7 +1141,7 @@ pub fn _mm512_maskz_sub_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sub_epi64&expand=5698) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubq))] pub fn _mm256_mask_sub_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1155,7 +1155,7 @@ pub fn _mm256_mask_sub_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sub_epi64&expand=5699) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubq))] pub fn _mm256_maskz_sub_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1169,7 +1169,7 @@ pub fn _mm256_maskz_sub_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sub_epi64&expand=5695) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubq))] pub fn _mm_mask_sub_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1183,7 +1183,7 @@ pub fn _mm_mask_sub_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sub_epi64&expand=5696) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsubq))] pub fn _mm_maskz_sub_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1197,7 +1197,7 @@ pub fn _mm_maskz_sub_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_ps&expand=5733) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps))] pub fn _mm512_sub_ps(a: __m512, b: __m512) -> __m512 { unsafe { transmute(simd_sub(a.as_f32x16(), b.as_f32x16())) } @@ -1208,7 +1208,7 @@ pub fn _mm512_sub_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_ps&expand=5731) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps))] pub fn _mm512_mask_sub_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -1222,7 +1222,7 @@ pub fn _mm512_mask_sub_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_ps&expand=5732) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps))] pub fn _mm512_maskz_sub_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -1236,7 +1236,7 @@ pub fn _mm512_maskz_sub_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sub_ps&expand=5728) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps))] pub fn _mm256_mask_sub_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -1250,7 +1250,7 @@ pub fn _mm256_mask_sub_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sub_ps&expand=5729) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps))] pub fn _mm256_maskz_sub_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -1264,7 +1264,7 @@ pub fn _mm256_maskz_sub_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sub_ps&expand=5725) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps))] pub fn _mm_mask_sub_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -1278,7 +1278,7 @@ pub fn _mm_mask_sub_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sub_ps&expand=5726) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps))] pub fn _mm_maskz_sub_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -1292,7 +1292,7 @@ pub fn _mm_maskz_sub_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_pd&expand=5721) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd))] pub fn _mm512_sub_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(simd_sub(a.as_f64x8(), b.as_f64x8())) } @@ -1303,7 +1303,7 @@ pub fn _mm512_sub_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_pd&expand=5719) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd))] pub fn _mm512_mask_sub_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -1317,7 +1317,7 @@ pub fn _mm512_mask_sub_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_pd&expand=5720) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd))] pub fn _mm512_maskz_sub_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -1331,7 +1331,7 @@ pub fn _mm512_maskz_sub_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sub_pd&expand=5716) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd))] pub fn _mm256_mask_sub_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -1345,7 +1345,7 @@ pub fn _mm256_mask_sub_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sub_pd&expand=5717) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd))] pub fn _mm256_maskz_sub_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -1359,7 +1359,7 @@ pub fn _mm256_maskz_sub_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sub_pd&expand=5713) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd))] pub fn _mm_mask_sub_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -1373,7 +1373,7 @@ pub fn _mm_mask_sub_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sub_pd&expand=5714) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd))] pub fn _mm_maskz_sub_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -1387,7 +1387,7 @@ pub fn _mm_maskz_sub_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mul_epi32&expand=3907) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuldq))] pub fn _mm512_mul_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1402,7 +1402,7 @@ pub fn _mm512_mul_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mul_epi32&expand=3905) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuldq))] pub fn _mm512_mask_mul_epi32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1416,7 +1416,7 @@ pub fn _mm512_mask_mul_epi32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mul_epi32&expand=3906) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuldq))] pub fn _mm512_maskz_mul_epi32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1430,7 +1430,7 @@ pub fn _mm512_maskz_mul_epi32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mul_epi32&expand=3902) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuldq))] pub fn _mm256_mask_mul_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1444,7 +1444,7 @@ pub fn _mm256_mask_mul_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mul_epi32&expand=3903) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuldq))] pub fn _mm256_maskz_mul_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1458,7 +1458,7 @@ pub fn _mm256_maskz_mul_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mul_epi32&expand=3899) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuldq))] pub fn _mm_mask_mul_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1472,7 +1472,7 @@ pub fn _mm_mask_mul_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mul_epi32&expand=3900) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuldq))] pub fn _mm_maskz_mul_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1486,7 +1486,7 @@ pub fn _mm_maskz_mul_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mullo_epi32&expand=4005) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulld))] pub fn _mm512_mullo_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_mul(a.as_i32x16(), b.as_i32x16())) } @@ -1497,7 +1497,7 @@ pub fn _mm512_mullo_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mullo_epi32&expand=4003) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulld))] pub fn _mm512_mask_mullo_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1511,7 +1511,7 @@ pub fn _mm512_mask_mullo_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mullo_epi32&expand=4004) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulld))] pub fn _mm512_maskz_mullo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1525,7 +1525,7 @@ pub fn _mm512_maskz_mullo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mullo_epi32&expand=4000) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulld))] pub fn _mm256_mask_mullo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1539,7 +1539,7 @@ pub fn _mm256_mask_mullo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mullo_epi32&expand=4001) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulld))] pub fn _mm256_maskz_mullo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1553,7 +1553,7 @@ pub fn _mm256_maskz_mullo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mullo_epi32&expand=3997) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulld))] pub fn _mm_mask_mullo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1567,7 +1567,7 @@ pub fn _mm_mask_mullo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mullo_epi32&expand=3998) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmulld))] pub fn _mm_maskz_mullo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1583,7 +1583,7 @@ pub fn _mm_maskz_mullo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// This intrinsic generates a sequence of instructions, which may perform worse than a native instruction. Consider the performance impact of this intrinsic. #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mullox_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_mul(a.as_i64x8(), b.as_i64x8())) } } @@ -1595,7 +1595,7 @@ pub fn _mm512_mullox_epi64(a: __m512i, b: __m512i) -> __m512i { /// This intrinsic generates a sequence of instructions, which may perform worse than a native instruction. Consider the performance impact of this intrinsic. #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_mullox_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { let mul = _mm512_mullox_epi64(a, b).as_i64x8(); @@ -1608,7 +1608,7 @@ pub fn _mm512_mask_mullox_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mul_epu32&expand=3916) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuludq))] pub fn _mm512_mul_epu32(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1624,7 +1624,7 @@ pub fn _mm512_mul_epu32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mul_epu32&expand=3914) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuludq))] pub fn _mm512_mask_mul_epu32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1638,7 +1638,7 @@ pub fn _mm512_mask_mul_epu32(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mul_epu32&expand=3915) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuludq))] pub fn _mm512_maskz_mul_epu32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -1652,7 +1652,7 @@ pub fn _mm512_maskz_mul_epu32(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mul_epu32&expand=3911) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuludq))] pub fn _mm256_mask_mul_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1666,7 +1666,7 @@ pub fn _mm256_mask_mul_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mul_epu32&expand=3912) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuludq))] pub fn _mm256_maskz_mul_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -1680,7 +1680,7 @@ pub fn _mm256_maskz_mul_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mul_epu32&expand=3908) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuludq))] pub fn _mm_mask_mul_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1694,7 +1694,7 @@ pub fn _mm_mask_mul_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mul_epu32&expand=3909) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmuludq))] pub fn _mm_maskz_mul_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -1708,7 +1708,7 @@ pub fn _mm_maskz_mul_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mul_ps&expand=3934) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps))] pub fn _mm512_mul_ps(a: __m512, b: __m512) -> __m512 { unsafe { transmute(simd_mul(a.as_f32x16(), b.as_f32x16())) } @@ -1719,7 +1719,7 @@ pub fn _mm512_mul_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mul_ps&expand=3932) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps))] pub fn _mm512_mask_mul_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -1733,7 +1733,7 @@ pub fn _mm512_mask_mul_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mul_ps&expand=3933) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps))] pub fn _mm512_maskz_mul_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -1747,7 +1747,7 @@ pub fn _mm512_maskz_mul_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mul_ps&expand=3929) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps))] pub fn _mm256_mask_mul_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -1761,7 +1761,7 @@ pub fn _mm256_mask_mul_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mul_ps&expand=3930) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps))] pub fn _mm256_maskz_mul_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -1775,7 +1775,7 @@ pub fn _mm256_maskz_mul_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mul_ps&expand=3926) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps))] pub fn _mm_mask_mul_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -1789,7 +1789,7 @@ pub fn _mm_mask_mul_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mul_ps&expand=3927) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps))] pub fn _mm_maskz_mul_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -1803,7 +1803,7 @@ pub fn _mm_maskz_mul_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mul_pd&expand=3925) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd))] pub fn _mm512_mul_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(simd_mul(a.as_f64x8(), b.as_f64x8())) } @@ -1814,7 +1814,7 @@ pub fn _mm512_mul_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mul_pd&expand=3923) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd))] pub fn _mm512_mask_mul_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -1828,7 +1828,7 @@ pub fn _mm512_mask_mul_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mul_pd&expand=3924) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd))] pub fn _mm512_maskz_mul_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -1842,7 +1842,7 @@ pub fn _mm512_maskz_mul_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mul_pd&expand=3920) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd))] pub fn _mm256_mask_mul_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -1856,7 +1856,7 @@ pub fn _mm256_mask_mul_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mul_pd&expand=3921) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd))] pub fn _mm256_maskz_mul_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -1870,7 +1870,7 @@ pub fn _mm256_maskz_mul_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mul_pd&expand=3917) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd))] pub fn _mm_mask_mul_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -1884,7 +1884,7 @@ pub fn _mm_mask_mul_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mul_pd&expand=3918) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd))] pub fn _mm_maskz_mul_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -1898,7 +1898,7 @@ pub fn _mm_maskz_mul_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_div_ps&expand=2162) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps))] pub fn _mm512_div_ps(a: __m512, b: __m512) -> __m512 { unsafe { transmute(simd_div(a.as_f32x16(), b.as_f32x16())) } @@ -1909,7 +1909,7 @@ pub fn _mm512_div_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_div_ps&expand=2163) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps))] pub fn _mm512_mask_div_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -1923,7 +1923,7 @@ pub fn _mm512_mask_div_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_div_ps&expand=2164) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps))] pub fn _mm512_maskz_div_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -1937,7 +1937,7 @@ pub fn _mm512_maskz_div_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_div_ps&expand=2160) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps))] pub fn _mm256_mask_div_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -1951,7 +1951,7 @@ pub fn _mm256_mask_div_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_div_ps&expand=2161) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps))] pub fn _mm256_maskz_div_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -1965,7 +1965,7 @@ pub fn _mm256_maskz_div_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_div_ps&expand=2157) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps))] pub fn _mm_mask_div_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -1979,7 +1979,7 @@ pub fn _mm_mask_div_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_div_ps&expand=2158) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps))] pub fn _mm_maskz_div_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -1993,7 +1993,7 @@ pub fn _mm_maskz_div_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_div_pd&expand=2153) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd))] pub fn _mm512_div_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(simd_div(a.as_f64x8(), b.as_f64x8())) } @@ -2004,7 +2004,7 @@ pub fn _mm512_div_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_div_pd&expand=2154) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd))] pub fn _mm512_mask_div_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -2018,7 +2018,7 @@ pub fn _mm512_mask_div_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_div_pd&expand=2155) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd))] pub fn _mm512_maskz_div_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -2032,7 +2032,7 @@ pub fn _mm512_maskz_div_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_div_pd&expand=2151) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd))] pub fn _mm256_mask_div_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -2046,7 +2046,7 @@ pub fn _mm256_mask_div_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_div_pd&expand=2152) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd))] pub fn _mm256_maskz_div_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -2060,7 +2060,7 @@ pub fn _mm256_maskz_div_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_div_pd&expand=2148) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd))] pub fn _mm_mask_div_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -2074,7 +2074,7 @@ pub fn _mm_mask_div_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_div_pd&expand=2149) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd))] pub fn _mm_maskz_div_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -2088,7 +2088,7 @@ pub fn _mm_maskz_div_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epi32&expand=3582) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsd))] pub fn _mm512_max_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2103,7 +2103,7 @@ pub fn _mm512_max_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epi32&expand=3580) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsd))] pub fn _mm512_mask_max_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2117,7 +2117,7 @@ pub fn _mm512_mask_max_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epi32&expand=3581) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsd))] pub fn _mm512_maskz_max_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2131,7 +2131,7 @@ pub fn _mm512_maskz_max_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epi32&expand=3577) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsd))] pub fn _mm256_mask_max_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2145,7 +2145,7 @@ pub fn _mm256_mask_max_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epi32&expand=3578) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsd))] pub fn _mm256_maskz_max_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2159,7 +2159,7 @@ pub fn _mm256_maskz_max_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epi32&expand=3574) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsd))] pub fn _mm_mask_max_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2173,7 +2173,7 @@ pub fn _mm_mask_max_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epi32&expand=3575) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsd))] pub fn _mm_maskz_max_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2187,7 +2187,7 @@ pub fn _mm_maskz_max_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epi64&expand=3591) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm512_max_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2202,7 +2202,7 @@ pub fn _mm512_max_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epi64&expand=3589) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm512_mask_max_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2216,7 +2216,7 @@ pub fn _mm512_mask_max_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epi64&expand=3590) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm512_maskz_max_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2230,7 +2230,7 @@ pub fn _mm512_maskz_max_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_max_epi64&expand=3588) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm256_max_epi64(a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2245,7 +2245,7 @@ pub fn _mm256_max_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epi64&expand=3586) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm256_mask_max_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2259,7 +2259,7 @@ pub fn _mm256_mask_max_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epi64&expand=3587) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm256_maskz_max_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2273,7 +2273,7 @@ pub fn _mm256_maskz_max_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_epi64&expand=3585) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm_max_epi64(a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2288,7 +2288,7 @@ pub fn _mm_max_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epi64&expand=3583) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm_mask_max_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2302,7 +2302,7 @@ pub fn _mm_mask_max_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epi64&expand=3584) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxsq))] pub fn _mm_maskz_max_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2316,7 +2316,7 @@ pub fn _mm_maskz_max_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_ps&expand=3655) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps))] pub fn _mm512_max_ps(a: __m512, b: __m512) -> __m512 { unsafe { @@ -2333,7 +2333,7 @@ pub fn _mm512_max_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_ps&expand=3653) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps))] pub fn _mm512_mask_max_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -2347,7 +2347,7 @@ pub fn _mm512_mask_max_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_ps&expand=3654) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps))] pub fn _mm512_maskz_max_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -2361,7 +2361,7 @@ pub fn _mm512_maskz_max_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_ps&expand=3650) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps))] pub fn _mm256_mask_max_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -2375,7 +2375,7 @@ pub fn _mm256_mask_max_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_ps&expand=3651) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps))] pub fn _mm256_maskz_max_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -2389,7 +2389,7 @@ pub fn _mm256_maskz_max_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_ps&expand=3647) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps))] pub fn _mm_mask_max_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -2403,7 +2403,7 @@ pub fn _mm_mask_max_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_ps&expand=3648) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps))] pub fn _mm_maskz_max_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -2417,7 +2417,7 @@ pub fn _mm_maskz_max_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_pd&expand=3645) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd))] pub fn _mm512_max_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(vmaxpd(a.as_f64x8(), b.as_f64x8(), _MM_FROUND_CUR_DIRECTION)) } @@ -2428,7 +2428,7 @@ pub fn _mm512_max_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_pd&expand=3643) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd))] pub fn _mm512_mask_max_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -2442,7 +2442,7 @@ pub fn _mm512_mask_max_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_pd&expand=3644) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd))] pub fn _mm512_maskz_max_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -2456,7 +2456,7 @@ pub fn _mm512_maskz_max_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_pd&expand=3640) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd))] pub fn _mm256_mask_max_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -2470,7 +2470,7 @@ pub fn _mm256_mask_max_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_pd&expand=3641) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd))] pub fn _mm256_maskz_max_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -2484,7 +2484,7 @@ pub fn _mm256_maskz_max_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_pd&expand=3637) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd))] pub fn _mm_mask_max_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -2498,7 +2498,7 @@ pub fn _mm_mask_max_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_pd&expand=3638) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd))] pub fn _mm_maskz_max_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -2512,7 +2512,7 @@ pub fn _mm_maskz_max_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epu32&expand=3618) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxud))] pub fn _mm512_max_epu32(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2527,7 +2527,7 @@ pub fn _mm512_max_epu32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epu32&expand=3616) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxud))] pub fn _mm512_mask_max_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2541,7 +2541,7 @@ pub fn _mm512_mask_max_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epu32&expand=3617) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxud))] pub fn _mm512_maskz_max_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2555,7 +2555,7 @@ pub fn _mm512_maskz_max_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epu32&expand=3613) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxud))] pub fn _mm256_mask_max_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2569,7 +2569,7 @@ pub fn _mm256_mask_max_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epu32&expand=3614) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxud))] pub fn _mm256_maskz_max_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2583,7 +2583,7 @@ pub fn _mm256_maskz_max_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epu32&expand=3610) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxud))] pub fn _mm_mask_max_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2597,7 +2597,7 @@ pub fn _mm_mask_max_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epu32&expand=3611) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxud))] pub fn _mm_maskz_max_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2611,7 +2611,7 @@ pub fn _mm_maskz_max_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epu64&expand=3627) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm512_max_epu64(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2626,7 +2626,7 @@ pub fn _mm512_max_epu64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epu64&expand=3625) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm512_mask_max_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2640,7 +2640,7 @@ pub fn _mm512_mask_max_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epu64&expand=3626) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm512_maskz_max_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2654,7 +2654,7 @@ pub fn _mm512_maskz_max_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_max_epu64&expand=3624) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm256_max_epu64(a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2669,7 +2669,7 @@ pub fn _mm256_max_epu64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epu64&expand=3622) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm256_mask_max_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2683,7 +2683,7 @@ pub fn _mm256_mask_max_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epu64&expand=3623) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm256_maskz_max_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2697,7 +2697,7 @@ pub fn _mm256_maskz_max_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_epu64&expand=3621) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm_max_epu64(a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2712,7 +2712,7 @@ pub fn _mm_max_epu64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epu64&expand=3619) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm_mask_max_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2726,7 +2726,7 @@ pub fn _mm_mask_max_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epu64&expand=3620) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmaxuq))] pub fn _mm_maskz_max_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2740,7 +2740,7 @@ pub fn _mm_maskz_max_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epi32&expand=3696) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsd))] pub fn _mm512_min_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2755,7 +2755,7 @@ pub fn _mm512_min_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epi32&expand=3694) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsd))] pub fn _mm512_mask_min_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2769,7 +2769,7 @@ pub fn _mm512_mask_min_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epi32&expand=3695) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsd))] pub fn _mm512_maskz_min_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2783,7 +2783,7 @@ pub fn _mm512_maskz_min_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epi32&expand=3691) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsd))] pub fn _mm256_mask_min_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2797,7 +2797,7 @@ pub fn _mm256_mask_min_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epi32&expand=3692) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsd))] pub fn _mm256_maskz_min_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2811,7 +2811,7 @@ pub fn _mm256_maskz_min_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epi32&expand=3688) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsd))] pub fn _mm_mask_min_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2825,7 +2825,7 @@ pub fn _mm_mask_min_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epi32&expand=3689) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsd))] pub fn _mm_maskz_min_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2839,7 +2839,7 @@ pub fn _mm_maskz_min_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epi64&expand=3705) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm512_min_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2854,7 +2854,7 @@ pub fn _mm512_min_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epi64&expand=3703) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm512_mask_min_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2868,7 +2868,7 @@ pub fn _mm512_mask_min_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epi64&expand=3704) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm512_maskz_min_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -2882,7 +2882,7 @@ pub fn _mm512_maskz_min_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_min_epi64&expand=3702) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm256_min_epi64(a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2897,7 +2897,7 @@ pub fn _mm256_min_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epi64&expand=3700) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm256_mask_min_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2911,7 +2911,7 @@ pub fn _mm256_mask_min_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epi64&expand=3701) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm256_maskz_min_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -2925,7 +2925,7 @@ pub fn _mm256_maskz_min_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_min_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm_min_epi64(a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2940,7 +2940,7 @@ pub fn _mm_min_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm_mask_min_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2954,7 +2954,7 @@ pub fn _mm_mask_min_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminsq))] pub fn _mm_maskz_min_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -2968,7 +2968,7 @@ pub fn _mm_maskz_min_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_ps&expand=3769) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps))] pub fn _mm512_min_ps(a: __m512, b: __m512) -> __m512 { unsafe { @@ -2985,7 +2985,7 @@ pub fn _mm512_min_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_ps&expand=3767) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps))] pub fn _mm512_mask_min_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -2999,7 +2999,7 @@ pub fn _mm512_mask_min_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_ps&expand=3768) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps))] pub fn _mm512_maskz_min_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -3013,7 +3013,7 @@ pub fn _mm512_maskz_min_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_ps&expand=3764) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps))] pub fn _mm256_mask_min_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -3027,7 +3027,7 @@ pub fn _mm256_mask_min_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_ps&expand=3765) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps))] pub fn _mm256_maskz_min_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -3041,7 +3041,7 @@ pub fn _mm256_maskz_min_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_ps&expand=3761) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps))] pub fn _mm_mask_min_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -3055,7 +3055,7 @@ pub fn _mm_mask_min_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_ps&expand=3762) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps))] pub fn _mm_maskz_min_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -3069,7 +3069,7 @@ pub fn _mm_maskz_min_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_pd&expand=3759) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd))] pub fn _mm512_min_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(vminpd(a.as_f64x8(), b.as_f64x8(), _MM_FROUND_CUR_DIRECTION)) } @@ -3080,7 +3080,7 @@ pub fn _mm512_min_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_pd&expand=3757) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd))] pub fn _mm512_mask_min_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -3094,7 +3094,7 @@ pub fn _mm512_mask_min_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_pd&expand=3758) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd))] pub fn _mm512_maskz_min_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -3108,7 +3108,7 @@ pub fn _mm512_maskz_min_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_pd&expand=3754) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd))] pub fn _mm256_mask_min_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -3122,7 +3122,7 @@ pub fn _mm256_mask_min_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_pd&expand=3755) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd))] pub fn _mm256_maskz_min_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -3136,7 +3136,7 @@ pub fn _mm256_maskz_min_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_pd&expand=3751) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd))] pub fn _mm_mask_min_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -3150,7 +3150,7 @@ pub fn _mm_mask_min_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_pd&expand=3752) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd))] pub fn _mm_maskz_min_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -3164,7 +3164,7 @@ pub fn _mm_maskz_min_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epu32&expand=3732) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminud))] pub fn _mm512_min_epu32(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -3179,7 +3179,7 @@ pub fn _mm512_min_epu32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epu32&expand=3730) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminud))] pub fn _mm512_mask_min_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -3193,7 +3193,7 @@ pub fn _mm512_mask_min_epu32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epu32&expand=3731) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminud))] pub fn _mm512_maskz_min_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -3207,7 +3207,7 @@ pub fn _mm512_maskz_min_epu32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epu32&expand=3727) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminud))] pub fn _mm256_mask_min_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -3221,7 +3221,7 @@ pub fn _mm256_mask_min_epu32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epu32&expand=3728) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminud))] pub fn _mm256_maskz_min_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -3235,7 +3235,7 @@ pub fn _mm256_maskz_min_epu32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epu32&expand=3724) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminud))] pub fn _mm_mask_min_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -3249,7 +3249,7 @@ pub fn _mm_mask_min_epu32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epu32&expand=3725) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminud))] pub fn _mm_maskz_min_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -3263,7 +3263,7 @@ pub fn _mm_maskz_min_epu32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epu64&expand=3741) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm512_min_epu64(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -3278,7 +3278,7 @@ pub fn _mm512_min_epu64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epu64&expand=3739) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm512_mask_min_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -3292,7 +3292,7 @@ pub fn _mm512_mask_min_epu64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epu64&expand=3740) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm512_maskz_min_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -3306,7 +3306,7 @@ pub fn _mm512_maskz_min_epu64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_min_epu64&expand=3738) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm256_min_epu64(a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -3321,7 +3321,7 @@ pub fn _mm256_min_epu64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epu64&expand=3736) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm256_mask_min_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -3335,7 +3335,7 @@ pub fn _mm256_mask_min_epu64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epu64&expand=3737) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm256_maskz_min_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -3349,7 +3349,7 @@ pub fn _mm256_maskz_min_epu64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_min_epu64&expand=3735) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm_min_epu64(a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -3364,7 +3364,7 @@ pub fn _mm_min_epu64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epu64&expand=3733) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm_mask_min_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -3378,7 +3378,7 @@ pub fn _mm_mask_min_epu64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epu64&expand=3734) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpminuq))] pub fn _mm_maskz_min_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -3392,7 +3392,7 @@ pub fn _mm_maskz_min_epu64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sqrt_ps&expand=5371) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps))] pub fn _mm512_sqrt_ps(a: __m512) -> __m512 { unsafe { simd_fsqrt(a) } @@ -3403,7 +3403,7 @@ pub fn _mm512_sqrt_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sqrt_ps&expand=5369) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps))] pub fn _mm512_mask_sqrt_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { simd_select_bitmask(k, simd_fsqrt(a), src) } @@ -3414,7 +3414,7 @@ pub fn _mm512_mask_sqrt_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sqrt_ps&expand=5370) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps))] pub fn _mm512_maskz_sqrt_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { simd_select_bitmask(k, simd_fsqrt(a), _mm512_setzero_ps()) } @@ -3425,7 +3425,7 @@ pub fn _mm512_maskz_sqrt_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sqrt_ps&expand=5366) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps))] pub fn _mm256_mask_sqrt_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { simd_select_bitmask(k, simd_fsqrt(a), src) } @@ -3436,7 +3436,7 @@ pub fn _mm256_mask_sqrt_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sqrt_ps&expand=5367) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps))] pub fn _mm256_maskz_sqrt_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { simd_select_bitmask(k, simd_fsqrt(a), _mm256_setzero_ps()) } @@ -3447,7 +3447,7 @@ pub fn _mm256_maskz_sqrt_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sqrt_ps&expand=5363) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps))] pub fn _mm_mask_sqrt_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { simd_select_bitmask(k, simd_fsqrt(a), src) } @@ -3458,7 +3458,7 @@ pub fn _mm_mask_sqrt_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sqrt_ps&expand=5364) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps))] pub fn _mm_maskz_sqrt_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { simd_select_bitmask(k, simd_fsqrt(a), _mm_setzero_ps()) } @@ -3469,7 +3469,7 @@ pub fn _mm_maskz_sqrt_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sqrt_pd&expand=5362) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd))] pub fn _mm512_sqrt_pd(a: __m512d) -> __m512d { unsafe { simd_fsqrt(a) } @@ -3480,7 +3480,7 @@ pub fn _mm512_sqrt_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sqrt_pd&expand=5360) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd))] pub fn _mm512_mask_sqrt_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, simd_fsqrt(a), src) } @@ -3491,7 +3491,7 @@ pub fn _mm512_mask_sqrt_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sqrt_pd&expand=5361) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd))] pub fn _mm512_maskz_sqrt_pd(k: __mmask8, a: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, simd_fsqrt(a), _mm512_setzero_pd()) } @@ -3502,7 +3502,7 @@ pub fn _mm512_maskz_sqrt_pd(k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sqrt_pd&expand=5357) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd))] pub fn _mm256_mask_sqrt_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, simd_fsqrt(a), src) } @@ -3513,7 +3513,7 @@ pub fn _mm256_mask_sqrt_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sqrt_pd&expand=5358) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd))] pub fn _mm256_maskz_sqrt_pd(k: __mmask8, a: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, simd_fsqrt(a), _mm256_setzero_pd()) } @@ -3524,7 +3524,7 @@ pub fn _mm256_maskz_sqrt_pd(k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sqrt_pd&expand=5354) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd))] pub fn _mm_mask_sqrt_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, simd_fsqrt(a), src) } @@ -3535,7 +3535,7 @@ pub fn _mm_mask_sqrt_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sqrt_pd&expand=5355) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd))] pub fn _mm_maskz_sqrt_pd(k: __mmask8, a: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, simd_fsqrt(a), _mm_setzero_pd()) } @@ -3546,7 +3546,7 @@ pub fn _mm_maskz_sqrt_pd(k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmadd_ps&expand=2557) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm512_fmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_fma(a, b, c) } @@ -3557,7 +3557,7 @@ pub fn _mm512_fmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmadd_ps&expand=2558) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm512_mask_fmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmadd_ps(a, b, c), a) } @@ -3568,7 +3568,7 @@ pub fn _mm512_mask_fmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmadd_ps&expand=2560) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm512_maskz_fmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmadd_ps(a, b, c), _mm512_setzero_ps()) } @@ -3579,7 +3579,7 @@ pub fn _mm512_maskz_fmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmadd_ps&expand=2559) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm512_mask3_fmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmadd_ps(a, b, c), c) } @@ -3590,7 +3590,7 @@ pub fn _mm512_mask3_fmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fmadd_ps&expand=2554) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm256_mask_fmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmadd_ps(a, b, c), a) } @@ -3601,7 +3601,7 @@ pub fn _mm256_mask_fmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fmadd_ps&expand=2556) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm256_maskz_fmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmadd_ps(a, b, c), _mm256_setzero_ps()) } @@ -3612,7 +3612,7 @@ pub fn _mm256_maskz_fmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fmadd_ps&expand=2555) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm256_mask3_fmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmadd_ps(a, b, c), c) } @@ -3623,7 +3623,7 @@ pub fn _mm256_mask3_fmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fmadd_ps&expand=2550) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm_mask_fmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmadd_ps(a, b, c), a) } @@ -3634,7 +3634,7 @@ pub fn _mm_mask_fmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fmadd_ps&expand=2552) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm_maskz_fmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmadd_ps(a, b, c), _mm_setzero_ps()) } @@ -3645,7 +3645,7 @@ pub fn _mm_maskz_fmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fmadd_ps&expand=2551) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132ps or vfmadd213ps or vfmadd231ps pub fn _mm_mask3_fmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmadd_ps(a, b, c), c) } @@ -3656,7 +3656,7 @@ pub fn _mm_mask3_fmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmadd_pd&expand=2545) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm512_fmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_fma(a, b, c) } @@ -3667,7 +3667,7 @@ pub fn _mm512_fmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmadd_pd&expand=2546) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm512_mask_fmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmadd_pd(a, b, c), a) } @@ -3678,7 +3678,7 @@ pub fn _mm512_mask_fmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmadd_pd&expand=2548) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm512_maskz_fmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmadd_pd(a, b, c), _mm512_setzero_pd()) } @@ -3689,7 +3689,7 @@ pub fn _mm512_maskz_fmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmadd_pd&expand=2547) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm512_mask3_fmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmadd_pd(a, b, c), c) } @@ -3700,7 +3700,7 @@ pub fn _mm512_mask3_fmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fmadd_pd&expand=2542) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm256_mask_fmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmadd_pd(a, b, c), a) } @@ -3711,7 +3711,7 @@ pub fn _mm256_mask_fmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fmadd_pd&expand=2544) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm256_maskz_fmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmadd_pd(a, b, c), _mm256_setzero_pd()) } @@ -3722,7 +3722,7 @@ pub fn _mm256_maskz_fmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fmadd_pd&expand=2543) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm256_mask3_fmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmadd_pd(a, b, c), c) } @@ -3733,7 +3733,7 @@ pub fn _mm256_mask3_fmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fmadd_pd&expand=2538) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm_mask_fmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmadd_pd(a, b, c), a) } @@ -3744,7 +3744,7 @@ pub fn _mm_mask_fmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fmadd_pd&expand=2540) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm_maskz_fmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmadd_pd(a, b, c), _mm_setzero_pd()) } @@ -3755,7 +3755,7 @@ pub fn _mm_maskz_fmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fmadd_pd&expand=2539) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] //vfmadd132pd or vfmadd213pd or vfmadd231pd pub fn _mm_mask3_fmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmadd_pd(a, b, c), c) } @@ -3766,7 +3766,7 @@ pub fn _mm_mask3_fmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmsub_ps&expand=2643) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm512_fmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -3777,7 +3777,7 @@ pub fn _mm512_fmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmsub_ps&expand=2644) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm512_mask_fmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmsub_ps(a, b, c), a) } @@ -3788,7 +3788,7 @@ pub fn _mm512_mask_fmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmsub_ps&expand=2646) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm512_maskz_fmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmsub_ps(a, b, c), _mm512_setzero_ps()) } @@ -3799,7 +3799,7 @@ pub fn _mm512_maskz_fmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmsub_ps&expand=2645) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm512_mask3_fmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmsub_ps(a, b, c), c) } @@ -3810,7 +3810,7 @@ pub fn _mm512_mask3_fmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fmsub_ps&expand=2640) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm256_mask_fmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmsub_ps(a, b, c), a) } @@ -3821,7 +3821,7 @@ pub fn _mm256_mask_fmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fmsub_ps&expand=2642) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm256_maskz_fmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmsub_ps(a, b, c), _mm256_setzero_ps()) } @@ -3832,7 +3832,7 @@ pub fn _mm256_maskz_fmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fmsub_ps&expand=2641) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm256_mask3_fmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmsub_ps(a, b, c), c) } @@ -3843,7 +3843,7 @@ pub fn _mm256_mask3_fmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fmsub_ps&expand=2636) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm_mask_fmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmsub_ps(a, b, c), a) } @@ -3854,7 +3854,7 @@ pub fn _mm_mask_fmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fmsub_ps&expand=2638) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm_maskz_fmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmsub_ps(a, b, c), _mm_setzero_ps()) } @@ -3865,7 +3865,7 @@ pub fn _mm_maskz_fmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fmsub_ps&expand=2637) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generate vfmadd, gcc generate vfmsub pub fn _mm_mask3_fmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmsub_ps(a, b, c), c) } @@ -3876,7 +3876,7 @@ pub fn _mm_mask3_fmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmsub_pd&expand=2631) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm512_fmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -3887,7 +3887,7 @@ pub fn _mm512_fmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmsub_pd&expand=2632) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm512_mask_fmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmsub_pd(a, b, c), a) } @@ -3898,7 +3898,7 @@ pub fn _mm512_mask_fmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmsub_pd&expand=2634) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm512_maskz_fmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmsub_pd(a, b, c), _mm512_setzero_pd()) } @@ -3909,7 +3909,7 @@ pub fn _mm512_maskz_fmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmsub_pd&expand=2633) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm512_mask3_fmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmsub_pd(a, b, c), c) } @@ -3920,7 +3920,7 @@ pub fn _mm512_mask3_fmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fmsub_pd&expand=2628) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm256_mask_fmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmsub_pd(a, b, c), a) } @@ -3931,7 +3931,7 @@ pub fn _mm256_mask_fmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fmsub_pd&expand=2630) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm256_maskz_fmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmsub_pd(a, b, c), _mm256_setzero_pd()) } @@ -3942,7 +3942,7 @@ pub fn _mm256_maskz_fmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fmsub_pd&expand=2629) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm256_mask3_fmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmsub_pd(a, b, c), c) } @@ -3953,7 +3953,7 @@ pub fn _mm256_mask3_fmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fmsub_pd&expand=2624) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm_mask_fmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmsub_pd(a, b, c), a) } @@ -3964,7 +3964,7 @@ pub fn _mm_mask_fmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fmsub_pd&expand=2626) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm_maskz_fmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmsub_pd(a, b, c), _mm_setzero_pd()) } @@ -3975,7 +3975,7 @@ pub fn _mm_maskz_fmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fmsub_pd&expand=2625) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang fmadd, gcc fmsub pub fn _mm_mask3_fmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmsub_pd(a, b, c), c) } @@ -3986,7 +3986,7 @@ pub fn _mm_mask3_fmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmaddsub_ps&expand=2611) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm512_fmaddsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { @@ -4005,7 +4005,7 @@ pub fn _mm512_fmaddsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmaddsub_ps&expand=2612) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm512_mask_fmaddsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ps(a, b, c), a) } @@ -4016,7 +4016,7 @@ pub fn _mm512_mask_fmaddsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmaddsub_ps&expand=2614) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm512_maskz_fmaddsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ps(a, b, c), _mm512_setzero_ps()) } @@ -4027,7 +4027,7 @@ pub fn _mm512_maskz_fmaddsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmaddsub_ps&expand=2613) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm512_mask3_fmaddsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ps(a, b, c), c) } @@ -4038,7 +4038,7 @@ pub fn _mm512_mask3_fmaddsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fmaddsub_ps&expand=2608) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm256_mask_fmaddsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ps(a, b, c), a) } @@ -4049,7 +4049,7 @@ pub fn _mm256_mask_fmaddsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fmaddsub_ps&expand=2610) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm256_maskz_fmaddsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ps(a, b, c), _mm256_setzero_ps()) } @@ -4060,7 +4060,7 @@ pub fn _mm256_maskz_fmaddsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fmaddsub_ps&expand=2609) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm256_mask3_fmaddsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ps(a, b, c), c) } @@ -4071,7 +4071,7 @@ pub fn _mm256_mask3_fmaddsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fmaddsub_ps&expand=2604) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm_mask_fmaddsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ps(a, b, c), a) } @@ -4082,7 +4082,7 @@ pub fn _mm_mask_fmaddsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/IntrinsicsGuide/#text=_mm_maskz_fmaddsub_ps&expand=2606) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm_maskz_fmaddsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ps(a, b, c), _mm_setzero_ps()) } @@ -4093,7 +4093,7 @@ pub fn _mm_maskz_fmaddsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fmaddsub_ps&expand=2605) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps pub fn _mm_mask3_fmaddsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ps(a, b, c), c) } @@ -4104,7 +4104,7 @@ pub fn _mm_mask3_fmaddsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmaddsub_pd&expand=2599) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm512_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { @@ -4119,7 +4119,7 @@ pub fn _mm512_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmaddsub_pd&expand=2600) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm512_mask_fmaddsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_pd(a, b, c), a) } @@ -4130,7 +4130,7 @@ pub fn _mm512_mask_fmaddsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmaddsub_pd&expand=2602) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm512_maskz_fmaddsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_pd(a, b, c), _mm512_setzero_pd()) } @@ -4141,7 +4141,7 @@ pub fn _mm512_maskz_fmaddsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmaddsub_pd&expand=2613) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm512_mask3_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_pd(a, b, c), c) } @@ -4152,7 +4152,7 @@ pub fn _mm512_mask3_fmaddsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fmaddsub_pd&expand=2596) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm256_mask_fmaddsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_pd(a, b, c), a) } @@ -4163,7 +4163,7 @@ pub fn _mm256_mask_fmaddsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fmaddsub_pd&expand=2598) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm256_maskz_fmaddsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_pd(a, b, c), _mm256_setzero_pd()) } @@ -4174,7 +4174,7 @@ pub fn _mm256_maskz_fmaddsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fmaddsub_pd&expand=2597) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm256_mask3_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_pd(a, b, c), c) } @@ -4185,7 +4185,7 @@ pub fn _mm256_mask3_fmaddsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fmaddsub_pd&expand=2592) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm_mask_fmaddsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmaddsub_pd(a, b, c), a) } @@ -4196,7 +4196,7 @@ pub fn _mm_mask_fmaddsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fmaddsub_pd&expand=2594) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm_maskz_fmaddsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmaddsub_pd(a, b, c), _mm_setzero_pd()) } @@ -4207,7 +4207,7 @@ pub fn _mm_maskz_fmaddsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fmaddsub_pd&expand=2593) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd pub fn _mm_mask3_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmaddsub_pd(a, b, c), c) } @@ -4218,7 +4218,7 @@ pub fn _mm_mask3_fmaddsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmsubadd_ps&expand=2691) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm512_fmsubadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { @@ -4237,7 +4237,7 @@ pub fn _mm512_fmsubadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmsubadd_ps&expand=2692) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm512_mask_fmsubadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ps(a, b, c), a) } @@ -4248,7 +4248,7 @@ pub fn _mm512_mask_fmsubadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmsubadd_ps&expand=2694) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm512_maskz_fmsubadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ps(a, b, c), _mm512_setzero_ps()) } @@ -4259,7 +4259,7 @@ pub fn _mm512_maskz_fmsubadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmsubadd_ps&expand=2693) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm512_mask3_fmsubadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ps(a, b, c), c) } @@ -4270,7 +4270,7 @@ pub fn _mm512_mask3_fmsubadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fmsubadd_ps&expand=2688) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm256_mask_fmsubadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ps(a, b, c), a) } @@ -4281,7 +4281,7 @@ pub fn _mm256_mask_fmsubadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fmsubadd_ps&expand=2690) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm256_maskz_fmsubadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ps(a, b, c), _mm256_setzero_ps()) } @@ -4292,7 +4292,7 @@ pub fn _mm256_maskz_fmsubadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fmsubadd_ps&expand=2689) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm256_mask3_fmsubadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ps(a, b, c), c) } @@ -4303,7 +4303,7 @@ pub fn _mm256_mask3_fmsubadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fmsubadd_ps&expand=2684) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm_mask_fmsubadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ps(a, b, c), a) } @@ -4314,7 +4314,7 @@ pub fn _mm_mask_fmsubadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fmsubadd_ps&expand=2686) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm_maskz_fmsubadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ps(a, b, c), _mm_setzero_ps()) } @@ -4325,7 +4325,7 @@ pub fn _mm_maskz_fmsubadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fmsubadd_ps&expand=2685) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps pub fn _mm_mask3_fmsubadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ps(a, b, c), c) } @@ -4336,7 +4336,7 @@ pub fn _mm_mask3_fmsubadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmsubadd_pd&expand=2679) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm512_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { @@ -4351,7 +4351,7 @@ pub fn _mm512_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmsubadd_pd&expand=2680) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm512_mask_fmsubadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_pd(a, b, c), a) } @@ -4362,7 +4362,7 @@ pub fn _mm512_mask_fmsubadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmsubadd_pd&expand=2682) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm512_maskz_fmsubadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_pd(a, b, c), _mm512_setzero_pd()) } @@ -4373,7 +4373,7 @@ pub fn _mm512_maskz_fmsubadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmsubadd_pd&expand=2681) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm512_mask3_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_pd(a, b, c), c) } @@ -4384,7 +4384,7 @@ pub fn _mm512_mask3_fmsubadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fmsubadd_pd&expand=2676) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm256_mask_fmsubadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_pd(a, b, c), a) } @@ -4395,7 +4395,7 @@ pub fn _mm256_mask_fmsubadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fmsubadd_pd&expand=2678) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm256_maskz_fmsubadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_pd(a, b, c), _mm256_setzero_pd()) } @@ -4406,7 +4406,7 @@ pub fn _mm256_maskz_fmsubadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fmsubadd_pd&expand=2677) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm256_mask3_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_pd(a, b, c), c) } @@ -4417,7 +4417,7 @@ pub fn _mm256_mask3_fmsubadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fmsubadd_pd&expand=2672) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm_mask_fmsubadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmsubadd_pd(a, b, c), a) } @@ -4428,7 +4428,7 @@ pub fn _mm_mask_fmsubadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fmsubadd_pd&expand=2674) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm_maskz_fmsubadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmsubadd_pd(a, b, c), _mm_setzero_pd()) } @@ -4439,7 +4439,7 @@ pub fn _mm_maskz_fmsubadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fmsubadd_pd&expand=2673) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd pub fn _mm_mask3_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fmsubadd_pd(a, b, c), c) } @@ -4450,7 +4450,7 @@ pub fn _mm_mask3_fmsubadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fnmadd_ps&expand=2723) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm512_fnmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_fma(simd_neg(a), b, c) } @@ -4461,7 +4461,7 @@ pub fn _mm512_fnmadd_ps(a: __m512, b: __m512, c: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fnmadd_ps&expand=2724) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm512_mask_fnmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ps(a, b, c), a) } @@ -4472,7 +4472,7 @@ pub fn _mm512_mask_fnmadd_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fnmadd_ps&expand=2726) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm512_maskz_fnmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ps(a, b, c), _mm512_setzero_ps()) } @@ -4483,7 +4483,7 @@ pub fn _mm512_maskz_fnmadd_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fnmadd_ps&expand=2725) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm512_mask3_fnmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ps(a, b, c), c) } @@ -4494,7 +4494,7 @@ pub fn _mm512_mask3_fnmadd_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fnmadd_ps&expand=2720) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm256_mask_fnmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ps(a, b, c), a) } @@ -4505,7 +4505,7 @@ pub fn _mm256_mask_fnmadd_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fnmadd_ps&expand=2722) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm256_maskz_fnmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ps(a, b, c), _mm256_setzero_ps()) } @@ -4516,7 +4516,7 @@ pub fn _mm256_maskz_fnmadd_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fnmadd_ps&expand=2721) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm256_mask3_fnmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ps(a, b, c), c) } @@ -4527,7 +4527,7 @@ pub fn _mm256_mask3_fnmadd_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fnmadd_ps&expand=2716) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm_mask_fnmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fnmadd_ps(a, b, c), a) } @@ -4538,7 +4538,7 @@ pub fn _mm_mask_fnmadd_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fnmadd_ps&expand=2718) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm_maskz_fnmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fnmadd_ps(a, b, c), _mm_setzero_ps()) } @@ -4549,7 +4549,7 @@ pub fn _mm_maskz_fnmadd_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fnmadd_ps&expand=2717) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps pub fn _mm_mask3_fnmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fnmadd_ps(a, b, c), c) } @@ -4560,7 +4560,7 @@ pub fn _mm_mask3_fnmadd_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fnmadd_pd&expand=2711) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm512_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_fma(simd_neg(a), b, c) } @@ -4571,7 +4571,7 @@ pub fn _mm512_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fnmadd_pd&expand=2712) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm512_mask_fnmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fnmadd_pd(a, b, c), a) } @@ -4582,7 +4582,7 @@ pub fn _mm512_mask_fnmadd_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fnmadd_pd&expand=2714) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm512_maskz_fnmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fnmadd_pd(a, b, c), _mm512_setzero_pd()) } @@ -4593,7 +4593,7 @@ pub fn _mm512_maskz_fnmadd_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fnmadd_pd&expand=2713) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm512_mask3_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fnmadd_pd(a, b, c), c) } @@ -4604,7 +4604,7 @@ pub fn _mm512_mask3_fnmadd_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fnmadd_pd&expand=2708) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm256_mask_fnmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fnmadd_pd(a, b, c), a) } @@ -4615,7 +4615,7 @@ pub fn _mm256_mask_fnmadd_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fnmadd_pd&expand=2710) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm256_maskz_fnmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fnmadd_pd(a, b, c), _mm256_setzero_pd()) } @@ -4626,7 +4626,7 @@ pub fn _mm256_maskz_fnmadd_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fnmadd_pd&expand=2709) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm256_mask3_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fnmadd_pd(a, b, c), c) } @@ -4637,7 +4637,7 @@ pub fn _mm256_mask3_fnmadd_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fnmadd_pd&expand=2704) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm_mask_fnmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fnmadd_pd(a, b, c), a) } @@ -4648,7 +4648,7 @@ pub fn _mm_mask_fnmadd_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fnmadd_pd&expand=2706) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm_maskz_fnmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fnmadd_pd(a, b, c), _mm_setzero_pd()) } @@ -4659,7 +4659,7 @@ pub fn _mm_maskz_fnmadd_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fnmadd_pd&expand=2705) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd pub fn _mm_mask3_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fnmadd_pd(a, b, c), c) } @@ -4670,7 +4670,7 @@ pub fn _mm_mask3_fnmadd_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fnmsub_ps&expand=2771) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm512_fnmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -4681,7 +4681,7 @@ pub fn _mm512_fnmsub_ps(a: __m512, b: __m512, c: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fnmsub_ps&expand=2772) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm512_mask_fnmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ps(a, b, c), a) } @@ -4692,7 +4692,7 @@ pub fn _mm512_mask_fnmsub_ps(a: __m512, k: __mmask16, b: __m512, c: __m512) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fnmsub_ps&expand=2774) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm512_maskz_fnmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ps(a, b, c), _mm512_setzero_ps()) } @@ -4703,7 +4703,7 @@ pub fn _mm512_maskz_fnmsub_ps(k: __mmask16, a: __m512, b: __m512, c: __m512) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fnmsub_ps&expand=2773) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm512_mask3_fnmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> __m512 { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ps(a, b, c), c) } @@ -4714,7 +4714,7 @@ pub fn _mm512_mask3_fnmsub_ps(a: __m512, b: __m512, c: __m512, k: __mmask16) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fnmsub_ps&expand=2768) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm256_mask_fnmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ps(a, b, c), a) } @@ -4725,7 +4725,7 @@ pub fn _mm256_mask_fnmsub_ps(a: __m256, k: __mmask8, b: __m256, c: __m256) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fnmsub_ps&expand=2770) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm256_maskz_fnmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ps(a, b, c), _mm256_setzero_ps()) } @@ -4736,7 +4736,7 @@ pub fn _mm256_maskz_fnmsub_ps(k: __mmask8, a: __m256, b: __m256, c: __m256) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fnmsub_ps&expand=2769) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm256_mask3_fnmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> __m256 { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ps(a, b, c), c) } @@ -4747,7 +4747,7 @@ pub fn _mm256_mask3_fnmsub_ps(a: __m256, b: __m256, c: __m256, k: __mmask8) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fnmsub_ps&expand=2764) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm_mask_fnmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fnmsub_ps(a, b, c), a) } @@ -4758,7 +4758,7 @@ pub fn _mm_mask_fnmsub_ps(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fnmsub_ps&expand=2766) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm_maskz_fnmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fnmsub_ps(a, b, c), _mm_setzero_ps()) } @@ -4769,7 +4769,7 @@ pub fn _mm_maskz_fnmsub_ps(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fnmsub_ps&expand=2765) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps pub fn _mm_mask3_fnmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { simd_select_bitmask(k, _mm_fnmsub_ps(a, b, c), c) } @@ -4780,7 +4780,7 @@ pub fn _mm_mask3_fnmsub_ps(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fnmsub_pd&expand=2759) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm512_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -4791,7 +4791,7 @@ pub fn _mm512_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fnmsub_pd&expand=2760) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm512_mask_fnmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fnmsub_pd(a, b, c), a) } @@ -4802,7 +4802,7 @@ pub fn _mm512_mask_fnmsub_pd(a: __m512d, k: __mmask8, b: __m512d, c: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fnmsub_pd&expand=2762) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm512_maskz_fnmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fnmsub_pd(a, b, c), _mm512_setzero_pd()) } @@ -4813,7 +4813,7 @@ pub fn _mm512_maskz_fnmsub_pd(k: __mmask8, a: __m512d, b: __m512d, c: __m512d) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fnmsub_pd&expand=2761) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm512_mask3_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) -> __m512d { unsafe { simd_select_bitmask(k, _mm512_fnmsub_pd(a, b, c), c) } @@ -4824,7 +4824,7 @@ pub fn _mm512_mask3_fnmsub_pd(a: __m512d, b: __m512d, c: __m512d, k: __mmask8) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fnmsub_pd&expand=2756) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm256_mask_fnmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fnmsub_pd(a, b, c), a) } @@ -4835,7 +4835,7 @@ pub fn _mm256_mask_fnmsub_pd(a: __m256d, k: __mmask8, b: __m256d, c: __m256d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fnmsub_pd&expand=2758) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm256_maskz_fnmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fnmsub_pd(a, b, c), _mm256_setzero_pd()) } @@ -4846,7 +4846,7 @@ pub fn _mm256_maskz_fnmsub_pd(k: __mmask8, a: __m256d, b: __m256d, c: __m256d) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask3_fnmsub_pd&expand=2757) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm256_mask3_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) -> __m256d { unsafe { simd_select_bitmask(k, _mm256_fnmsub_pd(a, b, c), c) } @@ -4857,7 +4857,7 @@ pub fn _mm256_mask3_fnmsub_pd(a: __m256d, b: __m256d, c: __m256d, k: __mmask8) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fnmsub_pd&expand=2752) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm_mask_fnmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fnmsub_pd(a, b, c), a) } @@ -4868,7 +4868,7 @@ pub fn _mm_mask_fnmsub_pd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fnmsub_pd&expand=2754) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm_maskz_fnmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fnmsub_pd(a, b, c), _mm_setzero_pd()) } @@ -4879,7 +4879,7 @@ pub fn _mm_maskz_fnmsub_pd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask3_fnmsub_pd&expand=2753) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd pub fn _mm_mask3_fnmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { simd_select_bitmask(k, _mm_fnmsub_pd(a, b, c), c) } @@ -4890,7 +4890,7 @@ pub fn _mm_mask3_fnmsub_pd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rcp14_ps&expand=4502) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm512_rcp14_ps(a: __m512) -> __m512 { unsafe { transmute(vrcp14ps(a.as_f32x16(), f32x16::ZERO, 0b11111111_11111111)) } @@ -4901,7 +4901,7 @@ pub fn _mm512_rcp14_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rcp14_ps&expand=4500) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm512_mask_rcp14_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { transmute(vrcp14ps(a.as_f32x16(), src.as_f32x16(), k)) } @@ -4912,7 +4912,7 @@ pub fn _mm512_mask_rcp14_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rcp14_ps&expand=4501) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm512_maskz_rcp14_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { transmute(vrcp14ps(a.as_f32x16(), f32x16::ZERO, k)) } @@ -4923,7 +4923,7 @@ pub fn _mm512_maskz_rcp14_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rcp14_ps&expand=4499) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm256_rcp14_ps(a: __m256) -> __m256 { unsafe { transmute(vrcp14ps256(a.as_f32x8(), f32x8::ZERO, 0b11111111)) } @@ -4934,7 +4934,7 @@ pub fn _mm256_rcp14_ps(a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rcp14_ps&expand=4497) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm256_mask_rcp14_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vrcp14ps256(a.as_f32x8(), src.as_f32x8(), k)) } @@ -4945,7 +4945,7 @@ pub fn _mm256_mask_rcp14_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rcp14_ps&expand=4498) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm256_maskz_rcp14_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vrcp14ps256(a.as_f32x8(), f32x8::ZERO, k)) } @@ -4956,7 +4956,7 @@ pub fn _mm256_maskz_rcp14_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rcp14_ps&expand=4496) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm_rcp14_ps(a: __m128) -> __m128 { unsafe { transmute(vrcp14ps128(a.as_f32x4(), f32x4::ZERO, 0b00001111)) } @@ -4967,7 +4967,7 @@ pub fn _mm_rcp14_ps(a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rcp14_ps&expand=4494) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm_mask_rcp14_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vrcp14ps128(a.as_f32x4(), src.as_f32x4(), k)) } @@ -4978,7 +4978,7 @@ pub fn _mm_mask_rcp14_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rcp14_ps&expand=4495) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ps))] pub fn _mm_maskz_rcp14_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vrcp14ps128(a.as_f32x4(), f32x4::ZERO, k)) } @@ -4989,7 +4989,7 @@ pub fn _mm_maskz_rcp14_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rcp14_pd&expand=4493) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm512_rcp14_pd(a: __m512d) -> __m512d { unsafe { transmute(vrcp14pd(a.as_f64x8(), f64x8::ZERO, 0b11111111)) } @@ -5000,7 +5000,7 @@ pub fn _mm512_rcp14_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rcp14_pd&expand=4491) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm512_mask_rcp14_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { transmute(vrcp14pd(a.as_f64x8(), src.as_f64x8(), k)) } @@ -5011,7 +5011,7 @@ pub fn _mm512_mask_rcp14_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rcp14_pd&expand=4492) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm512_maskz_rcp14_pd(k: __mmask8, a: __m512d) -> __m512d { unsafe { transmute(vrcp14pd(a.as_f64x8(), f64x8::ZERO, k)) } @@ -5022,7 +5022,7 @@ pub fn _mm512_maskz_rcp14_pd(k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rcp14_pd&expand=4490) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm256_rcp14_pd(a: __m256d) -> __m256d { unsafe { transmute(vrcp14pd256(a.as_f64x4(), f64x4::ZERO, 0b00001111)) } @@ -5033,7 +5033,7 @@ pub fn _mm256_rcp14_pd(a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rcp14_pd&expand=4488) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm256_mask_rcp14_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vrcp14pd256(a.as_f64x4(), src.as_f64x4(), k)) } @@ -5044,7 +5044,7 @@ pub fn _mm256_mask_rcp14_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rcp14_pd&expand=4489) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm256_maskz_rcp14_pd(k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vrcp14pd256(a.as_f64x4(), f64x4::ZERO, k)) } @@ -5055,7 +5055,7 @@ pub fn _mm256_maskz_rcp14_pd(k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rcp14_pd&expand=4487) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm_rcp14_pd(a: __m128d) -> __m128d { unsafe { transmute(vrcp14pd128(a.as_f64x2(), f64x2::ZERO, 0b00000011)) } @@ -5066,7 +5066,7 @@ pub fn _mm_rcp14_pd(a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rcp14_pd&expand=4485) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm_mask_rcp14_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vrcp14pd128(a.as_f64x2(), src.as_f64x2(), k)) } @@ -5077,7 +5077,7 @@ pub fn _mm_mask_rcp14_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rcp14_pd&expand=4486) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14pd))] pub fn _mm_maskz_rcp14_pd(k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vrcp14pd128(a.as_f64x2(), f64x2::ZERO, k)) } @@ -5088,7 +5088,7 @@ pub fn _mm_maskz_rcp14_pd(k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rsqrt14_ps&expand=4819) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm512_rsqrt14_ps(a: __m512) -> __m512 { unsafe { transmute(vrsqrt14ps(a.as_f32x16(), f32x16::ZERO, 0b11111111_11111111)) } @@ -5099,7 +5099,7 @@ pub fn _mm512_rsqrt14_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rsqrt14_ps&expand=4817) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm512_mask_rsqrt14_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { transmute(vrsqrt14ps(a.as_f32x16(), src.as_f32x16(), k)) } @@ -5110,7 +5110,7 @@ pub fn _mm512_mask_rsqrt14_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rsqrt14_ps&expand=4818) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm512_maskz_rsqrt14_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { transmute(vrsqrt14ps(a.as_f32x16(), f32x16::ZERO, k)) } @@ -5121,7 +5121,7 @@ pub fn _mm512_maskz_rsqrt14_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rsqrt14_ps) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm256_rsqrt14_ps(a: __m256) -> __m256 { unsafe { transmute(vrsqrt14ps256(a.as_f32x8(), f32x8::ZERO, 0b11111111)) } @@ -5132,7 +5132,7 @@ pub fn _mm256_rsqrt14_ps(a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rsqrt14_ps&expand=4815) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm256_mask_rsqrt14_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vrsqrt14ps256(a.as_f32x8(), src.as_f32x8(), k)) } @@ -5143,7 +5143,7 @@ pub fn _mm256_mask_rsqrt14_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rsqrt14_ps&expand=4816) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm256_maskz_rsqrt14_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vrsqrt14ps256(a.as_f32x8(), f32x8::ZERO, k)) } @@ -5154,7 +5154,7 @@ pub fn _mm256_maskz_rsqrt14_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rsqrt14_ps) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm_rsqrt14_ps(a: __m128) -> __m128 { unsafe { transmute(vrsqrt14ps128(a.as_f32x4(), f32x4::ZERO, 0b00001111)) } @@ -5165,7 +5165,7 @@ pub fn _mm_rsqrt14_ps(a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rsqrt14_ps&expand=4813) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm_mask_rsqrt14_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vrsqrt14ps128(a.as_f32x4(), src.as_f32x4(), k)) } @@ -5176,7 +5176,7 @@ pub fn _mm_mask_rsqrt14_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rsqrt14_ps&expand=4814) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ps))] pub fn _mm_maskz_rsqrt14_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vrsqrt14ps128(a.as_f32x4(), f32x4::ZERO, k)) } @@ -5187,7 +5187,7 @@ pub fn _mm_maskz_rsqrt14_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rsqrt14_pd&expand=4812) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm512_rsqrt14_pd(a: __m512d) -> __m512d { unsafe { transmute(vrsqrt14pd(a.as_f64x8(), f64x8::ZERO, 0b11111111)) } @@ -5198,7 +5198,7 @@ pub fn _mm512_rsqrt14_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rsqrt14_pd&expand=4810) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm512_mask_rsqrt14_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { transmute(vrsqrt14pd(a.as_f64x8(), src.as_f64x8(), k)) } @@ -5209,7 +5209,7 @@ pub fn _mm512_mask_rsqrt14_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rsqrt14_pd&expand=4811) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm512_maskz_rsqrt14_pd(k: __mmask8, a: __m512d) -> __m512d { unsafe { transmute(vrsqrt14pd(a.as_f64x8(), f64x8::ZERO, k)) } @@ -5220,7 +5220,7 @@ pub fn _mm512_maskz_rsqrt14_pd(k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rsqrt14_pd) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm256_rsqrt14_pd(a: __m256d) -> __m256d { unsafe { transmute(vrsqrt14pd256(a.as_f64x4(), f64x4::ZERO, 0b00001111)) } @@ -5231,7 +5231,7 @@ pub fn _mm256_rsqrt14_pd(a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rsqrt14_pd&expand=4808) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm256_mask_rsqrt14_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vrsqrt14pd256(a.as_f64x4(), src.as_f64x4(), k)) } @@ -5242,7 +5242,7 @@ pub fn _mm256_mask_rsqrt14_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rsqrt14_pd&expand=4809) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm256_maskz_rsqrt14_pd(k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vrsqrt14pd256(a.as_f64x4(), f64x4::ZERO, k)) } @@ -5253,7 +5253,7 @@ pub fn _mm256_maskz_rsqrt14_pd(k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rsqrt14_pd) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm_rsqrt14_pd(a: __m128d) -> __m128d { unsafe { transmute(vrsqrt14pd128(a.as_f64x2(), f64x2::ZERO, 0b00000011)) } @@ -5264,7 +5264,7 @@ pub fn _mm_rsqrt14_pd(a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rsqrt14_pd&expand=4806) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm_mask_rsqrt14_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vrsqrt14pd128(a.as_f64x2(), src.as_f64x2(), k)) } @@ -5275,7 +5275,7 @@ pub fn _mm_mask_rsqrt14_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rsqrt14_pd&expand=4807) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14pd))] pub fn _mm_maskz_rsqrt14_pd(k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vrsqrt14pd128(a.as_f64x2(), f64x2::ZERO, k)) } @@ -5286,7 +5286,7 @@ pub fn _mm_maskz_rsqrt14_pd(k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_getexp_ps&expand=2844) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm512_getexp_ps(a: __m512) -> __m512 { unsafe { @@ -5304,7 +5304,7 @@ pub fn _mm512_getexp_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_getexp_ps&expand=2845) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm512_mask_getexp_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { @@ -5322,7 +5322,7 @@ pub fn _mm512_mask_getexp_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_getexp_ps&expand=2846) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm512_maskz_getexp_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { @@ -5340,7 +5340,7 @@ pub fn _mm512_maskz_getexp_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_getexp_ps&expand=2841) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm256_getexp_ps(a: __m256) -> __m256 { unsafe { transmute(vgetexpps256(a.as_f32x8(), f32x8::ZERO, 0b11111111)) } @@ -5351,7 +5351,7 @@ pub fn _mm256_getexp_ps(a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_getexp_ps&expand=2842) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm256_mask_getexp_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vgetexpps256(a.as_f32x8(), src.as_f32x8(), k)) } @@ -5362,7 +5362,7 @@ pub fn _mm256_mask_getexp_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_getexp_ps&expand=2843) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm256_maskz_getexp_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vgetexpps256(a.as_f32x8(), f32x8::ZERO, k)) } @@ -5373,7 +5373,7 @@ pub fn _mm256_maskz_getexp_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_getexp_ps&expand=2838) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm_getexp_ps(a: __m128) -> __m128 { unsafe { transmute(vgetexpps128(a.as_f32x4(), f32x4::ZERO, 0b00001111)) } @@ -5384,7 +5384,7 @@ pub fn _mm_getexp_ps(a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_getexp_ps&expand=2839) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm_mask_getexp_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vgetexpps128(a.as_f32x4(), src.as_f32x4(), k)) } @@ -5395,7 +5395,7 @@ pub fn _mm_mask_getexp_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_getexp_ps&expand=2840) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps))] pub fn _mm_maskz_getexp_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vgetexpps128(a.as_f32x4(), f32x4::ZERO, k)) } @@ -5406,7 +5406,7 @@ pub fn _mm_maskz_getexp_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_getexp_pd&expand=2835) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm512_getexp_pd(a: __m512d) -> __m512d { unsafe { @@ -5424,7 +5424,7 @@ pub fn _mm512_getexp_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_getexp_pd&expand=2836) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm512_mask_getexp_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { @@ -5442,7 +5442,7 @@ pub fn _mm512_mask_getexp_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_getexp_pd&expand=2837) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm512_maskz_getexp_pd(k: __mmask8, a: __m512d) -> __m512d { unsafe { @@ -5460,7 +5460,7 @@ pub fn _mm512_maskz_getexp_pd(k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_getexp_pd&expand=2832) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm256_getexp_pd(a: __m256d) -> __m256d { unsafe { transmute(vgetexppd256(a.as_f64x4(), f64x4::ZERO, 0b00001111)) } @@ -5471,7 +5471,7 @@ pub fn _mm256_getexp_pd(a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_getexp_pd&expand=2833) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm256_mask_getexp_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vgetexppd256(a.as_f64x4(), src.as_f64x4(), k)) } @@ -5482,7 +5482,7 @@ pub fn _mm256_mask_getexp_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_getexp_pd&expand=2834) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm256_maskz_getexp_pd(k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vgetexppd256(a.as_f64x4(), f64x4::ZERO, k)) } @@ -5493,7 +5493,7 @@ pub fn _mm256_maskz_getexp_pd(k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_getexp_pd&expand=2829) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm_getexp_pd(a: __m128d) -> __m128d { unsafe { transmute(vgetexppd128(a.as_f64x2(), f64x2::ZERO, 0b00000011)) } @@ -5504,7 +5504,7 @@ pub fn _mm_getexp_pd(a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_getexp_pd&expand=2830) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm_mask_getexp_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vgetexppd128(a.as_f64x2(), src.as_f64x2(), k)) } @@ -5515,7 +5515,7 @@ pub fn _mm_mask_getexp_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_getexp_pd&expand=2831) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd))] pub fn _mm_maskz_getexp_pd(k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vgetexppd128(a.as_f64x2(), f64x2::ZERO, k)) } @@ -5532,7 +5532,7 @@ pub fn _mm_maskz_getexp_pd(k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_roundscale_ps&expand=4784) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0))] #[rustc_legacy_const_generics(1)] pub fn _mm512_roundscale_ps(a: __m512) -> __m512 { @@ -5561,7 +5561,7 @@ pub fn _mm512_roundscale_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_roundscale_ps&expand=4782) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_roundscale_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { @@ -5585,7 +5585,7 @@ pub fn _mm512_mask_roundscale_ps(src: __m512, k: __mmask16, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_roundscale_ps&expand=4783) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_roundscale_ps(k: __mmask16, a: __m512) -> __m512 { @@ -5608,7 +5608,7 @@ pub fn _mm512_maskz_roundscale_ps(k: __mmask16, a: __m512) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_roundscale_ps&expand=4781) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 250))] #[rustc_legacy_const_generics(1)] pub fn _mm256_roundscale_ps(a: __m256) -> __m256 { @@ -5631,7 +5631,7 @@ pub fn _mm256_roundscale_ps(a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_roundscale_ps&expand=4779) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_roundscale_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { @@ -5655,7 +5655,7 @@ pub fn _mm256_mask_roundscale_ps(src: __m256, k: __mmask8, a: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_roundscale_ps&expand=4780) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_roundscale_ps(k: __mmask8, a: __m256) -> __m256 { @@ -5678,7 +5678,7 @@ pub fn _mm256_maskz_roundscale_ps(k: __mmask8, a: __m256) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_roundscale_ps&expand=4778) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 250))] #[rustc_legacy_const_generics(1)] pub fn _mm_roundscale_ps(a: __m128) -> __m128 { @@ -5701,7 +5701,7 @@ pub fn _mm_roundscale_ps(a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_roundscale_ps&expand=4776) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_roundscale_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { @@ -5725,7 +5725,7 @@ pub fn _mm_mask_roundscale_ps(src: __m128, k: __mmask8, a: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_roundscale_ps&expand=4777) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_roundscale_ps(k: __mmask8, a: __m128) -> __m128 { @@ -5748,7 +5748,7 @@ pub fn _mm_maskz_roundscale_ps(k: __mmask8, a: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_roundscale_pd&expand=4775) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] pub fn _mm512_roundscale_pd(a: __m512d) -> __m512d { @@ -5771,7 +5771,7 @@ pub fn _mm512_roundscale_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_roundscale_pd&expand=4773) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_roundscale_pd( @@ -5799,7 +5799,7 @@ pub fn _mm512_mask_roundscale_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_roundscale_pd&expand=4774) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_roundscale_pd(k: __mmask8, a: __m512d) -> __m512d { @@ -5822,7 +5822,7 @@ pub fn _mm512_maskz_roundscale_pd(k: __mmask8, a: __m512d) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_roundscale_pd&expand=4772) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] pub fn _mm256_roundscale_pd(a: __m256d) -> __m256d { @@ -5845,7 +5845,7 @@ pub fn _mm256_roundscale_pd(a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_roundscale_pd&expand=4770) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_roundscale_pd( @@ -5873,7 +5873,7 @@ pub fn _mm256_mask_roundscale_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_roundscale_pd&expand=4771) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_roundscale_pd(k: __mmask8, a: __m256d) -> __m256d { @@ -5896,7 +5896,7 @@ pub fn _mm256_maskz_roundscale_pd(k: __mmask8, a: __m256d) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_roundscale_pd&expand=4769) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(1)] pub fn _mm_roundscale_pd(a: __m128d) -> __m128d { @@ -5919,7 +5919,7 @@ pub fn _mm_roundscale_pd(a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_roundscale_pd&expand=4767) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_roundscale_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { @@ -5943,7 +5943,7 @@ pub fn _mm_mask_roundscale_pd(src: __m128d, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_roundscale_pd&expand=4768) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_roundscale_pd(k: __mmask8, a: __m128d) -> __m128d { @@ -5960,7 +5960,7 @@ pub fn _mm_maskz_roundscale_pd(k: __mmask8, a: __m128d) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_scalef_ps&expand=4883) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm512_scalef_ps(a: __m512, b: __m512) -> __m512 { unsafe { @@ -5979,7 +5979,7 @@ pub fn _mm512_scalef_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_scalef_ps&expand=4881) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm512_mask_scalef_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -5998,7 +5998,7 @@ pub fn _mm512_mask_scalef_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_scalef_ps&expand=4882) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm512_maskz_scalef_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -6017,7 +6017,7 @@ pub fn _mm512_maskz_scalef_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_scalef_ps&expand=4880) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm256_scalef_ps(a: __m256, b: __m256) -> __m256 { unsafe { @@ -6035,7 +6035,7 @@ pub fn _mm256_scalef_ps(a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_scalef_ps&expand=4878) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm256_mask_scalef_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { transmute(vscalefps256(a.as_f32x8(), b.as_f32x8(), src.as_f32x8(), k)) } @@ -6046,7 +6046,7 @@ pub fn _mm256_mask_scalef_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_scalef_ps&expand=4879) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm256_maskz_scalef_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { transmute(vscalefps256(a.as_f32x8(), b.as_f32x8(), f32x8::ZERO, k)) } @@ -6057,7 +6057,7 @@ pub fn _mm256_maskz_scalef_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_scalef_ps&expand=4877) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm_scalef_ps(a: __m128, b: __m128) -> __m128 { unsafe { @@ -6075,7 +6075,7 @@ pub fn _mm_scalef_ps(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_scalef_ps&expand=4875) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm_mask_scalef_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { transmute(vscalefps128(a.as_f32x4(), b.as_f32x4(), src.as_f32x4(), k)) } @@ -6086,7 +6086,7 @@ pub fn _mm_mask_scalef_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_scalef_ps&expand=4876) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps))] pub fn _mm_maskz_scalef_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { transmute(vscalefps128(a.as_f32x4(), b.as_f32x4(), f32x4::ZERO, k)) } @@ -6097,7 +6097,7 @@ pub fn _mm_maskz_scalef_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_scalef_pd&expand=4874) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm512_scalef_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -6116,7 +6116,7 @@ pub fn _mm512_scalef_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_scalef_pd&expand=4872) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm512_mask_scalef_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -6135,7 +6135,7 @@ pub fn _mm512_mask_scalef_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_scalef_pd&expand=4873) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm512_maskz_scalef_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -6154,7 +6154,7 @@ pub fn _mm512_maskz_scalef_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_scalef_pd&expand=4871) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm256_scalef_pd(a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -6172,7 +6172,7 @@ pub fn _mm256_scalef_pd(a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_scalef_pd&expand=4869) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm256_mask_scalef_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { transmute(vscalefpd256(a.as_f64x4(), b.as_f64x4(), src.as_f64x4(), k)) } @@ -6183,7 +6183,7 @@ pub fn _mm256_mask_scalef_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_scalef_pd&expand=4870) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm256_maskz_scalef_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { transmute(vscalefpd256(a.as_f64x4(), b.as_f64x4(), f64x4::ZERO, k)) } @@ -6194,7 +6194,7 @@ pub fn _mm256_maskz_scalef_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_scalef_pd&expand=4868) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm_scalef_pd(a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -6212,7 +6212,7 @@ pub fn _mm_scalef_pd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_scalef_pd&expand=4866) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm_mask_scalef_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(vscalefpd128(a.as_f64x2(), b.as_f64x2(), src.as_f64x2(), k)) } @@ -6223,7 +6223,7 @@ pub fn _mm_mask_scalef_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_scalef_pd&expand=4867) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd))] pub fn _mm_maskz_scalef_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(vscalefpd128(a.as_f64x2(), b.as_f64x2(), f64x2::ZERO, k)) } @@ -6234,7 +6234,7 @@ pub fn _mm_maskz_scalef_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fixupimm_ps&expand=2499) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm512_fixupimm_ps(a: __m512, b: __m512, c: __m512i) -> __m512 { @@ -6253,7 +6253,7 @@ pub fn _mm512_fixupimm_ps(a: __m512, b: __m512, c: __m512i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fixupimm_ps&expand=2500) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fixupimm_ps( @@ -6277,7 +6277,7 @@ pub fn _mm512_mask_fixupimm_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fixupimm_ps&expand=2501) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fixupimm_ps( @@ -6301,7 +6301,7 @@ pub fn _mm512_maskz_fixupimm_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_fixupimm_ps&expand=2496) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm256_fixupimm_ps(a: __m256, b: __m256, c: __m256i) -> __m256 { @@ -6320,7 +6320,7 @@ pub fn _mm256_fixupimm_ps(a: __m256, b: __m256, c: __m256i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fixupimm_ps&expand=2497) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_fixupimm_ps( @@ -6344,7 +6344,7 @@ pub fn _mm256_mask_fixupimm_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fixupimm_ps&expand=2498) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm256_maskz_fixupimm_ps( @@ -6368,7 +6368,7 @@ pub fn _mm256_maskz_fixupimm_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_fixupimm_ps&expand=2493) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_fixupimm_ps(a: __m128, b: __m128, c: __m128i) -> __m128 { @@ -6387,7 +6387,7 @@ pub fn _mm_fixupimm_ps(a: __m128, b: __m128, c: __m128i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fixupimm_ps&expand=2494) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fixupimm_ps( @@ -6411,7 +6411,7 @@ pub fn _mm_mask_fixupimm_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fixupimm_ps&expand=2495) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fixupimm_ps( @@ -6435,7 +6435,7 @@ pub fn _mm_maskz_fixupimm_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fixupimm_pd&expand=2490) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm512_fixupimm_pd(a: __m512d, b: __m512d, c: __m512i) -> __m512d { @@ -6454,7 +6454,7 @@ pub fn _mm512_fixupimm_pd(a: __m512d, b: __m512d, c: __m512i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fixupimm_pd&expand=2491) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fixupimm_pd( @@ -6478,7 +6478,7 @@ pub fn _mm512_mask_fixupimm_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fixupimm_pd&expand=2492) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fixupimm_pd( @@ -6502,7 +6502,7 @@ pub fn _mm512_maskz_fixupimm_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_fixupimm_pd&expand=2487) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm256_fixupimm_pd(a: __m256d, b: __m256d, c: __m256i) -> __m256d { @@ -6521,7 +6521,7 @@ pub fn _mm256_fixupimm_pd(a: __m256d, b: __m256d, c: __m256i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_fixupimm_pd&expand=2488) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_fixupimm_pd( @@ -6545,7 +6545,7 @@ pub fn _mm256_mask_fixupimm_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_fixupimm_pd&expand=2489) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm256_maskz_fixupimm_pd( @@ -6569,7 +6569,7 @@ pub fn _mm256_maskz_fixupimm_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_fixupimm_pd&expand=2484) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_fixupimm_pd(a: __m128d, b: __m128d, c: __m128i) -> __m128d { @@ -6588,7 +6588,7 @@ pub fn _mm_fixupimm_pd(a: __m128d, b: __m128d, c: __m128i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_fixupimm_pd&expand=2485) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fixupimm_pd( @@ -6612,7 +6612,7 @@ pub fn _mm_mask_fixupimm_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_fixupimm_pd&expand=2486) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fixupimm_pd( @@ -6636,7 +6636,7 @@ pub fn _mm_maskz_fixupimm_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_ternarylogic_epi32&expand=5867) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(3)] pub fn _mm512_ternarylogic_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i { @@ -6655,7 +6655,7 @@ pub fn _mm512_ternarylogic_epi32(a: __m512i, b: __m512i, c: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_ternarylogic_epi32&expand=5865) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_ternarylogic_epi32( @@ -6679,7 +6679,7 @@ pub fn _mm512_mask_ternarylogic_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_ternarylogic_epi32&expand=5866) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_ternarylogic_epi32( @@ -6703,7 +6703,7 @@ pub fn _mm512_maskz_ternarylogic_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_ternarylogic_epi32&expand=5864) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(3)] pub fn _mm256_ternarylogic_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i { @@ -6722,7 +6722,7 @@ pub fn _mm256_ternarylogic_epi32(a: __m256i, b: __m256i, c: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_ternarylogic_epi32&expand=5862) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_ternarylogic_epi32( @@ -6746,7 +6746,7 @@ pub fn _mm256_mask_ternarylogic_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_ternarylogic_epi32&expand=5863) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm256_maskz_ternarylogic_epi32( @@ -6770,7 +6770,7 @@ pub fn _mm256_maskz_ternarylogic_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ternarylogic_epi32&expand=5861) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(3)] pub fn _mm_ternarylogic_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i { @@ -6789,7 +6789,7 @@ pub fn _mm_ternarylogic_epi32(a: __m128i, b: __m128i, c: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_ternarylogic_epi32&expand=5859) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_ternarylogic_epi32( @@ -6813,7 +6813,7 @@ pub fn _mm_mask_ternarylogic_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_ternarylogic_epi32&expand=5860) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogd, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_ternarylogic_epi32( @@ -6837,7 +6837,7 @@ pub fn _mm_maskz_ternarylogic_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_ternarylogic_epi64&expand=5876) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(3)] pub fn _mm512_ternarylogic_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { @@ -6856,7 +6856,7 @@ pub fn _mm512_ternarylogic_epi64(a: __m512i, b: __m512i, c: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_ternarylogic_epi64&expand=5874) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_ternarylogic_epi64( @@ -6880,7 +6880,7 @@ pub fn _mm512_mask_ternarylogic_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_ternarylogic_epi64&expand=5875) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_ternarylogic_epi64( @@ -6904,7 +6904,7 @@ pub fn _mm512_maskz_ternarylogic_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_ternarylogic_epi64&expand=5873) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(3)] pub fn _mm256_ternarylogic_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { @@ -6923,7 +6923,7 @@ pub fn _mm256_ternarylogic_epi64(a: __m256i, b: __m256i, c: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_ternarylogic_epi64&expand=5871) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_ternarylogic_epi64( @@ -6947,7 +6947,7 @@ pub fn _mm256_mask_ternarylogic_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_ternarylogic_epi64&expand=5872) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm256_maskz_ternarylogic_epi64( @@ -6971,7 +6971,7 @@ pub fn _mm256_maskz_ternarylogic_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ternarylogic_epi64&expand=5870) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(3)] pub fn _mm_ternarylogic_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { @@ -6990,7 +6990,7 @@ pub fn _mm_ternarylogic_epi64(a: __m128i, b: __m128i, c: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_ternarylogic_epi64&expand=5868) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_ternarylogic_epi64( @@ -7014,7 +7014,7 @@ pub fn _mm_mask_ternarylogic_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_ternarylogic_epi64&expand=5869) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpternlogq, IMM8 = 114))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_ternarylogic_epi64( @@ -7047,7 +7047,7 @@ pub fn _mm_maskz_ternarylogic_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_getmant_ps&expand=2880) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] #[rustc_legacy_const_generics(1, 2)] pub fn _mm512_getmant_ps( @@ -7083,7 +7083,7 @@ pub fn _mm512_getmant_ps( @@ -7186,7 +7186,7 @@ pub fn _mm256_getmant_ps( @@ -7283,7 +7283,7 @@ pub fn _mm_getmant_ps( @@ -7387,7 +7387,7 @@ pub fn _mm512_getmant_pd( @@ -7490,7 +7490,7 @@ pub fn _mm256_getmant_pd( @@ -7587,7 +7587,7 @@ pub fn _mm_getmant_pd(a: __m512, b: __m512) -> __m512 { @@ -7678,7 +7678,7 @@ pub fn _mm512_add_round_ps(a: __m512, b: __m512) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_round_ps&expand=146) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_add_round_ps( @@ -7708,7 +7708,7 @@ pub fn _mm512_mask_add_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_round_ps&expand=147) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_add_round_ps( @@ -7737,7 +7737,7 @@ pub fn _mm512_maskz_add_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_round_pd&expand=142) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_add_round_pd(a: __m512d, b: __m512d) -> __m512d { @@ -7762,7 +7762,7 @@ pub fn _mm512_add_round_pd(a: __m512d, b: __m512d) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_round_pd&expand=143) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_add_round_pd( @@ -7792,7 +7792,7 @@ pub fn _mm512_mask_add_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_round_pd&expand=144) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddpd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_add_round_pd( @@ -7821,7 +7821,7 @@ pub fn _mm512_maskz_add_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_round_ps&expand=5739) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_sub_round_ps(a: __m512, b: __m512) -> __m512 { @@ -7846,7 +7846,7 @@ pub fn _mm512_sub_round_ps(a: __m512, b: __m512) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_round_ps&expand=5737) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_sub_round_ps( @@ -7876,7 +7876,7 @@ pub fn _mm512_mask_sub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_round_ps&expand=5738) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_sub_round_ps( @@ -7905,7 +7905,7 @@ pub fn _mm512_maskz_sub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_round_pd&expand=5736) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_sub_round_pd(a: __m512d, b: __m512d) -> __m512d { @@ -7930,7 +7930,7 @@ pub fn _mm512_sub_round_pd(a: __m512d, b: __m512d) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_round_pd&expand=5734) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_sub_round_pd( @@ -7960,7 +7960,7 @@ pub fn _mm512_mask_sub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_round_pd&expand=5735) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubpd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_sub_round_pd( @@ -7989,7 +7989,7 @@ pub fn _mm512_maskz_sub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mul_round_ps&expand=3940) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_mul_round_ps(a: __m512, b: __m512) -> __m512 { @@ -8014,7 +8014,7 @@ pub fn _mm512_mul_round_ps(a: __m512, b: __m512) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mul_round_ps&expand=3938) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_mul_round_ps( @@ -8044,7 +8044,7 @@ pub fn _mm512_mask_mul_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mul_round_ps&expand=3939) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_mul_round_ps( @@ -8073,7 +8073,7 @@ pub fn _mm512_maskz_mul_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mul_round_pd&expand=3937) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_mul_round_pd(a: __m512d, b: __m512d) -> __m512d { @@ -8098,7 +8098,7 @@ pub fn _mm512_mul_round_pd(a: __m512d, b: __m512d) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mul_round_pd&expand=3935) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_mul_round_pd( @@ -8128,7 +8128,7 @@ pub fn _mm512_mask_mul_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mul_round_pd&expand=3939) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulpd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_mul_round_pd( @@ -8157,7 +8157,7 @@ pub fn _mm512_maskz_mul_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_div_round_ps&expand=2168) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_div_round_ps(a: __m512, b: __m512) -> __m512 { @@ -8182,7 +8182,7 @@ pub fn _mm512_div_round_ps(a: __m512, b: __m512) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_div_round_ps&expand=2169) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_div_round_ps( @@ -8212,7 +8212,7 @@ pub fn _mm512_mask_div_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_div_round_ps&expand=2170) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_div_round_ps( @@ -8241,7 +8241,7 @@ pub fn _mm512_maskz_div_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_div_round_pd&expand=2165) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_div_round_pd(a: __m512d, b: __m512d) -> __m512d { @@ -8266,7 +8266,7 @@ pub fn _mm512_div_round_pd(a: __m512d, b: __m512d) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_div_round_pd&expand=2166) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_div_round_pd( @@ -8296,7 +8296,7 @@ pub fn _mm512_mask_div_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_div_round_pd&expand=2167) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivpd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_div_round_pd( @@ -8325,7 +8325,7 @@ pub fn _mm512_maskz_div_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sqrt_round_ps&expand=5377) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_sqrt_round_ps(a: __m512) -> __m512 { @@ -8349,7 +8349,7 @@ pub fn _mm512_sqrt_round_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sqrt_round_ps&expand=5375) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_sqrt_round_ps( @@ -8377,7 +8377,7 @@ pub fn _mm512_mask_sqrt_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sqrt_round_ps&expand=5376) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_sqrt_round_ps(k: __mmask16, a: __m512) -> __m512 { @@ -8401,7 +8401,7 @@ pub fn _mm512_maskz_sqrt_round_ps(k: __mmask16, a: __m512) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sqrt_round_pd&expand=5374) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_sqrt_round_pd(a: __m512d) -> __m512d { @@ -8425,7 +8425,7 @@ pub fn _mm512_sqrt_round_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sqrt_round_pd&expand=5372) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_sqrt_round_pd( @@ -8453,7 +8453,7 @@ pub fn _mm512_mask_sqrt_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sqrt_round_pd&expand=5373) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtpd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_sqrt_round_pd(k: __mmask8, a: __m512d) -> __m512d { @@ -8477,7 +8477,7 @@ pub fn _mm512_maskz_sqrt_round_pd(k: __mmask8, a: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmadd_round_ps&expand=2565) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] //vfmadd132ps or vfmadd213ps or vfmadd231ps #[rustc_legacy_const_generics(3)] pub fn _mm512_fmadd_round_ps(a: __m512, b: __m512, c: __m512) -> __m512 { @@ -8499,7 +8499,7 @@ pub fn _mm512_fmadd_round_ps(a: __m512, b: __m512, c: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmadd_round_ps&expand=2566) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] //vfmadd132ps or vfmadd213ps or vfmadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fmadd_round_ps( @@ -8526,7 +8526,7 @@ pub fn _mm512_mask_fmadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmadd_round_ps&expand=2568) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] //vfmadd132ps or vfmadd213ps or vfmadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fmadd_round_ps( @@ -8553,7 +8553,7 @@ pub fn _mm512_maskz_fmadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmadd_round_ps&expand=2567) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] //vfmadd132ps or vfmadd213ps or vfmadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fmadd_round_ps( @@ -8580,7 +8580,7 @@ pub fn _mm512_mask3_fmadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmadd_round_pd&expand=2561) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] //vfmadd132pd or vfmadd213pd or vfmadd231pd #[rustc_legacy_const_generics(3)] pub fn _mm512_fmadd_round_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { @@ -8602,7 +8602,7 @@ pub fn _mm512_fmadd_round_pd(a: __m512d, b: __m512d, c: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmadd_round_pd&expand=2562) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] //vfmadd132pd or vfmadd213pd or vfmadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fmadd_round_pd( @@ -8629,7 +8629,7 @@ pub fn _mm512_mask_fmadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmadd_round_pd&expand=2564) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] //vfmadd132pd or vfmadd213pd or vfmadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fmadd_round_pd( @@ -8656,7 +8656,7 @@ pub fn _mm512_maskz_fmadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmadd_round_pd&expand=2563) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] //vfmadd132pd or vfmadd213pd or vfmadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fmadd_round_pd( @@ -8683,7 +8683,7 @@ pub fn _mm512_mask3_fmadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmsub_round_ps&expand=2651) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generates vfmadd, gcc generates vfmsub #[rustc_legacy_const_generics(3)] pub fn _mm512_fmsub_round_ps(a: __m512, b: __m512, c: __m512) -> __m512 { @@ -8705,7 +8705,7 @@ pub fn _mm512_fmsub_round_ps(a: __m512, b: __m512, c: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmsub_round_ps&expand=2652) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generates vfmadd, gcc generates vfmsub #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fmsub_round_ps( @@ -8733,7 +8733,7 @@ pub fn _mm512_mask_fmsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmsub_round_ps&expand=2654) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generates vfmadd, gcc generates vfmsub #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fmsub_round_ps( @@ -8761,7 +8761,7 @@ pub fn _mm512_maskz_fmsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmsub_round_ps&expand=2653) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] //vfmsub132ps or vfmsub213ps or vfmsub231ps, clang generates vfmadd, gcc generates vfmsub #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fmsub_round_ps( @@ -8789,7 +8789,7 @@ pub fn _mm512_mask3_fmsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmsub_round_pd&expand=2647) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang generates fmadd, gcc generates fmsub #[rustc_legacy_const_generics(3)] pub fn _mm512_fmsub_round_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { @@ -8811,7 +8811,7 @@ pub fn _mm512_fmsub_round_pd(a: __m512d, b: __m512d, c: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmsub_round_pd&expand=2648) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang generates fmadd, gcc generates fmsub #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fmsub_round_pd( @@ -8839,7 +8839,7 @@ pub fn _mm512_mask_fmsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmsub_round_pd&expand=2650) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang generates fmadd, gcc generates fmsub #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fmsub_round_pd( @@ -8867,7 +8867,7 @@ pub fn _mm512_maskz_fmsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmsub_round_pd&expand=2649) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] //vfmsub132pd or vfmsub213pd or vfmsub231pd. clang generates fmadd, gcc generates fmsub #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fmsub_round_pd( @@ -8895,7 +8895,7 @@ pub fn _mm512_mask3_fmsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmaddsub_round_ps&expand=2619) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps #[rustc_legacy_const_generics(3)] pub fn _mm512_fmaddsub_round_ps(a: __m512, b: __m512, c: __m512) -> __m512 { @@ -8917,7 +8917,7 @@ pub fn _mm512_fmaddsub_round_ps(a: __m512, b: __m512, c: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmaddsub_round_ps&expand=2620) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fmaddsub_round_ps( @@ -8944,7 +8944,7 @@ pub fn _mm512_mask_fmaddsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmaddsub_round_ps&expand=2622) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fmaddsub_round_ps( @@ -8971,7 +8971,7 @@ pub fn _mm512_maskz_fmaddsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmaddsub_round_ps&expand=2621) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] //vfmaddsub132ps or vfmaddsub213ps or vfmaddsub231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fmaddsub_round_ps( @@ -8998,7 +8998,7 @@ pub fn _mm512_mask3_fmaddsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmaddsub_round_pd&expand=2615) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd #[rustc_legacy_const_generics(3)] pub fn _mm512_fmaddsub_round_pd( @@ -9024,7 +9024,7 @@ pub fn _mm512_fmaddsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmaddsub_round_pd&expand=2616) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fmaddsub_round_pd( @@ -9051,7 +9051,7 @@ pub fn _mm512_mask_fmaddsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmaddsub_round_pd&expand=2618) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fmaddsub_round_pd( @@ -9078,7 +9078,7 @@ pub fn _mm512_maskz_fmaddsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmaddsub_round_pd&expand=2617) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] //vfmaddsub132pd or vfmaddsub213pd or vfmaddsub231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fmaddsub_round_pd( @@ -9105,7 +9105,7 @@ pub fn _mm512_mask3_fmaddsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmsubadd_round_ps&expand=2699) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps #[rustc_legacy_const_generics(3)] pub fn _mm512_fmsubadd_round_ps(a: __m512, b: __m512, c: __m512) -> __m512 { @@ -9127,7 +9127,7 @@ pub fn _mm512_fmsubadd_round_ps(a: __m512, b: __m512, c: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmsubadd_round_ps&expand=2700) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fmsubadd_round_ps( @@ -9155,7 +9155,7 @@ pub fn _mm512_mask_fmsubadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmsubadd_round_ps&expand=2702) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fmsubadd_round_ps( @@ -9183,7 +9183,7 @@ pub fn _mm512_maskz_fmsubadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmsubadd_round_ps&expand=2701) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] //vfmsubadd132ps or vfmsubadd213ps or vfmsubadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fmsubadd_round_ps( @@ -9211,7 +9211,7 @@ pub fn _mm512_mask3_fmsubadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fmsubadd_round_pd&expand=2695) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd #[rustc_legacy_const_generics(3)] pub fn _mm512_fmsubadd_round_pd( @@ -9237,7 +9237,7 @@ pub fn _mm512_fmsubadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fmsubadd_round_pd&expand=2696) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fmsubadd_round_pd( @@ -9265,7 +9265,7 @@ pub fn _mm512_mask_fmsubadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fmsubadd_round_pd&expand=2698) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fmsubadd_round_pd( @@ -9293,7 +9293,7 @@ pub fn _mm512_maskz_fmsubadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fmsubadd_round_pd&expand=2697) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] //vfmsubadd132pd or vfmsubadd213pd or vfmsubadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fmsubadd_round_pd( @@ -9321,7 +9321,7 @@ pub fn _mm512_mask3_fmsubadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fnmadd_round_ps&expand=2731) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps #[rustc_legacy_const_generics(3)] pub fn _mm512_fnmadd_round_ps(a: __m512, b: __m512, c: __m512) -> __m512 { @@ -9343,7 +9343,7 @@ pub fn _mm512_fnmadd_round_ps(a: __m512, b: __m512, c: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fnmadd_round_ps&expand=2732) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fnmadd_round_ps( @@ -9371,7 +9371,7 @@ pub fn _mm512_mask_fnmadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fnmadd_round_ps&expand=2734) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fnmadd_round_ps( @@ -9399,7 +9399,7 @@ pub fn _mm512_maskz_fnmadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fnmadd_round_ps&expand=2733) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] //vfnmadd132ps or vfnmadd213ps or vfnmadd231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fnmadd_round_ps( @@ -9427,7 +9427,7 @@ pub fn _mm512_mask3_fnmadd_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fnmadd_round_pd&expand=2711) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd #[rustc_legacy_const_generics(3)] pub fn _mm512_fnmadd_round_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { @@ -9449,7 +9449,7 @@ pub fn _mm512_fnmadd_round_pd(a: __m512d, b: __m512d, c: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fnmadd_round_pd&expand=2728) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fnmadd_round_pd( @@ -9477,7 +9477,7 @@ pub fn _mm512_mask_fnmadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fnmadd_round_pd&expand=2730) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fnmadd_round_pd( @@ -9505,7 +9505,7 @@ pub fn _mm512_maskz_fnmadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fnmadd_round_pd&expand=2729) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] //vfnmadd132pd or vfnmadd213pd or vfnmadd231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fnmadd_round_pd( @@ -9533,7 +9533,7 @@ pub fn _mm512_mask3_fnmadd_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fnmsub_round_ps&expand=2779) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps #[rustc_legacy_const_generics(3)] pub fn _mm512_fnmsub_round_ps(a: __m512, b: __m512, c: __m512) -> __m512 { @@ -9555,7 +9555,7 @@ pub fn _mm512_fnmsub_round_ps(a: __m512, b: __m512, c: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fnmsub_round_ps&expand=2780) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fnmsub_round_ps( @@ -9583,7 +9583,7 @@ pub fn _mm512_mask_fnmsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fnmsub_round_ps&expand=2782) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fnmsub_round_ps( @@ -9611,7 +9611,7 @@ pub fn _mm512_maskz_fnmsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fnmsub_round_ps&expand=2781) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] //vfnmsub132ps or vfnmsub213ps or vfnmsub231ps #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fnmsub_round_ps( @@ -9639,7 +9639,7 @@ pub fn _mm512_mask3_fnmsub_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fnmsub_round_pd&expand=2775) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd #[rustc_legacy_const_generics(3)] pub fn _mm512_fnmsub_round_pd(a: __m512d, b: __m512d, c: __m512d) -> __m512d { @@ -9661,7 +9661,7 @@ pub fn _mm512_fnmsub_round_pd(a: __m512d, b: __m512d, c: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fnmsub_round_pd&expand=2776) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_fnmsub_round_pd( @@ -9689,7 +9689,7 @@ pub fn _mm512_mask_fnmsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fnmsub_round_pd&expand=2778) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_maskz_fnmsub_round_pd( @@ -9717,7 +9717,7 @@ pub fn _mm512_maskz_fnmsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask3_fnmsub_round_pd&expand=2777) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] //vfnmsub132pd or vfnmsub213pd or vfnmsub231pd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask3_fnmsub_round_pd( @@ -9739,7 +9739,7 @@ pub fn _mm512_mask3_fnmsub_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_round_ps&expand=3662) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_max_round_ps(a: __m512, b: __m512) -> __m512 { @@ -9758,7 +9758,7 @@ pub fn _mm512_max_round_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_round_ps&expand=3660) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_max_round_ps( @@ -9782,7 +9782,7 @@ pub fn _mm512_mask_max_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_round_ps&expand=3661) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxps, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_max_round_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { @@ -9801,7 +9801,7 @@ pub fn _mm512_maskz_max_round_ps(k: __mmask16, a: __m512, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_round_pd&expand=3659) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_max_round_pd(a: __m512d, b: __m512d) -> __m512d { @@ -9820,7 +9820,7 @@ pub fn _mm512_max_round_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_round_pd&expand=3657) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_max_round_pd( @@ -9844,7 +9844,7 @@ pub fn _mm512_mask_max_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_round_pd&expand=3658) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxpd, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_max_round_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { @@ -9863,7 +9863,7 @@ pub fn _mm512_maskz_max_round_pd(k: __mmask8, a: __m512d, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_round_ps&expand=3776) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_min_round_ps(a: __m512, b: __m512) -> __m512 { @@ -9882,7 +9882,7 @@ pub fn _mm512_min_round_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_round_ps&expand=3774) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_min_round_ps( @@ -9906,7 +9906,7 @@ pub fn _mm512_mask_min_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_round_ps&expand=3775) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminps, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_min_round_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { @@ -9925,7 +9925,7 @@ pub fn _mm512_maskz_min_round_ps(k: __mmask16, a: __m512, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_round_pd&expand=3773) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_min_round_pd(a: __m512d, b: __m512d) -> __m512d { @@ -9944,7 +9944,7 @@ pub fn _mm512_min_round_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_round_pd&expand=3771) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_min_round_pd( @@ -9968,7 +9968,7 @@ pub fn _mm512_mask_min_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_round_pd&expand=3772) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminpd, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_min_round_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { @@ -9987,7 +9987,7 @@ pub fn _mm512_maskz_min_round_pd(k: __mmask8, a: __m512d, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_getexp_round_ps&expand=2850) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_getexp_round_ps(a: __m512) -> __m512 { @@ -10005,7 +10005,7 @@ pub fn _mm512_getexp_round_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_getexp_round_ps&expand=2851) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_getexp_round_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { @@ -10024,7 +10024,7 @@ pub fn _mm512_mask_getexp_round_ps(src: __m512, k: __mmask16, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_getexp_round_ps&expand=2852) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpps, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_getexp_round_ps(k: __mmask16, a: __m512) -> __m512 { @@ -10042,7 +10042,7 @@ pub fn _mm512_maskz_getexp_round_ps(k: __mmask16, a: __m512) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_getexp_round_pd&expand=2847) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_getexp_round_pd(a: __m512d) -> __m512d { @@ -10060,7 +10060,7 @@ pub fn _mm512_getexp_round_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_getexp_round_pd&expand=2848) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_getexp_round_pd( @@ -10083,7 +10083,7 @@ pub fn _mm512_mask_getexp_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_getexp_round_pd&expand=2849) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexppd, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_getexp_round_pd(k: __mmask8, a: __m512d) -> __m512d { @@ -10107,7 +10107,7 @@ pub fn _mm512_maskz_getexp_round_pd(k: __mmask8, a: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_roundscale_round_ps&expand=4790) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] pub fn _mm512_roundscale_round_ps(a: __m512) -> __m512 { @@ -10132,7 +10132,7 @@ pub fn _mm512_roundscale_round_ps(a: __m512) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_roundscale_round_ps&expand=4788) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm512_mask_roundscale_round_ps( @@ -10162,7 +10162,7 @@ pub fn _mm512_mask_roundscale_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_roundscale_round_ps&expand=4789) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm512_maskz_roundscale_round_ps( @@ -10190,7 +10190,7 @@ pub fn _mm512_maskz_roundscale_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_roundscale_round_pd&expand=4787) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] pub fn _mm512_roundscale_round_pd(a: __m512d) -> __m512d { @@ -10215,7 +10215,7 @@ pub fn _mm512_roundscale_round_pd(a: __m512d) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_roundscale_round_pd&expand=4785) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm512_mask_roundscale_round_pd( @@ -10245,7 +10245,7 @@ pub fn _mm512_mask_roundscale_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_roundscale_round_pd&expand=4786) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm512_maskz_roundscale_round_pd( @@ -10273,7 +10273,7 @@ pub fn _mm512_maskz_roundscale_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_scalef_round_ps&expand=4889) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_scalef_round_ps(a: __m512, b: __m512) -> __m512 { @@ -10298,7 +10298,7 @@ pub fn _mm512_scalef_round_ps(a: __m512, b: __m512) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_scalef_round_ps&expand=4887) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_scalef_round_ps( @@ -10329,7 +10329,7 @@ pub fn _mm512_mask_scalef_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_scalef_round_ps&expand=4888) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_scalef_round_ps( @@ -10358,7 +10358,7 @@ pub fn _mm512_maskz_scalef_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_scalef_round_pd&expand=4886) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_scalef_round_pd(a: __m512d, b: __m512d) -> __m512d { @@ -10383,7 +10383,7 @@ pub fn _mm512_scalef_round_pd(a: __m512d, b: __m512d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_scalef_round_pd&expand=4884) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_scalef_round_pd( @@ -10414,7 +10414,7 @@ pub fn _mm512_mask_scalef_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_scalef_round_pd&expand=4885) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefpd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_scalef_round_pd( @@ -10437,7 +10437,7 @@ pub fn _mm512_maskz_scalef_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fixupimm_round_ps&expand=2505) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm512_fixupimm_round_ps( @@ -10462,7 +10462,7 @@ pub fn _mm512_fixupimm_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fixupimm_round_ps&expand=2506) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm512_mask_fixupimm_round_ps( @@ -10488,7 +10488,7 @@ pub fn _mm512_mask_fixupimm_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fixupimm_round_ps&expand=2507) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm512_maskz_fixupimm_round_ps( @@ -10514,7 +10514,7 @@ pub fn _mm512_maskz_fixupimm_round_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_fixupimm_round_pd&expand=2502) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm512_fixupimm_round_pd( @@ -10539,7 +10539,7 @@ pub fn _mm512_fixupimm_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_fixupimm_round_pd&expand=2503) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm512_mask_fixupimm_round_pd( @@ -10565,7 +10565,7 @@ pub fn _mm512_mask_fixupimm_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_fixupimm_round_pd&expand=2504) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm512_maskz_fixupimm_round_pd( @@ -10600,7 +10600,7 @@ pub fn _mm512_maskz_fixupimm_round_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_getmant_round_ps&expand=2886) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(1, 2, 3)] pub fn _mm512_getmant_round_ps< @@ -10635,7 +10635,7 @@ pub fn _mm512_getmant_round_ps< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_getmant_round_ps&expand=2887) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(3, 4, 5)] pub fn _mm512_mask_getmant_round_ps< @@ -10673,7 +10673,7 @@ pub fn _mm512_mask_getmant_round_ps< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_getmant_round_ps&expand=2888) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(2, 3, 4)] pub fn _mm512_maskz_getmant_round_ps< @@ -10709,7 +10709,7 @@ pub fn _mm512_maskz_getmant_round_ps< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_getmant_round_pd&expand=2883) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(1, 2, 3)] pub fn _mm512_getmant_round_pd< @@ -10744,7 +10744,7 @@ pub fn _mm512_getmant_round_pd< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_getmant_round_pd&expand=2884) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(3, 4, 5)] pub fn _mm512_mask_getmant_round_pd< @@ -10782,7 +10782,7 @@ pub fn _mm512_mask_getmant_round_pd< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_getmant_round_pd&expand=2885) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(2, 3, 4)] pub fn _mm512_maskz_getmant_round_pd< @@ -10808,7 +10808,7 @@ pub fn _mm512_maskz_getmant_round_pd< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtps_epi32&expand=1737) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq))] pub fn _mm512_cvtps_epi32(a: __m512) -> __m512i { unsafe { @@ -10826,7 +10826,7 @@ pub fn _mm512_cvtps_epi32(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtps_epi32&expand=1738) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq))] pub fn _mm512_mask_cvtps_epi32(src: __m512i, k: __mmask16, a: __m512) -> __m512i { unsafe { @@ -10844,7 +10844,7 @@ pub fn _mm512_mask_cvtps_epi32(src: __m512i, k: __mmask16, a: __m512) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtps_epi32&expand=1739) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq))] pub fn _mm512_maskz_cvtps_epi32(k: __mmask16, a: __m512) -> __m512i { unsafe { @@ -10862,7 +10862,7 @@ pub fn _mm512_maskz_cvtps_epi32(k: __mmask16, a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtps_epi32&expand=1735) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq))] pub fn _mm256_mask_cvtps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i { unsafe { @@ -10876,7 +10876,7 @@ pub fn _mm256_mask_cvtps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtps_epi32&expand=1736) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq))] pub fn _mm256_maskz_cvtps_epi32(k: __mmask8, a: __m256) -> __m256i { unsafe { @@ -10890,7 +10890,7 @@ pub fn _mm256_maskz_cvtps_epi32(k: __mmask8, a: __m256) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtps_epi32&expand=1732) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq))] pub fn _mm_mask_cvtps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { @@ -10904,7 +10904,7 @@ pub fn _mm_mask_cvtps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtps_epi32&expand=1733) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq))] pub fn _mm_maskz_cvtps_epi32(k: __mmask8, a: __m128) -> __m128i { unsafe { @@ -10918,7 +10918,7 @@ pub fn _mm_maskz_cvtps_epi32(k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtps_epu32&expand=1755) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm512_cvtps_epu32(a: __m512) -> __m512i { unsafe { @@ -10936,7 +10936,7 @@ pub fn _mm512_cvtps_epu32(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtps_epu32&expand=1756) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm512_mask_cvtps_epu32(src: __m512i, k: __mmask16, a: __m512) -> __m512i { unsafe { @@ -10954,7 +10954,7 @@ pub fn _mm512_mask_cvtps_epu32(src: __m512i, k: __mmask16, a: __m512) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtps_epu32&expand=1343) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm512_maskz_cvtps_epu32(k: __mmask16, a: __m512) -> __m512i { unsafe { @@ -10972,7 +10972,7 @@ pub fn _mm512_maskz_cvtps_epu32(k: __mmask16, a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtps_epu32&expand=1752) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm256_cvtps_epu32(a: __m256) -> __m256i { unsafe { transmute(vcvtps2udq256(a.as_f32x8(), u32x8::ZERO, 0b11111111)) } @@ -10983,7 +10983,7 @@ pub fn _mm256_cvtps_epu32(a: __m256) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtps_epu32&expand=1753) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm256_mask_cvtps_epu32(src: __m256i, k: __mmask8, a: __m256) -> __m256i { unsafe { transmute(vcvtps2udq256(a.as_f32x8(), src.as_u32x8(), k)) } @@ -10994,7 +10994,7 @@ pub fn _mm256_mask_cvtps_epu32(src: __m256i, k: __mmask8, a: __m256) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtps_epu32&expand=1754) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm256_maskz_cvtps_epu32(k: __mmask8, a: __m256) -> __m256i { unsafe { transmute(vcvtps2udq256(a.as_f32x8(), u32x8::ZERO, k)) } @@ -11005,7 +11005,7 @@ pub fn _mm256_maskz_cvtps_epu32(k: __mmask8, a: __m256) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtps_epu32&expand=1749) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm_cvtps_epu32(a: __m128) -> __m128i { unsafe { transmute(vcvtps2udq128(a.as_f32x4(), u32x4::ZERO, 0b11111111)) } @@ -11016,7 +11016,7 @@ pub fn _mm_cvtps_epu32(a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtps_epu32&expand=1750) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm_mask_cvtps_epu32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvtps2udq128(a.as_f32x4(), src.as_u32x4(), k)) } @@ -11027,7 +11027,7 @@ pub fn _mm_mask_cvtps_epu32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtps_epu32&expand=1751) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq))] pub fn _mm_maskz_cvtps_epu32(k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvtps2udq128(a.as_f32x4(), u32x4::ZERO, k)) } @@ -11038,7 +11038,7 @@ pub fn _mm_maskz_cvtps_epu32(k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtps_pd&expand=1769) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2pd))] pub fn _mm512_cvtps_pd(a: __m256) -> __m512d { unsafe { @@ -11056,7 +11056,7 @@ pub fn _mm512_cvtps_pd(a: __m256) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtps_pd&expand=1770) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2pd))] pub fn _mm512_mask_cvtps_pd(src: __m512d, k: __mmask8, a: __m256) -> __m512d { unsafe { @@ -11074,7 +11074,7 @@ pub fn _mm512_mask_cvtps_pd(src: __m512d, k: __mmask8, a: __m256) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtps_pd&expand=1771) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2pd))] pub fn _mm512_maskz_cvtps_pd(k: __mmask8, a: __m256) -> __m512d { unsafe { @@ -11092,7 +11092,7 @@ pub fn _mm512_maskz_cvtps_pd(k: __mmask8, a: __m256) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtpslo_pd&expand=1784) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2pd))] pub fn _mm512_cvtpslo_pd(v2: __m512) -> __m512d { unsafe { @@ -11110,7 +11110,7 @@ pub fn _mm512_cvtpslo_pd(v2: __m512) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtpslo_pd&expand=1785) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2pd))] pub fn _mm512_mask_cvtpslo_pd(src: __m512d, k: __mmask8, v2: __m512) -> __m512d { unsafe { @@ -11128,7 +11128,7 @@ pub fn _mm512_mask_cvtpslo_pd(src: __m512d, k: __mmask8, v2: __m512) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtpd_ps&expand=1712) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm512_cvtpd_ps(a: __m512d) -> __m256 { unsafe { @@ -11146,7 +11146,7 @@ pub fn _mm512_cvtpd_ps(a: __m512d) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtpd_ps&expand=1713) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm512_mask_cvtpd_ps(src: __m256, k: __mmask8, a: __m512d) -> __m256 { unsafe { @@ -11164,7 +11164,7 @@ pub fn _mm512_mask_cvtpd_ps(src: __m256, k: __mmask8, a: __m512d) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtpd_ps&expand=1714) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm512_maskz_cvtpd_ps(k: __mmask8, a: __m512d) -> __m256 { unsafe { @@ -11182,7 +11182,7 @@ pub fn _mm512_maskz_cvtpd_ps(k: __mmask8, a: __m512d) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtpd_ps&expand=1710) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm256_mask_cvtpd_ps(src: __m128, k: __mmask8, a: __m256d) -> __m128 { unsafe { @@ -11196,7 +11196,7 @@ pub fn _mm256_mask_cvtpd_ps(src: __m128, k: __mmask8, a: __m256d) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtpd_ps&expand=1711) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm256_maskz_cvtpd_ps(k: __mmask8, a: __m256d) -> __m128 { unsafe { @@ -11210,7 +11210,7 @@ pub fn _mm256_maskz_cvtpd_ps(k: __mmask8, a: __m256d) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtpd_ps&expand=1707) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm_mask_cvtpd_ps(src: __m128, k: __mmask8, a: __m128d) -> __m128 { unsafe { @@ -11224,7 +11224,7 @@ pub fn _mm_mask_cvtpd_ps(src: __m128, k: __mmask8, a: __m128d) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtpd_ps&expand=1708) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm_maskz_cvtpd_ps(k: __mmask8, a: __m128d) -> __m128 { unsafe { @@ -11238,7 +11238,7 @@ pub fn _mm_maskz_cvtpd_ps(k: __mmask8, a: __m128d) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtpd_epi32&expand=1675) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq))] pub fn _mm512_cvtpd_epi32(a: __m512d) -> __m256i { unsafe { @@ -11256,7 +11256,7 @@ pub fn _mm512_cvtpd_epi32(a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtpd_epi32&expand=1676) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq))] pub fn _mm512_mask_cvtpd_epi32(src: __m256i, k: __mmask8, a: __m512d) -> __m256i { unsafe { @@ -11274,7 +11274,7 @@ pub fn _mm512_mask_cvtpd_epi32(src: __m256i, k: __mmask8, a: __m512d) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtpd_epi32&expand=1677) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq))] pub fn _mm512_maskz_cvtpd_epi32(k: __mmask8, a: __m512d) -> __m256i { unsafe { @@ -11292,7 +11292,7 @@ pub fn _mm512_maskz_cvtpd_epi32(k: __mmask8, a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtpd_epi32&expand=1673) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq))] pub fn _mm256_mask_cvtpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i { unsafe { @@ -11306,7 +11306,7 @@ pub fn _mm256_mask_cvtpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtpd_epi32&expand=1674) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq))] pub fn _mm256_maskz_cvtpd_epi32(k: __mmask8, a: __m256d) -> __m128i { unsafe { @@ -11320,7 +11320,7 @@ pub fn _mm256_maskz_cvtpd_epi32(k: __mmask8, a: __m256d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtpd_epi32&expand=1670) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq))] pub fn _mm_mask_cvtpd_epi32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { unsafe { @@ -11334,7 +11334,7 @@ pub fn _mm_mask_cvtpd_epi32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtpd_epi32&expand=1671) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq))] pub fn _mm_maskz_cvtpd_epi32(k: __mmask8, a: __m128d) -> __m128i { unsafe { @@ -11348,7 +11348,7 @@ pub fn _mm_maskz_cvtpd_epi32(k: __mmask8, a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtpd_epu32&expand=1693) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm512_cvtpd_epu32(a: __m512d) -> __m256i { unsafe { @@ -11366,7 +11366,7 @@ pub fn _mm512_cvtpd_epu32(a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtpd_epu32&expand=1694) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm512_mask_cvtpd_epu32(src: __m256i, k: __mmask8, a: __m512d) -> __m256i { unsafe { @@ -11384,7 +11384,7 @@ pub fn _mm512_mask_cvtpd_epu32(src: __m256i, k: __mmask8, a: __m512d) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtpd_epu32&expand=1695) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm512_maskz_cvtpd_epu32(k: __mmask8, a: __m512d) -> __m256i { unsafe { @@ -11402,7 +11402,7 @@ pub fn _mm512_maskz_cvtpd_epu32(k: __mmask8, a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtpd_epu32&expand=1690) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm256_cvtpd_epu32(a: __m256d) -> __m128i { unsafe { transmute(vcvtpd2udq256(a.as_f64x4(), u32x4::ZERO, 0b11111111)) } @@ -11413,7 +11413,7 @@ pub fn _mm256_cvtpd_epu32(a: __m256d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtpd_epu32&expand=1691) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm256_mask_cvtpd_epu32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i { unsafe { transmute(vcvtpd2udq256(a.as_f64x4(), src.as_u32x4(), k)) } @@ -11424,7 +11424,7 @@ pub fn _mm256_mask_cvtpd_epu32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtpd_epu32&expand=1692) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm256_maskz_cvtpd_epu32(k: __mmask8, a: __m256d) -> __m128i { unsafe { transmute(vcvtpd2udq256(a.as_f64x4(), u32x4::ZERO, k)) } @@ -11435,7 +11435,7 @@ pub fn _mm256_maskz_cvtpd_epu32(k: __mmask8, a: __m256d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtpd_epu32&expand=1687) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm_cvtpd_epu32(a: __m128d) -> __m128i { unsafe { transmute(vcvtpd2udq128(a.as_f64x2(), u32x4::ZERO, 0b11111111)) } @@ -11446,7 +11446,7 @@ pub fn _mm_cvtpd_epu32(a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtpd_epu32&expand=1688) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm_mask_cvtpd_epu32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvtpd2udq128(a.as_f64x2(), src.as_u32x4(), k)) } @@ -11457,7 +11457,7 @@ pub fn _mm_mask_cvtpd_epu32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtpd_epu32&expand=1689) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq))] pub fn _mm_maskz_cvtpd_epu32(k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvtpd2udq128(a.as_f64x2(), u32x4::ZERO, k)) } @@ -11468,7 +11468,7 @@ pub fn _mm_maskz_cvtpd_epu32(k: __mmask8, a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtpd_pslo&expand=1715) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm512_cvtpd_pslo(v2: __m512d) -> __m512 { unsafe { @@ -11491,7 +11491,7 @@ pub fn _mm512_cvtpd_pslo(v2: __m512d) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtpd_pslo&expand=1716) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps))] pub fn _mm512_mask_cvtpd_pslo(src: __m512, k: __mmask8, v2: __m512d) -> __m512 { unsafe { @@ -11514,7 +11514,7 @@ pub fn _mm512_mask_cvtpd_pslo(src: __m512, k: __mmask8, v2: __m512d) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi8_epi32&expand=1535) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbd))] pub fn _mm512_cvtepi8_epi32(a: __m128i) -> __m512i { unsafe { @@ -11528,7 +11528,7 @@ pub fn _mm512_cvtepi8_epi32(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi8_epi32&expand=1536) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbd))] pub fn _mm512_mask_cvtepi8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i { unsafe { @@ -11542,7 +11542,7 @@ pub fn _mm512_mask_cvtepi8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi8_epi32&expand=1537) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbd))] pub fn _mm512_maskz_cvtepi8_epi32(k: __mmask16, a: __m128i) -> __m512i { unsafe { @@ -11556,7 +11556,7 @@ pub fn _mm512_maskz_cvtepi8_epi32(k: __mmask16, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi8_epi32&expand=1533) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbd))] pub fn _mm256_mask_cvtepi8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11570,7 +11570,7 @@ pub fn _mm256_mask_cvtepi8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi8_epi32&expand=1534) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbd))] pub fn _mm256_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11584,7 +11584,7 @@ pub fn _mm256_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi8_epi32&expand=1530) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbd))] pub fn _mm_mask_cvtepi8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11598,7 +11598,7 @@ pub fn _mm_mask_cvtepi8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi8_epi32&expand=1531) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbd))] pub fn _mm_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11612,7 +11612,7 @@ pub fn _mm_maskz_cvtepi8_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi8_epi64&expand=1544) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbq))] pub fn _mm512_cvtepi8_epi64(a: __m128i) -> __m512i { unsafe { @@ -11627,7 +11627,7 @@ pub fn _mm512_cvtepi8_epi64(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi8_epi64&expand=1545) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbq))] pub fn _mm512_mask_cvtepi8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -11641,7 +11641,7 @@ pub fn _mm512_mask_cvtepi8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi8_epi64&expand=1546) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbq))] pub fn _mm512_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -11655,7 +11655,7 @@ pub fn _mm512_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi8_epi64&expand=1542) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbq))] pub fn _mm256_mask_cvtepi8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11669,7 +11669,7 @@ pub fn _mm256_mask_cvtepi8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi8_epi64&expand=1543) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbq))] pub fn _mm256_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11683,7 +11683,7 @@ pub fn _mm256_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi8_epi64&expand=1539) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbq))] pub fn _mm_mask_cvtepi8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11697,7 +11697,7 @@ pub fn _mm_mask_cvtepi8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi8_epi64&expand=1540) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxbq))] pub fn _mm_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11711,7 +11711,7 @@ pub fn _mm_maskz_cvtepi8_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu8_epi32&expand=1621) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbd))] pub fn _mm512_cvtepu8_epi32(a: __m128i) -> __m512i { unsafe { @@ -11725,7 +11725,7 @@ pub fn _mm512_cvtepu8_epi32(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu8_epi32&expand=1622) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbd))] pub fn _mm512_mask_cvtepu8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i { unsafe { @@ -11739,7 +11739,7 @@ pub fn _mm512_mask_cvtepu8_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu8_epi32&expand=1623) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbd))] pub fn _mm512_maskz_cvtepu8_epi32(k: __mmask16, a: __m128i) -> __m512i { unsafe { @@ -11753,7 +11753,7 @@ pub fn _mm512_maskz_cvtepu8_epi32(k: __mmask16, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepu8_epi32&expand=1619) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbd))] pub fn _mm256_mask_cvtepu8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11767,7 +11767,7 @@ pub fn _mm256_mask_cvtepu8_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m25 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/IntrinsicsGuide/#text=_mm256_maskz_cvtepu8_epi32&expand=1620) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbd))] pub fn _mm256_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11781,7 +11781,7 @@ pub fn _mm256_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepu8_epi32&expand=1616) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbd))] pub fn _mm_mask_cvtepu8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11795,7 +11795,7 @@ pub fn _mm_mask_cvtepu8_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/IntrinsicsGuide/#text=_mm_maskz_cvtepu8_epi32&expand=1617) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbd))] pub fn _mm_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11809,7 +11809,7 @@ pub fn _mm_maskz_cvtepu8_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu8_epi64&expand=1630) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbq))] pub fn _mm512_cvtepu8_epi64(a: __m128i) -> __m512i { unsafe { @@ -11824,7 +11824,7 @@ pub fn _mm512_cvtepu8_epi64(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu8_epi64&expand=1631) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbq))] pub fn _mm512_mask_cvtepu8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -11838,7 +11838,7 @@ pub fn _mm512_mask_cvtepu8_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu8_epi64&expand=1632) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbq))] pub fn _mm512_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -11852,7 +11852,7 @@ pub fn _mm512_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepu8_epi64&expand=1628) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbq))] pub fn _mm256_mask_cvtepu8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11866,7 +11866,7 @@ pub fn _mm256_mask_cvtepu8_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepu8_epi64&expand=1629) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbq))] pub fn _mm256_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11880,7 +11880,7 @@ pub fn _mm256_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepu8_epi64&expand=1625) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbq))] pub fn _mm_mask_cvtepu8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11894,7 +11894,7 @@ pub fn _mm_mask_cvtepu8_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepu8_epi64&expand=1626) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxbq))] pub fn _mm_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11908,7 +11908,7 @@ pub fn _mm_maskz_cvtepu8_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi16_epi32&expand=1389) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwd))] pub fn _mm512_cvtepi16_epi32(a: __m256i) -> __m512i { unsafe { @@ -11922,7 +11922,7 @@ pub fn _mm512_cvtepi16_epi32(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi16_epi32&expand=1390) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwd))] pub fn _mm512_mask_cvtepi16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m512i { unsafe { @@ -11936,7 +11936,7 @@ pub fn _mm512_mask_cvtepi16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi16_epi32&expand=1391) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwd))] pub fn _mm512_maskz_cvtepi16_epi32(k: __mmask16, a: __m256i) -> __m512i { unsafe { @@ -11950,7 +11950,7 @@ pub fn _mm512_maskz_cvtepi16_epi32(k: __mmask16, a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi16_epi32&expand=1387) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwd))] pub fn _mm256_mask_cvtepi16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11964,7 +11964,7 @@ pub fn _mm256_mask_cvtepi16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi16_epi32&expand=1388) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwd))] pub fn _mm256_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -11978,7 +11978,7 @@ pub fn _mm256_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi16_epi32&expand=1384) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwd))] pub fn _mm_mask_cvtepi16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -11992,7 +11992,7 @@ pub fn _mm_mask_cvtepi16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi16_epi32&expand=1385) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwd))] pub fn _mm_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12006,7 +12006,7 @@ pub fn _mm_maskz_cvtepi16_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi16_epi64&expand=1398) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwq))] pub fn _mm512_cvtepi16_epi64(a: __m128i) -> __m512i { unsafe { @@ -12020,7 +12020,7 @@ pub fn _mm512_cvtepi16_epi64(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi16_epi64&expand=1399) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwq))] pub fn _mm512_mask_cvtepi16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -12034,7 +12034,7 @@ pub fn _mm512_mask_cvtepi16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi16_epi64&expand=1400) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwq))] pub fn _mm512_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -12048,7 +12048,7 @@ pub fn _mm512_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi16_epi64&expand=1396) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwq))] pub fn _mm256_mask_cvtepi16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12062,7 +12062,7 @@ pub fn _mm256_mask_cvtepi16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi16_epi64&expand=1397) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwq))] pub fn _mm256_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12076,7 +12076,7 @@ pub fn _mm256_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi16_epi64&expand=1393) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwq))] pub fn _mm_mask_cvtepi16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12090,7 +12090,7 @@ pub fn _mm_mask_cvtepi16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi16_epi64&expand=1394) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxwq))] pub fn _mm_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12104,7 +12104,7 @@ pub fn _mm_maskz_cvtepi16_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu16_epi32&expand=1553) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwd))] pub fn _mm512_cvtepu16_epi32(a: __m256i) -> __m512i { unsafe { @@ -12118,7 +12118,7 @@ pub fn _mm512_cvtepu16_epi32(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu16_epi32&expand=1554) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwd))] pub fn _mm512_mask_cvtepu16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m512i { unsafe { @@ -12132,7 +12132,7 @@ pub fn _mm512_mask_cvtepu16_epi32(src: __m512i, k: __mmask16, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu16_epi32&expand=1555) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwd))] pub fn _mm512_maskz_cvtepu16_epi32(k: __mmask16, a: __m256i) -> __m512i { unsafe { @@ -12146,7 +12146,7 @@ pub fn _mm512_maskz_cvtepu16_epi32(k: __mmask16, a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepu16_epi32&expand=1551) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwd))] pub fn _mm256_mask_cvtepu16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12160,7 +12160,7 @@ pub fn _mm256_mask_cvtepu16_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepu16_epi32&expand=1552) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwd))] pub fn _mm256_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12174,7 +12174,7 @@ pub fn _mm256_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepu16_epi32&expand=1548) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwd))] pub fn _mm_mask_cvtepu16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12188,7 +12188,7 @@ pub fn _mm_mask_cvtepu16_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepu16_epi32&expand=1549) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwd))] pub fn _mm_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12202,7 +12202,7 @@ pub fn _mm_maskz_cvtepu16_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu16_epi64&expand=1562) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwq))] pub fn _mm512_cvtepu16_epi64(a: __m128i) -> __m512i { unsafe { @@ -12216,7 +12216,7 @@ pub fn _mm512_cvtepu16_epi64(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu16_epi64&expand=1563) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwq))] pub fn _mm512_mask_cvtepu16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -12230,7 +12230,7 @@ pub fn _mm512_mask_cvtepu16_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu16_epi64&expand=1564) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwq))] pub fn _mm512_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -12244,7 +12244,7 @@ pub fn _mm512_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepu16_epi64&expand=1560) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwq))] pub fn _mm256_mask_cvtepu16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12258,7 +12258,7 @@ pub fn _mm256_mask_cvtepu16_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepu16_epi64&expand=1561) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwq))] pub fn _mm256_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12272,7 +12272,7 @@ pub fn _mm256_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepu16_epi64&expand=1557) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwq))] pub fn _mm_mask_cvtepu16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12286,7 +12286,7 @@ pub fn _mm_mask_cvtepu16_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepu16_epi64&expand=1558) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxwq))] pub fn _mm_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12300,7 +12300,7 @@ pub fn _mm_maskz_cvtepu16_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi32_epi64&expand=1428) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxdq))] pub fn _mm512_cvtepi32_epi64(a: __m256i) -> __m512i { unsafe { @@ -12314,7 +12314,7 @@ pub fn _mm512_cvtepi32_epi64(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi32_epi64&expand=1429) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxdq))] pub fn _mm512_mask_cvtepi32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m512i { unsafe { @@ -12328,7 +12328,7 @@ pub fn _mm512_mask_cvtepi32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi32_epi64&expand=1430) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxdq))] pub fn _mm512_maskz_cvtepi32_epi64(k: __mmask8, a: __m256i) -> __m512i { unsafe { @@ -12342,7 +12342,7 @@ pub fn _mm512_maskz_cvtepi32_epi64(k: __mmask8, a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi32_epi64&expand=1426) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxdq))] pub fn _mm256_mask_cvtepi32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12356,7 +12356,7 @@ pub fn _mm256_mask_cvtepi32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi32_epi64&expand=1427) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxdq))] pub fn _mm256_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12370,7 +12370,7 @@ pub fn _mm256_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi32_epi64&expand=1423) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxdq))] pub fn _mm_mask_cvtepi32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12384,7 +12384,7 @@ pub fn _mm_mask_cvtepi32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi32_epi64&expand=1424) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsxdq))] pub fn _mm_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12398,7 +12398,7 @@ pub fn _mm_maskz_cvtepi32_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu32_epi64&expand=1571) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxdq))] pub fn _mm512_cvtepu32_epi64(a: __m256i) -> __m512i { unsafe { @@ -12412,7 +12412,7 @@ pub fn _mm512_cvtepu32_epi64(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu32_epi64&expand=1572) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxdq))] pub fn _mm512_mask_cvtepu32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m512i { unsafe { @@ -12426,7 +12426,7 @@ pub fn _mm512_mask_cvtepu32_epi64(src: __m512i, k: __mmask8, a: __m256i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu32_epi64&expand=1573) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxdq))] pub fn _mm512_maskz_cvtepu32_epi64(k: __mmask8, a: __m256i) -> __m512i { unsafe { @@ -12440,7 +12440,7 @@ pub fn _mm512_maskz_cvtepu32_epi64(k: __mmask8, a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepu32_epi64&expand=1569) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxdq))] pub fn _mm256_mask_cvtepu32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12454,7 +12454,7 @@ pub fn _mm256_mask_cvtepu32_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepu32_epi64&expand=1570) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxdq))] pub fn _mm256_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -12468,7 +12468,7 @@ pub fn _mm256_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepu32_epi64&expand=1566) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxdq))] pub fn _mm_mask_cvtepu32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12482,7 +12482,7 @@ pub fn _mm_mask_cvtepu32_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepu32_epi64&expand=1567) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovzxdq))] pub fn _mm_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -12496,7 +12496,7 @@ pub fn _mm_maskz_cvtepu32_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi32_ps&expand=1455) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps))] pub fn _mm512_cvtepi32_ps(a: __m512i) -> __m512 { unsafe { @@ -12510,7 +12510,7 @@ pub fn _mm512_cvtepi32_ps(a: __m512i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi32_ps&expand=1456) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps))] pub fn _mm512_mask_cvtepi32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512 { unsafe { @@ -12524,7 +12524,7 @@ pub fn _mm512_mask_cvtepi32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi32_ps&expand=1457) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps))] pub fn _mm512_maskz_cvtepi32_ps(k: __mmask16, a: __m512i) -> __m512 { unsafe { @@ -12538,7 +12538,7 @@ pub fn _mm512_maskz_cvtepi32_ps(k: __mmask16, a: __m512i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi32_ps&expand=1453) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps))] pub fn _mm256_mask_cvtepi32_ps(src: __m256, k: __mmask8, a: __m256i) -> __m256 { unsafe { @@ -12552,7 +12552,7 @@ pub fn _mm256_mask_cvtepi32_ps(src: __m256, k: __mmask8, a: __m256i) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi32_ps&expand=1454) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps))] pub fn _mm256_maskz_cvtepi32_ps(k: __mmask8, a: __m256i) -> __m256 { unsafe { @@ -12566,7 +12566,7 @@ pub fn _mm256_maskz_cvtepi32_ps(k: __mmask8, a: __m256i) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi32_ps&expand=1450) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps))] pub fn _mm_mask_cvtepi32_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 { unsafe { @@ -12580,7 +12580,7 @@ pub fn _mm_mask_cvtepi32_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi32_ps&expand=1451) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps))] pub fn _mm_maskz_cvtepi32_ps(k: __mmask8, a: __m128i) -> __m128 { unsafe { @@ -12594,7 +12594,7 @@ pub fn _mm_maskz_cvtepi32_ps(k: __mmask8, a: __m128i) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi32_pd&expand=1446) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm512_cvtepi32_pd(a: __m256i) -> __m512d { unsafe { @@ -12608,7 +12608,7 @@ pub fn _mm512_cvtepi32_pd(a: __m256i) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi32_pd&expand=1447) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm512_mask_cvtepi32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d { unsafe { @@ -12622,7 +12622,7 @@ pub fn _mm512_mask_cvtepi32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi32_pd&expand=1448) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm512_maskz_cvtepi32_pd(k: __mmask8, a: __m256i) -> __m512d { unsafe { @@ -12636,7 +12636,7 @@ pub fn _mm512_maskz_cvtepi32_pd(k: __mmask8, a: __m256i) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi32_pd&expand=1444) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm256_mask_cvtepi32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d { unsafe { @@ -12650,7 +12650,7 @@ pub fn _mm256_mask_cvtepi32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi32_pd&expand=1445) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm256_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m256d { unsafe { @@ -12664,7 +12664,7 @@ pub fn _mm256_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi32_pd&expand=1441) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm_mask_cvtepi32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d { unsafe { @@ -12678,7 +12678,7 @@ pub fn _mm_mask_cvtepi32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi32_pd&expand=1442) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m128d { unsafe { @@ -12692,7 +12692,7 @@ pub fn _mm_maskz_cvtepi32_pd(k: __mmask8, a: __m128i) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu32_ps&expand=1583) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2ps))] pub fn _mm512_cvtepu32_ps(a: __m512i) -> __m512 { unsafe { @@ -12706,7 +12706,7 @@ pub fn _mm512_cvtepu32_ps(a: __m512i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu32_ps&expand=1584) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2ps))] pub fn _mm512_mask_cvtepu32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512 { unsafe { @@ -12720,7 +12720,7 @@ pub fn _mm512_mask_cvtepu32_ps(src: __m512, k: __mmask16, a: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu32_ps&expand=1585) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2ps))] pub fn _mm512_maskz_cvtepu32_ps(k: __mmask16, a: __m512i) -> __m512 { unsafe { @@ -12734,7 +12734,7 @@ pub fn _mm512_maskz_cvtepu32_ps(k: __mmask16, a: __m512i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu32_pd&expand=1580) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm512_cvtepu32_pd(a: __m256i) -> __m512d { unsafe { @@ -12748,7 +12748,7 @@ pub fn _mm512_cvtepu32_pd(a: __m256i) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu32_pd&expand=1581) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm512_mask_cvtepu32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d { unsafe { @@ -12762,7 +12762,7 @@ pub fn _mm512_mask_cvtepu32_pd(src: __m512d, k: __mmask8, a: __m256i) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu32_pd&expand=1582) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm512_maskz_cvtepu32_pd(k: __mmask8, a: __m256i) -> __m512d { unsafe { @@ -12776,7 +12776,7 @@ pub fn _mm512_maskz_cvtepu32_pd(k: __mmask8, a: __m256i) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtepu32_pd&expand=1577) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm256_cvtepu32_pd(a: __m128i) -> __m256d { unsafe { @@ -12790,7 +12790,7 @@ pub fn _mm256_cvtepu32_pd(a: __m128i) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepu32_pd&expand=1578) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm256_mask_cvtepu32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d { unsafe { @@ -12804,7 +12804,7 @@ pub fn _mm256_mask_cvtepu32_pd(src: __m256d, k: __mmask8, a: __m128i) -> __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepu32_pd&expand=1579) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm256_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m256d { unsafe { @@ -12818,7 +12818,7 @@ pub fn _mm256_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepu32_pd&expand=1574) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm_cvtepu32_pd(a: __m128i) -> __m128d { unsafe { @@ -12833,7 +12833,7 @@ pub fn _mm_cvtepu32_pd(a: __m128i) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepu32_pd&expand=1575) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm_mask_cvtepu32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d { unsafe { @@ -12847,7 +12847,7 @@ pub fn _mm_mask_cvtepu32_pd(src: __m128d, k: __mmask8, a: __m128i) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepu32_pd&expand=1576) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m128d { unsafe { @@ -12861,7 +12861,7 @@ pub fn _mm_maskz_cvtepu32_pd(k: __mmask8, a: __m128i) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi32lo_pd&expand=1464) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm512_cvtepi32lo_pd(v2: __m512i) -> __m512d { unsafe { @@ -12876,7 +12876,7 @@ pub fn _mm512_cvtepi32lo_pd(v2: __m512i) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi32lo_pd&expand=1465) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2pd))] pub fn _mm512_mask_cvtepi32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m512d { unsafe { @@ -12890,7 +12890,7 @@ pub fn _mm512_mask_cvtepi32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu32lo_pd&expand=1586) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm512_cvtepu32lo_pd(v2: __m512i) -> __m512d { unsafe { @@ -12905,7 +12905,7 @@ pub fn _mm512_cvtepu32lo_pd(v2: __m512i) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu32lo_pd&expand=1587) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2pd))] pub fn _mm512_mask_cvtepu32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m512d { unsafe { @@ -12919,7 +12919,7 @@ pub fn _mm512_mask_cvtepu32lo_pd(src: __m512d, k: __mmask8, v2: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi32_epi16&expand=1419) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm512_cvtepi32_epi16(a: __m512i) -> __m256i { unsafe { @@ -12933,7 +12933,7 @@ pub fn _mm512_cvtepi32_epi16(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi32_epi16&expand=1420) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm512_mask_cvtepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> __m256i { unsafe { @@ -12947,7 +12947,7 @@ pub fn _mm512_mask_cvtepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi32_epi16&expand=1421) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm512_maskz_cvtepi32_epi16(k: __mmask16, a: __m512i) -> __m256i { unsafe { @@ -12961,7 +12961,7 @@ pub fn _mm512_maskz_cvtepi32_epi16(k: __mmask16, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtepi32_epi16&expand=1416) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm256_cvtepi32_epi16(a: __m256i) -> __m128i { unsafe { @@ -12975,7 +12975,7 @@ pub fn _mm256_cvtepi32_epi16(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi32_epi16&expand=1417) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm256_mask_cvtepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { @@ -12989,7 +12989,7 @@ pub fn _mm256_mask_cvtepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi32_epi16&expand=1418) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm256_maskz_cvtepi32_epi16(k: __mmask8, a: __m256i) -> __m128i { unsafe { @@ -13003,7 +13003,7 @@ pub fn _mm256_maskz_cvtepi32_epi16(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi32_epi16&expand=1413) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm_cvtepi32_epi16(a: __m128i) -> __m128i { unsafe { transmute(vpmovdw128(a.as_i32x4(), i16x8::ZERO, 0b11111111)) } @@ -13014,7 +13014,7 @@ pub fn _mm_cvtepi32_epi16(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi32_epi16&expand=1414) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm_mask_cvtepi32_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovdw128(a.as_i32x4(), src.as_i16x8(), k)) } @@ -13025,7 +13025,7 @@ pub fn _mm_mask_cvtepi32_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi32_epi16&expand=1415) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub fn _mm_maskz_cvtepi32_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovdw128(a.as_i32x4(), i16x8::ZERO, k)) } @@ -13036,7 +13036,7 @@ pub fn _mm_maskz_cvtepi32_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi32_epi8&expand=1437) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm512_cvtepi32_epi8(a: __m512i) -> __m128i { unsafe { @@ -13050,7 +13050,7 @@ pub fn _mm512_cvtepi32_epi8(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi32_epi8&expand=1438) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm512_mask_cvtepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __m128i { unsafe { @@ -13064,7 +13064,7 @@ pub fn _mm512_mask_cvtepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi32_epi8&expand=1439) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm512_maskz_cvtepi32_epi8(k: __mmask16, a: __m512i) -> __m128i { unsafe { @@ -13078,7 +13078,7 @@ pub fn _mm512_maskz_cvtepi32_epi8(k: __mmask16, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtepi32_epi8&expand=1434) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm256_cvtepi32_epi8(a: __m256i) -> __m128i { unsafe { transmute(vpmovdb256(a.as_i32x8(), i8x16::ZERO, 0b11111111)) } @@ -13089,7 +13089,7 @@ pub fn _mm256_cvtepi32_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi32_epi8&expand=1435) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm256_mask_cvtepi32_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovdb256(a.as_i32x8(), src.as_i8x16(), k)) } @@ -13100,7 +13100,7 @@ pub fn _mm256_mask_cvtepi32_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi32_epi8&expand=1436) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm256_maskz_cvtepi32_epi8(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovdb256(a.as_i32x8(), i8x16::ZERO, k)) } @@ -13111,7 +13111,7 @@ pub fn _mm256_maskz_cvtepi32_epi8(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi32_epi8&expand=1431) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm_cvtepi32_epi8(a: __m128i) -> __m128i { unsafe { transmute(vpmovdb128(a.as_i32x4(), i8x16::ZERO, 0b11111111)) } @@ -13122,7 +13122,7 @@ pub fn _mm_cvtepi32_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi32_epi8&expand=1432) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm_mask_cvtepi32_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovdb128(a.as_i32x4(), src.as_i8x16(), k)) } @@ -13133,7 +13133,7 @@ pub fn _mm_mask_cvtepi32_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi32_epi8&expand=1433) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub fn _mm_maskz_cvtepi32_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovdb128(a.as_i32x4(), i8x16::ZERO, k)) } @@ -13144,7 +13144,7 @@ pub fn _mm_maskz_cvtepi32_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi64_epi32&expand=1481) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm512_cvtepi64_epi32(a: __m512i) -> __m256i { unsafe { @@ -13158,7 +13158,7 @@ pub fn _mm512_cvtepi64_epi32(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi64_epi32&expand=1482) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm512_mask_cvtepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __m256i { unsafe { @@ -13172,7 +13172,7 @@ pub fn _mm512_mask_cvtepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi64_epi32&expand=1483) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm512_maskz_cvtepi64_epi32(k: __mmask8, a: __m512i) -> __m256i { unsafe { @@ -13186,7 +13186,7 @@ pub fn _mm512_maskz_cvtepi64_epi32(k: __mmask8, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtepi64_epi32&expand=1478) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm256_cvtepi64_epi32(a: __m256i) -> __m128i { unsafe { @@ -13200,7 +13200,7 @@ pub fn _mm256_cvtepi64_epi32(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi64_epi32&expand=1479) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm256_mask_cvtepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { @@ -13214,7 +13214,7 @@ pub fn _mm256_mask_cvtepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi64_epi32&expand=1480) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm256_maskz_cvtepi64_epi32(k: __mmask8, a: __m256i) -> __m128i { unsafe { @@ -13228,7 +13228,7 @@ pub fn _mm256_maskz_cvtepi64_epi32(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi64_epi32&expand=1475) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm_cvtepi64_epi32(a: __m128i) -> __m128i { unsafe { transmute(vpmovqd128(a.as_i64x2(), i32x4::ZERO, 0b11111111)) } @@ -13239,7 +13239,7 @@ pub fn _mm_cvtepi64_epi32(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi64_epi32&expand=1476) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm_mask_cvtepi64_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovqd128(a.as_i64x2(), src.as_i32x4(), k)) } @@ -13250,7 +13250,7 @@ pub fn _mm_mask_cvtepi64_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi64_epi32&expand=1477) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub fn _mm_maskz_cvtepi64_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovqd128(a.as_i64x2(), i32x4::ZERO, k)) } @@ -13261,7 +13261,7 @@ pub fn _mm_maskz_cvtepi64_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi64_epi16&expand=1472) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm512_cvtepi64_epi16(a: __m512i) -> __m128i { unsafe { @@ -13275,7 +13275,7 @@ pub fn _mm512_cvtepi64_epi16(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi64_epi16&expand=1473) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm512_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __m128i { unsafe { @@ -13289,7 +13289,7 @@ pub fn _mm512_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi64_epi16&expand=1474) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm512_maskz_cvtepi64_epi16(k: __mmask8, a: __m512i) -> __m128i { unsafe { @@ -13303,7 +13303,7 @@ pub fn _mm512_maskz_cvtepi64_epi16(k: __mmask8, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtepi64_epi16&expand=1469) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm256_cvtepi64_epi16(a: __m256i) -> __m128i { unsafe { transmute(vpmovqw256(a.as_i64x4(), i16x8::ZERO, 0b11111111)) } @@ -13314,7 +13314,7 @@ pub fn _mm256_cvtepi64_epi16(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi64_epi16&expand=1470) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm256_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovqw256(a.as_i64x4(), src.as_i16x8(), k)) } @@ -13325,7 +13325,7 @@ pub fn _mm256_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi64_epi16&expand=1471) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm256_maskz_cvtepi64_epi16(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovqw256(a.as_i64x4(), i16x8::ZERO, k)) } @@ -13336,7 +13336,7 @@ pub fn _mm256_maskz_cvtepi64_epi16(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi64_epi16&expand=1466) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm_cvtepi64_epi16(a: __m128i) -> __m128i { unsafe { transmute(vpmovqw128(a.as_i64x2(), i16x8::ZERO, 0b11111111)) } @@ -13347,7 +13347,7 @@ pub fn _mm_cvtepi64_epi16(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi64_epi16&expand=1467) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovqw128(a.as_i64x2(), src.as_i16x8(), k)) } @@ -13358,7 +13358,7 @@ pub fn _mm_mask_cvtepi64_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi64_epi16&expand=1468) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub fn _mm_maskz_cvtepi64_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovqw128(a.as_i64x2(), i16x8::ZERO, k)) } @@ -13369,7 +13369,7 @@ pub fn _mm_maskz_cvtepi64_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi64_epi8&expand=1490) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm512_cvtepi64_epi8(a: __m512i) -> __m128i { unsafe { transmute(vpmovqb(a.as_i64x8(), i8x16::ZERO, 0b11111111)) } @@ -13380,7 +13380,7 @@ pub fn _mm512_cvtepi64_epi8(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi64_epi8&expand=1491) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm512_mask_cvtepi64_epi8(src: __m128i, k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovqb(a.as_i64x8(), src.as_i8x16(), k)) } @@ -13391,7 +13391,7 @@ pub fn _mm512_mask_cvtepi64_epi8(src: __m128i, k: __mmask8, a: __m512i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi64_epi8&expand=1492) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm512_maskz_cvtepi64_epi8(k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovqb(a.as_i64x8(), i8x16::ZERO, k)) } @@ -13402,7 +13402,7 @@ pub fn _mm512_maskz_cvtepi64_epi8(k: __mmask8, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtepi64_epi8&expand=1487) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm256_cvtepi64_epi8(a: __m256i) -> __m128i { unsafe { transmute(vpmovqb256(a.as_i64x4(), i8x16::ZERO, 0b11111111)) } @@ -13413,7 +13413,7 @@ pub fn _mm256_cvtepi64_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi64_epi8&expand=1488) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm256_mask_cvtepi64_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovqb256(a.as_i64x4(), src.as_i8x16(), k)) } @@ -13424,7 +13424,7 @@ pub fn _mm256_mask_cvtepi64_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi64_epi8&expand=1489) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm256_maskz_cvtepi64_epi8(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovqb256(a.as_i64x4(), i8x16::ZERO, k)) } @@ -13435,7 +13435,7 @@ pub fn _mm256_maskz_cvtepi64_epi8(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi64_epi8&expand=1484) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm_cvtepi64_epi8(a: __m128i) -> __m128i { unsafe { transmute(vpmovqb128(a.as_i64x2(), i8x16::ZERO, 0b11111111)) } @@ -13446,7 +13446,7 @@ pub fn _mm_cvtepi64_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi64_epi8&expand=1485) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm_mask_cvtepi64_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovqb128(a.as_i64x2(), src.as_i8x16(), k)) } @@ -13457,7 +13457,7 @@ pub fn _mm_mask_cvtepi64_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi64_epi8&expand=1486) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub fn _mm_maskz_cvtepi64_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovqb128(a.as_i64x2(), i8x16::ZERO, k)) } @@ -13468,7 +13468,7 @@ pub fn _mm_maskz_cvtepi64_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsepi32_epi16&expand=1819) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm512_cvtsepi32_epi16(a: __m512i) -> __m256i { unsafe { transmute(vpmovsdw(a.as_i32x16(), i16x16::ZERO, 0b11111111_11111111)) } @@ -13479,7 +13479,7 @@ pub fn _mm512_cvtsepi32_epi16(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi32_epi16&expand=1820) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm512_mask_cvtsepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> __m256i { unsafe { transmute(vpmovsdw(a.as_i32x16(), src.as_i16x16(), k)) } @@ -13490,7 +13490,7 @@ pub fn _mm512_mask_cvtsepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtsepi32_epi16&expand=1819) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm512_maskz_cvtsepi32_epi16(k: __mmask16, a: __m512i) -> __m256i { unsafe { transmute(vpmovsdw(a.as_i32x16(), i16x16::ZERO, k)) } @@ -13501,7 +13501,7 @@ pub fn _mm512_maskz_cvtsepi32_epi16(k: __mmask16, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsepi32_epi16&expand=1816) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm256_cvtsepi32_epi16(a: __m256i) -> __m128i { unsafe { transmute(vpmovsdw256(a.as_i32x8(), i16x8::ZERO, 0b11111111)) } @@ -13512,7 +13512,7 @@ pub fn _mm256_cvtsepi32_epi16(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi32_epi16&expand=1817) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm256_mask_cvtsepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsdw256(a.as_i32x8(), src.as_i16x8(), k)) } @@ -13523,7 +13523,7 @@ pub fn _mm256_mask_cvtsepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtsepi32_epi16&expand=1818) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm256_maskz_cvtsepi32_epi16(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsdw256(a.as_i32x8(), i16x8::ZERO, k)) } @@ -13534,7 +13534,7 @@ pub fn _mm256_maskz_cvtsepi32_epi16(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsepi32_epi16&expand=1813) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm_cvtsepi32_epi16(a: __m128i) -> __m128i { unsafe { transmute(vpmovsdw128(a.as_i32x4(), i16x8::ZERO, 0b11111111)) } @@ -13545,7 +13545,7 @@ pub fn _mm_cvtsepi32_epi16(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi32_epi16&expand=1814) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm_mask_cvtsepi32_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsdw128(a.as_i32x4(), src.as_i16x8(), k)) } @@ -13556,7 +13556,7 @@ pub fn _mm_mask_cvtsepi32_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtsepi32_epi16&expand=1815) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub fn _mm_maskz_cvtsepi32_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsdw128(a.as_i32x4(), i16x8::ZERO, k)) } @@ -13567,7 +13567,7 @@ pub fn _mm_maskz_cvtsepi32_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsepi32_epi8&expand=1828) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm512_cvtsepi32_epi8(a: __m512i) -> __m128i { unsafe { transmute(vpmovsdb(a.as_i32x16(), i8x16::ZERO, 0b11111111_11111111)) } @@ -13578,7 +13578,7 @@ pub fn _mm512_cvtsepi32_epi8(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi32_epi8&expand=1829) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm512_mask_cvtsepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __m128i { unsafe { transmute(vpmovsdb(a.as_i32x16(), src.as_i8x16(), k)) } @@ -13589,7 +13589,7 @@ pub fn _mm512_mask_cvtsepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtsepi32_epi8&expand=1830) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm512_maskz_cvtsepi32_epi8(k: __mmask16, a: __m512i) -> __m128i { unsafe { transmute(vpmovsdb(a.as_i32x16(), i8x16::ZERO, k)) } @@ -13600,7 +13600,7 @@ pub fn _mm512_maskz_cvtsepi32_epi8(k: __mmask16, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsepi32_epi8&expand=1825) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm256_cvtsepi32_epi8(a: __m256i) -> __m128i { unsafe { transmute(vpmovsdb256(a.as_i32x8(), i8x16::ZERO, 0b11111111)) } @@ -13611,7 +13611,7 @@ pub fn _mm256_cvtsepi32_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi32_epi8&expand=1826) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm256_mask_cvtsepi32_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsdb256(a.as_i32x8(), src.as_i8x16(), k)) } @@ -13622,7 +13622,7 @@ pub fn _mm256_mask_cvtsepi32_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtsepi32_epi8&expand=1827) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm256_maskz_cvtsepi32_epi8(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsdb256(a.as_i32x8(), i8x16::ZERO, k)) } @@ -13633,7 +13633,7 @@ pub fn _mm256_maskz_cvtsepi32_epi8(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsepi32_epi8&expand=1822) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm_cvtsepi32_epi8(a: __m128i) -> __m128i { unsafe { transmute(vpmovsdb128(a.as_i32x4(), i8x16::ZERO, 0b11111111)) } @@ -13644,7 +13644,7 @@ pub fn _mm_cvtsepi32_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi32_epi8&expand=1823) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm_mask_cvtsepi32_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsdb128(a.as_i32x4(), src.as_i8x16(), k)) } @@ -13655,7 +13655,7 @@ pub fn _mm_mask_cvtsepi32_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtsepi32_epi8&expand=1824) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub fn _mm_maskz_cvtsepi32_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsdb128(a.as_i32x4(), i8x16::ZERO, k)) } @@ -13666,7 +13666,7 @@ pub fn _mm_maskz_cvtsepi32_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsepi64_epi32&expand=1852) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm512_cvtsepi64_epi32(a: __m512i) -> __m256i { unsafe { transmute(vpmovsqd(a.as_i64x8(), i32x8::ZERO, 0b11111111)) } @@ -13677,7 +13677,7 @@ pub fn _mm512_cvtsepi64_epi32(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi64_epi32&expand=1853) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm512_mask_cvtsepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __m256i { unsafe { transmute(vpmovsqd(a.as_i64x8(), src.as_i32x8(), k)) } @@ -13688,7 +13688,7 @@ pub fn _mm512_mask_cvtsepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtsepi64_epi32&expand=1854) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm512_maskz_cvtsepi64_epi32(k: __mmask8, a: __m512i) -> __m256i { unsafe { transmute(vpmovsqd(a.as_i64x8(), i32x8::ZERO, k)) } @@ -13699,7 +13699,7 @@ pub fn _mm512_maskz_cvtsepi64_epi32(k: __mmask8, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsepi64_epi32&expand=1849) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm256_cvtsepi64_epi32(a: __m256i) -> __m128i { unsafe { transmute(vpmovsqd256(a.as_i64x4(), i32x4::ZERO, 0b11111111)) } @@ -13710,7 +13710,7 @@ pub fn _mm256_cvtsepi64_epi32(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi64_epi32&expand=1850) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm256_mask_cvtsepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsqd256(a.as_i64x4(), src.as_i32x4(), k)) } @@ -13721,7 +13721,7 @@ pub fn _mm256_mask_cvtsepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtsepi64_epi32&expand=1851) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm256_maskz_cvtsepi64_epi32(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsqd256(a.as_i64x4(), i32x4::ZERO, k)) } @@ -13732,7 +13732,7 @@ pub fn _mm256_maskz_cvtsepi64_epi32(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsepi64_epi32&expand=1846) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm_cvtsepi64_epi32(a: __m128i) -> __m128i { unsafe { transmute(vpmovsqd128(a.as_i64x2(), i32x4::ZERO, 0b11111111)) } @@ -13743,7 +13743,7 @@ pub fn _mm_cvtsepi64_epi32(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi64_epi32&expand=1847) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm_mask_cvtsepi64_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsqd128(a.as_i64x2(), src.as_i32x4(), k)) } @@ -13754,7 +13754,7 @@ pub fn _mm_mask_cvtsepi64_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtsepi64_epi32&expand=1848) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub fn _mm_maskz_cvtsepi64_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsqd128(a.as_i64x2(), i32x4::ZERO, k)) } @@ -13765,7 +13765,7 @@ pub fn _mm_maskz_cvtsepi64_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsepi64_epi16&expand=1843) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm512_cvtsepi64_epi16(a: __m512i) -> __m128i { unsafe { transmute(vpmovsqw(a.as_i64x8(), i16x8::ZERO, 0b11111111)) } @@ -13776,7 +13776,7 @@ pub fn _mm512_cvtsepi64_epi16(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi64_epi16&expand=1844) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm512_mask_cvtsepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovsqw(a.as_i64x8(), src.as_i16x8(), k)) } @@ -13787,7 +13787,7 @@ pub fn _mm512_mask_cvtsepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtsepi64_epi16&expand=1845) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm512_maskz_cvtsepi64_epi16(k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovsqw(a.as_i64x8(), i16x8::ZERO, k)) } @@ -13798,7 +13798,7 @@ pub fn _mm512_maskz_cvtsepi64_epi16(k: __mmask8, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsepi64_epi16&expand=1840) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm256_cvtsepi64_epi16(a: __m256i) -> __m128i { unsafe { transmute(vpmovsqw256(a.as_i64x4(), i16x8::ZERO, 0b11111111)) } @@ -13809,7 +13809,7 @@ pub fn _mm256_cvtsepi64_epi16(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi64_epi16&expand=1841) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm256_mask_cvtsepi64_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsqw256(a.as_i64x4(), src.as_i16x8(), k)) } @@ -13820,7 +13820,7 @@ pub fn _mm256_mask_cvtsepi64_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtsepi64_epi16&expand=1842) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm256_maskz_cvtsepi64_epi16(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsqw256(a.as_i64x4(), i16x8::ZERO, k)) } @@ -13831,7 +13831,7 @@ pub fn _mm256_maskz_cvtsepi64_epi16(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsepi64_epi16&expand=1837) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm_cvtsepi64_epi16(a: __m128i) -> __m128i { unsafe { transmute(vpmovsqw128(a.as_i64x2(), i16x8::ZERO, 0b11111111)) } @@ -13842,7 +13842,7 @@ pub fn _mm_cvtsepi64_epi16(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi64_epi16&expand=1838) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm_mask_cvtsepi64_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsqw128(a.as_i64x2(), src.as_i16x8(), k)) } @@ -13853,7 +13853,7 @@ pub fn _mm_mask_cvtsepi64_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtsepi64_epi16&expand=1839) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub fn _mm_maskz_cvtsepi64_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsqw128(a.as_i64x2(), i16x8::ZERO, k)) } @@ -13864,7 +13864,7 @@ pub fn _mm_maskz_cvtsepi64_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsepi64_epi8&expand=1861) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm512_cvtsepi64_epi8(a: __m512i) -> __m128i { unsafe { transmute(vpmovsqb(a.as_i64x8(), i8x16::ZERO, 0b11111111)) } @@ -13875,7 +13875,7 @@ pub fn _mm512_cvtsepi64_epi8(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi64_epi8&expand=1862) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm512_mask_cvtsepi64_epi8(src: __m128i, k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovsqb(a.as_i64x8(), src.as_i8x16(), k)) } @@ -13886,7 +13886,7 @@ pub fn _mm512_mask_cvtsepi64_epi8(src: __m128i, k: __mmask8, a: __m512i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtsepi64_epi8&expand=1863) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm512_maskz_cvtsepi64_epi8(k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovsqb(a.as_i64x8(), i8x16::ZERO, k)) } @@ -13897,7 +13897,7 @@ pub fn _mm512_maskz_cvtsepi64_epi8(k: __mmask8, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsepi64_epi8&expand=1858) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm256_cvtsepi64_epi8(a: __m256i) -> __m128i { unsafe { transmute(vpmovsqb256(a.as_i64x4(), i8x16::ZERO, 0b11111111)) } @@ -13908,7 +13908,7 @@ pub fn _mm256_cvtsepi64_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi64_epi8&expand=1859) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm256_mask_cvtsepi64_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsqb256(a.as_i64x4(), src.as_i8x16(), k)) } @@ -13919,7 +13919,7 @@ pub fn _mm256_mask_cvtsepi64_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtsepi64_epi8&expand=1860) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm256_maskz_cvtsepi64_epi8(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovsqb256(a.as_i64x4(), i8x16::ZERO, k)) } @@ -13930,7 +13930,7 @@ pub fn _mm256_maskz_cvtsepi64_epi8(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsepi64_epi8&expand=1855) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm_cvtsepi64_epi8(a: __m128i) -> __m128i { unsafe { transmute(vpmovsqb128(a.as_i64x2(), i8x16::ZERO, 0b11111111)) } @@ -13941,7 +13941,7 @@ pub fn _mm_cvtsepi64_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi64_epi8&expand=1856) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm_mask_cvtsepi64_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsqb128(a.as_i64x2(), src.as_i8x16(), k)) } @@ -13952,7 +13952,7 @@ pub fn _mm_mask_cvtsepi64_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtsepi64_epi8&expand=1857) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub fn _mm_maskz_cvtsepi64_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovsqb128(a.as_i64x2(), i8x16::ZERO, k)) } @@ -13963,7 +13963,7 @@ pub fn _mm_maskz_cvtsepi64_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtusepi32_epi16&expand=2054) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm512_cvtusepi32_epi16(a: __m512i) -> __m256i { unsafe { transmute(vpmovusdw(a.as_u32x16(), u16x16::ZERO, 0b11111111_11111111)) } @@ -13974,7 +13974,7 @@ pub fn _mm512_cvtusepi32_epi16(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi32_epi16&expand=2055) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm512_mask_cvtusepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> __m256i { unsafe { transmute(vpmovusdw(a.as_u32x16(), src.as_u16x16(), k)) } @@ -13985,7 +13985,7 @@ pub fn _mm512_mask_cvtusepi32_epi16(src: __m256i, k: __mmask16, a: __m512i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtusepi32_epi16&expand=2056) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm512_maskz_cvtusepi32_epi16(k: __mmask16, a: __m512i) -> __m256i { unsafe { transmute(vpmovusdw(a.as_u32x16(), u16x16::ZERO, k)) } @@ -13996,7 +13996,7 @@ pub fn _mm512_maskz_cvtusepi32_epi16(k: __mmask16, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtusepi32_epi16&expand=2051) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm256_cvtusepi32_epi16(a: __m256i) -> __m128i { unsafe { transmute(vpmovusdw256(a.as_u32x8(), u16x8::ZERO, 0b11111111)) } @@ -14007,7 +14007,7 @@ pub fn _mm256_cvtusepi32_epi16(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi32_epi16&expand=2052) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm256_mask_cvtusepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusdw256(a.as_u32x8(), src.as_u16x8(), k)) } @@ -14018,7 +14018,7 @@ pub fn _mm256_mask_cvtusepi32_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtusepi32_epi16&expand=2053) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm256_maskz_cvtusepi32_epi16(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusdw256(a.as_u32x8(), u16x8::ZERO, k)) } @@ -14029,7 +14029,7 @@ pub fn _mm256_maskz_cvtusepi32_epi16(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtusepi32_epi16&expand=2048) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm_cvtusepi32_epi16(a: __m128i) -> __m128i { unsafe { transmute(vpmovusdw128(a.as_u32x4(), u16x8::ZERO, 0b11111111)) } @@ -14040,7 +14040,7 @@ pub fn _mm_cvtusepi32_epi16(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi32_epi16&expand=2049) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm_mask_cvtusepi32_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusdw128(a.as_u32x4(), src.as_u16x8(), k)) } @@ -14051,7 +14051,7 @@ pub fn _mm_mask_cvtusepi32_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtusepi32_epi16&expand=2050) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub fn _mm_maskz_cvtusepi32_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusdw128(a.as_u32x4(), u16x8::ZERO, k)) } @@ -14062,7 +14062,7 @@ pub fn _mm_maskz_cvtusepi32_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtusepi32_epi8&expand=2063) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm512_cvtusepi32_epi8(a: __m512i) -> __m128i { unsafe { transmute(vpmovusdb(a.as_u32x16(), u8x16::ZERO, 0b11111111_11111111)) } @@ -14073,7 +14073,7 @@ pub fn _mm512_cvtusepi32_epi8(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi32_epi8&expand=2064) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm512_mask_cvtusepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __m128i { unsafe { transmute(vpmovusdb(a.as_u32x16(), src.as_u8x16(), k)) } @@ -14084,7 +14084,7 @@ pub fn _mm512_mask_cvtusepi32_epi8(src: __m128i, k: __mmask16, a: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtusepi32_epi8&expand=2065) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm512_maskz_cvtusepi32_epi8(k: __mmask16, a: __m512i) -> __m128i { unsafe { transmute(vpmovusdb(a.as_u32x16(), u8x16::ZERO, k)) } @@ -14095,7 +14095,7 @@ pub fn _mm512_maskz_cvtusepi32_epi8(k: __mmask16, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtusepi32_epi8&expand=2060) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm256_cvtusepi32_epi8(a: __m256i) -> __m128i { unsafe { transmute(vpmovusdb256(a.as_u32x8(), u8x16::ZERO, 0b11111111)) } @@ -14106,7 +14106,7 @@ pub fn _mm256_cvtusepi32_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi32_epi8&expand=2061) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm256_mask_cvtusepi32_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusdb256(a.as_u32x8(), src.as_u8x16(), k)) } @@ -14117,7 +14117,7 @@ pub fn _mm256_mask_cvtusepi32_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtusepi32_epi8&expand=2062) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm256_maskz_cvtusepi32_epi8(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusdb256(a.as_u32x8(), u8x16::ZERO, k)) } @@ -14128,7 +14128,7 @@ pub fn _mm256_maskz_cvtusepi32_epi8(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtusepi32_epi8&expand=2057) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm_cvtusepi32_epi8(a: __m128i) -> __m128i { unsafe { transmute(vpmovusdb128(a.as_u32x4(), u8x16::ZERO, 0b11111111)) } @@ -14139,7 +14139,7 @@ pub fn _mm_cvtusepi32_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi32_epi8&expand=2058) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm_mask_cvtusepi32_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusdb128(a.as_u32x4(), src.as_u8x16(), k)) } @@ -14150,7 +14150,7 @@ pub fn _mm_mask_cvtusepi32_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtusepi32_epi8&expand=2059) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub fn _mm_maskz_cvtusepi32_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusdb128(a.as_u32x4(), u8x16::ZERO, k)) } @@ -14161,7 +14161,7 @@ pub fn _mm_maskz_cvtusepi32_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtusepi64_epi32&expand=2087) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm512_cvtusepi64_epi32(a: __m512i) -> __m256i { unsafe { transmute(vpmovusqd(a.as_u64x8(), u32x8::ZERO, 0b11111111)) } @@ -14172,7 +14172,7 @@ pub fn _mm512_cvtusepi64_epi32(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi64_epi32&expand=2088) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm512_mask_cvtusepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __m256i { unsafe { transmute(vpmovusqd(a.as_u64x8(), src.as_u32x8(), k)) } @@ -14183,7 +14183,7 @@ pub fn _mm512_mask_cvtusepi64_epi32(src: __m256i, k: __mmask8, a: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtusepi64_epi32&expand=2089) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm512_maskz_cvtusepi64_epi32(k: __mmask8, a: __m512i) -> __m256i { unsafe { transmute(vpmovusqd(a.as_u64x8(), u32x8::ZERO, k)) } @@ -14194,7 +14194,7 @@ pub fn _mm512_maskz_cvtusepi64_epi32(k: __mmask8, a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtusepi64_epi32&expand=2084) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm256_cvtusepi64_epi32(a: __m256i) -> __m128i { unsafe { transmute(vpmovusqd256(a.as_u64x4(), u32x4::ZERO, 0b11111111)) } @@ -14205,7 +14205,7 @@ pub fn _mm256_cvtusepi64_epi32(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi64_epi32&expand=2085) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm256_mask_cvtusepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusqd256(a.as_u64x4(), src.as_u32x4(), k)) } @@ -14216,7 +14216,7 @@ pub fn _mm256_mask_cvtusepi64_epi32(src: __m128i, k: __mmask8, a: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtusepi64_epi32&expand=2086) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm256_maskz_cvtusepi64_epi32(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusqd256(a.as_u64x4(), u32x4::ZERO, k)) } @@ -14227,7 +14227,7 @@ pub fn _mm256_maskz_cvtusepi64_epi32(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtusepi64_epi32&expand=2081) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm_cvtusepi64_epi32(a: __m128i) -> __m128i { unsafe { transmute(vpmovusqd128(a.as_u64x2(), u32x4::ZERO, 0b11111111)) } @@ -14238,7 +14238,7 @@ pub fn _mm_cvtusepi64_epi32(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi64_epi32&expand=2082) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm_mask_cvtusepi64_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusqd128(a.as_u64x2(), src.as_u32x4(), k)) } @@ -14249,7 +14249,7 @@ pub fn _mm_mask_cvtusepi64_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtusepi64_epi32&expand=2083) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub fn _mm_maskz_cvtusepi64_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusqd128(a.as_u64x2(), u32x4::ZERO, k)) } @@ -14260,7 +14260,7 @@ pub fn _mm_maskz_cvtusepi64_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtusepi64_epi16&expand=2078) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm512_cvtusepi64_epi16(a: __m512i) -> __m128i { unsafe { transmute(vpmovusqw(a.as_u64x8(), u16x8::ZERO, 0b11111111)) } @@ -14271,7 +14271,7 @@ pub fn _mm512_cvtusepi64_epi16(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi64_epi16&expand=2079) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm512_mask_cvtusepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovusqw(a.as_u64x8(), src.as_u16x8(), k)) } @@ -14282,7 +14282,7 @@ pub fn _mm512_mask_cvtusepi64_epi16(src: __m128i, k: __mmask8, a: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtusepi64_epi16&expand=2080) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm512_maskz_cvtusepi64_epi16(k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovusqw(a.as_u64x8(), u16x8::ZERO, k)) } @@ -14293,7 +14293,7 @@ pub fn _mm512_maskz_cvtusepi64_epi16(k: __mmask8, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtusepi64_epi16&expand=2075) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm256_cvtusepi64_epi16(a: __m256i) -> __m128i { unsafe { transmute(vpmovusqw256(a.as_u64x4(), u16x8::ZERO, 0b11111111)) } @@ -14304,7 +14304,7 @@ pub fn _mm256_cvtusepi64_epi16(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi64_epi16&expand=2076) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm256_mask_cvtusepi64_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusqw256(a.as_u64x4(), src.as_u16x8(), k)) } @@ -14315,7 +14315,7 @@ pub fn _mm256_mask_cvtusepi64_epi16(src: __m128i, k: __mmask8, a: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtusepi64_epi16&expand=2077) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm256_maskz_cvtusepi64_epi16(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusqw256(a.as_u64x4(), u16x8::ZERO, k)) } @@ -14326,7 +14326,7 @@ pub fn _mm256_maskz_cvtusepi64_epi16(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtusepi64_epi16&expand=2072) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm_cvtusepi64_epi16(a: __m128i) -> __m128i { unsafe { transmute(vpmovusqw128(a.as_u64x2(), u16x8::ZERO, 0b11111111)) } @@ -14337,7 +14337,7 @@ pub fn _mm_cvtusepi64_epi16(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi64_epi16&expand=2073) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm_mask_cvtusepi64_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusqw128(a.as_u64x2(), src.as_u16x8(), k)) } @@ -14348,7 +14348,7 @@ pub fn _mm_mask_cvtusepi64_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtusepi64_epi16&expand=2074) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub fn _mm_maskz_cvtusepi64_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusqw128(a.as_u64x2(), u16x8::ZERO, k)) } @@ -14359,7 +14359,7 @@ pub fn _mm_maskz_cvtusepi64_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtusepi64_epi8&expand=2096) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm512_cvtusepi64_epi8(a: __m512i) -> __m128i { unsafe { transmute(vpmovusqb(a.as_u64x8(), u8x16::ZERO, 0b11111111)) } @@ -14370,7 +14370,7 @@ pub fn _mm512_cvtusepi64_epi8(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi64_epi8&expand=2097) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm512_mask_cvtusepi64_epi8(src: __m128i, k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovusqb(a.as_u64x8(), src.as_u8x16(), k)) } @@ -14381,7 +14381,7 @@ pub fn _mm512_mask_cvtusepi64_epi8(src: __m128i, k: __mmask8, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtusepi64_epi8&expand=2098) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm512_maskz_cvtusepi64_epi8(k: __mmask8, a: __m512i) -> __m128i { unsafe { transmute(vpmovusqb(a.as_u64x8(), u8x16::ZERO, k)) } @@ -14392,7 +14392,7 @@ pub fn _mm512_maskz_cvtusepi64_epi8(k: __mmask8, a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtusepi64_epi8&expand=2093) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm256_cvtusepi64_epi8(a: __m256i) -> __m128i { unsafe { transmute(vpmovusqb256(a.as_u64x4(), u8x16::ZERO, 0b11111111)) } @@ -14403,7 +14403,7 @@ pub fn _mm256_cvtusepi64_epi8(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi64_epi8&expand=2094) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm256_mask_cvtusepi64_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusqb256(a.as_u64x4(), src.as_u8x16(), k)) } @@ -14414,7 +14414,7 @@ pub fn _mm256_mask_cvtusepi64_epi8(src: __m128i, k: __mmask8, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtusepi64_epi8&expand=2095) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm256_maskz_cvtusepi64_epi8(k: __mmask8, a: __m256i) -> __m128i { unsafe { transmute(vpmovusqb256(a.as_u64x4(), u8x16::ZERO, k)) } @@ -14425,7 +14425,7 @@ pub fn _mm256_maskz_cvtusepi64_epi8(k: __mmask8, a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtusepi64_epi8&expand=2090) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm_cvtusepi64_epi8(a: __m128i) -> __m128i { unsafe { transmute(vpmovusqb128(a.as_u64x2(), u8x16::ZERO, 0b11111111)) } @@ -14436,7 +14436,7 @@ pub fn _mm_cvtusepi64_epi8(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi64_epi8&expand=2091) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm_mask_cvtusepi64_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusqb128(a.as_u64x2(), src.as_u8x16(), k)) } @@ -14447,7 +14447,7 @@ pub fn _mm_mask_cvtusepi64_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtusepi64_epi8&expand=2092) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub fn _mm_maskz_cvtusepi64_epi8(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpmovusqb128(a.as_u64x2(), u8x16::ZERO, k)) } @@ -14465,7 +14465,7 @@ pub fn _mm_maskz_cvtusepi64_epi8(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundps_epi32&expand=1335) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundps_epi32(a: __m512) -> __m512i { @@ -14489,7 +14489,7 @@ pub fn _mm512_cvt_roundps_epi32(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundps_epi32&expand=1336) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundps_epi32( @@ -14518,7 +14518,7 @@ pub fn _mm512_mask_cvt_roundps_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvt_roundps_epi32&expand=1337) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundps_epi32(k: __mmask16, a: __m512) -> __m512i { @@ -14542,7 +14542,7 @@ pub fn _mm512_maskz_cvt_roundps_epi32(k: __mmask16, a: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundps_epu32&expand=1341) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundps_epu32(a: __m512) -> __m512i { @@ -14566,7 +14566,7 @@ pub fn _mm512_cvt_roundps_epu32(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundps_epu32&expand=1342) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundps_epu32( @@ -14595,7 +14595,7 @@ pub fn _mm512_mask_cvt_roundps_epu32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvt_roundps_epu32&expand=1343) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundps_epu32(k: __mmask16, a: __m512) -> __m512i { @@ -14613,7 +14613,7 @@ pub fn _mm512_maskz_cvt_roundps_epu32(k: __mmask16, a: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundps_pd&expand=1347) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2pd, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundps_pd(a: __m256) -> __m512d { @@ -14631,7 +14631,7 @@ pub fn _mm512_cvt_roundps_pd(a: __m256) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundps_pd&expand=1336) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2pd, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundps_pd(src: __m512d, k: __mmask8, a: __m256) -> __m512d { @@ -14650,7 +14650,7 @@ pub fn _mm512_mask_cvt_roundps_pd(src: __m512d, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvt_roundps_pd&expand=1337) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2pd, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundps_pd(k: __mmask8, a: __m256) -> __m512d { @@ -14674,7 +14674,7 @@ pub fn _mm512_maskz_cvt_roundps_pd(k: __mmask8, a: __m256) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundpd_epi32&expand=1315) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundpd_epi32(a: __m512d) -> __m256i { @@ -14698,7 +14698,7 @@ pub fn _mm512_cvt_roundpd_epi32(a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundpd_epi32&expand=1316) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundpd_epi32( @@ -14727,7 +14727,7 @@ pub fn _mm512_mask_cvt_roundpd_epi32( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_epi32&expand=1317) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundpd_epi32(k: __mmask8, a: __m512d) -> __m256i { @@ -14751,7 +14751,7 @@ pub fn _mm512_maskz_cvt_roundpd_epi32(k: __mmask8, a: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundpd_epu32&expand=1321) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundpd_epu32(a: __m512d) -> __m256i { @@ -14775,7 +14775,7 @@ pub fn _mm512_cvt_roundpd_epu32(a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundpd_epu32&expand=1322) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundpd_epu32( @@ -14804,7 +14804,7 @@ pub fn _mm512_mask_cvt_roundpd_epu32( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/IntrinsicsGuide/#text=_mm512_maskz_cvt_roundpd_epu32&expand=1323) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundpd_epu32(k: __mmask8, a: __m512d) -> __m256i { @@ -14828,7 +14828,7 @@ pub fn _mm512_maskz_cvt_roundpd_epu32(k: __mmask8, a: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundpd_ps&expand=1327) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundpd_ps(a: __m512d) -> __m256 { @@ -14852,7 +14852,7 @@ pub fn _mm512_cvt_roundpd_ps(a: __m512d) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundpd_ps&expand=1328) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundpd_ps( @@ -14881,7 +14881,7 @@ pub fn _mm512_mask_cvt_roundpd_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvt_roundpd_ps&expand=1329) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtpd2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundpd_ps(k: __mmask8, a: __m512d) -> __m256 { @@ -14905,7 +14905,7 @@ pub fn _mm512_maskz_cvt_roundpd_ps(k: __mmask8, a: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundepi32_ps&expand=1294) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundepi32_ps(a: __m512i) -> __m512 { @@ -14929,7 +14929,7 @@ pub fn _mm512_cvt_roundepi32_ps(a: __m512i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundepi32_ps&expand=1295) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundepi32_ps( @@ -14957,7 +14957,7 @@ pub fn _mm512_mask_cvt_roundepi32_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvt_roundepi32_ps&expand=1296) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtdq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundepi32_ps(k: __mmask16, a: __m512i) -> __m512 { @@ -14981,7 +14981,7 @@ pub fn _mm512_maskz_cvt_roundepi32_ps(k: __mmask16, a: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundepu32_ps&expand=1303) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundepu32_ps(a: __m512i) -> __m512 { @@ -15005,7 +15005,7 @@ pub fn _mm512_cvt_roundepu32_ps(a: __m512i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundepu32_ps&expand=1304) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundepu32_ps( @@ -15033,7 +15033,7 @@ pub fn _mm512_mask_cvt_roundepu32_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvt_roundepu32_ps&expand=1305) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtudq2ps, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundepu32_ps(k: __mmask16, a: __m512i) -> __m512 { @@ -15061,7 +15061,7 @@ pub fn _mm512_maskz_cvt_roundepu32_ps(k: __mmask16, a: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundps_ph&expand=1354) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundps_ph(a: __m512) -> __m256i { @@ -15089,7 +15089,7 @@ pub fn _mm512_cvt_roundps_ph(a: __m512) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundps_ph&expand=1355) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundps_ph( @@ -15122,7 +15122,7 @@ pub fn _mm512_mask_cvt_roundps_ph( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvt_roundps_ph&expand=1356) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundps_ph(k: __mmask16, a: __m512) -> __m256i { @@ -15145,7 +15145,7 @@ pub fn _mm512_maskz_cvt_roundps_ph(k: __mmask16, a: __m512) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvt_roundps_ph&expand=1352) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_cvt_roundps_ph( @@ -15173,7 +15173,7 @@ pub fn _mm256_mask_cvt_roundps_ph( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvt_roundps_ph&expand=1353) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_cvt_roundps_ph(k: __mmask8, a: __m256) -> __m128i { @@ -15196,7 +15196,7 @@ pub fn _mm256_maskz_cvt_roundps_ph(k: __mmask8, a: __m256) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvt_roundps_ph&expand=1350) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_cvt_roundps_ph(src: __m128i, k: __mmask8, a: __m128) -> __m128i { @@ -15220,7 +15220,7 @@ pub fn _mm_mask_cvt_roundps_ph(src: __m128i, k: __mmask8, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvt_roundps_ph&expand=1351) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_cvt_roundps_ph(k: __mmask8, a: __m128) -> __m128i { @@ -15248,7 +15248,7 @@ pub fn _mm_maskz_cvt_roundps_ph(k: __mmask8, a: __m128) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtps_ph&expand=1778) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvtps_ph(a: __m512) -> __m256i { @@ -15276,7 +15276,7 @@ pub fn _mm512_cvtps_ph(a: __m512) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtps_ph&expand=1779) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvtps_ph(src: __m256i, k: __mmask16, a: __m512) -> __m256i { @@ -15305,7 +15305,7 @@ pub fn _mm512_mask_cvtps_ph(src: __m256i, k: __mmask16, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtps_ph&expand=1780) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvtps_ph(k: __mmask16, a: __m512) -> __m256i { @@ -15328,7 +15328,7 @@ pub fn _mm512_maskz_cvtps_ph(k: __mmask16, a: __m512) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtps_ph&expand=1776) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_cvtps_ph(src: __m128i, k: __mmask8, a: __m256) -> __m128i { @@ -15352,7 +15352,7 @@ pub fn _mm256_mask_cvtps_ph(src: __m128i, k: __mmask8, a: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtps_ph&expand=1777) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_cvtps_ph(k: __mmask8, a: __m256) -> __m128i { @@ -15375,7 +15375,7 @@ pub fn _mm256_maskz_cvtps_ph(k: __mmask8, a: __m256) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtps_ph&expand=1773) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_cvtps_ph(src: __m128i, k: __mmask8, a: __m128) -> __m128i { @@ -15399,7 +15399,7 @@ pub fn _mm_mask_cvtps_ph(src: __m128i, k: __mmask8, a: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtps_ph&expand=1774) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtps2ph, IMM8 = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_cvtps_ph(k: __mmask8, a: __m128) -> __m128i { @@ -15417,7 +15417,7 @@ pub fn _mm_maskz_cvtps_ph(k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvt_roundph_ps&expand=1332) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvt_roundph_ps(a: __m256i) -> __m512 { @@ -15435,7 +15435,7 @@ pub fn _mm512_cvt_roundph_ps(a: __m256i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvt_roundph_ps&expand=1333) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvt_roundph_ps(src: __m512, k: __mmask16, a: __m256i) -> __m512 { @@ -15454,7 +15454,7 @@ pub fn _mm512_mask_cvt_roundph_ps(src: __m512, k: __mmask16, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvt_roundph_ps&expand=1334) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvt_roundph_ps(k: __mmask16, a: __m256i) -> __m512 { @@ -15471,7 +15471,7 @@ pub fn _mm512_maskz_cvt_roundph_ps(k: __mmask16, a: __m256i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtph_ps&expand=1723) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps))] pub fn _mm512_cvtph_ps(a: __m256i) -> __m512 { unsafe { @@ -15489,7 +15489,7 @@ pub fn _mm512_cvtph_ps(a: __m256i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtph_ps&expand=1724) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps))] pub fn _mm512_mask_cvtph_ps(src: __m512, k: __mmask16, a: __m256i) -> __m512 { unsafe { @@ -15507,7 +15507,7 @@ pub fn _mm512_mask_cvtph_ps(src: __m512, k: __mmask16, a: __m256i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtph_ps&expand=1725) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps))] pub fn _mm512_maskz_cvtph_ps(k: __mmask16, a: __m256i) -> __m512 { unsafe { transmute(vcvtph2ps(a.as_i16x16(), f32x16::ZERO, k, _MM_FROUND_NO_EXC)) } @@ -15518,7 +15518,7 @@ pub fn _mm512_maskz_cvtph_ps(k: __mmask16, a: __m256i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtph_ps&expand=1721) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps))] pub fn _mm256_mask_cvtph_ps(src: __m256, k: __mmask8, a: __m128i) -> __m256 { unsafe { @@ -15532,7 +15532,7 @@ pub fn _mm256_mask_cvtph_ps(src: __m256, k: __mmask8, a: __m128i) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtph_ps&expand=1722) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps))] pub fn _mm256_maskz_cvtph_ps(k: __mmask8, a: __m128i) -> __m256 { unsafe { @@ -15546,7 +15546,7 @@ pub fn _mm256_maskz_cvtph_ps(k: __mmask8, a: __m128i) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtph_ps&expand=1718) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps))] pub fn _mm_mask_cvtph_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 { unsafe { @@ -15560,7 +15560,7 @@ pub fn _mm_mask_cvtph_ps(src: __m128, k: __mmask8, a: __m128i) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtph_ps&expand=1719) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtph2ps))] pub fn _mm_maskz_cvtph_ps(k: __mmask8, a: __m128i) -> __m128 { unsafe { @@ -15575,7 +15575,7 @@ pub fn _mm_maskz_cvtph_ps(k: __mmask8, a: __m128i) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtt_roundps_epi32&expand=1916) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvtt_roundps_epi32(a: __m512) -> __m512i { @@ -15593,7 +15593,7 @@ pub fn _mm512_cvtt_roundps_epi32(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtt_roundps_epi32&expand=1917) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvtt_roundps_epi32( @@ -15616,7 +15616,7 @@ pub fn _mm512_mask_cvtt_roundps_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtt_roundps_epi32&expand=1918) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvtt_roundps_epi32(k: __mmask16, a: __m512) -> __m512i { @@ -15634,7 +15634,7 @@ pub fn _mm512_maskz_cvtt_roundps_epi32(k: __mmask16, a: __m512) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtt_roundps_epu32&expand=1922) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvtt_roundps_epu32(a: __m512) -> __m512i { @@ -15652,7 +15652,7 @@ pub fn _mm512_cvtt_roundps_epu32(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtt_roundps_epu32&expand=1923) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvtt_roundps_epu32( @@ -15675,7 +15675,7 @@ pub fn _mm512_mask_cvtt_roundps_epu32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtt_roundps_epu32&expand=1924) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvtt_roundps_epu32(k: __mmask16, a: __m512) -> __m512i { @@ -15693,7 +15693,7 @@ pub fn _mm512_maskz_cvtt_roundps_epu32(k: __mmask16, a: __m512) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtt_roundpd_epi32&expand=1904) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvtt_roundpd_epi32(a: __m512d) -> __m256i { @@ -15711,7 +15711,7 @@ pub fn _mm512_cvtt_roundpd_epi32(a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtt_roundpd_epi32&expand=1905) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvtt_roundpd_epi32( @@ -15734,7 +15734,7 @@ pub fn _mm512_mask_cvtt_roundpd_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtt_roundpd_epi32&expand=1918) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvtt_roundpd_epi32(k: __mmask8, a: __m512d) -> __m256i { @@ -15752,7 +15752,7 @@ pub fn _mm512_maskz_cvtt_roundpd_epi32(k: __mmask8, a: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtt_roundpd_epu32&expand=1910) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm512_cvtt_roundpd_epu32(a: __m512d) -> __m256i { @@ -15770,7 +15770,7 @@ pub fn _mm512_cvtt_roundpd_epu32(a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtt_roundpd_epu32&expand=1911) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_cvtt_roundpd_epu32( @@ -15792,7 +15792,7 @@ pub fn _mm512_mask_cvtt_roundpd_epu32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvttps_epi32&expand=1984) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm512_cvttps_epi32(a: __m512) -> __m512i { unsafe { @@ -15810,7 +15810,7 @@ pub fn _mm512_cvttps_epi32(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvttps_epi32&expand=1985) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm512_mask_cvttps_epi32(src: __m512i, k: __mmask16, a: __m512) -> __m512i { unsafe { @@ -15828,7 +15828,7 @@ pub fn _mm512_mask_cvttps_epi32(src: __m512i, k: __mmask16, a: __m512) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvttps_epi32&expand=1986) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm512_maskz_cvttps_epi32(k: __mmask16, a: __m512) -> __m512i { unsafe { @@ -15846,7 +15846,7 @@ pub fn _mm512_maskz_cvttps_epi32(k: __mmask16, a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvttps_epi32&expand=1982) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm256_mask_cvttps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i { unsafe { transmute(vcvttps2dq256(a.as_f32x8(), src.as_i32x8(), k)) } @@ -15857,7 +15857,7 @@ pub fn _mm256_mask_cvttps_epi32(src: __m256i, k: __mmask8, a: __m256) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvttps_epi32&expand=1983) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm256_maskz_cvttps_epi32(k: __mmask8, a: __m256) -> __m256i { unsafe { transmute(vcvttps2dq256(a.as_f32x8(), i32x8::ZERO, k)) } @@ -15868,7 +15868,7 @@ pub fn _mm256_maskz_cvttps_epi32(k: __mmask8, a: __m256) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvttps_epi32&expand=1979) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm_mask_cvttps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvttps2dq128(a.as_f32x4(), src.as_i32x4(), k)) } @@ -15879,7 +15879,7 @@ pub fn _mm_mask_cvttps_epi32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvttps_epi32&expand=1980) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2dq))] pub fn _mm_maskz_cvttps_epi32(k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvttps2dq128(a.as_f32x4(), i32x4::ZERO, k)) } @@ -15890,7 +15890,7 @@ pub fn _mm_maskz_cvttps_epi32(k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvttps_epu32&expand=2002) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm512_cvttps_epu32(a: __m512) -> __m512i { unsafe { @@ -15908,7 +15908,7 @@ pub fn _mm512_cvttps_epu32(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvttps_epu32&expand=2003) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm512_mask_cvttps_epu32(src: __m512i, k: __mmask16, a: __m512) -> __m512i { unsafe { @@ -15926,7 +15926,7 @@ pub fn _mm512_mask_cvttps_epu32(src: __m512i, k: __mmask16, a: __m512) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvttps_epu32&expand=2004) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm512_maskz_cvttps_epu32(k: __mmask16, a: __m512) -> __m512i { unsafe { @@ -15944,7 +15944,7 @@ pub fn _mm512_maskz_cvttps_epu32(k: __mmask16, a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvttps_epu32&expand=1999) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm256_cvttps_epu32(a: __m256) -> __m256i { unsafe { transmute(vcvttps2udq256(a.as_f32x8(), u32x8::ZERO, 0b11111111)) } @@ -15955,7 +15955,7 @@ pub fn _mm256_cvttps_epu32(a: __m256) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvttps_epu32&expand=2000) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm256_mask_cvttps_epu32(src: __m256i, k: __mmask8, a: __m256) -> __m256i { unsafe { transmute(vcvttps2udq256(a.as_f32x8(), src.as_u32x8(), k)) } @@ -15966,7 +15966,7 @@ pub fn _mm256_mask_cvttps_epu32(src: __m256i, k: __mmask8, a: __m256) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvttps_epu32&expand=2001) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm256_maskz_cvttps_epu32(k: __mmask8, a: __m256) -> __m256i { unsafe { transmute(vcvttps2udq256(a.as_f32x8(), u32x8::ZERO, k)) } @@ -15977,7 +15977,7 @@ pub fn _mm256_maskz_cvttps_epu32(k: __mmask8, a: __m256) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttps_epu32&expand=1996) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm_cvttps_epu32(a: __m128) -> __m128i { unsafe { transmute(vcvttps2udq128(a.as_f32x4(), u32x4::ZERO, 0b11111111)) } @@ -15988,7 +15988,7 @@ pub fn _mm_cvttps_epu32(a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvttps_epu32&expand=1997) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm_mask_cvttps_epu32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvttps2udq128(a.as_f32x4(), src.as_u32x4(), k)) } @@ -15999,7 +15999,7 @@ pub fn _mm_mask_cvttps_epu32(src: __m128i, k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvttps_epu32&expand=1998) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttps2udq))] pub fn _mm_maskz_cvttps_epu32(k: __mmask8, a: __m128) -> __m128i { unsafe { transmute(vcvttps2udq128(a.as_f32x4(), u32x4::ZERO, k)) } @@ -16011,7 +16011,7 @@ pub fn _mm_maskz_cvttps_epu32(k: __mmask8, a: __m128) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtt_roundpd_epu32&expand=1912) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_cvtt_roundpd_epu32(k: __mmask8, a: __m512d) -> __m256i { @@ -16028,7 +16028,7 @@ pub fn _mm512_maskz_cvtt_roundpd_epu32(k: __mmask8, a: __m512d) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvttpd_epi32&expand=1947) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm512_cvttpd_epi32(a: __m512d) -> __m256i { unsafe { @@ -16046,7 +16046,7 @@ pub fn _mm512_cvttpd_epi32(a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvttpd_epi32&expand=1948) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm512_mask_cvttpd_epi32(src: __m256i, k: __mmask8, a: __m512d) -> __m256i { unsafe { @@ -16064,7 +16064,7 @@ pub fn _mm512_mask_cvttpd_epi32(src: __m256i, k: __mmask8, a: __m512d) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvttpd_epi32&expand=1949) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm512_maskz_cvttpd_epi32(k: __mmask8, a: __m512d) -> __m256i { unsafe { @@ -16082,7 +16082,7 @@ pub fn _mm512_maskz_cvttpd_epi32(k: __mmask8, a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvttpd_epi32&expand=1945) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm256_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i { unsafe { transmute(vcvttpd2dq256(a.as_f64x4(), src.as_i32x4(), k)) } @@ -16093,7 +16093,7 @@ pub fn _mm256_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m256d) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvttpd_epi32&expand=1946) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm256_maskz_cvttpd_epi32(k: __mmask8, a: __m256d) -> __m128i { unsafe { transmute(vcvttpd2dq256(a.as_f64x4(), i32x4::ZERO, k)) } @@ -16104,7 +16104,7 @@ pub fn _mm256_maskz_cvttpd_epi32(k: __mmask8, a: __m256d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvttpd_epi32&expand=1942) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvttpd2dq128(a.as_f64x2(), src.as_i32x4(), k)) } @@ -16115,7 +16115,7 @@ pub fn _mm_mask_cvttpd_epi32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvttpd_epi32&expand=1943) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2dq))] pub fn _mm_maskz_cvttpd_epi32(k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvttpd2dq128(a.as_f64x2(), i32x4::ZERO, k)) } @@ -16126,7 +16126,7 @@ pub fn _mm_maskz_cvttpd_epi32(k: __mmask8, a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvttpd_epu32&expand=1965) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm512_cvttpd_epu32(a: __m512d) -> __m256i { unsafe { @@ -16144,7 +16144,7 @@ pub fn _mm512_cvttpd_epu32(a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvttpd_epu32&expand=1966) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm512_mask_cvttpd_epu32(src: __m256i, k: __mmask8, a: __m512d) -> __m256i { unsafe { @@ -16162,7 +16162,7 @@ pub fn _mm512_mask_cvttpd_epu32(src: __m256i, k: __mmask8, a: __m512d) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvttpd_epu32&expand=1967) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm512_maskz_cvttpd_epu32(k: __mmask8, a: __m512d) -> __m256i { unsafe { @@ -16180,7 +16180,7 @@ pub fn _mm512_maskz_cvttpd_epu32(k: __mmask8, a: __m512d) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvttpd_epu32&expand=1962) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm256_cvttpd_epu32(a: __m256d) -> __m128i { unsafe { transmute(vcvttpd2udq256(a.as_f64x4(), i32x4::ZERO, 0b11111111)) } @@ -16191,7 +16191,7 @@ pub fn _mm256_cvttpd_epu32(a: __m256d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvttpd_epu32&expand=1963) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm256_mask_cvttpd_epu32(src: __m128i, k: __mmask8, a: __m256d) -> __m128i { unsafe { transmute(vcvttpd2udq256(a.as_f64x4(), src.as_i32x4(), k)) } @@ -16202,7 +16202,7 @@ pub fn _mm256_mask_cvttpd_epu32(src: __m128i, k: __mmask8, a: __m256d) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvttpd_epu32&expand=1964) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm256_maskz_cvttpd_epu32(k: __mmask8, a: __m256d) -> __m128i { unsafe { transmute(vcvttpd2udq256(a.as_f64x4(), i32x4::ZERO, k)) } @@ -16213,7 +16213,7 @@ pub fn _mm256_maskz_cvttpd_epu32(k: __mmask8, a: __m256d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttpd_epu32&expand=1959) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm_cvttpd_epu32(a: __m128d) -> __m128i { unsafe { transmute(vcvttpd2udq128(a.as_f64x2(), i32x4::ZERO, 0b11111111)) } @@ -16224,7 +16224,7 @@ pub fn _mm_cvttpd_epu32(a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvttpd_epu32&expand=1960) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm_mask_cvttpd_epu32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvttpd2udq128(a.as_f64x2(), src.as_i32x4(), k)) } @@ -16235,7 +16235,7 @@ pub fn _mm_mask_cvttpd_epu32(src: __m128i, k: __mmask8, a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvttpd_epu32&expand=1961) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttpd2udq))] pub fn _mm_maskz_cvttpd_epu32(k: __mmask8, a: __m128d) -> __m128i { unsafe { transmute(vcvttpd2udq128(a.as_f64x2(), i32x4::ZERO, k)) } @@ -16246,7 +16246,7 @@ pub fn _mm_maskz_cvttpd_epu32(k: __mmask8, a: __m128d) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setzero_pd&expand=5018) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxorps))] pub fn _mm512_setzero_pd() -> __m512d { // All-0 is a properly initialized __m512d @@ -16258,7 +16258,7 @@ pub fn _mm512_setzero_pd() -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setzero_ps&expand=5021) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxorps))] pub fn _mm512_setzero_ps() -> __m512 { // All-0 is a properly initialized __m512 @@ -16270,7 +16270,7 @@ pub fn _mm512_setzero_ps() -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setzero&expand=5014) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxorps))] pub fn _mm512_setzero() -> __m512 { // All-0 is a properly initialized __m512 @@ -16282,7 +16282,7 @@ pub fn _mm512_setzero() -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setzero_si512&expand=5024) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxorps))] pub fn _mm512_setzero_si512() -> __m512i { // All-0 is a properly initialized __m512i @@ -16294,7 +16294,7 @@ pub fn _mm512_setzero_si512() -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setzero_epi32&expand=5015) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxorps))] pub fn _mm512_setzero_epi32() -> __m512i { // All-0 is a properly initialized __m512i @@ -16307,7 +16307,7 @@ pub fn _mm512_setzero_epi32() -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setr_epi32&expand=4991) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_setr_epi32( e15: i32, e14: i32, @@ -16339,7 +16339,7 @@ pub fn _mm512_setr_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set_epi8&expand=4915) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set_epi8( e63: i8, e62: i8, @@ -16422,7 +16422,7 @@ pub fn _mm512_set_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set_epi16&expand=4905) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set_epi16( e31: i16, e30: i16, @@ -16471,7 +16471,7 @@ pub fn _mm512_set_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set4_epi32&expand=4982) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i { _mm512_set_epi32(d, c, b, a, d, c, b, a, d, c, b, a, d, c, b, a) } @@ -16481,7 +16481,7 @@ pub fn _mm512_set4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set4_ps&expand=4985) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 { _mm512_set_ps(d, c, b, a, d, c, b, a, d, c, b, a, d, c, b, a) } @@ -16491,7 +16491,7 @@ pub fn _mm512_set4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set4_pd&expand=4984) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d { _mm512_set_pd(d, c, b, a, d, c, b, a) } @@ -16501,7 +16501,7 @@ pub fn _mm512_set4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setr4_epi32&expand=5009) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_setr4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i { _mm512_set_epi32(a, b, c, d, a, b, c, d, a, b, c, d, a, b, c, d) } @@ -16511,7 +16511,7 @@ pub fn _mm512_setr4_epi32(d: i32, c: i32, b: i32, a: i32) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setr4_ps&expand=5012) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_setr4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 { _mm512_set_ps(a, b, c, d, a, b, c, d, a, b, c, d, a, b, c, d) } @@ -16521,7 +16521,7 @@ pub fn _mm512_setr4_ps(d: f32, c: f32, b: f32, a: f32) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setr4_pd&expand=5011) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_setr4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d { _mm512_set_pd(a, b, c, d, a, b, c, d) } @@ -16531,7 +16531,7 @@ pub fn _mm512_setr4_pd(d: f64, c: f64, b: f64, a: f64) -> __m512d { /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set_epi64&expand=4910) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set_epi64( e0: i64, e1: i64, @@ -16550,7 +16550,7 @@ pub fn _mm512_set_epi64( /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setr_epi64&expand=4993) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_setr_epi64( e0: i64, e1: i64, @@ -16572,7 +16572,7 @@ pub fn _mm512_setr_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i32gather_pd&expand=3002) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgatherdpd, SCALE = 1))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_i32gather_pd( @@ -16593,7 +16593,7 @@ pub unsafe fn _mm512_i32gather_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i32gather_pd&expand=3003) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgatherdpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i32gather_pd( @@ -16615,7 +16615,7 @@ pub unsafe fn _mm512_mask_i32gather_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i64gather_pd&expand=3092) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgatherqpd, SCALE = 1))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_i64gather_pd( @@ -16636,7 +16636,7 @@ pub unsafe fn _mm512_i64gather_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i64gather_pd&expand=3093) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgatherqpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i64gather_pd( @@ -16658,7 +16658,7 @@ pub unsafe fn _mm512_mask_i64gather_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i64gather_ps&expand=3100) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgatherqps, SCALE = 1))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_i64gather_ps(offsets: __m512i, slice: *const f32) -> __m256 { @@ -16676,7 +16676,7 @@ pub unsafe fn _mm512_i64gather_ps(offsets: __m512i, slice: *co /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i64gather_ps&expand=3101) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgatherqps, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i64gather_ps( @@ -16698,7 +16698,7 @@ pub unsafe fn _mm512_mask_i64gather_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i32gather_ps&expand=3010) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgatherdps, SCALE = 1))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_i32gather_ps(offsets: __m512i, slice: *const f32) -> __m512 { @@ -16716,7 +16716,7 @@ pub unsafe fn _mm512_i32gather_ps(offsets: __m512i, slice: *co /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i32gather_ps&expand=3011) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgatherdps, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i32gather_ps( @@ -16738,7 +16738,7 @@ pub unsafe fn _mm512_mask_i32gather_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i32gather_epi32&expand=2986) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpgatherdd, SCALE = 1))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_i32gather_epi32( @@ -16759,7 +16759,7 @@ pub unsafe fn _mm512_i32gather_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i32gather_epi32&expand=2987) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpgatherdd, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i32gather_epi32( @@ -16782,7 +16782,7 @@ pub unsafe fn _mm512_mask_i32gather_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i32gather_epi64&expand=2994) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpgatherdq, SCALE = 1))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_i32gather_epi64( @@ -16803,7 +16803,7 @@ pub unsafe fn _mm512_i32gather_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i32gather_epi64&expand=2995) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpgatherdq, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i32gather_epi64( @@ -16826,7 +16826,7 @@ pub unsafe fn _mm512_mask_i32gather_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i64gather_epi64&expand=3084) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpgatherqq, SCALE = 1))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_i64gather_epi64( @@ -16847,7 +16847,7 @@ pub unsafe fn _mm512_i64gather_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i64gather_epi64&expand=3085) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpgatherqq, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i64gather_epi64( @@ -16870,7 +16870,7 @@ pub unsafe fn _mm512_mask_i64gather_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i64gather_epi32&expand=3074) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpgatherqd, SCALE = 1))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_i64gather_epi32( @@ -16891,7 +16891,7 @@ pub unsafe fn _mm512_i64gather_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i64gather_epi32&expand=3075) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpgatherqd, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i64gather_epi32( @@ -16914,7 +16914,7 @@ pub unsafe fn _mm512_mask_i64gather_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i32scatter_pd&expand=3044) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscatterdpd, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm512_i32scatter_pd( @@ -16935,7 +16935,7 @@ pub unsafe fn _mm512_i32scatter_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i32scatter_pd&expand=3045) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscatterdpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i32scatter_pd( @@ -16956,7 +16956,7 @@ pub unsafe fn _mm512_mask_i32scatter_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i64scatter_pd&expand=3122) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscatterqpd, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm512_i64scatter_pd( @@ -16977,7 +16977,7 @@ pub unsafe fn _mm512_i64scatter_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i64scatter_pd&expand=3123) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscatterqpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i64scatter_pd( @@ -16998,7 +16998,7 @@ pub unsafe fn _mm512_mask_i64scatter_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i32scatter_ps&expand=3050) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscatterdps, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm512_i32scatter_ps( @@ -17019,7 +17019,7 @@ pub unsafe fn _mm512_i32scatter_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i32scatter_ps&expand=3051) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscatterdps, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i32scatter_ps( @@ -17040,7 +17040,7 @@ pub unsafe fn _mm512_mask_i32scatter_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i64scatter_ps&expand=3128) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscatterqps, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm512_i64scatter_ps( @@ -17061,7 +17061,7 @@ pub unsafe fn _mm512_i64scatter_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i64scatter_ps&expand=3129) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscatterqps, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i64scatter_ps( @@ -17082,7 +17082,7 @@ pub unsafe fn _mm512_mask_i64scatter_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i32scatter_epi64&expand=3038) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterdq, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm512_i32scatter_epi64( @@ -17103,7 +17103,7 @@ pub unsafe fn _mm512_i32scatter_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i32scatter_epi64&expand=3039) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterdq, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i32scatter_epi64( @@ -17125,7 +17125,7 @@ pub unsafe fn _mm512_mask_i32scatter_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i64scatter_epi64&expand=3116) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterqq, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm512_i64scatter_epi64( @@ -17146,7 +17146,7 @@ pub unsafe fn _mm512_i64scatter_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i64scatter_epi64&expand=3117) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterqq, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i64scatter_epi64( @@ -17168,7 +17168,7 @@ pub unsafe fn _mm512_mask_i64scatter_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i32scatter_epi32&expand=3032) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterdd, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm512_i32scatter_epi32( @@ -17189,7 +17189,7 @@ pub unsafe fn _mm512_i32scatter_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i32scatter_epi32&expand=3033) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterdd, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i32scatter_epi32( @@ -17211,7 +17211,7 @@ pub unsafe fn _mm512_mask_i32scatter_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_i64scatter_epi32&expand=3108) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterqd, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm512_i64scatter_epi32( @@ -17232,7 +17232,7 @@ pub unsafe fn _mm512_i64scatter_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_i64scatter_epi32&expand=3109) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterqd, SCALE = 1))] #[rustc_legacy_const_generics(4)] pub unsafe fn _mm512_mask_i64scatter_epi32( @@ -17257,7 +17257,7 @@ pub unsafe fn _mm512_mask_i64scatter_epi32( #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vpgatherdq, SCALE = 1))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_i32logather_epi64( vindex: __m512i, base_addr: *const i64, @@ -17274,7 +17274,7 @@ pub unsafe fn _mm512_i32logather_epi64( #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vpgatherdq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_i32logather_epi64( src: __m512i, k: __mmask8, @@ -17292,7 +17292,7 @@ pub unsafe fn _mm512_mask_i32logather_epi64( #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vgatherdpd, SCALE = 1))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_i32logather_pd( vindex: __m512i, base_addr: *const f64, @@ -17309,7 +17309,7 @@ pub unsafe fn _mm512_i32logather_pd( #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vgatherdpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_i32logather_pd( src: __m512d, k: __mmask8, @@ -17327,7 +17327,7 @@ pub unsafe fn _mm512_mask_i32logather_pd( #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vpscatterdq, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_i32loscatter_epi64( base_addr: *mut i64, vindex: __m512i, @@ -17345,7 +17345,7 @@ pub unsafe fn _mm512_i32loscatter_epi64( #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vpscatterdq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_i32loscatter_epi64( base_addr: *mut i64, k: __mmask8, @@ -17363,7 +17363,7 @@ pub unsafe fn _mm512_mask_i32loscatter_epi64( #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vscatterdpd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_i32loscatter_pd( base_addr: *mut f64, vindex: __m512i, @@ -17381,7 +17381,7 @@ pub unsafe fn _mm512_i32loscatter_pd( #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vscatterdpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_i32loscatter_pd( base_addr: *mut f64, k: __mmask8, @@ -17399,7 +17399,7 @@ pub unsafe fn _mm512_mask_i32loscatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterdd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_i32scatter_epi32( base_addr: *mut i32, vindex: __m256i, @@ -17418,7 +17418,7 @@ pub unsafe fn _mm256_i32scatter_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterdd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_i32scatter_epi32( base_addr: *mut i32, k: __mmask8, @@ -17434,7 +17434,7 @@ pub unsafe fn _mm256_mask_i32scatter_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_i32scatter_epi64&expand=4099) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpscatterdq, SCALE = 1))] #[rustc_legacy_const_generics(3)] pub unsafe fn _mm256_i32scatter_epi64( @@ -17458,7 +17458,7 @@ pub unsafe fn _mm256_i32scatter_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterdq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_i32scatter_epi64( base_addr: *mut i64, k: __mmask8, @@ -17477,7 +17477,7 @@ pub unsafe fn _mm256_mask_i32scatter_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterdpd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_i32scatter_pd( base_addr: *mut f64, vindex: __m128i, @@ -17496,7 +17496,7 @@ pub unsafe fn _mm256_i32scatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterdpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_i32scatter_pd( base_addr: *mut f64, k: __mmask8, @@ -17515,7 +17515,7 @@ pub unsafe fn _mm256_mask_i32scatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterdps, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_i32scatter_ps( base_addr: *mut f32, vindex: __m256i, @@ -17534,7 +17534,7 @@ pub unsafe fn _mm256_i32scatter_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterdps, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_i32scatter_ps( base_addr: *mut f32, k: __mmask8, @@ -17553,7 +17553,7 @@ pub unsafe fn _mm256_mask_i32scatter_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterqd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_i64scatter_epi32( base_addr: *mut i32, vindex: __m256i, @@ -17572,7 +17572,7 @@ pub unsafe fn _mm256_i64scatter_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterqd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_i64scatter_epi32( base_addr: *mut i32, k: __mmask8, @@ -17591,7 +17591,7 @@ pub unsafe fn _mm256_mask_i64scatter_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterqq, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_i64scatter_epi64( base_addr: *mut i64, vindex: __m256i, @@ -17610,7 +17610,7 @@ pub unsafe fn _mm256_i64scatter_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterqq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_i64scatter_epi64( base_addr: *mut i64, k: __mmask8, @@ -17629,7 +17629,7 @@ pub unsafe fn _mm256_mask_i64scatter_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterqpd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_i64scatter_pd( base_addr: *mut f64, vindex: __m256i, @@ -17648,7 +17648,7 @@ pub unsafe fn _mm256_i64scatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterqpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_i64scatter_pd( base_addr: *mut f64, k: __mmask8, @@ -17667,7 +17667,7 @@ pub unsafe fn _mm256_mask_i64scatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterqps, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_i64scatter_ps( base_addr: *mut f32, vindex: __m256i, @@ -17686,7 +17686,7 @@ pub unsafe fn _mm256_i64scatter_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterqps, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_i64scatter_ps( base_addr: *mut f32, k: __mmask8, @@ -17706,7 +17706,7 @@ pub unsafe fn _mm256_mask_i64scatter_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpgatherdd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mmask_i32gather_epi32( src: __m256i, k: __mmask8, @@ -17732,7 +17732,7 @@ pub unsafe fn _mm256_mmask_i32gather_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpgatherdq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mmask_i32gather_epi64( src: __m256i, k: __mmask8, @@ -17758,7 +17758,7 @@ pub unsafe fn _mm256_mmask_i32gather_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vgatherdpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mmask_i32gather_pd( src: __m256d, k: __mmask8, @@ -17784,7 +17784,7 @@ pub unsafe fn _mm256_mmask_i32gather_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vgatherdps, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mmask_i32gather_ps( src: __m256, k: __mmask8, @@ -17810,7 +17810,7 @@ pub unsafe fn _mm256_mmask_i32gather_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpgatherqd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mmask_i64gather_epi32( src: __m128i, k: __mmask8, @@ -17836,7 +17836,7 @@ pub unsafe fn _mm256_mmask_i64gather_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpgatherqq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mmask_i64gather_epi64( src: __m256i, k: __mmask8, @@ -17862,7 +17862,7 @@ pub unsafe fn _mm256_mmask_i64gather_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vgatherqpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mmask_i64gather_pd( src: __m256d, k: __mmask8, @@ -17888,7 +17888,7 @@ pub unsafe fn _mm256_mmask_i64gather_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vgatherqps, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mmask_i64gather_ps( src: __m128, k: __mmask8, @@ -17913,7 +17913,7 @@ pub unsafe fn _mm256_mmask_i64gather_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterdd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_i32scatter_epi32( base_addr: *mut i32, vindex: __m128i, @@ -17932,7 +17932,7 @@ pub unsafe fn _mm_i32scatter_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterdd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_i32scatter_epi32( base_addr: *mut i32, k: __mmask8, @@ -17951,7 +17951,7 @@ pub unsafe fn _mm_mask_i32scatter_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterdq, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_i32scatter_epi64( base_addr: *mut i64, vindex: __m128i, @@ -17970,7 +17970,7 @@ pub unsafe fn _mm_i32scatter_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterdq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_i32scatter_epi64( base_addr: *mut i64, k: __mmask8, @@ -17989,7 +17989,7 @@ pub unsafe fn _mm_mask_i32scatter_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterdpd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_i32scatter_pd( base_addr: *mut f64, vindex: __m128i, @@ -18008,7 +18008,7 @@ pub unsafe fn _mm_i32scatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterdpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_i32scatter_pd( base_addr: *mut f64, k: __mmask8, @@ -18027,7 +18027,7 @@ pub unsafe fn _mm_mask_i32scatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterdps, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_i32scatter_ps(base_addr: *mut f32, vindex: __m128i, a: __m128) { static_assert_imm8_scale!(SCALE); vscatterdps_128(base_addr as _, 0xff, vindex.as_i32x4(), a.as_f32x4(), SCALE) @@ -18042,7 +18042,7 @@ pub unsafe fn _mm_i32scatter_ps(base_addr: *mut f32, vindex: _ #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterdps, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_i32scatter_ps( base_addr: *mut f32, k: __mmask8, @@ -18061,7 +18061,7 @@ pub unsafe fn _mm_mask_i32scatter_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterqd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_i64scatter_epi32( base_addr: *mut i32, vindex: __m128i, @@ -18080,7 +18080,7 @@ pub unsafe fn _mm_i64scatter_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterqd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_i64scatter_epi32( base_addr: *mut i32, k: __mmask8, @@ -18099,7 +18099,7 @@ pub unsafe fn _mm_mask_i64scatter_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterqq, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_i64scatter_epi64( base_addr: *mut i64, vindex: __m128i, @@ -18118,7 +18118,7 @@ pub unsafe fn _mm_i64scatter_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpscatterqq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_i64scatter_epi64( base_addr: *mut i64, k: __mmask8, @@ -18137,7 +18137,7 @@ pub unsafe fn _mm_mask_i64scatter_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterqpd, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_i64scatter_pd( base_addr: *mut f64, vindex: __m128i, @@ -18156,7 +18156,7 @@ pub unsafe fn _mm_i64scatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterqpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_i64scatter_pd( base_addr: *mut f64, k: __mmask8, @@ -18175,7 +18175,7 @@ pub unsafe fn _mm_mask_i64scatter_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterqps, SCALE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_i64scatter_ps(base_addr: *mut f32, vindex: __m128i, a: __m128) { static_assert_imm8_scale!(SCALE); vscatterqps_128(base_addr as _, 0xff, vindex.as_i64x2(), a.as_f32x4(), SCALE) @@ -18189,7 +18189,7 @@ pub unsafe fn _mm_i64scatter_ps(base_addr: *mut f32, vindex: _ #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vscatterqps, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_i64scatter_ps( base_addr: *mut f32, k: __mmask8, @@ -18209,7 +18209,7 @@ pub unsafe fn _mm_mask_i64scatter_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpgatherdd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mmask_i32gather_epi32( src: __m128i, k: __mmask8, @@ -18235,7 +18235,7 @@ pub unsafe fn _mm_mmask_i32gather_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpgatherdq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mmask_i32gather_epi64( src: __m128i, k: __mmask8, @@ -18261,7 +18261,7 @@ pub unsafe fn _mm_mmask_i32gather_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vgatherdpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mmask_i32gather_pd( src: __m128d, k: __mmask8, @@ -18287,7 +18287,7 @@ pub unsafe fn _mm_mmask_i32gather_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vgatherdps, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mmask_i32gather_ps( src: __m128, k: __mmask8, @@ -18313,7 +18313,7 @@ pub unsafe fn _mm_mmask_i32gather_ps( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpgatherqd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mmask_i64gather_epi32( src: __m128i, k: __mmask8, @@ -18339,7 +18339,7 @@ pub unsafe fn _mm_mmask_i64gather_epi32( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpgatherqq, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mmask_i64gather_epi64( src: __m128i, k: __mmask8, @@ -18365,7 +18365,7 @@ pub unsafe fn _mm_mmask_i64gather_epi64( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vgatherqpd, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mmask_i64gather_pd( src: __m128d, k: __mmask8, @@ -18391,7 +18391,7 @@ pub unsafe fn _mm_mmask_i64gather_pd( #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vgatherqps, SCALE = 1))] #[rustc_legacy_const_generics(4)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mmask_i64gather_ps( src: __m128, k: __mmask8, @@ -18413,7 +18413,7 @@ pub unsafe fn _mm_mmask_i64gather_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compress_epi32&expand=1198) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub fn _mm512_mask_compress_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { unsafe { transmute(vpcompressd(a.as_i32x16(), src.as_i32x16(), k)) } @@ -18424,7 +18424,7 @@ pub fn _mm512_mask_compress_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_compress_epi32&expand=1199) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub fn _mm512_maskz_compress_epi32(k: __mmask16, a: __m512i) -> __m512i { unsafe { transmute(vpcompressd(a.as_i32x16(), i32x16::ZERO, k)) } @@ -18435,7 +18435,7 @@ pub fn _mm512_maskz_compress_epi32(k: __mmask16, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compress_epi32&expand=1196) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub fn _mm256_mask_compress_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { transmute(vpcompressd256(a.as_i32x8(), src.as_i32x8(), k)) } @@ -18446,7 +18446,7 @@ pub fn _mm256_mask_compress_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_compress_epi32&expand=1197) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub fn _mm256_maskz_compress_epi32(k: __mmask8, a: __m256i) -> __m256i { unsafe { transmute(vpcompressd256(a.as_i32x8(), i32x8::ZERO, k)) } @@ -18457,7 +18457,7 @@ pub fn _mm256_maskz_compress_epi32(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compress_epi32&expand=1194) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub fn _mm_mask_compress_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpcompressd128(a.as_i32x4(), src.as_i32x4(), k)) } @@ -18468,7 +18468,7 @@ pub fn _mm_mask_compress_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_compress_epi32&expand=1195) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub fn _mm_maskz_compress_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpcompressd128(a.as_i32x4(), i32x4::ZERO, k)) } @@ -18479,7 +18479,7 @@ pub fn _mm_maskz_compress_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compress_epi64&expand=1204) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub fn _mm512_mask_compress_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { unsafe { transmute(vpcompressq(a.as_i64x8(), src.as_i64x8(), k)) } @@ -18490,7 +18490,7 @@ pub fn _mm512_mask_compress_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_compress_epi64&expand=1205) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub fn _mm512_maskz_compress_epi64(k: __mmask8, a: __m512i) -> __m512i { unsafe { transmute(vpcompressq(a.as_i64x8(), i64x8::ZERO, k)) } @@ -18501,7 +18501,7 @@ pub fn _mm512_maskz_compress_epi64(k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compress_epi64&expand=1202) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub fn _mm256_mask_compress_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { transmute(vpcompressq256(a.as_i64x4(), src.as_i64x4(), k)) } @@ -18512,7 +18512,7 @@ pub fn _mm256_mask_compress_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_compress_epi64&expand=1203) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub fn _mm256_maskz_compress_epi64(k: __mmask8, a: __m256i) -> __m256i { unsafe { transmute(vpcompressq256(a.as_i64x4(), i64x4::ZERO, k)) } @@ -18523,7 +18523,7 @@ pub fn _mm256_maskz_compress_epi64(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compress_epi64&expand=1200) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub fn _mm_mask_compress_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpcompressq128(a.as_i64x2(), src.as_i64x2(), k)) } @@ -18534,7 +18534,7 @@ pub fn _mm_mask_compress_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_compress_epi64&expand=1201) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub fn _mm_maskz_compress_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpcompressq128(a.as_i64x2(), i64x2::ZERO, k)) } @@ -18545,7 +18545,7 @@ pub fn _mm_maskz_compress_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compress_ps&expand=1222) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub fn _mm512_mask_compress_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { transmute(vcompressps(a.as_f32x16(), src.as_f32x16(), k)) } @@ -18556,7 +18556,7 @@ pub fn _mm512_mask_compress_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_compress_ps&expand=1223) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub fn _mm512_maskz_compress_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { transmute(vcompressps(a.as_f32x16(), f32x16::ZERO, k)) } @@ -18567,7 +18567,7 @@ pub fn _mm512_maskz_compress_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compress_ps&expand=1220) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub fn _mm256_mask_compress_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vcompressps256(a.as_f32x8(), src.as_f32x8(), k)) } @@ -18578,7 +18578,7 @@ pub fn _mm256_mask_compress_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_compress_ps&expand=1221) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub fn _mm256_maskz_compress_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vcompressps256(a.as_f32x8(), f32x8::ZERO, k)) } @@ -18589,7 +18589,7 @@ pub fn _mm256_maskz_compress_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compress_ps&expand=1218) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub fn _mm_mask_compress_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vcompressps128(a.as_f32x4(), src.as_f32x4(), k)) } @@ -18600,7 +18600,7 @@ pub fn _mm_mask_compress_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_compress_ps&expand=1219) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub fn _mm_maskz_compress_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vcompressps128(a.as_f32x4(), f32x4::ZERO, k)) } @@ -18611,7 +18611,7 @@ pub fn _mm_maskz_compress_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compress_pd&expand=1216) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub fn _mm512_mask_compress_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { transmute(vcompresspd(a.as_f64x8(), src.as_f64x8(), k)) } @@ -18622,7 +18622,7 @@ pub fn _mm512_mask_compress_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_compress_pd&expand=1217) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub fn _mm512_maskz_compress_pd(k: __mmask8, a: __m512d) -> __m512d { unsafe { transmute(vcompresspd(a.as_f64x8(), f64x8::ZERO, k)) } @@ -18633,7 +18633,7 @@ pub fn _mm512_maskz_compress_pd(k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compress_pd&expand=1214) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub fn _mm256_mask_compress_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vcompresspd256(a.as_f64x4(), src.as_f64x4(), k)) } @@ -18644,7 +18644,7 @@ pub fn _mm256_mask_compress_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_compress_pd&expand=1215) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub fn _mm256_maskz_compress_pd(k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vcompresspd256(a.as_f64x4(), f64x4::ZERO, k)) } @@ -18655,7 +18655,7 @@ pub fn _mm256_maskz_compress_pd(k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compress_pd&expand=1212) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub fn _mm_mask_compress_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vcompresspd128(a.as_f64x2(), src.as_f64x2(), k)) } @@ -18666,7 +18666,7 @@ pub fn _mm_mask_compress_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_compress_pd&expand=1213) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub fn _mm_maskz_compress_pd(k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vcompresspd128(a.as_f64x2(), f64x2::ZERO, k)) } @@ -18677,7 +18677,7 @@ pub fn _mm_maskz_compress_pd(k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compressstoreu_epi32) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub unsafe fn _mm512_mask_compressstoreu_epi32(base_addr: *mut i32, k: __mmask16, a: __m512i) { vcompressstored(base_addr as *mut _, a.as_i32x16(), k) @@ -18688,7 +18688,7 @@ pub unsafe fn _mm512_mask_compressstoreu_epi32(base_addr: *mut i32, k: __mmask16 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compressstoreu_epi32) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub unsafe fn _mm256_mask_compressstoreu_epi32(base_addr: *mut i32, k: __mmask8, a: __m256i) { vcompressstored256(base_addr as *mut _, a.as_i32x8(), k) @@ -18699,7 +18699,7 @@ pub unsafe fn _mm256_mask_compressstoreu_epi32(base_addr: *mut i32, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compressstoreu_epi32) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressd))] pub unsafe fn _mm_mask_compressstoreu_epi32(base_addr: *mut i32, k: __mmask8, a: __m128i) { vcompressstored128(base_addr as *mut _, a.as_i32x4(), k) @@ -18710,7 +18710,7 @@ pub unsafe fn _mm_mask_compressstoreu_epi32(base_addr: *mut i32, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compressstoreu_epi64) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub unsafe fn _mm512_mask_compressstoreu_epi64(base_addr: *mut i64, k: __mmask8, a: __m512i) { vcompressstoreq(base_addr as *mut _, a.as_i64x8(), k) @@ -18721,7 +18721,7 @@ pub unsafe fn _mm512_mask_compressstoreu_epi64(base_addr: *mut i64, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compressstoreu_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub unsafe fn _mm256_mask_compressstoreu_epi64(base_addr: *mut i64, k: __mmask8, a: __m256i) { vcompressstoreq256(base_addr as *mut _, a.as_i64x4(), k) @@ -18732,7 +18732,7 @@ pub unsafe fn _mm256_mask_compressstoreu_epi64(base_addr: *mut i64, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compressstoreu_epi64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressq))] pub unsafe fn _mm_mask_compressstoreu_epi64(base_addr: *mut i64, k: __mmask8, a: __m128i) { vcompressstoreq128(base_addr as *mut _, a.as_i64x2(), k) @@ -18743,7 +18743,7 @@ pub unsafe fn _mm_mask_compressstoreu_epi64(base_addr: *mut i64, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compressstoreu_ps) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub unsafe fn _mm512_mask_compressstoreu_ps(base_addr: *mut f32, k: __mmask16, a: __m512) { vcompressstoreps(base_addr as *mut _, a.as_f32x16(), k) @@ -18754,7 +18754,7 @@ pub unsafe fn _mm512_mask_compressstoreu_ps(base_addr: *mut f32, k: __mmask16, a /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compressstoreu_ps) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub unsafe fn _mm256_mask_compressstoreu_ps(base_addr: *mut f32, k: __mmask8, a: __m256) { vcompressstoreps256(base_addr as *mut _, a.as_f32x8(), k) @@ -18765,7 +18765,7 @@ pub unsafe fn _mm256_mask_compressstoreu_ps(base_addr: *mut f32, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compressstoreu_ps) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompressps))] pub unsafe fn _mm_mask_compressstoreu_ps(base_addr: *mut f32, k: __mmask8, a: __m128) { vcompressstoreps128(base_addr as *mut _, a.as_f32x4(), k) @@ -18776,7 +18776,7 @@ pub unsafe fn _mm_mask_compressstoreu_ps(base_addr: *mut f32, k: __mmask8, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compressstoreu_pd) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub unsafe fn _mm512_mask_compressstoreu_pd(base_addr: *mut f64, k: __mmask8, a: __m512d) { vcompressstorepd(base_addr as *mut _, a.as_f64x8(), k) @@ -18787,7 +18787,7 @@ pub unsafe fn _mm512_mask_compressstoreu_pd(base_addr: *mut f64, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compressstoreu_pd) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub unsafe fn _mm256_mask_compressstoreu_pd(base_addr: *mut f64, k: __mmask8, a: __m256d) { vcompressstorepd256(base_addr as *mut _, a.as_f64x4(), k) @@ -18798,7 +18798,7 @@ pub unsafe fn _mm256_mask_compressstoreu_pd(base_addr: *mut f64, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compressstoreu_pd) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcompresspd))] pub unsafe fn _mm_mask_compressstoreu_pd(base_addr: *mut f64, k: __mmask8, a: __m128d) { vcompressstorepd128(base_addr as *mut _, a.as_f64x2(), k) @@ -18809,7 +18809,7 @@ pub unsafe fn _mm_mask_compressstoreu_pd(base_addr: *mut f64, k: __mmask8, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_expand_epi32&expand=2316) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandd))] pub fn _mm512_mask_expand_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { unsafe { transmute(vpexpandd(a.as_i32x16(), src.as_i32x16(), k)) } @@ -18820,7 +18820,7 @@ pub fn _mm512_mask_expand_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_expand_epi32&expand=2317) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandd))] pub fn _mm512_maskz_expand_epi32(k: __mmask16, a: __m512i) -> __m512i { unsafe { transmute(vpexpandd(a.as_i32x16(), i32x16::ZERO, k)) } @@ -18831,7 +18831,7 @@ pub fn _mm512_maskz_expand_epi32(k: __mmask16, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_expand_epi32&expand=2314) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandd))] pub fn _mm256_mask_expand_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { transmute(vpexpandd256(a.as_i32x8(), src.as_i32x8(), k)) } @@ -18842,7 +18842,7 @@ pub fn _mm256_mask_expand_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_expand_epi32&expand=2315) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandd))] pub fn _mm256_maskz_expand_epi32(k: __mmask8, a: __m256i) -> __m256i { unsafe { transmute(vpexpandd256(a.as_i32x8(), i32x8::ZERO, k)) } @@ -18853,7 +18853,7 @@ pub fn _mm256_maskz_expand_epi32(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_expand_epi32&expand=2312) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandd))] pub fn _mm_mask_expand_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpexpandd128(a.as_i32x4(), src.as_i32x4(), k)) } @@ -18864,7 +18864,7 @@ pub fn _mm_mask_expand_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_expand_epi32&expand=2313) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandd))] pub fn _mm_maskz_expand_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpexpandd128(a.as_i32x4(), i32x4::ZERO, k)) } @@ -18875,7 +18875,7 @@ pub fn _mm_maskz_expand_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_expand_epi64&expand=2322) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandq))] pub fn _mm512_mask_expand_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { unsafe { transmute(vpexpandq(a.as_i64x8(), src.as_i64x8(), k)) } @@ -18886,7 +18886,7 @@ pub fn _mm512_mask_expand_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_expand_epi64&expand=2323) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandq))] pub fn _mm512_maskz_expand_epi64(k: __mmask8, a: __m512i) -> __m512i { unsafe { transmute(vpexpandq(a.as_i64x8(), i64x8::ZERO, k)) } @@ -18897,7 +18897,7 @@ pub fn _mm512_maskz_expand_epi64(k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_expand_epi64&expand=2320) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandq))] pub fn _mm256_mask_expand_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { transmute(vpexpandq256(a.as_i64x4(), src.as_i64x4(), k)) } @@ -18908,7 +18908,7 @@ pub fn _mm256_mask_expand_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_expand_epi64&expand=2321) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandq))] pub fn _mm256_maskz_expand_epi64(k: __mmask8, a: __m256i) -> __m256i { unsafe { transmute(vpexpandq256(a.as_i64x4(), i64x4::ZERO, k)) } @@ -18919,7 +18919,7 @@ pub fn _mm256_maskz_expand_epi64(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_expand_epi64&expand=2318) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandq))] pub fn _mm_mask_expand_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpexpandq128(a.as_i64x2(), src.as_i64x2(), k)) } @@ -18930,7 +18930,7 @@ pub fn _mm_mask_expand_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_expand_epi64&expand=2319) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandq))] pub fn _mm_maskz_expand_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpexpandq128(a.as_i64x2(), i64x2::ZERO, k)) } @@ -18941,7 +18941,7 @@ pub fn _mm_maskz_expand_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_expand_ps&expand=2340) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandps))] pub fn _mm512_mask_expand_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { transmute(vexpandps(a.as_f32x16(), src.as_f32x16(), k)) } @@ -18952,7 +18952,7 @@ pub fn _mm512_mask_expand_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_expand_ps&expand=2341) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandps))] pub fn _mm512_maskz_expand_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { transmute(vexpandps(a.as_f32x16(), f32x16::ZERO, k)) } @@ -18963,7 +18963,7 @@ pub fn _mm512_maskz_expand_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_expand_ps&expand=2338) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandps))] pub fn _mm256_mask_expand_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vexpandps256(a.as_f32x8(), src.as_f32x8(), k)) } @@ -18974,7 +18974,7 @@ pub fn _mm256_mask_expand_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_expand_ps&expand=2339) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandps))] pub fn _mm256_maskz_expand_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { transmute(vexpandps256(a.as_f32x8(), f32x8::ZERO, k)) } @@ -18985,7 +18985,7 @@ pub fn _mm256_maskz_expand_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_expand_ps&expand=2336) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandps))] pub fn _mm_mask_expand_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vexpandps128(a.as_f32x4(), src.as_f32x4(), k)) } @@ -18996,7 +18996,7 @@ pub fn _mm_mask_expand_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_expand_ps&expand=2337) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandps))] pub fn _mm_maskz_expand_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { transmute(vexpandps128(a.as_f32x4(), f32x4::ZERO, k)) } @@ -19007,7 +19007,7 @@ pub fn _mm_maskz_expand_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_expand_pd&expand=2334) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandpd))] pub fn _mm512_mask_expand_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { transmute(vexpandpd(a.as_f64x8(), src.as_f64x8(), k)) } @@ -19018,7 +19018,7 @@ pub fn _mm512_mask_expand_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_expand_pd&expand=2335) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandpd))] pub fn _mm512_maskz_expand_pd(k: __mmask8, a: __m512d) -> __m512d { unsafe { transmute(vexpandpd(a.as_f64x8(), f64x8::ZERO, k)) } @@ -19029,7 +19029,7 @@ pub fn _mm512_maskz_expand_pd(k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_expand_pd&expand=2332) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandpd))] pub fn _mm256_mask_expand_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vexpandpd256(a.as_f64x4(), src.as_f64x4(), k)) } @@ -19040,7 +19040,7 @@ pub fn _mm256_mask_expand_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_expand_pd&expand=2333) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandpd))] pub fn _mm256_maskz_expand_pd(k: __mmask8, a: __m256d) -> __m256d { unsafe { transmute(vexpandpd256(a.as_f64x4(), f64x4::ZERO, k)) } @@ -19051,7 +19051,7 @@ pub fn _mm256_maskz_expand_pd(k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_expand_pd&expand=2330) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandpd))] pub fn _mm_mask_expand_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vexpandpd128(a.as_f64x2(), src.as_f64x2(), k)) } @@ -19062,7 +19062,7 @@ pub fn _mm_mask_expand_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_expand_pd&expand=2331) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vexpandpd))] pub fn _mm_maskz_expand_pd(k: __mmask8, a: __m128d) -> __m128d { unsafe { transmute(vexpandpd128(a.as_f64x2(), f64x2::ZERO, k)) } @@ -19073,7 +19073,7 @@ pub fn _mm_maskz_expand_pd(k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rol_epi32&expand=4685) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_rol_epi32(a: __m512i) -> __m512i { @@ -19090,7 +19090,7 @@ pub fn _mm512_rol_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rol_epi32&expand=4683) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_rol_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { @@ -19107,7 +19107,7 @@ pub fn _mm512_mask_rol_epi32(src: __m512i, k: __mmask16, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rol_epi32&expand=4684) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_rol_epi32(k: __mmask16, a: __m512i) -> __m512i { @@ -19124,7 +19124,7 @@ pub fn _mm512_maskz_rol_epi32(k: __mmask16, a: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rol_epi32&expand=4682) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm256_rol_epi32(a: __m256i) -> __m256i { @@ -19141,7 +19141,7 @@ pub fn _mm256_rol_epi32(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rol_epi32&expand=4680) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_rol_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -19158,7 +19158,7 @@ pub fn _mm256_mask_rol_epi32(src: __m256i, k: __mmask8, a: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rol_epi32&expand=4681) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_rol_epi32(k: __mmask8, a: __m256i) -> __m256i { @@ -19175,7 +19175,7 @@ pub fn _mm256_maskz_rol_epi32(k: __mmask8, a: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rol_epi32&expand=4679) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm_rol_epi32(a: __m128i) -> __m128i { @@ -19192,7 +19192,7 @@ pub fn _mm_rol_epi32(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rol_epi32&expand=4677) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_rol_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -19209,7 +19209,7 @@ pub fn _mm_mask_rol_epi32(src: __m128i, k: __mmask8, a: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rol_epi32&expand=4678) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_rol_epi32(k: __mmask8, a: __m128i) -> __m128i { @@ -19226,7 +19226,7 @@ pub fn _mm_maskz_rol_epi32(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_ror_epi32&expand=4721) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_ror_epi32(a: __m512i) -> __m512i { @@ -19243,7 +19243,7 @@ pub fn _mm512_ror_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_ror_epi32&expand=4719) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_ror_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { @@ -19260,7 +19260,7 @@ pub fn _mm512_mask_ror_epi32(src: __m512i, k: __mmask16, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_ror_epi32&expand=4720) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_ror_epi32(k: __mmask16, a: __m512i) -> __m512i { @@ -19277,7 +19277,7 @@ pub fn _mm512_maskz_ror_epi32(k: __mmask16, a: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_ror_epi32&expand=4718) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm256_ror_epi32(a: __m256i) -> __m256i { @@ -19294,7 +19294,7 @@ pub fn _mm256_ror_epi32(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_ror_epi32&expand=4716) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_ror_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -19311,7 +19311,7 @@ pub fn _mm256_mask_ror_epi32(src: __m256i, k: __mmask8, a: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_ror_epi32&expand=4717) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_ror_epi32(k: __mmask8, a: __m256i) -> __m256i { @@ -19328,7 +19328,7 @@ pub fn _mm256_maskz_ror_epi32(k: __mmask8, a: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ror_epi32&expand=4715) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm_ror_epi32(a: __m128i) -> __m128i { @@ -19345,7 +19345,7 @@ pub fn _mm_ror_epi32(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_ror_epi32&expand=4713) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_ror_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -19362,7 +19362,7 @@ pub fn _mm_mask_ror_epi32(src: __m128i, k: __mmask8, a: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_ror_epi32&expand=4714) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprold, IMM8 = 123))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_ror_epi32(k: __mmask8, a: __m128i) -> __m128i { @@ -19379,7 +19379,7 @@ pub fn _mm_maskz_ror_epi32(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rol_epi64&expand=4694) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_rol_epi64(a: __m512i) -> __m512i { @@ -19396,7 +19396,7 @@ pub fn _mm512_rol_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rol_epi64&expand=4692) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_rol_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { @@ -19413,7 +19413,7 @@ pub fn _mm512_mask_rol_epi64(src: __m512i, k: __mmask8, a: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rol_epi64&expand=4693) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_rol_epi64(k: __mmask8, a: __m512i) -> __m512i { @@ -19430,7 +19430,7 @@ pub fn _mm512_maskz_rol_epi64(k: __mmask8, a: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rol_epi64&expand=4691) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm256_rol_epi64(a: __m256i) -> __m256i { @@ -19447,7 +19447,7 @@ pub fn _mm256_rol_epi64(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rol_epi64&expand=4689) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_rol_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -19464,7 +19464,7 @@ pub fn _mm256_mask_rol_epi64(src: __m256i, k: __mmask8, a: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rol_epi64&expand=4690) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_rol_epi64(k: __mmask8, a: __m256i) -> __m256i { @@ -19481,7 +19481,7 @@ pub fn _mm256_maskz_rol_epi64(k: __mmask8, a: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rol_epi64&expand=4688) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm_rol_epi64(a: __m128i) -> __m128i { @@ -19498,7 +19498,7 @@ pub fn _mm_rol_epi64(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rol_epi64&expand=4686) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_rol_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -19515,7 +19515,7 @@ pub fn _mm_mask_rol_epi64(src: __m128i, k: __mmask8, a: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rol_epi64&expand=4687) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_rol_epi64(k: __mmask8, a: __m128i) -> __m128i { @@ -19532,7 +19532,7 @@ pub fn _mm_maskz_rol_epi64(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_ror_epi64&expand=4730) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(1)] pub fn _mm512_ror_epi64(a: __m512i) -> __m512i { @@ -19549,7 +19549,7 @@ pub fn _mm512_ror_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_ror_epi64&expand=4728) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_ror_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { @@ -19566,7 +19566,7 @@ pub fn _mm512_mask_ror_epi64(src: __m512i, k: __mmask8, a: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_ror_epi64&expand=4729) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_ror_epi64(k: __mmask8, a: __m512i) -> __m512i { @@ -19583,7 +19583,7 @@ pub fn _mm512_maskz_ror_epi64(k: __mmask8, a: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_ror_epi64&expand=4727) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(1)] pub fn _mm256_ror_epi64(a: __m256i) -> __m256i { @@ -19600,7 +19600,7 @@ pub fn _mm256_ror_epi64(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_ror_epi64&expand=4725) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_ror_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -19617,7 +19617,7 @@ pub fn _mm256_mask_ror_epi64(src: __m256i, k: __mmask8, a: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_ror_epi64&expand=4726) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_ror_epi64(k: __mmask8, a: __m256i) -> __m256i { @@ -19634,7 +19634,7 @@ pub fn _mm256_maskz_ror_epi64(k: __mmask8, a: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ror_epi64&expand=4724) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(1)] pub fn _mm_ror_epi64(a: __m128i) -> __m128i { @@ -19651,7 +19651,7 @@ pub fn _mm_ror_epi64(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_ror_epi64&expand=4722) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_ror_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -19668,7 +19668,7 @@ pub fn _mm_mask_ror_epi64(src: __m128i, k: __mmask8, a: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_ror_epi64&expand=4723) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolq, IMM8 = 15))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_ror_epi64(k: __mmask8, a: __m128i) -> __m128i { @@ -19685,7 +19685,7 @@ pub fn _mm_maskz_ror_epi64(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_slli_epi32&expand=5310) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))] #[rustc_legacy_const_generics(1)] pub fn _mm512_slli_epi32(a: __m512i) -> __m512i { @@ -19704,7 +19704,7 @@ pub fn _mm512_slli_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_slli_epi32&expand=5308) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_slli_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { @@ -19724,7 +19724,7 @@ pub fn _mm512_mask_slli_epi32(src: __m512i, k: __mmask16, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_slli_epi32&expand=5309) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_slli_epi32(k: __mmask16, a: __m512i) -> __m512i { @@ -19744,7 +19744,7 @@ pub fn _mm512_maskz_slli_epi32(k: __mmask16, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_slli_epi32&expand=5305) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_slli_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -19764,7 +19764,7 @@ pub fn _mm256_mask_slli_epi32(src: __m256i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_slli_epi32&expand=5306) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_slli_epi32(k: __mmask8, a: __m256i) -> __m256i { @@ -19784,7 +19784,7 @@ pub fn _mm256_maskz_slli_epi32(k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_slli_epi32&expand=5302) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_slli_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -19804,7 +19804,7 @@ pub fn _mm_mask_slli_epi32(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_slli_epi32&expand=5303) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_slli_epi32(k: __mmask8, a: __m128i) -> __m128i { @@ -19824,7 +19824,7 @@ pub fn _mm_maskz_slli_epi32(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srli_epi32&expand=5522) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_srli_epi32(a: __m512i) -> __m512i { @@ -19843,7 +19843,7 @@ pub fn _mm512_srli_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srli_epi32&expand=5520) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_srli_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { @@ -19863,7 +19863,7 @@ pub fn _mm512_mask_srli_epi32(src: __m512i, k: __mmask16, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srli_epi32&expand=5521) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_srli_epi32(k: __mmask16, a: __m512i) -> __m512i { @@ -19883,7 +19883,7 @@ pub fn _mm512_maskz_srli_epi32(k: __mmask16, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srli_epi32&expand=5517) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_srli_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -19903,7 +19903,7 @@ pub fn _mm256_mask_srli_epi32(src: __m256i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srli_epi32&expand=5518) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_srli_epi32(k: __mmask8, a: __m256i) -> __m256i { @@ -19923,7 +19923,7 @@ pub fn _mm256_maskz_srli_epi32(k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srli_epi32&expand=5514) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_srli_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -19943,7 +19943,7 @@ pub fn _mm_mask_srli_epi32(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srli_epi32&expand=5515) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_srli_epi32(k: __mmask8, a: __m128i) -> __m128i { @@ -19963,7 +19963,7 @@ pub fn _mm_maskz_srli_epi32(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_slli_epi64&expand=5319) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))] #[rustc_legacy_const_generics(1)] pub fn _mm512_slli_epi64(a: __m512i) -> __m512i { @@ -19982,7 +19982,7 @@ pub fn _mm512_slli_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_slli_epi64&expand=5317) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_slli_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { @@ -20002,7 +20002,7 @@ pub fn _mm512_mask_slli_epi64(src: __m512i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_slli_epi64&expand=5318) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_slli_epi64(k: __mmask8, a: __m512i) -> __m512i { @@ -20022,7 +20022,7 @@ pub fn _mm512_maskz_slli_epi64(k: __mmask8, a: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_slli_epi64&expand=5314) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_slli_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -20042,7 +20042,7 @@ pub fn _mm256_mask_slli_epi64(src: __m256i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_slli_epi64&expand=5315) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_slli_epi64(k: __mmask8, a: __m256i) -> __m256i { @@ -20062,7 +20062,7 @@ pub fn _mm256_maskz_slli_epi64(k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_slli_epi64&expand=5311) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_slli_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -20082,7 +20082,7 @@ pub fn _mm_mask_slli_epi64(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_slli_epi64&expand=5312) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_slli_epi64(k: __mmask8, a: __m128i) -> __m128i { @@ -20102,7 +20102,7 @@ pub fn _mm_maskz_slli_epi64(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srli_epi64&expand=5531) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_srli_epi64(a: __m512i) -> __m512i { @@ -20121,7 +20121,7 @@ pub fn _mm512_srli_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srli_epi64&expand=5529) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_srli_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { @@ -20141,7 +20141,7 @@ pub fn _mm512_mask_srli_epi64(src: __m512i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srli_epi64&expand=5530) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_srli_epi64(k: __mmask8, a: __m512i) -> __m512i { @@ -20161,7 +20161,7 @@ pub fn _mm512_maskz_srli_epi64(k: __mmask8, a: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srli_epi64&expand=5526) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_srli_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -20181,7 +20181,7 @@ pub fn _mm256_mask_srli_epi64(src: __m256i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srli_epi64&expand=5527) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_srli_epi64(k: __mmask8, a: __m256i) -> __m256i { @@ -20201,7 +20201,7 @@ pub fn _mm256_maskz_srli_epi64(k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srli_epi64&expand=5523) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_srli_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -20221,7 +20221,7 @@ pub fn _mm_mask_srli_epi64(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srli_epi64&expand=5524) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_srli_epi64(k: __mmask8, a: __m128i) -> __m128i { @@ -20241,7 +20241,7 @@ pub fn _mm_maskz_srli_epi64(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sll_epi32&expand=5280) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld))] pub fn _mm512_sll_epi32(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpslld(a.as_i32x16(), count.as_i32x4())) } @@ -20252,7 +20252,7 @@ pub fn _mm512_sll_epi32(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sll_epi32&expand=5278) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld))] pub fn _mm512_mask_sll_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20266,7 +20266,7 @@ pub fn _mm512_mask_sll_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sll_epi32&expand=5279) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld))] pub fn _mm512_maskz_sll_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20280,7 +20280,7 @@ pub fn _mm512_maskz_sll_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sll_epi32&expand=5275) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld))] pub fn _mm256_mask_sll_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20294,7 +20294,7 @@ pub fn _mm256_mask_sll_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sll_epi32&expand=5276) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld))] pub fn _mm256_maskz_sll_epi32(k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20308,7 +20308,7 @@ pub fn _mm256_maskz_sll_epi32(k: __mmask8, a: __m256i, count: __m128i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sll_epi32&expand=5272) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld))] pub fn _mm_mask_sll_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20322,7 +20322,7 @@ pub fn _mm_mask_sll_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sll_epi32&expand=5273) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpslld))] pub fn _mm_maskz_sll_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20336,7 +20336,7 @@ pub fn _mm_maskz_sll_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srl_epi32&expand=5492) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld))] pub fn _mm512_srl_epi32(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpsrld(a.as_i32x16(), count.as_i32x4())) } @@ -20347,7 +20347,7 @@ pub fn _mm512_srl_epi32(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srl_epi32&expand=5490) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld))] pub fn _mm512_mask_srl_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20361,7 +20361,7 @@ pub fn _mm512_mask_srl_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srl_epi32&expand=5491) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld))] pub fn _mm512_maskz_srl_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20375,7 +20375,7 @@ pub fn _mm512_maskz_srl_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srl_epi32&expand=5487) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld))] pub fn _mm256_mask_srl_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20389,7 +20389,7 @@ pub fn _mm256_mask_srl_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srl_epi32&expand=5488) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld))] pub fn _mm256_maskz_srl_epi32(k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20403,7 +20403,7 @@ pub fn _mm256_maskz_srl_epi32(k: __mmask8, a: __m256i, count: __m128i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srl_epi32&expand=5484) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld))] pub fn _mm_mask_srl_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20417,7 +20417,7 @@ pub fn _mm_mask_srl_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srl_epi32&expand=5485) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrld))] pub fn _mm_maskz_srl_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20431,7 +20431,7 @@ pub fn _mm_maskz_srl_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sll_epi64&expand=5289) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq))] pub fn _mm512_sll_epi64(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpsllq(a.as_i64x8(), count.as_i64x2())) } @@ -20442,7 +20442,7 @@ pub fn _mm512_sll_epi64(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sll_epi64&expand=5287) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq))] pub fn _mm512_mask_sll_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20456,7 +20456,7 @@ pub fn _mm512_mask_sll_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sll_epi64&expand=5288) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq))] pub fn _mm512_maskz_sll_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20470,7 +20470,7 @@ pub fn _mm512_maskz_sll_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sll_epi64&expand=5284) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq))] pub fn _mm256_mask_sll_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20484,7 +20484,7 @@ pub fn _mm256_mask_sll_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sll_epi64&expand=5285) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq))] pub fn _mm256_maskz_sll_epi64(k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20498,7 +20498,7 @@ pub fn _mm256_maskz_sll_epi64(k: __mmask8, a: __m256i, count: __m128i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sll_epi64&expand=5281) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq))] pub fn _mm_mask_sll_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20512,7 +20512,7 @@ pub fn _mm_mask_sll_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sll_epi64&expand=5282) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllq))] pub fn _mm_maskz_sll_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20526,7 +20526,7 @@ pub fn _mm_maskz_sll_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srl_epi64&expand=5501) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq))] pub fn _mm512_srl_epi64(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpsrlq(a.as_i64x8(), count.as_i64x2())) } @@ -20537,7 +20537,7 @@ pub fn _mm512_srl_epi64(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srl_epi64&expand=5499) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq))] pub fn _mm512_mask_srl_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20551,7 +20551,7 @@ pub fn _mm512_mask_srl_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srl_epi64&expand=5500) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq))] pub fn _mm512_maskz_srl_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20565,7 +20565,7 @@ pub fn _mm512_maskz_srl_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srl_epi64&expand=5496) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq))] pub fn _mm256_mask_srl_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20579,7 +20579,7 @@ pub fn _mm256_mask_srl_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srl_epi64&expand=5497) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq))] pub fn _mm256_maskz_srl_epi64(k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20593,7 +20593,7 @@ pub fn _mm256_maskz_srl_epi64(k: __mmask8, a: __m256i, count: __m128i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srl_epi64&expand=5493) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq))] pub fn _mm_mask_srl_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20607,7 +20607,7 @@ pub fn _mm_mask_srl_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srl_epi64&expand=5494) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlq))] pub fn _mm_maskz_srl_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20621,7 +20621,7 @@ pub fn _mm_maskz_srl_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sra_epi32&expand=5407) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad))] pub fn _mm512_sra_epi32(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpsrad(a.as_i32x16(), count.as_i32x4())) } @@ -20632,7 +20632,7 @@ pub fn _mm512_sra_epi32(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sra_epi32&expand=5405) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad))] pub fn _mm512_mask_sra_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20646,7 +20646,7 @@ pub fn _mm512_mask_sra_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sra_epi32&expand=5406) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad))] pub fn _mm512_maskz_sra_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20660,7 +20660,7 @@ pub fn _mm512_maskz_sra_epi32(k: __mmask16, a: __m512i, count: __m128i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sra_epi32&expand=5402) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad))] pub fn _mm256_mask_sra_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20674,7 +20674,7 @@ pub fn _mm256_mask_sra_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sra_epi32&expand=5403) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad))] pub fn _mm256_maskz_sra_epi32(k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20688,7 +20688,7 @@ pub fn _mm256_maskz_sra_epi32(k: __mmask8, a: __m256i, count: __m128i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sra_epi32&expand=5399) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad))] pub fn _mm_mask_sra_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20702,7 +20702,7 @@ pub fn _mm_mask_sra_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sra_epi32&expand=5400) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad))] pub fn _mm_maskz_sra_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20716,7 +20716,7 @@ pub fn _mm_maskz_sra_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sra_epi64&expand=5416) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm512_sra_epi64(a: __m512i, count: __m128i) -> __m512i { unsafe { transmute(vpsraq(a.as_i64x8(), count.as_i64x2())) } @@ -20727,7 +20727,7 @@ pub fn _mm512_sra_epi64(a: __m512i, count: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sra_epi64&expand=5414) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm512_mask_sra_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20741,7 +20741,7 @@ pub fn _mm512_mask_sra_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sra_epi64&expand=5415) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm512_maskz_sra_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512i { unsafe { @@ -20755,7 +20755,7 @@ pub fn _mm512_maskz_sra_epi64(k: __mmask8, a: __m512i, count: __m128i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_sra_epi64&expand=5413) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm256_sra_epi64(a: __m256i, count: __m128i) -> __m256i { unsafe { transmute(vpsraq256(a.as_i64x4(), count.as_i64x2())) } @@ -20766,7 +20766,7 @@ pub fn _mm256_sra_epi64(a: __m256i, count: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sra_epi64&expand=5411) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm256_mask_sra_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20780,7 +20780,7 @@ pub fn _mm256_mask_sra_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sra_epi64&expand=5412) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm256_maskz_sra_epi64(k: __mmask8, a: __m256i, count: __m128i) -> __m256i { unsafe { @@ -20794,7 +20794,7 @@ pub fn _mm256_maskz_sra_epi64(k: __mmask8, a: __m256i, count: __m128i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sra_epi64&expand=5410) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm_sra_epi64(a: __m128i, count: __m128i) -> __m128i { unsafe { transmute(vpsraq128(a.as_i64x2(), count.as_i64x2())) } @@ -20805,7 +20805,7 @@ pub fn _mm_sra_epi64(a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sra_epi64&expand=5408) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm_mask_sra_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20819,7 +20819,7 @@ pub fn _mm_mask_sra_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sra_epi64&expand=5409) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq))] pub fn _mm_maskz_sra_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -20833,7 +20833,7 @@ pub fn _mm_maskz_sra_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srai_epi32&expand=5436) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_srai_epi32(a: __m512i) -> __m512i { @@ -20848,7 +20848,7 @@ pub fn _mm512_srai_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srai_epi32&expand=5434) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_srai_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { @@ -20864,7 +20864,7 @@ pub fn _mm512_mask_srai_epi32(src: __m512i, k: __mmask16, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srai_epi32&expand=5435) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_srai_epi32(k: __mmask16, a: __m512i) -> __m512i { @@ -20880,7 +20880,7 @@ pub fn _mm512_maskz_srai_epi32(k: __mmask16, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srai_epi32&expand=5431) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_srai_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -20895,7 +20895,7 @@ pub fn _mm256_mask_srai_epi32(src: __m256i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srai_epi32&expand=5432) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_srai_epi32(k: __mmask8, a: __m256i) -> __m256i { @@ -20910,7 +20910,7 @@ pub fn _mm256_maskz_srai_epi32(k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srai_epi32&expand=5428) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_srai_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -20925,7 +20925,7 @@ pub fn _mm_mask_srai_epi32(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srai_epi32&expand=5429) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrad, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_srai_epi32(k: __mmask8, a: __m128i) -> __m128i { @@ -20940,7 +20940,7 @@ pub fn _mm_maskz_srai_epi32(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srai_epi64&expand=5445) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_srai_epi64(a: __m512i) -> __m512i { @@ -20955,7 +20955,7 @@ pub fn _mm512_srai_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srai_epi64&expand=5443) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_srai_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { @@ -20971,7 +20971,7 @@ pub fn _mm512_mask_srai_epi64(src: __m512i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srai_epi64&expand=5444) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_srai_epi64(k: __mmask8, a: __m512i) -> __m512i { @@ -20987,7 +20987,7 @@ pub fn _mm512_maskz_srai_epi64(k: __mmask8, a: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_srai_epi64&expand=5442) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm256_srai_epi64(a: __m256i) -> __m256i { @@ -21002,7 +21002,7 @@ pub fn _mm256_srai_epi64(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srai_epi64&expand=5440) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_srai_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { @@ -21018,7 +21018,7 @@ pub fn _mm256_mask_srai_epi64(src: __m256i, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srai_epi64&expand=5441) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_srai_epi64(k: __mmask8, a: __m256i) -> __m256i { @@ -21034,7 +21034,7 @@ pub fn _mm256_maskz_srai_epi64(k: __mmask8, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srai_epi64&expand=5439) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm_srai_epi64(a: __m128i) -> __m128i { @@ -21049,7 +21049,7 @@ pub fn _mm_srai_epi64(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srai_epi64&expand=5437) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_srai_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { @@ -21065,7 +21065,7 @@ pub fn _mm_mask_srai_epi64(src: __m128i, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srai_epi64&expand=5438) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsraq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_srai_epi64(k: __mmask8, a: __m128i) -> __m128i { @@ -21081,7 +21081,7 @@ pub fn _mm_maskz_srai_epi64(k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srav_epi32&expand=5465) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravd))] pub fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsravd(a.as_i32x16(), count.as_i32x16())) } @@ -21092,7 +21092,7 @@ pub fn _mm512_srav_epi32(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srav_epi32&expand=5463) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravd))] pub fn _mm512_mask_srav_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21106,7 +21106,7 @@ pub fn _mm512_mask_srav_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srav_epi32&expand=5464) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravd))] pub fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21120,7 +21120,7 @@ pub fn _mm512_maskz_srav_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srav_epi32&expand=5460) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravd))] pub fn _mm256_mask_srav_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -21134,7 +21134,7 @@ pub fn _mm256_mask_srav_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srav_epi32&expand=5461) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravd))] pub fn _mm256_maskz_srav_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -21148,7 +21148,7 @@ pub fn _mm256_maskz_srav_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srav_epi32&expand=5457) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravd))] pub fn _mm_mask_srav_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -21162,7 +21162,7 @@ pub fn _mm_mask_srav_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srav_epi32&expand=5458) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravd))] pub fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -21176,7 +21176,7 @@ pub fn _mm_maskz_srav_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srav_epi64&expand=5474) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsravq(a.as_i64x8(), count.as_i64x8())) } @@ -21187,7 +21187,7 @@ pub fn _mm512_srav_epi64(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srav_epi64&expand=5472) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm512_mask_srav_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21201,7 +21201,7 @@ pub fn _mm512_mask_srav_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srav_epi64&expand=5473) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21215,7 +21215,7 @@ pub fn _mm512_maskz_srav_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_srav_epi64&expand=5471) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i { unsafe { transmute(vpsravq256(a.as_i64x4(), count.as_i64x4())) } @@ -21226,7 +21226,7 @@ pub fn _mm256_srav_epi64(a: __m256i, count: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srav_epi64&expand=5469) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm256_mask_srav_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -21240,7 +21240,7 @@ pub fn _mm256_mask_srav_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srav_epi64&expand=5470) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -21254,7 +21254,7 @@ pub fn _mm256_maskz_srav_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srav_epi64&expand=5468) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i { unsafe { transmute(vpsravq128(a.as_i64x2(), count.as_i64x2())) } @@ -21265,7 +21265,7 @@ pub fn _mm_srav_epi64(a: __m128i, count: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srav_epi64&expand=5466) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm_mask_srav_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -21279,7 +21279,7 @@ pub fn _mm_mask_srav_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srav_epi64&expand=5467) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsravq))] pub fn _mm_maskz_srav_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -21293,7 +21293,7 @@ pub fn _mm_maskz_srav_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rolv_epi32&expand=4703) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm512_rolv_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vprolvd(a.as_i32x16(), b.as_i32x16())) } @@ -21304,7 +21304,7 @@ pub fn _mm512_rolv_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rolv_epi32&expand=4701) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm512_mask_rolv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -21318,7 +21318,7 @@ pub fn _mm512_mask_rolv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rolv_epi32&expand=4702) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm512_maskz_rolv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -21332,7 +21332,7 @@ pub fn _mm512_maskz_rolv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rolv_epi32&expand=4700) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm256_rolv_epi32(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vprolvd256(a.as_i32x8(), b.as_i32x8())) } @@ -21343,7 +21343,7 @@ pub fn _mm256_rolv_epi32(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rolv_epi32&expand=4698) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm256_mask_rolv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -21357,7 +21357,7 @@ pub fn _mm256_mask_rolv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rolv_epi32&expand=4699) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm256_maskz_rolv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -21371,7 +21371,7 @@ pub fn _mm256_maskz_rolv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rolv_epi32&expand=4697) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm_rolv_epi32(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vprolvd128(a.as_i32x4(), b.as_i32x4())) } @@ -21382,7 +21382,7 @@ pub fn _mm_rolv_epi32(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rolv_epi32&expand=4695) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm_mask_rolv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -21396,7 +21396,7 @@ pub fn _mm_mask_rolv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rolv_epi32&expand=4696) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvd))] pub fn _mm_maskz_rolv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -21410,7 +21410,7 @@ pub fn _mm_maskz_rolv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rorv_epi32&expand=4739) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm512_rorv_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vprorvd(a.as_i32x16(), b.as_i32x16())) } @@ -21421,7 +21421,7 @@ pub fn _mm512_rorv_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rorv_epi32&expand=4737) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm512_mask_rorv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -21435,7 +21435,7 @@ pub fn _mm512_mask_rorv_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rorv_epi32&expand=4738) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm512_maskz_rorv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -21449,7 +21449,7 @@ pub fn _mm512_maskz_rorv_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rorv_epi32&expand=4736) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm256_rorv_epi32(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vprorvd256(a.as_i32x8(), b.as_i32x8())) } @@ -21460,7 +21460,7 @@ pub fn _mm256_rorv_epi32(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rorv_epi32&expand=4734) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm256_mask_rorv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -21474,7 +21474,7 @@ pub fn _mm256_mask_rorv_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rorv_epi32&expand=4735) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm256_maskz_rorv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -21488,7 +21488,7 @@ pub fn _mm256_maskz_rorv_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rorv_epi32&expand=4733) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm_rorv_epi32(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vprorvd128(a.as_i32x4(), b.as_i32x4())) } @@ -21499,7 +21499,7 @@ pub fn _mm_rorv_epi32(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rorv_epi32&expand=4731) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm_mask_rorv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -21513,7 +21513,7 @@ pub fn _mm_mask_rorv_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rorv_epi32&expand=4732) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvd))] pub fn _mm_maskz_rorv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -21527,7 +21527,7 @@ pub fn _mm_maskz_rorv_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rolv_epi64&expand=4712) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm512_rolv_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vprolvq(a.as_i64x8(), b.as_i64x8())) } @@ -21538,7 +21538,7 @@ pub fn _mm512_rolv_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rolv_epi64&expand=4710) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm512_mask_rolv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -21552,7 +21552,7 @@ pub fn _mm512_mask_rolv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rolv_epi64&expand=4711) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm512_maskz_rolv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -21566,7 +21566,7 @@ pub fn _mm512_maskz_rolv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rolv_epi64&expand=4709) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm256_rolv_epi64(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vprolvq256(a.as_i64x4(), b.as_i64x4())) } @@ -21577,7 +21577,7 @@ pub fn _mm256_rolv_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rolv_epi64&expand=4707) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm256_mask_rolv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -21591,7 +21591,7 @@ pub fn _mm256_mask_rolv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rolv_epi64&expand=4708) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm256_maskz_rolv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -21605,7 +21605,7 @@ pub fn _mm256_maskz_rolv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rolv_epi64&expand=4706) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm_rolv_epi64(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vprolvq128(a.as_i64x2(), b.as_i64x2())) } @@ -21616,7 +21616,7 @@ pub fn _mm_rolv_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rolv_epi64&expand=4704) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm_mask_rolv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -21630,7 +21630,7 @@ pub fn _mm_mask_rolv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rolv_epi64&expand=4705) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprolvq))] pub fn _mm_maskz_rolv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -21644,7 +21644,7 @@ pub fn _mm_maskz_rolv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_rorv_epi64&expand=4748) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm512_rorv_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vprorvq(a.as_i64x8(), b.as_i64x8())) } @@ -21655,7 +21655,7 @@ pub fn _mm512_rorv_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_rorv_epi64&expand=4746) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm512_mask_rorv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -21669,7 +21669,7 @@ pub fn _mm512_mask_rorv_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_rorv_epi64&expand=4747) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm512_maskz_rorv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -21683,7 +21683,7 @@ pub fn _mm512_maskz_rorv_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_rorv_epi64&expand=4745) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm256_rorv_epi64(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vprorvq256(a.as_i64x4(), b.as_i64x4())) } @@ -21694,7 +21694,7 @@ pub fn _mm256_rorv_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_rorv_epi64&expand=4743) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm256_mask_rorv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -21708,7 +21708,7 @@ pub fn _mm256_mask_rorv_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_rorv_epi64&expand=4744) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm256_maskz_rorv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -21722,7 +21722,7 @@ pub fn _mm256_maskz_rorv_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_rorv_epi64&expand=4742) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm_rorv_epi64(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vprorvq128(a.as_i64x2(), b.as_i64x2())) } @@ -21733,7 +21733,7 @@ pub fn _mm_rorv_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_rorv_epi64&expand=4740) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm_mask_rorv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -21747,7 +21747,7 @@ pub fn _mm_mask_rorv_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_rorv_epi64&expand=4741) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vprorvq))] pub fn _mm_maskz_rorv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -21761,7 +21761,7 @@ pub fn _mm_maskz_rorv_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sllv_epi32&expand=5342) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvd))] pub fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsllvd(a.as_i32x16(), count.as_i32x16())) } @@ -21772,7 +21772,7 @@ pub fn _mm512_sllv_epi32(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sllv_epi32&expand=5340) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvd))] pub fn _mm512_mask_sllv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21786,7 +21786,7 @@ pub fn _mm512_mask_sllv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sllv_epi32&expand=5341) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvd))] pub fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21800,7 +21800,7 @@ pub fn _mm512_maskz_sllv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sllv_epi32&expand=5337) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvd))] pub fn _mm256_mask_sllv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -21814,7 +21814,7 @@ pub fn _mm256_mask_sllv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sllv_epi32&expand=5338) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvd))] pub fn _mm256_maskz_sllv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -21828,7 +21828,7 @@ pub fn _mm256_maskz_sllv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sllv_epi32&expand=5334) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvd))] pub fn _mm_mask_sllv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -21842,7 +21842,7 @@ pub fn _mm_mask_sllv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sllv_epi32&expand=5335) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvd))] pub fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -21856,7 +21856,7 @@ pub fn _mm_maskz_sllv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srlv_epi32&expand=5554) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvd))] pub fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsrlvd(a.as_i32x16(), count.as_i32x16())) } @@ -21867,7 +21867,7 @@ pub fn _mm512_srlv_epi32(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srlv_epi32&expand=5552) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvd))] pub fn _mm512_mask_srlv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21881,7 +21881,7 @@ pub fn _mm512_mask_srlv_epi32(src: __m512i, k: __mmask16, a: __m512i, count: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srlv_epi32&expand=5553) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvd))] pub fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21895,7 +21895,7 @@ pub fn _mm512_maskz_srlv_epi32(k: __mmask16, a: __m512i, count: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srlv_epi32&expand=5549) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvd))] pub fn _mm256_mask_srlv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -21909,7 +21909,7 @@ pub fn _mm256_mask_srlv_epi32(src: __m256i, k: __mmask8, a: __m256i, count: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srlv_epi32&expand=5550) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvd))] pub fn _mm256_maskz_srlv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -21923,7 +21923,7 @@ pub fn _mm256_maskz_srlv_epi32(k: __mmask8, a: __m256i, count: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srlv_epi32&expand=5546) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvd))] pub fn _mm_mask_srlv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -21937,7 +21937,7 @@ pub fn _mm_mask_srlv_epi32(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srlv_epi32&expand=5547) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvd))] pub fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -21951,7 +21951,7 @@ pub fn _mm_maskz_srlv_epi32(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sllv_epi64&expand=5351) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvq))] pub fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsllvq(a.as_i64x8(), count.as_i64x8())) } @@ -21962,7 +21962,7 @@ pub fn _mm512_sllv_epi64(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sllv_epi64&expand=5349) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvq))] pub fn _mm512_mask_sllv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21976,7 +21976,7 @@ pub fn _mm512_mask_sllv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sllv_epi64&expand=5350) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvq))] pub fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -21990,7 +21990,7 @@ pub fn _mm512_maskz_sllv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sllv_epi64&expand=5346) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvq))] pub fn _mm256_mask_sllv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -22004,7 +22004,7 @@ pub fn _mm256_mask_sllv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sllv_epi64&expand=5347) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvq))] pub fn _mm256_maskz_sllv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -22018,7 +22018,7 @@ pub fn _mm256_maskz_sllv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sllv_epi64&expand=5343) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvq))] pub fn _mm_mask_sllv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -22032,7 +22032,7 @@ pub fn _mm_mask_sllv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sllv_epi64&expand=5344) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsllvq))] pub fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -22046,7 +22046,7 @@ pub fn _mm_maskz_sllv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srlv_epi64&expand=5563) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvq))] pub fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i { unsafe { transmute(vpsrlvq(a.as_i64x8(), count.as_i64x8())) } @@ -22057,7 +22057,7 @@ pub fn _mm512_srlv_epi64(a: __m512i, count: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srlv_epi64&expand=5561) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvq))] pub fn _mm512_mask_srlv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -22071,7 +22071,7 @@ pub fn _mm512_mask_srlv_epi64(src: __m512i, k: __mmask8, a: __m512i, count: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srlv_epi64&expand=5562) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvq))] pub fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m512i { unsafe { @@ -22085,7 +22085,7 @@ pub fn _mm512_maskz_srlv_epi64(k: __mmask8, a: __m512i, count: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srlv_epi64&expand=5558) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvq))] pub fn _mm256_mask_srlv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -22099,7 +22099,7 @@ pub fn _mm256_mask_srlv_epi64(src: __m256i, k: __mmask8, a: __m256i, count: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srlv_epi64&expand=5559) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvq))] pub fn _mm256_maskz_srlv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m256i { unsafe { @@ -22113,7 +22113,7 @@ pub fn _mm256_maskz_srlv_epi64(k: __mmask8, a: __m256i, count: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srlv_epi64&expand=5555) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvq))] pub fn _mm_mask_srlv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -22127,7 +22127,7 @@ pub fn _mm_mask_srlv_epi64(src: __m128i, k: __mmask8, a: __m128i, count: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srlv_epi64&expand=5556) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpsrlvq))] pub fn _mm_maskz_srlv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i { unsafe { @@ -22141,7 +22141,7 @@ pub fn _mm_maskz_srlv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permute_ps&expand=4170) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))] #[rustc_legacy_const_generics(1)] pub fn _mm512_permute_ps(a: __m512) -> __m512 { @@ -22177,7 +22177,7 @@ pub fn _mm512_permute_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permute_ps&expand=4168) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_permute_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { @@ -22193,7 +22193,7 @@ pub fn _mm512_mask_permute_ps(src: __m512, k: __mmask16, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permute_ps&expand=4169) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_permute_ps(k: __mmask16, a: __m512) -> __m512 { @@ -22209,7 +22209,7 @@ pub fn _mm512_maskz_permute_ps(k: __mmask16, a: __m512) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permute_ps&expand=4165) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_permute_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { @@ -22224,7 +22224,7 @@ pub fn _mm256_mask_permute_ps(src: __m256, k: __mmask8, a: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permute_ps&expand=4166) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_permute_ps(k: __mmask8, a: __m256) -> __m256 { @@ -22239,7 +22239,7 @@ pub fn _mm256_maskz_permute_ps(k: __mmask8, a: __m256) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permute_ps&expand=4162) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_permute_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { @@ -22254,7 +22254,7 @@ pub fn _mm_mask_permute_ps(src: __m128, k: __mmask8, a: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permute_ps&expand=4163) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 0b11_00_01_11))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_permute_ps(k: __mmask8, a: __m128) -> __m128 { @@ -22269,7 +22269,7 @@ pub fn _mm_maskz_permute_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permute_pd&expand=4161) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01_10_01))] #[rustc_legacy_const_generics(1)] pub fn _mm512_permute_pd(a: __m512d) -> __m512d { @@ -22297,7 +22297,7 @@ pub fn _mm512_permute_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permute_pd&expand=4159) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01_10_01))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_permute_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { @@ -22313,7 +22313,7 @@ pub fn _mm512_mask_permute_pd(src: __m512d, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permute_pd&expand=4160) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01_10_01))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_permute_pd(k: __mmask8, a: __m512d) -> __m512d { @@ -22329,7 +22329,7 @@ pub fn _mm512_maskz_permute_pd(k: __mmask8, a: __m512d) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permute_pd&expand=4156) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_permute_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { @@ -22345,7 +22345,7 @@ pub fn _mm256_mask_permute_pd(src: __m256d, k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permute_pd&expand=4157) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 0b11_01))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_permute_pd(k: __mmask8, a: __m256d) -> __m256d { @@ -22361,7 +22361,7 @@ pub fn _mm256_maskz_permute_pd(k: __mmask8, a: __m256d) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permute_pd&expand=4153) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, IMM2 = 0b01))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_permute_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { @@ -22377,7 +22377,7 @@ pub fn _mm_mask_permute_pd(src: __m128d, k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permute_pd&expand=4154) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, IMM2 = 0b01))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_permute_pd(k: __mmask8, a: __m128d) -> __m128d { @@ -22393,7 +22393,7 @@ pub fn _mm_maskz_permute_pd(k: __mmask8, a: __m128d) -> __m128d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex_epi64&expand=4208) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq #[rustc_legacy_const_generics(1)] pub fn _mm512_permutex_epi64(a: __m512i) -> __m512i { @@ -22421,7 +22421,7 @@ pub fn _mm512_permutex_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex_epi64&expand=4206) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_permutex_epi64( @@ -22441,7 +22441,7 @@ pub fn _mm512_mask_permutex_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex_epi64&expand=4207) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_permutex_epi64(k: __mmask8, a: __m512i) -> __m512i { @@ -22457,7 +22457,7 @@ pub fn _mm512_maskz_permutex_epi64(k: __mmask8, a: __m512i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex_epi64&expand=4205) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq #[rustc_legacy_const_generics(1)] pub fn _mm256_permutex_epi64(a: __m256i) -> __m256i { @@ -22481,7 +22481,7 @@ pub fn _mm256_permutex_epi64(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex_epi64&expand=4203) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_permutex_epi64( @@ -22501,7 +22501,7 @@ pub fn _mm256_mask_permutex_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex_epi64&expand=4204) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_permutex_epi64(k: __mmask8, a: __m256i) -> __m256i { @@ -22517,7 +22517,7 @@ pub fn _mm256_maskz_permutex_epi64(k: __mmask8, a: __m256i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex_pd&expand=4214) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd #[rustc_legacy_const_generics(1)] pub fn _mm512_permutex_pd(a: __m512d) -> __m512d { @@ -22545,7 +22545,7 @@ pub fn _mm512_permutex_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex_pd&expand=4212) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_permutex_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { @@ -22560,7 +22560,7 @@ pub fn _mm512_mask_permutex_pd(src: __m512d, k: __mmask8, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex_pd&expand=4213) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_permutex_pd(k: __mmask8, a: __m512d) -> __m512d { @@ -22575,7 +22575,7 @@ pub fn _mm512_maskz_permutex_pd(k: __mmask8, a: __m512d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex_pd&expand=4211) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd #[rustc_legacy_const_generics(1)] pub fn _mm256_permutex_pd(a: __m256d) -> __m256d { @@ -22599,7 +22599,7 @@ pub fn _mm256_permutex_pd(a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex_pd&expand=4209) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_permutex_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { @@ -22615,7 +22615,7 @@ pub fn _mm256_mask_permutex_pd(src: __m256d, k: __mmask8, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex_pd&expand=4210) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermpd #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_permutex_pd(k: __mmask8, a: __m256d) -> __m256d { @@ -22631,7 +22631,7 @@ pub fn _mm256_maskz_permutex_pd(k: __mmask8, a: __m256d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutevar_epi32&expand=4182) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermd pub fn _mm512_permutevar_epi32(idx: __m512i, a: __m512i) -> __m512i { unsafe { transmute(vpermd(a.as_i32x16(), idx.as_i32x16())) } @@ -22642,7 +22642,7 @@ pub fn _mm512_permutevar_epi32(idx: __m512i, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutevar_epi32&expand=4181) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermd))] pub fn _mm512_mask_permutevar_epi32( src: __m512i, @@ -22661,7 +22661,7 @@ pub fn _mm512_mask_permutevar_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutevar_ps&expand=4200) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilps))] pub fn _mm512_permutevar_ps(a: __m512, b: __m512i) -> __m512 { unsafe { transmute(vpermilps(a.as_f32x16(), b.as_i32x16())) } @@ -22672,7 +22672,7 @@ pub fn _mm512_permutevar_ps(a: __m512, b: __m512i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutevar_ps&expand=4198) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilps))] pub fn _mm512_mask_permutevar_ps(src: __m512, k: __mmask16, a: __m512, b: __m512i) -> __m512 { unsafe { @@ -22686,7 +22686,7 @@ pub fn _mm512_mask_permutevar_ps(src: __m512, k: __mmask16, a: __m512, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutevar_ps&expand=4199) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilps))] pub fn _mm512_maskz_permutevar_ps(k: __mmask16, a: __m512, b: __m512i) -> __m512 { unsafe { @@ -22700,7 +22700,7 @@ pub fn _mm512_maskz_permutevar_ps(k: __mmask16, a: __m512, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm256_mask_permutevar_ps&expand=4195) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilps))] pub fn _mm256_mask_permutevar_ps(src: __m256, k: __mmask8, a: __m256, b: __m256i) -> __m256 { unsafe { @@ -22714,7 +22714,7 @@ pub fn _mm256_mask_permutevar_ps(src: __m256, k: __mmask8, a: __m256, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutevar_ps&expand=4196) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilps))] pub fn _mm256_maskz_permutevar_ps(k: __mmask8, a: __m256, b: __m256i) -> __m256 { unsafe { @@ -22728,7 +22728,7 @@ pub fn _mm256_maskz_permutevar_ps(k: __mmask8, a: __m256, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutevar_ps&expand=4192) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilps))] pub fn _mm_mask_permutevar_ps(src: __m128, k: __mmask8, a: __m128, b: __m128i) -> __m128 { unsafe { @@ -22742,7 +22742,7 @@ pub fn _mm_mask_permutevar_ps(src: __m128, k: __mmask8, a: __m128, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutevar_ps&expand=4193) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilps))] pub fn _mm_maskz_permutevar_ps(k: __mmask8, a: __m128, b: __m128i) -> __m128 { unsafe { @@ -22756,7 +22756,7 @@ pub fn _mm_maskz_permutevar_ps(k: __mmask8, a: __m128, b: __m128i) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutevar_pd&expand=4191) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilpd))] pub fn _mm512_permutevar_pd(a: __m512d, b: __m512i) -> __m512d { unsafe { transmute(vpermilpd(a.as_f64x8(), b.as_i64x8())) } @@ -22767,7 +22767,7 @@ pub fn _mm512_permutevar_pd(a: __m512d, b: __m512i) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutevar_pd&expand=4189) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilpd))] pub fn _mm512_mask_permutevar_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512i) -> __m512d { unsafe { @@ -22781,7 +22781,7 @@ pub fn _mm512_mask_permutevar_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutevar_pd&expand=4190) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilpd))] pub fn _mm512_maskz_permutevar_pd(k: __mmask8, a: __m512d, b: __m512i) -> __m512d { unsafe { @@ -22795,7 +22795,7 @@ pub fn _mm512_maskz_permutevar_pd(k: __mmask8, a: __m512d, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutevar_pd&expand=4186) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilpd))] pub fn _mm256_mask_permutevar_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256i) -> __m256d { unsafe { @@ -22809,7 +22809,7 @@ pub fn _mm256_mask_permutevar_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutevar_pd&expand=4187) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilpd))] pub fn _mm256_maskz_permutevar_pd(k: __mmask8, a: __m256d, b: __m256i) -> __m256d { unsafe { @@ -22823,7 +22823,7 @@ pub fn _mm256_maskz_permutevar_pd(k: __mmask8, a: __m256d, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutevar_pd&expand=4183) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilpd))] pub fn _mm_mask_permutevar_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128i) -> __m128d { unsafe { @@ -22837,7 +22837,7 @@ pub fn _mm_mask_permutevar_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutevar_pd&expand=4184) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermilpd))] pub fn _mm_maskz_permutevar_pd(k: __mmask8, a: __m128d, b: __m128i) -> __m128d { unsafe { @@ -22851,7 +22851,7 @@ pub fn _mm_maskz_permutevar_pd(k: __mmask8, a: __m128d, b: __m128i) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutexvar_epi32&expand=4301) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermd pub fn _mm512_permutexvar_epi32(idx: __m512i, a: __m512i) -> __m512i { unsafe { transmute(vpermd(a.as_i32x16(), idx.as_i32x16())) } @@ -22862,7 +22862,7 @@ pub fn _mm512_permutexvar_epi32(idx: __m512i, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutexvar_epi32&expand=4299) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermd))] pub fn _mm512_mask_permutexvar_epi32( src: __m512i, @@ -22881,7 +22881,7 @@ pub fn _mm512_mask_permutexvar_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutexvar_epi32&expand=4300) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermd))] pub fn _mm512_maskz_permutexvar_epi32(k: __mmask16, idx: __m512i, a: __m512i) -> __m512i { unsafe { @@ -22895,7 +22895,7 @@ pub fn _mm512_maskz_permutexvar_epi32(k: __mmask16, idx: __m512i, a: __m512i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutexvar_epi32&expand=4298) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermd pub fn _mm256_permutexvar_epi32(idx: __m256i, a: __m256i) -> __m256i { _mm256_permutevar8x32_epi32(a, idx) // llvm use llvm.x86.avx2.permd @@ -22906,7 +22906,7 @@ pub fn _mm256_permutexvar_epi32(idx: __m256i, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutexvar_epi32&expand=4296) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermd))] pub fn _mm256_mask_permutexvar_epi32( src: __m256i, @@ -22925,7 +22925,7 @@ pub fn _mm256_mask_permutexvar_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutexvar_epi32&expand=4297) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermd))] pub fn _mm256_maskz_permutexvar_epi32(k: __mmask8, idx: __m256i, a: __m256i) -> __m256i { unsafe { @@ -22939,7 +22939,7 @@ pub fn _mm256_maskz_permutexvar_epi32(k: __mmask8, idx: __m256i, a: __m256i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutexvar_epi64&expand=4307) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermq pub fn _mm512_permutexvar_epi64(idx: __m512i, a: __m512i) -> __m512i { unsafe { transmute(vpermq(a.as_i64x8(), idx.as_i64x8())) } @@ -22950,7 +22950,7 @@ pub fn _mm512_permutexvar_epi64(idx: __m512i, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutexvar_epi64&expand=4305) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermq))] pub fn _mm512_mask_permutexvar_epi64( src: __m512i, @@ -22969,7 +22969,7 @@ pub fn _mm512_mask_permutexvar_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutexvar_epi64&expand=4306) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermq))] pub fn _mm512_maskz_permutexvar_epi64(k: __mmask8, idx: __m512i, a: __m512i) -> __m512i { unsafe { @@ -22983,7 +22983,7 @@ pub fn _mm512_maskz_permutexvar_epi64(k: __mmask8, idx: __m512i, a: __m512i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutexvar_epi64&expand=4304) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermq pub fn _mm256_permutexvar_epi64(idx: __m256i, a: __m256i) -> __m256i { unsafe { transmute(vpermq256(a.as_i64x4(), idx.as_i64x4())) } @@ -22994,7 +22994,7 @@ pub fn _mm256_permutexvar_epi64(idx: __m256i, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutexvar_epi64&expand=4302) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermq))] pub fn _mm256_mask_permutexvar_epi64( src: __m256i, @@ -23013,7 +23013,7 @@ pub fn _mm256_mask_permutexvar_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutexvar_epi64&expand=4303) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermq))] pub fn _mm256_maskz_permutexvar_epi64(k: __mmask8, idx: __m256i, a: __m256i) -> __m256i { unsafe { @@ -23027,7 +23027,7 @@ pub fn _mm256_maskz_permutexvar_epi64(k: __mmask8, idx: __m256i, a: __m256i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutexvar_ps&expand=4200) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermps))] pub fn _mm512_permutexvar_ps(idx: __m512i, a: __m512) -> __m512 { unsafe { transmute(vpermps(a.as_f32x16(), idx.as_i32x16())) } @@ -23038,7 +23038,7 @@ pub fn _mm512_permutexvar_ps(idx: __m512i, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutexvar_ps&expand=4326) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermps))] pub fn _mm512_mask_permutexvar_ps(src: __m512, k: __mmask16, idx: __m512i, a: __m512) -> __m512 { unsafe { @@ -23052,7 +23052,7 @@ pub fn _mm512_mask_permutexvar_ps(src: __m512, k: __mmask16, idx: __m512i, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutexvar_ps&expand=4327) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermps))] pub fn _mm512_maskz_permutexvar_ps(k: __mmask16, idx: __m512i, a: __m512) -> __m512 { unsafe { @@ -23066,7 +23066,7 @@ pub fn _mm512_maskz_permutexvar_ps(k: __mmask16, idx: __m512i, a: __m512) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutexvar_ps&expand=4325) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermps))] pub fn _mm256_permutexvar_ps(idx: __m256i, a: __m256) -> __m256 { _mm256_permutevar8x32_ps(a, idx) //llvm.x86.avx2.permps @@ -23077,7 +23077,7 @@ pub fn _mm256_permutexvar_ps(idx: __m256i, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutexvar_ps&expand=4323) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermps))] pub fn _mm256_mask_permutexvar_ps(src: __m256, k: __mmask8, idx: __m256i, a: __m256) -> __m256 { unsafe { @@ -23091,7 +23091,7 @@ pub fn _mm256_mask_permutexvar_ps(src: __m256, k: __mmask8, idx: __m256i, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutexvar_ps&expand=4324) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermps))] pub fn _mm256_maskz_permutexvar_ps(k: __mmask8, idx: __m256i, a: __m256) -> __m256 { unsafe { @@ -23105,7 +23105,7 @@ pub fn _mm256_maskz_permutexvar_ps(k: __mmask8, idx: __m256i, a: __m256) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutexvar_pd&expand=4322) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermpd))] pub fn _mm512_permutexvar_pd(idx: __m512i, a: __m512d) -> __m512d { unsafe { transmute(vpermpd(a.as_f64x8(), idx.as_i64x8())) } @@ -23116,7 +23116,7 @@ pub fn _mm512_permutexvar_pd(idx: __m512i, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutexvar_pd&expand=4320) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermpd))] pub fn _mm512_mask_permutexvar_pd(src: __m512d, k: __mmask8, idx: __m512i, a: __m512d) -> __m512d { unsafe { @@ -23130,7 +23130,7 @@ pub fn _mm512_mask_permutexvar_pd(src: __m512d, k: __mmask8, idx: __m512i, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutexvar_pd&expand=4321) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermpd))] pub fn _mm512_maskz_permutexvar_pd(k: __mmask8, idx: __m512i, a: __m512d) -> __m512d { unsafe { @@ -23144,7 +23144,7 @@ pub fn _mm512_maskz_permutexvar_pd(k: __mmask8, idx: __m512i, a: __m512d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutexvar_pd&expand=4319) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermpd))] pub fn _mm256_permutexvar_pd(idx: __m256i, a: __m256d) -> __m256d { unsafe { transmute(vpermpd256(a.as_f64x4(), idx.as_i64x4())) } @@ -23155,7 +23155,7 @@ pub fn _mm256_permutexvar_pd(idx: __m256i, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutexvar_pd&expand=4317) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermpd))] pub fn _mm256_mask_permutexvar_pd(src: __m256d, k: __mmask8, idx: __m256i, a: __m256d) -> __m256d { unsafe { @@ -23169,7 +23169,7 @@ pub fn _mm256_mask_permutexvar_pd(src: __m256d, k: __mmask8, idx: __m256i, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutexvar_pd&expand=4318) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermpd))] pub fn _mm256_maskz_permutexvar_pd(k: __mmask8, idx: __m256i, a: __m256d) -> __m256d { unsafe { @@ -23183,7 +23183,7 @@ pub fn _mm256_maskz_permutexvar_pd(k: __mmask8, idx: __m256i, a: __m256d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex2var_epi32&expand=4238) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2d or vpermt2d pub fn _mm512_permutex2var_epi32(a: __m512i, idx: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpermi2d(a.as_i32x16(), idx.as_i32x16(), b.as_i32x16())) } @@ -23194,7 +23194,7 @@ pub fn _mm512_permutex2var_epi32(a: __m512i, idx: __m512i, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex2var_epi32&expand=4235) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2d))] pub fn _mm512_mask_permutex2var_epi32( a: __m512i, @@ -23213,7 +23213,7 @@ pub fn _mm512_mask_permutex2var_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex2var_epi32&expand=4237) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2d or vpermt2d pub fn _mm512_maskz_permutex2var_epi32( k: __mmask16, @@ -23232,7 +23232,7 @@ pub fn _mm512_maskz_permutex2var_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask2_permutex2var_epi32&expand=4236) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2d))] pub fn _mm512_mask2_permutex2var_epi32( a: __m512i, @@ -23251,7 +23251,7 @@ pub fn _mm512_mask2_permutex2var_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex2var_epi32&expand=4234) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2d or vpermt2d pub fn _mm256_permutex2var_epi32(a: __m256i, idx: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpermi2d256(a.as_i32x8(), idx.as_i32x8(), b.as_i32x8())) } @@ -23262,7 +23262,7 @@ pub fn _mm256_permutex2var_epi32(a: __m256i, idx: __m256i, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex2var_epi32&expand=4231) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2d))] pub fn _mm256_mask_permutex2var_epi32( a: __m256i, @@ -23281,7 +23281,7 @@ pub fn _mm256_mask_permutex2var_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex2var_epi32&expand=4233) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2d or vpermt2d pub fn _mm256_maskz_permutex2var_epi32( k: __mmask8, @@ -23300,7 +23300,7 @@ pub fn _mm256_maskz_permutex2var_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask2_permutex2var_epi32&expand=4232) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2d))] pub fn _mm256_mask2_permutex2var_epi32( a: __m256i, @@ -23319,7 +23319,7 @@ pub fn _mm256_mask2_permutex2var_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutex2var_epi32&expand=4230) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2d or vpermt2d pub fn _mm_permutex2var_epi32(a: __m128i, idx: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpermi2d128(a.as_i32x4(), idx.as_i32x4(), b.as_i32x4())) } @@ -23330,7 +23330,7 @@ pub fn _mm_permutex2var_epi32(a: __m128i, idx: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutex2var_epi32&expand=4227) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2d))] pub fn _mm_mask_permutex2var_epi32(a: __m128i, k: __mmask8, idx: __m128i, b: __m128i) -> __m128i { unsafe { @@ -23344,7 +23344,7 @@ pub fn _mm_mask_permutex2var_epi32(a: __m128i, k: __mmask8, idx: __m128i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutex2var_epi32&expand=4229) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2d or vpermt2d pub fn _mm_maskz_permutex2var_epi32(k: __mmask8, a: __m128i, idx: __m128i, b: __m128i) -> __m128i { unsafe { @@ -23358,7 +23358,7 @@ pub fn _mm_maskz_permutex2var_epi32(k: __mmask8, a: __m128i, idx: __m128i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask2_permutex2var_epi32&expand=4228) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2d))] pub fn _mm_mask2_permutex2var_epi32(a: __m128i, idx: __m128i, k: __mmask8, b: __m128i) -> __m128i { unsafe { @@ -23372,7 +23372,7 @@ pub fn _mm_mask2_permutex2var_epi32(a: __m128i, idx: __m128i, k: __mmask8, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex2var_epi64&expand=4250) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2q or vpermt2q pub fn _mm512_permutex2var_epi64(a: __m512i, idx: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpermi2q(a.as_i64x8(), idx.as_i64x8(), b.as_i64x8())) } @@ -23383,7 +23383,7 @@ pub fn _mm512_permutex2var_epi64(a: __m512i, idx: __m512i, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex2var_epi64&expand=4247) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2q))] pub fn _mm512_mask_permutex2var_epi64( a: __m512i, @@ -23402,7 +23402,7 @@ pub fn _mm512_mask_permutex2var_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex2var_epi64&expand=4249) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2q or vpermt2q pub fn _mm512_maskz_permutex2var_epi64( k: __mmask8, @@ -23421,7 +23421,7 @@ pub fn _mm512_maskz_permutex2var_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask2_permutex2var_epi64&expand=4248) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2q))] pub fn _mm512_mask2_permutex2var_epi64( a: __m512i, @@ -23440,7 +23440,7 @@ pub fn _mm512_mask2_permutex2var_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex2var_epi64&expand=4246) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2q or vpermt2q pub fn _mm256_permutex2var_epi64(a: __m256i, idx: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpermi2q256(a.as_i64x4(), idx.as_i64x4(), b.as_i64x4())) } @@ -23451,7 +23451,7 @@ pub fn _mm256_permutex2var_epi64(a: __m256i, idx: __m256i, b: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex2var_epi64&expand=4243) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2q))] pub fn _mm256_mask_permutex2var_epi64( a: __m256i, @@ -23470,7 +23470,7 @@ pub fn _mm256_mask_permutex2var_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex2var_epi64&expand=4245) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2q or vpermt2q pub fn _mm256_maskz_permutex2var_epi64( k: __mmask8, @@ -23489,7 +23489,7 @@ pub fn _mm256_maskz_permutex2var_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask2_permutex2var_epi64&expand=4244) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2q))] pub fn _mm256_mask2_permutex2var_epi64( a: __m256i, @@ -23508,7 +23508,7 @@ pub fn _mm256_mask2_permutex2var_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutex2var_epi64&expand=4242) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2q or vpermt2q pub fn _mm_permutex2var_epi64(a: __m128i, idx: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpermi2q128(a.as_i64x2(), idx.as_i64x2(), b.as_i64x2())) } @@ -23519,7 +23519,7 @@ pub fn _mm_permutex2var_epi64(a: __m128i, idx: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutex2var_epi64&expand=4239) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2q))] pub fn _mm_mask_permutex2var_epi64(a: __m128i, k: __mmask8, idx: __m128i, b: __m128i) -> __m128i { unsafe { @@ -23533,7 +23533,7 @@ pub fn _mm_mask_permutex2var_epi64(a: __m128i, k: __mmask8, idx: __m128i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutex2var_epi64&expand=4241) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2q or vpermt2q pub fn _mm_maskz_permutex2var_epi64(k: __mmask8, a: __m128i, idx: __m128i, b: __m128i) -> __m128i { unsafe { @@ -23547,7 +23547,7 @@ pub fn _mm_maskz_permutex2var_epi64(k: __mmask8, a: __m128i, idx: __m128i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask2_permutex2var_epi64&expand=4240) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2q))] pub fn _mm_mask2_permutex2var_epi64(a: __m128i, idx: __m128i, k: __mmask8, b: __m128i) -> __m128i { unsafe { @@ -23561,7 +23561,7 @@ pub fn _mm_mask2_permutex2var_epi64(a: __m128i, idx: __m128i, k: __mmask8, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex2var_ps&expand=4286) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2ps or vpermt2ps pub fn _mm512_permutex2var_ps(a: __m512, idx: __m512i, b: __m512) -> __m512 { unsafe { transmute(vpermi2ps(a.as_f32x16(), idx.as_i32x16(), b.as_f32x16())) } @@ -23572,7 +23572,7 @@ pub fn _mm512_permutex2var_ps(a: __m512, idx: __m512i, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex2var_ps&expand=4283) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2ps))] pub fn _mm512_mask_permutex2var_ps(a: __m512, k: __mmask16, idx: __m512i, b: __m512) -> __m512 { unsafe { @@ -23586,7 +23586,7 @@ pub fn _mm512_mask_permutex2var_ps(a: __m512, k: __mmask16, idx: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex2var_ps&expand=4285) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2ps or vpermt2ps pub fn _mm512_maskz_permutex2var_ps(k: __mmask16, a: __m512, idx: __m512i, b: __m512) -> __m512 { unsafe { @@ -23600,7 +23600,7 @@ pub fn _mm512_maskz_permutex2var_ps(k: __mmask16, a: __m512, idx: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask2_permutex2var_ps&expand=4284) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2ps, but it shows vpermt2ps pub fn _mm512_mask2_permutex2var_ps(a: __m512, idx: __m512i, k: __mmask16, b: __m512) -> __m512 { unsafe { @@ -23615,7 +23615,7 @@ pub fn _mm512_mask2_permutex2var_ps(a: __m512, idx: __m512i, k: __mmask16, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex2var_ps&expand=4282) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2ps or vpermt2ps pub fn _mm256_permutex2var_ps(a: __m256, idx: __m256i, b: __m256) -> __m256 { unsafe { transmute(vpermi2ps256(a.as_f32x8(), idx.as_i32x8(), b.as_f32x8())) } @@ -23626,7 +23626,7 @@ pub fn _mm256_permutex2var_ps(a: __m256, idx: __m256i, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex2var_ps&expand=4279) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2ps))] pub fn _mm256_mask_permutex2var_ps(a: __m256, k: __mmask8, idx: __m256i, b: __m256) -> __m256 { unsafe { @@ -23640,7 +23640,7 @@ pub fn _mm256_mask_permutex2var_ps(a: __m256, k: __mmask8, idx: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex2var_ps&expand=4281) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2ps or vpermt2ps pub fn _mm256_maskz_permutex2var_ps(k: __mmask8, a: __m256, idx: __m256i, b: __m256) -> __m256 { unsafe { @@ -23654,7 +23654,7 @@ pub fn _mm256_maskz_permutex2var_ps(k: __mmask8, a: __m256, idx: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask2_permutex2var_ps&expand=4280) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2ps, but it shows vpermt2ps pub fn _mm256_mask2_permutex2var_ps(a: __m256, idx: __m256i, k: __mmask8, b: __m256) -> __m256 { unsafe { @@ -23669,7 +23669,7 @@ pub fn _mm256_mask2_permutex2var_ps(a: __m256, idx: __m256i, k: __mmask8, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutex2var_ps&expand=4278) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2ps or vpermt2ps pub fn _mm_permutex2var_ps(a: __m128, idx: __m128i, b: __m128) -> __m128 { unsafe { transmute(vpermi2ps128(a.as_f32x4(), idx.as_i32x4(), b.as_f32x4())) } @@ -23680,7 +23680,7 @@ pub fn _mm_permutex2var_ps(a: __m128, idx: __m128i, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutex2var_ps&expand=4275) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2ps))] pub fn _mm_mask_permutex2var_ps(a: __m128, k: __mmask8, idx: __m128i, b: __m128) -> __m128 { unsafe { @@ -23694,7 +23694,7 @@ pub fn _mm_mask_permutex2var_ps(a: __m128, k: __mmask8, idx: __m128i, b: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutex2var_ps&expand=4277) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2ps or vpermt2ps pub fn _mm_maskz_permutex2var_ps(k: __mmask8, a: __m128, idx: __m128i, b: __m128) -> __m128 { unsafe { @@ -23708,7 +23708,7 @@ pub fn _mm_maskz_permutex2var_ps(k: __mmask8, a: __m128, idx: __m128i, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask2_permutex2var_ps&expand=4276) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2ps, but it shows vpermt2ps pub fn _mm_mask2_permutex2var_ps(a: __m128, idx: __m128i, k: __mmask8, b: __m128) -> __m128 { unsafe { @@ -23723,7 +23723,7 @@ pub fn _mm_mask2_permutex2var_ps(a: __m128, idx: __m128i, k: __mmask8, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex2var_pd&expand=4274) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2pd or vpermt2pd pub fn _mm512_permutex2var_pd(a: __m512d, idx: __m512i, b: __m512d) -> __m512d { unsafe { transmute(vpermi2pd(a.as_f64x8(), idx.as_i64x8(), b.as_f64x8())) } @@ -23734,7 +23734,7 @@ pub fn _mm512_permutex2var_pd(a: __m512d, idx: __m512i, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex2var_pd&expand=4271) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2pd))] pub fn _mm512_mask_permutex2var_pd(a: __m512d, k: __mmask8, idx: __m512i, b: __m512d) -> __m512d { unsafe { @@ -23748,7 +23748,7 @@ pub fn _mm512_mask_permutex2var_pd(a: __m512d, k: __mmask8, idx: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex2var_pd&expand=4273) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2pd or vpermt2pd pub fn _mm512_maskz_permutex2var_pd(k: __mmask8, a: __m512d, idx: __m512i, b: __m512d) -> __m512d { unsafe { @@ -23762,7 +23762,7 @@ pub fn _mm512_maskz_permutex2var_pd(k: __mmask8, a: __m512d, idx: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask2_permutex2var_pd&expand=4272) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2pd, but it shows vpermt2pd pub fn _mm512_mask2_permutex2var_pd(a: __m512d, idx: __m512i, k: __mmask8, b: __m512d) -> __m512d { unsafe { @@ -23777,7 +23777,7 @@ pub fn _mm512_mask2_permutex2var_pd(a: __m512d, idx: __m512i, k: __mmask8, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex2var_pd&expand=4270) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2pd or vpermt2pd pub fn _mm256_permutex2var_pd(a: __m256d, idx: __m256i, b: __m256d) -> __m256d { unsafe { transmute(vpermi2pd256(a.as_f64x4(), idx.as_i64x4(), b.as_f64x4())) } @@ -23788,7 +23788,7 @@ pub fn _mm256_permutex2var_pd(a: __m256d, idx: __m256i, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex2var_pd&expand=4267) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2pd))] pub fn _mm256_mask_permutex2var_pd(a: __m256d, k: __mmask8, idx: __m256i, b: __m256d) -> __m256d { unsafe { @@ -23802,7 +23802,7 @@ pub fn _mm256_mask_permutex2var_pd(a: __m256d, k: __mmask8, idx: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex2var_pd&expand=4269) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2pd or vpermt2pd pub fn _mm256_maskz_permutex2var_pd(k: __mmask8, a: __m256d, idx: __m256i, b: __m256d) -> __m256d { unsafe { @@ -23816,7 +23816,7 @@ pub fn _mm256_maskz_permutex2var_pd(k: __mmask8, a: __m256d, idx: __m256i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask2_permutex2var_pd&expand=4268) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2pd, but it shows vpermt2pd pub fn _mm256_mask2_permutex2var_pd(a: __m256d, idx: __m256i, k: __mmask8, b: __m256d) -> __m256d { unsafe { @@ -23831,7 +23831,7 @@ pub fn _mm256_mask2_permutex2var_pd(a: __m256d, idx: __m256i, k: __mmask8, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutex2var_pd&expand=4266) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2pd or vpermt2pd pub fn _mm_permutex2var_pd(a: __m128d, idx: __m128i, b: __m128d) -> __m128d { unsafe { transmute(vpermi2pd128(a.as_f64x2(), idx.as_i64x2(), b.as_f64x2())) } @@ -23842,7 +23842,7 @@ pub fn _mm_permutex2var_pd(a: __m128d, idx: __m128i, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutex2var_pd&expand=4263) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2pd))] pub fn _mm_mask_permutex2var_pd(a: __m128d, k: __mmask8, idx: __m128i, b: __m128d) -> __m128d { unsafe { @@ -23856,7 +23856,7 @@ pub fn _mm_mask_permutex2var_pd(a: __m128d, k: __mmask8, idx: __m128i, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutex2var_pd&expand=4265) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //vpermi2pd or vpermt2pd pub fn _mm_maskz_permutex2var_pd(k: __mmask8, a: __m128d, idx: __m128i, b: __m128d) -> __m128d { unsafe { @@ -23870,7 +23870,7 @@ pub fn _mm_maskz_permutex2var_pd(k: __mmask8, a: __m128d, idx: __m128i, b: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask2_permutex2var_pd&expand=4264) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2pd, but it shows vpermt2pd pub fn _mm_mask2_permutex2var_pd(a: __m128d, idx: __m128i, k: __mmask8, b: __m128d) -> __m128d { unsafe { @@ -23885,7 +23885,7 @@ pub fn _mm_mask2_permutex2var_pd(a: __m128d, idx: __m128i, k: __mmask8, b: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_epi32&expand=5150) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 9))] //should be vpshufd #[rustc_legacy_const_generics(1)] pub fn _mm512_shuffle_epi32(a: __m512i) -> __m512i { @@ -23922,7 +23922,7 @@ pub fn _mm512_shuffle_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_epi32&expand=5148) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_shuffle_epi32( @@ -23942,7 +23942,7 @@ pub fn _mm512_mask_shuffle_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_epi32&expand=5149) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_shuffle_epi32(k: __mmask16, a: __m512i) -> __m512i { @@ -23958,7 +23958,7 @@ pub fn _mm512_maskz_shuffle_epi32(k: __mmask16, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_epi32&expand=5145) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_shuffle_epi32( @@ -23978,7 +23978,7 @@ pub fn _mm256_mask_shuffle_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_epi32&expand=5146) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_shuffle_epi32(k: __mmask8, a: __m256i) -> __m256i { @@ -23994,7 +23994,7 @@ pub fn _mm256_maskz_shuffle_epi32(k: __mmask8, a: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shuffle_epi32&expand=5142) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))] #[rustc_legacy_const_generics(3)] pub fn _mm_mask_shuffle_epi32( @@ -24014,7 +24014,7 @@ pub fn _mm_mask_shuffle_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shuffle_epi32&expand=5143) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshufd, MASK = 9))] #[rustc_legacy_const_generics(2)] pub fn _mm_maskz_shuffle_epi32(k: __mmask8, a: __m128i) -> __m128i { @@ -24030,7 +24030,7 @@ pub fn _mm_maskz_shuffle_epi32(k: __mmask8, a: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_ps&expand=5203) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 3))] #[rustc_legacy_const_generics(2)] pub fn _mm512_shuffle_ps(a: __m512, b: __m512) -> __m512 { @@ -24066,7 +24066,7 @@ pub fn _mm512_shuffle_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_ps&expand=5201) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 3))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shuffle_ps( @@ -24087,7 +24087,7 @@ pub fn _mm512_mask_shuffle_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_ps&expand=5202) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 3))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shuffle_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { @@ -24103,7 +24103,7 @@ pub fn _mm512_maskz_shuffle_ps(k: __mmask16, a: __m512, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_ps&expand=5198) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 3))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shuffle_ps( @@ -24124,7 +24124,7 @@ pub fn _mm256_mask_shuffle_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_ps&expand=5199) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 3))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shuffle_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { @@ -24140,7 +24140,7 @@ pub fn _mm256_maskz_shuffle_ps(k: __mmask8, a: __m256, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shuffle_ps&expand=5195) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 3))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_shuffle_ps( @@ -24161,7 +24161,7 @@ pub fn _mm_mask_shuffle_ps( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shuffle_ps&expand=5196) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufps, MASK = 3))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_shuffle_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -24177,7 +24177,7 @@ pub fn _mm_maskz_shuffle_ps(k: __mmask8, a: __m128, b: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_pd&expand=5192) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))] #[rustc_legacy_const_generics(2)] pub fn _mm512_shuffle_pd(a: __m512d, b: __m512d) -> __m512d { @@ -24205,7 +24205,7 @@ pub fn _mm512_shuffle_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_pd&expand=5190) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shuffle_pd( @@ -24226,7 +24226,7 @@ pub fn _mm512_mask_shuffle_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_pd&expand=5191) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shuffle_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { @@ -24242,7 +24242,7 @@ pub fn _mm512_maskz_shuffle_pd(k: __mmask8, a: __m512d, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_pd&expand=5187) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shuffle_pd( @@ -24263,7 +24263,7 @@ pub fn _mm256_mask_shuffle_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_pd&expand=5188) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 3))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shuffle_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { @@ -24279,7 +24279,7 @@ pub fn _mm256_maskz_shuffle_pd(k: __mmask8, a: __m256d, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shuffle_pd&expand=5184) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_shuffle_pd( @@ -24300,7 +24300,7 @@ pub fn _mm_mask_shuffle_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shuffle_pd&expand=5185) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufpd, MASK = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_shuffle_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -24316,7 +24316,7 @@ pub fn _mm_maskz_shuffle_pd(k: __mmask8, a: __m128d, b: __m128d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_i32x4&expand=5177) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b10_01_01_01))] //should be vshufi32x4 #[rustc_legacy_const_generics(2)] pub fn _mm512_shuffle_i32x4(a: __m512i, b: __m512i) -> __m512i { @@ -24355,7 +24355,7 @@ pub fn _mm512_shuffle_i32x4(a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_i32x4&expand=5175) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi32x4, MASK = 0b10_11_01_01))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shuffle_i32x4( @@ -24376,7 +24376,7 @@ pub fn _mm512_mask_shuffle_i32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_i32x4&expand=5176) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi32x4, MASK = 0b10_11_01_01))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shuffle_i32x4( @@ -24396,7 +24396,7 @@ pub fn _mm512_maskz_shuffle_i32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shuffle_i32x4&expand=5174) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b11))] //should be vshufi32x4 #[rustc_legacy_const_generics(2)] pub fn _mm256_shuffle_i32x4(a: __m256i, b: __m256i) -> __m256i { @@ -24427,7 +24427,7 @@ pub fn _mm256_shuffle_i32x4(a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_i32x4&expand=5172) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi32x4, MASK = 0b11))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shuffle_i32x4( @@ -24448,7 +24448,7 @@ pub fn _mm256_mask_shuffle_i32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_i32x4&expand=5173) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi32x4, MASK = 0b11))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shuffle_i32x4(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { @@ -24464,7 +24464,7 @@ pub fn _mm256_maskz_shuffle_i32x4(k: __mmask8, a: __m256i, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_i64x2&expand=5183) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b10_11_11_11))] #[rustc_legacy_const_generics(2)] pub fn _mm512_shuffle_i64x2(a: __m512i, b: __m512i) -> __m512i { @@ -24495,7 +24495,7 @@ pub fn _mm512_shuffle_i64x2(a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_i64x2&expand=5181) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b10_11_11_11))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shuffle_i64x2( @@ -24516,7 +24516,7 @@ pub fn _mm512_mask_shuffle_i64x2( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_i64x2&expand=5182) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b10_11_11_11))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shuffle_i64x2(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { @@ -24532,7 +24532,7 @@ pub fn _mm512_maskz_shuffle_i64x2(k: __mmask8, a: __m512i, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shuffle_i64x2&expand=5180) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b01))] //should be vshufi64x2 #[rustc_legacy_const_generics(2)] pub fn _mm256_shuffle_i64x2(a: __m256i, b: __m256i) -> __m256i { @@ -24559,7 +24559,7 @@ pub fn _mm256_shuffle_i64x2(a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_i64x2&expand=5178) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b11))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shuffle_i64x2( @@ -24580,7 +24580,7 @@ pub fn _mm256_mask_shuffle_i64x2( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_i64x2&expand=5179) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshufi64x2, MASK = 0b11))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shuffle_i64x2(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { @@ -24596,7 +24596,7 @@ pub fn _mm256_maskz_shuffle_i64x2(k: __mmask8, a: __m256i, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_f32x4&expand=5165) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b1011))] //should be vshuff32x4, but generate vshuff64x2 #[rustc_legacy_const_generics(2)] pub fn _mm512_shuffle_f32x4(a: __m512, b: __m512) -> __m512 { @@ -24635,7 +24635,7 @@ pub fn _mm512_shuffle_f32x4(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_f32x4&expand=5163) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff32x4, MASK = 0b1011))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shuffle_f32x4( @@ -24656,7 +24656,7 @@ pub fn _mm512_mask_shuffle_f32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_f32x4&expand=5164) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff32x4, MASK = 0b1011))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shuffle_f32x4(k: __mmask16, a: __m512, b: __m512) -> __m512 { @@ -24672,7 +24672,7 @@ pub fn _mm512_maskz_shuffle_f32x4(k: __mmask16, a: __m512, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shuffle_f32x4&expand=5162) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b01))] //should be vshuff32x4 #[rustc_legacy_const_generics(2)] pub fn _mm256_shuffle_f32x4(a: __m256, b: __m256) -> __m256 { @@ -24703,7 +24703,7 @@ pub fn _mm256_shuffle_f32x4(a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_f32x4&expand=5160) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff32x4, MASK = 0b11))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shuffle_f32x4( @@ -24724,7 +24724,7 @@ pub fn _mm256_mask_shuffle_f32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_f32x4&expand=5161) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff32x4, MASK = 0b11))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shuffle_f32x4(k: __mmask8, a: __m256, b: __m256) -> __m256 { @@ -24740,7 +24740,7 @@ pub fn _mm256_maskz_shuffle_f32x4(k: __mmask8, a: __m256, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_f64x2&expand=5171) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b10_11_11_11))] #[rustc_legacy_const_generics(2)] pub fn _mm512_shuffle_f64x2(a: __m512d, b: __m512d) -> __m512d { @@ -24771,7 +24771,7 @@ pub fn _mm512_shuffle_f64x2(a: __m512d, b: __m512d) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_f64x2&expand=5169) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b10_11_11_11))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shuffle_f64x2( @@ -24792,7 +24792,7 @@ pub fn _mm512_mask_shuffle_f64x2( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_f64x2&expand=5170) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b10_11_11_11))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shuffle_f64x2(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { @@ -24808,7 +24808,7 @@ pub fn _mm512_maskz_shuffle_f64x2(k: __mmask8, a: __m512d, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shuffle_f64x2&expand=5168) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm, MASK = 0b01))] //should be vshuff64x2 #[rustc_legacy_const_generics(2)] pub fn _mm256_shuffle_f64x2(a: __m256d, b: __m256d) -> __m256d { @@ -24835,7 +24835,7 @@ pub fn _mm256_shuffle_f64x2(a: __m256d, b: __m256d) -> __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_f64x2&expand=5166) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b11))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shuffle_f64x2( @@ -24856,7 +24856,7 @@ pub fn _mm256_mask_shuffle_f64x2( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_f64x2&expand=5167) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vshuff64x2, MASK = 0b11))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shuffle_f64x2(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { @@ -24872,7 +24872,7 @@ pub fn _mm256_maskz_shuffle_f64x2(k: __mmask8, a: __m256d, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_extractf32x4_ps&expand=2442) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))] #[rustc_legacy_const_generics(1)] pub fn _mm512_extractf32x4_ps(a: __m512) -> __m128 { @@ -24892,7 +24892,7 @@ pub fn _mm512_extractf32x4_ps(a: __m512) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_extractf32x4_ps&expand=2443) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_extractf32x4_ps(src: __m128, k: __mmask8, a: __m512) -> __m128 { @@ -24908,7 +24908,7 @@ pub fn _mm512_mask_extractf32x4_ps(src: __m128, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_extractf32x4_ps&expand=2444) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 3))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_extractf32x4_ps(k: __mmask8, a: __m512) -> __m128 { @@ -24924,7 +24924,7 @@ pub fn _mm512_maskz_extractf32x4_ps(k: __mmask8, a: __m512) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_extractf32x4_ps&expand=2439) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( test, assert_instr(vextract, IMM8 = 1) //should be vextractf32x4 @@ -24945,7 +24945,7 @@ pub fn _mm256_extractf32x4_ps(a: __m256) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_extractf32x4_ps&expand=2440) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_extractf32x4_ps(src: __m128, k: __mmask8, a: __m256) -> __m128 { @@ -24961,7 +24961,7 @@ pub fn _mm256_mask_extractf32x4_ps(src: __m128, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_extractf32x4_ps&expand=2441) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextractf32x4, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_extractf32x4_ps(k: __mmask8, a: __m256) -> __m128 { @@ -24977,7 +24977,7 @@ pub fn _mm256_maskz_extractf32x4_ps(k: __mmask8, a: __m256) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_extracti64x4_epi64&expand=2473) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( test, assert_instr(vextractf64x4, IMM1 = 1) //should be vextracti64x4 @@ -24998,7 +24998,7 @@ pub fn _mm512_extracti64x4_epi64(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_extracti64x4_epi64&expand=2474) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextracti64x4, IMM1 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_extracti64x4_epi64( @@ -25018,7 +25018,7 @@ pub fn _mm512_mask_extracti64x4_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_extracti64x4_epi64&expand=2475) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextracti64x4, IMM1 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_extracti64x4_epi64(k: __mmask8, a: __m512i) -> __m256i { @@ -25034,7 +25034,7 @@ pub fn _mm512_maskz_extracti64x4_epi64(k: __mmask8, a: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_extractf64x4_pd&expand=2454) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))] #[rustc_legacy_const_generics(1)] pub fn _mm512_extractf64x4_pd(a: __m512d) -> __m256d { @@ -25052,7 +25052,7 @@ pub fn _mm512_extractf64x4_pd(a: __m512d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_extractf64x4_pd&expand=2455) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_extractf64x4_pd( @@ -25072,7 +25072,7 @@ pub fn _mm512_mask_extractf64x4_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_extractf64x4_pd&expand=2456) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextractf64x4, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_extractf64x4_pd(k: __mmask8, a: __m512d) -> __m256d { @@ -25088,7 +25088,7 @@ pub fn _mm512_maskz_extractf64x4_pd(k: __mmask8, a: __m512d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_extracti32x4_epi32&expand=2461) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( test, assert_instr(vextractf32x4, IMM2 = 3) //should be vextracti32x4 @@ -25114,7 +25114,7 @@ pub fn _mm512_extracti32x4_epi32(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_extracti32x4_epi32&expand=2462) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextracti32x4, IMM2 = 3))] #[rustc_legacy_const_generics(3)] pub fn _mm512_mask_extracti32x4_epi32( @@ -25134,7 +25134,7 @@ pub fn _mm512_mask_extracti32x4_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_extracti32x4_epi32&expand=2463) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextracti32x4, IMM2 = 3))] #[rustc_legacy_const_generics(2)] pub fn _mm512_maskz_extracti32x4_epi32(k: __mmask8, a: __m512i) -> __m128i { @@ -25150,7 +25150,7 @@ pub fn _mm512_maskz_extracti32x4_epi32(k: __mmask8, a: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_extracti32x4_epi32&expand=2458) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( test, assert_instr(vextract, IMM1 = 1) //should be vextracti32x4 @@ -25174,7 +25174,7 @@ pub fn _mm256_extracti32x4_epi32(a: __m256i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_extracti32x4_epi32&expand=2459) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextracti32x4, IMM1 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_mask_extracti32x4_epi32( @@ -25194,7 +25194,7 @@ pub fn _mm256_mask_extracti32x4_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_extracti32x4_epi32&expand=2460) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vextracti32x4, IMM1 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_maskz_extracti32x4_epi32(k: __mmask8, a: __m256i) -> __m128i { @@ -25210,7 +25210,7 @@ pub fn _mm256_maskz_extracti32x4_epi32(k: __mmask8, a: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_moveldup_ps&expand=3862) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsldup))] pub fn _mm512_moveldup_ps(a: __m512) -> __m512 { unsafe { @@ -25224,7 +25224,7 @@ pub fn _mm512_moveldup_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_moveldup_ps&expand=3860) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsldup))] pub fn _mm512_mask_moveldup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { @@ -25239,7 +25239,7 @@ pub fn _mm512_mask_moveldup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_moveldup_ps&expand=3861) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsldup))] pub fn _mm512_maskz_moveldup_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { @@ -25254,7 +25254,7 @@ pub fn _mm512_maskz_moveldup_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_moveldup_ps&expand=3857) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsldup))] pub fn _mm256_mask_moveldup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { @@ -25268,7 +25268,7 @@ pub fn _mm256_mask_moveldup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_moveldup_ps&expand=3858) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsldup))] pub fn _mm256_maskz_moveldup_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { @@ -25282,7 +25282,7 @@ pub fn _mm256_maskz_moveldup_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_moveldup_ps&expand=3854) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsldup))] pub fn _mm_mask_moveldup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { @@ -25296,7 +25296,7 @@ pub fn _mm_mask_moveldup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_moveldup_ps&expand=3855) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsldup))] pub fn _mm_maskz_moveldup_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { @@ -25310,7 +25310,7 @@ pub fn _mm_maskz_moveldup_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movehdup_ps&expand=3852) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovshdup))] pub fn _mm512_movehdup_ps(a: __m512) -> __m512 { unsafe { @@ -25324,7 +25324,7 @@ pub fn _mm512_movehdup_ps(a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_movehdup_ps&expand=3850) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovshdup))] pub fn _mm512_mask_movehdup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { unsafe { @@ -25339,7 +25339,7 @@ pub fn _mm512_mask_movehdup_ps(src: __m512, k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_movehdup_ps&expand=3851) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovshdup))] pub fn _mm512_maskz_movehdup_ps(k: __mmask16, a: __m512) -> __m512 { unsafe { @@ -25354,7 +25354,7 @@ pub fn _mm512_maskz_movehdup_ps(k: __mmask16, a: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_movehdup_ps&expand=3847) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovshdup))] pub fn _mm256_mask_movehdup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { unsafe { @@ -25368,7 +25368,7 @@ pub fn _mm256_mask_movehdup_ps(src: __m256, k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_movehdup_ps&expand=3848) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovshdup))] pub fn _mm256_maskz_movehdup_ps(k: __mmask8, a: __m256) -> __m256 { unsafe { @@ -25382,7 +25382,7 @@ pub fn _mm256_maskz_movehdup_ps(k: __mmask8, a: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_movehdup_ps&expand=3844) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovshdup))] pub fn _mm_mask_movehdup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { @@ -25396,7 +25396,7 @@ pub fn _mm_mask_movehdup_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_movehdup_ps&expand=3845) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovshdup))] pub fn _mm_maskz_movehdup_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { @@ -25410,7 +25410,7 @@ pub fn _mm_maskz_movehdup_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movedup_pd&expand=3843) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovddup))] pub fn _mm512_movedup_pd(a: __m512d) -> __m512d { unsafe { @@ -25424,7 +25424,7 @@ pub fn _mm512_movedup_pd(a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_movedup_pd&expand=3841) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovddup))] pub fn _mm512_mask_movedup_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d { unsafe { @@ -25438,7 +25438,7 @@ pub fn _mm512_mask_movedup_pd(src: __m512d, k: __mmask8, a: __m512d) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_movedup_pd&expand=3842) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovddup))] pub fn _mm512_maskz_movedup_pd(k: __mmask8, a: __m512d) -> __m512d { unsafe { @@ -25452,7 +25452,7 @@ pub fn _mm512_maskz_movedup_pd(k: __mmask8, a: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_movedup_pd&expand=3838) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovddup))] pub fn _mm256_mask_movedup_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d { unsafe { @@ -25466,7 +25466,7 @@ pub fn _mm256_mask_movedup_pd(src: __m256d, k: __mmask8, a: __m256d) -> __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_movedup_pd&expand=3839) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovddup))] pub fn _mm256_maskz_movedup_pd(k: __mmask8, a: __m256d) -> __m256d { unsafe { @@ -25480,7 +25480,7 @@ pub fn _mm256_maskz_movedup_pd(k: __mmask8, a: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_movedup_pd&expand=3835) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovddup))] pub fn _mm_mask_movedup_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { unsafe { @@ -25494,7 +25494,7 @@ pub fn _mm_mask_movedup_pd(src: __m128d, k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_movedup_pd&expand=3836) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovddup))] pub fn _mm_maskz_movedup_pd(k: __mmask8, a: __m128d) -> __m128d { unsafe { @@ -25508,7 +25508,7 @@ pub fn _mm_maskz_movedup_pd(k: __mmask8, a: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_inserti32x4&expand=3174) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 2))] //should be vinserti32x4 #[rustc_legacy_const_generics(2)] pub fn _mm512_inserti32x4(a: __m512i, b: __m128i) -> __m512i { @@ -25551,7 +25551,7 @@ pub fn _mm512_inserti32x4(a: __m512i, b: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_inserti32x4&expand=3175) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 2))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_inserti32x4( @@ -25572,7 +25572,7 @@ pub fn _mm512_mask_inserti32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_inserti32x4&expand=3176) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 2))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_inserti32x4(k: __mmask16, a: __m512i, b: __m128i) -> __m512i { @@ -25588,7 +25588,7 @@ pub fn _mm512_maskz_inserti32x4(k: __mmask16, a: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_inserti32x4&expand=3171) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( test, assert_instr(vinsert, IMM8 = 1) //should be vinserti32x4 @@ -25612,7 +25612,7 @@ pub fn _mm256_inserti32x4(a: __m256i, b: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_inserti32x4&expand=3172) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_inserti32x4( @@ -25633,7 +25633,7 @@ pub fn _mm256_mask_inserti32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_inserti32x4&expand=3173) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinserti32x4, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_inserti32x4(k: __mmask8, a: __m256i, b: __m128i) -> __m256i { @@ -25649,7 +25649,7 @@ pub fn _mm256_maskz_inserti32x4(k: __mmask8, a: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_inserti64x4&expand=3186) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf64x4, IMM8 = 1))] //should be vinserti64x4 #[rustc_legacy_const_generics(2)] pub fn _mm512_inserti64x4(a: __m512i, b: __m256i) -> __m512i { @@ -25668,7 +25668,7 @@ pub fn _mm512_inserti64x4(a: __m512i, b: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_inserti64x4&expand=3187) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinserti64x4, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_inserti64x4( @@ -25689,7 +25689,7 @@ pub fn _mm512_mask_inserti64x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_inserti64x4&expand=3188) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinserti64x4, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_inserti64x4(k: __mmask8, a: __m512i, b: __m256i) -> __m512i { @@ -25705,7 +25705,7 @@ pub fn _mm512_maskz_inserti64x4(k: __mmask8, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_insertf32x4&expand=3155) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 2))] #[rustc_legacy_const_generics(2)] pub fn _mm512_insertf32x4(a: __m512, b: __m128) -> __m512 { @@ -25746,7 +25746,7 @@ pub fn _mm512_insertf32x4(a: __m512, b: __m128) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_insertf32x4&expand=3156) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 2))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_insertf32x4( @@ -25767,7 +25767,7 @@ pub fn _mm512_mask_insertf32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_insertf32x4&expand=3157) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 2))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_insertf32x4(k: __mmask16, a: __m512, b: __m128) -> __m512 { @@ -25783,7 +25783,7 @@ pub fn _mm512_maskz_insertf32x4(k: __mmask16, a: __m512, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_insertf32x4&expand=3152) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( test, assert_instr(vinsert, IMM8 = 1) //should be vinsertf32x4 @@ -25805,7 +25805,7 @@ pub fn _mm256_insertf32x4(a: __m256, b: __m128) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_insertf32x4&expand=3153) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_insertf32x4( @@ -25826,7 +25826,7 @@ pub fn _mm256_mask_insertf32x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_insertf32x4&expand=3154) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf32x4, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_insertf32x4(k: __mmask8, a: __m256, b: __m128) -> __m256 { @@ -25842,7 +25842,7 @@ pub fn _mm256_maskz_insertf32x4(k: __mmask8, a: __m256, b: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_insertf64x4&expand=3167) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf64x4, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_insertf64x4(a: __m512d, b: __m256d) -> __m512d { @@ -25861,7 +25861,7 @@ pub fn _mm512_insertf64x4(a: __m512d, b: __m256d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_insertf64x4&expand=3168) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf64x4, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_insertf64x4( @@ -25882,7 +25882,7 @@ pub fn _mm512_mask_insertf64x4( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_insertf64x4&expand=3169) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vinsertf64x4, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_insertf64x4(k: __mmask8, a: __m512d, b: __m256d) -> __m512d { @@ -25898,7 +25898,7 @@ pub fn _mm512_maskz_insertf64x4(k: __mmask8, a: __m512d, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpackhi_epi32&expand=6021) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhps))] //should be vpunpckhdq pub fn _mm512_unpackhi_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -25921,7 +25921,7 @@ pub fn _mm512_unpackhi_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpackhi_epi32&expand=6019) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhdq))] pub fn _mm512_mask_unpackhi_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -25935,7 +25935,7 @@ pub fn _mm512_mask_unpackhi_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpackhi_epi32&expand=6020) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhdq))] pub fn _mm512_maskz_unpackhi_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -25949,7 +25949,7 @@ pub fn _mm512_maskz_unpackhi_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpackhi_epi32&expand=6016) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhdq))] pub fn _mm256_mask_unpackhi_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -25963,7 +25963,7 @@ pub fn _mm256_mask_unpackhi_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpackhi_epi32&expand=6017) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhdq))] pub fn _mm256_maskz_unpackhi_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -25977,7 +25977,7 @@ pub fn _mm256_maskz_unpackhi_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpackhi_epi32&expand=6013) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhdq))] pub fn _mm_mask_unpackhi_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -25991,7 +25991,7 @@ pub fn _mm_mask_unpackhi_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpackhi_epi32&expand=6014) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhdq))] pub fn _mm_maskz_unpackhi_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -26005,7 +26005,7 @@ pub fn _mm_maskz_unpackhi_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpackhi_epi64&expand=6030) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhpd))] //should be vpunpckhqdq pub fn _mm512_unpackhi_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { simd_shuffle!(a, b, [1, 9, 1 + 2, 9 + 2, 1 + 4, 9 + 4, 1 + 6, 9 + 6]) } @@ -26016,7 +26016,7 @@ pub fn _mm512_unpackhi_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpackhi_epi64&expand=6028) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhqdq))] pub fn _mm512_mask_unpackhi_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -26030,7 +26030,7 @@ pub fn _mm512_mask_unpackhi_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpackhi_epi64&expand=6029) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhqdq))] pub fn _mm512_maskz_unpackhi_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -26044,7 +26044,7 @@ pub fn _mm512_maskz_unpackhi_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpackhi_epi64&expand=6025) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhqdq))] pub fn _mm256_mask_unpackhi_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -26058,7 +26058,7 @@ pub fn _mm256_mask_unpackhi_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpackhi_epi64&expand=6026) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhqdq))] pub fn _mm256_maskz_unpackhi_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -26072,7 +26072,7 @@ pub fn _mm256_maskz_unpackhi_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpackhi_epi64&expand=6022) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhqdq))] pub fn _mm_mask_unpackhi_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -26086,7 +26086,7 @@ pub fn _mm_mask_unpackhi_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpackhi_epi64&expand=6023) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckhqdq))] pub fn _mm_maskz_unpackhi_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -26100,7 +26100,7 @@ pub fn _mm_maskz_unpackhi_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpackhi_ps&expand=6060) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhps))] pub fn _mm512_unpackhi_ps(a: __m512, b: __m512) -> __m512 { unsafe { @@ -26120,7 +26120,7 @@ pub fn _mm512_unpackhi_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpackhi_ps&expand=6058) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhps))] pub fn _mm512_mask_unpackhi_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -26134,7 +26134,7 @@ pub fn _mm512_mask_unpackhi_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpackhi_ps&expand=6059) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhps))] pub fn _mm512_maskz_unpackhi_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -26148,7 +26148,7 @@ pub fn _mm512_maskz_unpackhi_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpackhi_ps&expand=6055) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhps))] pub fn _mm256_mask_unpackhi_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -26162,7 +26162,7 @@ pub fn _mm256_mask_unpackhi_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpackhi_ps&expand=6056) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhps))] pub fn _mm256_maskz_unpackhi_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -26176,7 +26176,7 @@ pub fn _mm256_maskz_unpackhi_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpackhi_ps&expand=6052) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhps))] pub fn _mm_mask_unpackhi_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -26190,7 +26190,7 @@ pub fn _mm_mask_unpackhi_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpackhi_ps&expand=6053) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhps))] pub fn _mm_maskz_unpackhi_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -26204,7 +26204,7 @@ pub fn _mm_maskz_unpackhi_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpackhi_pd&expand=6048) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhpd))] pub fn _mm512_unpackhi_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { simd_shuffle!(a, b, [1, 9, 1 + 2, 9 + 2, 1 + 4, 9 + 4, 1 + 6, 9 + 6]) } @@ -26215,7 +26215,7 @@ pub fn _mm512_unpackhi_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpackhi_pd&expand=6046) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhpd))] pub fn _mm512_mask_unpackhi_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -26229,7 +26229,7 @@ pub fn _mm512_mask_unpackhi_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpackhi_pd&expand=6047) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhpd))] pub fn _mm512_maskz_unpackhi_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -26243,7 +26243,7 @@ pub fn _mm512_maskz_unpackhi_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpackhi_pd&expand=6043) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhpd))] pub fn _mm256_mask_unpackhi_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -26257,7 +26257,7 @@ pub fn _mm256_mask_unpackhi_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpackhi_pd&expand=6044) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhpd))] pub fn _mm256_maskz_unpackhi_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -26271,7 +26271,7 @@ pub fn _mm256_maskz_unpackhi_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpackhi_pd&expand=6040) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhpd))] pub fn _mm_mask_unpackhi_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -26285,7 +26285,7 @@ pub fn _mm_mask_unpackhi_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpackhi_pd&expand=6041) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpckhpd))] pub fn _mm_maskz_unpackhi_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -26299,7 +26299,7 @@ pub fn _mm_maskz_unpackhi_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpacklo_epi32&expand=6078) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklps))] //should be vpunpckldq pub fn _mm512_unpacklo_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -26322,7 +26322,7 @@ pub fn _mm512_unpacklo_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpacklo_epi32&expand=6076) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckldq))] pub fn _mm512_mask_unpacklo_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -26336,7 +26336,7 @@ pub fn _mm512_mask_unpacklo_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpacklo_epi32&expand=6077) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckldq))] pub fn _mm512_maskz_unpacklo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -26350,7 +26350,7 @@ pub fn _mm512_maskz_unpacklo_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpacklo_epi32&expand=6073) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckldq))] pub fn _mm256_mask_unpacklo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -26364,7 +26364,7 @@ pub fn _mm256_mask_unpacklo_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpacklo_epi32&expand=6074) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckldq))] pub fn _mm256_maskz_unpacklo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -26378,7 +26378,7 @@ pub fn _mm256_maskz_unpacklo_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpacklo_epi32&expand=6070) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckldq))] pub fn _mm_mask_unpacklo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -26392,7 +26392,7 @@ pub fn _mm_mask_unpacklo_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpacklo_epi32&expand=6071) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpckldq))] pub fn _mm_maskz_unpacklo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -26406,7 +26406,7 @@ pub fn _mm_maskz_unpacklo_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpacklo_epi64&expand=6087) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklpd))] //should be vpunpcklqdq pub fn _mm512_unpacklo_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { simd_shuffle!(a, b, [0, 8, 0 + 2, 8 + 2, 0 + 4, 8 + 4, 0 + 6, 8 + 6]) } @@ -26417,7 +26417,7 @@ pub fn _mm512_unpacklo_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpacklo_epi64&expand=6085) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklqdq))] pub fn _mm512_mask_unpacklo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -26431,7 +26431,7 @@ pub fn _mm512_mask_unpacklo_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpacklo_epi64&expand=6086) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklqdq))] pub fn _mm512_maskz_unpacklo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -26445,7 +26445,7 @@ pub fn _mm512_maskz_unpacklo_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpacklo_epi64&expand=6082) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklqdq))] pub fn _mm256_mask_unpacklo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -26459,7 +26459,7 @@ pub fn _mm256_mask_unpacklo_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpacklo_epi64&expand=6083) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklqdq))] pub fn _mm256_maskz_unpacklo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -26473,7 +26473,7 @@ pub fn _mm256_maskz_unpacklo_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpacklo_epi64&expand=6079) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklqdq))] pub fn _mm_mask_unpacklo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -26487,7 +26487,7 @@ pub fn _mm_mask_unpacklo_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpacklo_epi64&expand=6080) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpunpcklqdq))] pub fn _mm_maskz_unpacklo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -26501,7 +26501,7 @@ pub fn _mm_maskz_unpacklo_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpacklo_ps&expand=6117) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklps))] pub fn _mm512_unpacklo_ps(a: __m512, b: __m512) -> __m512 { unsafe { @@ -26520,7 +26520,7 @@ pub fn _mm512_unpacklo_ps(a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpacklo_ps&expand=6115) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklps))] pub fn _mm512_mask_unpacklo_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -26534,7 +26534,7 @@ pub fn _mm512_mask_unpacklo_ps(src: __m512, k: __mmask16, a: __m512, b: __m512) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpacklo_ps&expand=6116) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklps))] pub fn _mm512_maskz_unpacklo_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { @@ -26548,7 +26548,7 @@ pub fn _mm512_maskz_unpacklo_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpacklo_ps&expand=6112) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklps))] pub fn _mm256_mask_unpacklo_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -26562,7 +26562,7 @@ pub fn _mm256_mask_unpacklo_ps(src: __m256, k: __mmask8, a: __m256, b: __m256) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpacklo_ps&expand=6113) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklps))] pub fn _mm256_maskz_unpacklo_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { @@ -26576,7 +26576,7 @@ pub fn _mm256_maskz_unpacklo_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpacklo_ps&expand=6109) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklps))] pub fn _mm_mask_unpacklo_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -26590,7 +26590,7 @@ pub fn _mm_mask_unpacklo_ps(src: __m128, k: __mmask8, a: __m128, b: __m128) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpacklo_ps&expand=6110) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklps))] pub fn _mm_maskz_unpacklo_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -26604,7 +26604,7 @@ pub fn _mm_maskz_unpacklo_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpacklo_pd&expand=6105) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklpd))] pub fn _mm512_unpacklo_pd(a: __m512d, b: __m512d) -> __m512d { unsafe { simd_shuffle!(a, b, [0, 8, 0 + 2, 8 + 2, 0 + 4, 8 + 4, 0 + 6, 8 + 6]) } @@ -26615,7 +26615,7 @@ pub fn _mm512_unpacklo_pd(a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpacklo_pd&expand=6103) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklpd))] pub fn _mm512_mask_unpacklo_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -26629,7 +26629,7 @@ pub fn _mm512_mask_unpacklo_pd(src: __m512d, k: __mmask8, a: __m512d, b: __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpacklo_pd&expand=6104) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklpd))] pub fn _mm512_maskz_unpacklo_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { @@ -26643,7 +26643,7 @@ pub fn _mm512_maskz_unpacklo_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpacklo_pd&expand=6100) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklpd))] pub fn _mm256_mask_unpacklo_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -26657,7 +26657,7 @@ pub fn _mm256_mask_unpacklo_pd(src: __m256d, k: __mmask8, a: __m256d, b: __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpacklo_pd&expand=6101) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklpd))] pub fn _mm256_maskz_unpacklo_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { @@ -26671,7 +26671,7 @@ pub fn _mm256_maskz_unpacklo_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpacklo_pd&expand=6097) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklpd))] pub fn _mm_mask_unpacklo_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -26685,7 +26685,7 @@ pub fn _mm_mask_unpacklo_pd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpacklo_pd&expand=6098) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vunpcklpd))] pub fn _mm_maskz_unpacklo_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -26699,7 +26699,7 @@ pub fn _mm_maskz_unpacklo_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castps128_ps512&expand=621) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castps128_ps512(a: __m128) -> __m512 { unsafe { simd_shuffle!( @@ -26715,7 +26715,7 @@ pub fn _mm512_castps128_ps512(a: __m128) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castps256_ps512&expand=623) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castps256_ps512(a: __m256) -> __m512 { unsafe { simd_shuffle!( @@ -26731,7 +26731,7 @@ pub fn _mm512_castps256_ps512(a: __m256) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_zextps128_ps512&expand=6196) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_zextps128_ps512(a: __m128) -> __m512 { unsafe { simd_shuffle!( @@ -26747,7 +26747,7 @@ pub fn _mm512_zextps128_ps512(a: __m128) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_zextps256_ps512&expand=6197) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_zextps256_ps512(a: __m256) -> __m512 { unsafe { simd_shuffle!( @@ -26763,7 +26763,7 @@ pub fn _mm512_zextps256_ps512(a: __m256) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castps512_ps128&expand=624) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castps512_ps128(a: __m512) -> __m128 { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } @@ -26773,7 +26773,7 @@ pub fn _mm512_castps512_ps128(a: __m512) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castps512_ps256&expand=625) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castps512_ps256(a: __m512) -> __m256 { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } } @@ -26783,7 +26783,7 @@ pub fn _mm512_castps512_ps256(a: __m512) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castps_pd&expand=616) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castps_pd(a: __m512) -> __m512d { unsafe { transmute(a) } } @@ -26793,7 +26793,7 @@ pub fn _mm512_castps_pd(a: __m512) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castps_si512&expand=619) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castps_si512(a: __m512) -> __m512i { unsafe { transmute(a) } } @@ -26803,7 +26803,7 @@ pub fn _mm512_castps_si512(a: __m512) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castpd128_pd512&expand=609) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castpd128_pd512(a: __m128d) -> __m512d { unsafe { simd_shuffle!(a, _mm_undefined_pd(), [0, 1, 2, 2, 2, 2, 2, 2]) } } @@ -26813,7 +26813,7 @@ pub fn _mm512_castpd128_pd512(a: __m128d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castpd256_pd512&expand=611) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castpd256_pd512(a: __m256d) -> __m512d { unsafe { simd_shuffle!(a, _mm256_undefined_pd(), [0, 1, 2, 3, 4, 4, 4, 4]) } } @@ -26823,7 +26823,7 @@ pub fn _mm512_castpd256_pd512(a: __m256d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_zextpd128_pd512&expand=6193) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_zextpd128_pd512(a: __m128d) -> __m512d { unsafe { simd_shuffle!(a, _mm_set1_pd(0.), [0, 1, 2, 2, 2, 2, 2, 2]) } } @@ -26833,7 +26833,7 @@ pub fn _mm512_zextpd128_pd512(a: __m128d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_zextpd256_pd512&expand=6194) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_zextpd256_pd512(a: __m256d) -> __m512d { unsafe { simd_shuffle!(a, _mm256_set1_pd(0.), [0, 1, 2, 3, 4, 4, 4, 4]) } } @@ -26843,7 +26843,7 @@ pub fn _mm512_zextpd256_pd512(a: __m256d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castpd512_pd128&expand=612) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castpd512_pd128(a: __m512d) -> __m128d { unsafe { simd_shuffle!(a, a, [0, 1]) } } @@ -26853,7 +26853,7 @@ pub fn _mm512_castpd512_pd128(a: __m512d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castpd512_pd256&expand=613) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castpd512_pd256(a: __m512d) -> __m256d { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } @@ -26863,7 +26863,7 @@ pub fn _mm512_castpd512_pd256(a: __m512d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castpd_ps&expand=604) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castpd_ps(a: __m512d) -> __m512 { unsafe { transmute(a) } } @@ -26873,7 +26873,7 @@ pub fn _mm512_castpd_ps(a: __m512d) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castpd_si512&expand=607) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castpd_si512(a: __m512d) -> __m512i { unsafe { transmute(a) } } @@ -26883,7 +26883,7 @@ pub fn _mm512_castpd_si512(a: __m512d) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castsi128_si512&expand=629) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castsi128_si512(a: __m128i) -> __m512i { unsafe { simd_shuffle!(a, _mm_undefined_si128(), [0, 1, 2, 2, 2, 2, 2, 2]) } } @@ -26893,7 +26893,7 @@ pub fn _mm512_castsi128_si512(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castsi256_si512&expand=633) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castsi256_si512(a: __m256i) -> __m512i { unsafe { simd_shuffle!(a, _mm256_undefined_si256(), [0, 1, 2, 3, 4, 4, 4, 4]) } } @@ -26903,7 +26903,7 @@ pub fn _mm512_castsi256_si512(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_zextsi128_si512&expand=6199) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_zextsi128_si512(a: __m128i) -> __m512i { unsafe { simd_shuffle!(a, _mm_setzero_si128(), [0, 1, 2, 2, 2, 2, 2, 2]) } } @@ -26913,7 +26913,7 @@ pub fn _mm512_zextsi128_si512(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_zextsi256_si512&expand=6200) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_zextsi256_si512(a: __m256i) -> __m512i { unsafe { simd_shuffle!(a, _mm256_setzero_si256(), [0, 1, 2, 3, 4, 4, 4, 4]) } } @@ -26923,7 +26923,7 @@ pub fn _mm512_zextsi256_si512(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castsi512_si128&expand=636) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castsi512_si128(a: __m512i) -> __m128i { unsafe { simd_shuffle!(a, a, [0, 1]) } } @@ -26933,7 +26933,7 @@ pub fn _mm512_castsi512_si128(a: __m512i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castsi512_si256&expand=637) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castsi512_si256(a: __m512i) -> __m256i { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) } } @@ -26943,7 +26943,7 @@ pub fn _mm512_castsi512_si256(a: __m512i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castsi512_ps&expand=635) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castsi512_ps(a: __m512i) -> __m512 { unsafe { transmute(a) } } @@ -26953,7 +26953,7 @@ pub fn _mm512_castsi512_ps(a: __m512i) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_castsi512_pd&expand=634) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_castsi512_pd(a: __m512i) -> __m512d { unsafe { transmute(a) } } @@ -26963,7 +26963,7 @@ pub fn _mm512_castsi512_pd(a: __m512i) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsi512_si32&expand=1882) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovd))] pub fn _mm512_cvtsi512_si32(a: __m512i) -> i32 { unsafe { simd_extract!(a.as_i32x16(), 0) } @@ -26974,7 +26974,7 @@ pub fn _mm512_cvtsi512_si32(a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtss_f32) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtss_f32(a: __m512) -> f32 { unsafe { simd_extract!(a, 0) } } @@ -26984,7 +26984,7 @@ pub fn _mm512_cvtss_f32(a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsd_f64) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_cvtsd_f64(a: __m512d) -> f64 { unsafe { simd_extract!(a, 0) } } @@ -26994,7 +26994,7 @@ pub fn _mm512_cvtsd_f64(a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastd_epi32&expand=545) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcast))] //should be vpbroadcastd pub fn _mm512_broadcastd_epi32(a: __m128i) -> __m512i { unsafe { @@ -27009,7 +27009,7 @@ pub fn _mm512_broadcastd_epi32(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcastd_epi32&expand=546) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd pub fn _mm512_mask_broadcastd_epi32(src: __m512i, k: __mmask16, a: __m128i) -> __m512i { unsafe { @@ -27023,7 +27023,7 @@ pub fn _mm512_mask_broadcastd_epi32(src: __m512i, k: __mmask16, a: __m128i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcastd_epi32&expand=547) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd pub fn _mm512_maskz_broadcastd_epi32(k: __mmask16, a: __m128i) -> __m512i { unsafe { @@ -27037,7 +27037,7 @@ pub fn _mm512_maskz_broadcastd_epi32(k: __mmask16, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcastd_epi32&expand=543) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd pub fn _mm256_mask_broadcastd_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -27051,7 +27051,7 @@ pub fn _mm256_mask_broadcastd_epi32(src: __m256i, k: __mmask8, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcastd_epi32&expand=544) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd pub fn _mm256_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -27065,7 +27065,7 @@ pub fn _mm256_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_broadcastd_epi32&expand=540) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd pub fn _mm_mask_broadcastd_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -27079,7 +27079,7 @@ pub fn _mm_mask_broadcastd_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_broadcastd_epi32&expand=541) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastd pub fn _mm_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -27093,7 +27093,7 @@ pub fn _mm_maskz_broadcastd_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastq_epi64&expand=560) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcast))] //should be vpbroadcastq pub fn _mm512_broadcastq_epi64(a: __m128i) -> __m512i { unsafe { simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0]) } @@ -27104,7 +27104,7 @@ pub fn _mm512_broadcastq_epi64(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcastq_epi64&expand=561) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq pub fn _mm512_mask_broadcastq_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -27118,7 +27118,7 @@ pub fn _mm512_mask_broadcastq_epi64(src: __m512i, k: __mmask8, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcastq_epi64&expand=562) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq pub fn _mm512_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m512i { unsafe { @@ -27132,7 +27132,7 @@ pub fn _mm512_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcastq_epi64&expand=558) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq pub fn _mm256_mask_broadcastq_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -27146,7 +27146,7 @@ pub fn _mm256_mask_broadcastq_epi64(src: __m256i, k: __mmask8, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcastq_epi64&expand=559) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq pub fn _mm256_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m256i { unsafe { @@ -27160,7 +27160,7 @@ pub fn _mm256_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_broadcastq_epi64&expand=555) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq pub fn _mm_mask_broadcastq_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -27174,7 +27174,7 @@ pub fn _mm_mask_broadcastq_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_broadcastq_epi64&expand=556) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcast))] //should be vpbroadcastq pub fn _mm_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -27188,7 +27188,7 @@ pub fn _mm_maskz_broadcastq_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastss_ps&expand=578) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastss))] pub fn _mm512_broadcastss_ps(a: __m128) -> __m512 { unsafe { simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]) } @@ -27199,7 +27199,7 @@ pub fn _mm512_broadcastss_ps(a: __m128) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcastss_ps&expand=579) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastss))] pub fn _mm512_mask_broadcastss_ps(src: __m512, k: __mmask16, a: __m128) -> __m512 { unsafe { @@ -27213,7 +27213,7 @@ pub fn _mm512_mask_broadcastss_ps(src: __m512, k: __mmask16, a: __m128) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcastss_ps&expand=580) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastss))] pub fn _mm512_maskz_broadcastss_ps(k: __mmask16, a: __m128) -> __m512 { unsafe { @@ -27227,7 +27227,7 @@ pub fn _mm512_maskz_broadcastss_ps(k: __mmask16, a: __m128) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcastss_ps&expand=576) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastss))] pub fn _mm256_mask_broadcastss_ps(src: __m256, k: __mmask8, a: __m128) -> __m256 { unsafe { @@ -27241,7 +27241,7 @@ pub fn _mm256_mask_broadcastss_ps(src: __m256, k: __mmask8, a: __m128) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcastss_ps&expand=577) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastss))] pub fn _mm256_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m256 { unsafe { @@ -27255,7 +27255,7 @@ pub fn _mm256_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_broadcastss_ps&expand=573) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastss))] pub fn _mm_mask_broadcastss_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { unsafe { @@ -27269,7 +27269,7 @@ pub fn _mm_mask_broadcastss_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_broadcastss_ps&expand=574) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastss))] pub fn _mm_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m128 { unsafe { @@ -27283,7 +27283,7 @@ pub fn _mm_maskz_broadcastss_ps(k: __mmask8, a: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastsd_pd&expand=567) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastsd))] pub fn _mm512_broadcastsd_pd(a: __m128d) -> __m512d { unsafe { simd_shuffle!(a, a, [0, 0, 0, 0, 0, 0, 0, 0]) } @@ -27294,7 +27294,7 @@ pub fn _mm512_broadcastsd_pd(a: __m128d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcastsd_pd&expand=568) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastsd))] pub fn _mm512_mask_broadcastsd_pd(src: __m512d, k: __mmask8, a: __m128d) -> __m512d { unsafe { @@ -27308,7 +27308,7 @@ pub fn _mm512_mask_broadcastsd_pd(src: __m512d, k: __mmask8, a: __m128d) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcastsd_pd&expand=569) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastsd))] pub fn _mm512_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m512d { unsafe { @@ -27322,7 +27322,7 @@ pub fn _mm512_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcastsd_pd&expand=565) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastsd))] pub fn _mm256_mask_broadcastsd_pd(src: __m256d, k: __mmask8, a: __m128d) -> __m256d { unsafe { @@ -27336,7 +27336,7 @@ pub fn _mm256_mask_broadcastsd_pd(src: __m256d, k: __mmask8, a: __m128d) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcastsd_pd&expand=566) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vbroadcastsd))] pub fn _mm256_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m256d { unsafe { @@ -27350,7 +27350,7 @@ pub fn _mm256_maskz_broadcastsd_pd(k: __mmask8, a: __m128d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_i32x4&expand=510) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_i32x4(a: __m128i) -> __m512i { unsafe { let a = a.as_i32x4(); @@ -27364,7 +27364,7 @@ pub fn _mm512_broadcast_i32x4(a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcast_i32x4&expand=511) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_i32x4(src: __m512i, k: __mmask16, a: __m128i) -> __m512i { unsafe { let broadcast = _mm512_broadcast_i32x4(a).as_i32x16(); @@ -27377,7 +27377,7 @@ pub fn _mm512_mask_broadcast_i32x4(src: __m512i, k: __mmask16, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcast_i32x4&expand=512) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcasti32x4, linux: vshuf -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_i32x4(k: __mmask16, a: __m128i) -> __m512i { unsafe { let broadcast = _mm512_broadcast_i32x4(a).as_i32x16(); @@ -27390,7 +27390,7 @@ pub fn _mm512_maskz_broadcast_i32x4(k: __mmask16, a: __m128i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcast_i32x4&expand=507) #[inline] #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcasti32x4, linux: vshuf -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_broadcast_i32x4(a: __m128i) -> __m256i { unsafe { let a = a.as_i32x4(); @@ -27404,7 +27404,7 @@ pub fn _mm256_broadcast_i32x4(a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcast_i32x4&expand=508) #[inline] #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcasti32x4, linux: vshuf -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_broadcast_i32x4(src: __m256i, k: __mmask8, a: __m128i) -> __m256i { unsafe { let broadcast = _mm256_broadcast_i32x4(a).as_i32x8(); @@ -27417,7 +27417,7 @@ pub fn _mm256_mask_broadcast_i32x4(src: __m256i, k: __mmask8, a: __m128i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcast_i32x4&expand=509) #[inline] #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcasti32x4, linux: vshuf -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_broadcast_i32x4(k: __mmask8, a: __m128i) -> __m256i { unsafe { let broadcast = _mm256_broadcast_i32x4(a).as_i32x8(); @@ -27430,7 +27430,7 @@ pub fn _mm256_maskz_broadcast_i32x4(k: __mmask8, a: __m128i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_i64x4&expand=522) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_i64x4(a: __m256i) -> __m512i { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3]) } } @@ -27440,7 +27440,7 @@ pub fn _mm512_broadcast_i64x4(a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcast_i64x4&expand=523) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_i64x4(src: __m512i, k: __mmask8, a: __m256i) -> __m512i { unsafe { let broadcast = _mm512_broadcast_i64x4(a).as_i64x8(); @@ -27453,7 +27453,7 @@ pub fn _mm512_mask_broadcast_i64x4(src: __m512i, k: __mmask8, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcast_i64x4&expand=524) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcasti64x4, linux: vperm -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_i64x4(k: __mmask8, a: __m256i) -> __m512i { unsafe { let broadcast = _mm512_broadcast_i64x4(a).as_i64x8(); @@ -27466,7 +27466,7 @@ pub fn _mm512_maskz_broadcast_i64x4(k: __mmask8, a: __m256i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_f32x4&expand=483) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshuf -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_f32x4(a: __m128) -> __m512 { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3]) } } @@ -27476,7 +27476,7 @@ pub fn _mm512_broadcast_f32x4(a: __m128) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcast_f32x4&expand=484) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshu -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_f32x4(src: __m512, k: __mmask16, a: __m128) -> __m512 { unsafe { let broadcast = _mm512_broadcast_f32x4(a).as_f32x16(); @@ -27489,7 +27489,7 @@ pub fn _mm512_mask_broadcast_f32x4(src: __m512, k: __mmask16, a: __m128) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcast_f32x4&expand=485) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcastf32x4, linux: vshu -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_f32x4(k: __mmask16, a: __m128) -> __m512 { unsafe { let broadcast = _mm512_broadcast_f32x4(a).as_f32x16(); @@ -27502,7 +27502,7 @@ pub fn _mm512_maskz_broadcast_f32x4(k: __mmask16, a: __m128) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_broadcast_f32x4&expand=480) #[inline] #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcastf32x4, linux: vshuf -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_broadcast_f32x4(a: __m128) -> __m256 { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3]) } } @@ -27512,7 +27512,7 @@ pub fn _mm256_broadcast_f32x4(a: __m128) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcast_f32x4&expand=481) #[inline] #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcastf32x4, linux: vshu -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_mask_broadcast_f32x4(src: __m256, k: __mmask8, a: __m128) -> __m256 { unsafe { let broadcast = _mm256_broadcast_f32x4(a).as_f32x8(); @@ -27525,7 +27525,7 @@ pub fn _mm256_mask_broadcast_f32x4(src: __m256, k: __mmask8, a: __m128) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcast_f32x4&expand=482) #[inline] #[target_feature(enable = "avx512f,avx512vl")] //msvc: vbroadcastf32x4, linux: vshu -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_maskz_broadcast_f32x4(k: __mmask8, a: __m128) -> __m256 { unsafe { let broadcast = _mm256_broadcast_f32x4(a).as_f32x8(); @@ -27538,7 +27538,7 @@ pub fn _mm256_maskz_broadcast_f32x4(k: __mmask8, a: __m128) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcast_f64x4&expand=495) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vperm -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_broadcast_f64x4(a: __m256d) -> __m512d { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 0, 1, 2, 3]) } } @@ -27548,7 +27548,7 @@ pub fn _mm512_broadcast_f64x4(a: __m256d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcast_f64x4&expand=496) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vper -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_broadcast_f64x4(src: __m512d, k: __mmask8, a: __m256d) -> __m512d { unsafe { let broadcast = _mm512_broadcast_f64x4(a).as_f64x8(); @@ -27561,7 +27561,7 @@ pub fn _mm512_mask_broadcast_f64x4(src: __m512d, k: __mmask8, a: __m256d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcast_f64x4&expand=497) #[inline] #[target_feature(enable = "avx512f")] //msvc: vbroadcastf64x4, linux: vper -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_maskz_broadcast_f64x4(k: __mmask8, a: __m256d) -> __m512d { unsafe { let broadcast = _mm512_broadcast_f64x4(a).as_f64x8(); @@ -27574,7 +27574,7 @@ pub fn _mm512_maskz_broadcast_f64x4(k: __mmask8, a: __m256d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_blend_epi32&expand=435) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] //should be vpblendmd pub fn _mm512_mask_blend_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_select_bitmask(k, b.as_i32x16(), a.as_i32x16())) } @@ -27585,7 +27585,7 @@ pub fn _mm512_mask_blend_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_blend_epi32&expand=434) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] //should be vpblendmd pub fn _mm256_mask_blend_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_select_bitmask(k, b.as_i32x8(), a.as_i32x8())) } @@ -27596,7 +27596,7 @@ pub fn _mm256_mask_blend_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_blend_epi32&expand=432) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa32))] //should be vpblendmd pub fn _mm_mask_blend_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_select_bitmask(k, b.as_i32x4(), a.as_i32x4())) } @@ -27607,7 +27607,7 @@ pub fn _mm_mask_blend_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_blend_epi64&expand=438) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] //should be vpblendmq pub fn _mm512_mask_blend_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_select_bitmask(k, b.as_i64x8(), a.as_i64x8())) } @@ -27618,7 +27618,7 @@ pub fn _mm512_mask_blend_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_blend_epi64&expand=437) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] //should be vpblendmq pub fn _mm256_mask_blend_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_select_bitmask(k, b.as_i64x4(), a.as_i64x4())) } @@ -27629,7 +27629,7 @@ pub fn _mm256_mask_blend_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_blend_epi64&expand=436) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovdqa64))] //should be vpblendmq pub fn _mm_mask_blend_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_select_bitmask(k, b.as_i64x2(), a.as_i64x2())) } @@ -27640,7 +27640,7 @@ pub fn _mm_mask_blend_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_blend_ps&expand=451) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] //should be vpblendmps pub fn _mm512_mask_blend_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { unsafe { transmute(simd_select_bitmask(k, b.as_f32x16(), a.as_f32x16())) } @@ -27651,7 +27651,7 @@ pub fn _mm512_mask_blend_ps(k: __mmask16, a: __m512, b: __m512) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_blend_ps&expand=450) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] //should be vpblendmps pub fn _mm256_mask_blend_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { unsafe { transmute(simd_select_bitmask(k, b.as_f32x8(), a.as_f32x8())) } @@ -27662,7 +27662,7 @@ pub fn _mm256_mask_blend_ps(k: __mmask8, a: __m256, b: __m256) -> __m256 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_blend_ps&expand=448) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovaps))] //should be vpblendmps pub fn _mm_mask_blend_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { transmute(simd_select_bitmask(k, b.as_f32x4(), a.as_f32x4())) } @@ -27673,7 +27673,7 @@ pub fn _mm_mask_blend_ps(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_blend_pd&expand=446) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] //should be vpblendmpd pub fn _mm512_mask_blend_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { unsafe { transmute(simd_select_bitmask(k, b.as_f64x8(), a.as_f64x8())) } @@ -27684,7 +27684,7 @@ pub fn _mm512_mask_blend_pd(k: __mmask8, a: __m512d, b: __m512d) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_blend_pd&expand=445) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] //should be vpblendmpd pub fn _mm256_mask_blend_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { unsafe { transmute(simd_select_bitmask(k, b.as_f64x4(), a.as_f64x4())) } @@ -27695,7 +27695,7 @@ pub fn _mm256_mask_blend_pd(k: __mmask8, a: __m256d, b: __m256d) -> __m256d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_blend_pd&expand=443) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovapd))] //should be vpblendmpd pub fn _mm_mask_blend_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(simd_select_bitmask(k, b.as_f64x2(), a.as_f64x2())) } @@ -27708,7 +27708,7 @@ pub fn _mm_mask_blend_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_alignr_epi32&expand=245) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_alignr_epi32(a: __m512i, b: __m512i) -> __m512i { @@ -27789,7 +27789,7 @@ pub fn _mm512_alignr_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_alignr_epi32&expand=246) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_alignr_epi32( @@ -27810,7 +27810,7 @@ pub fn _mm512_mask_alignr_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_alignr_epi32&expand=247) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_alignr_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { @@ -27828,7 +27828,7 @@ pub fn _mm512_maskz_alignr_epi32(k: __mmask16, a: __m512i, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_alignr_epi32&expand=242) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_alignr_epi32(a: __m256i, b: __m256i) -> __m256i { @@ -27857,7 +27857,7 @@ pub fn _mm256_alignr_epi32(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_alignr_epi32&expand=243) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_alignr_epi32( @@ -27878,7 +27878,7 @@ pub fn _mm256_mask_alignr_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_alignr_epi32&expand=244) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_alignr_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { @@ -27896,7 +27896,7 @@ pub fn _mm256_maskz_alignr_epi32(k: __mmask8, a: __m256i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_alignr_epi32&expand=239) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] //should be valignd #[rustc_legacy_const_generics(2)] pub fn _mm_alignr_epi32(a: __m128i, b: __m128i) -> __m128i { @@ -27921,7 +27921,7 @@ pub fn _mm_alignr_epi32(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_alignr_epi32&expand=240) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_alignr_epi32( @@ -27942,7 +27942,7 @@ pub fn _mm_mask_alignr_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_alignr_epi32&expand=241) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_alignr_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { @@ -27960,7 +27960,7 @@ pub fn _mm_maskz_alignr_epi32(k: __mmask8, a: __m128i, b: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_alignr_epi64&expand=254) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm512_alignr_epi64(a: __m512i, b: __m512i) -> __m512i { @@ -27987,7 +27987,7 @@ pub fn _mm512_alignr_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_alignr_epi64&expand=255) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_alignr_epi64( @@ -28008,7 +28008,7 @@ pub fn _mm512_mask_alignr_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_alignr_epi64&expand=256) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_alignr_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { @@ -28026,7 +28026,7 @@ pub fn _mm512_maskz_alignr_epi64(k: __mmask8, a: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_alignr_epi64&expand=251) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] #[rustc_legacy_const_generics(2)] pub fn _mm256_alignr_epi64(a: __m256i, b: __m256i) -> __m256i { @@ -28049,7 +28049,7 @@ pub fn _mm256_alignr_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_alignr_epi64&expand=252) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_alignr_epi64( @@ -28070,7 +28070,7 @@ pub fn _mm256_mask_alignr_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_alignr_epi64&expand=253) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_alignr_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { @@ -28088,7 +28088,7 @@ pub fn _mm256_maskz_alignr_epi64(k: __mmask8, a: __m256i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_alignr_epi64&expand=248) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] //should be valignq #[rustc_legacy_const_generics(2)] pub fn _mm_alignr_epi64(a: __m128i, b: __m128i) -> __m128i { @@ -28109,7 +28109,7 @@ pub fn _mm_alignr_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_alignr_epi64&expand=249) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_alignr_epi64( @@ -28130,7 +28130,7 @@ pub fn _mm_mask_alignr_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_alignr_epi64&expand=250) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_alignr_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { @@ -28146,7 +28146,7 @@ pub fn _mm_maskz_alignr_epi64(k: __mmask8, a: __m128i, b: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_and_epi32&expand=272) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] //should be vpandd, but generate vpandq pub fn _mm512_and_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_and(a.as_i32x16(), b.as_i32x16())) } @@ -28157,7 +28157,7 @@ pub fn _mm512_and_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_and_epi32&expand=273) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandd))] pub fn _mm512_mask_and_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28171,7 +28171,7 @@ pub fn _mm512_mask_and_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_and_epi32&expand=274) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandd))] pub fn _mm512_maskz_and_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28185,7 +28185,7 @@ pub fn _mm512_maskz_and_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_and_epi32&expand=270) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandd))] pub fn _mm256_mask_and_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28199,7 +28199,7 @@ pub fn _mm256_mask_and_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_and_epi32&expand=271) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandd))] pub fn _mm256_maskz_and_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28213,7 +28213,7 @@ pub fn _mm256_maskz_and_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_and_epi32&expand=268) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandd))] pub fn _mm_mask_and_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28227,7 +28227,7 @@ pub fn _mm_mask_and_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_and_epi32&expand=269) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandd))] pub fn _mm_maskz_and_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28241,7 +28241,7 @@ pub fn _mm_maskz_and_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_and_epi64&expand=279) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm512_and_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_and(a.as_i64x8(), b.as_i64x8())) } @@ -28252,7 +28252,7 @@ pub fn _mm512_and_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_and_epi64&expand=280) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm512_mask_and_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28266,7 +28266,7 @@ pub fn _mm512_mask_and_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_and_epi64&expand=281) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm512_maskz_and_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28280,7 +28280,7 @@ pub fn _mm512_maskz_and_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_and_epi64&expand=277) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm256_mask_and_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28294,7 +28294,7 @@ pub fn _mm256_mask_and_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_and_epi64&expand=278) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm256_maskz_and_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28308,7 +28308,7 @@ pub fn _mm256_maskz_and_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_and_epi64&expand=275) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm_mask_and_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28322,7 +28322,7 @@ pub fn _mm_mask_and_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_and_epi64&expand=276) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm_maskz_and_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28336,7 +28336,7 @@ pub fn _mm_maskz_and_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_and_si512&expand=302) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandq))] pub fn _mm512_and_si512(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_and(a.as_i32x16(), b.as_i32x16())) } @@ -28347,7 +28347,7 @@ pub fn _mm512_and_si512(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_or_epi32&expand=4042) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm512_or_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_or(a.as_i32x16(), b.as_i32x16())) } @@ -28358,7 +28358,7 @@ pub fn _mm512_or_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_or_epi32&expand=4040) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpord))] pub fn _mm512_mask_or_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28372,7 +28372,7 @@ pub fn _mm512_mask_or_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_or_epi32&expand=4041) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpord))] pub fn _mm512_maskz_or_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28386,7 +28386,7 @@ pub fn _mm512_maskz_or_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_or_epi32&expand=4039) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vor))] //should be vpord pub fn _mm256_or_epi32(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_or(a.as_i32x8(), b.as_i32x8())) } @@ -28397,7 +28397,7 @@ pub fn _mm256_or_epi32(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_or_epi32&expand=4037) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpord))] pub fn _mm256_mask_or_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28411,7 +28411,7 @@ pub fn _mm256_mask_or_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_or_epi32&expand=4038) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpord))] pub fn _mm256_maskz_or_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28425,7 +28425,7 @@ pub fn _mm256_maskz_or_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_or_epi32&expand=4036) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vor))] //should be vpord pub fn _mm_or_epi32(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_or(a.as_i32x4(), b.as_i32x4())) } @@ -28436,7 +28436,7 @@ pub fn _mm_or_epi32(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_or_epi32&expand=4034) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpord))] pub fn _mm_mask_or_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28450,7 +28450,7 @@ pub fn _mm_mask_or_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_or_epi32&expand=4035) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpord))] pub fn _mm_maskz_or_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28464,7 +28464,7 @@ pub fn _mm_maskz_or_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_or_epi64&expand=4051) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm512_or_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_or(a.as_i64x8(), b.as_i64x8())) } @@ -28475,7 +28475,7 @@ pub fn _mm512_or_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_or_epi64&expand=4049) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm512_mask_or_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28489,7 +28489,7 @@ pub fn _mm512_mask_or_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_or_epi64&expand=4050) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm512_maskz_or_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28503,7 +28503,7 @@ pub fn _mm512_maskz_or_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_or_epi64&expand=4048) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vor))] //should be vporq pub fn _mm256_or_epi64(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_or(a.as_i64x4(), b.as_i64x4())) } @@ -28514,7 +28514,7 @@ pub fn _mm256_or_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_or_epi64&expand=4046) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm256_mask_or_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28528,7 +28528,7 @@ pub fn _mm256_mask_or_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_or_epi64&expand=4047) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm256_maskz_or_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28542,7 +28542,7 @@ pub fn _mm256_maskz_or_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_or_epi64&expand=4045) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vor))] //should be vporq pub fn _mm_or_epi64(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_or(a.as_i64x2(), b.as_i64x2())) } @@ -28553,7 +28553,7 @@ pub fn _mm_or_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_or_epi64&expand=4043) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm_mask_or_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28567,7 +28567,7 @@ pub fn _mm_mask_or_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_or_epi64&expand=4044) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm_maskz_or_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28581,7 +28581,7 @@ pub fn _mm_maskz_or_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_or_si512&expand=4072) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vporq))] pub fn _mm512_or_si512(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_or(a.as_i32x16(), b.as_i32x16())) } @@ -28592,7 +28592,7 @@ pub fn _mm512_or_si512(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_xor_epi32&expand=6142) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] //should be vpxord pub fn _mm512_xor_epi32(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_xor(a.as_i32x16(), b.as_i32x16())) } @@ -28603,7 +28603,7 @@ pub fn _mm512_xor_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_xor_epi32&expand=6140) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxord))] pub fn _mm512_mask_xor_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28617,7 +28617,7 @@ pub fn _mm512_mask_xor_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_xor_epi32&expand=6141) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxord))] pub fn _mm512_maskz_xor_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28631,7 +28631,7 @@ pub fn _mm512_maskz_xor_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_xor_epi32&expand=6139) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxor))] //should be vpxord pub fn _mm256_xor_epi32(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_xor(a.as_i32x8(), b.as_i32x8())) } @@ -28642,7 +28642,7 @@ pub fn _mm256_xor_epi32(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_xor_epi32&expand=6137) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxord))] pub fn _mm256_mask_xor_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28656,7 +28656,7 @@ pub fn _mm256_mask_xor_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_xor_epi32&expand=6138) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxord))] pub fn _mm256_maskz_xor_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28670,7 +28670,7 @@ pub fn _mm256_maskz_xor_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_xor_epi32&expand=6136) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxor))] //should be vpxord pub fn _mm_xor_epi32(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_xor(a.as_i32x4(), b.as_i32x4())) } @@ -28681,7 +28681,7 @@ pub fn _mm_xor_epi32(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_xor_epi32&expand=6134) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxord))] pub fn _mm_mask_xor_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28695,7 +28695,7 @@ pub fn _mm_mask_xor_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_xor_epi32&expand=6135) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxord))] pub fn _mm_maskz_xor_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28709,7 +28709,7 @@ pub fn _mm_maskz_xor_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_xor_epi64&expand=6151) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] pub fn _mm512_xor_epi64(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_xor(a.as_i64x8(), b.as_i64x8())) } @@ -28720,7 +28720,7 @@ pub fn _mm512_xor_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_xor_epi64&expand=6149) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] pub fn _mm512_mask_xor_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28734,7 +28734,7 @@ pub fn _mm512_mask_xor_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_xor_epi64&expand=6150) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] pub fn _mm512_maskz_xor_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28748,7 +28748,7 @@ pub fn _mm512_maskz_xor_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_xor_epi64&expand=6148) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxor))] //should be vpxorq pub fn _mm256_xor_epi64(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(simd_xor(a.as_i64x4(), b.as_i64x4())) } @@ -28759,7 +28759,7 @@ pub fn _mm256_xor_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_xor_epi64&expand=6146) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] pub fn _mm256_mask_xor_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28773,7 +28773,7 @@ pub fn _mm256_mask_xor_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_xor_epi64&expand=6147) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] pub fn _mm256_maskz_xor_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28787,7 +28787,7 @@ pub fn _mm256_maskz_xor_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_xor_epi64&expand=6145) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vxor))] //should be vpxorq pub fn _mm_xor_epi64(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(simd_xor(a.as_i64x2(), b.as_i64x2())) } @@ -28798,7 +28798,7 @@ pub fn _mm_xor_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_xor_epi64&expand=6143) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] pub fn _mm_mask_xor_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28812,7 +28812,7 @@ pub fn _mm_mask_xor_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_xor_epi64&expand=6144) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] pub fn _mm_maskz_xor_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28826,7 +28826,7 @@ pub fn _mm_maskz_xor_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_xor_si512&expand=6172) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpxorq))] pub fn _mm512_xor_si512(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(simd_xor(a.as_i32x16(), b.as_i32x16())) } @@ -28837,7 +28837,7 @@ pub fn _mm512_xor_si512(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_andnot_epi32&expand=310) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] //should be vpandnd pub fn _mm512_andnot_epi32(a: __m512i, b: __m512i) -> __m512i { _mm512_and_epi32(_mm512_xor_epi32(a, _mm512_set1_epi32(u32::MAX as i32)), b) @@ -28848,7 +28848,7 @@ pub fn _mm512_andnot_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_andnot_epi32&expand=311) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnd))] pub fn _mm512_mask_andnot_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28862,7 +28862,7 @@ pub fn _mm512_mask_andnot_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_andnot_epi32&expand=312) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnd))] pub fn _mm512_maskz_andnot_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28876,7 +28876,7 @@ pub fn _mm512_maskz_andnot_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_andnot_epi32&expand=308) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnd))] pub fn _mm256_mask_andnot_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28891,7 +28891,7 @@ pub fn _mm256_mask_andnot_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_andnot_epi32&expand=309) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnd))] pub fn _mm256_maskz_andnot_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28906,7 +28906,7 @@ pub fn _mm256_maskz_andnot_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_andnot_epi32&expand=306) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnd))] pub fn _mm_mask_andnot_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28921,7 +28921,7 @@ pub fn _mm_mask_andnot_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_andnot_epi32&expand=307) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnd))] pub fn _mm_maskz_andnot_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -28936,7 +28936,7 @@ pub fn _mm_maskz_andnot_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_andnot_epi64&expand=317) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] //should be vpandnd pub fn _mm512_andnot_epi64(a: __m512i, b: __m512i) -> __m512i { _mm512_and_epi64(_mm512_xor_epi64(a, _mm512_set1_epi64(u64::MAX as i64)), b) @@ -28947,7 +28947,7 @@ pub fn _mm512_andnot_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_andnot_epi64&expand=318) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] pub fn _mm512_mask_andnot_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28961,7 +28961,7 @@ pub fn _mm512_mask_andnot_epi64(src: __m512i, k: __mmask8, a: __m512i, b: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_andnot_epi64&expand=319) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] pub fn _mm512_maskz_andnot_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -28975,7 +28975,7 @@ pub fn _mm512_maskz_andnot_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_andnot_epi64&expand=315) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] pub fn _mm256_mask_andnot_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -28990,7 +28990,7 @@ pub fn _mm256_mask_andnot_epi64(src: __m256i, k: __mmask8, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_andnot_epi64&expand=316) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] pub fn _mm256_maskz_andnot_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -29005,7 +29005,7 @@ pub fn _mm256_maskz_andnot_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_andnot_epi64&expand=313) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] pub fn _mm_mask_andnot_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -29020,7 +29020,7 @@ pub fn _mm_mask_andnot_epi64(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_andnot_epi64&expand=314) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] pub fn _mm_maskz_andnot_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -29035,7 +29035,7 @@ pub fn _mm_maskz_andnot_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_andnot_si512&expand=340) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpandnq))] pub fn _mm512_andnot_si512(a: __m512i, b: __m512i) -> __m512i { _mm512_and_epi64(_mm512_xor_epi64(a, _mm512_set1_epi64(u64::MAX as i64)), b) @@ -29046,7 +29046,7 @@ pub fn _mm512_andnot_si512(a: __m512i, b: __m512i) -> __m512i { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtmask16_u32) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _cvtmask16_u32(a: __mmask16) -> u32 { a as u32 } @@ -29056,7 +29056,7 @@ pub fn _cvtmask16_u32(a: __mmask16) -> u32 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtu32_mask16) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _cvtu32_mask16(a: u32) -> __mmask16 { a as __mmask16 } @@ -29066,7 +29066,7 @@ pub fn _cvtu32_mask16(a: u32) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=kand_mask16&expand=3212) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(and))] // generate normal and code instead of kandw pub fn _kand_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { a & b @@ -29077,7 +29077,7 @@ pub fn _kand_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kand&expand=3210) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(and))] // generate normal and code instead of kandw pub fn _mm512_kand(a: __mmask16, b: __mmask16) -> __mmask16 { a & b @@ -29088,7 +29088,7 @@ pub fn _mm512_kand(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=kor_mask16&expand=3239) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(or))] // generate normal or code instead of korw pub fn _kor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { a | b @@ -29099,7 +29099,7 @@ pub fn _kor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kor&expand=3237) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(or))] // generate normal or code instead of korw pub fn _mm512_kor(a: __mmask16, b: __mmask16) -> __mmask16 { a | b @@ -29110,7 +29110,7 @@ pub fn _mm512_kor(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=kxor_mask16&expand=3291) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(xor))] // generate normal xor code instead of kxorw pub fn _kxor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { a ^ b @@ -29121,7 +29121,7 @@ pub fn _kxor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kxor&expand=3289) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(xor))] // generate normal xor code instead of kxorw pub fn _mm512_kxor(a: __mmask16, b: __mmask16) -> __mmask16 { a ^ b @@ -29132,7 +29132,7 @@ pub fn _mm512_kxor(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=knot_mask16&expand=3233) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _knot_mask16(a: __mmask16) -> __mmask16 { a ^ 0b11111111_11111111 } @@ -29142,7 +29142,7 @@ pub fn _knot_mask16(a: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_knot&expand=3231) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_knot(a: __mmask16) -> __mmask16 { a ^ 0b11111111_11111111 } @@ -29152,7 +29152,7 @@ pub fn _mm512_knot(a: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=kandn_mask16&expand=3218) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(not))] // generate normal and, not code instead of kandnw pub fn _kandn_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { _mm512_kand(_mm512_knot(a), b) @@ -29163,7 +29163,7 @@ pub fn _kandn_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kandn&expand=3216) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(not))] // generate normal and code instead of kandw pub fn _mm512_kandn(a: __mmask16, b: __mmask16) -> __mmask16 { _mm512_kand(_mm512_knot(a), b) @@ -29174,7 +29174,7 @@ pub fn _mm512_kandn(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=kxnor_mask16&expand=3285) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(xor))] // generate normal xor, not code instead of kxnorw pub fn _kxnor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { _mm512_knot(_mm512_kxor(a, b)) @@ -29185,7 +29185,7 @@ pub fn _kxnor_mask16(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kxnor&expand=3283) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(xor))] // generate normal and code instead of kandw pub fn _mm512_kxnor(a: __mmask16, b: __mmask16) -> __mmask16 { _mm512_knot(_mm512_kxor(a, b)) @@ -29197,7 +29197,7 @@ pub fn _mm512_kxnor(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortest_mask16_u8) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _kortest_mask16_u8(a: __mmask16, b: __mmask16, all_ones: *mut u8) -> u8 { let tmp = _kor_mask16(a, b); *all_ones = (tmp == 0xffff) as u8; @@ -29210,7 +29210,7 @@ pub unsafe fn _kortest_mask16_u8(a: __mmask16, b: __mmask16, all_ones: *mut u8) /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortestc_mask16_u8) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kortestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 { (_kor_mask16(a, b) == 0xffff) as u8 } @@ -29221,7 +29221,7 @@ pub fn _kortestc_mask16_u8(a: __mmask16, b: __mmask16) -> u8 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kortestz_mask16_u8) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kortestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 { (_kor_mask16(a, b) == 0) as u8 } @@ -29232,7 +29232,7 @@ pub fn _kortestz_mask16_u8(a: __mmask16, b: __mmask16) -> u8 { #[inline] #[target_feature(enable = "avx512f")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kshiftli_mask16(a: __mmask16) -> __mmask16 { a << COUNT } @@ -29243,7 +29243,7 @@ pub fn _kshiftli_mask16(a: __mmask16) -> __mmask16 { #[inline] #[target_feature(enable = "avx512f")] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _kshiftri_mask16(a: __mmask16) -> __mmask16 { a >> COUNT } @@ -29253,7 +29253,7 @@ pub fn _kshiftri_mask16(a: __mmask16) -> __mmask16 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_load_mask16) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _load_mask16(mem_addr: *const __mmask16) -> __mmask16 { *mem_addr } @@ -29263,7 +29263,7 @@ pub unsafe fn _load_mask16(mem_addr: *const __mmask16) -> __mmask16 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_store_mask16) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _store_mask16(mem_addr: *mut __mmask16, a: __mmask16) { *mem_addr = a; } @@ -29273,7 +29273,7 @@ pub unsafe fn _store_mask16(mem_addr: *mut __mmask16, a: __mmask16) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm512_kmov&expand=3228) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kmovw pub fn _mm512_kmov(a: __mmask16) -> __mmask16 { a @@ -29284,7 +29284,7 @@ pub fn _mm512_kmov(a: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_int2mask&expand=3189) #[inline] #[target_feature(enable = "avx512f")] // generate normal and code instead of kmovw -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_int2mask(mask: i32) -> __mmask16 { mask as u16 } @@ -29294,7 +29294,7 @@ pub fn _mm512_int2mask(mask: i32) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask2int&expand=3544) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kmovw pub fn _mm512_mask2int(k1: __mmask16) -> i32 { k1 as i32 @@ -29305,7 +29305,7 @@ pub fn _mm512_mask2int(k1: __mmask16) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kunpackb&expand=3280) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(mov))] // generate normal and code instead of kunpckbw pub fn _mm512_kunpackb(a: __mmask16, b: __mmask16) -> __mmask16 { ((a & 0xff) << 8) | (b & 0xff) @@ -29316,7 +29316,7 @@ pub fn _mm512_kunpackb(a: __mmask16, b: __mmask16) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kortestc&expand=3247) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(cmp))] // generate normal and code instead of kortestw pub fn _mm512_kortestc(a: __mmask16, b: __mmask16) -> i32 { let r = (a | b) == 0b11111111_11111111; @@ -29328,7 +29328,7 @@ pub fn _mm512_kortestc(a: __mmask16, b: __mmask16) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_kortestz) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(xor))] // generate normal and code instead of kortestw pub fn _mm512_kortestz(a: __mmask16, b: __mmask16) -> i32 { let r = (a | b) == 0; @@ -29340,7 +29340,7 @@ pub fn _mm512_kortestz(a: __mmask16, b: __mmask16) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_test_epi32_mask&expand=5890) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmd))] pub fn _mm512_test_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { let and = _mm512_and_epi32(a, b); @@ -29353,7 +29353,7 @@ pub fn _mm512_test_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_test_epi32_mask&expand=5889) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmd))] pub fn _mm512_mask_test_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { let and = _mm512_and_epi32(a, b); @@ -29366,7 +29366,7 @@ pub fn _mm512_mask_test_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_test_epi32_mask&expand=5888) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmd))] pub fn _mm256_test_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { let and = _mm256_and_si256(a, b); @@ -29379,7 +29379,7 @@ pub fn _mm256_test_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_test_epi32_mask&expand=5887) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmd))] pub fn _mm256_mask_test_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { let and = _mm256_and_si256(a, b); @@ -29392,7 +29392,7 @@ pub fn _mm256_mask_test_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_test_epi32_mask&expand=5886) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmd))] pub fn _mm_test_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -29405,7 +29405,7 @@ pub fn _mm_test_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_test_epi32_mask&expand=5885) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmd))] pub fn _mm_mask_test_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -29418,7 +29418,7 @@ pub fn _mm_mask_test_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_test_epi64_mask&expand=5896) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmq))] pub fn _mm512_test_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { let and = _mm512_and_epi64(a, b); @@ -29431,7 +29431,7 @@ pub fn _mm512_test_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_test_epi64_mask&expand=5895) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmq))] pub fn _mm512_mask_test_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { let and = _mm512_and_epi64(a, b); @@ -29444,7 +29444,7 @@ pub fn _mm512_mask_test_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_test_epi64_mask&expand=5894) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmq))] pub fn _mm256_test_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { let and = _mm256_and_si256(a, b); @@ -29457,7 +29457,7 @@ pub fn _mm256_test_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_test_epi64_mask&expand=5893) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmq))] pub fn _mm256_mask_test_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { let and = _mm256_and_si256(a, b); @@ -29470,7 +29470,7 @@ pub fn _mm256_mask_test_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_test_epi64_mask&expand=5892) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmq))] pub fn _mm_test_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -29483,7 +29483,7 @@ pub fn _mm_test_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_test_epi64_mask&expand=5891) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestmq))] pub fn _mm_mask_test_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -29496,7 +29496,7 @@ pub fn _mm_mask_test_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_testn_epi32_mask&expand=5921) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmd))] pub fn _mm512_testn_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { let and = _mm512_and_epi32(a, b); @@ -29509,7 +29509,7 @@ pub fn _mm512_testn_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_testn_epi32_mask&expand=5920) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmd))] pub fn _mm512_mask_testn_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { let and = _mm512_and_epi32(a, b); @@ -29522,7 +29522,7 @@ pub fn _mm512_mask_testn_epi32_mask(k: __mmask16, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testn_epi32_mask&expand=5919) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmd))] pub fn _mm256_testn_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { let and = _mm256_and_si256(a, b); @@ -29535,7 +29535,7 @@ pub fn _mm256_testn_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_testn_epi32_mask&expand=5918) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmd))] pub fn _mm256_mask_testn_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { let and = _mm256_and_si256(a, b); @@ -29548,7 +29548,7 @@ pub fn _mm256_mask_testn_epi32_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_testn_epi32_mask&expand=5917) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmd))] pub fn _mm_testn_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -29561,7 +29561,7 @@ pub fn _mm_testn_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_testn_epi32_mask&expand=5916) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmd))] pub fn _mm_mask_testn_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -29574,7 +29574,7 @@ pub fn _mm_mask_testn_epi32_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_testn_epi64_mask&expand=5927) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmq))] pub fn _mm512_testn_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { let and = _mm512_and_epi64(a, b); @@ -29587,7 +29587,7 @@ pub fn _mm512_testn_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_testn_epi64_mask&expand=5926) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmq))] pub fn _mm512_mask_testn_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { let and = _mm512_and_epi64(a, b); @@ -29600,7 +29600,7 @@ pub fn _mm512_mask_testn_epi64_mask(k: __mmask8, a: __m512i, b: __m512i) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testn_epi64_mask&expand=5925) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmq))] pub fn _mm256_testn_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { let and = _mm256_and_si256(a, b); @@ -29613,7 +29613,7 @@ pub fn _mm256_testn_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_testn_epi64_mask&expand=5924) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmq))] pub fn _mm256_mask_testn_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { let and = _mm256_and_si256(a, b); @@ -29626,7 +29626,7 @@ pub fn _mm256_mask_testn_epi64_mask(k: __mmask8, a: __m256i, b: __m256i) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_testn_epi64_mask&expand=5923) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmq))] pub fn _mm_testn_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -29639,7 +29639,7 @@ pub fn _mm_testn_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_testn_epi64_mask&expand=5922) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vptestnmq))] pub fn _mm_mask_testn_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { let and = _mm_and_si128(a, b); @@ -29661,7 +29661,7 @@ pub fn _mm_mask_testn_epi64_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask /// See [`_mm_sfence`] for details. #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovntps))] #[allow(clippy::cast_ptr_alignment)] pub unsafe fn _mm512_stream_ps(mem_addr: *mut f32, a: __m512) { @@ -29687,7 +29687,7 @@ pub unsafe fn _mm512_stream_ps(mem_addr: *mut f32, a: __m512) { /// See [`_mm_sfence`] for details. #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovntpd))] #[allow(clippy::cast_ptr_alignment)] pub unsafe fn _mm512_stream_pd(mem_addr: *mut f64, a: __m512d) { @@ -29713,7 +29713,7 @@ pub unsafe fn _mm512_stream_pd(mem_addr: *mut f64, a: __m512d) { /// See [`_mm_sfence`] for details. #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovntdq))] #[allow(clippy::cast_ptr_alignment)] pub unsafe fn _mm512_stream_si512(mem_addr: *mut __m512i, a: __m512i) { @@ -29732,7 +29732,7 @@ pub unsafe fn _mm512_stream_si512(mem_addr: *mut __m512i, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_stream_load_si512) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_stream_load_si512(mem_addr: *const __m512i) -> __m512i { let dst: __m512i; crate::arch::asm!( @@ -29749,7 +29749,7 @@ pub unsafe fn _mm512_stream_load_si512(mem_addr: *const __m512i) -> __m512i { /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set_ps&expand=4931) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set_ps( e0: f32, e1: f32, @@ -29779,7 +29779,7 @@ pub fn _mm512_set_ps( /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setr_ps&expand=5008) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_setr_ps( e0: f32, e1: f32, @@ -29811,7 +29811,7 @@ pub fn _mm512_setr_ps( /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set1_pd&expand=4975) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set1_pd(a: f64) -> __m512d { unsafe { transmute(f64x8::splat(a)) } } @@ -29821,7 +29821,7 @@ pub fn _mm512_set1_pd(a: f64) -> __m512d { /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set1_ps&expand=4981) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set1_ps(a: f32) -> __m512 { unsafe { transmute(f32x16::splat(a)) } } @@ -29831,7 +29831,7 @@ pub fn _mm512_set1_ps(a: f32) -> __m512 { /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set_epi32&expand=4908) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set_epi32( e15: i32, e14: i32, @@ -29860,7 +29860,7 @@ pub fn _mm512_set_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set1_epi8&expand=4972) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set1_epi8(a: i8) -> __m512i { unsafe { transmute(i8x64::splat(a)) } } @@ -29870,7 +29870,7 @@ pub fn _mm512_set1_epi8(a: i8) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set1_epi16&expand=4944) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set1_epi16(a: i16) -> __m512i { unsafe { transmute(i16x32::splat(a)) } } @@ -29880,7 +29880,7 @@ pub fn _mm512_set1_epi16(a: i16) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_set1_epi32) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set1_epi32(a: i32) -> __m512i { unsafe { transmute(i32x16::splat(a)) } } @@ -29890,7 +29890,7 @@ pub fn _mm512_set1_epi32(a: i32) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_set1_epi32&expand=4951) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastd))] pub fn _mm512_mask_set1_epi32(src: __m512i, k: __mmask16, a: i32) -> __m512i { unsafe { @@ -29904,7 +29904,7 @@ pub fn _mm512_mask_set1_epi32(src: __m512i, k: __mmask16, a: i32) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_set1_epi32&expand=4952) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastd))] pub fn _mm512_maskz_set1_epi32(k: __mmask16, a: i32) -> __m512i { unsafe { @@ -29918,7 +29918,7 @@ pub fn _mm512_maskz_set1_epi32(k: __mmask16, a: i32) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_set1_epi32&expand=4948) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastd))] pub fn _mm256_mask_set1_epi32(src: __m256i, k: __mmask8, a: i32) -> __m256i { unsafe { @@ -29932,7 +29932,7 @@ pub fn _mm256_mask_set1_epi32(src: __m256i, k: __mmask8, a: i32) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_set1_epi32&expand=4949) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastd))] pub fn _mm256_maskz_set1_epi32(k: __mmask8, a: i32) -> __m256i { unsafe { @@ -29946,7 +29946,7 @@ pub fn _mm256_maskz_set1_epi32(k: __mmask8, a: i32) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_set1_epi32&expand=4945) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastd))] pub fn _mm_mask_set1_epi32(src: __m128i, k: __mmask8, a: i32) -> __m128i { unsafe { @@ -29960,7 +29960,7 @@ pub fn _mm_mask_set1_epi32(src: __m128i, k: __mmask8, a: i32) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_set1_epi32&expand=4946) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastd))] pub fn _mm_maskz_set1_epi32(k: __mmask8, a: i32) -> __m128i { unsafe { @@ -29974,7 +29974,7 @@ pub fn _mm_maskz_set1_epi32(k: __mmask8, a: i32) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set1_epi64&expand=4961) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set1_epi64(a: i64) -> __m512i { unsafe { transmute(i64x8::splat(a)) } } @@ -29984,7 +29984,7 @@ pub fn _mm512_set1_epi64(a: i64) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_set1_epi64&expand=4959) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastq))] pub fn _mm512_mask_set1_epi64(src: __m512i, k: __mmask8, a: i64) -> __m512i { unsafe { @@ -29998,7 +29998,7 @@ pub fn _mm512_mask_set1_epi64(src: __m512i, k: __mmask8, a: i64) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_set1_epi64&expand=4960) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastq))] pub fn _mm512_maskz_set1_epi64(k: __mmask8, a: i64) -> __m512i { unsafe { @@ -30012,7 +30012,7 @@ pub fn _mm512_maskz_set1_epi64(k: __mmask8, a: i64) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_set1_epi64&expand=4957) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastq))] pub fn _mm256_mask_set1_epi64(src: __m256i, k: __mmask8, a: i64) -> __m256i { unsafe { @@ -30026,7 +30026,7 @@ pub fn _mm256_mask_set1_epi64(src: __m256i, k: __mmask8, a: i64) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_set1_epi64&expand=4958) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastq))] pub fn _mm256_maskz_set1_epi64(k: __mmask8, a: i64) -> __m256i { unsafe { @@ -30040,7 +30040,7 @@ pub fn _mm256_maskz_set1_epi64(k: __mmask8, a: i64) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_set1_epi64&expand=4954) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastq))] pub fn _mm_mask_set1_epi64(src: __m128i, k: __mmask8, a: i64) -> __m128i { unsafe { @@ -30054,7 +30054,7 @@ pub fn _mm_mask_set1_epi64(src: __m128i, k: __mmask8, a: i64) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_set1_epi64&expand=4955) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpbroadcastq))] pub fn _mm_maskz_set1_epi64(k: __mmask8, a: i64) -> __m128i { unsafe { @@ -30068,7 +30068,7 @@ pub fn _mm_maskz_set1_epi64(k: __mmask8, a: i64) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set4_epi64&expand=4983) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i { _mm512_set_epi64(d, c, b, a, d, c, b, a) } @@ -30078,7 +30078,7 @@ pub fn _mm512_set4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setr4_epi64&expand=5010) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_setr4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i { _mm512_set_epi64(a, b, c, d, a, b, c, d) } @@ -30088,7 +30088,7 @@ pub fn _mm512_setr4_epi64(d: i64, c: i64, b: i64, a: i64) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_ps_mask&expand=1074) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_cmplt_ps_mask(a: __m512, b: __m512) -> __mmask16 { _mm512_cmp_ps_mask::<_CMP_LT_OS>(a, b) @@ -30099,7 +30099,7 @@ pub fn _mm512_cmplt_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_ps_mask&expand=1075) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_mask_cmplt_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { _mm512_mask_cmp_ps_mask::<_CMP_LT_OS>(k1, a, b) @@ -30110,7 +30110,7 @@ pub fn _mm512_mask_cmplt_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpnlt_ps_mask&expand=1154) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_cmpnlt_ps_mask(a: __m512, b: __m512) -> __mmask16 { _mm512_cmp_ps_mask::<_CMP_NLT_US>(a, b) @@ -30121,7 +30121,7 @@ pub fn _mm512_cmpnlt_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpnlt_ps_mask&expand=1155) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_mask_cmpnlt_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { _mm512_mask_cmp_ps_mask::<_CMP_NLT_US>(k1, a, b) @@ -30132,7 +30132,7 @@ pub fn _mm512_mask_cmpnlt_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_ps_mask&expand=1013) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_cmple_ps_mask(a: __m512, b: __m512) -> __mmask16 { _mm512_cmp_ps_mask::<_CMP_LE_OS>(a, b) @@ -30143,7 +30143,7 @@ pub fn _mm512_cmple_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_ps_mask&expand=1014) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_mask_cmple_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { _mm512_mask_cmp_ps_mask::<_CMP_LE_OS>(k1, a, b) @@ -30154,7 +30154,7 @@ pub fn _mm512_mask_cmple_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpnle_ps_mask&expand=1146) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_cmpnle_ps_mask(a: __m512, b: __m512) -> __mmask16 { _mm512_cmp_ps_mask::<_CMP_NLE_US>(a, b) @@ -30165,7 +30165,7 @@ pub fn _mm512_cmpnle_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpnle_ps_mask&expand=1147) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_mask_cmpnle_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { _mm512_mask_cmp_ps_mask::<_CMP_NLE_US>(k1, a, b) @@ -30176,7 +30176,7 @@ pub fn _mm512_mask_cmpnle_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_ps_mask&expand=828) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_cmpeq_ps_mask(a: __m512, b: __m512) -> __mmask16 { _mm512_cmp_ps_mask::<_CMP_EQ_OQ>(a, b) @@ -30187,7 +30187,7 @@ pub fn _mm512_cmpeq_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_ps_mask&expand=829) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_mask_cmpeq_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { _mm512_mask_cmp_ps_mask::<_CMP_EQ_OQ>(k1, a, b) @@ -30198,7 +30198,7 @@ pub fn _mm512_mask_cmpeq_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_ps_mask&expand=1130) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_cmpneq_ps_mask(a: __m512, b: __m512) -> __mmask16 { _mm512_cmp_ps_mask::<_CMP_NEQ_UQ>(a, b) @@ -30209,7 +30209,7 @@ pub fn _mm512_cmpneq_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_ps_mask&expand=1131) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_mask_cmpneq_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { _mm512_mask_cmp_ps_mask::<_CMP_NEQ_UQ>(k1, a, b) @@ -30220,7 +30220,7 @@ pub fn _mm512_mask_cmpneq_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_ps_mask&expand=749) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm512_cmp_ps_mask(a: __m512, b: __m512) -> __mmask16 { @@ -30239,7 +30239,7 @@ pub fn _mm512_cmp_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_ps_mask&expand=750) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm512_mask_cmp_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { @@ -30257,7 +30257,7 @@ pub fn _mm512_mask_cmp_ps_mask(k1: __mmask16, a: __m512, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_ps_mask&expand=747) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm256_cmp_ps_mask(a: __m256, b: __m256) -> __mmask8 { @@ -30276,7 +30276,7 @@ pub fn _mm256_cmp_ps_mask(a: __m256, b: __m256) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_ps_mask&expand=748) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm256_mask_cmp_ps_mask(k1: __mmask8, a: __m256, b: __m256) -> __mmask8 { @@ -30294,7 +30294,7 @@ pub fn _mm256_mask_cmp_ps_mask(k1: __mmask8, a: __m256, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_ps_mask&expand=745) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm_cmp_ps_mask(a: __m128, b: __m128) -> __mmask8 { @@ -30313,7 +30313,7 @@ pub fn _mm_cmp_ps_mask(a: __m128, b: __m128) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_ps_mask&expand=746) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm_mask_cmp_ps_mask(k1: __mmask8, a: __m128, b: __m128) -> __mmask8 { @@ -30332,7 +30332,7 @@ pub fn _mm_mask_cmp_ps_mask(k1: __mmask8, a: __m128, b: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_round_ps_mask&expand=753) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm512_cmp_round_ps_mask( @@ -30356,7 +30356,7 @@ pub fn _mm512_cmp_round_ps_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_round_ps_mask&expand=754) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm512_mask_cmp_round_ps_mask( @@ -30379,7 +30379,7 @@ pub fn _mm512_mask_cmp_round_ps_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpord_ps_mask&expand=1162) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmps pub fn _mm512_cmpord_ps_mask(a: __m512, b: __m512) -> __mmask16 { _mm512_cmp_ps_mask::<_CMP_ORD_Q>(a, b) @@ -30390,7 +30390,7 @@ pub fn _mm512_cmpord_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpord_ps_mask&expand=1163) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_mask_cmpord_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { _mm512_mask_cmp_ps_mask::<_CMP_ORD_Q>(k1, a, b) @@ -30401,7 +30401,7 @@ pub fn _mm512_mask_cmpord_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpunord_ps_mask&expand=1170) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_cmpunord_ps_mask(a: __m512, b: __m512) -> __mmask16 { _mm512_cmp_ps_mask::<_CMP_UNORD_Q>(a, b) @@ -30412,7 +30412,7 @@ pub fn _mm512_cmpunord_ps_mask(a: __m512, b: __m512) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpunord_ps_mask&expand=1171) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmpps pub fn _mm512_mask_cmpunord_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mmask16 { _mm512_mask_cmp_ps_mask::<_CMP_UNORD_Q>(k1, a, b) @@ -30423,7 +30423,7 @@ pub fn _mm512_mask_cmpunord_ps_mask(k1: __mmask16, a: __m512, b: __m512) -> __mm /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_pd_mask&expand=1071) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_cmplt_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { _mm512_cmp_pd_mask::<_CMP_LT_OS>(a, b) @@ -30434,7 +30434,7 @@ pub fn _mm512_cmplt_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_pd_mask&expand=1072) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_mask_cmplt_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { _mm512_mask_cmp_pd_mask::<_CMP_LT_OS>(k1, a, b) @@ -30445,7 +30445,7 @@ pub fn _mm512_mask_cmplt_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpnlt_pd_mask&expand=1151) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_cmpnlt_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { _mm512_cmp_pd_mask::<_CMP_NLT_US>(a, b) @@ -30456,7 +30456,7 @@ pub fn _mm512_cmpnlt_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpnlt_pd_mask&expand=1152) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_mask_cmpnlt_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { _mm512_mask_cmp_pd_mask::<_CMP_NLT_US>(m, a, b) @@ -30467,7 +30467,7 @@ pub fn _mm512_mask_cmpnlt_pd_mask(m: __mmask8, a: __m512d, b: __m512d) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_pd_mask&expand=1010) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_cmple_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { _mm512_cmp_pd_mask::<_CMP_LE_OS>(a, b) @@ -30478,7 +30478,7 @@ pub fn _mm512_cmple_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_pd_mask&expand=1011) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_mask_cmple_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { _mm512_mask_cmp_pd_mask::<_CMP_LE_OS>(k1, a, b) @@ -30489,7 +30489,7 @@ pub fn _mm512_mask_cmple_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpnle_pd_mask&expand=1143) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_cmpnle_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { _mm512_cmp_pd_mask::<_CMP_NLE_US>(a, b) @@ -30500,7 +30500,7 @@ pub fn _mm512_cmpnle_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpnle_pd_mask&expand=1144) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_mask_cmpnle_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { _mm512_mask_cmp_pd_mask::<_CMP_NLE_US>(k1, a, b) @@ -30511,7 +30511,7 @@ pub fn _mm512_mask_cmpnle_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_pd_mask&expand=822) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_cmpeq_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { _mm512_cmp_pd_mask::<_CMP_EQ_OQ>(a, b) @@ -30522,7 +30522,7 @@ pub fn _mm512_cmpeq_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_pd_mask&expand=823) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_mask_cmpeq_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { _mm512_mask_cmp_pd_mask::<_CMP_EQ_OQ>(k1, a, b) @@ -30533,7 +30533,7 @@ pub fn _mm512_mask_cmpeq_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_pd_mask&expand=1127) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_cmpneq_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { _mm512_cmp_pd_mask::<_CMP_NEQ_UQ>(a, b) @@ -30544,7 +30544,7 @@ pub fn _mm512_cmpneq_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_pd_mask&expand=1128) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_mask_cmpneq_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { _mm512_mask_cmp_pd_mask::<_CMP_NEQ_UQ>(k1, a, b) @@ -30555,7 +30555,7 @@ pub fn _mm512_mask_cmpneq_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_pd_mask&expand=741) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm512_cmp_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { @@ -30574,7 +30574,7 @@ pub fn _mm512_cmp_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_pd_mask&expand=742) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm512_mask_cmp_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { @@ -30592,7 +30592,7 @@ pub fn _mm512_mask_cmp_pd_mask(k1: __mmask8, a: __m512d, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_pd_mask&expand=739) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm256_cmp_pd_mask(a: __m256d, b: __m256d) -> __mmask8 { @@ -30611,7 +30611,7 @@ pub fn _mm256_cmp_pd_mask(a: __m256d, b: __m256d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_pd_mask&expand=740) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm256_mask_cmp_pd_mask(k1: __mmask8, a: __m256d, b: __m256d) -> __mmask8 { @@ -30629,7 +30629,7 @@ pub fn _mm256_mask_cmp_pd_mask(k1: __mmask8, a: __m256d, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_pd_mask&expand=737) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm_cmp_pd_mask(a: __m128d, b: __m128d) -> __mmask8 { @@ -30648,7 +30648,7 @@ pub fn _mm_cmp_pd_mask(a: __m128d, b: __m128d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_pd_mask&expand=738) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm_mask_cmp_pd_mask(k1: __mmask8, a: __m128d, b: __m128d) -> __mmask8 { @@ -30667,7 +30667,7 @@ pub fn _mm_mask_cmp_pd_mask(k1: __mmask8, a: __m128d, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_round_pd_mask&expand=751) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm512_cmp_round_pd_mask( @@ -30691,7 +30691,7 @@ pub fn _mm512_cmp_round_pd_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_round_pd_mask&expand=752) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm512_mask_cmp_round_pd_mask( @@ -30714,7 +30714,7 @@ pub fn _mm512_mask_cmp_round_pd_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpord_pd_mask&expand=1159) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_cmpord_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { _mm512_cmp_pd_mask::<_CMP_ORD_Q>(a, b) @@ -30725,7 +30725,7 @@ pub fn _mm512_cmpord_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpord_pd_mask&expand=1160) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_mask_cmpord_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { _mm512_mask_cmp_pd_mask::<_CMP_ORD_Q>(k1, a, b) @@ -30736,7 +30736,7 @@ pub fn _mm512_mask_cmpord_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpunord_pd_mask&expand=1167) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_cmpunord_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { _mm512_cmp_pd_mask::<_CMP_UNORD_Q>(a, b) @@ -30747,7 +30747,7 @@ pub fn _mm512_cmpunord_pd_mask(a: __m512d, b: __m512d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpunord_pd_mask&expand=1168) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp))] //should be vcmppd pub fn _mm512_mask_cmpunord_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __mmask8 { _mm512_mask_cmp_pd_mask::<_CMP_UNORD_Q>(k1, a, b) @@ -30758,7 +30758,7 @@ pub fn _mm512_mask_cmpunord_pd_mask(k1: __mmask8, a: __m512d, b: __m512d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_ss_mask&expand=763) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm_cmp_ss_mask(a: __m128, b: __m128) -> __mmask8 { @@ -30775,7 +30775,7 @@ pub fn _mm_cmp_ss_mask(a: __m128, b: __m128) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_ss_mask&expand=764) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm_mask_cmp_ss_mask(k1: __mmask8, a: __m128, b: __m128) -> __mmask8 { @@ -30792,7 +30792,7 @@ pub fn _mm_mask_cmp_ss_mask(k1: __mmask8, a: __m128, b: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_round_ss_mask&expand=757) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm_cmp_round_ss_mask(a: __m128, b: __m128) -> __mmask8 { @@ -30811,7 +30811,7 @@ pub fn _mm_cmp_round_ss_mask(a: __m128, b: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_round_ss_mask&expand=758) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm_mask_cmp_round_ss_mask( @@ -30832,7 +30832,7 @@ pub fn _mm_mask_cmp_round_ss_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_sd_mask&expand=760) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm_cmp_sd_mask(a: __m128d, b: __m128d) -> __mmask8 { @@ -30849,7 +30849,7 @@ pub fn _mm_cmp_sd_mask(a: __m128d, b: __m128d) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_sd_mask&expand=761) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vcmp, IMM8 = 0))] pub fn _mm_mask_cmp_sd_mask(k1: __mmask8, a: __m128d, b: __m128d) -> __mmask8 { @@ -30866,7 +30866,7 @@ pub fn _mm_mask_cmp_sd_mask(k1: __mmask8, a: __m128d, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_round_sd_mask&expand=755) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm_cmp_round_sd_mask(a: __m128d, b: __m128d) -> __mmask8 { @@ -30885,7 +30885,7 @@ pub fn _mm_cmp_round_sd_mask(a: __m128d, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_round_sd_mask&expand=756) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm_mask_cmp_round_sd_mask( @@ -30906,7 +30906,7 @@ pub fn _mm_mask_cmp_round_sd_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epu32_mask&expand=1056) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_cmplt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_lt(a.as_u32x16(), b.as_u32x16())) } @@ -30917,7 +30917,7 @@ pub fn _mm512_cmplt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epu32_mask&expand=1057) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_mask_cmplt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -30928,7 +30928,7 @@ pub fn _mm512_mask_cmplt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epu32_mask&expand=1054) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_cmplt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_lt(a.as_u32x8(), b.as_u32x8())) } @@ -30939,7 +30939,7 @@ pub fn _mm256_cmplt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epu32_mask&expand=1055) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_mask_cmplt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -30950,7 +30950,7 @@ pub fn _mm256_mask_cmplt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epu32_mask&expand=1052) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_cmplt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_lt(a.as_u32x4(), b.as_u32x4())) } @@ -30961,7 +30961,7 @@ pub fn _mm_cmplt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epu32_mask&expand=1053) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_mask_cmplt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu32_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -30972,7 +30972,7 @@ pub fn _mm_mask_cmplt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epu32_mask&expand=933) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_cmpgt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_gt(a.as_u32x16(), b.as_u32x16())) } @@ -30983,7 +30983,7 @@ pub fn _mm512_cmpgt_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epu32_mask&expand=934) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_mask_cmpgt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -30994,7 +30994,7 @@ pub fn _mm512_mask_cmpgt_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epu32_mask&expand=931) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_cmpgt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_gt(a.as_u32x8(), b.as_u32x8())) } @@ -31005,7 +31005,7 @@ pub fn _mm256_cmpgt_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epu32_mask&expand=932) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -31016,7 +31016,7 @@ pub fn _mm256_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epu32_mask&expand=929) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_cmpgt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_gt(a.as_u32x4(), b.as_u32x4())) } @@ -31027,7 +31027,7 @@ pub fn _mm_cmpgt_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epu32_mask&expand=930) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu32_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -31038,7 +31038,7 @@ pub fn _mm_mask_cmpgt_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epu32_mask&expand=995) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_cmple_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_le(a.as_u32x16(), b.as_u32x16())) } @@ -31049,7 +31049,7 @@ pub fn _mm512_cmple_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epu32_mask&expand=996) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_mask_cmple_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -31060,7 +31060,7 @@ pub fn _mm512_mask_cmple_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epu32_mask&expand=993) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_cmple_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_le(a.as_u32x8(), b.as_u32x8())) } @@ -31071,7 +31071,7 @@ pub fn _mm256_cmple_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epu32_mask&expand=994) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_mask_cmple_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -31082,7 +31082,7 @@ pub fn _mm256_mask_cmple_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epu32_mask&expand=991) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_cmple_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_le(a.as_u32x4(), b.as_u32x4())) } @@ -31093,7 +31093,7 @@ pub fn _mm_cmple_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epu32_mask&expand=992) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_mask_cmple_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu32_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -31104,7 +31104,7 @@ pub fn _mm_mask_cmple_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epu32_mask&expand=873) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_cmpge_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_ge(a.as_u32x16(), b.as_u32x16())) } @@ -31115,7 +31115,7 @@ pub fn _mm512_cmpge_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epu32_mask&expand=874) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_mask_cmpge_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -31126,7 +31126,7 @@ pub fn _mm512_mask_cmpge_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epu32_mask&expand=871) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_cmpge_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_ge(a.as_u32x8(), b.as_u32x8())) } @@ -31137,7 +31137,7 @@ pub fn _mm256_cmpge_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epu32_mask&expand=872) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_mask_cmpge_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -31148,7 +31148,7 @@ pub fn _mm256_mask_cmpge_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epu32_mask&expand=869) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_cmpge_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_ge(a.as_u32x4(), b.as_u32x4())) } @@ -31159,7 +31159,7 @@ pub fn _mm_cmpge_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epu32_mask&expand=870) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_mask_cmpge_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu32_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -31170,7 +31170,7 @@ pub fn _mm_mask_cmpge_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epu32_mask&expand=807) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_cmpeq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_eq(a.as_u32x16(), b.as_u32x16())) } @@ -31181,7 +31181,7 @@ pub fn _mm512_cmpeq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epu32_mask&expand=808) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_mask_cmpeq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -31192,7 +31192,7 @@ pub fn _mm512_mask_cmpeq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epu32_mask&expand=805) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_cmpeq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_eq(a.as_u32x8(), b.as_u32x8())) } @@ -31203,7 +31203,7 @@ pub fn _mm256_cmpeq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epu32_mask&expand=806) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -31214,7 +31214,7 @@ pub fn _mm256_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epu32_mask&expand=803) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_cmpeq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_eq(a.as_u32x4(), b.as_u32x4())) } @@ -31225,7 +31225,7 @@ pub fn _mm_cmpeq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epu32_mask&expand=804) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu32_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -31236,7 +31236,7 @@ pub fn _mm_mask_cmpeq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epu32_mask&expand=1112) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_cmpneq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_ne(a.as_u32x16(), b.as_u32x16())) } @@ -31247,7 +31247,7 @@ pub fn _mm512_cmpneq_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epu32_mask&expand=1113) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm512_mask_cmpneq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epu32_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -31258,7 +31258,7 @@ pub fn _mm512_mask_cmpneq_epu32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epu32_mask&expand=1110) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_cmpneq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_ne(a.as_u32x8(), b.as_u32x8())) } @@ -31269,7 +31269,7 @@ pub fn _mm256_cmpneq_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epu32_mask&expand=1111) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm256_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu32_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -31280,7 +31280,7 @@ pub fn _mm256_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epu32_mask&expand=1108) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_cmpneq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_ne(a.as_u32x4(), b.as_u32x4())) } @@ -31291,7 +31291,7 @@ pub fn _mm_cmpneq_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epu32_mask&expand=1109) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpud pub fn _mm_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu32_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -31302,7 +31302,7 @@ pub fn _mm_mask_cmpneq_epu32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epu32_mask&expand=721) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm512_cmp_epu32_mask(a: __m512i, b: __m512i) -> __mmask16 { @@ -31329,7 +31329,7 @@ pub fn _mm512_cmp_epu32_mask(a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epu32_mask&expand=722) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm512_mask_cmp_epu32_mask( @@ -31361,7 +31361,7 @@ pub fn _mm512_mask_cmp_epu32_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epu32_mask&expand=719) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm256_cmp_epu32_mask(a: __m256i, b: __m256i) -> __mmask8 { @@ -31388,7 +31388,7 @@ pub fn _mm256_cmp_epu32_mask(a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epu32_mask&expand=720) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm256_mask_cmp_epu32_mask( @@ -31420,7 +31420,7 @@ pub fn _mm256_mask_cmp_epu32_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epu32_mask&expand=717) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm_cmp_epu32_mask(a: __m128i, b: __m128i) -> __mmask8 { @@ -31447,7 +31447,7 @@ pub fn _mm_cmp_epu32_mask(a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epu32_mask&expand=718) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm_mask_cmp_epu32_mask( @@ -31479,7 +31479,7 @@ pub fn _mm_mask_cmp_epu32_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epi32_mask&expand=1029) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_cmplt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_lt(a.as_i32x16(), b.as_i32x16())) } @@ -31490,7 +31490,7 @@ pub fn _mm512_cmplt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epi32_mask&expand=1031) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_mask_cmplt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -31501,7 +31501,7 @@ pub fn _mm512_mask_cmplt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epi32_mask&expand=1027) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_cmplt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_lt(a.as_i32x8(), b.as_i32x8())) } @@ -31512,7 +31512,7 @@ pub fn _mm256_cmplt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epi32_mask&expand=1028) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_mask_cmplt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -31523,7 +31523,7 @@ pub fn _mm256_mask_cmplt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi32_mask&expand=1025) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_cmplt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_lt(a.as_i32x4(), b.as_i32x4())) } @@ -31534,7 +31534,7 @@ pub fn _mm_cmplt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epi32_mask&expand=1026) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_mask_cmplt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi32_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -31545,7 +31545,7 @@ pub fn _mm_mask_cmplt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epi32_mask&expand=905) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_cmpgt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_gt(a.as_i32x16(), b.as_i32x16())) } @@ -31556,7 +31556,7 @@ pub fn _mm512_cmpgt_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epi32_mask&expand=906) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_mask_cmpgt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -31567,7 +31567,7 @@ pub fn _mm512_mask_cmpgt_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epi32_mask&expand=903) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_cmpgt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_gt(a.as_i32x8(), b.as_i32x8())) } @@ -31578,7 +31578,7 @@ pub fn _mm256_cmpgt_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epi32_mask&expand=904) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -31589,7 +31589,7 @@ pub fn _mm256_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi32_mask&expand=901) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_cmpgt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_gt(a.as_i32x4(), b.as_i32x4())) } @@ -31600,7 +31600,7 @@ pub fn _mm_cmpgt_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epi32_mask&expand=902) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi32_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -31611,7 +31611,7 @@ pub fn _mm_mask_cmpgt_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epi32_mask&expand=971) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_cmple_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_le(a.as_i32x16(), b.as_i32x16())) } @@ -31622,7 +31622,7 @@ pub fn _mm512_cmple_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epi32_mask&expand=972) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_mask_cmple_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -31633,7 +31633,7 @@ pub fn _mm512_mask_cmple_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epi32_mask&expand=969) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_cmple_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_le(a.as_i32x8(), b.as_i32x8())) } @@ -31644,7 +31644,7 @@ pub fn _mm256_cmple_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epi32_mask&expand=970) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_mask_cmple_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -31655,7 +31655,7 @@ pub fn _mm256_mask_cmple_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epi32_mask&expand=967) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_cmple_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_le(a.as_i32x4(), b.as_i32x4())) } @@ -31666,7 +31666,7 @@ pub fn _mm_cmple_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epi32_mask&expand=968) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_mask_cmple_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi32_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -31677,7 +31677,7 @@ pub fn _mm_mask_cmple_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epi32_mask&expand=849) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_cmpge_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_ge(a.as_i32x16(), b.as_i32x16())) } @@ -31688,7 +31688,7 @@ pub fn _mm512_cmpge_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epi32_mask&expand=850) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_mask_cmpge_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -31699,7 +31699,7 @@ pub fn _mm512_mask_cmpge_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epi32_mask&expand=847) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_cmpge_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_ge(a.as_i32x8(), b.as_i32x8())) } @@ -31710,7 +31710,7 @@ pub fn _mm256_cmpge_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epi32_mask&expand=848) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_mask_cmpge_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -31721,7 +31721,7 @@ pub fn _mm256_mask_cmpge_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epi32_mask&expand=845) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_cmpge_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_ge(a.as_i32x4(), b.as_i32x4())) } @@ -31732,7 +31732,7 @@ pub fn _mm_cmpge_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epi32_mask&expand=846) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_mask_cmpge_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi32_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -31743,7 +31743,7 @@ pub fn _mm_mask_cmpge_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epi32_mask&expand=779) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_cmpeq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_eq(a.as_i32x16(), b.as_i32x16())) } @@ -31754,7 +31754,7 @@ pub fn _mm512_cmpeq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epi32_mask&expand=780) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_mask_cmpeq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -31765,7 +31765,7 @@ pub fn _mm512_mask_cmpeq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epi32_mask&expand=777) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_cmpeq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_eq(a.as_i32x8(), b.as_i32x8())) } @@ -31776,7 +31776,7 @@ pub fn _mm256_cmpeq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epi32_mask&expand=778) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -31787,7 +31787,7 @@ pub fn _mm256_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi32_mask&expand=775) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_cmpeq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_eq(a.as_i32x4(), b.as_i32x4())) } @@ -31798,7 +31798,7 @@ pub fn _mm_cmpeq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epi32_mask&expand=776) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi32_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -31809,7 +31809,7 @@ pub fn _mm_mask_cmpeq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epi32_mask&expand=1088) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_cmpneq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { unsafe { simd_bitmask::(simd_ne(a.as_i32x16(), b.as_i32x16())) } @@ -31820,7 +31820,7 @@ pub fn _mm512_cmpneq_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epi32_mask&expand=1089) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm512_mask_cmpneq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> __mmask16 { _mm512_mask_cmp_epi32_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -31831,7 +31831,7 @@ pub fn _mm512_mask_cmpneq_epi32_mask(k1: __mmask16, a: __m512i, b: __m512i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epi32_mask&expand=1086) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_cmpneq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::(simd_ne(a.as_i32x8(), b.as_i32x8())) } @@ -31842,7 +31842,7 @@ pub fn _mm256_cmpneq_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epi32_mask&expand=1087) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm256_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi32_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -31853,7 +31853,7 @@ pub fn _mm256_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epi32_mask&expand=1084) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_cmpneq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::(simd_ne(a.as_i32x4(), b.as_i32x4())) } @@ -31864,7 +31864,7 @@ pub fn _mm_cmpneq_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epi32_mask&expand=1085) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpd pub fn _mm_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi32_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -31875,7 +31875,7 @@ pub fn _mm_mask_cmpneq_epi32_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epi32_mask&expand=697) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm512_cmp_epi32_mask(a: __m512i, b: __m512i) -> __mmask16 { @@ -31902,7 +31902,7 @@ pub fn _mm512_cmp_epi32_mask(a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epi32_mask&expand=698) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm512_mask_cmp_epi32_mask( @@ -31934,7 +31934,7 @@ pub fn _mm512_mask_cmp_epi32_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm256_cmp_epi32_mask&expand=695) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm256_cmp_epi32_mask(a: __m256i, b: __m256i) -> __mmask8 { @@ -31961,7 +31961,7 @@ pub fn _mm256_cmp_epi32_mask(a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epi32_mask&expand=696) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm256_mask_cmp_epi32_mask( @@ -31993,7 +31993,7 @@ pub fn _mm256_mask_cmp_epi32_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epi32_mask&expand=693) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm_cmp_epi32_mask(a: __m128i, b: __m128i) -> __mmask8 { @@ -32020,7 +32020,7 @@ pub fn _mm_cmp_epi32_mask(a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epi32_mask&expand=694) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm_mask_cmp_epi32_mask( @@ -32052,7 +32052,7 @@ pub fn _mm_mask_cmp_epi32_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epu64_mask&expand=1062) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_cmplt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_lt(a.as_u64x8(), b.as_u64x8())) } @@ -32063,7 +32063,7 @@ pub fn _mm512_cmplt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epu64_mask&expand=1063) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_mask_cmplt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -32074,7 +32074,7 @@ pub fn _mm512_mask_cmplt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epu64_mask&expand=1060) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_cmplt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_lt(a.as_u64x4(), b.as_u64x4())) } @@ -32085,7 +32085,7 @@ pub fn _mm256_cmplt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epu64_mask&expand=1061) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_mask_cmplt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -32096,7 +32096,7 @@ pub fn _mm256_mask_cmplt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epu64_mask&expand=1058) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_cmplt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_lt(a.as_u64x2(), b.as_u64x2())) } @@ -32107,7 +32107,7 @@ pub fn _mm_cmplt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epu64_mask&expand=1059) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_mask_cmplt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -32118,7 +32118,7 @@ pub fn _mm_mask_cmplt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epu64_mask&expand=939) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_cmpgt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_gt(a.as_u64x8(), b.as_u64x8())) } @@ -32129,7 +32129,7 @@ pub fn _mm512_cmpgt_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epu64_mask&expand=940) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -32140,7 +32140,7 @@ pub fn _mm512_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epu64_mask&expand=937) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_cmpgt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_gt(a.as_u64x4(), b.as_u64x4())) } @@ -32151,7 +32151,7 @@ pub fn _mm256_cmpgt_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epu64_mask&expand=938) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -32162,7 +32162,7 @@ pub fn _mm256_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epu64_mask&expand=935) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_cmpgt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_gt(a.as_u64x2(), b.as_u64x2())) } @@ -32173,7 +32173,7 @@ pub fn _mm_cmpgt_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epu64_mask&expand=936) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu64_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -32184,7 +32184,7 @@ pub fn _mm_mask_cmpgt_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epu64_mask&expand=1001) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_cmple_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_le(a.as_u64x8(), b.as_u64x8())) } @@ -32195,7 +32195,7 @@ pub fn _mm512_cmple_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epu64_mask&expand=1002) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_mask_cmple_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -32206,7 +32206,7 @@ pub fn _mm512_mask_cmple_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epu64_mask&expand=999) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_cmple_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_le(a.as_u64x4(), b.as_u64x4())) } @@ -32217,7 +32217,7 @@ pub fn _mm256_cmple_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epu64_mask&expand=1000) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_mask_cmple_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -32228,7 +32228,7 @@ pub fn _mm256_mask_cmple_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epu64_mask&expand=997) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_cmple_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_le(a.as_u64x2(), b.as_u64x2())) } @@ -32239,7 +32239,7 @@ pub fn _mm_cmple_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epu64_mask&expand=998) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_mask_cmple_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu64_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -32250,7 +32250,7 @@ pub fn _mm_mask_cmple_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epu64_mask&expand=879) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_cmpge_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_ge(a.as_u64x8(), b.as_u64x8())) } @@ -32261,7 +32261,7 @@ pub fn _mm512_cmpge_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epu64_mask&expand=880) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_mask_cmpge_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -32272,7 +32272,7 @@ pub fn _mm512_mask_cmpge_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epu64_mask&expand=877) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_cmpge_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_ge(a.as_u64x4(), b.as_u64x4())) } @@ -32283,7 +32283,7 @@ pub fn _mm256_cmpge_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epu64_mask&expand=878) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_mask_cmpge_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -32294,7 +32294,7 @@ pub fn _mm256_mask_cmpge_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epu64_mask&expand=875) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_cmpge_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_ge(a.as_u64x2(), b.as_u64x2())) } @@ -32305,7 +32305,7 @@ pub fn _mm_cmpge_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epu64_mask&expand=876) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_mask_cmpge_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu64_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -32316,7 +32316,7 @@ pub fn _mm_mask_cmpge_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epu64_mask&expand=813) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_cmpeq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_eq(a.as_u64x8(), b.as_u64x8())) } @@ -32327,7 +32327,7 @@ pub fn _mm512_cmpeq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epu64_mask&expand=814) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -32338,7 +32338,7 @@ pub fn _mm512_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epu64_mask&expand=811) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_cmpeq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_eq(a.as_u64x4(), b.as_u64x4())) } @@ -32349,7 +32349,7 @@ pub fn _mm256_cmpeq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epu64_mask&expand=812) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -32360,7 +32360,7 @@ pub fn _mm256_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epu64_mask&expand=809) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_cmpeq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_eq(a.as_u64x2(), b.as_u64x2())) } @@ -32371,7 +32371,7 @@ pub fn _mm_cmpeq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epu64_mask&expand=810) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu64_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -32382,7 +32382,7 @@ pub fn _mm_mask_cmpeq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epu64_mask&expand=1118) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_cmpneq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_ne(a.as_u64x8(), b.as_u64x8())) } @@ -32393,7 +32393,7 @@ pub fn _mm512_cmpneq_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epu64_mask&expand=1119) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm512_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epu64_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -32404,7 +32404,7 @@ pub fn _mm512_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epu64_mask&expand=1116) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_cmpneq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_ne(a.as_u64x4(), b.as_u64x4())) } @@ -32415,7 +32415,7 @@ pub fn _mm256_cmpneq_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epu64_mask&expand=1117) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm256_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epu64_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -32426,7 +32426,7 @@ pub fn _mm256_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epu64_mask&expand=1114) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_cmpneq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_ne(a.as_u64x2(), b.as_u64x2())) } @@ -32437,7 +32437,7 @@ pub fn _mm_cmpneq_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epu64_mask&expand=1115) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpuq pub fn _mm_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epu64_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -32448,7 +32448,7 @@ pub fn _mm_mask_cmpneq_epu64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epu64_mask&expand=727) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm512_cmp_epu64_mask(a: __m512i, b: __m512i) -> __mmask8 { @@ -32475,7 +32475,7 @@ pub fn _mm512_cmp_epu64_mask(a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epu64_mask&expand=728) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm512_mask_cmp_epu64_mask( @@ -32507,7 +32507,7 @@ pub fn _mm512_mask_cmp_epu64_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epu64_mask&expand=725) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm256_cmp_epu64_mask(a: __m256i, b: __m256i) -> __mmask8 { @@ -32534,7 +32534,7 @@ pub fn _mm256_cmp_epu64_mask(a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epu64_mask&expand=726) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm256_mask_cmp_epu64_mask( @@ -32566,7 +32566,7 @@ pub fn _mm256_mask_cmp_epu64_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epu64_mask&expand=723) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm_cmp_epu64_mask(a: __m128i, b: __m128i) -> __mmask8 { @@ -32593,7 +32593,7 @@ pub fn _mm_cmp_epu64_mask(a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epu64_mask&expand=724) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm_mask_cmp_epu64_mask( @@ -32625,7 +32625,7 @@ pub fn _mm_mask_cmp_epu64_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epi64_mask&expand=1037) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_cmplt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_lt(a.as_i64x8(), b.as_i64x8())) } @@ -32636,7 +32636,7 @@ pub fn _mm512_cmplt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epi64_mask&expand=1038) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_mask_cmplt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -32647,7 +32647,7 @@ pub fn _mm512_mask_cmplt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epi64_mask&expand=1035) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_cmplt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_lt(a.as_i64x4(), b.as_i64x4())) } @@ -32658,7 +32658,7 @@ pub fn _mm256_cmplt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epi64_mask&expand=1036) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_mask_cmplt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -32669,7 +32669,7 @@ pub fn _mm256_mask_cmplt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi64_mask&expand=1033) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_cmplt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_lt(a.as_i64x2(), b.as_i64x2())) } @@ -32680,7 +32680,7 @@ pub fn _mm_cmplt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epi64_mask&expand=1034) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_mask_cmplt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LT>(k1, a, b) @@ -32691,7 +32691,7 @@ pub fn _mm_mask_cmplt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epi64_mask&expand=913) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_cmpgt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_gt(a.as_i64x8(), b.as_i64x8())) } @@ -32702,7 +32702,7 @@ pub fn _mm512_cmpgt_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epi64_mask&expand=914) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -32713,7 +32713,7 @@ pub fn _mm512_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epi64_mask&expand=911) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_cmpgt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_gt(a.as_i64x4(), b.as_i64x4())) } @@ -32724,7 +32724,7 @@ pub fn _mm256_cmpgt_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epi64_mask&expand=912) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -32735,7 +32735,7 @@ pub fn _mm256_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi64_mask&expand=909) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_cmpgt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_gt(a.as_i64x2(), b.as_i64x2())) } @@ -32746,7 +32746,7 @@ pub fn _mm_cmpgt_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epi64_mask&expand=910) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi64_mask::<_MM_CMPINT_NLE>(k1, a, b) @@ -32757,7 +32757,7 @@ pub fn _mm_mask_cmpgt_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epi64_mask&expand=977) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_cmple_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_le(a.as_i64x8(), b.as_i64x8())) } @@ -32768,7 +32768,7 @@ pub fn _mm512_cmple_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epi64_mask&expand=978) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_mask_cmple_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -32779,7 +32779,7 @@ pub fn _mm512_mask_cmple_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epi64_mask&expand=975) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_cmple_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_le(a.as_i64x4(), b.as_i64x4())) } @@ -32790,7 +32790,7 @@ pub fn _mm256_cmple_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epi64_mask&expand=976) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_mask_cmple_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -32801,7 +32801,7 @@ pub fn _mm256_mask_cmple_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epi64_mask&expand=973) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_cmple_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_le(a.as_i64x2(), b.as_i64x2())) } @@ -32812,7 +32812,7 @@ pub fn _mm_cmple_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epi64_mask&expand=974) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_mask_cmple_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi64_mask::<_MM_CMPINT_LE>(k1, a, b) @@ -32823,7 +32823,7 @@ pub fn _mm_mask_cmple_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epi64_mask&expand=855) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_cmpge_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_ge(a.as_i64x8(), b.as_i64x8())) } @@ -32834,7 +32834,7 @@ pub fn _mm512_cmpge_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epi64_mask&expand=856) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_mask_cmpge_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -32845,7 +32845,7 @@ pub fn _mm512_mask_cmpge_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epi64_mask&expand=853) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_cmpge_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_ge(a.as_i64x4(), b.as_i64x4())) } @@ -32856,7 +32856,7 @@ pub fn _mm256_cmpge_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epi64_mask&expand=854) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_mask_cmpge_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -32867,7 +32867,7 @@ pub fn _mm256_mask_cmpge_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epi64_mask&expand=851) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_cmpge_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_ge(a.as_i64x2(), b.as_i64x2())) } @@ -32878,7 +32878,7 @@ pub fn _mm_cmpge_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epi64_mask&expand=852) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_mask_cmpge_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi64_mask::<_MM_CMPINT_NLT>(k1, a, b) @@ -32889,7 +32889,7 @@ pub fn _mm_mask_cmpge_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epi64_mask&expand=787) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_cmpeq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_eq(a.as_i64x8(), b.as_i64x8())) } @@ -32900,7 +32900,7 @@ pub fn _mm512_cmpeq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epi64_mask&expand=788) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -32911,7 +32911,7 @@ pub fn _mm512_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epi64_mask&expand=785) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_cmpeq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_eq(a.as_i64x4(), b.as_i64x4())) } @@ -32922,7 +32922,7 @@ pub fn _mm256_cmpeq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epi64_mask&expand=786) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -32933,7 +32933,7 @@ pub fn _mm256_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi64_mask&expand=783) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_cmpeq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_eq(a.as_i64x2(), b.as_i64x2())) } @@ -32944,7 +32944,7 @@ pub fn _mm_cmpeq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epi64_mask&expand=784) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi64_mask::<_MM_CMPINT_EQ>(k1, a, b) @@ -32955,7 +32955,7 @@ pub fn _mm_mask_cmpeq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmas /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epi64_mask&expand=1094) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_cmpneq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { unsafe { simd_bitmask::<__m512i, _>(simd_ne(a.as_i64x8(), b.as_i64x8())) } @@ -32966,7 +32966,7 @@ pub fn _mm512_cmpneq_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epi64_mask&expand=1095) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm512_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __mmask8 { _mm512_mask_cmp_epi64_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -32977,7 +32977,7 @@ pub fn _mm512_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m512i, b: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epi64_mask&expand=1092) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_cmpneq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { unsafe { simd_bitmask::<__m256i, _>(simd_ne(a.as_i64x4(), b.as_i64x4())) } @@ -32988,7 +32988,7 @@ pub fn _mm256_cmpneq_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epi64_mask&expand=1093) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm256_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __mmask8 { _mm256_mask_cmp_epi64_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -32999,7 +32999,7 @@ pub fn _mm256_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m256i, b: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epi64_mask&expand=1090) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_cmpneq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { unsafe { simd_bitmask::<__m128i, _>(simd_ne(a.as_i64x2(), b.as_i64x2())) } @@ -33010,7 +33010,7 @@ pub fn _mm_cmpneq_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epi64_mask&expand=1091) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcmp))] //should be vpcmpq pub fn _mm_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 { _mm_mask_cmp_epi64_mask::<_MM_CMPINT_NE>(k1, a, b) @@ -33021,7 +33021,7 @@ pub fn _mm_mask_cmpneq_epi64_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mma /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epi64_mask&expand=703) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm512_cmp_epi64_mask(a: __m512i, b: __m512i) -> __mmask8 { @@ -33048,7 +33048,7 @@ pub fn _mm512_cmp_epi64_mask(a: __m512i, b: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epi64_mask&expand=704) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm512_mask_cmp_epi64_mask( @@ -33080,7 +33080,7 @@ pub fn _mm512_mask_cmp_epi64_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epi64_mask&expand=701) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm256_cmp_epi64_mask(a: __m256i, b: __m256i) -> __mmask8 { @@ -33107,7 +33107,7 @@ pub fn _mm256_cmp_epi64_mask(a: __m256i, b: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epi64_mask&expand=702) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm256_mask_cmp_epi64_mask( @@ -33139,7 +33139,7 @@ pub fn _mm256_mask_cmp_epi64_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epi64_mask&expand=699) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm_cmp_epi64_mask(a: __m128i, b: __m128i) -> __mmask8 { @@ -33166,7 +33166,7 @@ pub fn _mm_cmp_epi64_mask(a: __m128i, b: __m128i) - /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epi64_mask&expand=700) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vpcmp, IMM3 = 0))] pub fn _mm_mask_cmp_epi64_mask( @@ -33198,7 +33198,7 @@ pub fn _mm_mask_cmp_epi64_mask( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_add_epi32&expand=4556) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_add_epi32(a: __m512i) -> i32 { unsafe { simd_reduce_add_unordered(a.as_i32x16()) } } @@ -33208,7 +33208,7 @@ pub fn _mm512_reduce_add_epi32(a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_add_epi32&expand=4555) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_add_epi32(k: __mmask16, a: __m512i) -> i32 { unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i32x16(), i32x16::ZERO)) } } @@ -33218,7 +33218,7 @@ pub fn _mm512_mask_reduce_add_epi32(k: __mmask16, a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_add_epi64&expand=4558) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_add_epi64(a: __m512i) -> i64 { unsafe { simd_reduce_add_unordered(a.as_i64x8()) } } @@ -33228,7 +33228,7 @@ pub fn _mm512_reduce_add_epi64(a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_add_epi64&expand=4557) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_add_epi64(k: __mmask8, a: __m512i) -> i64 { unsafe { simd_reduce_add_unordered(simd_select_bitmask(k, a.as_i64x8(), i64x8::ZERO)) } } @@ -33238,7 +33238,7 @@ pub fn _mm512_mask_reduce_add_epi64(k: __mmask8, a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_add_ps&expand=4562) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_add_ps(a: __m512) -> f32 { unsafe { // we have to use `simd_shuffle` here because `_mm512_extractf32x8_ps` is in AVX512DQ @@ -33257,7 +33257,7 @@ pub fn _mm512_reduce_add_ps(a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_add_ps&expand=4561) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_add_ps(k: __mmask16, a: __m512) -> f32 { unsafe { _mm512_reduce_add_ps(simd_select_bitmask(k, a, _mm512_setzero_ps())) } } @@ -33267,7 +33267,7 @@ pub fn _mm512_mask_reduce_add_ps(k: __mmask16, a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_add_pd&expand=4560) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_add_pd(a: __m512d) -> f64 { unsafe { let a = _mm256_add_pd( @@ -33284,7 +33284,7 @@ pub fn _mm512_reduce_add_pd(a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_add_pd&expand=4559) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_add_pd(k: __mmask8, a: __m512d) -> f64 { unsafe { _mm512_reduce_add_pd(simd_select_bitmask(k, a, _mm512_setzero_pd())) } } @@ -33294,7 +33294,7 @@ pub fn _mm512_mask_reduce_add_pd(k: __mmask8, a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_mul_epi32&expand=4600) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_mul_epi32(a: __m512i) -> i32 { unsafe { simd_reduce_mul_unordered(a.as_i32x16()) } } @@ -33304,7 +33304,7 @@ pub fn _mm512_reduce_mul_epi32(a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_mul_epi32&expand=4599) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_mul_epi32(k: __mmask16, a: __m512i) -> i32 { unsafe { simd_reduce_mul_unordered(simd_select_bitmask( @@ -33320,7 +33320,7 @@ pub fn _mm512_mask_reduce_mul_epi32(k: __mmask16, a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_mul_epi64&expand=4602) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_mul_epi64(a: __m512i) -> i64 { unsafe { simd_reduce_mul_unordered(a.as_i64x8()) } } @@ -33330,7 +33330,7 @@ pub fn _mm512_reduce_mul_epi64(a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_mul_epi64&expand=4601) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_mul_epi64(k: __mmask8, a: __m512i) -> i64 { unsafe { simd_reduce_mul_unordered(simd_select_bitmask( @@ -33346,7 +33346,7 @@ pub fn _mm512_mask_reduce_mul_epi64(k: __mmask8, a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_mul_ps&expand=4606) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_mul_ps(a: __m512) -> f32 { unsafe { // we have to use `simd_shuffle` here because `_mm512_extractf32x8_ps` is in AVX512DQ @@ -33365,7 +33365,7 @@ pub fn _mm512_reduce_mul_ps(a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_mul_ps&expand=4605) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_mul_ps(k: __mmask16, a: __m512) -> f32 { unsafe { _mm512_reduce_mul_ps(simd_select_bitmask(k, a, _mm512_set1_ps(1.))) } } @@ -33375,7 +33375,7 @@ pub fn _mm512_mask_reduce_mul_ps(k: __mmask16, a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_mul_pd&expand=4604) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_mul_pd(a: __m512d) -> f64 { unsafe { let a = _mm256_mul_pd( @@ -33392,7 +33392,7 @@ pub fn _mm512_reduce_mul_pd(a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_mul_pd&expand=4603) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_mul_pd(k: __mmask8, a: __m512d) -> f64 { unsafe { _mm512_reduce_mul_pd(simd_select_bitmask(k, a, _mm512_set1_pd(1.))) } } @@ -33402,7 +33402,7 @@ pub fn _mm512_mask_reduce_mul_pd(k: __mmask8, a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_max_epi32&expand=4576) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_max_epi32(a: __m512i) -> i32 { unsafe { simd_reduce_max(a.as_i32x16()) } } @@ -33412,7 +33412,7 @@ pub fn _mm512_reduce_max_epi32(a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_max_epi32&expand=4575) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_max_epi32(k: __mmask16, a: __m512i) -> i32 { unsafe { simd_reduce_max(simd_select_bitmask( @@ -33428,7 +33428,7 @@ pub fn _mm512_mask_reduce_max_epi32(k: __mmask16, a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_max_epi64&expand=4578) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_max_epi64(a: __m512i) -> i64 { unsafe { simd_reduce_max(a.as_i64x8()) } } @@ -33438,7 +33438,7 @@ pub fn _mm512_reduce_max_epi64(a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_max_epi64&expand=4577) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_max_epi64(k: __mmask8, a: __m512i) -> i64 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_i64x8(), i64x8::splat(i64::MIN))) } } @@ -33448,7 +33448,7 @@ pub fn _mm512_mask_reduce_max_epi64(k: __mmask8, a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_max_epu32&expand=4580) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_max_epu32(a: __m512i) -> u32 { unsafe { simd_reduce_max(a.as_u32x16()) } } @@ -33458,7 +33458,7 @@ pub fn _mm512_reduce_max_epu32(a: __m512i) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_max_epu32&expand=4579) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_max_epu32(k: __mmask16, a: __m512i) -> u32 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u32x16(), u32x16::ZERO)) } } @@ -33468,7 +33468,7 @@ pub fn _mm512_mask_reduce_max_epu32(k: __mmask16, a: __m512i) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_max_epu64&expand=4582) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_max_epu64(a: __m512i) -> u64 { unsafe { simd_reduce_max(a.as_u64x8()) } } @@ -33478,7 +33478,7 @@ pub fn _mm512_reduce_max_epu64(a: __m512i) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_max_epu64&expand=4581) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_max_epu64(k: __mmask8, a: __m512i) -> u64 { unsafe { simd_reduce_max(simd_select_bitmask(k, a.as_u64x8(), u64x8::ZERO)) } } @@ -33488,7 +33488,7 @@ pub fn _mm512_mask_reduce_max_epu64(k: __mmask8, a: __m512i) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_max_ps&expand=4586) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_max_ps(a: __m512) -> f32 { unsafe { let a = _mm256_max_ps( @@ -33506,7 +33506,7 @@ pub fn _mm512_reduce_max_ps(a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_max_ps&expand=4585) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_max_ps(k: __mmask16, a: __m512) -> f32 { _mm512_reduce_max_ps(_mm512_mask_mov_ps(_mm512_set1_ps(f32::MIN), k, a)) } @@ -33516,7 +33516,7 @@ pub fn _mm512_mask_reduce_max_ps(k: __mmask16, a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_max_pd&expand=4584) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_max_pd(a: __m512d) -> f64 { unsafe { let a = _mm256_max_pd( @@ -33533,7 +33533,7 @@ pub fn _mm512_reduce_max_pd(a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_max_pd&expand=4583) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_max_pd(k: __mmask8, a: __m512d) -> f64 { _mm512_reduce_max_pd(_mm512_mask_mov_pd(_mm512_set1_pd(f64::MIN), k, a)) } @@ -33543,7 +33543,7 @@ pub fn _mm512_mask_reduce_max_pd(k: __mmask8, a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_min_epi32&expand=4588) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_min_epi32(a: __m512i) -> i32 { unsafe { simd_reduce_min(a.as_i32x16()) } } @@ -33553,7 +33553,7 @@ pub fn _mm512_reduce_min_epi32(a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_min_epi32&expand=4587) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_min_epi32(k: __mmask16, a: __m512i) -> i32 { unsafe { simd_reduce_min(simd_select_bitmask( @@ -33569,7 +33569,7 @@ pub fn _mm512_mask_reduce_min_epi32(k: __mmask16, a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_min_epi64&expand=4590) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_min_epi64(a: __m512i) -> i64 { unsafe { simd_reduce_min(a.as_i64x8()) } } @@ -33579,7 +33579,7 @@ pub fn _mm512_reduce_min_epi64(a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_min_epi64&expand=4589) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_min_epi64(k: __mmask8, a: __m512i) -> i64 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_i64x8(), i64x8::splat(i64::MAX))) } } @@ -33589,7 +33589,7 @@ pub fn _mm512_mask_reduce_min_epi64(k: __mmask8, a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_min_epu32&expand=4592) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_min_epu32(a: __m512i) -> u32 { unsafe { simd_reduce_min(a.as_u32x16()) } } @@ -33599,7 +33599,7 @@ pub fn _mm512_reduce_min_epu32(a: __m512i) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_min_epu32&expand=4591) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_min_epu32(k: __mmask16, a: __m512i) -> u32 { unsafe { simd_reduce_min(simd_select_bitmask( @@ -33615,7 +33615,7 @@ pub fn _mm512_mask_reduce_min_epu32(k: __mmask16, a: __m512i) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_min_epu64&expand=4594) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_min_epu64(a: __m512i) -> u64 { unsafe { simd_reduce_min(a.as_u64x8()) } } @@ -33625,7 +33625,7 @@ pub fn _mm512_reduce_min_epu64(a: __m512i) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_min_epu64&expand=4589) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_min_epu64(k: __mmask8, a: __m512i) -> u64 { unsafe { simd_reduce_min(simd_select_bitmask(k, a.as_u64x8(), u64x8::splat(u64::MAX))) } } @@ -33635,7 +33635,7 @@ pub fn _mm512_mask_reduce_min_epu64(k: __mmask8, a: __m512i) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_min_ps&expand=4598) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_min_ps(a: __m512) -> f32 { unsafe { let a = _mm256_min_ps( @@ -33653,7 +33653,7 @@ pub fn _mm512_reduce_min_ps(a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_min_ps&expand=4597) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_min_ps(k: __mmask16, a: __m512) -> f32 { _mm512_reduce_min_ps(_mm512_mask_mov_ps(_mm512_set1_ps(f32::MAX), k, a)) } @@ -33663,7 +33663,7 @@ pub fn _mm512_mask_reduce_min_ps(k: __mmask16, a: __m512) -> f32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_min_pd&expand=4596) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_min_pd(a: __m512d) -> f64 { unsafe { let a = _mm256_min_pd( @@ -33680,7 +33680,7 @@ pub fn _mm512_reduce_min_pd(a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_min_pd&expand=4595) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_min_pd(k: __mmask8, a: __m512d) -> f64 { _mm512_reduce_min_pd(_mm512_mask_mov_pd(_mm512_set1_pd(f64::MAX), k, a)) } @@ -33690,7 +33690,7 @@ pub fn _mm512_mask_reduce_min_pd(k: __mmask8, a: __m512d) -> f64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_and_epi32&expand=4564) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_and_epi32(a: __m512i) -> i32 { unsafe { simd_reduce_and(a.as_i32x16()) } } @@ -33700,7 +33700,7 @@ pub fn _mm512_reduce_and_epi32(a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_and_epi32&expand=4563) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_and_epi32(k: __mmask16, a: __m512i) -> i32 { unsafe { simd_reduce_and(simd_select_bitmask(k, a.as_i32x16(), i32x16::splat(-1))) } } @@ -33710,7 +33710,7 @@ pub fn _mm512_mask_reduce_and_epi32(k: __mmask16, a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_and_epi64&expand=4566) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_and_epi64(a: __m512i) -> i64 { unsafe { simd_reduce_and(a.as_i64x8()) } } @@ -33720,7 +33720,7 @@ pub fn _mm512_reduce_and_epi64(a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_and_epi64&expand=4557) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_and_epi64(k: __mmask8, a: __m512i) -> i64 { unsafe { simd_reduce_and(simd_select_bitmask(k, a.as_i64x8(), i64x8::splat(-1))) } } @@ -33730,7 +33730,7 @@ pub fn _mm512_mask_reduce_and_epi64(k: __mmask8, a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_or_epi32&expand=4608) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_or_epi32(a: __m512i) -> i32 { unsafe { simd_reduce_or(a.as_i32x16()) } } @@ -33740,7 +33740,7 @@ pub fn _mm512_reduce_or_epi32(a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_or_epi32&expand=4607) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_or_epi32(k: __mmask16, a: __m512i) -> i32 { unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i32x16(), i32x16::ZERO)) } } @@ -33750,7 +33750,7 @@ pub fn _mm512_mask_reduce_or_epi32(k: __mmask16, a: __m512i) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_reduce_or_epi64&expand=4610) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_reduce_or_epi64(a: __m512i) -> i64 { unsafe { simd_reduce_or(a.as_i64x8()) } } @@ -33760,7 +33760,7 @@ pub fn _mm512_reduce_or_epi64(a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_reduce_or_epi64&expand=4609) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_mask_reduce_or_epi64(k: __mmask8, a: __m512i) -> i64 { unsafe { simd_reduce_or(simd_select_bitmask(k, a.as_i64x8(), i64x8::ZERO)) } } @@ -33773,7 +33773,7 @@ pub fn _mm512_mask_reduce_or_epi64(k: __mmask8, a: __m512i) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_undefined_pd) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] // This intrinsic has no corresponding instruction. pub fn _mm512_undefined_pd() -> __m512d { unsafe { const { mem::zeroed() } } @@ -33787,7 +33787,7 @@ pub fn _mm512_undefined_pd() -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_undefined_ps) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] // This intrinsic has no corresponding instruction. pub fn _mm512_undefined_ps() -> __m512 { unsafe { const { mem::zeroed() } } @@ -33801,7 +33801,7 @@ pub fn _mm512_undefined_ps() -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_undefined_epi32&expand=5995) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] // This intrinsic has no corresponding instruction. pub fn _mm512_undefined_epi32() -> __m512i { unsafe { const { mem::zeroed() } } @@ -33815,7 +33815,7 @@ pub fn _mm512_undefined_epi32() -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_undefined&expand=5994) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] // This intrinsic has no corresponding instruction. pub fn _mm512_undefined() -> __m512 { unsafe { const { mem::zeroed() } } @@ -33826,7 +33826,7 @@ pub fn _mm512_undefined() -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_epi32&expand=3377) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32 pub unsafe fn _mm512_loadu_epi32(mem_addr: *const i32) -> __m512i { ptr::read_unaligned(mem_addr as *const __m512i) @@ -33837,7 +33837,7 @@ pub unsafe fn _mm512_loadu_epi32(mem_addr: *const i32) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_loadu_epi32&expand=3374) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32 pub unsafe fn _mm256_loadu_epi32(mem_addr: *const i32) -> __m256i { ptr::read_unaligned(mem_addr as *const __m256i) @@ -33848,7 +33848,7 @@ pub unsafe fn _mm256_loadu_epi32(mem_addr: *const i32) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadu_epi32&expand=3371) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32 pub unsafe fn _mm_loadu_epi32(mem_addr: *const i32) -> __m128i { ptr::read_unaligned(mem_addr as *const __m128i) @@ -33859,7 +33859,7 @@ pub unsafe fn _mm_loadu_epi32(mem_addr: *const i32) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi32_storeu_epi16&expand=1460) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub unsafe fn _mm512_mask_cvtepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask16, a: __m512i) { vpmovdwmem(mem_addr.cast(), a.as_i32x16(), k); @@ -33870,7 +33870,7 @@ pub unsafe fn _mm512_mask_cvtepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask16 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi32_storeu_epi16&expand=1462) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub unsafe fn _mm256_mask_cvtepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m256i) { vpmovdwmem256(mem_addr.cast(), a.as_i32x8(), k); @@ -33881,7 +33881,7 @@ pub unsafe fn _mm256_mask_cvtepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi32_storeu_epi16&expand=1461) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdw))] pub unsafe fn _mm_mask_cvtepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m128i) { vpmovdwmem128(mem_addr.cast(), a.as_i32x4(), k); @@ -33892,7 +33892,7 @@ pub unsafe fn _mm_mask_cvtepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi32_storeu_epi16&expand=1833) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub unsafe fn _mm512_mask_cvtsepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask16, a: __m512i) { vpmovsdwmem(mem_addr.cast(), a.as_i32x16(), k); @@ -33903,7 +33903,7 @@ pub unsafe fn _mm512_mask_cvtsepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi32_storeu_epi16&expand=1832) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub unsafe fn _mm256_mask_cvtsepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m256i) { vpmovsdwmem256(mem_addr.cast(), a.as_i32x8(), k); @@ -33914,7 +33914,7 @@ pub unsafe fn _mm256_mask_cvtsepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi32_storeu_epi16&expand=1831) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdw))] pub unsafe fn _mm_mask_cvtsepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m128i) { vpmovsdwmem128(mem_addr.cast(), a.as_i32x4(), k); @@ -33925,7 +33925,7 @@ pub unsafe fn _mm_mask_cvtsepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi32_storeu_epi16&expand=2068) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub unsafe fn _mm512_mask_cvtusepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask16, a: __m512i) { vpmovusdwmem(mem_addr.cast(), a.as_i32x16(), k); @@ -33936,7 +33936,7 @@ pub unsafe fn _mm512_mask_cvtusepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi32_storeu_epi16&expand=2067) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub unsafe fn _mm256_mask_cvtusepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m256i) { vpmovusdwmem256(mem_addr.cast(), a.as_i32x8(), k); @@ -33947,7 +33947,7 @@ pub unsafe fn _mm256_mask_cvtusepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi32_storeu_epi16&expand=2066) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdw))] pub unsafe fn _mm_mask_cvtusepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m128i) { vpmovusdwmem128(mem_addr.cast(), a.as_i32x4(), k); @@ -33958,7 +33958,7 @@ pub unsafe fn _mm_mask_cvtusepi32_storeu_epi16(mem_addr: *mut i16, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi32_storeu_epi8&expand=1463) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub unsafe fn _mm512_mask_cvtepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m512i) { vpmovdbmem(mem_addr, a.as_i32x16(), k); @@ -33969,7 +33969,7 @@ pub unsafe fn _mm512_mask_cvtepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask16, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi32_storeu_epi8&expand=1462) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub unsafe fn _mm256_mask_cvtepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m256i) { vpmovdbmem256(mem_addr, a.as_i32x8(), k); @@ -33980,7 +33980,7 @@ pub unsafe fn _mm256_mask_cvtepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi32_storeu_epi8&expand=1461) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovdb))] pub unsafe fn _mm_mask_cvtepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovdbmem128(mem_addr, a.as_i32x4(), k); @@ -33991,7 +33991,7 @@ pub unsafe fn _mm_mask_cvtepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi32_storeu_epi8&expand=1836) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub unsafe fn _mm512_mask_cvtsepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m512i) { vpmovsdbmem(mem_addr, a.as_i32x16(), k); @@ -34002,7 +34002,7 @@ pub unsafe fn _mm512_mask_cvtsepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask16, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi32_storeu_epi8&expand=1835) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub unsafe fn _mm256_mask_cvtsepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m256i) { vpmovsdbmem256(mem_addr, a.as_i32x8(), k); @@ -34013,7 +34013,7 @@ pub unsafe fn _mm256_mask_cvtsepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi32_storeu_epi8&expand=1834) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsdb))] pub unsafe fn _mm_mask_cvtsepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovsdbmem128(mem_addr, a.as_i32x4(), k); @@ -34024,7 +34024,7 @@ pub unsafe fn _mm_mask_cvtsepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi32_storeu_epi8&expand=2071) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub unsafe fn _mm512_mask_cvtusepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m512i) { vpmovusdbmem(mem_addr, a.as_i32x16(), k); @@ -34035,7 +34035,7 @@ pub unsafe fn _mm512_mask_cvtusepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask16 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi32_storeu_epi8&expand=2070) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub unsafe fn _mm256_mask_cvtusepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m256i) { vpmovusdbmem256(mem_addr, a.as_i32x8(), k); @@ -34046,7 +34046,7 @@ pub unsafe fn _mm256_mask_cvtusepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi32_storeu_epi8&expand=2069) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusdb))] pub unsafe fn _mm_mask_cvtusepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovusdbmem128(mem_addr, a.as_i32x4(), k); @@ -34057,7 +34057,7 @@ pub unsafe fn _mm_mask_cvtusepi32_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi64_storeu_epi16&expand=1513) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub unsafe fn _mm512_mask_cvtepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m512i) { vpmovqwmem(mem_addr.cast(), a.as_i64x8(), k); @@ -34068,7 +34068,7 @@ pub unsafe fn _mm512_mask_cvtepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi64_storeu_epi16&expand=1512) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub unsafe fn _mm256_mask_cvtepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m256i) { vpmovqwmem256(mem_addr.cast(), a.as_i64x4(), k); @@ -34079,7 +34079,7 @@ pub unsafe fn _mm256_mask_cvtepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi64_storeu_epi16&expand=1511) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqw))] pub unsafe fn _mm_mask_cvtepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m128i) { vpmovqwmem128(mem_addr.cast(), a.as_i64x2(), k); @@ -34090,7 +34090,7 @@ pub unsafe fn _mm_mask_cvtepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi64_storeu_epi16&expand=1866) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub unsafe fn _mm512_mask_cvtsepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m512i) { vpmovsqwmem(mem_addr.cast(), a.as_i64x8(), k); @@ -34101,7 +34101,7 @@ pub unsafe fn _mm512_mask_cvtsepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi64_storeu_epi16&expand=1865) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub unsafe fn _mm256_mask_cvtsepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m256i) { vpmovsqwmem256(mem_addr.cast(), a.as_i64x4(), k); @@ -34112,7 +34112,7 @@ pub unsafe fn _mm256_mask_cvtsepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi64_storeu_epi16&expand=1864) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqw))] pub unsafe fn _mm_mask_cvtsepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m128i) { vpmovsqwmem128(mem_addr.cast(), a.as_i64x2(), k); @@ -34123,7 +34123,7 @@ pub unsafe fn _mm_mask_cvtsepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi64_storeu_epi16&expand=2101) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub unsafe fn _mm512_mask_cvtusepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m512i) { vpmovusqwmem(mem_addr.cast(), a.as_i64x8(), k); @@ -34134,7 +34134,7 @@ pub unsafe fn _mm512_mask_cvtusepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi64_storeu_epi16&expand=2100) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub unsafe fn _mm256_mask_cvtusepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m256i) { vpmovusqwmem256(mem_addr.cast(), a.as_i64x4(), k); @@ -34145,7 +34145,7 @@ pub unsafe fn _mm256_mask_cvtusepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi64_storeu_epi16&expand=2099) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqw))] pub unsafe fn _mm_mask_cvtusepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, a: __m128i) { vpmovusqwmem128(mem_addr.cast(), a.as_i64x2(), k); @@ -34156,7 +34156,7 @@ pub unsafe fn _mm_mask_cvtusepi64_storeu_epi16(mem_addr: *mut i16, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi64_storeu_epi8&expand=1519) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub unsafe fn _mm512_mask_cvtepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m512i) { vpmovqbmem(mem_addr, a.as_i64x8(), k); @@ -34167,7 +34167,7 @@ pub unsafe fn _mm512_mask_cvtepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi64_storeu_epi8&expand=1518) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub unsafe fn _mm256_mask_cvtepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m256i) { vpmovqbmem256(mem_addr, a.as_i64x4(), k); @@ -34178,7 +34178,7 @@ pub unsafe fn _mm256_mask_cvtepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi64_storeu_epi8&expand=1517) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqb))] pub unsafe fn _mm_mask_cvtepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovqbmem128(mem_addr, a.as_i64x2(), k); @@ -34189,7 +34189,7 @@ pub unsafe fn _mm_mask_cvtepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi64_storeu_epi8&expand=1872) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub unsafe fn _mm512_mask_cvtsepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m512i) { vpmovsqbmem(mem_addr, a.as_i64x8(), k); @@ -34200,7 +34200,7 @@ pub unsafe fn _mm512_mask_cvtsepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi64_storeu_epi8&expand=1871) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub unsafe fn _mm256_mask_cvtsepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m256i) { vpmovsqbmem256(mem_addr, a.as_i64x4(), k); @@ -34211,7 +34211,7 @@ pub unsafe fn _mm256_mask_cvtsepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi64_storeu_epi8&expand=1870) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqb))] pub unsafe fn _mm_mask_cvtsepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovsqbmem128(mem_addr, a.as_i64x2(), k); @@ -34222,7 +34222,7 @@ pub unsafe fn _mm_mask_cvtsepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi64_storeu_epi8&expand=2107) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub unsafe fn _mm512_mask_cvtusepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m512i) { vpmovusqbmem(mem_addr, a.as_i64x8(), k); @@ -34233,7 +34233,7 @@ pub unsafe fn _mm512_mask_cvtusepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi64_storeu_epi8&expand=2106) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub unsafe fn _mm256_mask_cvtusepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m256i) { vpmovusqbmem256(mem_addr, a.as_i64x4(), k); @@ -34244,7 +34244,7 @@ pub unsafe fn _mm256_mask_cvtusepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi64_storeu_epi8&expand=2105) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqb))] pub unsafe fn _mm_mask_cvtusepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { vpmovusqbmem128(mem_addr, a.as_i64x2(), k); @@ -34255,7 +34255,7 @@ pub unsafe fn _mm_mask_cvtusepi64_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi64_storeu_epi32&expand=1516) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub unsafe fn _mm512_mask_cvtepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m512i) { vpmovqdmem(mem_addr.cast(), a.as_i64x8(), k); @@ -34266,7 +34266,7 @@ pub unsafe fn _mm512_mask_cvtepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi64_storeu_epi32&expand=1515) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub unsafe fn _mm256_mask_cvtepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m256i) { vpmovqdmem256(mem_addr.cast(), a.as_i64x4(), k); @@ -34277,7 +34277,7 @@ pub unsafe fn _mm256_mask_cvtepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi64_storeu_epi32&expand=1514) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovqd))] pub unsafe fn _mm_mask_cvtepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m128i) { vpmovqdmem128(mem_addr.cast(), a.as_i64x2(), k); @@ -34288,7 +34288,7 @@ pub unsafe fn _mm_mask_cvtepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi64_storeu_epi32&expand=1869) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub unsafe fn _mm512_mask_cvtsepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m512i) { vpmovsqdmem(mem_addr.cast(), a.as_i64x8(), k); @@ -34299,7 +34299,7 @@ pub unsafe fn _mm512_mask_cvtsepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi64_storeu_epi32&expand=1868) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub unsafe fn _mm256_mask_cvtsepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m256i) { vpmovsqdmem256(mem_addr.cast(), a.as_i64x4(), k); @@ -34310,7 +34310,7 @@ pub unsafe fn _mm256_mask_cvtsepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi64_storeu_epi32&expand=1867) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovsqd))] pub unsafe fn _mm_mask_cvtsepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m128i) { vpmovsqdmem128(mem_addr.cast(), a.as_i64x2(), k); @@ -34321,7 +34321,7 @@ pub unsafe fn _mm_mask_cvtsepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi64_storeu_epi32&expand=2104) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub unsafe fn _mm512_mask_cvtusepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m512i) { vpmovusqdmem(mem_addr.cast(), a.as_i64x8(), k); @@ -34332,7 +34332,7 @@ pub unsafe fn _mm512_mask_cvtusepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi64_storeu_epi32&expand=2103) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub unsafe fn _mm256_mask_cvtusepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m256i) { vpmovusqdmem256(mem_addr.cast(), a.as_i64x4(), k); @@ -34343,7 +34343,7 @@ pub unsafe fn _mm256_mask_cvtusepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi64_storeu_epi32&expand=2102) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovusqd))] pub unsafe fn _mm_mask_cvtusepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, a: __m128i) { vpmovusqdmem128(mem_addr.cast(), a.as_i64x2(), k); @@ -34354,7 +34354,7 @@ pub unsafe fn _mm_mask_cvtusepi64_storeu_epi32(mem_addr: *mut i32, k: __mmask8, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_epi32&expand=5628) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32 pub unsafe fn _mm512_storeu_epi32(mem_addr: *mut i32, a: __m512i) { ptr::write_unaligned(mem_addr as *mut __m512i, a); @@ -34365,7 +34365,7 @@ pub unsafe fn _mm512_storeu_epi32(mem_addr: *mut i32, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_storeu_epi32&expand=5626) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32 pub unsafe fn _mm256_storeu_epi32(mem_addr: *mut i32, a: __m256i) { ptr::write_unaligned(mem_addr as *mut __m256i, a); @@ -34376,7 +34376,7 @@ pub unsafe fn _mm256_storeu_epi32(mem_addr: *mut i32, a: __m256i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeu_epi32&expand=5624) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32 pub unsafe fn _mm_storeu_epi32(mem_addr: *mut i32, a: __m128i) { ptr::write_unaligned(mem_addr as *mut __m128i, a); @@ -34387,7 +34387,7 @@ pub unsafe fn _mm_storeu_epi32(mem_addr: *mut i32, a: __m128i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_epi64&expand=3386) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64 pub unsafe fn _mm512_loadu_epi64(mem_addr: *const i64) -> __m512i { ptr::read_unaligned(mem_addr as *const __m512i) @@ -34398,7 +34398,7 @@ pub unsafe fn _mm512_loadu_epi64(mem_addr: *const i64) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_loadu_epi64&expand=3383) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64 pub unsafe fn _mm256_loadu_epi64(mem_addr: *const i64) -> __m256i { ptr::read_unaligned(mem_addr as *const __m256i) @@ -34409,7 +34409,7 @@ pub unsafe fn _mm256_loadu_epi64(mem_addr: *const i64) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadu_epi64&expand=3380) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64 pub unsafe fn _mm_loadu_epi64(mem_addr: *const i64) -> __m128i { ptr::read_unaligned(mem_addr as *const __m128i) @@ -34420,7 +34420,7 @@ pub unsafe fn _mm_loadu_epi64(mem_addr: *const i64) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_epi64&expand=5634) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64 pub unsafe fn _mm512_storeu_epi64(mem_addr: *mut i64, a: __m512i) { ptr::write_unaligned(mem_addr as *mut __m512i, a); @@ -34431,7 +34431,7 @@ pub unsafe fn _mm512_storeu_epi64(mem_addr: *mut i64, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_storeu_epi64&expand=5632) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64 pub unsafe fn _mm256_storeu_epi64(mem_addr: *mut i64, a: __m256i) { ptr::write_unaligned(mem_addr as *mut __m256i, a); @@ -34442,7 +34442,7 @@ pub unsafe fn _mm256_storeu_epi64(mem_addr: *mut i64, a: __m256i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeu_epi64&expand=5630) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu64 pub unsafe fn _mm_storeu_epi64(mem_addr: *mut i64, a: __m128i) { ptr::write_unaligned(mem_addr as *mut __m128i, a); @@ -34453,7 +34453,7 @@ pub unsafe fn _mm_storeu_epi64(mem_addr: *mut i64, a: __m128i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_si512&expand=3420) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32 pub unsafe fn _mm512_loadu_si512(mem_addr: *const __m512i) -> __m512i { ptr::read_unaligned(mem_addr) @@ -34464,7 +34464,7 @@ pub unsafe fn _mm512_loadu_si512(mem_addr: *const __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_si512&expand=5657) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu32 pub unsafe fn _mm512_storeu_si512(mem_addr: *mut __m512i, a: __m512i) { ptr::write_unaligned(mem_addr, a); @@ -34477,7 +34477,7 @@ pub unsafe fn _mm512_storeu_si512(mem_addr: *mut __m512i, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_pd) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] pub unsafe fn _mm512_loadu_pd(mem_addr: *const f64) -> __m512d { ptr::read_unaligned(mem_addr as *const __m512d) @@ -34490,7 +34490,7 @@ pub unsafe fn _mm512_loadu_pd(mem_addr: *const f64) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_pd) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] pub unsafe fn _mm512_storeu_pd(mem_addr: *mut f64, a: __m512d) { ptr::write_unaligned(mem_addr as *mut __m512d, a); @@ -34503,7 +34503,7 @@ pub unsafe fn _mm512_storeu_pd(mem_addr: *mut f64, a: __m512d) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_ps) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] pub unsafe fn _mm512_loadu_ps(mem_addr: *const f32) -> __m512 { ptr::read_unaligned(mem_addr as *const __m512) @@ -34516,7 +34516,7 @@ pub unsafe fn _mm512_loadu_ps(mem_addr: *const f32) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_ps) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovups))] pub unsafe fn _mm512_storeu_ps(mem_addr: *mut f32, a: __m512) { ptr::write_unaligned(mem_addr as *mut __m512, a); @@ -34527,7 +34527,7 @@ pub unsafe fn _mm512_storeu_ps(mem_addr: *mut f32, a: __m512) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_load_si512&expand=3345) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34541,7 +34541,7 @@ pub unsafe fn _mm512_load_si512(mem_addr: *const __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_store_si512&expand=5598) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34555,7 +34555,7 @@ pub unsafe fn _mm512_store_si512(mem_addr: *mut __m512i, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_load_epi32&expand=3304) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34569,7 +34569,7 @@ pub unsafe fn _mm512_load_epi32(mem_addr: *const i32) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_load_epi32&expand=3301) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34583,7 +34583,7 @@ pub unsafe fn _mm256_load_epi32(mem_addr: *const i32) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_epi32&expand=3298) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34597,7 +34597,7 @@ pub unsafe fn _mm_load_epi32(mem_addr: *const i32) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_store_epi32&expand=5569) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34611,7 +34611,7 @@ pub unsafe fn _mm512_store_epi32(mem_addr: *mut i32, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_store_epi32&expand=5567) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34625,7 +34625,7 @@ pub unsafe fn _mm256_store_epi32(mem_addr: *mut i32, a: __m256i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_epi32&expand=5565) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34639,7 +34639,7 @@ pub unsafe fn _mm_store_epi32(mem_addr: *mut i32, a: __m128i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_load_epi64&expand=3313) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34653,7 +34653,7 @@ pub unsafe fn _mm512_load_epi64(mem_addr: *const i64) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_load_epi64&expand=3310) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34667,7 +34667,7 @@ pub unsafe fn _mm256_load_epi64(mem_addr: *const i64) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_epi64&expand=3307) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34681,7 +34681,7 @@ pub unsafe fn _mm_load_epi64(mem_addr: *const i64) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_store_epi64&expand=5575) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34695,7 +34695,7 @@ pub unsafe fn _mm512_store_epi64(mem_addr: *mut i64, a: __m512i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_store_epi64&expand=5573) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34709,7 +34709,7 @@ pub unsafe fn _mm256_store_epi64(mem_addr: *mut i64, a: __m256i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_epi64&expand=5571) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34723,7 +34723,7 @@ pub unsafe fn _mm_store_epi64(mem_addr: *mut i64, a: __m128i) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_load_ps&expand=3336) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34737,7 +34737,7 @@ pub unsafe fn _mm512_load_ps(mem_addr: *const f32) -> __m512 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_store_ps&expand=5592) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34751,7 +34751,7 @@ pub unsafe fn _mm512_store_ps(mem_addr: *mut f32, a: __m512) { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_load_pd&expand=3326) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34765,7 +34765,7 @@ pub unsafe fn _mm512_load_pd(mem_addr: *const f64) -> __m512d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_store_pd&expand=5585) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr( all(test, not(all(target_arch = "x86", target_env = "msvc"))), assert_instr(vmovaps) @@ -34782,7 +34782,7 @@ pub unsafe fn _mm512_store_pd(mem_addr: *mut f64, a: __m512d) { #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_loadu_epi32(src: __m512i, k: __mmask16, mem_addr: *const i32) -> __m512i { transmute(loaddqu32_512(mem_addr, src.as_i32x16(), k)) } @@ -34795,7 +34795,7 @@ pub unsafe fn _mm512_mask_loadu_epi32(src: __m512i, k: __mmask16, mem_addr: *con #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_loadu_epi32(k: __mmask16, mem_addr: *const i32) -> __m512i { _mm512_mask_loadu_epi32(_mm512_setzero_si512(), k, mem_addr) } @@ -34808,7 +34808,7 @@ pub unsafe fn _mm512_maskz_loadu_epi32(k: __mmask16, mem_addr: *const i32) -> __ #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_loadu_epi64(src: __m512i, k: __mmask8, mem_addr: *const i64) -> __m512i { transmute(loaddqu64_512(mem_addr, src.as_i64x8(), k)) } @@ -34821,7 +34821,7 @@ pub unsafe fn _mm512_mask_loadu_epi64(src: __m512i, k: __mmask8, mem_addr: *cons #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m512i { _mm512_mask_loadu_epi64(_mm512_setzero_si512(), k, mem_addr) } @@ -34834,7 +34834,7 @@ pub unsafe fn _mm512_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_loadu_ps(src: __m512, k: __mmask16, mem_addr: *const f32) -> __m512 { transmute(loadups_512(mem_addr, src.as_f32x16(), k)) } @@ -34847,7 +34847,7 @@ pub unsafe fn _mm512_mask_loadu_ps(src: __m512, k: __mmask16, mem_addr: *const f #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_loadu_ps(k: __mmask16, mem_addr: *const f32) -> __m512 { _mm512_mask_loadu_ps(_mm512_setzero_ps(), k, mem_addr) } @@ -34860,7 +34860,7 @@ pub unsafe fn _mm512_maskz_loadu_ps(k: __mmask16, mem_addr: *const f32) -> __m51 #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_loadu_pd(src: __m512d, k: __mmask8, mem_addr: *const f64) -> __m512d { transmute(loadupd_512(mem_addr, src.as_f64x8(), k)) } @@ -34873,7 +34873,7 @@ pub unsafe fn _mm512_mask_loadu_pd(src: __m512d, k: __mmask8, mem_addr: *const f #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m512d { _mm512_mask_loadu_pd(_mm512_setzero_pd(), k, mem_addr) } @@ -34886,7 +34886,7 @@ pub unsafe fn _mm512_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m512 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_loadu_epi32(src: __m256i, k: __mmask8, mem_addr: *const i32) -> __m256i { transmute(loaddqu32_256(mem_addr, src.as_i32x8(), k)) } @@ -34899,7 +34899,7 @@ pub unsafe fn _mm256_mask_loadu_epi32(src: __m256i, k: __mmask8, mem_addr: *cons #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m256i { _mm256_mask_loadu_epi32(_mm256_setzero_si256(), k, mem_addr) } @@ -34912,7 +34912,7 @@ pub unsafe fn _mm256_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_loadu_epi64(src: __m256i, k: __mmask8, mem_addr: *const i64) -> __m256i { transmute(loaddqu64_256(mem_addr, src.as_i64x4(), k)) } @@ -34925,7 +34925,7 @@ pub unsafe fn _mm256_mask_loadu_epi64(src: __m256i, k: __mmask8, mem_addr: *cons #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m256i { _mm256_mask_loadu_epi64(_mm256_setzero_si256(), k, mem_addr) } @@ -34938,7 +34938,7 @@ pub unsafe fn _mm256_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_loadu_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 { transmute(loadups_256(mem_addr, src.as_f32x8(), k)) } @@ -34951,7 +34951,7 @@ pub unsafe fn _mm256_mask_loadu_ps(src: __m256, k: __mmask8, mem_addr: *const f3 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m256 { _mm256_mask_loadu_ps(_mm256_setzero_ps(), k, mem_addr) } @@ -34964,7 +34964,7 @@ pub unsafe fn _mm256_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m256 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_loadu_pd(src: __m256d, k: __mmask8, mem_addr: *const f64) -> __m256d { transmute(loadupd_256(mem_addr, src.as_f64x4(), k)) } @@ -34977,7 +34977,7 @@ pub unsafe fn _mm256_mask_loadu_pd(src: __m256d, k: __mmask8, mem_addr: *const f #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m256d { _mm256_mask_loadu_pd(_mm256_setzero_pd(), k, mem_addr) } @@ -34990,7 +34990,7 @@ pub unsafe fn _mm256_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m256 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_loadu_epi32(src: __m128i, k: __mmask8, mem_addr: *const i32) -> __m128i { transmute(loaddqu32_128(mem_addr, src.as_i32x4(), k)) } @@ -35003,7 +35003,7 @@ pub unsafe fn _mm_mask_loadu_epi32(src: __m128i, k: __mmask8, mem_addr: *const i #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i { _mm_mask_loadu_epi32(_mm_setzero_si128(), k, mem_addr) } @@ -35016,7 +35016,7 @@ pub unsafe fn _mm_maskz_loadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m128 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_loadu_epi64(src: __m128i, k: __mmask8, mem_addr: *const i64) -> __m128i { transmute(loaddqu64_128(mem_addr, src.as_i64x2(), k)) } @@ -35029,7 +35029,7 @@ pub unsafe fn _mm_mask_loadu_epi64(src: __m128i, k: __mmask8, mem_addr: *const i #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i { _mm_mask_loadu_epi64(_mm_setzero_si128(), k, mem_addr) } @@ -35042,7 +35042,7 @@ pub unsafe fn _mm_maskz_loadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m128 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_loadu_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 { transmute(loadups_128(mem_addr, src.as_f32x4(), k)) } @@ -35055,7 +35055,7 @@ pub unsafe fn _mm_mask_loadu_ps(src: __m128, k: __mmask8, mem_addr: *const f32) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m128 { _mm_mask_loadu_ps(_mm_setzero_ps(), k, mem_addr) } @@ -35068,7 +35068,7 @@ pub unsafe fn _mm_maskz_loadu_ps(k: __mmask8, mem_addr: *const f32) -> __m128 { #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_loadu_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d { transmute(loadupd_128(mem_addr, src.as_f64x2(), k)) } @@ -35081,7 +35081,7 @@ pub unsafe fn _mm_mask_loadu_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m128d { _mm_mask_loadu_pd(_mm_setzero_pd(), k, mem_addr) } @@ -35094,7 +35094,7 @@ pub unsafe fn _mm_maskz_loadu_pd(k: __mmask8, mem_addr: *const f64) -> __m128d { #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_load_epi32(src: __m512i, k: __mmask16, mem_addr: *const i32) -> __m512i { transmute(loaddqa32_512(mem_addr, src.as_i32x16(), k)) } @@ -35107,7 +35107,7 @@ pub unsafe fn _mm512_mask_load_epi32(src: __m512i, k: __mmask16, mem_addr: *cons #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_load_epi32(k: __mmask16, mem_addr: *const i32) -> __m512i { _mm512_mask_load_epi32(_mm512_setzero_si512(), k, mem_addr) } @@ -35120,7 +35120,7 @@ pub unsafe fn _mm512_maskz_load_epi32(k: __mmask16, mem_addr: *const i32) -> __m #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_load_epi64(src: __m512i, k: __mmask8, mem_addr: *const i64) -> __m512i { transmute(loaddqa64_512(mem_addr, src.as_i64x8(), k)) } @@ -35133,7 +35133,7 @@ pub unsafe fn _mm512_mask_load_epi64(src: __m512i, k: __mmask8, mem_addr: *const #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m512i { _mm512_mask_load_epi64(_mm512_setzero_si512(), k, mem_addr) } @@ -35146,7 +35146,7 @@ pub unsafe fn _mm512_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m5 #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_load_ps(src: __m512, k: __mmask16, mem_addr: *const f32) -> __m512 { transmute(loadaps_512(mem_addr, src.as_f32x16(), k)) } @@ -35159,7 +35159,7 @@ pub unsafe fn _mm512_mask_load_ps(src: __m512, k: __mmask16, mem_addr: *const f3 #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_load_ps(k: __mmask16, mem_addr: *const f32) -> __m512 { _mm512_mask_load_ps(_mm512_setzero_ps(), k, mem_addr) } @@ -35172,7 +35172,7 @@ pub unsafe fn _mm512_maskz_load_ps(k: __mmask16, mem_addr: *const f32) -> __m512 #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_load_pd(src: __m512d, k: __mmask8, mem_addr: *const f64) -> __m512d { transmute(loadapd_512(mem_addr, src.as_f64x8(), k)) } @@ -35185,7 +35185,7 @@ pub unsafe fn _mm512_mask_load_pd(src: __m512d, k: __mmask8, mem_addr: *const f6 #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m512d { _mm512_mask_load_pd(_mm512_setzero_pd(), k, mem_addr) } @@ -35198,7 +35198,7 @@ pub unsafe fn _mm512_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m512d #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_load_epi32(src: __m256i, k: __mmask8, mem_addr: *const i32) -> __m256i { transmute(loaddqa32_256(mem_addr, src.as_i32x8(), k)) } @@ -35211,7 +35211,7 @@ pub unsafe fn _mm256_mask_load_epi32(src: __m256i, k: __mmask8, mem_addr: *const #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m256i { _mm256_mask_load_epi32(_mm256_setzero_si256(), k, mem_addr) } @@ -35224,7 +35224,7 @@ pub unsafe fn _mm256_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m2 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_load_epi64(src: __m256i, k: __mmask8, mem_addr: *const i64) -> __m256i { transmute(loaddqa64_256(mem_addr, src.as_i64x4(), k)) } @@ -35237,7 +35237,7 @@ pub unsafe fn _mm256_mask_load_epi64(src: __m256i, k: __mmask8, mem_addr: *const #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m256i { _mm256_mask_load_epi64(_mm256_setzero_si256(), k, mem_addr) } @@ -35250,7 +35250,7 @@ pub unsafe fn _mm256_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m2 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_load_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 { transmute(loadaps_256(mem_addr, src.as_f32x8(), k)) } @@ -35263,7 +35263,7 @@ pub unsafe fn _mm256_mask_load_ps(src: __m256, k: __mmask8, mem_addr: *const f32 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m256 { _mm256_mask_load_ps(_mm256_setzero_ps(), k, mem_addr) } @@ -35276,7 +35276,7 @@ pub unsafe fn _mm256_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m256 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_load_pd(src: __m256d, k: __mmask8, mem_addr: *const f64) -> __m256d { transmute(loadapd_256(mem_addr, src.as_f64x4(), k)) } @@ -35289,7 +35289,7 @@ pub unsafe fn _mm256_mask_load_pd(src: __m256d, k: __mmask8, mem_addr: *const f6 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m256d { _mm256_mask_load_pd(_mm256_setzero_pd(), k, mem_addr) } @@ -35302,7 +35302,7 @@ pub unsafe fn _mm256_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m256d #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_load_epi32(src: __m128i, k: __mmask8, mem_addr: *const i32) -> __m128i { transmute(loaddqa32_128(mem_addr, src.as_i32x4(), k)) } @@ -35315,7 +35315,7 @@ pub unsafe fn _mm_mask_load_epi32(src: __m128i, k: __mmask8, mem_addr: *const i3 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i { _mm_mask_load_epi32(_mm_setzero_si128(), k, mem_addr) } @@ -35328,7 +35328,7 @@ pub unsafe fn _mm_maskz_load_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_load_epi64(src: __m128i, k: __mmask8, mem_addr: *const i64) -> __m128i { transmute(loaddqa64_128(mem_addr, src.as_i64x2(), k)) } @@ -35341,7 +35341,7 @@ pub unsafe fn _mm_mask_load_epi64(src: __m128i, k: __mmask8, mem_addr: *const i6 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i { _mm_mask_load_epi64(_mm_setzero_si128(), k, mem_addr) } @@ -35354,7 +35354,7 @@ pub unsafe fn _mm_maskz_load_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_load_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 { transmute(loadaps_128(mem_addr, src.as_f32x4(), k)) } @@ -35367,7 +35367,7 @@ pub unsafe fn _mm_mask_load_ps(src: __m128, k: __mmask8, mem_addr: *const f32) - #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m128 { _mm_mask_load_ps(_mm_setzero_ps(), k, mem_addr) } @@ -35380,7 +35380,7 @@ pub unsafe fn _mm_maskz_load_ps(k: __mmask8, mem_addr: *const f32) -> __m128 { #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_load_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d { transmute(loadapd_128(mem_addr, src.as_f64x2(), k)) } @@ -35393,7 +35393,7 @@ pub unsafe fn _mm_mask_load_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m128d { _mm_mask_load_pd(_mm_setzero_pd(), k, mem_addr) } @@ -35407,7 +35407,7 @@ pub unsafe fn _mm_maskz_load_pd(k: __mmask8, mem_addr: *const f64) -> __m128d { #[inline] #[cfg_attr(test, assert_instr(vmovss))] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_load_ss(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 { let mut dst: __m128 = src; asm!( @@ -35429,7 +35429,7 @@ pub unsafe fn _mm_mask_load_ss(src: __m128, k: __mmask8, mem_addr: *const f32) - #[inline] #[cfg_attr(test, assert_instr(vmovss))] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_load_ss(k: __mmask8, mem_addr: *const f32) -> __m128 { let mut dst: __m128; asm!( @@ -35451,7 +35451,7 @@ pub unsafe fn _mm_maskz_load_ss(k: __mmask8, mem_addr: *const f32) -> __m128 { #[inline] #[cfg_attr(test, assert_instr(vmovsd))] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_load_sd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d { let mut dst: __m128d = src; asm!( @@ -35473,7 +35473,7 @@ pub unsafe fn _mm_mask_load_sd(src: __m128d, k: __mmask8, mem_addr: *const f64) #[inline] #[cfg_attr(test, assert_instr(vmovsd))] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_load_sd(k: __mmask8, mem_addr: *const f64) -> __m128d { let mut dst: __m128d; asm!( @@ -35493,7 +35493,7 @@ pub unsafe fn _mm_maskz_load_sd(k: __mmask8, mem_addr: *const f64) -> __m128d { #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask16, a: __m512i) { storedqu32_512(mem_addr, a.as_i32x16(), mask) } @@ -35505,7 +35505,7 @@ pub unsafe fn _mm512_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask16, a: _ #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m512i) { storedqu64_512(mem_addr, a.as_i64x8(), mask) } @@ -35517,7 +35517,7 @@ pub unsafe fn _mm512_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __ #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask16, a: __m512) { storeups_512(mem_addr, a.as_f32x16(), mask) } @@ -35529,7 +35529,7 @@ pub unsafe fn _mm512_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask16, a: __m5 #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512d) { storeupd_512(mem_addr, a.as_f64x8(), mask) } @@ -35541,7 +35541,7 @@ pub unsafe fn _mm512_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m256i) { storedqu32_256(mem_addr, a.as_i32x8(), mask) } @@ -35553,7 +35553,7 @@ pub unsafe fn _mm256_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __ #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m256i) { storedqu64_256(mem_addr, a.as_i64x4(), mask) } @@ -35565,7 +35565,7 @@ pub unsafe fn _mm256_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __ #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256) { storeups_256(mem_addr, a.as_f32x8(), mask) } @@ -35577,7 +35577,7 @@ pub unsafe fn _mm256_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m25 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256d) { storeupd_256(mem_addr, a.as_f64x4(), mask) } @@ -35589,7 +35589,7 @@ pub unsafe fn _mm256_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m25 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128i) { storedqu32_128(mem_addr, a.as_i32x4(), mask) } @@ -35601,7 +35601,7 @@ pub unsafe fn _mm_mask_storeu_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqu64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128i) { storedqu64_128(mem_addr, a.as_i64x2(), mask) } @@ -35613,7 +35613,7 @@ pub unsafe fn _mm_mask_storeu_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovups))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) { storeups_128(mem_addr, a.as_f32x4(), mask) } @@ -35625,7 +35625,7 @@ pub unsafe fn _mm_mask_storeu_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovupd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) { storeupd_128(mem_addr, a.as_f64x2(), mask) } @@ -35637,7 +35637,7 @@ pub unsafe fn _mm_mask_storeu_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_store_epi32(mem_addr: *mut i32, mask: __mmask16, a: __m512i) { storedqa32_512(mem_addr, a.as_i32x16(), mask) } @@ -35649,7 +35649,7 @@ pub unsafe fn _mm512_mask_store_epi32(mem_addr: *mut i32, mask: __mmask16, a: __ #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m512i) { storedqa64_512(mem_addr, a.as_i64x8(), mask) } @@ -35661,7 +35661,7 @@ pub unsafe fn _mm512_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_store_ps(mem_addr: *mut f32, mask: __mmask16, a: __m512) { storeaps_512(mem_addr, a.as_f32x16(), mask) } @@ -35673,7 +35673,7 @@ pub unsafe fn _mm512_mask_store_ps(mem_addr: *mut f32, mask: __mmask16, a: __m51 #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512d) { storeapd_512(mem_addr, a.as_f64x8(), mask) } @@ -35685,7 +35685,7 @@ pub unsafe fn _mm512_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m512 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m256i) { storedqa32_256(mem_addr, a.as_i32x8(), mask) } @@ -35697,7 +35697,7 @@ pub unsafe fn _mm256_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m256i) { storedqa64_256(mem_addr, a.as_i64x4(), mask) } @@ -35709,7 +35709,7 @@ pub unsafe fn _mm256_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256) { storeaps_256(mem_addr, a.as_f32x8(), mask) } @@ -35721,7 +35721,7 @@ pub unsafe fn _mm256_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m256 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256d) { storeapd_256(mem_addr, a.as_f64x4(), mask) } @@ -35733,7 +35733,7 @@ pub unsafe fn _mm256_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m256 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa32))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128i) { storedqa32_128(mem_addr, a.as_i32x4(), mask) } @@ -35745,7 +35745,7 @@ pub unsafe fn _mm_mask_store_epi32(mem_addr: *mut i32, mask: __mmask8, a: __m128 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovdqa64))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128i) { storedqa64_128(mem_addr, a.as_i64x2(), mask) } @@ -35757,7 +35757,7 @@ pub unsafe fn _mm_mask_store_epi64(mem_addr: *mut i64, mask: __mmask8, a: __m128 #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovaps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) { storeaps_128(mem_addr, a.as_f32x4(), mask) } @@ -35769,7 +35769,7 @@ pub unsafe fn _mm_mask_store_ps(mem_addr: *mut f32, mask: __mmask8, a: __m128) { #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vmovapd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) { storeapd_128(mem_addr, a.as_f64x2(), mask) } @@ -35781,7 +35781,7 @@ pub unsafe fn _mm_mask_store_pd(mem_addr: *mut f64, mask: __mmask8, a: __m128d) #[inline] #[cfg_attr(test, assert_instr(vmovss))] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_store_ss(mem_addr: *mut f32, k: __mmask8, a: __m128) { asm!( vps!("vmovss", "{{{k}}}, {a}"), @@ -35799,7 +35799,7 @@ pub unsafe fn _mm_mask_store_ss(mem_addr: *mut f32, k: __mmask8, a: __m128) { #[inline] #[cfg_attr(test, assert_instr(vmovsd))] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_store_sd(mem_addr: *mut f64, k: __mmask8, a: __m128d) { asm!( vps!("vmovsd", "{{{k}}}, {a}"), @@ -35816,7 +35816,7 @@ pub unsafe fn _mm_mask_store_sd(mem_addr: *mut f64, k: __mmask8, a: __m128d) { #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vpexpandd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_expandloadu_epi32( src: __m512i, k: __mmask16, @@ -35831,7 +35831,7 @@ pub unsafe fn _mm512_mask_expandloadu_epi32( #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vpexpandd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_expandloadu_epi32(k: __mmask16, mem_addr: *const i32) -> __m512i { _mm512_mask_expandloadu_epi32(_mm512_setzero_si512(), k, mem_addr) } @@ -35842,7 +35842,7 @@ pub unsafe fn _mm512_maskz_expandloadu_epi32(k: __mmask16, mem_addr: *const i32) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_expandloadu_epi32( src: __m256i, k: __mmask8, @@ -35857,7 +35857,7 @@ pub unsafe fn _mm256_mask_expandloadu_epi32( #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_expandloadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m256i { _mm256_mask_expandloadu_epi32(_mm256_setzero_si256(), k, mem_addr) } @@ -35868,7 +35868,7 @@ pub unsafe fn _mm256_maskz_expandloadu_epi32(k: __mmask8, mem_addr: *const i32) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_expandloadu_epi32( src: __m128i, k: __mmask8, @@ -35883,7 +35883,7 @@ pub unsafe fn _mm_mask_expandloadu_epi32( #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_expandloadu_epi32(k: __mmask8, mem_addr: *const i32) -> __m128i { _mm_mask_expandloadu_epi32(_mm_setzero_si128(), k, mem_addr) } @@ -35894,7 +35894,7 @@ pub unsafe fn _mm_maskz_expandloadu_epi32(k: __mmask8, mem_addr: *const i32) -> #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vpexpandq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_expandloadu_epi64( src: __m512i, k: __mmask8, @@ -35909,7 +35909,7 @@ pub unsafe fn _mm512_mask_expandloadu_epi64( #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vpexpandq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_expandloadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m512i { _mm512_mask_expandloadu_epi64(_mm512_setzero_si512(), k, mem_addr) } @@ -35920,7 +35920,7 @@ pub unsafe fn _mm512_maskz_expandloadu_epi64(k: __mmask8, mem_addr: *const i64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_expandloadu_epi64( src: __m256i, k: __mmask8, @@ -35935,7 +35935,7 @@ pub unsafe fn _mm256_mask_expandloadu_epi64( #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_expandloadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m256i { _mm256_mask_expandloadu_epi64(_mm256_setzero_si256(), k, mem_addr) } @@ -35946,7 +35946,7 @@ pub unsafe fn _mm256_maskz_expandloadu_epi64(k: __mmask8, mem_addr: *const i64) #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_expandloadu_epi64( src: __m128i, k: __mmask8, @@ -35961,7 +35961,7 @@ pub unsafe fn _mm_mask_expandloadu_epi64( #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandq))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_expandloadu_epi64(k: __mmask8, mem_addr: *const i64) -> __m128i { _mm_mask_expandloadu_epi64(_mm_setzero_si128(), k, mem_addr) } @@ -35972,7 +35972,7 @@ pub unsafe fn _mm_maskz_expandloadu_epi64(k: __mmask8, mem_addr: *const i64) -> #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vexpandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_expandloadu_ps( src: __m512, k: __mmask16, @@ -35987,7 +35987,7 @@ pub unsafe fn _mm512_mask_expandloadu_ps( #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vexpandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_expandloadu_ps(k: __mmask16, mem_addr: *const f32) -> __m512 { _mm512_mask_expandloadu_ps(_mm512_setzero_ps(), k, mem_addr) } @@ -35998,7 +35998,7 @@ pub unsafe fn _mm512_maskz_expandloadu_ps(k: __mmask16, mem_addr: *const f32) -> #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vexpandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_expandloadu_ps(src: __m256, k: __mmask8, mem_addr: *const f32) -> __m256 { transmute(expandloadps_256(mem_addr, src.as_f32x8(), k)) } @@ -36009,7 +36009,7 @@ pub unsafe fn _mm256_mask_expandloadu_ps(src: __m256, k: __mmask8, mem_addr: *co #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vexpandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_expandloadu_ps(k: __mmask8, mem_addr: *const f32) -> __m256 { _mm256_mask_expandloadu_ps(_mm256_setzero_ps(), k, mem_addr) } @@ -36020,7 +36020,7 @@ pub unsafe fn _mm256_maskz_expandloadu_ps(k: __mmask8, mem_addr: *const f32) -> #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vexpandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_expandloadu_ps(src: __m128, k: __mmask8, mem_addr: *const f32) -> __m128 { transmute(expandloadps_128(mem_addr, src.as_f32x4(), k)) } @@ -36031,7 +36031,7 @@ pub unsafe fn _mm_mask_expandloadu_ps(src: __m128, k: __mmask8, mem_addr: *const #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vexpandps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_expandloadu_ps(k: __mmask8, mem_addr: *const f32) -> __m128 { _mm_mask_expandloadu_ps(_mm_setzero_ps(), k, mem_addr) } @@ -36042,7 +36042,7 @@ pub unsafe fn _mm_maskz_expandloadu_ps(k: __mmask8, mem_addr: *const f32) -> __m #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vexpandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_expandloadu_pd( src: __m512d, k: __mmask8, @@ -36057,7 +36057,7 @@ pub unsafe fn _mm512_mask_expandloadu_pd( #[inline] #[target_feature(enable = "avx512f")] #[cfg_attr(test, assert_instr(vexpandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) -> __m512d { _mm512_mask_expandloadu_pd(_mm512_setzero_pd(), k, mem_addr) } @@ -36068,7 +36068,7 @@ pub unsafe fn _mm512_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) -> #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vexpandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_expandloadu_pd( src: __m256d, k: __mmask8, @@ -36083,7 +36083,7 @@ pub unsafe fn _mm256_mask_expandloadu_pd( #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vexpandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) -> __m256d { _mm256_mask_expandloadu_pd(_mm256_setzero_pd(), k, mem_addr) } @@ -36094,7 +36094,7 @@ pub unsafe fn _mm256_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) -> #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vexpandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_expandloadu_pd(src: __m128d, k: __mmask8, mem_addr: *const f64) -> __m128d { transmute(expandloadpd_128(mem_addr, src.as_f64x2(), k)) } @@ -36105,7 +36105,7 @@ pub unsafe fn _mm_mask_expandloadu_pd(src: __m128d, k: __mmask8, mem_addr: *cons #[inline] #[target_feature(enable = "avx512f,avx512vl")] #[cfg_attr(test, assert_instr(vexpandpd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) -> __m128d { _mm_mask_expandloadu_pd(_mm_setzero_pd(), k, mem_addr) } @@ -36115,7 +36115,7 @@ pub unsafe fn _mm_maskz_expandloadu_pd(k: __mmask8, mem_addr: *const f64) -> __m /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_setr_pd&expand=5002) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_setr_pd( e0: f64, e1: f64, @@ -36137,7 +36137,7 @@ pub fn _mm512_setr_pd( /// [Intel's documentation]( https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_set_pd&expand=4924) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm512_set_pd( e0: f64, e1: f64, @@ -36156,7 +36156,7 @@ pub fn _mm512_set_pd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_move_ss&expand=3832) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovss))] pub fn _mm_mask_move_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36174,7 +36174,7 @@ pub fn _mm_mask_move_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_move_ss&expand=3833) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovss))] pub fn _mm_maskz_move_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36191,7 +36191,7 @@ pub fn _mm_maskz_move_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_move_sd&expand=3829) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsd))] pub fn _mm_mask_move_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36209,7 +36209,7 @@ pub fn _mm_mask_move_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_move_sd&expand=3830) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmovsd))] pub fn _mm_maskz_move_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36226,7 +36226,7 @@ pub fn _mm_maskz_move_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_add_ss&expand=159) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddss))] pub fn _mm_mask_add_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36246,7 +36246,7 @@ pub fn _mm_mask_add_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_add_ss&expand=160) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddss))] pub fn _mm_maskz_add_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36265,7 +36265,7 @@ pub fn _mm_maskz_add_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_add_sd&expand=155) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddsd))] pub fn _mm_mask_add_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36285,7 +36285,7 @@ pub fn _mm_mask_add_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_add_sd&expand=156) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddsd))] pub fn _mm_maskz_add_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36304,7 +36304,7 @@ pub fn _mm_maskz_add_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_sub_ss&expand=5750) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubss))] pub fn _mm_mask_sub_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36324,7 +36324,7 @@ pub fn _mm_mask_sub_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_sub_ss&expand=5751) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubss))] pub fn _mm_maskz_sub_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36343,7 +36343,7 @@ pub fn _mm_maskz_sub_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_sub_sd&expand=5746) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubsd))] pub fn _mm_mask_sub_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36363,7 +36363,7 @@ pub fn _mm_mask_sub_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_sub_sd&expand=5747) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubsd))] pub fn _mm_maskz_sub_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36382,7 +36382,7 @@ pub fn _mm_maskz_sub_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_mul_ss&expand=3950) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulss))] pub fn _mm_mask_mul_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36402,7 +36402,7 @@ pub fn _mm_mask_mul_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_mul_ss&expand=3951) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulss))] pub fn _mm_maskz_mul_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36421,7 +36421,7 @@ pub fn _mm_maskz_mul_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_mul_sd&expand=3947) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulsd))] pub fn _mm_mask_mul_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36441,7 +36441,7 @@ pub fn _mm_mask_mul_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_mul_sd&expand=3948) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulsd))] pub fn _mm_maskz_mul_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36460,7 +36460,7 @@ pub fn _mm_maskz_mul_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_div_ss&expand=2181) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivss))] pub fn _mm_mask_div_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36480,7 +36480,7 @@ pub fn _mm_mask_div_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_div_ss&expand=2182) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivss))] pub fn _mm_maskz_div_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36499,7 +36499,7 @@ pub fn _mm_maskz_div_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_div_sd&expand=2178) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivsd))] pub fn _mm_mask_div_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36519,7 +36519,7 @@ pub fn _mm_mask_div_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_div_sd&expand=2179) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivsd))] pub fn _mm_maskz_div_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36538,7 +36538,7 @@ pub fn _mm_maskz_div_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_max_ss&expand=3672) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxss))] pub fn _mm_mask_max_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36557,7 +36557,7 @@ pub fn _mm_mask_max_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_max_ss&expand=3673) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxss))] pub fn _mm_maskz_max_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36576,7 +36576,7 @@ pub fn _mm_maskz_max_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_max_sd&expand=3669) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxsd))] pub fn _mm_mask_max_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36595,7 +36595,7 @@ pub fn _mm_mask_max_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_max_sd&expand=3670) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxsd))] pub fn _mm_maskz_max_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36614,7 +36614,7 @@ pub fn _mm_maskz_max_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_min_ss&expand=3786) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminss))] pub fn _mm_mask_min_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36633,7 +36633,7 @@ pub fn _mm_mask_min_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_min_ss&expand=3787) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminss))] pub fn _mm_maskz_min_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36652,7 +36652,7 @@ pub fn _mm_maskz_min_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_min_sd&expand=3783) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminsd))] pub fn _mm_mask_min_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36671,7 +36671,7 @@ pub fn _mm_mask_min_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_min_sd&expand=3784) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminsd))] pub fn _mm_maskz_min_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36690,7 +36690,7 @@ pub fn _mm_maskz_min_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_sqrt_ss&expand=5387) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtss))] pub fn _mm_mask_sqrt_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { vsqrtss(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } @@ -36701,7 +36701,7 @@ pub fn _mm_mask_sqrt_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_sqrt_ss&expand=5388) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtss))] pub fn _mm_maskz_sqrt_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { vsqrtss(a, b, _mm_setzero_ps(), k, _MM_FROUND_CUR_DIRECTION) } @@ -36712,7 +36712,7 @@ pub fn _mm_maskz_sqrt_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_sqrt_sd&expand=5384) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtsd))] pub fn _mm_mask_sqrt_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { vsqrtsd(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } @@ -36723,7 +36723,7 @@ pub fn _mm_mask_sqrt_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_sqrt_sd&expand=5385) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtsd))] pub fn _mm_maskz_sqrt_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { vsqrtsd(a, b, _mm_setzero_pd(), k, _MM_FROUND_CUR_DIRECTION) } @@ -36734,7 +36734,7 @@ pub fn _mm_maskz_sqrt_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_rsqrt14_ss&expand=4825) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ss))] pub fn _mm_rsqrt14_ss(a: __m128, b: __m128) -> __m128 { unsafe { transmute(vrsqrt14ss(a.as_f32x4(), b.as_f32x4(), f32x4::ZERO, 0b1)) } @@ -36745,7 +36745,7 @@ pub fn _mm_rsqrt14_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_rsqrt14_ss&expand=4823) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ss))] pub fn _mm_mask_rsqrt14_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { transmute(vrsqrt14ss(a.as_f32x4(), b.as_f32x4(), src.as_f32x4(), k)) } @@ -36756,7 +36756,7 @@ pub fn _mm_mask_rsqrt14_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_rsqrt14_ss&expand=4824) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14ss))] pub fn _mm_maskz_rsqrt14_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { transmute(vrsqrt14ss(a.as_f32x4(), b.as_f32x4(), f32x4::ZERO, k)) } @@ -36767,7 +36767,7 @@ pub fn _mm_maskz_rsqrt14_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_rsqrt14_sd&expand=4822) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14sd))] pub fn _mm_rsqrt14_sd(a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(vrsqrt14sd(a.as_f64x2(), b.as_f64x2(), f64x2::ZERO, 0b1)) } @@ -36778,7 +36778,7 @@ pub fn _mm_rsqrt14_sd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_rsqrt14_sd&expand=4820) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14sd))] pub fn _mm_mask_rsqrt14_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(vrsqrt14sd(a.as_f64x2(), b.as_f64x2(), src.as_f64x2(), k)) } @@ -36789,7 +36789,7 @@ pub fn _mm_mask_rsqrt14_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_rsqrt14_sd&expand=4821) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrsqrt14sd))] pub fn _mm_maskz_rsqrt14_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(vrsqrt14sd(a.as_f64x2(), b.as_f64x2(), f64x2::ZERO, k)) } @@ -36800,7 +36800,7 @@ pub fn _mm_maskz_rsqrt14_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_rcp14_ss&expand=4508) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ss))] pub fn _mm_rcp14_ss(a: __m128, b: __m128) -> __m128 { unsafe { transmute(vrcp14ss(a.as_f32x4(), b.as_f32x4(), f32x4::ZERO, 0b1)) } @@ -36811,7 +36811,7 @@ pub fn _mm_rcp14_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_rcp14_ss&expand=4506) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ss))] pub fn _mm_mask_rcp14_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { transmute(vrcp14ss(a.as_f32x4(), b.as_f32x4(), src.as_f32x4(), k)) } @@ -36822,7 +36822,7 @@ pub fn _mm_mask_rcp14_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_rcp14_ss&expand=4507) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14ss))] pub fn _mm_maskz_rcp14_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { transmute(vrcp14ss(a.as_f32x4(), b.as_f32x4(), f32x4::ZERO, k)) } @@ -36833,7 +36833,7 @@ pub fn _mm_maskz_rcp14_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_rcp14_sd&expand=4505) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14sd))] pub fn _mm_rcp14_sd(a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(vrcp14sd(a.as_f64x2(), b.as_f64x2(), f64x2::ZERO, 0b1)) } @@ -36844,7 +36844,7 @@ pub fn _mm_rcp14_sd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_rcp14_sd&expand=4503) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14sd))] pub fn _mm_mask_rcp14_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(vrcp14sd(a.as_f64x2(), b.as_f64x2(), src.as_f64x2(), k)) } @@ -36855,7 +36855,7 @@ pub fn _mm_mask_rcp14_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_rcp14_sd&expand=4504) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrcp14sd))] pub fn _mm_maskz_rcp14_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { transmute(vrcp14sd(a.as_f64x2(), b.as_f64x2(), f64x2::ZERO, k)) } @@ -36866,7 +36866,7 @@ pub fn _mm_maskz_rcp14_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_getexp_ss&expand=2862) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpss))] pub fn _mm_getexp_ss(a: __m128, b: __m128) -> __m128 { unsafe { @@ -36885,7 +36885,7 @@ pub fn _mm_getexp_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_getexp_ss&expand=2863) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpss))] pub fn _mm_mask_getexp_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36904,7 +36904,7 @@ pub fn _mm_mask_getexp_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_getexp_ss&expand=2864) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpss))] pub fn _mm_maskz_getexp_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -36923,7 +36923,7 @@ pub fn _mm_maskz_getexp_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_getexp_sd&expand=2859) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpsd))] pub fn _mm_getexp_sd(a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36942,7 +36942,7 @@ pub fn _mm_getexp_sd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_getexp_sd&expand=2860) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpsd))] pub fn _mm_mask_getexp_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36961,7 +36961,7 @@ pub fn _mm_mask_getexp_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_getexp_sd&expand=2861) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpsd))] pub fn _mm_maskz_getexp_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -36990,7 +36990,7 @@ pub fn _mm_maskz_getexp_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_getmant_ss&expand=2898) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm_getmant_ss( @@ -37029,7 +37029,7 @@ pub fn _mm_getmant_ss( @@ -37149,7 +37149,7 @@ pub fn _mm_getmant_sd(a: __m128, b: __m128) -> __m128 { @@ -37257,7 +37257,7 @@ pub fn _mm_roundscale_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_roundscale_ss&expand=4800) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaless, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_roundscale_ss( @@ -37287,7 +37287,7 @@ pub fn _mm_mask_roundscale_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_roundscale_ss&expand=4801) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaless, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_roundscale_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -37311,7 +37311,7 @@ pub fn _mm_maskz_roundscale_ss(k: __mmask8, a: __m128, b: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_roundscale_sd&expand=4799) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 255))] #[rustc_legacy_const_generics(2)] pub fn _mm_roundscale_sd(a: __m128d, b: __m128d) -> __m128d { @@ -37342,7 +37342,7 @@ pub fn _mm_roundscale_sd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_roundscale_sd&expand=4797) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_roundscale_sd( @@ -37372,7 +37372,7 @@ pub fn _mm_mask_roundscale_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_roundscale_sd&expand=4798) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_roundscale_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -37390,7 +37390,7 @@ pub fn _mm_maskz_roundscale_sd(k: __mmask8, a: __m128d, b: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_scalef_ss&expand=4901) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefss))] pub fn _mm_scalef_ss(a: __m128, b: __m128) -> __m128 { unsafe { @@ -37411,7 +37411,7 @@ pub fn _mm_scalef_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_scalef_ss&expand=4899) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefss))] pub fn _mm_mask_scalef_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -37427,7 +37427,7 @@ pub fn _mm_mask_scalef_ss(src: __m128, k: __mmask8, a: __m128, b: __m128) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_scalef_ss&expand=4900) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefss))] pub fn _mm_maskz_scalef_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { unsafe { @@ -37446,7 +37446,7 @@ pub fn _mm_maskz_scalef_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_scalef_sd&expand=4898) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefsd))] pub fn _mm_scalef_sd(a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -37465,7 +37465,7 @@ pub fn _mm_scalef_sd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_scalef_sd&expand=4896) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefsd))] pub fn _mm_mask_scalef_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -37484,7 +37484,7 @@ pub fn _mm_mask_scalef_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128d) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_scalef_sd&expand=4897) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefsd))] pub fn _mm_maskz_scalef_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { unsafe { @@ -37503,7 +37503,7 @@ pub fn _mm_maskz_scalef_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fmadd_ss&expand=2582) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] pub fn _mm_mask_fmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { @@ -37522,7 +37522,7 @@ pub fn _mm_mask_fmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fmadd_ss&expand=2584) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] pub fn _mm_maskz_fmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { @@ -37542,7 +37542,7 @@ pub fn _mm_maskz_fmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fmadd_ss&expand=2583) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] pub fn _mm_mask3_fmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { @@ -37561,7 +37561,7 @@ pub fn _mm_mask3_fmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fmadd_sd&expand=2578) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] pub fn _mm_mask_fmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { @@ -37580,7 +37580,7 @@ pub fn _mm_mask_fmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fmadd_sd&expand=2580) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] pub fn _mm_maskz_fmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { @@ -37600,7 +37600,7 @@ pub fn _mm_maskz_fmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fmadd_sd&expand=2579) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd))] pub fn _mm_mask3_fmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { @@ -37619,7 +37619,7 @@ pub fn _mm_mask3_fmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fmsub_ss&expand=2668) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] pub fn _mm_mask_fmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { @@ -37639,7 +37639,7 @@ pub fn _mm_mask_fmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fmsub_ss&expand=2670) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] pub fn _mm_maskz_fmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { @@ -37660,7 +37660,7 @@ pub fn _mm_maskz_fmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fmsub_ss&expand=2669) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] pub fn _mm_mask3_fmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { @@ -37680,7 +37680,7 @@ pub fn _mm_mask3_fmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fmsub_sd&expand=2664) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] pub fn _mm_mask_fmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { @@ -37700,7 +37700,7 @@ pub fn _mm_mask_fmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fmsub_sd&expand=2666) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] pub fn _mm_maskz_fmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { @@ -37721,7 +37721,7 @@ pub fn _mm_maskz_fmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fmsub_sd&expand=2665) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub))] pub fn _mm_mask3_fmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { @@ -37741,7 +37741,7 @@ pub fn _mm_mask3_fmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fnmadd_ss&expand=2748) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] pub fn _mm_mask_fnmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { @@ -37761,7 +37761,7 @@ pub fn _mm_mask_fnmadd_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fnmadd_ss&expand=2750) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] pub fn _mm_maskz_fnmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { @@ -37782,7 +37782,7 @@ pub fn _mm_maskz_fnmadd_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fnmadd_ss&expand=2749) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] pub fn _mm_mask3_fnmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { @@ -37802,7 +37802,7 @@ pub fn _mm_mask3_fnmadd_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fnmadd_sd&expand=2744) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] pub fn _mm_mask_fnmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { @@ -37822,7 +37822,7 @@ pub fn _mm_mask_fnmadd_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fnmadd_sd&expand=2746) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] pub fn _mm_maskz_fnmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { @@ -37843,7 +37843,7 @@ pub fn _mm_maskz_fnmadd_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fnmadd_sd&expand=2745) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd))] pub fn _mm_mask3_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { @@ -37863,7 +37863,7 @@ pub fn _mm_mask3_fnmadd_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fnmsub_ss&expand=2796) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] pub fn _mm_mask_fnmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m128 { unsafe { @@ -37884,7 +37884,7 @@ pub fn _mm_mask_fnmsub_ss(a: __m128, k: __mmask8, b: __m128, c: __m128) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fnmsub_ss&expand=2798) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] pub fn _mm_maskz_fnmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m128 { unsafe { @@ -37906,7 +37906,7 @@ pub fn _mm_maskz_fnmsub_ss(k: __mmask8, a: __m128, b: __m128, c: __m128) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fnmsub_ss&expand=2797) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] pub fn _mm_mask3_fnmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m128 { unsafe { @@ -37927,7 +37927,7 @@ pub fn _mm_mask3_fnmsub_ss(a: __m128, b: __m128, c: __m128, k: __mmask8) -> __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fnmsub_sd&expand=2792) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] pub fn _mm_mask_fnmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __m128d { unsafe { @@ -37948,7 +37948,7 @@ pub fn _mm_mask_fnmsub_sd(a: __m128d, k: __mmask8, b: __m128d, c: __m128d) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fnmsub_sd&expand=2794) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] pub fn _mm_maskz_fnmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> __m128d { unsafe { @@ -37970,7 +37970,7 @@ pub fn _mm_maskz_fnmsub_sd(k: __mmask8, a: __m128d, b: __m128d, c: __m128d) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fnmsub_sd&expand=2793) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub))] pub fn _mm_mask3_fnmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> __m128d { unsafe { @@ -37998,7 +37998,7 @@ pub fn _mm_mask3_fnmsub_sd(a: __m128d, b: __m128d, c: __m128d, k: __mmask8) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_round_ss&expand=151) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_add_round_ss(a: __m128, b: __m128) -> __m128 { @@ -38023,7 +38023,7 @@ pub fn _mm_add_round_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_add_round_ss&expand=152) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddss, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_add_round_ss( @@ -38054,7 +38054,7 @@ pub fn _mm_mask_add_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_round_ss&expand=153) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddss, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_add_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -38079,7 +38079,7 @@ pub fn _mm_maskz_add_round_ss(k: __mmask8, a: __m128, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_round_sd&expand=148) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddsd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_add_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -38104,7 +38104,7 @@ pub fn _mm_add_round_sd(a: __m128d, b: __m128d) -> __m128d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_add_round_sd&expand=149) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddsd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_add_round_sd( @@ -38135,7 +38135,7 @@ pub fn _mm_mask_add_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_round_sd&expand=150) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaddsd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_add_round_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -38160,7 +38160,7 @@ pub fn _mm_maskz_add_round_sd(k: __mmask8, a: __m128d, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_sub_round_ss&expand=5745) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_sub_round_ss(a: __m128, b: __m128) -> __m128 { @@ -38185,7 +38185,7 @@ pub fn _mm_sub_round_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_sub_round_ss&expand=5743) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubss, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_sub_round_ss( @@ -38216,7 +38216,7 @@ pub fn _mm_mask_sub_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_sub_round_ss&expand=5744) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubss, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_sub_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -38241,7 +38241,7 @@ pub fn _mm_maskz_sub_round_ss(k: __mmask8, a: __m128, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_sub_round_sd&expand=5742) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubsd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_sub_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -38266,7 +38266,7 @@ pub fn _mm_sub_round_sd(a: __m128d, b: __m128d) -> __m128d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_sub_round_sd&expand=5740) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubsd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_sub_round_sd( @@ -38297,7 +38297,7 @@ pub fn _mm_mask_sub_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_sub_round_sd&expand=5741) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsubsd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_sub_round_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -38322,7 +38322,7 @@ pub fn _mm_maskz_sub_round_sd(k: __mmask8, a: __m128d, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mul_round_ss&expand=3946) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_mul_round_ss(a: __m128, b: __m128) -> __m128 { @@ -38347,7 +38347,7 @@ pub fn _mm_mul_round_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_mul_round_ss&expand=3944) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulss, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_mul_round_ss( @@ -38378,7 +38378,7 @@ pub fn _mm_mask_mul_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_mul_round_ss&expand=3945) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulss, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_mul_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -38403,7 +38403,7 @@ pub fn _mm_maskz_mul_round_ss(k: __mmask8, a: __m128, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mul_round_sd&expand=3943) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulsd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_mul_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -38428,7 +38428,7 @@ pub fn _mm_mul_round_sd(a: __m128d, b: __m128d) -> __m128d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_mul_round_sd&expand=3941) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulsd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_mul_round_sd( @@ -38459,7 +38459,7 @@ pub fn _mm_mask_mul_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_mul_round_sd&expand=3942) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmulsd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_mul_round_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -38484,7 +38484,7 @@ pub fn _mm_maskz_mul_round_sd(k: __mmask8, a: __m128d, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_div_round_ss&expand=2174) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_div_round_ss(a: __m128, b: __m128) -> __m128 { @@ -38509,7 +38509,7 @@ pub fn _mm_div_round_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_div_round_ss&expand=2175) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivss, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_div_round_ss( @@ -38540,7 +38540,7 @@ pub fn _mm_mask_div_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_div_round_ss&expand=2176) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivss, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_div_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -38565,7 +38565,7 @@ pub fn _mm_maskz_div_round_ss(k: __mmask8, a: __m128, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_div_round_sd&expand=2171) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivsd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_div_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -38590,7 +38590,7 @@ pub fn _mm_div_round_sd(a: __m128d, b: __m128d) -> __m128d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_div_round_sd&expand=2172) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivsd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_div_round_sd( @@ -38621,7 +38621,7 @@ pub fn _mm_mask_div_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_div_round_sd&expand=2173) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vdivsd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_div_round_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -38640,7 +38640,7 @@ pub fn _mm_maskz_div_round_sd(k: __mmask8, a: __m128d, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_max_round_ss&expand=3668) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxss, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_max_round_ss(a: __m128, b: __m128) -> __m128 { @@ -38659,7 +38659,7 @@ pub fn _mm_max_round_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_round_ss&expand=3672) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxss, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_max_round_ss( @@ -38684,7 +38684,7 @@ pub fn _mm_mask_max_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_max_round_ss&expand=3667) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxss, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_max_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -38703,7 +38703,7 @@ pub fn _mm_maskz_max_round_ss(k: __mmask8, a: __m128, b: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_max_round_sd&expand=3665) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxsd, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_max_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -38722,7 +38722,7 @@ pub fn _mm_max_round_sd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_max_round_sd&expand=3663) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxsd, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_max_round_sd( @@ -38747,7 +38747,7 @@ pub fn _mm_mask_max_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_round_sd&expand=3670) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vmaxsd, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_max_round_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -38766,7 +38766,7 @@ pub fn _mm_maskz_max_round_sd(k: __mmask8, a: __m128d, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_min_round_ss&expand=3782) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminss, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_min_round_ss(a: __m128, b: __m128) -> __m128 { @@ -38785,7 +38785,7 @@ pub fn _mm_min_round_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_min_round_ss&expand=3780) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminss, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_min_round_ss( @@ -38810,7 +38810,7 @@ pub fn _mm_mask_min_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_min_round_ss&expand=3781) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminss, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_min_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -38829,7 +38829,7 @@ pub fn _mm_maskz_min_round_ss(k: __mmask8, a: __m128, b: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_min_round_sd&expand=3779) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminsd, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_min_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -38848,7 +38848,7 @@ pub fn _mm_min_round_sd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_min_round_sd&expand=3777) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminsd, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_min_round_sd( @@ -38873,7 +38873,7 @@ pub fn _mm_mask_min_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_min_round_sd&expand=3778) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vminsd, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_min_round_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -38898,7 +38898,7 @@ pub fn _mm_maskz_min_round_sd(k: __mmask8, a: __m128d, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_sqrt_round_ss&expand=5383) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_sqrt_round_ss(a: __m128, b: __m128) -> __m128 { @@ -38920,7 +38920,7 @@ pub fn _mm_sqrt_round_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_sqrt_round_ss&expand=5381) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtss, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_sqrt_round_ss( @@ -38947,7 +38947,7 @@ pub fn _mm_mask_sqrt_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_sqrt_round_ss&expand=5382) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtss, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_sqrt_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -38969,7 +38969,7 @@ pub fn _mm_maskz_sqrt_round_ss(k: __mmask8, a: __m128, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_sqrt_round_sd&expand=5380) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtsd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_sqrt_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -38991,7 +38991,7 @@ pub fn _mm_sqrt_round_sd(a: __m128d, b: __m128d) -> __m128d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_sqrt_round_sd&expand=5378) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtsd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_sqrt_round_sd( @@ -39018,7 +39018,7 @@ pub fn _mm_mask_sqrt_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_sqrt_round_sd&expand=5379) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vsqrtsd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_sqrt_round_sd( @@ -39038,7 +39038,7 @@ pub fn _mm_maskz_sqrt_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_getexp_round_ss&expand=2856) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpss, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_getexp_round_ss(a: __m128, b: __m128) -> __m128 { @@ -39057,7 +39057,7 @@ pub fn _mm_getexp_round_ss(a: __m128, b: __m128) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_getexp_round_ss&expand=2857) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpss, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_getexp_round_ss( @@ -39082,7 +39082,7 @@ pub fn _mm_mask_getexp_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_getexp_round_ss&expand=2858) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpss, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_getexp_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -39101,7 +39101,7 @@ pub fn _mm_maskz_getexp_round_ss(k: __mmask8, a: __m128, b: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_getexp_round_sd&expand=2853) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpsd, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_getexp_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -39120,7 +39120,7 @@ pub fn _mm_getexp_round_sd(a: __m128d, b: __m128d) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_getexp_round_sd&expand=2854) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpsd, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_getexp_round_sd( @@ -39145,7 +39145,7 @@ pub fn _mm_mask_getexp_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_getexp_round_sd&expand=2855) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetexpsd, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_getexp_round_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d { @@ -39173,7 +39173,7 @@ pub fn _mm_maskz_getexp_round_sd(k: __mmask8, a: __m128d, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_getmant_round_ss&expand=2892) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(2, 3, 4)] pub fn _mm_getmant_round_ss< @@ -39210,7 +39210,7 @@ pub fn _mm_getmant_round_ss< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_getmant_round_ss&expand=2893) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(4, 5, 6)] pub fn _mm_mask_getmant_round_ss< @@ -39250,7 +39250,7 @@ pub fn _mm_mask_getmant_round_ss< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_getmant_round_ss&expand=2894) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(3, 4, 5)] pub fn _mm_maskz_getmant_round_ss< @@ -39288,7 +39288,7 @@ pub fn _mm_maskz_getmant_round_ss< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_getmant_round_sd&expand=2889) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(2, 3, 4)] pub fn _mm_getmant_round_sd< @@ -39325,7 +39325,7 @@ pub fn _mm_getmant_round_sd< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_getmant_round_sd&expand=2890) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(4, 5, 6)] pub fn _mm_mask_getmant_round_sd< @@ -39365,7 +39365,7 @@ pub fn _mm_mask_getmant_round_sd< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_getmant_round_sd&expand=2891) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0, SAE = 4))] #[rustc_legacy_const_generics(3, 4, 5)] pub fn _mm_maskz_getmant_round_sd< @@ -39400,7 +39400,7 @@ pub fn _mm_maskz_getmant_round_sd< /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_roundscale_round_ss&expand=4796) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaless, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm_roundscale_round_ss(a: __m128, b: __m128) -> __m128 { @@ -39426,7 +39426,7 @@ pub fn _mm_roundscale_round_ss(a: __m128, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_roundscale_round_ss&expand=4794) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaless, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm_mask_roundscale_round_ss( @@ -39458,7 +39458,7 @@ pub fn _mm_mask_roundscale_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_roundscale_round_ss&expand=4795) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscaless, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm_maskz_roundscale_round_ss( @@ -39488,7 +39488,7 @@ pub fn _mm_maskz_roundscale_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_roundscale_round_sd&expand=4793) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] pub fn _mm_roundscale_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -39514,7 +39514,7 @@ pub fn _mm_roundscale_round_sd(a: __m128d, b: _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_roundscale_round_sd&expand=4791) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm_mask_roundscale_round_sd( @@ -39546,7 +39546,7 @@ pub fn _mm_mask_roundscale_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_roundscale_round_sd&expand=4792) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm_maskz_roundscale_round_sd( @@ -39576,7 +39576,7 @@ pub fn _mm_maskz_roundscale_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_scalef_round_ss&expand=4895) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_scalef_round_ss(a: __m128, b: __m128) -> __m128 { @@ -39601,7 +39601,7 @@ pub fn _mm_scalef_round_ss(a: __m128, b: __m128) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_scalef_round_ss&expand=4893) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefss, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_scalef_round_ss( @@ -39632,7 +39632,7 @@ pub fn _mm_mask_scalef_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_scalef_round_ss&expand=4894) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefss, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_scalef_round_ss(k: __mmask8, a: __m128, b: __m128) -> __m128 { @@ -39657,7 +39657,7 @@ pub fn _mm_maskz_scalef_round_ss(k: __mmask8, a: __m128, b: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_scalef_round_sd&expand=4892) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefsd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_scalef_round_sd(a: __m128d, b: __m128d) -> __m128d { @@ -39682,7 +39682,7 @@ pub fn _mm_scalef_round_sd(a: __m128d, b: __m128d) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_scalef_round_sd&expand=4890) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefsd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_scalef_round_sd( @@ -39712,7 +39712,7 @@ pub fn _mm_mask_scalef_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_scalef_round_sd&expand=4891) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vscalefsd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_scalef_round_sd( @@ -39741,7 +39741,7 @@ pub fn _mm_maskz_scalef_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fmadd_round_ss&expand=2573) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_fmadd_round_ss(a: __m128, b: __m128, c: __m128) -> __m128 { @@ -39767,7 +39767,7 @@ pub fn _mm_fmadd_round_ss(a: __m128, b: __m128, c: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fmadd_round_ss&expand=2574) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fmadd_round_ss( @@ -39800,7 +39800,7 @@ pub fn _mm_mask_fmadd_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fmadd_round_ss&expand=2576) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fmadd_round_ss( @@ -39834,7 +39834,7 @@ pub fn _mm_maskz_fmadd_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fmadd_round_ss&expand=2575) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask3_fmadd_round_ss( @@ -39867,7 +39867,7 @@ pub fn _mm_mask3_fmadd_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fmadd_round_sd&expand=2569) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_fmadd_round_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d { @@ -39893,7 +39893,7 @@ pub fn _mm_fmadd_round_sd(a: __m128d, b: __m128d, c: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fmadd_round_sd&expand=2570) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fmadd_round_sd( @@ -39926,7 +39926,7 @@ pub fn _mm_mask_fmadd_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fmadd_round_sd&expand=2572) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fmadd_round_sd( @@ -39960,7 +39960,7 @@ pub fn _mm_maskz_fmadd_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fmadd_round_sd&expand=2571) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask3_fmadd_round_sd( @@ -39993,7 +39993,7 @@ pub fn _mm_mask3_fmadd_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fmsub_round_ss&expand=2659) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_fmsub_round_ss(a: __m128, b: __m128, c: __m128) -> __m128 { @@ -40020,7 +40020,7 @@ pub fn _mm_fmsub_round_ss(a: __m128, b: __m128, c: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fmsub_round_ss&expand=2660) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fmsub_round_ss( @@ -40054,7 +40054,7 @@ pub fn _mm_mask_fmsub_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fmsub_round_ss&expand=2662) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fmsub_round_ss( @@ -40089,7 +40089,7 @@ pub fn _mm_maskz_fmsub_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fmsub_round_ss&expand=2661) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask3_fmsub_round_ss( @@ -40123,7 +40123,7 @@ pub fn _mm_mask3_fmsub_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fmsub_round_sd&expand=2655) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_fmsub_round_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d { @@ -40150,7 +40150,7 @@ pub fn _mm_fmsub_round_sd(a: __m128d, b: __m128d, c: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fmsub_round_sd&expand=2656) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fmsub_round_sd( @@ -40184,7 +40184,7 @@ pub fn _mm_mask_fmsub_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fmsub_round_sd&expand=2658) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fmsub_round_sd( @@ -40219,7 +40219,7 @@ pub fn _mm_maskz_fmsub_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fmsub_round_sd&expand=2657) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask3_fmsub_round_sd( @@ -40253,7 +40253,7 @@ pub fn _mm_mask3_fmsub_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fnmadd_round_ss&expand=2739) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_fnmadd_round_ss(a: __m128, b: __m128, c: __m128) -> __m128 { @@ -40280,7 +40280,7 @@ pub fn _mm_fnmadd_round_ss(a: __m128, b: __m128, c: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fnmadd_round_ss&expand=2740) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fnmadd_round_ss( @@ -40314,7 +40314,7 @@ pub fn _mm_mask_fnmadd_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fnmadd_round_ss&expand=2742) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fnmadd_round_ss( @@ -40349,7 +40349,7 @@ pub fn _mm_maskz_fnmadd_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fnmadd_round_ss&expand=2741) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask3_fnmadd_round_ss( @@ -40383,7 +40383,7 @@ pub fn _mm_mask3_fnmadd_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fnmadd_round_sd&expand=2735) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_fnmadd_round_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d { @@ -40410,7 +40410,7 @@ pub fn _mm_fnmadd_round_sd(a: __m128d, b: __m128d, c: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fnmadd_round_sd&expand=2736) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fnmadd_round_sd( @@ -40444,7 +40444,7 @@ pub fn _mm_mask_fnmadd_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fnmadd_round_sd&expand=2738) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fnmadd_round_sd( @@ -40479,7 +40479,7 @@ pub fn _mm_maskz_fnmadd_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fnmadd_round_sd&expand=2737) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask3_fnmadd_round_sd( @@ -40513,7 +40513,7 @@ pub fn _mm_mask3_fnmadd_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fnmsub_round_ss&expand=2787) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_fnmsub_round_ss(a: __m128, b: __m128, c: __m128) -> __m128 { @@ -40541,7 +40541,7 @@ pub fn _mm_fnmsub_round_ss(a: __m128, b: __m128, c: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fnmsub_round_ss&expand=2788) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fnmsub_round_ss( @@ -40576,7 +40576,7 @@ pub fn _mm_mask_fnmsub_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fnmsub_round_ss&expand=2790) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fnmsub_round_ss( @@ -40612,7 +40612,7 @@ pub fn _mm_maskz_fnmsub_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fnmsub_round_ss&expand=2789) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask3_fnmsub_round_ss( @@ -40647,7 +40647,7 @@ pub fn _mm_mask3_fnmsub_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fnmsub_round_sd&expand=2783) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_fnmsub_round_sd(a: __m128d, b: __m128d, c: __m128d) -> __m128d { @@ -40675,7 +40675,7 @@ pub fn _mm_fnmsub_round_sd(a: __m128d, b: __m128d, c: __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fnmsub_round_sd&expand=2784) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fnmsub_round_sd( @@ -40710,7 +40710,7 @@ pub fn _mm_mask_fnmsub_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fnmsub_round_sd&expand=2786) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fnmsub_round_sd( @@ -40746,7 +40746,7 @@ pub fn _mm_maskz_fnmsub_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask3_fnmsub_round_sd&expand=2785) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask3_fnmsub_round_sd( @@ -40774,7 +40774,7 @@ pub fn _mm_mask3_fnmsub_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_ss&expand=2517) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_fixupimm_ss(a: __m128, b: __m128, c: __m128i) -> __m128 { @@ -40795,7 +40795,7 @@ pub fn _mm_fixupimm_ss(a: __m128, b: __m128, c: __m128i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_ss&expand=2518) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fixupimm_ss( @@ -40821,7 +40821,7 @@ pub fn _mm_mask_fixupimm_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_ss&expand=2519) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fixupimm_ss( @@ -40847,7 +40847,7 @@ pub fn _mm_maskz_fixupimm_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_sd&expand=2514) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_fixupimm_sd(a: __m128d, b: __m128d, c: __m128i) -> __m128d { @@ -40868,7 +40868,7 @@ pub fn _mm_fixupimm_sd(a: __m128d, b: __m128d, c: __m128i) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_sd&expand=2515) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_fixupimm_sd( @@ -40894,7 +40894,7 @@ pub fn _mm_mask_fixupimm_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_sd&expand=2516) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_maskz_fixupimm_sd( @@ -40921,7 +40921,7 @@ pub fn _mm_maskz_fixupimm_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_round_ss&expand=2511) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm_fixupimm_round_ss( @@ -40948,7 +40948,7 @@ pub fn _mm_fixupimm_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_round_ss&expand=2512) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm_mask_fixupimm_round_ss( @@ -40976,7 +40976,7 @@ pub fn _mm_mask_fixupimm_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_round_ss&expand=2513) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm_maskz_fixupimm_round_ss( @@ -41004,7 +41004,7 @@ pub fn _mm_maskz_fixupimm_round_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_fixupimm_round_sd&expand=2508) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] pub fn _mm_fixupimm_round_sd( @@ -41031,7 +41031,7 @@ pub fn _mm_fixupimm_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_fixupimm_round_sd&expand=2509) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm_mask_fixupimm_round_sd( @@ -41059,7 +41059,7 @@ pub fn _mm_mask_fixupimm_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_fixupimm_round_sd&expand=2510) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] pub fn _mm_maskz_fixupimm_round_sd( @@ -41086,7 +41086,7 @@ pub fn _mm_maskz_fixupimm_round_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_cvtss_sd&expand=1896) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2sd))] pub fn _mm_mask_cvtss_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128) -> __m128d { unsafe { @@ -41105,7 +41105,7 @@ pub fn _mm_mask_cvtss_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_cvtss_sd&expand=1897) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2sd))] pub fn _mm_maskz_cvtss_sd(k: __mmask8, a: __m128d, b: __m128) -> __m128d { unsafe { @@ -41124,7 +41124,7 @@ pub fn _mm_maskz_cvtss_sd(k: __mmask8, a: __m128d, b: __m128) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_cvtsd_ss&expand=1797) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2ss))] pub fn _mm_mask_cvtsd_ss(src: __m128, k: __mmask8, a: __m128, b: __m128d) -> __m128 { unsafe { @@ -41143,7 +41143,7 @@ pub fn _mm_mask_cvtsd_ss(src: __m128, k: __mmask8, a: __m128, b: __m128d) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_cvtsd_ss&expand=1798) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2ss))] pub fn _mm_maskz_cvtsd_ss(k: __mmask8, a: __m128, b: __m128d) -> __m128 { unsafe { @@ -41163,7 +41163,7 @@ pub fn _mm_maskz_cvtsd_ss(k: __mmask8, a: __m128, b: __m128d) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundss_sd&expand=1371) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2sd, SAE = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundss_sd(a: __m128d, b: __m128) -> __m128d { @@ -41182,7 +41182,7 @@ pub fn _mm_cvt_roundss_sd(a: __m128d, b: __m128) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_cvt_roundss_sd&expand=1372) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2sd, SAE = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_cvt_roundss_sd( @@ -41207,7 +41207,7 @@ pub fn _mm_mask_cvt_roundss_sd( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_cvt_roundss_sd&expand=1373) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2sd, SAE = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_cvt_roundss_sd(k: __mmask8, a: __m128d, b: __m128) -> __m128d { @@ -41231,7 +41231,7 @@ pub fn _mm_maskz_cvt_roundss_sd(k: __mmask8, a: __m128d, b: __m1 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundsd_ss&expand=1361) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundsd_ss(a: __m128, b: __m128d) -> __m128 { @@ -41255,7 +41255,7 @@ pub fn _mm_cvt_roundsd_ss(a: __m128, b: __m128d) -> __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_mask_cvt_roundsd_ss&expand=1362) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_cvt_roundsd_ss( @@ -41285,7 +41285,7 @@ pub fn _mm_mask_cvt_roundsd_ss( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_maskz_cvt_roundsd_ss&expand=1363) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_cvt_roundsd_ss(k: __mmask8, a: __m128, b: __m128d) -> __m128 { @@ -41309,7 +41309,7 @@ pub fn _mm_maskz_cvt_roundsd_ss(k: __mmask8, a: __m128, b: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundss_si32&expand=1374) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundss_si32(a: __m128) -> i32 { @@ -41331,7 +41331,7 @@ pub fn _mm_cvt_roundss_si32(a: __m128) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundss_i32&expand=1369) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundss_i32(a: __m128) -> i32 { @@ -41353,7 +41353,7 @@ pub fn _mm_cvt_roundss_i32(a: __m128) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundss_u32&expand=1376) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundss_u32(a: __m128) -> u32 { @@ -41369,7 +41369,7 @@ pub fn _mm_cvt_roundss_u32(a: __m128) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvtss_i32&expand=1893) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2si))] pub fn _mm_cvtss_i32(a: __m128) -> i32 { unsafe { vcvtss2si(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) } @@ -41380,7 +41380,7 @@ pub fn _mm_cvtss_i32(a: __m128) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvtss_u32&expand=1901) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2usi))] pub fn _mm_cvtss_u32(a: __m128) -> u32 { unsafe { vcvtss2usi(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) } @@ -41397,7 +41397,7 @@ pub fn _mm_cvtss_u32(a: __m128) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundsd_si32&expand=1359) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundsd_si32(a: __m128d) -> i32 { @@ -41419,7 +41419,7 @@ pub fn _mm_cvt_roundsd_si32(a: __m128d) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundsd_i32&expand=1357) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundsd_i32(a: __m128d) -> i32 { @@ -41441,7 +41441,7 @@ pub fn _mm_cvt_roundsd_i32(a: __m128d) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u32&expand=1364) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundsd_u32(a: __m128d) -> u32 { @@ -41457,7 +41457,7 @@ pub fn _mm_cvt_roundsd_u32(a: __m128d) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvtsd_i32&expand=1791) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2si))] pub fn _mm_cvtsd_i32(a: __m128d) -> i32 { unsafe { vcvtsd2si(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) } @@ -41468,7 +41468,7 @@ pub fn _mm_cvtsd_i32(a: __m128d) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvtsd_u32&expand=1799) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2usi))] pub fn _mm_cvtsd_u32(a: __m128d) -> u32 { unsafe { vcvtsd2usi(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) } @@ -41486,7 +41486,7 @@ pub fn _mm_cvtsd_u32(a: __m128d) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundi32_ss&expand=1312) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundi32_ss(a: __m128, b: i32) -> __m128 { @@ -41510,7 +41510,7 @@ pub fn _mm_cvt_roundi32_ss(a: __m128, b: i32) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundsi32_ss&expand=1366) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundsi32_ss(a: __m128, b: i32) -> __m128 { @@ -41533,7 +41533,7 @@ pub fn _mm_cvt_roundsi32_ss(a: __m128, b: i32) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvt_roundu32_ss&expand=1378) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundu32_ss(a: __m128, b: u32) -> __m128 { @@ -41550,7 +41550,7 @@ pub fn _mm_cvt_roundu32_ss(a: __m128, b: u32) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti32_ss&expand=1643) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2ss))] pub fn _mm_cvti32_ss(a: __m128, b: i32) -> __m128 { unsafe { @@ -41564,7 +41564,7 @@ pub fn _mm_cvti32_ss(a: __m128, b: i32) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti32_sd&expand=1642) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2sd))] pub fn _mm_cvti32_sd(a: __m128d, b: i32) -> __m128d { unsafe { @@ -41579,7 +41579,7 @@ pub fn _mm_cvti32_sd(a: __m128d, b: i32) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvtt_roundss_si32&expand=1936) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundss_si32(a: __m128) -> i32 { @@ -41596,7 +41596,7 @@ pub fn _mm_cvtt_roundss_si32(a: __m128) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvtt_roundss_i32&expand=1934) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundss_i32(a: __m128) -> i32 { @@ -41613,7 +41613,7 @@ pub fn _mm_cvtt_roundss_i32(a: __m128) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvtt_roundss_u32&expand=1938) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundss_u32(a: __m128) -> u32 { @@ -41629,7 +41629,7 @@ pub fn _mm_cvtt_roundss_u32(a: __m128) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_i32&expand=2022) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2si))] pub fn _mm_cvttss_i32(a: __m128) -> i32 { unsafe { vcvttss2si(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) } @@ -41640,7 +41640,7 @@ pub fn _mm_cvttss_i32(a: __m128) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u32&expand=2026) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2usi))] pub fn _mm_cvttss_u32(a: __m128) -> u32 { unsafe { vcvttss2usi(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) } @@ -41652,7 +41652,7 @@ pub fn _mm_cvttss_u32(a: __m128) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si32&expand=1930) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundsd_si32(a: __m128d) -> i32 { @@ -41669,7 +41669,7 @@ pub fn _mm_cvtt_roundsd_si32(a: __m128d) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i32&expand=1928) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundsd_i32(a: __m128d) -> i32 { @@ -41686,7 +41686,7 @@ pub fn _mm_cvtt_roundsd_i32(a: __m128d) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvtt_roundsd_u32&expand=1932) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundsd_u32(a: __m128d) -> u32 { @@ -41702,7 +41702,7 @@ pub fn _mm_cvtt_roundsd_u32(a: __m128d) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i32&expand=2015) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2si))] pub fn _mm_cvttsd_i32(a: __m128d) -> i32 { unsafe { vcvttsd2si(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) } @@ -41713,7 +41713,7 @@ pub fn _mm_cvttsd_i32(a: __m128d) -> i32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u32&expand=2020) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2usi))] pub fn _mm_cvttsd_u32(a: __m128d) -> u32 { unsafe { vcvttsd2usi(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) } @@ -41724,7 +41724,7 @@ pub fn _mm_cvttsd_u32(a: __m128d) -> u32 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu32_ss&expand=2032) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtusi2ss))] pub fn _mm_cvtu32_ss(a: __m128, b: u32) -> __m128 { unsafe { @@ -41738,7 +41738,7 @@ pub fn _mm_cvtu32_ss(a: __m128, b: u32) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu32_sd&expand=2031) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtusi2sd))] pub fn _mm_cvtu32_sd(a: __m128d, b: u32) -> __m128d { unsafe { @@ -41753,7 +41753,7 @@ pub fn _mm_cvtu32_sd(a: __m128d, b: u32) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_comi_round_ss&expand=1175) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 5, SAE = 4))] //should be vcomiss #[rustc_legacy_const_generics(2, 3)] pub fn _mm_comi_round_ss(a: __m128, b: __m128) -> i32 { @@ -41772,7 +41772,7 @@ pub fn _mm_comi_round_ss(a: __m128, b: __m128) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_comi_round_sd&expand=1174) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcmp, IMM5 = 5, SAE = 4))] //should be vcomisd #[rustc_legacy_const_generics(2, 3)] pub fn _mm_comi_round_sd(a: __m128d, b: __m128d) -> i32 { @@ -41786,564 +41786,564 @@ pub fn _mm_comi_round_sd(a: __m128d, b: __m128d } /// Equal -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_CMPINT_EQ: _MM_CMPINT_ENUM = 0x00; /// Less-than -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_CMPINT_LT: _MM_CMPINT_ENUM = 0x01; /// Less-than-or-equal -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_CMPINT_LE: _MM_CMPINT_ENUM = 0x02; /// False -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_CMPINT_FALSE: _MM_CMPINT_ENUM = 0x03; /// Not-equal -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_CMPINT_NE: _MM_CMPINT_ENUM = 0x04; /// Not less-than -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_CMPINT_NLT: _MM_CMPINT_ENUM = 0x05; /// Not less-than-or-equal -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_CMPINT_NLE: _MM_CMPINT_ENUM = 0x06; /// True -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_CMPINT_TRUE: _MM_CMPINT_ENUM = 0x07; /// interval [1, 2) -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_MANT_NORM_1_2: _MM_MANTISSA_NORM_ENUM = 0x00; /// interval [0.5, 2) -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_MANT_NORM_P5_2: _MM_MANTISSA_NORM_ENUM = 0x01; /// interval [0.5, 1) -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_MANT_NORM_P5_1: _MM_MANTISSA_NORM_ENUM = 0x02; /// interval [0.75, 1.5) -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_MANT_NORM_P75_1P5: _MM_MANTISSA_NORM_ENUM = 0x03; /// sign = sign(SRC) -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_MANT_SIGN_SRC: _MM_MANTISSA_SIGN_ENUM = 0x00; /// sign = 0 -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_MANT_SIGN_ZERO: _MM_MANTISSA_SIGN_ENUM = 0x01; /// DEST = NaN if sign(SRC) = 1 -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_MANT_SIGN_NAN: _MM_MANTISSA_SIGN_ENUM = 0x02; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AAAA: _MM_PERM_ENUM = 0x00; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AAAB: _MM_PERM_ENUM = 0x01; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AAAC: _MM_PERM_ENUM = 0x02; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AAAD: _MM_PERM_ENUM = 0x03; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AABA: _MM_PERM_ENUM = 0x04; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AABB: _MM_PERM_ENUM = 0x05; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AABC: _MM_PERM_ENUM = 0x06; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AABD: _MM_PERM_ENUM = 0x07; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AACA: _MM_PERM_ENUM = 0x08; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AACB: _MM_PERM_ENUM = 0x09; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AACC: _MM_PERM_ENUM = 0x0A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AACD: _MM_PERM_ENUM = 0x0B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AADA: _MM_PERM_ENUM = 0x0C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AADB: _MM_PERM_ENUM = 0x0D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AADC: _MM_PERM_ENUM = 0x0E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_AADD: _MM_PERM_ENUM = 0x0F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABAA: _MM_PERM_ENUM = 0x10; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABAB: _MM_PERM_ENUM = 0x11; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABAC: _MM_PERM_ENUM = 0x12; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABAD: _MM_PERM_ENUM = 0x13; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABBA: _MM_PERM_ENUM = 0x14; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABBB: _MM_PERM_ENUM = 0x15; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABBC: _MM_PERM_ENUM = 0x16; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABBD: _MM_PERM_ENUM = 0x17; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABCA: _MM_PERM_ENUM = 0x18; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABCB: _MM_PERM_ENUM = 0x19; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABCC: _MM_PERM_ENUM = 0x1A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABCD: _MM_PERM_ENUM = 0x1B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABDA: _MM_PERM_ENUM = 0x1C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABDB: _MM_PERM_ENUM = 0x1D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABDC: _MM_PERM_ENUM = 0x1E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ABDD: _MM_PERM_ENUM = 0x1F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACAA: _MM_PERM_ENUM = 0x20; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACAB: _MM_PERM_ENUM = 0x21; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACAC: _MM_PERM_ENUM = 0x22; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACAD: _MM_PERM_ENUM = 0x23; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACBA: _MM_PERM_ENUM = 0x24; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACBB: _MM_PERM_ENUM = 0x25; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACBC: _MM_PERM_ENUM = 0x26; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACBD: _MM_PERM_ENUM = 0x27; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACCA: _MM_PERM_ENUM = 0x28; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACCB: _MM_PERM_ENUM = 0x29; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACCC: _MM_PERM_ENUM = 0x2A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACCD: _MM_PERM_ENUM = 0x2B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACDA: _MM_PERM_ENUM = 0x2C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACDB: _MM_PERM_ENUM = 0x2D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACDC: _MM_PERM_ENUM = 0x2E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ACDD: _MM_PERM_ENUM = 0x2F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADAA: _MM_PERM_ENUM = 0x30; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADAB: _MM_PERM_ENUM = 0x31; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADAC: _MM_PERM_ENUM = 0x32; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADAD: _MM_PERM_ENUM = 0x33; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADBA: _MM_PERM_ENUM = 0x34; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADBB: _MM_PERM_ENUM = 0x35; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADBC: _MM_PERM_ENUM = 0x36; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADBD: _MM_PERM_ENUM = 0x37; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADCA: _MM_PERM_ENUM = 0x38; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADCB: _MM_PERM_ENUM = 0x39; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADCC: _MM_PERM_ENUM = 0x3A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADCD: _MM_PERM_ENUM = 0x3B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADDA: _MM_PERM_ENUM = 0x3C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADDB: _MM_PERM_ENUM = 0x3D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADDC: _MM_PERM_ENUM = 0x3E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_ADDD: _MM_PERM_ENUM = 0x3F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BAAA: _MM_PERM_ENUM = 0x40; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BAAB: _MM_PERM_ENUM = 0x41; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BAAC: _MM_PERM_ENUM = 0x42; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BAAD: _MM_PERM_ENUM = 0x43; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BABA: _MM_PERM_ENUM = 0x44; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BABB: _MM_PERM_ENUM = 0x45; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BABC: _MM_PERM_ENUM = 0x46; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BABD: _MM_PERM_ENUM = 0x47; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BACA: _MM_PERM_ENUM = 0x48; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BACB: _MM_PERM_ENUM = 0x49; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BACC: _MM_PERM_ENUM = 0x4A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BACD: _MM_PERM_ENUM = 0x4B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BADA: _MM_PERM_ENUM = 0x4C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BADB: _MM_PERM_ENUM = 0x4D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BADC: _MM_PERM_ENUM = 0x4E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BADD: _MM_PERM_ENUM = 0x4F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBAA: _MM_PERM_ENUM = 0x50; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBAB: _MM_PERM_ENUM = 0x51; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBAC: _MM_PERM_ENUM = 0x52; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBAD: _MM_PERM_ENUM = 0x53; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBBA: _MM_PERM_ENUM = 0x54; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBBB: _MM_PERM_ENUM = 0x55; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBBC: _MM_PERM_ENUM = 0x56; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBBD: _MM_PERM_ENUM = 0x57; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBCA: _MM_PERM_ENUM = 0x58; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBCB: _MM_PERM_ENUM = 0x59; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBCC: _MM_PERM_ENUM = 0x5A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBCD: _MM_PERM_ENUM = 0x5B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBDA: _MM_PERM_ENUM = 0x5C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBDB: _MM_PERM_ENUM = 0x5D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBDC: _MM_PERM_ENUM = 0x5E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BBDD: _MM_PERM_ENUM = 0x5F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCAA: _MM_PERM_ENUM = 0x60; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCAB: _MM_PERM_ENUM = 0x61; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCAC: _MM_PERM_ENUM = 0x62; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCAD: _MM_PERM_ENUM = 0x63; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCBA: _MM_PERM_ENUM = 0x64; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCBB: _MM_PERM_ENUM = 0x65; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCBC: _MM_PERM_ENUM = 0x66; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCBD: _MM_PERM_ENUM = 0x67; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCCA: _MM_PERM_ENUM = 0x68; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCCB: _MM_PERM_ENUM = 0x69; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCCC: _MM_PERM_ENUM = 0x6A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCCD: _MM_PERM_ENUM = 0x6B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCDA: _MM_PERM_ENUM = 0x6C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCDB: _MM_PERM_ENUM = 0x6D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCDC: _MM_PERM_ENUM = 0x6E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BCDD: _MM_PERM_ENUM = 0x6F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDAA: _MM_PERM_ENUM = 0x70; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDAB: _MM_PERM_ENUM = 0x71; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDAC: _MM_PERM_ENUM = 0x72; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDAD: _MM_PERM_ENUM = 0x73; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDBA: _MM_PERM_ENUM = 0x74; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDBB: _MM_PERM_ENUM = 0x75; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDBC: _MM_PERM_ENUM = 0x76; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDBD: _MM_PERM_ENUM = 0x77; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDCA: _MM_PERM_ENUM = 0x78; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDCB: _MM_PERM_ENUM = 0x79; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDCC: _MM_PERM_ENUM = 0x7A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDCD: _MM_PERM_ENUM = 0x7B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDDA: _MM_PERM_ENUM = 0x7C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDDB: _MM_PERM_ENUM = 0x7D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDDC: _MM_PERM_ENUM = 0x7E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_BDDD: _MM_PERM_ENUM = 0x7F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CAAA: _MM_PERM_ENUM = 0x80; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CAAB: _MM_PERM_ENUM = 0x81; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CAAC: _MM_PERM_ENUM = 0x82; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CAAD: _MM_PERM_ENUM = 0x83; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CABA: _MM_PERM_ENUM = 0x84; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CABB: _MM_PERM_ENUM = 0x85; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CABC: _MM_PERM_ENUM = 0x86; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CABD: _MM_PERM_ENUM = 0x87; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CACA: _MM_PERM_ENUM = 0x88; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CACB: _MM_PERM_ENUM = 0x89; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CACC: _MM_PERM_ENUM = 0x8A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CACD: _MM_PERM_ENUM = 0x8B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CADA: _MM_PERM_ENUM = 0x8C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CADB: _MM_PERM_ENUM = 0x8D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CADC: _MM_PERM_ENUM = 0x8E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CADD: _MM_PERM_ENUM = 0x8F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBAA: _MM_PERM_ENUM = 0x90; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBAB: _MM_PERM_ENUM = 0x91; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBAC: _MM_PERM_ENUM = 0x92; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBAD: _MM_PERM_ENUM = 0x93; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBBA: _MM_PERM_ENUM = 0x94; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBBB: _MM_PERM_ENUM = 0x95; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBBC: _MM_PERM_ENUM = 0x96; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBBD: _MM_PERM_ENUM = 0x97; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBCA: _MM_PERM_ENUM = 0x98; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBCB: _MM_PERM_ENUM = 0x99; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBCC: _MM_PERM_ENUM = 0x9A; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBCD: _MM_PERM_ENUM = 0x9B; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBDA: _MM_PERM_ENUM = 0x9C; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBDB: _MM_PERM_ENUM = 0x9D; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBDC: _MM_PERM_ENUM = 0x9E; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CBDD: _MM_PERM_ENUM = 0x9F; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCAA: _MM_PERM_ENUM = 0xA0; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCAB: _MM_PERM_ENUM = 0xA1; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCAC: _MM_PERM_ENUM = 0xA2; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCAD: _MM_PERM_ENUM = 0xA3; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCBA: _MM_PERM_ENUM = 0xA4; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCBB: _MM_PERM_ENUM = 0xA5; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCBC: _MM_PERM_ENUM = 0xA6; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCBD: _MM_PERM_ENUM = 0xA7; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCCA: _MM_PERM_ENUM = 0xA8; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCCB: _MM_PERM_ENUM = 0xA9; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCCC: _MM_PERM_ENUM = 0xAA; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCCD: _MM_PERM_ENUM = 0xAB; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCDA: _MM_PERM_ENUM = 0xAC; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCDB: _MM_PERM_ENUM = 0xAD; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCDC: _MM_PERM_ENUM = 0xAE; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CCDD: _MM_PERM_ENUM = 0xAF; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDAA: _MM_PERM_ENUM = 0xB0; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDAB: _MM_PERM_ENUM = 0xB1; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDAC: _MM_PERM_ENUM = 0xB2; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDAD: _MM_PERM_ENUM = 0xB3; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDBA: _MM_PERM_ENUM = 0xB4; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDBB: _MM_PERM_ENUM = 0xB5; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDBC: _MM_PERM_ENUM = 0xB6; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDBD: _MM_PERM_ENUM = 0xB7; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDCA: _MM_PERM_ENUM = 0xB8; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDCB: _MM_PERM_ENUM = 0xB9; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDCC: _MM_PERM_ENUM = 0xBA; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDCD: _MM_PERM_ENUM = 0xBB; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDDA: _MM_PERM_ENUM = 0xBC; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDDB: _MM_PERM_ENUM = 0xBD; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDDC: _MM_PERM_ENUM = 0xBE; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_CDDD: _MM_PERM_ENUM = 0xBF; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DAAA: _MM_PERM_ENUM = 0xC0; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DAAB: _MM_PERM_ENUM = 0xC1; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DAAC: _MM_PERM_ENUM = 0xC2; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DAAD: _MM_PERM_ENUM = 0xC3; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DABA: _MM_PERM_ENUM = 0xC4; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DABB: _MM_PERM_ENUM = 0xC5; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DABC: _MM_PERM_ENUM = 0xC6; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DABD: _MM_PERM_ENUM = 0xC7; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DACA: _MM_PERM_ENUM = 0xC8; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DACB: _MM_PERM_ENUM = 0xC9; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DACC: _MM_PERM_ENUM = 0xCA; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DACD: _MM_PERM_ENUM = 0xCB; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DADA: _MM_PERM_ENUM = 0xCC; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DADB: _MM_PERM_ENUM = 0xCD; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DADC: _MM_PERM_ENUM = 0xCE; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DADD: _MM_PERM_ENUM = 0xCF; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBAA: _MM_PERM_ENUM = 0xD0; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBAB: _MM_PERM_ENUM = 0xD1; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBAC: _MM_PERM_ENUM = 0xD2; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBAD: _MM_PERM_ENUM = 0xD3; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBBA: _MM_PERM_ENUM = 0xD4; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBBB: _MM_PERM_ENUM = 0xD5; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBBC: _MM_PERM_ENUM = 0xD6; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBBD: _MM_PERM_ENUM = 0xD7; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBCA: _MM_PERM_ENUM = 0xD8; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBCB: _MM_PERM_ENUM = 0xD9; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBCC: _MM_PERM_ENUM = 0xDA; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBCD: _MM_PERM_ENUM = 0xDB; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBDA: _MM_PERM_ENUM = 0xDC; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBDB: _MM_PERM_ENUM = 0xDD; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBDC: _MM_PERM_ENUM = 0xDE; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DBDD: _MM_PERM_ENUM = 0xDF; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCAA: _MM_PERM_ENUM = 0xE0; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCAB: _MM_PERM_ENUM = 0xE1; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCAC: _MM_PERM_ENUM = 0xE2; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCAD: _MM_PERM_ENUM = 0xE3; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCBA: _MM_PERM_ENUM = 0xE4; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCBB: _MM_PERM_ENUM = 0xE5; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCBC: _MM_PERM_ENUM = 0xE6; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCBD: _MM_PERM_ENUM = 0xE7; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCCA: _MM_PERM_ENUM = 0xE8; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCCB: _MM_PERM_ENUM = 0xE9; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCCC: _MM_PERM_ENUM = 0xEA; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCCD: _MM_PERM_ENUM = 0xEB; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCDA: _MM_PERM_ENUM = 0xEC; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCDB: _MM_PERM_ENUM = 0xED; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCDC: _MM_PERM_ENUM = 0xEE; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DCDD: _MM_PERM_ENUM = 0xEF; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDAA: _MM_PERM_ENUM = 0xF0; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDAB: _MM_PERM_ENUM = 0xF1; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDAC: _MM_PERM_ENUM = 0xF2; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDAD: _MM_PERM_ENUM = 0xF3; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDBA: _MM_PERM_ENUM = 0xF4; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDBB: _MM_PERM_ENUM = 0xF5; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDBC: _MM_PERM_ENUM = 0xF6; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDBD: _MM_PERM_ENUM = 0xF7; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDCA: _MM_PERM_ENUM = 0xF8; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDCB: _MM_PERM_ENUM = 0xF9; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDCC: _MM_PERM_ENUM = 0xFA; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDCD: _MM_PERM_ENUM = 0xFB; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDDA: _MM_PERM_ENUM = 0xFC; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDDB: _MM_PERM_ENUM = 0xFD; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDDC: _MM_PERM_ENUM = 0xFE; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub const _MM_PERM_DDDD: _MM_PERM_ENUM = 0xFF; #[allow(improper_ctypes)] diff --git a/crates/core_arch/src/x86/avx512ifma.rs b/crates/core_arch/src/x86/avx512ifma.rs index 541745a402..7c9d07f690 100644 --- a/crates/core_arch/src/x86/avx512ifma.rs +++ b/crates/core_arch/src/x86/avx512ifma.rs @@ -13,7 +13,7 @@ use stdarch_test::assert_instr; /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm512_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm512_madd52hi_epu64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { vpmadd52huq_512(a, b, c) } @@ -29,7 +29,7 @@ pub fn _mm512_madd52hi_epu64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm512_mask_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm512_mask_madd52hi_epu64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) -> __m512i { unsafe { simd_select_bitmask(k, vpmadd52huq_512(a, b, c), a) } @@ -45,7 +45,7 @@ pub fn _mm512_mask_madd52hi_epu64(a: __m512i, k: __mmask8, b: __m512i, c: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm512_maskz_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm512_maskz_madd52hi_epu64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { simd_select_bitmask(k, vpmadd52huq_512(a, b, c), _mm512_setzero_si512()) } @@ -60,7 +60,7 @@ pub fn _mm512_maskz_madd52hi_epu64(k: __mmask8, a: __m512i, b: __m512i, c: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm512_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm512_madd52lo_epu64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { vpmadd52luq_512(a, b, c) } @@ -76,7 +76,7 @@ pub fn _mm512_madd52lo_epu64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm512_mask_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm512_mask_madd52lo_epu64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) -> __m512i { unsafe { simd_select_bitmask(k, vpmadd52luq_512(a, b, c), a) } @@ -92,7 +92,7 @@ pub fn _mm512_mask_madd52lo_epu64(a: __m512i, k: __mmask8, b: __m512i, c: __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm512_maskz_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm512_maskz_madd52lo_epu64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { simd_select_bitmask(k, vpmadd52luq_512(a, b, c), _mm512_setzero_si512()) } @@ -107,7 +107,7 @@ pub fn _mm512_maskz_madd52lo_epu64(k: __mmask8, a: __m512i, b: __m512i, c: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_madd52hi_avx_epu64) #[inline] #[target_feature(enable = "avxifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm256_madd52hi_avx_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { vpmadd52huq_256(a, b, c) } @@ -122,7 +122,7 @@ pub fn _mm256_madd52hi_avx_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm256_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm256_madd52hi_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { vpmadd52huq_256(a, b, c) } @@ -138,7 +138,7 @@ pub fn _mm256_madd52hi_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm256_mask_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm256_mask_madd52hi_epu64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i { unsafe { simd_select_bitmask(k, vpmadd52huq_256(a, b, c), a) } @@ -154,7 +154,7 @@ pub fn _mm256_mask_madd52hi_epu64(a: __m256i, k: __mmask8, b: __m256i, c: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm256_maskz_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm256_maskz_madd52hi_epu64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { simd_select_bitmask(k, vpmadd52huq_256(a, b, c), _mm256_setzero_si256()) } @@ -169,7 +169,7 @@ pub fn _mm256_maskz_madd52hi_epu64(k: __mmask8, a: __m256i, b: __m256i, c: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_madd52lo_avx_epu64) #[inline] #[target_feature(enable = "avxifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm256_madd52lo_avx_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { vpmadd52luq_256(a, b, c) } @@ -184,7 +184,7 @@ pub fn _mm256_madd52lo_avx_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm256_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm256_madd52lo_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { vpmadd52luq_256(a, b, c) } @@ -200,7 +200,7 @@ pub fn _mm256_madd52lo_epu64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm256_mask_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm256_mask_madd52lo_epu64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i { unsafe { simd_select_bitmask(k, vpmadd52luq_256(a, b, c), a) } @@ -216,7 +216,7 @@ pub fn _mm256_mask_madd52lo_epu64(a: __m256i, k: __mmask8, b: __m256i, c: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm256_maskz_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm256_maskz_madd52lo_epu64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { simd_select_bitmask(k, vpmadd52luq_256(a, b, c), _mm256_setzero_si256()) } @@ -231,7 +231,7 @@ pub fn _mm256_maskz_madd52lo_epu64(k: __mmask8, a: __m256i, b: __m256i, c: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_madd52hi_avx_epu64) #[inline] #[target_feature(enable = "avxifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm_madd52hi_avx_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { vpmadd52huq_128(a, b, c) } @@ -246,7 +246,7 @@ pub fn _mm_madd52hi_avx_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm_madd52hi_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { vpmadd52huq_128(a, b, c) } @@ -262,7 +262,7 @@ pub fn _mm_madd52hi_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm_mask_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm_mask_madd52hi_epu64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i { unsafe { simd_select_bitmask(k, vpmadd52huq_128(a, b, c), a) } @@ -278,7 +278,7 @@ pub fn _mm_mask_madd52hi_epu64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm_maskz_madd52hi_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52huq))] pub fn _mm_maskz_madd52hi_epu64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { simd_select_bitmask(k, vpmadd52huq_128(a, b, c), _mm_setzero_si128()) } @@ -293,7 +293,7 @@ pub fn _mm_maskz_madd52hi_epu64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_madd52lo_avx_epu64) #[inline] #[target_feature(enable = "avxifma")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm_madd52lo_avx_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { vpmadd52luq_128(a, b, c) } @@ -308,7 +308,7 @@ pub fn _mm_madd52lo_avx_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm_madd52lo_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { vpmadd52luq_128(a, b, c) } @@ -324,7 +324,7 @@ pub fn _mm_madd52lo_epu64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm_mask_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm_mask_madd52lo_epu64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i { unsafe { simd_select_bitmask(k, vpmadd52luq_128(a, b, c), a) } @@ -340,7 +340,7 @@ pub fn _mm_mask_madd52lo_epu64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#avx512techs=AVX512IFMA52&text=_mm_maskz_madd52lo_epu64) #[inline] #[target_feature(enable = "avx512ifma,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmadd52luq))] pub fn _mm_maskz_madd52lo_epu64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { simd_select_bitmask(k, vpmadd52luq_128(a, b, c), _mm_setzero_si128()) } diff --git a/crates/core_arch/src/x86/avx512vbmi.rs b/crates/core_arch/src/x86/avx512vbmi.rs index cd3f4ca03d..3527ccc9e4 100644 --- a/crates/core_arch/src/x86/avx512vbmi.rs +++ b/crates/core_arch/src/x86/avx512vbmi.rs @@ -9,7 +9,7 @@ use stdarch_test::assert_instr; /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex2var_epi8&expand=4262) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2b pub fn _mm512_permutex2var_epi8(a: __m512i, idx: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpermi2b(a.as_i8x64(), idx.as_i8x64(), b.as_i8x64())) } @@ -20,7 +20,7 @@ pub fn _mm512_permutex2var_epi8(a: __m512i, idx: __m512i, b: __m512i) -> __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex2var_epi8&expand=4259) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2b))] pub fn _mm512_mask_permutex2var_epi8( a: __m512i, @@ -39,7 +39,7 @@ pub fn _mm512_mask_permutex2var_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex2var_epi8&expand=4261) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2b pub fn _mm512_maskz_permutex2var_epi8( k: __mmask64, @@ -58,7 +58,7 @@ pub fn _mm512_maskz_permutex2var_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask2_permutex2var_epi8&expand=4260) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2b))] pub fn _mm512_mask2_permutex2var_epi8( a: __m512i, @@ -77,7 +77,7 @@ pub fn _mm512_mask2_permutex2var_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex2var_epi8&expand=4258) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2b pub fn _mm256_permutex2var_epi8(a: __m256i, idx: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpermi2b256(a.as_i8x32(), idx.as_i8x32(), b.as_i8x32())) } @@ -88,7 +88,7 @@ pub fn _mm256_permutex2var_epi8(a: __m256i, idx: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex2var_epi8&expand=4255) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2b))] pub fn _mm256_mask_permutex2var_epi8( a: __m256i, @@ -107,7 +107,7 @@ pub fn _mm256_mask_permutex2var_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex2var_epi8&expand=4257) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2b pub fn _mm256_maskz_permutex2var_epi8( k: __mmask32, @@ -126,7 +126,7 @@ pub fn _mm256_maskz_permutex2var_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask2_permutex2var_epi8&expand=4256) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2b))] pub fn _mm256_mask2_permutex2var_epi8( a: __m256i, @@ -145,7 +145,7 @@ pub fn _mm256_mask2_permutex2var_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutex2var_epi8&expand=4254) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2b pub fn _mm_permutex2var_epi8(a: __m128i, idx: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpermi2b128(a.as_i8x16(), idx.as_i8x16(), b.as_i8x16())) } @@ -156,7 +156,7 @@ pub fn _mm_permutex2var_epi8(a: __m128i, idx: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutex2var_epi8&expand=4251) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermt2b))] pub fn _mm_mask_permutex2var_epi8(a: __m128i, k: __mmask16, idx: __m128i, b: __m128i) -> __m128i { unsafe { @@ -170,7 +170,7 @@ pub fn _mm_mask_permutex2var_epi8(a: __m128i, k: __mmask16, idx: __m128i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutex2var_epi8&expand=4253) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vperm))] //should be vpermi2b pub fn _mm_maskz_permutex2var_epi8(k: __mmask16, a: __m128i, idx: __m128i, b: __m128i) -> __m128i { unsafe { @@ -184,7 +184,7 @@ pub fn _mm_maskz_permutex2var_epi8(k: __mmask16, a: __m128i, idx: __m128i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask2_permutex2var_epi8&expand=4252) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermi2b))] pub fn _mm_mask2_permutex2var_epi8(a: __m128i, idx: __m128i, k: __mmask16, b: __m128i) -> __m128i { unsafe { @@ -198,7 +198,7 @@ pub fn _mm_mask2_permutex2var_epi8(a: __m128i, idx: __m128i, k: __mmask16, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutexvar_epi8&expand=4316) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm512_permutexvar_epi8(idx: __m512i, a: __m512i) -> __m512i { unsafe { transmute(vpermb(a.as_i8x64(), idx.as_i8x64())) } @@ -209,7 +209,7 @@ pub fn _mm512_permutexvar_epi8(idx: __m512i, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutexvar_epi8&expand=4314) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm512_mask_permutexvar_epi8( src: __m512i, @@ -228,7 +228,7 @@ pub fn _mm512_mask_permutexvar_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutexvar_epi8&expand=4315) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm512_maskz_permutexvar_epi8(k: __mmask64, idx: __m512i, a: __m512i) -> __m512i { unsafe { @@ -242,7 +242,7 @@ pub fn _mm512_maskz_permutexvar_epi8(k: __mmask64, idx: __m512i, a: __m512i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutexvar_epi8&expand=4313) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm256_permutexvar_epi8(idx: __m256i, a: __m256i) -> __m256i { unsafe { transmute(vpermb256(a.as_i8x32(), idx.as_i8x32())) } @@ -253,7 +253,7 @@ pub fn _mm256_permutexvar_epi8(idx: __m256i, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutexvar_epi8&expand=4311) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm256_mask_permutexvar_epi8( src: __m256i, @@ -272,7 +272,7 @@ pub fn _mm256_mask_permutexvar_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutexvar_epi8&expand=4312) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm256_maskz_permutexvar_epi8(k: __mmask32, idx: __m256i, a: __m256i) -> __m256i { unsafe { @@ -286,7 +286,7 @@ pub fn _mm256_maskz_permutexvar_epi8(k: __mmask32, idx: __m256i, a: __m256i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutexvar_epi8&expand=4310) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm_permutexvar_epi8(idx: __m128i, a: __m128i) -> __m128i { unsafe { transmute(vpermb128(a.as_i8x16(), idx.as_i8x16())) } @@ -297,7 +297,7 @@ pub fn _mm_permutexvar_epi8(idx: __m128i, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutexvar_epi8&expand=4308) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm_mask_permutexvar_epi8(src: __m128i, k: __mmask16, idx: __m128i, a: __m128i) -> __m128i { unsafe { @@ -311,7 +311,7 @@ pub fn _mm_mask_permutexvar_epi8(src: __m128i, k: __mmask16, idx: __m128i, a: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutexvar_epi8&expand=4309) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpermb))] pub fn _mm_maskz_permutexvar_epi8(k: __mmask16, idx: __m128i, a: __m128i) -> __m128i { unsafe { @@ -325,7 +325,7 @@ pub fn _mm_maskz_permutexvar_epi8(k: __mmask16, idx: __m128i, a: __m128i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_multishift_epi64_epi8&expand=4026) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm512_multishift_epi64_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpmultishiftqb(a.as_i8x64(), b.as_i8x64())) } @@ -336,7 +336,7 @@ pub fn _mm512_multishift_epi64_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_multishift_epi64_epi8&expand=4024) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm512_mask_multishift_epi64_epi8( src: __m512i, @@ -355,7 +355,7 @@ pub fn _mm512_mask_multishift_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_multishift_epi64_epi8&expand=4025) #[inline] #[target_feature(enable = "avx512vbmi")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm512_maskz_multishift_epi64_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -369,7 +369,7 @@ pub fn _mm512_maskz_multishift_epi64_epi8(k: __mmask64, a: __m512i, b: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_multishift_epi64_epi8&expand=4023) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm256_multishift_epi64_epi8(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpmultishiftqb256(a.as_i8x32(), b.as_i8x32())) } @@ -380,7 +380,7 @@ pub fn _mm256_multishift_epi64_epi8(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_multishift_epi64_epi8&expand=4021) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm256_mask_multishift_epi64_epi8( src: __m256i, @@ -399,7 +399,7 @@ pub fn _mm256_mask_multishift_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_multishift_epi64_epi8&expand=4022) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm256_maskz_multishift_epi64_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -413,7 +413,7 @@ pub fn _mm256_maskz_multishift_epi64_epi8(k: __mmask32, a: __m256i, b: __m256i) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/IntrinsicsGuide/#text=_mm_multishift_epi64_epi8&expand=4020) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm_multishift_epi64_epi8(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpmultishiftqb128(a.as_i8x16(), b.as_i8x16())) } @@ -424,7 +424,7 @@ pub fn _mm_multishift_epi64_epi8(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_multishift_epi64_epi8&expand=4018) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm_mask_multishift_epi64_epi8( src: __m128i, @@ -443,7 +443,7 @@ pub fn _mm_mask_multishift_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_multishift_epi64_epi8&expand=4019) #[inline] #[target_feature(enable = "avx512vbmi,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmultishiftqb))] pub fn _mm_maskz_multishift_epi64_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { diff --git a/crates/core_arch/src/x86/avx512vbmi2.rs b/crates/core_arch/src/x86/avx512vbmi2.rs index 7fc22985d5..c722f7b370 100644 --- a/crates/core_arch/src/x86/avx512vbmi2.rs +++ b/crates/core_arch/src/x86/avx512vbmi2.rs @@ -12,7 +12,7 @@ use stdarch_test::assert_instr; #[inline] #[target_feature(enable = "avx512vbmi2")] #[cfg_attr(test, assert_instr(vpexpandw))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_expandloadu_epi16( src: __m512i, k: __mmask32, @@ -27,7 +27,7 @@ pub unsafe fn _mm512_mask_expandloadu_epi16( #[inline] #[target_feature(enable = "avx512vbmi2")] #[cfg_attr(test, assert_instr(vpexpandw))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_expandloadu_epi16(k: __mmask32, mem_addr: *const i16) -> __m512i { _mm512_mask_expandloadu_epi16(_mm512_setzero_si512(), k, mem_addr) } @@ -38,7 +38,7 @@ pub unsafe fn _mm512_maskz_expandloadu_epi16(k: __mmask32, mem_addr: *const i16) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandw))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_expandloadu_epi16( src: __m256i, k: __mmask16, @@ -53,7 +53,7 @@ pub unsafe fn _mm256_mask_expandloadu_epi16( #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandw))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_expandloadu_epi16(k: __mmask16, mem_addr: *const i16) -> __m256i { _mm256_mask_expandloadu_epi16(_mm256_setzero_si256(), k, mem_addr) } @@ -64,7 +64,7 @@ pub unsafe fn _mm256_maskz_expandloadu_epi16(k: __mmask16, mem_addr: *const i16) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandw))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_expandloadu_epi16( src: __m128i, k: __mmask8, @@ -79,7 +79,7 @@ pub unsafe fn _mm_mask_expandloadu_epi16( #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandw))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_expandloadu_epi16(k: __mmask8, mem_addr: *const i16) -> __m128i { _mm_mask_expandloadu_epi16(_mm_setzero_si128(), k, mem_addr) } @@ -90,7 +90,7 @@ pub unsafe fn _mm_maskz_expandloadu_epi16(k: __mmask8, mem_addr: *const i16) -> #[inline] #[target_feature(enable = "avx512vbmi2")] #[cfg_attr(test, assert_instr(vpexpandb))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_mask_expandloadu_epi8( src: __m512i, k: __mmask64, @@ -105,7 +105,7 @@ pub unsafe fn _mm512_mask_expandloadu_epi8( #[inline] #[target_feature(enable = "avx512vbmi2")] #[cfg_attr(test, assert_instr(vpexpandb))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm512_maskz_expandloadu_epi8(k: __mmask64, mem_addr: *const i8) -> __m512i { _mm512_mask_expandloadu_epi8(_mm512_setzero_si512(), k, mem_addr) } @@ -116,7 +116,7 @@ pub unsafe fn _mm512_maskz_expandloadu_epi8(k: __mmask64, mem_addr: *const i8) - #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandb))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_mask_expandloadu_epi8( src: __m256i, k: __mmask32, @@ -131,7 +131,7 @@ pub unsafe fn _mm256_mask_expandloadu_epi8( #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandb))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_maskz_expandloadu_epi8(k: __mmask32, mem_addr: *const i8) -> __m256i { _mm256_mask_expandloadu_epi8(_mm256_setzero_si256(), k, mem_addr) } @@ -142,7 +142,7 @@ pub unsafe fn _mm256_maskz_expandloadu_epi8(k: __mmask32, mem_addr: *const i8) - #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandb))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_mask_expandloadu_epi8( src: __m128i, k: __mmask16, @@ -157,7 +157,7 @@ pub unsafe fn _mm_mask_expandloadu_epi8( #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] #[cfg_attr(test, assert_instr(vpexpandb))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_maskz_expandloadu_epi8(k: __mmask16, mem_addr: *const i8) -> __m128i { _mm_mask_expandloadu_epi8(_mm_setzero_si128(), k, mem_addr) } @@ -167,7 +167,7 @@ pub unsafe fn _mm_maskz_expandloadu_epi8(k: __mmask16, mem_addr: *const i8) -> _ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compressstoreu_epi16) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub unsafe fn _mm512_mask_compressstoreu_epi16(base_addr: *mut i16, k: __mmask32, a: __m512i) { vcompressstorew(base_addr as *mut _, a.as_i16x32(), k) @@ -178,7 +178,7 @@ pub unsafe fn _mm512_mask_compressstoreu_epi16(base_addr: *mut i16, k: __mmask32 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compressstoreu_epi16) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub unsafe fn _mm256_mask_compressstoreu_epi16(base_addr: *mut i16, k: __mmask16, a: __m256i) { vcompressstorew256(base_addr as *mut _, a.as_i16x16(), k) @@ -189,7 +189,7 @@ pub unsafe fn _mm256_mask_compressstoreu_epi16(base_addr: *mut i16, k: __mmask16 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compressstoreu_epi16) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub unsafe fn _mm_mask_compressstoreu_epi16(base_addr: *mut i16, k: __mmask8, a: __m128i) { vcompressstorew128(base_addr as *mut _, a.as_i16x8(), k) @@ -200,7 +200,7 @@ pub unsafe fn _mm_mask_compressstoreu_epi16(base_addr: *mut i16, k: __mmask8, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compressstoreu_epi8) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub unsafe fn _mm512_mask_compressstoreu_epi8(base_addr: *mut i8, k: __mmask64, a: __m512i) { vcompressstoreb(base_addr, a.as_i8x64(), k) @@ -211,7 +211,7 @@ pub unsafe fn _mm512_mask_compressstoreu_epi8(base_addr: *mut i8, k: __mmask64, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compressstoreu_epi8) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub unsafe fn _mm256_mask_compressstoreu_epi8(base_addr: *mut i8, k: __mmask32, a: __m256i) { vcompressstoreb256(base_addr, a.as_i8x32(), k) @@ -222,7 +222,7 @@ pub unsafe fn _mm256_mask_compressstoreu_epi8(base_addr: *mut i8, k: __mmask32, /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compressstoreu_epi8) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub unsafe fn _mm_mask_compressstoreu_epi8(base_addr: *mut i8, k: __mmask16, a: __m128i) { vcompressstoreb128(base_addr, a.as_i8x16(), k) @@ -233,7 +233,7 @@ pub unsafe fn _mm_mask_compressstoreu_epi8(base_addr: *mut i8, k: __mmask16, a: /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compress_epi16&expand=1192) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub fn _mm512_mask_compress_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { unsafe { transmute(vpcompressw(a.as_i16x32(), src.as_i16x32(), k)) } @@ -244,7 +244,7 @@ pub fn _mm512_mask_compress_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_compress_epi16&expand=1193) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub fn _mm512_maskz_compress_epi16(k: __mmask32, a: __m512i) -> __m512i { unsafe { transmute(vpcompressw(a.as_i16x32(), i16x32::ZERO, k)) } @@ -255,7 +255,7 @@ pub fn _mm512_maskz_compress_epi16(k: __mmask32, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compress_epi16&expand=1190) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub fn _mm256_mask_compress_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i { unsafe { transmute(vpcompressw256(a.as_i16x16(), src.as_i16x16(), k)) } @@ -266,7 +266,7 @@ pub fn _mm256_mask_compress_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_compress_epi16&expand=1191) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub fn _mm256_maskz_compress_epi16(k: __mmask16, a: __m256i) -> __m256i { unsafe { transmute(vpcompressw256(a.as_i16x16(), i16x16::ZERO, k)) } @@ -277,7 +277,7 @@ pub fn _mm256_maskz_compress_epi16(k: __mmask16, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compress_epi16&expand=1188) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub fn _mm_mask_compress_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpcompressw128(a.as_i16x8(), src.as_i16x8(), k)) } @@ -288,7 +288,7 @@ pub fn _mm_mask_compress_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_compress_epi16&expand=1189) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressw))] pub fn _mm_maskz_compress_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpcompressw128(a.as_i16x8(), i16x8::ZERO, k)) } @@ -299,7 +299,7 @@ pub fn _mm_maskz_compress_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_compress_epi8&expand=1210) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub fn _mm512_mask_compress_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i { unsafe { transmute(vpcompressb(a.as_i8x64(), src.as_i8x64(), k)) } @@ -310,7 +310,7 @@ pub fn _mm512_mask_compress_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_compress_epi8&expand=1211) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub fn _mm512_maskz_compress_epi8(k: __mmask64, a: __m512i) -> __m512i { unsafe { transmute(vpcompressb(a.as_i8x64(), i8x64::ZERO, k)) } @@ -321,7 +321,7 @@ pub fn _mm512_maskz_compress_epi8(k: __mmask64, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_compress_epi8&expand=1208) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub fn _mm256_mask_compress_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i { unsafe { transmute(vpcompressb256(a.as_i8x32(), src.as_i8x32(), k)) } @@ -332,7 +332,7 @@ pub fn _mm256_mask_compress_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_compress_epi8&expand=1209) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub fn _mm256_maskz_compress_epi8(k: __mmask32, a: __m256i) -> __m256i { unsafe { transmute(vpcompressb256(a.as_i8x32(), i8x32::ZERO, k)) } @@ -343,7 +343,7 @@ pub fn _mm256_maskz_compress_epi8(k: __mmask32, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_compress_epi8&expand=1206) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub fn _mm_mask_compress_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { unsafe { transmute(vpcompressb128(a.as_i8x16(), src.as_i8x16(), k)) } @@ -354,7 +354,7 @@ pub fn _mm_mask_compress_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_compress_epi8&expand=1207) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpcompressb))] pub fn _mm_maskz_compress_epi8(k: __mmask16, a: __m128i) -> __m128i { unsafe { transmute(vpcompressb128(a.as_i8x16(), i8x16::ZERO, k)) } @@ -365,7 +365,7 @@ pub fn _mm_maskz_compress_epi8(k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_expand_epi16&expand=2310) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandw))] pub fn _mm512_mask_expand_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i { unsafe { transmute(vpexpandw(a.as_i16x32(), src.as_i16x32(), k)) } @@ -376,7 +376,7 @@ pub fn _mm512_mask_expand_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_expand_epi16&expand=2311) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandw))] pub fn _mm512_maskz_expand_epi16(k: __mmask32, a: __m512i) -> __m512i { unsafe { transmute(vpexpandw(a.as_i16x32(), i16x32::ZERO, k)) } @@ -387,7 +387,7 @@ pub fn _mm512_maskz_expand_epi16(k: __mmask32, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_expand_epi16&expand=2308) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandw))] pub fn _mm256_mask_expand_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i { unsafe { transmute(vpexpandw256(a.as_i16x16(), src.as_i16x16(), k)) } @@ -398,7 +398,7 @@ pub fn _mm256_mask_expand_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_expand_epi16&expand=2309) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandw))] pub fn _mm256_maskz_expand_epi16(k: __mmask16, a: __m256i) -> __m256i { unsafe { transmute(vpexpandw256(a.as_i16x16(), i16x16::ZERO, k)) } @@ -409,7 +409,7 @@ pub fn _mm256_maskz_expand_epi16(k: __mmask16, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_expand_epi16&expand=2306) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandw))] pub fn _mm_mask_expand_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpexpandw128(a.as_i16x8(), src.as_i16x8(), k)) } @@ -420,7 +420,7 @@ pub fn _mm_mask_expand_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_expand_epi16&expand=2307) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandw))] pub fn _mm_maskz_expand_epi16(k: __mmask8, a: __m128i) -> __m128i { unsafe { transmute(vpexpandw128(a.as_i16x8(), i16x8::ZERO, k)) } @@ -431,7 +431,7 @@ pub fn _mm_maskz_expand_epi16(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_expand_epi8&expand=2328) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandb))] pub fn _mm512_mask_expand_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i { unsafe { transmute(vpexpandb(a.as_i8x64(), src.as_i8x64(), k)) } @@ -442,7 +442,7 @@ pub fn _mm512_mask_expand_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_expand_epi8&expand=2329) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandb))] pub fn _mm512_maskz_expand_epi8(k: __mmask64, a: __m512i) -> __m512i { unsafe { transmute(vpexpandb(a.as_i8x64(), i8x64::ZERO, k)) } @@ -453,7 +453,7 @@ pub fn _mm512_maskz_expand_epi8(k: __mmask64, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_expand_epi8&expand=2326) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandb))] pub fn _mm256_mask_expand_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i { unsafe { transmute(vpexpandb256(a.as_i8x32(), src.as_i8x32(), k)) } @@ -464,7 +464,7 @@ pub fn _mm256_mask_expand_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_expand_epi8&expand=2327) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandb))] pub fn _mm256_maskz_expand_epi8(k: __mmask32, a: __m256i) -> __m256i { unsafe { transmute(vpexpandb256(a.as_i8x32(), i8x32::ZERO, k)) } @@ -475,7 +475,7 @@ pub fn _mm256_maskz_expand_epi8(k: __mmask32, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_expand_epi8&expand=2324) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandb))] pub fn _mm_mask_expand_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { unsafe { transmute(vpexpandb128(a.as_i8x16(), src.as_i8x16(), k)) } @@ -486,7 +486,7 @@ pub fn _mm_mask_expand_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_expand_epi8&expand=2325) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpexpandb))] pub fn _mm_maskz_expand_epi8(k: __mmask16, a: __m128i) -> __m128i { unsafe { transmute(vpexpandb128(a.as_i8x16(), i8x16::ZERO, k)) } @@ -497,7 +497,7 @@ pub fn _mm_maskz_expand_epi8(k: __mmask16, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shldv_epi64&expand=5087) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm512_shldv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { transmute(vpshldvq(a.as_i64x8(), b.as_i64x8(), c.as_i64x8())) } @@ -508,7 +508,7 @@ pub fn _mm512_shldv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shldv_epi64&expand=5085) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm512_mask_shldv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -522,7 +522,7 @@ pub fn _mm512_mask_shldv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shldv_epi64&expand=5086) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm512_maskz_shldv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -536,7 +536,7 @@ pub fn _mm512_maskz_shldv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shldv_epi64&expand=5084) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm256_shldv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { transmute(vpshldvq256(a.as_i64x4(), b.as_i64x4(), c.as_i64x4())) } @@ -547,7 +547,7 @@ pub fn _mm256_shldv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shldv_epi64&expand=5082) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm256_mask_shldv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -561,7 +561,7 @@ pub fn _mm256_mask_shldv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shldv_epi64&expand=5083) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm256_maskz_shldv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -575,7 +575,7 @@ pub fn _mm256_maskz_shldv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shldv_epi64&expand=5081) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm_shldv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { transmute(vpshldvq128(a.as_i64x2(), b.as_i64x2(), c.as_i64x2())) } @@ -586,7 +586,7 @@ pub fn _mm_shldv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shldv_epi64&expand=5079) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm_mask_shldv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -600,7 +600,7 @@ pub fn _mm_mask_shldv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shldv_epi64&expand=5080) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvq))] pub fn _mm_maskz_shldv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -614,7 +614,7 @@ pub fn _mm_maskz_shldv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shldv_epi32&expand=5078) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm512_shldv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { transmute(vpshldvd(a.as_i32x16(), b.as_i32x16(), c.as_i32x16())) } @@ -625,7 +625,7 @@ pub fn _mm512_shldv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shldv_epi32&expand=5076) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm512_mask_shldv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -639,7 +639,7 @@ pub fn _mm512_mask_shldv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shldv_epi32&expand=5077) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm512_maskz_shldv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -653,7 +653,7 @@ pub fn _mm512_maskz_shldv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shldv_epi32&expand=5075) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm256_shldv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { transmute(vpshldvd256(a.as_i32x8(), b.as_i32x8(), c.as_i32x8())) } @@ -664,7 +664,7 @@ pub fn _mm256_shldv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shldv_epi32&expand=5073) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm256_mask_shldv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -678,7 +678,7 @@ pub fn _mm256_mask_shldv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shldv_epi32&expand=5074) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm256_maskz_shldv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -692,7 +692,7 @@ pub fn _mm256_maskz_shldv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shldv_epi32&expand=5072) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm_shldv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { transmute(vpshldvd128(a.as_i32x4(), b.as_i32x4(), c.as_i32x4())) } @@ -703,7 +703,7 @@ pub fn _mm_shldv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shldv_epi32&expand=5070) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm_mask_shldv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -717,7 +717,7 @@ pub fn _mm_mask_shldv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shldv_epi32&expand=5071) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvd))] pub fn _mm_maskz_shldv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -731,7 +731,7 @@ pub fn _mm_maskz_shldv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shldv_epi16&expand=5069) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm512_shldv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { transmute(vpshldvw(a.as_i16x32(), b.as_i16x32(), c.as_i16x32())) } @@ -742,7 +742,7 @@ pub fn _mm512_shldv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shldv_epi16&expand=5067) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm512_mask_shldv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -756,7 +756,7 @@ pub fn _mm512_mask_shldv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shldv_epi16&expand=5068) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm512_maskz_shldv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -770,7 +770,7 @@ pub fn _mm512_maskz_shldv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shldv_epi16&expand=5066) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm256_shldv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { transmute(vpshldvw256(a.as_i16x16(), b.as_i16x16(), c.as_i16x16())) } @@ -781,7 +781,7 @@ pub fn _mm256_shldv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shldv_epi16&expand=5064) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm256_mask_shldv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -795,7 +795,7 @@ pub fn _mm256_mask_shldv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shldv_epi16&expand=5065) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm256_maskz_shldv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -809,7 +809,7 @@ pub fn _mm256_maskz_shldv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shldv_epi16&expand=5063) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm_shldv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { transmute(vpshldvw128(a.as_i16x8(), b.as_i16x8(), c.as_i16x8())) } @@ -820,7 +820,7 @@ pub fn _mm_shldv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shldv_epi16&expand=5061) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm_mask_shldv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -834,7 +834,7 @@ pub fn _mm_mask_shldv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shldv_epi16&expand=5062) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldvw))] pub fn _mm_maskz_shldv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -848,7 +848,7 @@ pub fn _mm_maskz_shldv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shrdv_epi64&expand=5141) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm512_shrdv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { transmute(vpshrdvq(b.as_i64x8(), a.as_i64x8(), c.as_i64x8())) } @@ -859,7 +859,7 @@ pub fn _mm512_shrdv_epi64(a: __m512i, b: __m512i, c: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shrdv_epi64&expand=5139) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm512_mask_shrdv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -873,7 +873,7 @@ pub fn _mm512_mask_shrdv_epi64(a: __m512i, k: __mmask8, b: __m512i, c: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shrdv_epi64&expand=5140) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm512_maskz_shrdv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -887,7 +887,7 @@ pub fn _mm512_maskz_shrdv_epi64(k: __mmask8, a: __m512i, b: __m512i, c: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shrdv_epi64&expand=5138) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm256_shrdv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { transmute(vpshrdvq256(b.as_i64x4(), a.as_i64x4(), c.as_i64x4())) } @@ -898,7 +898,7 @@ pub fn _mm256_shrdv_epi64(a: __m256i, b: __m256i, c: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shrdv_epi64&expand=5136) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm256_mask_shrdv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -912,7 +912,7 @@ pub fn _mm256_mask_shrdv_epi64(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shrdv_epi64&expand=5137) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm256_maskz_shrdv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -926,7 +926,7 @@ pub fn _mm256_maskz_shrdv_epi64(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shrdv_epi64&expand=5135) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm_shrdv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { transmute(vpshrdvq128(b.as_i64x2(), a.as_i64x2(), c.as_i64x2())) } @@ -937,7 +937,7 @@ pub fn _mm_shrdv_epi64(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shrdv_epi64&expand=5133) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm_mask_shrdv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -951,7 +951,7 @@ pub fn _mm_mask_shrdv_epi64(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shrdv_epi64&expand=5134) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvq))] pub fn _mm_maskz_shrdv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -965,7 +965,7 @@ pub fn _mm_maskz_shrdv_epi64(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shrdv_epi32&expand=5132) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm512_shrdv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { transmute(vpshrdvd(b.as_i32x16(), a.as_i32x16(), c.as_i32x16())) } @@ -976,7 +976,7 @@ pub fn _mm512_shrdv_epi32(a: __m512i, b: __m512i, c: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shrdv_epi32&expand=5130) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm512_mask_shrdv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -990,7 +990,7 @@ pub fn _mm512_mask_shrdv_epi32(a: __m512i, k: __mmask16, b: __m512i, c: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shrdv_epi32&expand=5131) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm512_maskz_shrdv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -1004,7 +1004,7 @@ pub fn _mm512_maskz_shrdv_epi32(k: __mmask16, a: __m512i, b: __m512i, c: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shrdv_epi32&expand=5129) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm256_shrdv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { transmute(vpshrdvd256(b.as_i32x8(), a.as_i32x8(), c.as_i32x8())) } @@ -1015,7 +1015,7 @@ pub fn _mm256_shrdv_epi32(a: __m256i, b: __m256i, c: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shrdv_epi32&expand=5127) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm256_mask_shrdv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -1029,7 +1029,7 @@ pub fn _mm256_mask_shrdv_epi32(a: __m256i, k: __mmask8, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shrdv_epi32&expand=5128) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm256_maskz_shrdv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -1043,7 +1043,7 @@ pub fn _mm256_maskz_shrdv_epi32(k: __mmask8, a: __m256i, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shrdv_epi32&expand=5126) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm_shrdv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { transmute(vpshrdvd128(b.as_i32x4(), a.as_i32x4(), c.as_i32x4())) } @@ -1054,7 +1054,7 @@ pub fn _mm_shrdv_epi32(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shrdv_epi32&expand=5124) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm_mask_shrdv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -1068,7 +1068,7 @@ pub fn _mm_mask_shrdv_epi32(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shrdv_epi32&expand=5125) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvd))] pub fn _mm_maskz_shrdv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -1082,7 +1082,7 @@ pub fn _mm_maskz_shrdv_epi32(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shrdv_epi16&expand=5123) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm512_shrdv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { transmute(vpshrdvw(b.as_i16x32(), a.as_i16x32(), c.as_i16x32())) } @@ -1093,7 +1093,7 @@ pub fn _mm512_shrdv_epi16(a: __m512i, b: __m512i, c: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shrdv_epi16&expand=5121) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm512_mask_shrdv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -1107,7 +1107,7 @@ pub fn _mm512_mask_shrdv_epi16(a: __m512i, k: __mmask32, b: __m512i, c: __m512i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shrdv_epi16&expand=5122) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm512_maskz_shrdv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i) -> __m512i { unsafe { @@ -1121,7 +1121,7 @@ pub fn _mm512_maskz_shrdv_epi16(k: __mmask32, a: __m512i, b: __m512i, c: __m512i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shrdv_epi16&expand=5120) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm256_shrdv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { transmute(vpshrdvw256(b.as_i16x16(), a.as_i16x16(), c.as_i16x16())) } @@ -1132,7 +1132,7 @@ pub fn _mm256_shrdv_epi16(a: __m256i, b: __m256i, c: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shrdv_epi16&expand=5118) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm256_mask_shrdv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -1146,7 +1146,7 @@ pub fn _mm256_mask_shrdv_epi16(a: __m256i, k: __mmask16, b: __m256i, c: __m256i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shrdv_epi16&expand=5119) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm256_maskz_shrdv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i) -> __m256i { unsafe { @@ -1160,7 +1160,7 @@ pub fn _mm256_maskz_shrdv_epi16(k: __mmask16, a: __m256i, b: __m256i, c: __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shrdv_epi16&expand=5117) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm_shrdv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { transmute(vpshrdvw128(b.as_i16x8(), a.as_i16x8(), c.as_i16x8())) } @@ -1171,7 +1171,7 @@ pub fn _mm_shrdv_epi16(a: __m128i, b: __m128i, c: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shrdv_epi16&expand=5115) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm_mask_shrdv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -1185,7 +1185,7 @@ pub fn _mm_mask_shrdv_epi16(a: __m128i, k: __mmask8, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shrdv_epi16&expand=5116) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshrdvw))] pub fn _mm_maskz_shrdv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> __m128i { unsafe { @@ -1199,7 +1199,7 @@ pub fn _mm_maskz_shrdv_epi16(k: __mmask8, a: __m128i, b: __m128i, c: __m128i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shldi_epi64&expand=5060) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm512_shldi_epi64(a: __m512i, b: __m512i) -> __m512i { @@ -1212,7 +1212,7 @@ pub fn _mm512_shldi_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shldi_epi64&expand=5058) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shldi_epi64( @@ -1233,7 +1233,7 @@ pub fn _mm512_mask_shldi_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shldi_epi64&expand=5059) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shldi_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { @@ -1249,7 +1249,7 @@ pub fn _mm512_maskz_shldi_epi64(k: __mmask8, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shldi_epi64&expand=5057) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_shldi_epi64(a: __m256i, b: __m256i) -> __m256i { @@ -1262,7 +1262,7 @@ pub fn _mm256_shldi_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shldi_epi64&expand=5055) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shldi_epi64( @@ -1283,7 +1283,7 @@ pub fn _mm256_mask_shldi_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shldi_epi64&expand=5056) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shldi_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { @@ -1299,7 +1299,7 @@ pub fn _mm256_maskz_shldi_epi64(k: __mmask8, a: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shldi_epi64&expand=5054) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_shldi_epi64(a: __m128i, b: __m128i) -> __m128i { @@ -1312,7 +1312,7 @@ pub fn _mm_shldi_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shldi_epi64&expand=5052) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_shldi_epi64( @@ -1333,7 +1333,7 @@ pub fn _mm_mask_shldi_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shldi_epi64&expand=5053) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_shldi_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { @@ -1349,7 +1349,7 @@ pub fn _mm_maskz_shldi_epi64(k: __mmask8, a: __m128i, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shldi_epi32&expand=5051) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm512_shldi_epi32(a: __m512i, b: __m512i) -> __m512i { @@ -1362,7 +1362,7 @@ pub fn _mm512_shldi_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shldi_epi32&expand=5049) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shldi_epi32( @@ -1383,7 +1383,7 @@ pub fn _mm512_mask_shldi_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shldi_epi32&expand=5050) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shldi_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { @@ -1399,7 +1399,7 @@ pub fn _mm512_maskz_shldi_epi32(k: __mmask16, a: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shldi_epi32&expand=5048) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_shldi_epi32(a: __m256i, b: __m256i) -> __m256i { @@ -1412,7 +1412,7 @@ pub fn _mm256_shldi_epi32(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shldi_epi32&expand=5046) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shldi_epi32( @@ -1433,7 +1433,7 @@ pub fn _mm256_mask_shldi_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shldi_epi32&expand=5047) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shldi_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { @@ -1449,7 +1449,7 @@ pub fn _mm256_maskz_shldi_epi32(k: __mmask8, a: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shldi_epi32&expand=5045) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_shldi_epi32(a: __m128i, b: __m128i) -> __m128i { @@ -1462,7 +1462,7 @@ pub fn _mm_shldi_epi32(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shldi_epi32&expand=5043) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_shldi_epi32( @@ -1483,7 +1483,7 @@ pub fn _mm_mask_shldi_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shldi_epi32&expand=5044) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_shldi_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { @@ -1499,7 +1499,7 @@ pub fn _mm_maskz_shldi_epi32(k: __mmask8, a: __m128i, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shldi_epi16&expand=5042) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm512_shldi_epi16(a: __m512i, b: __m512i) -> __m512i { @@ -1512,7 +1512,7 @@ pub fn _mm512_shldi_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shldi_epi16&expand=5040) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shldi_epi16( @@ -1533,7 +1533,7 @@ pub fn _mm512_mask_shldi_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shldi_epi16&expand=5041) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shldi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { @@ -1549,7 +1549,7 @@ pub fn _mm512_maskz_shldi_epi16(k: __mmask32, a: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shldi_epi16&expand=5039) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm256_shldi_epi16(a: __m256i, b: __m256i) -> __m256i { @@ -1562,7 +1562,7 @@ pub fn _mm256_shldi_epi16(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shldi_epi16&expand=5037) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shldi_epi16( @@ -1583,7 +1583,7 @@ pub fn _mm256_mask_shldi_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shldi_epi16&expand=5038) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shldi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { @@ -1599,7 +1599,7 @@ pub fn _mm256_maskz_shldi_epi16(k: __mmask16, a: __m256i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shldi_epi16&expand=5036) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(2)] pub fn _mm_shldi_epi16(a: __m128i, b: __m128i) -> __m128i { @@ -1612,7 +1612,7 @@ pub fn _mm_shldi_epi16(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shldi_epi16&expand=5034) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_shldi_epi16( @@ -1633,7 +1633,7 @@ pub fn _mm_mask_shldi_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shldi_epi16&expand=5035) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_shldi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { @@ -1649,7 +1649,7 @@ pub fn _mm_maskz_shldi_epi16(k: __mmask8, a: __m128i, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shrdi_epi64&expand=5114) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq #[rustc_legacy_const_generics(2)] pub fn _mm512_shrdi_epi64(a: __m512i, b: __m512i) -> __m512i { @@ -1662,7 +1662,7 @@ pub fn _mm512_shrdi_epi64(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shrdi_epi64&expand=5112) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shrdi_epi64( @@ -1683,7 +1683,7 @@ pub fn _mm512_mask_shrdi_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shrdi_epi64&expand=5113) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 255))] //should be vpshrdq #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shrdi_epi64(k: __mmask8, a: __m512i, b: __m512i) -> __m512i { @@ -1699,7 +1699,7 @@ pub fn _mm512_maskz_shrdi_epi64(k: __mmask8, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shrdi_epi64&expand=5111) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq #[rustc_legacy_const_generics(2)] pub fn _mm256_shrdi_epi64(a: __m256i, b: __m256i) -> __m256i { @@ -1712,7 +1712,7 @@ pub fn _mm256_shrdi_epi64(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shrdi_epi64&expand=5109) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shrdi_epi64( @@ -1733,7 +1733,7 @@ pub fn _mm256_mask_shrdi_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shrdi_epi64&expand=5110) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shrdi_epi64(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { @@ -1749,7 +1749,7 @@ pub fn _mm256_maskz_shrdi_epi64(k: __mmask8, a: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shrdi_epi64&expand=5108) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq #[rustc_legacy_const_generics(2)] pub fn _mm_shrdi_epi64(a: __m128i, b: __m128i) -> __m128i { @@ -1762,7 +1762,7 @@ pub fn _mm_shrdi_epi64(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shrdi_epi64&expand=5106) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq #[rustc_legacy_const_generics(4)] pub fn _mm_mask_shrdi_epi64( @@ -1783,7 +1783,7 @@ pub fn _mm_mask_shrdi_epi64( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shrdi_epi64&expand=5107) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldq, IMM8 = 5))] //should be vpshrdq #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_shrdi_epi64(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { @@ -1799,7 +1799,7 @@ pub fn _mm_maskz_shrdi_epi64(k: __mmask8, a: __m128i, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shrdi_epi32&expand=5105) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(2)] pub fn _mm512_shrdi_epi32(a: __m512i, b: __m512i) -> __m512i { @@ -1812,7 +1812,7 @@ pub fn _mm512_shrdi_epi32(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shrdi_epi32&expand=5103) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shrdi_epi32( @@ -1833,7 +1833,7 @@ pub fn _mm512_mask_shrdi_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shrdi_epi32&expand=5104) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shrdi_epi32(k: __mmask16, a: __m512i, b: __m512i) -> __m512i { @@ -1849,7 +1849,7 @@ pub fn _mm512_maskz_shrdi_epi32(k: __mmask16, a: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shrdi_epi32&expand=5102) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(2)] pub fn _mm256_shrdi_epi32(a: __m256i, b: __m256i) -> __m256i { @@ -1862,7 +1862,7 @@ pub fn _mm256_shrdi_epi32(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shrdi_epi32&expand=5100) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shrdi_epi32( @@ -1883,7 +1883,7 @@ pub fn _mm256_mask_shrdi_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shrdi_epi32&expand=5101) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shrdi_epi32(k: __mmask8, a: __m256i, b: __m256i) -> __m256i { @@ -1899,7 +1899,7 @@ pub fn _mm256_maskz_shrdi_epi32(k: __mmask8, a: __m256i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shrdi_epi32&expand=5099) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(2)] pub fn _mm_shrdi_epi32(a: __m128i, b: __m128i) -> __m128i { @@ -1912,7 +1912,7 @@ pub fn _mm_shrdi_epi32(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shrdi_epi32&expand=5097) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(4)] pub fn _mm_mask_shrdi_epi32( @@ -1933,7 +1933,7 @@ pub fn _mm_mask_shrdi_epi32( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shrdi_epi32&expand=5098) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldd, IMM8 = 5))] //should be vpshldd #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_shrdi_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { @@ -1949,7 +1949,7 @@ pub fn _mm_maskz_shrdi_epi32(k: __mmask8, a: __m128i, b: __m128 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shrdi_epi16&expand=5096) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(2)] pub fn _mm512_shrdi_epi16(a: __m512i, b: __m512i) -> __m512i { @@ -1962,7 +1962,7 @@ pub fn _mm512_shrdi_epi16(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shrdi_epi16&expand=5094) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_shrdi_epi16( @@ -1983,7 +1983,7 @@ pub fn _mm512_mask_shrdi_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shrdi_epi16&expand=5095) #[inline] #[target_feature(enable = "avx512vbmi2")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_shrdi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i { @@ -1999,7 +1999,7 @@ pub fn _mm512_maskz_shrdi_epi16(k: __mmask32, a: __m512i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_shrdi_epi16&expand=5093) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(2)] pub fn _mm256_shrdi_epi16(a: __m256i, b: __m256i) -> __m256i { @@ -2012,7 +2012,7 @@ pub fn _mm256_shrdi_epi16(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shrdi_epi16&expand=5091) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_shrdi_epi16( @@ -2033,7 +2033,7 @@ pub fn _mm256_mask_shrdi_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shrdi_epi16&expand=5092) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_shrdi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { @@ -2049,7 +2049,7 @@ pub fn _mm256_maskz_shrdi_epi16(k: __mmask16, a: __m256i, b: __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shrdi_epi16&expand=5090) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(2)] pub fn _mm_shrdi_epi16(a: __m128i, b: __m128i) -> __m128i { @@ -2062,7 +2062,7 @@ pub fn _mm_shrdi_epi16(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shrdi_epi16&expand=5088) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(4)] pub fn _mm_mask_shrdi_epi16( @@ -2083,7 +2083,7 @@ pub fn _mm_mask_shrdi_epi16( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shrdi_epi16&expand=5089) #[inline] #[target_feature(enable = "avx512vbmi2,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpshldw, IMM8 = 5))] //should be vpshrdw #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_shrdi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i { diff --git a/crates/core_arch/src/x86/avx512vnni.rs b/crates/core_arch/src/x86/avx512vnni.rs index e087d23171..93ea01cbb4 100644 --- a/crates/core_arch/src/x86/avx512vnni.rs +++ b/crates/core_arch/src/x86/avx512vnni.rs @@ -9,7 +9,7 @@ use stdarch_test::assert_instr; /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_dpwssd_epi32&expand=2219) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm512_dpwssd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpdpwssd(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } @@ -20,7 +20,7 @@ pub fn _mm512_dpwssd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_dpwssd_epi32&expand=2220) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm512_mask_dpwssd_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -34,7 +34,7 @@ pub fn _mm512_mask_dpwssd_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_dpwssd_epi32&expand=2221) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm512_maskz_dpwssd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -48,7 +48,7 @@ pub fn _mm512_maskz_dpwssd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwssd_avx_epi32&expand=2713) #[inline] #[target_feature(enable = "avxvnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } @@ -59,7 +59,7 @@ pub fn _mm256_dpwssd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwssd_epi32&expand=2216) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm256_dpwssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwssd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } @@ -70,7 +70,7 @@ pub fn _mm256_dpwssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_dpwssd_epi32&expand=2217) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm256_mask_dpwssd_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -84,7 +84,7 @@ pub fn _mm256_mask_dpwssd_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_dpwssd_epi32&expand=2218) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm256_maskz_dpwssd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -98,7 +98,7 @@ pub fn _mm256_maskz_dpwssd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwssd_avx_epi32&expand=2712) #[inline] #[target_feature(enable = "avxvnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } @@ -109,7 +109,7 @@ pub fn _mm_dpwssd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwssd_epi32&expand=2213) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm_dpwssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwssd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } @@ -120,7 +120,7 @@ pub fn _mm_dpwssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_dpwssd_epi32&expand=2214) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm_mask_dpwssd_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -134,7 +134,7 @@ pub fn _mm_mask_dpwssd_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_dpwssd_epi32&expand=2215) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssd))] pub fn _mm_maskz_dpwssd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -148,7 +148,7 @@ pub fn _mm_maskz_dpwssd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_dpwssds_epi32&expand=2228) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm512_dpwssds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpdpwssds(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } @@ -159,7 +159,7 @@ pub fn _mm512_dpwssds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_dpwssds_epi32&expand=2229) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm512_mask_dpwssds_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -173,7 +173,7 @@ pub fn _mm512_mask_dpwssds_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_dpwssds_epi32&expand=2230) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm512_maskz_dpwssds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -187,7 +187,7 @@ pub fn _mm512_maskz_dpwssds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwssds_avx_epi32&expand=2726) #[inline] #[target_feature(enable = "avxvnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } @@ -198,7 +198,7 @@ pub fn _mm256_dpwssds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpwssds_epi32&expand=2225) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm256_dpwssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwssds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } @@ -209,7 +209,7 @@ pub fn _mm256_dpwssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_dpwssds_epi32&expand=2226) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm256_mask_dpwssds_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -223,7 +223,7 @@ pub fn _mm256_mask_dpwssds_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_dpwssds_epi32&expand=2227) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm256_maskz_dpwssds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -237,7 +237,7 @@ pub fn _mm256_maskz_dpwssds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwssds_avx_epi32&expand=2725) #[inline] #[target_feature(enable = "avxvnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } @@ -248,7 +248,7 @@ pub fn _mm_dpwssds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpwssds_epi32&expand=2222) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm_dpwssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwssds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } @@ -259,7 +259,7 @@ pub fn _mm_dpwssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_dpwssds_epi32&expand=2223) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm_mask_dpwssds_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -273,7 +273,7 @@ pub fn _mm_mask_dpwssds_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_dpwssds_epi32&expand=2224) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpwssds))] pub fn _mm_maskz_dpwssds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -287,7 +287,7 @@ pub fn _mm_maskz_dpwssds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_dpbusd_epi32&expand=2201) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm512_dpbusd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpdpbusd(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } @@ -298,7 +298,7 @@ pub fn _mm512_dpbusd_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_dpbusd_epi32&expand=2202) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm512_mask_dpbusd_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -312,7 +312,7 @@ pub fn _mm512_mask_dpbusd_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_dpbusd_epi32&expand=2203) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm512_maskz_dpbusd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -326,7 +326,7 @@ pub fn _mm512_maskz_dpbusd_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbusd_avx_epi32&expand=2683) #[inline] #[target_feature(enable = "avxvnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } @@ -337,7 +337,7 @@ pub fn _mm256_dpbusd_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbusd_epi32&expand=2198) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm256_dpbusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbusd256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } @@ -348,7 +348,7 @@ pub fn _mm256_dpbusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_dpbusd_epi32&expand=2199) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm256_mask_dpbusd_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -362,7 +362,7 @@ pub fn _mm256_mask_dpbusd_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_dpbusd_epi32&expand=2200) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm256_maskz_dpbusd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -376,7 +376,7 @@ pub fn _mm256_maskz_dpbusd_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbusd_avx_epi32&expand=2682) #[inline] #[target_feature(enable = "avxvnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } @@ -387,7 +387,7 @@ pub fn _mm_dpbusd_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbusd_epi32&expand=2195) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm_dpbusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbusd128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } @@ -398,7 +398,7 @@ pub fn _mm_dpbusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_dpbusd_epi32&expand=2196) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm_mask_dpbusd_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -412,7 +412,7 @@ pub fn _mm_mask_dpbusd_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_dpbusd_epi32&expand=2197) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusd))] pub fn _mm_maskz_dpbusd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -426,7 +426,7 @@ pub fn _mm_maskz_dpbusd_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_dpbusds_epi32&expand=2210) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm512_dpbusds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vpdpbusds(src.as_i32x16(), a.as_i32x16(), b.as_i32x16())) } @@ -437,7 +437,7 @@ pub fn _mm512_dpbusds_epi32(src: __m512i, a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_dpbusds_epi32&expand=2211) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm512_mask_dpbusds_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -451,7 +451,7 @@ pub fn _mm512_mask_dpbusds_epi32(src: __m512i, k: __mmask16, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_dpbusds_epi32&expand=2212) #[inline] #[target_feature(enable = "avx512vnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm512_maskz_dpbusds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -465,7 +465,7 @@ pub fn _mm512_maskz_dpbusds_epi32(k: __mmask16, src: __m512i, a: __m512i, b: __m /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbusds_avx_epi32&expand=2696) #[inline] #[target_feature(enable = "avxvnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } @@ -476,7 +476,7 @@ pub fn _mm256_dpbusds_avx_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dpbusds_epi32&expand=2207) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm256_dpbusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbusds256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } @@ -487,7 +487,7 @@ pub fn _mm256_dpbusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_dpbusds_epi32&expand=2208) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm256_mask_dpbusds_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -501,7 +501,7 @@ pub fn _mm256_mask_dpbusds_epi32(src: __m256i, k: __mmask8, a: __m256i, b: __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_dpbusds_epi32&expand=2209) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm256_maskz_dpbusds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -515,7 +515,7 @@ pub fn _mm256_maskz_dpbusds_epi32(k: __mmask8, src: __m256i, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbusds_avx_epi32&expand=2695) #[inline] #[target_feature(enable = "avxvnni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } @@ -526,7 +526,7 @@ pub fn _mm_dpbusds_avx_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dpbusds_epi32&expand=2204) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm_dpbusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbusds128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } @@ -537,7 +537,7 @@ pub fn _mm_dpbusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_dpbusds_epi32&expand=2205) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm_mask_dpbusds_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -551,7 +551,7 @@ pub fn _mm_mask_dpbusds_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_dpbusds_epi32&expand=2206) #[inline] #[target_feature(enable = "avx512vnni,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpdpbusds))] pub fn _mm_maskz_dpbusds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -568,7 +568,7 @@ pub fn _mm_maskz_dpbusds_epi32(k: __mmask8, src: __m128i, a: __m128i, b: __m128i #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbssd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbssd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -581,7 +581,7 @@ pub fn _mm_dpbssd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbssd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbssd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -594,7 +594,7 @@ pub fn _mm256_dpbssd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbssds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbssds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -607,7 +607,7 @@ pub fn _mm_dpbssds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbssds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbssds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -620,7 +620,7 @@ pub fn _mm256_dpbssds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbsud))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -633,7 +633,7 @@ pub fn _mm_dpbsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbsud))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -646,7 +646,7 @@ pub fn _mm256_dpbsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbsuds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -659,7 +659,7 @@ pub fn _mm_dpbsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbsuds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -672,7 +672,7 @@ pub fn _mm256_dpbsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbuud))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -685,7 +685,7 @@ pub fn _mm_dpbuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbuud))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -698,7 +698,7 @@ pub fn _mm256_dpbuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbuuds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpbuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -711,7 +711,7 @@ pub fn _mm_dpbuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint8")] #[cfg_attr(test, assert_instr(vpdpbuuds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpbuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -724,7 +724,7 @@ pub fn _mm256_dpbuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwsud))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwsud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -737,7 +737,7 @@ pub fn _mm_dpwsud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwsud))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwsud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -750,7 +750,7 @@ pub fn _mm256_dpwsud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwsuds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwsuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -763,7 +763,7 @@ pub fn _mm_dpwsuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwsuds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwsuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -776,7 +776,7 @@ pub fn _mm256_dpwsuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwusd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwusd_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -789,7 +789,7 @@ pub fn _mm_dpwusd_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwusd))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwusd_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -802,7 +802,7 @@ pub fn _mm256_dpwusd_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwusds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwusds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -815,7 +815,7 @@ pub fn _mm_dpwusds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwusds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwusds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -828,7 +828,7 @@ pub fn _mm256_dpwusds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwuud))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwuud_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -841,7 +841,7 @@ pub fn _mm_dpwuud_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwuud))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwuud_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } @@ -854,7 +854,7 @@ pub fn _mm256_dpwuud_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwuuds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vpdpwuuds_128(src.as_i32x4(), a.as_i32x4(), b.as_i32x4())) } } @@ -867,7 +867,7 @@ pub fn _mm_dpwuuds_epi32(src: __m128i, a: __m128i, b: __m128i) -> __m128i { #[inline] #[target_feature(enable = "avxvnniint16")] #[cfg_attr(test, assert_instr(vpdpwuuds))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_dpwuuds_epi32(src: __m256i, a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vpdpwuuds_256(src.as_i32x8(), a.as_i32x8(), b.as_i32x8())) } } diff --git a/crates/core_arch/src/x86/avx512vpopcntdq.rs b/crates/core_arch/src/x86/avx512vpopcntdq.rs index 7a06f09b19..e47a14b24d 100644 --- a/crates/core_arch/src/x86/avx512vpopcntdq.rs +++ b/crates/core_arch/src/x86/avx512vpopcntdq.rs @@ -24,7 +24,7 @@ use stdarch_test::assert_instr; /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm512_popcnt_epi32(a: __m512i) -> __m512i { unsafe { transmute(simd_ctpop(a.as_i32x16())) } @@ -38,7 +38,7 @@ pub fn _mm512_popcnt_epi32(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm512_maskz_popcnt_epi32(k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -58,7 +58,7 @@ pub fn _mm512_maskz_popcnt_epi32(k: __mmask16, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm512_mask_popcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m512i { unsafe { @@ -75,7 +75,7 @@ pub fn _mm512_mask_popcnt_epi32(src: __m512i, k: __mmask16, a: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm256_popcnt_epi32(a: __m256i) -> __m256i { unsafe { transmute(simd_ctpop(a.as_i32x8())) } @@ -89,7 +89,7 @@ pub fn _mm256_popcnt_epi32(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm256_maskz_popcnt_epi32(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -109,7 +109,7 @@ pub fn _mm256_maskz_popcnt_epi32(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm256_mask_popcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -126,7 +126,7 @@ pub fn _mm256_mask_popcnt_epi32(src: __m256i, k: __mmask8, a: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm_popcnt_epi32(a: __m128i) -> __m128i { unsafe { transmute(simd_ctpop(a.as_i32x4())) } @@ -140,7 +140,7 @@ pub fn _mm_popcnt_epi32(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm_maskz_popcnt_epi32(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -160,7 +160,7 @@ pub fn _mm_maskz_popcnt_epi32(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_popcnt_epi32) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntd))] pub fn _mm_mask_popcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -177,7 +177,7 @@ pub fn _mm_mask_popcnt_epi32(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm512_popcnt_epi64(a: __m512i) -> __m512i { unsafe { transmute(simd_ctpop(a.as_i64x8())) } @@ -191,7 +191,7 @@ pub fn _mm512_popcnt_epi64(a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm512_maskz_popcnt_epi64(k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -211,7 +211,7 @@ pub fn _mm512_maskz_popcnt_epi64(k: __mmask8, a: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm512_mask_popcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512i { unsafe { @@ -228,7 +228,7 @@ pub fn _mm512_mask_popcnt_epi64(src: __m512i, k: __mmask8, a: __m512i) -> __m512 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm256_popcnt_epi64(a: __m256i) -> __m256i { unsafe { transmute(simd_ctpop(a.as_i64x4())) } @@ -242,7 +242,7 @@ pub fn _mm256_popcnt_epi64(a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm256_maskz_popcnt_epi64(k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -262,7 +262,7 @@ pub fn _mm256_maskz_popcnt_epi64(k: __mmask8, a: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm256_mask_popcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256i { unsafe { @@ -279,7 +279,7 @@ pub fn _mm256_mask_popcnt_epi64(src: __m256i, k: __mmask8, a: __m256i) -> __m256 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm_popcnt_epi64(a: __m128i) -> __m128i { unsafe { transmute(simd_ctpop(a.as_i64x2())) } @@ -293,7 +293,7 @@ pub fn _mm_popcnt_epi64(a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm_maskz_popcnt_epi64(k: __mmask8, a: __m128i) -> __m128i { unsafe { @@ -313,7 +313,7 @@ pub fn _mm_maskz_popcnt_epi64(k: __mmask8, a: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_popcnt_epi64) #[inline] #[target_feature(enable = "avx512vpopcntdq,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpopcntq))] pub fn _mm_mask_popcnt_epi64(src: __m128i, k: __mmask8, a: __m128i) -> __m128i { unsafe { diff --git a/crates/core_arch/src/x86/avxneconvert.rs b/crates/core_arch/src/x86/avxneconvert.rs index 1bc68d5548..b92ec823ec 100644 --- a/crates/core_arch/src/x86/avxneconvert.rs +++ b/crates/core_arch/src/x86/avxneconvert.rs @@ -63,7 +63,7 @@ pub unsafe fn _mm256_bcstnesh_ps(a: *const f16) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneebf162ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_cvtneebf16_ps(a: *const __m128bh) -> __m128 { transmute(cvtneebf162ps_128(a)) } @@ -75,7 +75,7 @@ pub unsafe fn _mm_cvtneebf16_ps(a: *const __m128bh) -> __m128 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneebf162ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_cvtneebf16_ps(a: *const __m256bh) -> __m256 { transmute(cvtneebf162ps_256(a)) } @@ -111,7 +111,7 @@ pub unsafe fn _mm256_cvtneeph_ps(a: *const __m256h) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneobf162ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm_cvtneobf16_ps(a: *const __m128bh) -> __m128 { transmute(cvtneobf162ps_128(a)) } @@ -123,7 +123,7 @@ pub unsafe fn _mm_cvtneobf16_ps(a: *const __m128bh) -> __m128 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneobf162ps))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub unsafe fn _mm256_cvtneobf16_ps(a: *const __m256bh) -> __m256 { transmute(cvtneobf162ps_256(a)) } @@ -159,7 +159,7 @@ pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneps2bf16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh { unsafe { let mut dst: __m128bh; @@ -180,7 +180,7 @@ pub fn _mm_cvtneps_avx_pbh(a: __m128) -> __m128bh { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneps2bf16))] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _mm256_cvtneps_avx_pbh(a: __m256) -> __m128bh { unsafe { let mut dst: __m128bh; diff --git a/crates/core_arch/src/x86/gfni.rs b/crates/core_arch/src/x86/gfni.rs index dbb1191de5..9386684aba 100644 --- a/crates/core_arch/src/x86/gfni.rs +++ b/crates/core_arch/src/x86/gfni.rs @@ -60,7 +60,7 @@ unsafe extern "C" { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] pub fn _mm512_gf2p8mul_epi8(a: __m512i, b: __m512i) -> __m512i { unsafe { transmute(vgf2p8mulb_512(a.as_i8x64(), b.as_i8x64())) } @@ -76,7 +76,7 @@ pub fn _mm512_gf2p8mul_epi8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] pub fn _mm512_mask_gf2p8mul_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i { unsafe { @@ -98,7 +98,7 @@ pub fn _mm512_mask_gf2p8mul_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] pub fn _mm512_maskz_gf2p8mul_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i { let zero = i8x64::ZERO; @@ -118,7 +118,7 @@ pub fn _mm512_maskz_gf2p8mul_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m51 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] pub fn _mm256_gf2p8mul_epi8(a: __m256i, b: __m256i) -> __m256i { unsafe { transmute(vgf2p8mulb_256(a.as_i8x32(), b.as_i8x32())) } @@ -134,7 +134,7 @@ pub fn _mm256_gf2p8mul_epi8(a: __m256i, b: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] pub fn _mm256_mask_gf2p8mul_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i { unsafe { @@ -156,7 +156,7 @@ pub fn _mm256_mask_gf2p8mul_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m2 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] pub fn _mm256_maskz_gf2p8mul_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i { let zero = i8x32::ZERO; @@ -176,7 +176,7 @@ pub fn _mm256_maskz_gf2p8mul_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m25 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(gf2p8mulb))] pub fn _mm_gf2p8mul_epi8(a: __m128i, b: __m128i) -> __m128i { unsafe { transmute(vgf2p8mulb_128(a.as_i8x16(), b.as_i8x16())) } @@ -192,7 +192,7 @@ pub fn _mm_gf2p8mul_epi8(a: __m128i, b: __m128i) -> __m128i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] pub fn _mm_mask_gf2p8mul_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -214,7 +214,7 @@ pub fn _mm_mask_gf2p8mul_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] pub fn _mm_maskz_gf2p8mul_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i { unsafe { @@ -235,7 +235,7 @@ pub fn _mm_maskz_gf2p8mul_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm512_gf2p8affine_epi64_epi8(x: __m512i, a: __m512i) -> __m512i { @@ -260,7 +260,7 @@ pub fn _mm512_gf2p8affine_epi64_epi8(x: __m512i, a: __m512i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_gf2p8affine_epi64_epi8( @@ -290,7 +290,7 @@ pub fn _mm512_maskz_gf2p8affine_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_gf2p8affine_epi64_epi8( @@ -317,7 +317,7 @@ pub fn _mm512_mask_gf2p8affine_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm256_gf2p8affine_epi64_epi8(x: __m256i, a: __m256i) -> __m256i { @@ -342,7 +342,7 @@ pub fn _mm256_gf2p8affine_epi64_epi8(x: __m256i, a: __m256i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_gf2p8affine_epi64_epi8( @@ -372,7 +372,7 @@ pub fn _mm256_maskz_gf2p8affine_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_gf2p8affine_epi64_epi8( @@ -399,7 +399,7 @@ pub fn _mm256_mask_gf2p8affine_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(gf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm_gf2p8affine_epi64_epi8(x: __m128i, a: __m128i) -> __m128i { @@ -424,7 +424,7 @@ pub fn _mm_gf2p8affine_epi64_epi8(x: __m128i, a: __m128i) -> __m12 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_gf2p8affine_epi64_epi8( @@ -454,7 +454,7 @@ pub fn _mm_maskz_gf2p8affine_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_gf2p8affine_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_gf2p8affine_epi64_epi8( @@ -483,7 +483,7 @@ pub fn _mm_mask_gf2p8affine_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm512_gf2p8affineinv_epi64_epi8(x: __m512i, a: __m512i) -> __m512i { @@ -510,7 +510,7 @@ pub fn _mm512_gf2p8affineinv_epi64_epi8(x: __m512i, a: __m512i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm512_maskz_gf2p8affineinv_epi64_epi8( @@ -542,7 +542,7 @@ pub fn _mm512_maskz_gf2p8affineinv_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm512_mask_gf2p8affineinv_epi64_epi8( @@ -571,7 +571,7 @@ pub fn _mm512_mask_gf2p8affineinv_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm256_gf2p8affineinv_epi64_epi8(x: __m256i, a: __m256i) -> __m256i { @@ -598,7 +598,7 @@ pub fn _mm256_gf2p8affineinv_epi64_epi8(x: __m256i, a: __m256i) -> /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm256_maskz_gf2p8affineinv_epi64_epi8( @@ -630,7 +630,7 @@ pub fn _mm256_maskz_gf2p8affineinv_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm256_mask_gf2p8affineinv_epi64_epi8( @@ -659,7 +659,7 @@ pub fn _mm256_mask_gf2p8affineinv_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(gf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm_gf2p8affineinv_epi64_epi8(x: __m128i, a: __m128i) -> __m128i { @@ -686,7 +686,7 @@ pub fn _mm_gf2p8affineinv_epi64_epi8(x: __m128i, a: __m128i) -> __ /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(3)] pub fn _mm_maskz_gf2p8affineinv_epi64_epi8( @@ -718,7 +718,7 @@ pub fn _mm_maskz_gf2p8affineinv_epi64_epi8( /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(4)] pub fn _mm_mask_gf2p8affineinv_epi64_epi8( @@ -881,7 +881,7 @@ mod tests { } #[target_feature(enable = "sse2")] - #[unstable(feature = "stdarch_x86_avx512", issue = "111137")] + #[stable(feature = "stdarch_x86_avx512", since = "1.89")] unsafe fn load_m128i_word(data: &[T], word_index: usize) -> __m128i { let byte_offset = word_index * 16 / size_of::(); let pointer = data.as_ptr().add(byte_offset) as *const __m128i; @@ -889,7 +889,7 @@ mod tests { } #[target_feature(enable = "avx")] - #[unstable(feature = "stdarch_x86_avx512", issue = "111137")] + #[stable(feature = "stdarch_x86_avx512", since = "1.89")] unsafe fn load_m256i_word(data: &[T], word_index: usize) -> __m256i { let byte_offset = word_index * 32 / size_of::(); let pointer = data.as_ptr().add(byte_offset) as *const __m256i; @@ -897,7 +897,7 @@ mod tests { } #[target_feature(enable = "avx512f")] - #[unstable(feature = "stdarch_x86_avx512", issue = "111137")] + #[stable(feature = "stdarch_x86_avx512", since = "1.89")] unsafe fn load_m512i_word(data: &[T], word_index: usize) -> __m512i { let byte_offset = word_index * 64 / size_of::(); let pointer = data.as_ptr().add(byte_offset) as *const _; diff --git a/crates/core_arch/src/x86/mod.rs b/crates/core_arch/src/x86/mod.rs index 721dcd5f0e..8897258c7d 100644 --- a/crates/core_arch/src/x86/mod.rs +++ b/crates/core_arch/src/x86/mod.rs @@ -356,7 +356,7 @@ types! { } types! { - #![unstable(feature = "stdarch_x86_avx512", issue = "111137")] + #![stable(feature = "stdarch_x86_avx512", since = "1.89")] /// 128-bit wide set of eight `u16` types, x86-specific /// @@ -473,42 +473,42 @@ impl bf16 { /// The `__mmask64` type used in AVX-512 intrinsics, a 64-bit integer #[allow(non_camel_case_types)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub type __mmask64 = u64; /// The `__mmask32` type used in AVX-512 intrinsics, a 32-bit integer #[allow(non_camel_case_types)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub type __mmask32 = u32; /// The `__mmask16` type used in AVX-512 intrinsics, a 16-bit integer #[allow(non_camel_case_types)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub type __mmask16 = u16; /// The `__mmask8` type used in AVX-512 intrinsics, a 8-bit integer #[allow(non_camel_case_types)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub type __mmask8 = u8; /// The `_MM_CMPINT_ENUM` type used to specify comparison operations in AVX-512 intrinsics. #[allow(non_camel_case_types)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub type _MM_CMPINT_ENUM = i32; /// The `MM_MANTISSA_NORM_ENUM` type used to specify mantissa normalized operations in AVX-512 intrinsics. #[allow(non_camel_case_types)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub type _MM_MANTISSA_NORM_ENUM = i32; /// The `MM_MANTISSA_SIGN_ENUM` type used to specify mantissa signed operations in AVX-512 intrinsics. #[allow(non_camel_case_types)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub type _MM_MANTISSA_SIGN_ENUM = i32; /// The `MM_PERM_ENUM` type used to specify shuffle operations in AVX-512 intrinsics. #[allow(non_camel_case_types)] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub type _MM_PERM_ENUM = i32; #[cfg(test)] @@ -696,55 +696,55 @@ pub use self::adx::*; use stdarch_test::assert_instr; mod avx512f; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512f::*; mod avx512bw; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512bw::*; mod avx512cd; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512cd::*; mod avx512dq; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512dq::*; mod avx512ifma; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512ifma::*; mod avx512vbmi; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512vbmi::*; mod avx512vbmi2; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512vbmi2::*; mod avx512vnni; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512vnni::*; mod avx512bitalg; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512bitalg::*; mod gfni; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::gfni::*; mod avx512vpopcntdq; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512vpopcntdq::*; mod vaes; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::vaes::*; mod vpclmulqdq; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::vpclmulqdq::*; mod bt; @@ -760,11 +760,11 @@ mod f16c; pub use self::f16c::*; mod avx512bf16; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512bf16::*; mod avxneconvert; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avxneconvert::*; mod avx512fp16; diff --git a/crates/core_arch/src/x86/vaes.rs b/crates/core_arch/src/x86/vaes.rs index 99ee0f2f58..b1fe193e3f 100644 --- a/crates/core_arch/src/x86/vaes.rs +++ b/crates/core_arch/src/x86/vaes.rs @@ -39,7 +39,7 @@ unsafe extern "C" { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_aesenc_epi128) #[inline] #[target_feature(enable = "vaes")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaesenc))] pub fn _mm256_aesenc_epi128(a: __m256i, round_key: __m256i) -> __m256i { unsafe { aesenc_256(a, round_key) } @@ -51,7 +51,7 @@ pub fn _mm256_aesenc_epi128(a: __m256i, round_key: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_aesenclast_epi128) #[inline] #[target_feature(enable = "vaes")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaesenclast))] pub fn _mm256_aesenclast_epi128(a: __m256i, round_key: __m256i) -> __m256i { unsafe { aesenclast_256(a, round_key) } @@ -63,7 +63,7 @@ pub fn _mm256_aesenclast_epi128(a: __m256i, round_key: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_aesdec_epi128) #[inline] #[target_feature(enable = "vaes")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaesdec))] pub fn _mm256_aesdec_epi128(a: __m256i, round_key: __m256i) -> __m256i { unsafe { aesdec_256(a, round_key) } @@ -75,7 +75,7 @@ pub fn _mm256_aesdec_epi128(a: __m256i, round_key: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_aesdeclast_epi128) #[inline] #[target_feature(enable = "vaes")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaesdeclast))] pub fn _mm256_aesdeclast_epi128(a: __m256i, round_key: __m256i) -> __m256i { unsafe { aesdeclast_256(a, round_key) } @@ -87,7 +87,7 @@ pub fn _mm256_aesdeclast_epi128(a: __m256i, round_key: __m256i) -> __m256i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_aesenc_epi128) #[inline] #[target_feature(enable = "vaes,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaesenc))] pub fn _mm512_aesenc_epi128(a: __m512i, round_key: __m512i) -> __m512i { unsafe { aesenc_512(a, round_key) } @@ -99,7 +99,7 @@ pub fn _mm512_aesenc_epi128(a: __m512i, round_key: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_aesenclast_epi128) #[inline] #[target_feature(enable = "vaes,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaesenclast))] pub fn _mm512_aesenclast_epi128(a: __m512i, round_key: __m512i) -> __m512i { unsafe { aesenclast_512(a, round_key) } @@ -111,7 +111,7 @@ pub fn _mm512_aesenclast_epi128(a: __m512i, round_key: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_aesdec_epi128) #[inline] #[target_feature(enable = "vaes,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaesdec))] pub fn _mm512_aesdec_epi128(a: __m512i, round_key: __m512i) -> __m512i { unsafe { aesdec_512(a, round_key) } @@ -123,7 +123,7 @@ pub fn _mm512_aesdec_epi128(a: __m512i, round_key: __m512i) -> __m512i { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_aesdeclast_epi128) #[inline] #[target_feature(enable = "vaes,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vaesdeclast))] pub fn _mm512_aesdeclast_epi128(a: __m512i, round_key: __m512i) -> __m512i { unsafe { aesdeclast_512(a, round_key) } diff --git a/crates/core_arch/src/x86/vpclmulqdq.rs b/crates/core_arch/src/x86/vpclmulqdq.rs index 16af2a9b9f..b1f23bd2f4 100644 --- a/crates/core_arch/src/x86/vpclmulqdq.rs +++ b/crates/core_arch/src/x86/vpclmulqdq.rs @@ -33,7 +33,7 @@ unsafe extern "C" { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_clmulepi64_epi128) #[inline] #[target_feature(enable = "vpclmulqdq,avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] // technically according to Intel's documentation we don't need avx512f here, however LLVM gets confused otherwise #[cfg_attr(test, assert_instr(vpclmul, IMM8 = 0))] #[rustc_legacy_const_generics(2)] @@ -52,7 +52,7 @@ pub fn _mm512_clmulepi64_epi128(a: __m512i, b: __m512i) -> __m5 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_clmulepi64_epi128) #[inline] #[target_feature(enable = "vpclmulqdq")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpclmul, IMM8 = 0))] #[rustc_legacy_const_generics(2)] pub fn _mm256_clmulepi64_epi128(a: __m256i, b: __m256i) -> __m256i { diff --git a/crates/core_arch/src/x86_64/avx512bw.rs b/crates/core_arch/src/x86_64/avx512bw.rs index 43999b2a50..466c36ef31 100644 --- a/crates/core_arch/src/x86_64/avx512bw.rs +++ b/crates/core_arch/src/x86_64/avx512bw.rs @@ -5,7 +5,7 @@ use crate::core_arch::x86::*; /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtmask64_u64) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _cvtmask64_u64(a: __mmask64) -> u64 { a } @@ -15,7 +15,7 @@ pub fn _cvtmask64_u64(a: __mmask64) -> u64 { /// [Intel's Documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_cvtu64_mask64) #[inline] #[target_feature(enable = "avx512bw")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub fn _cvtu64_mask64(a: u64) -> __mmask64 { a } diff --git a/crates/core_arch/src/x86_64/avx512f.rs b/crates/core_arch/src/x86_64/avx512f.rs index c6f84fd965..934c9e2812 100644 --- a/crates/core_arch/src/x86_64/avx512f.rs +++ b/crates/core_arch/src/x86_64/avx512f.rs @@ -11,7 +11,7 @@ use stdarch_test::assert_instr; /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_i64&expand=1792) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2si))] pub fn _mm_cvtsd_i64(a: __m128d) -> i64 { _mm_cvtsd_si64(a) @@ -22,7 +22,7 @@ pub fn _mm_cvtsd_i64(a: __m128d) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_i64&expand=1894) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2si))] pub fn _mm_cvtss_i64(a: __m128) -> i64 { _mm_cvtss_si64(a) @@ -33,7 +33,7 @@ pub fn _mm_cvtss_i64(a: __m128) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_u64&expand=1902) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2usi))] pub fn _mm_cvtss_u64(a: __m128) -> u64 { unsafe { vcvtss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) } @@ -44,7 +44,7 @@ pub fn _mm_cvtss_u64(a: __m128) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_u64&expand=1800) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2usi))] pub fn _mm_cvtsd_u64(a: __m128d) -> u64 { unsafe { vcvtsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) } @@ -55,7 +55,7 @@ pub fn _mm_cvtsd_u64(a: __m128d) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm_cvti64_ss&expand=1643) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2ss))] pub fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 { unsafe { @@ -69,7 +69,7 @@ pub fn _mm_cvti64_ss(a: __m128, b: i64) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvti64_sd&expand=1644) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2sd))] pub fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d { unsafe { @@ -83,7 +83,7 @@ pub fn _mm_cvti64_sd(a: __m128d, b: i64) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_ss&expand=2035) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtusi2ss))] pub fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 { unsafe { @@ -97,7 +97,7 @@ pub fn _mm_cvtu64_ss(a: __m128, b: u64) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtu64_sd&expand=2034) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtusi2sd))] pub fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d { unsafe { @@ -111,7 +111,7 @@ pub fn _mm_cvtu64_sd(a: __m128d, b: u64) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_i64&expand=2016) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2si))] pub fn _mm_cvttsd_i64(a: __m128d) -> i64 { unsafe { vcvttsd2si64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) } @@ -122,7 +122,7 @@ pub fn _mm_cvttsd_i64(a: __m128d) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_u64&expand=2021) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2usi))] pub fn _mm_cvttsd_u64(a: __m128d) -> u64 { unsafe { vcvttsd2usi64(a.as_f64x2(), _MM_FROUND_CUR_DIRECTION) } @@ -133,7 +133,7 @@ pub fn _mm_cvttsd_u64(a: __m128d) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm_cvttss_i64&expand=2023) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2si))] pub fn _mm_cvttss_i64(a: __m128) -> i64 { unsafe { vcvttss2si64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) } @@ -144,7 +144,7 @@ pub fn _mm_cvttss_i64(a: __m128) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_u64&expand=2027) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2usi))] pub fn _mm_cvttss_u64(a: __m128) -> u64 { unsafe { vcvttss2usi64(a.as_f32x4(), _MM_FROUND_CUR_DIRECTION) } @@ -161,7 +161,7 @@ pub fn _mm_cvttss_u64(a: __m128) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_sd&expand=1313) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundi64_sd(a: __m128d, b: i64) -> __m128d { @@ -184,7 +184,7 @@ pub fn _mm_cvt_roundi64_sd(a: __m128d, b: i64) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_sd&expand=1367) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2sd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundsi64_sd(a: __m128d, b: i64) -> __m128d { @@ -207,7 +207,7 @@ pub fn _mm_cvt_roundsi64_sd(a: __m128d, b: i64) -> __m128d /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundi64_ss&expand=1314) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundi64_ss(a: __m128, b: i64) -> __m128 { @@ -230,7 +230,7 @@ pub fn _mm_cvt_roundi64_ss(a: __m128, b: i64) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_sd&expand=1379) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtusi2sd, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundu64_sd(a: __m128d, b: u64) -> __m128d { @@ -253,7 +253,7 @@ pub fn _mm_cvt_roundu64_sd(a: __m128d, b: u64) -> __m128d { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsi64_ss&expand=1368) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsi2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundsi64_ss(a: __m128, b: i64) -> __m128 { @@ -276,7 +276,7 @@ pub fn _mm_cvt_roundsi64_ss(a: __m128, b: i64) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundu64_ss&expand=1380) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtusi2ss, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] pub fn _mm_cvt_roundu64_ss(a: __m128, b: u64) -> __m128 { @@ -299,7 +299,7 @@ pub fn _mm_cvt_roundu64_ss(a: __m128, b: u64) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_si64&expand=1360) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundsd_si64(a: __m128d) -> i64 { @@ -321,7 +321,7 @@ pub fn _mm_cvt_roundsd_si64(a: __m128d) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_i64&expand=1358) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundsd_i64(a: __m128d) -> i64 { @@ -343,7 +343,7 @@ pub fn _mm_cvt_roundsd_i64(a: __m128d) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundsd_u64&expand=1365) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtsd2usi, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundsd_u64(a: __m128d) -> u64 { @@ -365,7 +365,7 @@ pub fn _mm_cvt_roundsd_u64(a: __m128d) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_si64&expand=1375) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundss_si64(a: __m128) -> i64 { @@ -387,7 +387,7 @@ pub fn _mm_cvt_roundss_si64(a: __m128) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_i64&expand=1370) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundss_i64(a: __m128) -> i64 { @@ -409,7 +409,7 @@ pub fn _mm_cvt_roundss_i64(a: __m128) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvt_roundss_u64&expand=1377) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvtss2usi, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvt_roundss_u64(a: __m128) -> u64 { @@ -426,7 +426,7 @@ pub fn _mm_cvt_roundss_u64(a: __m128) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_si64&expand=1931) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundsd_si64(a: __m128d) -> i64 { @@ -443,7 +443,7 @@ pub fn _mm_cvtt_roundsd_si64(a: __m128d) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_i64&expand=1929) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2si, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundsd_i64(a: __m128d) -> i64 { @@ -460,7 +460,7 @@ pub fn _mm_cvtt_roundsd_i64(a: __m128d) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundsd_u64&expand=1933) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttsd2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundsd_u64(a: __m128d) -> u64 { @@ -477,7 +477,7 @@ pub fn _mm_cvtt_roundsd_u64(a: __m128d) -> u64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_i64&expand=1935) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundss_i64(a: __m128) -> i64 { @@ -494,7 +494,7 @@ pub fn _mm_cvtt_roundss_i64(a: __m128) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_si64&expand=1937) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2si, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundss_si64(a: __m128) -> i64 { @@ -511,7 +511,7 @@ pub fn _mm_cvtt_roundss_si64(a: __m128) -> i64 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtt_roundss_u64&expand=1939) #[inline] #[target_feature(enable = "avx512f")] -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vcvttss2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] pub fn _mm_cvtt_roundss_u64(a: __m128) -> u64 { diff --git a/crates/core_arch/src/x86_64/mod.rs b/crates/core_arch/src/x86_64/mod.rs index 32ebf87d9c..7d681882be 100644 --- a/crates/core_arch/src/x86_64/mod.rs +++ b/crates/core_arch/src/x86_64/mod.rs @@ -47,11 +47,11 @@ mod tbm; pub use self::tbm::*; mod avx512f; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512f::*; mod avx512bw; -#[unstable(feature = "stdarch_x86_avx512", issue = "111137")] +#[stable(feature = "stdarch_x86_avx512", since = "1.89")] pub use self::avx512bw::*; mod bswap; diff --git a/examples/connect5.rs b/examples/connect5.rs index 8b8ee106c7..2b451f45d7 100644 --- a/examples/connect5.rs +++ b/examples/connect5.rs @@ -29,8 +29,8 @@ //! each move. #![allow(internal_features)] -#![cfg_attr(target_arch = "x86", feature(stdarch_x86_avx512, stdarch_internal))] -#![cfg_attr(target_arch = "x86_64", feature(stdarch_x86_avx512, stdarch_internal))] +#![cfg_attr(target_arch = "x86", feature(stdarch_internal))] +#![cfg_attr(target_arch = "x86_64", feature(stdarch_internal))] #![feature(stmt_expr_attributes)] use rand::seq::SliceRandom;