Auto merge of #148507 - Zalathar:rollup-vvz4knr, r=Zalathar

Rollup of 6 pull requests

Successful merges:

 - rust-lang/rust#147355 (Add alignment parameter to `simd_masked_{load,store}`)
 - rust-lang/rust#147925 (Fix tests for big-endian)
 - rust-lang/rust#148341 (compiler: Fix a couple issues around cargo feature unification)
 - rust-lang/rust#148371 (Dogfood `trim_{suffix|prefix}` in compiler)
 - rust-lang/rust#148495 (Implement Path::is_empty)
 - rust-lang/rust#148502 (rustc-dev-guide subtree update)

r? `@ghost`
`@rustbot` modify labels: rollup

Author: bors

src/intrinsics/simd.rs

@@ -2,6 +2,7 @@
 
 use cranelift_codegen::ir::immediates::Offset32;
 use rustc_abi::Endian;
+use rustc_middle::ty::SimdAlign;
 
 use super::*;
 use crate::prelude::*;
@@ -960,6 +961,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
             let lane_clif_ty = fx.clif_type(val_lane_ty).unwrap();
             let ptr_val = ptr.load_scalar(fx);
 
+            let alignment = generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+                .unwrap_leaf()
+                .to_simd_alignment();
+
+            let memflags = match alignment {
+                SimdAlign::Unaligned => MemFlags::new().with_notrap(),
+                _ => MemFlags::trusted(),
+            };
+
             for lane_idx in 0..val_lane_count {
                 let val_lane = val.value_lane(fx, lane_idx).load_scalar(fx);
                 let mask_lane = mask.value_lane(fx, lane_idx).load_scalar(fx);
@@ -972,7 +982,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
 
                 fx.bcx.switch_to_block(if_enabled);
                 let offset = lane_idx as i32 * lane_clif_ty.bytes() as i32;
-                fx.bcx.ins().store(MemFlags::trusted(), val_lane, ptr_val, Offset32::new(offset));
+                fx.bcx.ins().store(memflags, val_lane, ptr_val, Offset32::new(offset));
                 fx.bcx.ins().jump(next, &[]);
 
                 fx.bcx.seal_block(next);
@@ -996,6 +1006,15 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
             let lane_clif_ty = fx.clif_type(val_lane_ty).unwrap();
             let ret_lane_layout = fx.layout_of(ret_lane_ty);
 
+            let alignment = generic_args[3].expect_const().to_value().valtree.unwrap_branch()[0]
+                .unwrap_leaf()
+                .to_simd_alignment();
+
+            let memflags = match alignment {
+                SimdAlign::Unaligned => MemFlags::new().with_notrap(),
+                _ => MemFlags::trusted(),
+            };
+
             for lane_idx in 0..ptr_lane_count {
                 let val_lane = val.value_lane(fx, lane_idx).load_scalar(fx);
                 let ptr_lane = ptr.value_lane(fx, lane_idx).load_scalar(fx);
@@ -1011,7 +1030,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
                 fx.bcx.seal_block(if_disabled);
 
                 fx.bcx.switch_to_block(if_enabled);
-                let res = fx.bcx.ins().load(lane_clif_ty, MemFlags::trusted(), ptr_lane, 0);
+                let res = fx.bcx.ins().load(lane_clif_ty, memflags, ptr_lane, 0);
                 fx.bcx.ins().jump(next, &[res.into()]);
 
                 fx.bcx.switch_to_block(if_disabled);