diff --git a/src/shims/intrinsics.rs b/src/shims/intrinsics.rs
index 06af6db76a..875a344363 100644
--- a/src/shims/intrinsics.rs
+++ b/src/shims/intrinsics.rs
@@ -88,7 +88,10 @@ pub trait EvalContextExt<'mir, 'tcx: 'mir>: crate::MiriEvalContextExt<'mir, 'tcx
                 this.write_scalar(val, place.into())?;
             }
 
-            "atomic_fence_acq" => {
+            "atomic_fence_acq" |
+            "atomic_fence_rel" |
+            "atomic_fence_acqrel" |
+            "atomic_fence" => {
                 // we are inherently singlethreaded and singlecored, this is a nop
             }
 
diff --git a/tests/run-pass/atomic.rs b/tests/run-pass/atomic.rs
index f0b8ec06b9..5872a496db 100644
--- a/tests/run-pass/atomic.rs
+++ b/tests/run-pass/atomic.rs
@@ -1,9 +1,10 @@
-use std::sync::atomic::{AtomicBool, AtomicIsize, AtomicU64, Ordering::*};
+use std::sync::atomic::{fence, AtomicBool, AtomicIsize, AtomicU64, Ordering::*};
 
 fn main() {
     atomic_bool();
     atomic_isize();
     atomic_u64();
+    atomic_fences();
 }
 
 fn atomic_bool() {
@@ -57,6 +58,15 @@ fn atomic_u64() {
 
     ATOMIC.store(1, SeqCst);
     assert_eq!(ATOMIC.compare_exchange(0, 0x100, AcqRel, Acquire), Err(1));
-    assert_eq!(ATOMIC.compare_exchange_weak(1, 0x100, AcqRel, Acquire), Ok(1));
+    assert_eq!(
+        ATOMIC.compare_exchange_weak(1, 0x100, AcqRel, Acquire),
+        Ok(1)
+    );
     assert_eq!(ATOMIC.load(Relaxed), 0x100);
 }
+
+fn atomic_fences() {
+    fence(SeqCst);
+    fence(Release);
+    fence(Acquire);
+}