diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 67e875f..b98115d 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -88,36 +88,6 @@ jobs:
           cargo +nightly-2025-10-29 build --target ${{ matrix.target }} -Zbuild-std=core
           cargo +nightly-2025-10-29 build --target ${{ matrix.target }} -Zbuild-std=core --features "serde, defmt, check-asm"
 
-  build-versatileab:
-    runs-on: ubuntu-24.04
-    needs: setup
-    strategy:
-      matrix:
-        rust: ${{ fromJSON(needs.setup.outputs.matrix).rust }}
-    steps:
-      - name: Checkout
-        uses: actions/checkout@v4
-      - name: Build
-        run: |
-          cd examples/versatileab
-          cargo build --target armv7a-none-eabi
-          cargo build --target armv7r-none-eabi
-          cargo build --target armv7r-none-eabihf
-
-  build-mps3-an536:
-    runs-on: ubuntu-24.04
-    needs: setup
-    strategy:
-      matrix:
-        rust: ${{ fromJSON(needs.setup.outputs.matrix).rust }}
-    steps:
-      - name: Checkout
-        uses: actions/checkout@v4
-      - name: Build
-        run: |
-          cd examples/mps3-an536
-          cargo build --target armv8r-none-eabihf
-
   # Build the host tools
   build-host:
     runs-on: ubuntu-24.04
@@ -141,7 +111,7 @@ jobs:
   # Gather all the above build jobs together for the purposes of getting an overall pass-fail
   build-all:
     runs-on: ubuntu-24.04
-    needs: [build-tier2, build-tier2-nightly, build-tier3-no-atomics, build-host, build-versatileab, build-mps3-an536]
+    needs: [build-tier2, build-tier2-nightly, build-tier3-no-atomics, build-host]
     steps:
       - run: /bin/true
 
@@ -301,6 +271,7 @@ jobs:
           cargo test --manifest-path aarch32-cpu/Cargo.toml
 
   # Run some programs in QEMU 9
+  # These tests build with nightly as pinned by the rust-toolchain.toml file, because they include Tier 3 targets
   qemu-test:
     runs-on: ubuntu-24.04
     needs: [build-all]
diff --git a/aarch32-cpu/CHANGELOG.md b/aarch32-cpu/CHANGELOG.md
index 4eb9c4e..1e4e98f 100644
--- a/aarch32-cpu/CHANGELOG.md
+++ b/aarch32-cpu/CHANGELOG.md
@@ -7,10 +7,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [aarch32-cpu v0.1.0]
+
+### Added
+
+- ARMv4T and ARMv5TE support
+- Thumb mode target support
+
 ### Changed
 
 - Renamed from `cortex-ar` to `aarch32-cpu`
-- Added ARMv4T and ARMv5TE support
+- Restarted numbering from 0.1.0
+- All BAR register types now hold plain `u32`, not `*mut u32` - fixes issues with `serde` derives on some types
 
 ## [cortex-ar v0.3.0]
 
@@ -54,7 +62,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 Initial release
 
-[Unreleased]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-v0.3.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-cpu-v0.1.0...HEAD
+[aarch32-cpu v0.1.0]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-v0.3.0...aarch32-cpu-v0.1.0
 [cortex-ar v0.3.0]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-v0.2.0...cortex-ar-v0.3.0
 [cortex-ar v0.2.0]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-v0.1.0...cortex-ar-v0.2.0
 [cortex-ar v0.1.0]: https://github.com/rust-embedded/aarch32/releases/tag/cortex-ar-v0.1.0
diff --git a/aarch32-cpu/Cargo.toml b/aarch32-cpu/Cargo.toml
index 5d81438..86f4715 100644
--- a/aarch32-cpu/Cargo.toml
+++ b/aarch32-cpu/Cargo.toml
@@ -34,7 +34,7 @@ defmt = { version = "1", optional = true }
 serde = { version = "1", features = ["derive"], default-features = false, optional = true }
 
 [build-dependencies]
-arm-targets = { version = "0.3.0", path = "../arm-targets" }
+arm-targets = { version = "0.4.0", path = "../arm-targets" }
 
 [features]
 # Adds a critical-section implementation that only disables interrupts.
diff --git a/aarch32-rt-macros/CHANGELOG.md b/aarch32-rt-macros/CHANGELOG.md
index 447e8ed..7529cba 100644
--- a/aarch32-rt-macros/CHANGELOG.md
+++ b/aarch32-rt-macros/CHANGELOG.md
@@ -7,7 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
-- Renamed to `aarch32-rt-macros`
+## [aarch32-rt-macros v0.1.0]
+
+- Renamed to `aarch32-rt-macros`, restarted numbering from 0.1.0
 
 ## [cortex-ar-rt-macros v0.1.1]
 
@@ -17,6 +19,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 Initial release
 
-[Unreleased]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-rt-macros-v0.1.1...HEAD
+[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-macros-v0.1.0...HEAD
+[aarch32-rt-macros v0.1.0]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-rt-macros-v0.1.1...aarch32-rt-macros-v0.1.0
 [cortex-ar-rt-macros v0.1.1]: https://github.com/rust-embedded/aarch32/compare/cortex-ar-rt-macros-v0.1.0...cortex-ar-rt-macros-v0.1.1
 [cortex-ar-rt-macros v0.1.0]: https://github.com/rust-embedded/aarch32/releases/tag/cortex-ar-rt-macros-v0.1.0
diff --git a/aarch32-rt/CHANGELOG.md b/aarch32-rt/CHANGELOG.md
index 4e8de52..089d11e 100644
--- a/aarch32-rt/CHANGELOG.md
+++ b/aarch32-rt/CHANGELOG.md
@@ -7,11 +7,19 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [aarch32-rt v0.1.0]
+
+### Added
+
+- ARMv7-A support, by merging with the old `cortex-a-rt` crate
+- ARMv4T and ARMv5TE support
+- Thumb mode target support
+- `fpu-d32` feature (was called `vfp-dp` in the old `cortex-a-rt`)
+
 ### Changed
 
 - Renamed from `cortex-r-rt` to `aarch32-rt`
-- Added ARMv4T and ARMv5TE support
-- Added `fpu-d32` feature
+- Restarted numbering from 0.1.0
 - Fixed SVC handling from T32 mode
 
 ## [cortex-r-rt v0.2.1]
@@ -42,7 +50,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 Initial release
 
-[Unreleased]: https://github.com/rust-embedded/aarch32/compare/cortex-r-rt-v0.2.1...HEAD
+[Unreleased]: https://github.com/rust-embedded/aarch32/compare/aarch32-rt-v0.1.0...HEAD
+[aarch32-rt v0.1.0]: https://github.com/rust-embedded/aarch32/compare/cortex-r-rt-v0.2.1...aarch32-rt-v0.1.0
 [cortex-r-rt v0.2.1]: https://github.com/rust-embedded/aarch32/compare/cortex-r-rt-v0.2.0...cortex-r-rt-v0.2.1
 [cortex-r-rt v0.2.0]: https://github.com/rust-embedded/aarch32/compare/cortex-r-rt-v0.1.0...cortex-r-rt-v0.2.0
 [cortex-r-rt v0.1.0]: https://github.com/rust-embedded/aarch32/releases/tag/cortex-r-rt-v0.1.0
diff --git a/aarch32-rt/Cargo.toml b/aarch32-rt/Cargo.toml
index 82fa738..15cd166 100644
--- a/aarch32-rt/Cargo.toml
+++ b/aarch32-rt/Cargo.toml
@@ -11,7 +11,7 @@ description = "Run-time support for Arm AArch32"
 edition = "2021"
 keywords = [
     "arm",
-    "cortex-r",
+    "aarch32",
     "embedded",
     "no-std",
     "run-time",
@@ -37,7 +37,7 @@ eabi-fpu = []
 fpu-d32 = []
 
 [build-dependencies]
-arm-targets = { version = "0.3.0", path = "../arm-targets" }
+arm-targets = { version = "0.4.0", path = "../arm-targets" }
 
 [package.metadata.docs.rs]
 targets = ["armv7r-none-eabihf", "armv7r-none-eabihf", "armv7a-none-eabi"]
diff --git a/aarch32-rt/src/lib.rs b/aarch32-rt/src/lib.rs
index 2f2a3b8..1c64fe3 100644
--- a/aarch32-rt/src/lib.rs
+++ b/aarch32-rt/src/lib.rs
@@ -17,6 +17,12 @@
 //! ## Features
 //!
 //! - `eabi-fpu`: Enables the FPU, even if you selected a soft-float ABI target.
+//! - `fpu-d32`: Make the interrupt context store routines save the upper
+//!   double-precision registers.
+//!
+//!   If your program is using all 32 double-precision registers (e.g. if you
+//!   have set the `+d32` target feature) then you need to enable this option
+//!   otherwise important FPU state may be lost when an exception occurs.
 //!
 //! ## Information about the Run-Time
 //!
diff --git a/arm-targets/CHANGELOG.md b/arm-targets/CHANGELOG.md
index 4ee3b7b..346f8f3 100644
--- a/arm-targets/CHANGELOG.md
+++ b/arm-targets/CHANGELOG.md
@@ -7,6 +7,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.4.0]
+
+### Added
+
+- Added `Arch::Armv6`
+
+### Changed
+
+- Targets starting with `thumb` are identified as T32 targets
+
 ## [v0.3.0]
 
 ### Added
@@ -32,7 +42,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 Initial release
 
-[Unreleased]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.3.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.4.0...HEAD
+[v0.4.0]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.3.0...arm-targets-v0.4.0
 [v0.3.0]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.2.0...arm-targets-v0.3.0
 [v0.2.0]: https://github.com/rust-embedded/aarch32/compare/arm-targets-v0.1.0...arm-targets-v0.2.0
 [v0.1.0]: https://github.com/rust-embedded/aarch32/releases/tag/arm-targets-v0.1.0
diff --git a/arm-targets/Cargo.toml b/arm-targets/Cargo.toml
index a7fcdfb..8cef727 100644
--- a/arm-targets/Cargo.toml
+++ b/arm-targets/Cargo.toml
@@ -12,6 +12,6 @@ readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
 homepage = "https://github.com/rust-embedded/aarch32"
 rust-version = "1.59"
-version = "0.3.0"
+version = "0.4.0"
 
 [dependencies]
diff --git a/examples/mps3-an536/Cargo.toml b/examples/mps3-an536/Cargo.toml
index 290c617..7d0f2f2 100644
--- a/examples/mps3-an536/Cargo.toml
+++ b/examples/mps3-an536/Cargo.toml
@@ -25,7 +25,7 @@ libm = "0.2.15"
 semihosting = { version = "0.1.18", features = ["stdio"] }
 
 [build-dependencies]
-arm-targets = {version = "0.3.0", path = "../../arm-targets"}
+arm-targets = {version = "0.4.0", path = "../../arm-targets"}
 
 [features]
 eabi-fpu = ["aarch32-rt/eabi-fpu"]
diff --git a/examples/versatileab/Cargo.toml b/examples/versatileab/Cargo.toml
index d1a73ca..c4e6bfe 100644
--- a/examples/versatileab/Cargo.toml
+++ b/examples/versatileab/Cargo.toml
@@ -25,7 +25,7 @@ portable-atomic = { version = "1.11.1", features = ["critical-section"] }
 semihosting = { version = "0.1.18", features = ["stdio"] }
 
 [build-dependencies]
-arm-targets = { version = "0.3.0", path = "../../arm-targets" }
+arm-targets = { version = "0.4.0", path = "../../arm-targets" }
 
 [features]
 eabi-fpu = ["aarch32-rt/eabi-fpu"]