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20 | 20 | #define P2SBC_HIDE BIT(8)
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21 | 21 |
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22 | 22 | #define P2SB_DEVFN_DEFAULT PCI_DEVFN(31, 1)
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| 23 | +#define P2SB_DEVFN_GOLDMONT PCI_DEVFN(13, 0) |
| 24 | +#define SPI_DEVFN_GOLDMONT PCI_DEVFN(13, 2) |
23 | 25 |
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24 | 26 | static const struct x86_cpu_id p2sb_cpu_ids[] = {
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25 |
| - X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)), |
| 27 | + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), |
26 | 28 | {}
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27 | 29 | };
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28 | 30 |
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@@ -98,21 +100,12 @@ static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn)
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98 | 100 |
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99 | 101 | static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn)
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100 | 102 | {
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101 |
| - unsigned int slot, fn; |
102 |
| - |
103 |
| - if (PCI_FUNC(devfn) == 0) { |
104 |
| - /* |
105 |
| - * When function number of the P2SB device is zero, scan it and |
106 |
| - * other function numbers, and if devices are available, cache |
107 |
| - * their BAR0s. |
108 |
| - */ |
109 |
| - slot = PCI_SLOT(devfn); |
110 |
| - for (fn = 0; fn < NR_P2SB_RES_CACHE; fn++) |
111 |
| - p2sb_scan_and_cache_devfn(bus, PCI_DEVFN(slot, fn)); |
112 |
| - } else { |
113 |
| - /* Scan the P2SB device and cache its BAR0 */ |
114 |
| - p2sb_scan_and_cache_devfn(bus, devfn); |
115 |
| - } |
| 103 | + /* Scan the P2SB device and cache its BAR0 */ |
| 104 | + p2sb_scan_and_cache_devfn(bus, devfn); |
| 105 | + |
| 106 | + /* On Goldmont p2sb_bar() also gets called for the SPI controller */ |
| 107 | + if (devfn == P2SB_DEVFN_GOLDMONT) |
| 108 | + p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT); |
116 | 109 |
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117 | 110 | if (!p2sb_valid_resource(&p2sb_resources[PCI_FUNC(devfn)].res))
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118 | 111 | return -ENOENT;
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