_drafts added for WIP stuff

Author: rigred

_drafts/2025-08-04-440lx-agp-issues.md

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+---
+layout: post
+title: "Resolving AGP Initialization Lockups on the Intel 440LX"
+date: 2025-08-04 15:00:00 +0200
+toc: true
+toc_label: "440LX AGP Issues"
+excerpt: "A deep dive into the chipset errata and register-level pitfalls that cause system hangs when enabling AGP in coreboot on the 440LX, and a robust software solution."
+header:
+  teaser: 
+categories:
+  - Firmware
+  - Hardware
+  - Retro Computing
+tags:
+  - coreboot
+  - firmware
+  - retro
+  - i440lx
+  - agp
+  - bugfix
+---
+
+## 440LX, Intel's First Go at AGP
+
+There's a special kind of satisfaction in bringing modern, open-source firmware to a piece of vintage hardware. After getting coreboot running smoothly on the [MSI MS-6117](https://theretroweb.com/motherboards/s/msi-ms-6117-lx6) motherboard, I was feeling pretty good.
+
+The final boss was in sight: enabling the Accelerated Graphics Port (AGP). I flipped the config switch, rebuilt, and... nothing. A hard lockup during the PCI scan.
+
+The most baffling part? It hung even with no AGP card in the slot. This wasn't a fussy graphics card. This was the chipset itself throwing a tantrum.
+
+This is the story of taming the Intel [440LX](https://theretroweb.com/chipsets/282)-Intel's first stab at AGP, and a masterclass in quirky hardware design.
+
+---
+
+## The First Clue: A Chipset with a Split Personality
+
+My first assumption was a simple bug in my code, but the “no card” hang pointed to something deeper. It turns out the 440LX isn't a single northbridge in the way you'd expect. Instead, Intel designed it as two logical devices on the PCI bus:
+
+- **Device 0 (ID 7180h):** Host Bridge - manages DRAM controller and AGP registers.
+- **Device 1 (ID 7181h):** Virtual PCI-to-PCI Bridge - exposes AGP as a secondary PCI bus.
+
+This meant that the AGP engine on Device 0 wouldn’t function correctly unless Device 1 was properly initialized. My code was talking to the AGP registers before their parent bus existed.
+
+---
+
+## Datasheet Archaeology: Unearthing Ancient Bugs
+
+The next stop was Intel’s specification updates. Buried within:
+
+> **VGA Hang Erratum**: If a PCI device tries to access the legacy VGA memory range (0xA0000–0xBFFFF) while the VGA card is on AGP, the chipset locks up *completely*.  
+> There is no hardware fix-only a strict software sequence can avoid it.
+
+That explained the lockup with *no card inserted*. The firmware was forwarding VGA cycles to an empty AGP bus, resulting in deadlock.
+
+---
+
+## The Rules of Engagement
+
+Key takeaways from the errata and datasheets:
+
+- **Order matters**: Write `APSIZE` before `APBASE`. Get it wrong, and `APBASE` is undefined.
+- **Don’t enable the AGP aperture in firmware**: Let the OS driver handle that.
+- **Don’t confuse 440LX with 440BX**: 440LX architecturely is more akin to Intel's 430TX chipset with AGP and a new host bus slapped on.
+
+---
+
+## The Fix: A Two-Part Incantation
+
+### Phase 1: Before PCI Enumeration
+
+Set up the aperture carefully while leaving it disabled. This prevents undefined states and the VGA hang.
+
+```c
+/**
+ * @brief Initialize the AGP aperture early in ramstage.
+ */
+void i440lx_agp_aperture_init(struct device *dev)
+{
+    uint32_t tolm, aperture_base;
+    uint16_t paccfg;
+    const uint32_t aperture_size = 64 * 1024 * 1024; /* 64 MB */
+
+    printk(BIOS_INFO, "440LX: Initializing AGP Aperture...\n");
+
+    /* Set a sane aperture size */
+    pci_write_config8(dev, APSIZE, 0x30); /* 64MB */
+
+    /* Set base address above system RAM */
+    tolm = find_pci_tolm(dev->bus);
+    aperture_base = (tolm + (aperture_size - 1)) & ~(aperture_size - 1);
+    pci_write_config32(dev, APBASE, aperture_base);
+
+    /* Configure PACCFG for VGA hang workaround */
+    paccfg = pci_read_config16(dev, PACCFG);
+    paccfg |= PACCFG_PCI_APER_DIS;
+    paccfg &= ~PACCFG_GBL_APER_EN;
+    paccfg &= ~PACCFG_MDA_PRESENT;
+    pci_write_config16(dev, PACCFG, paccfg);
+}
+````
+
+---
+
+### Phase 2: After PCI Scan
+
+Enable AGP protocol only if a VGA card is actually detected.
+
+```c
+/**
+ * @brief Finalize AGP configuration after PCI enumeration.
+ */
+void i440lx_agp_enable_devices(void)
+{
+    struct device *host_bridge, *agp_bridge, *agp_dev;
+    uint16_t bctrl;
+    uint32_t agpcmd;
+
+    host_bridge = dev_find_slot(0, PCI_DEVFN(0, 0));
+    agp_bridge = dev_find_slot(0, PCI_DEVFN(0, 1));
+    agp_dev = dev_find_slot(1, PCI_DEVFN(0, 0));
+
+    if (!agp_dev || !agp_dev->enabled) {
+        printk(BIOS_INFO, "440LX: No AGP device found. Keeping AGP disabled.\n");
+        bctrl = pci_read_config16(agp_bridge, BCTRL);
+        bctrl &= ~BCTRL_VGA_EN;
+        pci_write_config16(agp_bridge, BCTRL, bctrl);
+        return;
+    }
+
+    /* Enable VGA forwarding if needed */
+    if (pci_read_class(agp_dev) == PCI_CLASS_DISPLAY_VGA) {
+        printk(BIOS_INFO, "440LX: Enabling VGA forwarding for AGP device.\n");
+        bctrl = pci_read_config16(agp_bridge, BCTRL);
+        bctrl |= BCTRL_VGA_EN;
+        pci_write_config16(agp_bridge, BCTRL, bctrl);
+    }
+
+    /* Enable AGP 2x mode */
+    agpcmd = AGPCMD_AGP_EN | AGPCMD_RATE_2X;
+    printk(BIOS_INFO, "440LX: Enabling AGP 2x mode.\n");
+
+    pci_write_config32(host_bridge, AGPCMD, agpcmd);
+    pci_write_config32(agp_dev, agp_dev->cap_ptr + 4, agpcmd);
+}
+```
+---