From 1e8f9237db5f317ecc3714d48ad851dc5f93041f Mon Sep 17 00:00:00 2001 From: Sid Manning Date: Wed, 8 Oct 2025 09:42:35 -0700 Subject: [PATCH] semihosting update to comply with hexagon specification Fixes PicoLibc's test-fread-fwrite test. Returns the newly set offset on success or -1 on error, with r1 set to the associated errno. ARM-SWI returns 0 if the request was successful, negative value otherwise. Change-Id: Ie3e7ea07a5623ee178a98484bbf1cdbdd3363a01 Signed-off-by: Sid Manning --- target/hexagon/hexswi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c index 29a3d29799a40..4ac02574783a8 100644 --- a/target/hexagon/hexswi.c +++ b/target/hexagon/hexswi.c @@ -28,6 +28,7 @@ /* non-arm-compatible semihosting calls */ #define HEXAGON_SPECIFIC_SWI_FLAGS \ + DEF_SWI_FLAG(SEEK, 0x0A) \ DEF_SWI_FLAG(EXCEPTION, 0x18) \ DEF_SWI_FLAG(READ_CYCLES, 0x40) \ DEF_SWI_FLAG(PROF_ON, 0x41) \ @@ -325,6 +326,17 @@ static void sim_handle_trap0(CPUHexagonState *env) semi_cb(cs, 0, 0); break; + case HEX_SYS_SEEK: + { + int fd; + target_ulong off; + hexagon_read_memory(env, swi_info, 4, &fd, retaddr); + hexagon_read_memory(env, swi_info + 4, 4, &off, retaddr); + semihost_sys_lseek(env_cpu(env), common_semi_ftell_cb, fd, off, + GDB_SEEK_SET); + } + break; + case HEX_SYS_STAT: case HEX_SYS_FSTAT: {