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[ET-VK][conv2d] Use * and + instead of fma() on f16 vectors - #24856

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@SS-JIA SS-JIA commented Nov 10, 2026 •

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Stack from ghstack (oldest at bottom):

Ulterior Motive

Optimizing the FP16 1x1 convolutions of the DSR model on mobile GPUs.

Rationale

What: A mul_add(a, b, c) helper in common.glslh computes a * b + c. In shaders that define HAS_FLOAT16_ACCUMULATION, it uses * and + for f16vec4 and fma() for vec4; in other shaders it is fma(). The GEMM tile helper and conv2d_tiled call it instead of fma(), and the conv2d shaders that accumulate in f16 vectors define the marker: conv2d_pw_tiled, conv2d_tiled and the buffer input conv2d_gemm.

Why: Adreno 740 and 750 run fma() on f16 vectors at about half the speed of a multiply and an add. With this commit, Half pointwise convolutions take 0.37 to 0.49 of the time on a Galaxy S23 (Adreno 740) and a Galaxy S24 (Adreno 750). Replacing fma() in every shader regardless of type made Float shaders up to 1.35 times as slow on the same phones, so the form depends on the type.

Details

  • Before: Multiply-accumulates call fma() for both dtypes.
  • After: In the Half variants of conv2d_pw_tiled, conv2d_tiled and the buffer input conv2d_gemm, multiply-accumulates on f16 vectors compute c + a * b. Every other shader still calls fma(), including the other users of the GEMM tile helper (linear, matmul, Q4 and Q8 linear, fused SDPA).

f16vec4 is a type only when GL_EXT_shader_explicit_arithmetic_types_float16 is enabled, so a shader opts in by defining HAS_FLOAT16_ACCUMULATION before it includes common.glslh; without it, mul_add is a macro for fma(). Two alternatives do not work:

  • Enabling the extension in common.glslh for every shader changes implicit conversions in shaders that do not use f16 arithmetic (max_pool2d's mix() call becomes ambiguous).
  • The extension's own macro cannot be the guard: glslang defines GL_EXT_shader_explicit_arithmetic_types_float16 whether or not the extension is enabled.

Other shaders that accumulate in f16 vectors can opt in once their accuracy and performance are measured.

c + a * b rounds the product before the add, which fma() does not. On Adreno 740 and 750, the f16 error statistics of some conv2d correctness configurations change; all still pass. Outputs on Adreno 840, Mali-G715 and Xclipse 940 are bit-identical to the parent's.

Only 16 SPIR-V modules change: the Half conv2d_pw_tiled (4), conv2d_tiled (11) and conv2d_gemm_buffer_half modules.

Differential Revision: D130986954

[ghstack-poisoned]
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pytorch-bot Bot commented Nov 10, 2026 •

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🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/24856

Note: Links to docs will display an error until the docs builds have been completed.

❌ 1 New Failure, 4 Unrelated Failures

As of commit 6ed8fce with merge base 115655c (image):

NEW FAILURE - The following job has failed:

BROKEN TRUNK - The following jobs failed but were present on the merge base:

👉 Rebase onto the `viable/strict` branch to avoid these failures

This comment was automatically generated by Dr. CI and updates every 15 minutes.

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cadence — 6ed8fce6 Deployed Nov 10, 2026 by SS-JIA via hifi-op-test / hifi4 #37656
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