-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy pathindex.html
66 lines (66 loc) · 44.7 KB
/
index.html
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
<!doctype html><html class="not-ready lg:text-base" style=--bg:#fff lang=en-gb><head><meta charset=utf-8><meta http-equiv=X-UA-Compatible content="IE=edge"><meta name=viewport content="width=device-width,initial-scale=1,shrink-to-fit=no"><title>Project F</title>
<meta name=theme-color><meta name=description content="FPGA and RISC-V. Only hardware makes it possible!"><meta name=author content="Project F"><link rel="preload stylesheet" as=style href=https://projectf.io/main.min.css><link rel=preload as=image href=https://projectf.io/theme.png><link rel=preload as=image href=https://projectf.io/rss.svg><link rel=icon href=https://projectf.io/favicon.ico><link rel=apple-touch-icon href=https://projectf.io/apple-touch-icon.png><meta name=generator content="Hugo 0.128.2"><meta itemprop=name content="Project F"><meta itemprop=description content="FPGA and RISC-V. Only hardware makes it possible!"><meta itemprop=datePublished content="2025-02-12T00:00:00+00:00"><meta itemprop=dateModified content="2026-01-04T00:00:00+00:00"><meta property="og:url" content="https://projectf.io/"><meta property="og:site_name" content="Project F"><meta property="og:title" content="Project F"><meta property="og:description" content="FPGA and RISC-V. Only hardware makes it possible!"><meta property="og:locale" content="en_gb"><meta property="og:type" content="website"><meta name=twitter:card content="summary"><meta name=twitter:title content="Project F"><meta name=twitter:description content="FPGA and RISC-V. Only hardware makes it possible!"><link rel=alternate type=application/rss+xml href=https://projectf.io/index.xml title="Project F"><link rel=canonical href=https://projectf.io/></head><body class="text-black duration-200 ease-out dark:text-white"><header class="mx-auto flex h-[4.5rem] max-w-4xl px-8 lg:justify-center"><div class="relative z-50 mr-auto flex items-center"><a class="-translate-x-[1px] -translate-y-[1px] text-2xl font-semibold" href=https://projectf.io/>Project F</a><div class="btn-dark text-[0] ml-4 h-6 w-6 shrink-0 cursor-pointer [background:url(./theme.png)_left_center/_auto_theme('spacing.6')_no-repeat] [transition:_background-position_0.4s_steps(5)] dark:[background-position:right]" role=button aria-label=Dark></div></div><div class="btn-menu relative z-50 -mr-8 flex h-[4.5rem] w-[5rem] shrink-0 cursor-pointer flex-col items-center justify-center gap-2.5 lg:hidden" role=button aria-label=Menu></div><script>const htmlClass=document.documentElement.classList;setTimeout(()=>{htmlClass.remove("not-ready")},10);const btnMenu=document.querySelector(".btn-menu");btnMenu.addEventListener("click",()=>{htmlClass.toggle("open")});const metaTheme=document.querySelector('meta[name="theme-color"]'),lightBg="#fff".replace(/"/g,""),setDark=e=>{metaTheme.setAttribute("content",e?"#000":lightBg),htmlClass[e?"add":"remove"]("dark"),localStorage.setItem("dark",e)},darkScheme=window.matchMedia("(prefers-color-scheme: dark)");if(htmlClass.contains("dark"))setDark(!0);else{const e=localStorage.getItem("dark");setDark(e?e==="true":darkScheme.matches)}darkScheme.addEventListener("change",e=>{setDark(e.matches)});const btnDark=document.querySelector(".btn-dark");btnDark.addEventListener("click",()=>{setDark(localStorage.getItem("dark")!=="true")})</script><div class="nav-wrapper fixed inset-x-0 top-full z-40 flex h-full select-none flex-col justify-center pb-16 duration-200 dark:bg-black lg:static lg:h-auto lg:flex-row lg:!bg-transparent lg:pb-0 lg:transition-none"><nav class="lg:ml-12 lg:flex lg:flex-row lg:items-center lg:space-x-6"><a class="block text-center text-2xl leading-[5rem] lg:text-base lg:font-normal" href=/about/>About</a>
<a class="block text-center text-2xl leading-[5rem] lg:text-base lg:font-normal" href=/demos/>Demos</a>
<a class="block text-center text-2xl leading-[5rem] lg:text-base lg:font-normal" href=/verilog-lib/>Lib</a>
<a class="block text-center text-2xl leading-[5rem] lg:text-base lg:font-normal" href=/tools/>Tools</a>
<a class="block text-center text-2xl leading-[5rem] lg:text-base lg:font-normal" href=/tutorials/>Tutorials</a></nav><nav class="mt-12 flex justify-center space-x-10 dark:invert lg:ml-12 lg:mt-0 lg:items-center lg:space-x-6"><a class="h-8 w-8 text-[0] [background:var(--url)_center_center/cover_no-repeat] lg:h-6 lg:w-6" style=--url:url(./rss.svg) href=https://projectf.io/index.xml target=_blank rel=alternate>rss</a></nav></div></header><main class="prose prose-neutral relative mx-auto min-h-[calc(100%-9rem)] max-w-4xl px-8 pb-4 pt-4 dark:prose-invert"><p class=mb-20><em>Welcome to <strong>Project F</strong>. FPGA and RISC-V. Only hardware makes it possible!</em></p><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">ECP5 FPGA Clock Generation</h2><time class="text-sm antialiased opacity-60">30 Jan 2025</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/ecp5-fpga-clock/>ECP5 FPGA Clock Generation</a><p>Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you’re stuck running at the speed of your dev board oscillator. This post outlines the architecture of ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies. Generating your own clock frequencies is much more straightforward than it first appears. <a href=https://projectf.io/posts/ecp5-fpga-clock/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler: Compiler Explorer</h2><time class="text-sm antialiased opacity-60">15 Oct 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-compiler-explorer/>RISC-V Assembler: Compiler Explorer</a><p>The Godbolt Compiler Explorer is a fantastic tool for assembler programmers. In this post, I show you how to use Compiler Explorer to generate RISC-V assembly code and offer some ideas to make best use of this tool. <a href=https://projectf.io/posts/riscv-compiler-explorer/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler Cheat Sheet</h2><time class="text-sm antialiased opacity-60">14 Jun 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-cheat-sheet/>RISC-V Assembler Cheat Sheet</a><p>This cheat sheet provides a handy guide to 32-bit RISC-V instructions. I’ve aimed it at software developers, so group instructions by purpose and include common pseudoinstructions. <a href=https://projectf.io/posts/riscv-cheat-sheet/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler: Multiply Divide</h2><time class="text-sm antialiased opacity-60">17 May 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-multiply-divide/>RISC-V Assembler: Multiply Divide</a><p>Integer multiply and divide instructions form the optional <strong>M</strong> extension. Making multiplication and division optional keeps the base instruction set simple and reduces the size of the smallest RISC-V core. This post includes a brief overview of common RISC-V extensions. <a href=https://projectf.io/posts/riscv-multiply-divide/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler: Jump and Function</h2><time class="text-sm antialiased opacity-60">30 Apr 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-jump-function/>RISC-V Assembler: Jump and Function</a><p>This RISC-V assembler post begins by examining the RISC-V jump instructions: <strong>jal</strong> and <strong>jalr</strong>. Jump instructions are the basis of functions, so we’ll then dig into function calls, the RISC-V ABI, calling convention, and how to use the stack. <a href=https://projectf.io/posts/riscv-jump-function/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler: Branch Set</h2><time class="text-sm antialiased opacity-60">19 Mar 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-branch-set/>RISC-V Assembler: Branch Set</a><p>This RISC-V assembler post covers branch and set instructions, such as <strong>beq</strong>, <strong>bltu</strong>, <strong>bgez</strong>, and <strong>slt</strong>. We’ll also cover the zero register, program counter, condition codes, and multi-word addition. <a href=https://projectf.io/posts/riscv-branch-set/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler: Load Store</h2><time class="text-sm antialiased opacity-60">15 Feb 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-load-store/>RISC-V Assembler: Load Store</a><p>This RISC-V assembler post covers load and store instructions, such as <strong>lw</strong>, <strong>sw</strong>, and <strong>lbu</strong>. We also cover memory alignment, addressing modes, and loading symbol addresses. <a href=https://projectf.io/posts/riscv-load-store/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler: Shift</h2><time class="text-sm antialiased opacity-60">30 Jan 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-shift/>RISC-V Assembler: Shift</a><p>This RISC-V assembler post covers shift instructions, such as <strong>sll</strong>, <strong>srl</strong>, and <strong>srai</strong>. I also explain how to use shift instructions to quickly multiply and divide by powers of two. <a href=https://projectf.io/posts/riscv-shift/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler: Logical</h2><time class="text-sm antialiased opacity-60">29 Jan 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-logical/>RISC-V Assembler: Logical</a><p>This RISC-V assembler post covers bitwise logical instructions, such as <strong>and</strong>, <strong>not</strong>, and <strong>xori</strong>. Bitwise instructions carry out the specified operator on each bit of the sources in turn. <a href=https://projectf.io/posts/riscv-logical/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">RISC-V Assembler: Arithmetic</h2><time class="text-sm antialiased opacity-60">15 Jan 2024</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/riscv-arithmetic/>RISC-V Assembler: Arithmetic</a><p>This series will help you learn and understand 32-bit RISC-V instructions and programming. The first part looks at load immediate, addition, and subtraction. We’ll also cover sign extension and pseudoinstructions. <a href=https://projectf.io/posts/riscv-arithmetic/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: April 2023</h2><time class="text-sm antialiased opacity-60">29 Apr 2023</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2023-04/>News: April 2023</a><p>Welcome to the latest Project F news covering the first part of 2023. In this edition, we sail the sea of chaos, round out division, automate Vivado with Tcl, and uncover openFPGALoader and cocotb. <a href=https://projectf.io/posts/news-2023-04/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Vivado Tcl Build Script</h2><time class="text-sm antialiased opacity-60">20 Apr 2023</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/vivado-tcl-build-script/>Vivado Tcl Build Script</a><p>Are you tired of firing up the Vivado GUI to build an FPGA project? You can automate your Xilinx FPGA build using a little Tcl. And you don’t even need to know any Tcl. Building your design from a script also comes in handy for continuous integration (CI) and Makefiles. Plus, I’ll show you how to quickly program your dev board with openFPGALoader. <a href=https://projectf.io/posts/vivado-tcl-build-script/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Mandelbrot in Verilog</h2><time class="text-sm antialiased opacity-60">07 Mar 2023</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/mandelbrot-verilog/>Mandelbrot in Verilog</a><p>This FPGA demo uses fixed-point multiplication and a small framebuffer to render the Mandelbrot set. You can navigate around the complex plane using buttons on your dev board. <a href=https://projectf.io/posts/mandelbrot-verilog/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: December 2022</h2><time class="text-sm antialiased opacity-60">04 Jan 2023</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2022-12/>News: December 2022</a><p>Happy New Year and welcome to the latest Project F news covering the end of 2022. This update is packed with maths, graphics and the usual smattering of bits and pieces. <a href=https://projectf.io/posts/news-2022-12/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Verilog Vectors and Arrays</h2><time class="text-sm antialiased opacity-60">13 Dec 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/verilog-vectors-arrays/>Verilog Vectors and Arrays</a><p>Welcome back to my series covering mathematics and algorithms with FPGAs. In this part, we dig into vectors and arrays, including slicing, configurable widths, for loops, and bit and byte ordering. <a href=https://projectf.io/posts/verilog-vectors-arrays/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Rasterbars</h2><time class="text-sm antialiased opacity-60">23 Nov 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/rasterbars/>Rasterbars</a><p>This FPGA demo effect renders four animated rasterbars. I created this effect with benjamin.computer for <em>All You Need</em>, a Chapterhouse prod released at Revision 2022. <a href=https://projectf.io/posts/rasterbars/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Sine Scroller</h2><time class="text-sm antialiased opacity-60">24 Oct 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/sinescroll/>Sine Scroller</a><p>This FPGA demo effect renders a horizontally scrolling message along a sine wave. I created this effect with benjamin.computer for <em>All You Need</em>, a Chapterhouse prod released at Revision 2022. <a href=https://projectf.io/posts/sinescroll/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: September 2022</h2><time class="text-sm antialiased opacity-60">22 Sep 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2022-09/>News: September 2022</a><p>Welcome to Project F news for July, August, and September 2022. There are four blog posts to cover and plans for the remainder of 2022. <a href=https://projectf.io/posts/news-2022-09/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Castle Drawing</h2><time class="text-sm antialiased opacity-60">11 Sep 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/castle-drawing/>Castle Drawing</a><p>In this FPGA demo, we use multiple shapes (rectangles, triangles, circles) to render a simple picture of a castle. We don’t use any software or CPU, just shape rasterization and finite state machines. This Verilog design runs on the Digilent Arty A7 or as a Verilator/SDL simulation on your computer. <a href=https://projectf.io/posts/castle-drawing/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: June 2022</h2><time class="text-sm antialiased opacity-60">24 Jun 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2022-06/>News: June 2022</a><p>Project F news is back! It’s been a while, so this edition covers the first half of 2022. There are six new blog posts to cover as well as plans for the next few months. <a href=https://projectf.io/posts/news-2022-06/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Lib: clock/xd</h2><time class="text-sm antialiased opacity-60">15 Jun 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/lib-clock-xd/>Lib: clock/xd</a><p>Sometimes you need to send a single pulse from one clock domain to another. This is a simple case of <strong>clock domain crossing</strong> or <strong>CDC</strong>. This post uses the <strong>xd</strong> module from the <em>Project F Library</em> to handle such situations simply and safely. <a href=https://projectf.io/posts/lib-clock-xd/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Display Signals</h2><time class="text-sm antialiased opacity-60">07 May 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/display-signals/>Display Signals</a><p>Welcome back to <em>Exploring FPGA Graphics</em>. Last time, we played Pong against our FPGA; this time, we revisit displays signals and learn about palettes and indexed colour. <a href=https://projectf.io/posts/display-signals/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Racing the Beam</h2><time class="text-sm antialiased opacity-60">12 Mar 2022</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/racing-the-beam/>Racing the Beam</a><p>Welcome back to <em>Exploring FPGA Graphics</em>. Last time, we got an introduction to FPGA graphics; let’s put our new graphical skills to work with some simple demo effects. I hope these examples inspire you to create your own effects and improve your hardware design skills. <a href=https://projectf.io/posts/racing-the-beam/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: November 2021</h2><time class="text-sm antialiased opacity-60">03 Dec 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2021-11/>News: November 2021</a><p>Welcome to your November news from Project F. This month’s new blog post covers multiplication with DSPs, plus there are loads of interesting links and an FPGA advent calendar. I’m also happy to report that the main Project F repo <em>projf-explore</em> passed 200 stars on GitHub. <a href=https://projectf.io/posts/news-2021-11/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Multiplication with FPGA DSPs</h2><time class="text-sm antialiased opacity-60">27 Nov 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/multiplication-fpga-dsps/>Multiplication with FPGA DSPs</a><p>Welcome back to my series covering mathematics and algorithms with FPGAs. Project F is known for its practical, hands-on tutorials. So, I decided to dedicate a post to a topic usually ignored by FPGA authors: multiplication with DSPs. <a href=https://projectf.io/posts/multiplication-fpga-dsps/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: October 2021</h2><time class="text-sm antialiased opacity-60">31 Oct 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2021-10/>News: October 2021</a><p>Welcome to October’s update from Project F. This month, we build a rainbow from circles, learn more about numbers in Verilog, find a UART in the library, and hear about exciting FPGA projects from Ben Blundell and Rob Shelton. <a href=https://projectf.io/posts/news-2021-10/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: September 2021</h2><time class="text-sm antialiased opacity-60">09 Oct 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2021-09/>News: September 2021</a><p>Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. This month I began a new series on <em>Maths & Algorithms</em>, added a new rotation demo, and started a new blog on computing history. September also saw the release of Yosys 0.10 and the sad death of Sir Clive Sinclair. <a href=https://projectf.io/posts/news-2021-09/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Numbers in Verilog</h2><time class="text-sm antialiased opacity-60">30 Sep 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/numbers-in-verilog/>Numbers in Verilog</a><p>Welcome to my ongoing series covering mathematics and algorithms with FPGAs. This series begins with the basics of Verilog numbers, then considers fixed-point, division, square roots and CORDIC before covering more complex algorithms, such as data compression. <a href=https://projectf.io/posts/numbers-in-verilog/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: August 2021</h2><time class="text-sm antialiased opacity-60">03 Sep 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2021-08/>News: August 2021</a><p>Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. August saw my first circle drawn, new graphics designs for iCEBreaker, improved build instructions, and the first draft of a new post covering animated graphics and double buffering. <a href=https://projectf.io/posts/news-2021-08/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Animated Shapes</h2><time class="text-sm antialiased opacity-60">31 Aug 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/animated-shapes/>Animated Shapes</a><p>Welcome back to <em>Exploring FPGA Graphics</em>. In the final part of our introductory graphics series, we’re looking at animation. We’ve already seen animation with hardware sprites, but double buffering gives us maximum creative freedom with fast, tear-free motion. <a href=https://projectf.io/posts/animated-shapes/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: July 2021</h2><time class="text-sm antialiased opacity-60">04 Aug 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2021-07/>News: July 2021</a><p>Project F news is your monthly update on the FPGA project, with tasty tips and links from other developers thrown in. This month, iCE40 SPRAM takes centre stage, filled triangles add graphical goodness, we learn that Linux will fit on an iCEBreaker, and discover FPGAs on Mars. <a href=https://projectf.io/posts/news-2021-07/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">SPRAM on iCE40 FPGA</h2><time class="text-sm antialiased opacity-60">30 Jul 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/spram-ice40-fpga/>SPRAM on iCE40 FPGA</a><p>The iCE40 UltraPlus distinguishes itself from the rest of the iCE40 FPGA family by including a relatively generous 1 Mb (128 KiB) of single port synchronous SRAM known as <strong>SPRAM</strong>. SPRAM blocks are much larger than BRAM but are limited to a single port and 16-bit data bus. <a href=https://projectf.io/posts/spram-ice40-fpga/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: June 2021</h2><time class="text-sm antialiased opacity-60">01 Jul 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2021-06/>News: June 2021</a><p>Project F news is your monthly update on the project, with tasty tips and links thrown in. Last month’s issue was well received, so I’m continuing with the experiment. June wasn’t the easiest of months, with a stint of COVID self-isolation, but I’m happy to have written about Verilator and SDL. <a href=https://projectf.io/posts/news-2021-06/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Verilog Simulation with Verilator and SDL</h2><time class="text-sm antialiased opacity-60">11 Jun 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/verilog-sim-verilator-sdl/>Verilog Simulation with Verilator and SDL</a><p>It can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining <strong>Verilator</strong> and <strong>SDL</strong>, you can build Verilog simulations that let you see your design on your computer. <a href=https://projectf.io/posts/verilog-sim-verilator-sdl/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">News: May 2021</h2><time class="text-sm antialiased opacity-60">30 May 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/news-2021-05/>News: May 2021</a><p>As well as the occasional big blog post, I make many smaller FPGA discoveries and Project F updates each month. I thought it would be interesting to share a few of these in a monthly news post. What do you think? <a href=https://projectf.io/posts/news-2021-05/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">FPGA Sine Lookup Table</h2><time class="text-sm antialiased opacity-60">27 May 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/fpga-sine-table/>FPGA Sine Lookup Table</a><p>In this how to, we’re going to look at a straightforward method for generating sine and cosine using a lookup table. There are more precise methods, but this one is fast and simple and will suffice for many applications. <a href=https://projectf.io/posts/fpga-sine-table/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Hello Arty - Part 3</h2><time class="text-sm antialiased opacity-60">17 May 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/hello-arty-3/>Hello Arty - Part 3</a><p>Welcome back to our three-part FPGA tutorial with <strong>SystemVerilog</strong> and the <strong>Digilent Arty A7</strong>. In this third instalment, we build a countdown timer and model traffic lights. There’s a lot to get through this time: enums, case statements, button debouncing, shift registers, and the all-important finite state machine. <a href=https://projectf.io/posts/hello-arty-3/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Verilog Library Announcement</h2><time class="text-sm antialiased opacity-60">27 Apr 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/verilog-library-announcement/>Verilog Library Announcement</a><p>I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA hackers and beginners. <a href=https://projectf.io/posts/verilog-library-announcement/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">2D Shapes</h2><time class="text-sm antialiased opacity-60">17 Mar 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/fpga-shapes/>2D Shapes</a><p>Welcome back to Exploring FPGA Graphics. In 2D Shapes, we build on what we learned from Lines and Triangles in two ways: drawing new shapes and learning to colour them in. We’ll start with rectangles and filled triangles before moving on to circles. These basic shapes make it possible to create a wide variety of graphics and user interfaces. <a href=https://projectf.io/posts/fpga-shapes/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Hello Nexys - Part 2</h2><time class="text-sm antialiased opacity-60">11 Feb 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/hello-nexys-2/>Hello Nexys - Part 2</a><p>Welcome back to our two-part FPGA tutorial with <strong>SystemVerilog</strong> and the <strong>Digilent Nexys Video</strong>. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation. <a href=https://projectf.io/posts/hello-nexys-2/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Lines and Triangles</h2><time class="text-sm antialiased opacity-60">28 Jan 2021</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/lines-and-triangles/>Lines and Triangles</a><p>Welcome back to <em>Exploring FPGA Graphics</em>. It’s time to turn our attention to drawing. Most modern computer graphics come down to drawing triangles and colouring them in. So, it seems fitting to begin our drawing tour with triangles and the straight lines that form them. This post will implement Bresenham’s line algorithm in Verilog and create lines, triangles, and even a cube (our first sort-of 3D). <a href=https://projectf.io/posts/lines-and-triangles/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Verilog Lint with Verilator</h2><time class="text-sm antialiased opacity-60">31 Dec 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/verilog-lint-with-verilator/>Verilog Lint with Verilator</a><p>Hardware design can be unforgiving, so it pays to use any advantage you can get. <strong>Verilator</strong> is a Verilog simulator and C++ compiler that also supports linting: statically analysing your designs for issues. Not only can Verilator spot problems your synthesis tool might overlook, but it also runs quickly. <a href=https://projectf.io/posts/verilog-lint-with-verilator/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Square Root in Verilog</h2><time class="text-sm antialiased opacity-60">22 Dec 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/square-root-in-verilog/>Square Root in Verilog</a><p>The square root is useful in many circumstances, including statistics, graphics, and signal processing. In this how to, we’re going to look at a straightforward digit-by-digit square root algorithm for integer and fixed-point numbers. There are lower-latency methods, but this one is simple, using only subtraction and bit shifts. <a href=https://projectf.io/posts/square-root-in-verilog/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">iCE40 FPGA Toolchain on Linux</h2><time class="text-sm antialiased opacity-60">11 Nov 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/building-ice40-fpga-toolchain/>iCE40 FPGA Toolchain on Linux</a><p>In this post, I provide a quick guide to building an open-source FPGA toolchain for iCE40 boards, such as iCEBreaker, on Linux. This guide is designed for Ubuntu or Pop!_OS 20.04, but should be straightforward to adjust to your own distro. <a href=https://projectf.io/posts/building-ice40-fpga-toolchain/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Hello Nexys - Part 1</h2><time class="text-sm antialiased opacity-60">04 Nov 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/hello-nexys-1/>Hello Nexys - Part 1</a><p>This two-part tutorial provides a quick introduction to FPGA development with <strong>SystemVerilog</strong> and the <strong>Digilent Nexys Video</strong> board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program with Python or JavaScript, you shouldn’t have any trouble. <a href=https://projectf.io/posts/hello-nexys-1/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Framebuffers</h2><time class="text-sm antialiased opacity-60">30 Oct 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/framebuffers/>Framebuffers</a><p>Welcome back to <em>Exploring FPGA Graphics</em>. In the previous part, we worked with sprites, but another approach is needed as graphics become more complex. Instead of drawing directly to the screen, we draw to a bitmap, which is read out to the screen. This post provides an introduction to framebuffers and how to scale them up. We’ll also learn how to fizzlefade graphics Wolfenstein 3D style. <a href=https://projectf.io/posts/framebuffers/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Hardware Sprites</h2><time class="text-sm antialiased opacity-60">28 Oct 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/hardware-sprites/>Hardware Sprites</a><p>Welcome back to <em>Exploring FPGA Graphics</em>. In the previous part, we updated our display signals and learnt about colour palettes. This part shows you how to create fast, colourful graphics with minimal logic. Hardware sprites maintain much of the simplicity of our Pong design while offering greater creative freedom. <a href=https://projectf.io/posts/hardware-sprites/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Life on Screen</h2><time class="text-sm antialiased opacity-60">22 Sep 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/life-on-screen/>Life on Screen</a><p>In this FPGA demo we’ll experiment with Game of Life, a cellular automaton created by prolific mathematician John Conway in 1970. <a href=https://projectf.io/posts/life-on-screen/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">FPGA Memory Types</h2><time class="text-sm antialiased opacity-60">24 Aug 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/fpga-memory-types/>FPGA Memory Types</a><p>Designing with FPGAs involves many types of memory, some familiar from other devices, but some that are specific to FPGAs. This how to gives a quick overview of the different flavours, together with their strengths and weaknesses, and some sample designs. This guide includes external memory types, such as SRAM and HBM, that are used in CPUs and GPUs, so much of what is said here is generally applicable, but the focus is on FPGAs. <a href=https://projectf.io/posts/fpga-memory-types/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">FPGA Pong</h2><time class="text-sm antialiased opacity-60">30 Jul 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/fpga-pong/>FPGA Pong</a><p>Welcome back to <em>Exploring FPGA Graphics</em>. Last time, we raced the beam; this time, we’ll recreate the arcade classic, Pong and play against our FPGA. <a href=https://projectf.io/posts/fpga-pong/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Division in Verilog</h2><time class="text-sm antialiased opacity-60">01 Jul 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/division-in-verilog/>Division in Verilog</a><p>Division is a fundamental arithmetic operation we take for granted. FPGAs include dedicated hardware to perform addition, subtraction, and multiplication and will infer the necessary logic. Division is different: we need to do it ourselves. This post looks at a straightforward division algorithm for positive integers before extending it to cover fixed-point numbers and signed numbers. <a href=https://projectf.io/posts/division-in-verilog/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Video Timings: VGA, SVGA, 720p, 1080p</h2><time class="text-sm antialiased opacity-60">26 Jun 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/video-timings-vga-720p-1080p/>Video Timings: VGA, SVGA, 720p, 1080p</a><p>To work with standard monitors and TVs, you need to use the correct video timings. This how to includes the timings for five standard display modes using analogue VGA, DVI, HDMI, or DisplayPort: 640x480 (VGA), 800x600 (SVGA), 1280x720, and 1920x1080 (30 Hz and 60 Hz). <a href=https://projectf.io/posts/video-timings-vga-720p-1080p/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Ad Astra</h2><time class="text-sm antialiased opacity-60">10 Jun 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/fpga-ad-astra/>Ad Astra</a><p>This collection of related demos combines some of my earliest FPGA designs from 2018: simple sprites and an animated starfield generated with a linear-feedback shift register. <a href=https://projectf.io/posts/fpga-ad-astra/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Fixed Point Numbers in Verilog</h2><time class="text-sm antialiased opacity-60">26 May 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/fixed-point-numbers-in-verilog/>Fixed Point Numbers in Verilog</a><p>Sometimes you need more precision than integers can provide, but floating-point computation is not trivial (try reading IEEE 754). You could use a library or IP block, but simple fixed point maths can often get the job done with little effort. Furthermore, most FPGAs have dedicated DSP blocks that make multiplication and addition of integers fast; we can take advantage of that with a fixed-point approach. <a href=https://projectf.io/posts/fixed-point-numbers-in-verilog/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Beginning FPGA Graphics</h2><time class="text-sm antialiased opacity-60">20 May 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/fpga-graphics/>Beginning FPGA Graphics</a><p>Welcome to <em>Exploring FPGA Graphics</em>. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo’s David, draw lines and triangles, and animate characters and shapes. Along the way, you’ll experience a range of designs and techniques, from memory and finite state machines to crossing clock domains and translating C algorithms into Verilog. <a href=https://projectf.io/posts/fpga-graphics/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Hello Arty - Part 2</h2><time class="text-sm antialiased opacity-60">06 May 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/hello-arty-2/>Hello Arty - Part 2</a><p>Welcome back to our three-part FPGA tutorial with <strong>SystemVerilog</strong> and the <strong>Digilent Arty A7</strong>. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation. You might be surprised how far counting takes you: by the end of this tutorial, you’ll be creating RGB lighting effects worthy of a cheesy gaming PC. <a href=https://projectf.io/posts/hello-arty-2/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Hello Arty - Part 1</h2><time class="text-sm antialiased opacity-60">24 Apr 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/hello-arty-1/>Hello Arty - Part 1</a><p>This three-part tutorial provides a quick introduction to FPGA development with <strong>SystemVerilog</strong> and the <strong>Digilent Arty A7</strong> board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program with Python or JavaScript, you shouldn’t have any trouble. <a href=https://projectf.io/posts/hello-arty-1/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">Initialize Memory in Verilog</h2><time class="text-sm antialiased opacity-60">16 Apr 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/initialize-memory-in-verilog/>Initialize Memory in Verilog</a><p>It’s common for a simulation or firmware to need data loading into a memory array, ram, or rom. Fortunately, Verilog provides the <strong><code>$readmemh</code></strong> and <strong><code>$readmemb</code></strong> functions for this very purpose. Unfortunately, there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This how to explains the syntax and provides plenty of examples, including how to do this in Yosys and Xilinx Vivado. <a href=https://projectf.io/posts/initialize-memory-in-verilog/>Read More...</a></p></section><section class="relative my-10 first-of-type:mt-0 last-of-type:mb-0"><h2 class="!my-0 pb-1 font-bold !leading-none">FPGA Tooling on Ubuntu 20.04</h2><time class="text-sm antialiased opacity-60">06 Apr 2020</time>
<a class="absolute inset-0 text-[0]" href=https://projectf.io/posts/fpga-dev-ubuntu-20.04/>FPGA Tooling on Ubuntu 20.04</a><p>In this post, I test common FPGA tools for compatibility with Ubuntu 20.04 (AKA Focal Fossa), and my regular desktop OS: Pop!_OS 20.04. These tests are in no way exhaustive: I have tried using the applications as I usually do to exercise the main functionality. I have also included instructions for building the tools from source when available. <a href=https://projectf.io/posts/fpga-dev-ubuntu-20.04/>Read More...</a></p></section></main><footer class="opaco mx-auto flex h-[4.5rem] max-w-4xl items-center px-8 text-[0.9em] opacity-60"><div class=mr-auto><a class=link href=https://projectf.io/>Project F</a>: FPGA and RISC-V. Only hardware makes it possible!
© 2025 Will Green.</div></footer></body></html>