Enable pipe crc regional

Add pipe crc regional size/position registers
settting to enable crc regional.

Signed-off-by: Jialin <lin.a.jia@intel.com>

Author: ljia5

drivers/gpu/drm/i915/display/intel_pipe_crc.c

@@ -434,6 +434,48 @@ display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
 	return 0;
 }
 
+static int intel_crtc_change_crc_region(struct drm_i915_private *dev_priv, 
+					struct intel_crtc *crtc,
+  			       enum pipe pipe,
+			       enum intel_pipe_crc_source *source, u32 *val)
+{
+	struct display_region *region;/* = &dev_priv->regions[dev_priv->next_region++];*/
+	struct drm_checksum_region *region_data =
+			(struct drm_checksum_region *)crtc->config->hw.region_blob->data;
+	u32 reg_val = 0;
+
+	region->x = region_data->x_start;
+	region->y = region_data->y_start;	
+	region->width = region_data->x_end - region_data->x_start;
+	region->height = region_data->y_end - region_data->y_start;
+#if 0
+	intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
+	intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+#endif
+	reg_val = intel_de_read(dev_priv, PIPE_CRC_REGIONAL_SIZE(pipe));
+	reg_val &= ~PIPE_CRC_REGIONAL_SIZE_Y_MASK;
+	reg_val |= (region->height << PIPE_CRC_REGIONAL_SIZE_Y_SHIFT) & PIPE_CRC_REGIONAL_SIZE_Y_MASK;
+	reg_val &= ~PIPE_CRC_REGIONAL_SIZE_X_MASK;
+	reg_val |= (region->width << PIPE_CRC_REGIONAL_SIZE_X_SHIFT) & PIPE_CRC_REGIONAL_SIZE_X_MASK;
+	intel_de_write(dev_priv, PIPE_CRC_REGIONAL_SIZE(pipe), reg_val);
+	intel_de_posting_read(dev_priv, PIPE_CRC_REGIONAL_SIZE(pipe));
+
+	reg_val = intel_de_read(dev_priv, PIPE_CRC_REGIONAL_POS(pipe));
+	reg_val &= ~PIPE_CRC_REGIONAL_POS_Y_MASK;
+	reg_val |= (region->y << PIPE_CRC_REGIONAL_POS_Y_SHIFT) & PIPE_CRC_REGIONAL_POS_Y_MASK;
+	reg_val &= ~PIPE_CRC_REGIONAL_POS_X_MASK;
+	reg_val |= (region->x << PIPE_CRC_REGIONAL_POS_X_SHIFT) & PIPE_CRC_REGIONAL_POS_X_MASK;
+	intel_de_write(dev_priv, PIPE_CRC_REGIONAL_POS(pipe), reg_val);
+	intel_de_posting_read(dev_priv, PIPE_CRC_REGIONAL_POS(pipe));
+#if 0
+	if (dev_priv->next_region == dev_priv->region_cnt) {
+		dev_priv->next_region = 0;
+	}
+#endif
+	return 0;
+}
+
+
 void intel_crtc_crc_init(struct intel_crtc *crtc)
 {
 	struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
@@ -608,6 +650,8 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
 		goto out;
 
 	pipe_crc->source = source;
+
+	intel_crtc_change_crc_region(dev_priv, crtc, pipe, &source, &val);
 	intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
 	intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
 

drivers/gpu/drm/i915/display/intel_pipe_crc.h

@@ -13,6 +13,12 @@ struct drm_i915_private;
 struct intel_crtc;
 
 #ifdef CONFIG_DEBUG_FS
+struct display_region {
+	uint16_t x, y;
+	uint16_t width, height;
+	//uint64_t fbbuf; 	/* gpa, size = width * height * BPP */
+}__packed;
+
 void intel_crtc_crc_init(struct intel_crtc *crtc);
 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,

drivers/gpu/drm/i915/i915_reg.h

@@ -1844,6 +1844,18 @@
  */
 
 /* Pipe A CRC regs */
+#define _PIPE_CRC_REGIONAL_SIZE_A 	0x60048
+#define   PIPE_CRC_REGIONAL_SIZE_Y_SHIFT 		0
+#define   PIPE_CRC_REGIONAL_SIZE_Y_MASK 		0x00003FFF
+#define   PIPE_CRC_REGIONAL_SIZE_X_SHIFT    	16
+#define   PIPE_CRC_REGIONAL_SIZE_X_MASK     	0x3FFF0000
+
+#define _PIPE_CRC_REGIONAL_POS_A 	0x6004C
+#define   PIPE_CRC_REGIONAL_POS_Y_SHIFT 		0
+#define   PIPE_CRC_REGIONAL_POS_Y_MASK  		0x00003FFF
+#define   PIPE_CRC_REGIONAL_POS_X_SHIFT 		16
+#define   PIPE_CRC_REGIONAL_POS_X_MASK  		0x1FFF0000
+
 #define _PIPE_CRC_CTL_A			0x60050
 #define   PIPE_CRC_ENABLE		REG_BIT(31)
 /* skl+ source selection */
@@ -1911,6 +1923,8 @@
 #define _PIPE_CRC_RES_4_B_IVB		0x61070
 #define _PIPE_CRC_RES_5_B_IVB		0x61074
 
+#define PIPE_CRC_REGIONAL_SIZE(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_REGIONAL_SIZE_A)
+#define PIPE_CRC_REGIONAL_POS(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_REGIONAL_POS_A)
 #define PIPE_CRC_CTL(pipe)		_MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
 #define PIPE_CRC_RES_1_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
 #define PIPE_CRC_RES_2_IVB(pipe)	_MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)