giga_r1: enable wifi

Author: pillo79

loader/blobs/CMakeLists.txt

@@ -9,4 +9,15 @@ if (CONFIG_BOARD_ARDUINO_PORTENTA_C33)
         ${CMAKE_CURRENT_SOURCE_DIR}/c33_bl.bin
         ${gen_dir}/c33_bl.bin.inc
     )
-endif()
+endif()
+
+if(CONFIG_BOARD_ARDUINO_GIGA_R1)
+    set(hal_dir                ${ZEPHYR_HAL_INFINEON_MODULE_DIR})
+    set(hal_blobs_dir          ${hal_dir}/zephyr/blobs/img/whd/resources)
+    set(hal_wifi_dir_resources ${hal_dir}/wifi-host-driver/WHD/COMPONENT_WIFI5/resources)
+    # zephyr_library_sources(${hal_blobs_dir}/firmware/COMPONENT_4343W/4343WA1_bin.c)
+    zephyr_library_sources(${hal_blobs_dir}/clm/COMPONENT_4343W/4343WA1_clm_blob.c)
+    zephyr_include_directories(${hal_wifi_dir_resources}/nvram/COMPONENT_4343W/COMPONENT_MURATA-1DX)
+    zephyr_include_directories(${hal_wifi_dir_resources}/resource_imp)
+    zephyr_library_sources(murata_wifi_fw.c)
+endif()

loader/blobs/murata_wifi_fw.c

@@ -0,0 +1,15 @@
+#include <zephyr/devicetree.h>
+#include "wiced_resource.h"
+
+#define QUADSPI_MMAP_BASE   DT_REG_ADDR_BY_IDX(DT_NODELABEL(quadspi), 1)
+#define FLASH_CHIP_OFFSET   DT_REG_ADDR(DT_NODELABEL(qspi_flash))
+#define AIROC_PART_OFS      DT_REG_ADDR(DT_NODELABEL(airoc_firmware))
+
+#define FW_ADDR (QUADSPI_MMAP_BASE + FLASH_CHIP_OFFSET + AIROC_PART_OFS)
+#define FW_SIZE 421421 /* providing this at runtime needs HAL update */
+
+const resource_hnd_t wifi_firmware_image = {
+	RESOURCE_IN_MEMORY,
+	FW_SIZE,
+	{ .mem = { (const char *) FW_ADDR } }
+};

variants/arduino_giga_r1_stm32h747xx_m7/arduino_giga_r1_stm32h747xx_m7.conf

@@ -11,7 +11,7 @@ CONFIG_CDC_ACM_DTE_RATE_CALLBACK_SUPPORT=y
 
 CONFIG_LLEXT_STORAGE_WRITABLE=n
 CONFIG_SHARED_MULTI_HEAP=y
-CONFIG_HEAP_MEM_POOL_SIZE=2048
+CONFIG_HEAP_MEM_POOL_SIZE=24576
 CONFIG_SHELL_STACK_SIZE=32768
 CONFIG_MAIN_STACK_SIZE=32768
 CONFIG_LLEXT_HEAP_SIZE=128
@@ -64,3 +64,25 @@ CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048
 CONFIG_BT_RX_STACK_SIZE=4096
 
 CONFIG_STM32H7_BOOT_M4_AT_INIT=n
+
+CONFIG_SDHC=y
+CONFIG_NETWORKING=y
+CONFIG_SDIO_STACK=y
+CONFIG_WIFI=y
+CONFIG_SDHC_INIT_PRIORITY=75
+CONFIG_AIROC_WIFI_CUSTOM=y
+CONFIG_CYW4343W=y
+CONFIG_CYW4343W_MURATA_1DX=y
+
+CONFIG_NET_MGMT=y
+CONFIG_NET_MGMT_EVENT=y
+CONFIG_NET_MGMT_EVENT_STACK_SIZE=8192
+CONFIG_NET_MAX_CONTEXTS=10
+CONFIG_NET_MGMT_EVENT_QUEUE_TIMEOUT=5000
+CONFIG_NET_MGMT_EVENT_QUEUE_SIZE=16
+CONFIG_NET_MGMT_EVENT_QUEUE_SIZE=20
+CONFIG_NET_MAX_CONN=10
+CONFIG_NET_MGMT_THREAD_PRIO_CUSTOM=y
+CONFIG_NET_MGMT_THREAD_PRIORITY=3
+CONFIG_NET_MGMT_EVENT_STACK_SIZE=4608
+CONFIG_NET_L2_ETHERNET_MGMT=y

variants/arduino_giga_r1_stm32h747xx_m7/arduino_giga_r1_stm32h747xx_m7.overlay

@@ -342,6 +342,45 @@
 	};
 };
 
+qspi_flash: &n25q128a1 {
+	/delete-node/ partitions;
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Partition 1: WiFi firmware and certificates 1MB - 4kB */
+		wlan_partition: partition@1000 {
+			label = "wlan";
+			reg = <0x001000 DT_SIZE_K(1020)>;
+		};
+
+		/* Partition 2: OTA 5MB */
+		ota_partition: partition@100000 {
+			label = "ota";
+			reg = <0x100000 DT_SIZE_M(5)>;
+		};
+
+		/* Partition 3: Provisioning KVStore 1MB */
+		kvs_partition: partition@600000 {
+			label = "kvs";
+			reg = <0x600000 DT_SIZE_M(1)>;
+		};
+
+		/* Partition 4: User data 7MB */
+		storage_partition: partition@700000 {
+			label = "storage";
+			reg = <0x700000 DT_SIZE_M(7)>;
+		};
+
+		/* Partition 5: Binary FW image for the Airoc WLAN */
+		airoc_firmware: partition@e80000 {
+			label = "4343WA1.bin";
+			reg = <0xe80000 DT_SIZE_K(512)>;
+		};
+	};
+};
+
 / {
 	zephyr,user {
 		digital-pin-gpios = <&arduino_header 6 0>,