@@ -1809,6 +1809,11 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
18091809 __ std(R0, dst_offset+8, R1_SP);
18101810 }
18111811 size += 16;
1812+ #ifndef PRODUCT
1813+ if (st != nullptr) {
1814+ st->print("%-7s [R1_SP + #%d] -> [R1_SP + #%d] \t// vector spill copy", "SPILL", src_offset, dst_offset);
1815+ }
1816+ #endif // !PRODUCT
18121817 }
18131818 // VectorRegister->Memory Spill.
18141819 else if (src_lo_rc == rc_vec && dst_lo_rc == rc_stack) {
@@ -1825,6 +1830,16 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
18251830 }
18261831 size += 8;
18271832 }
1833+ #ifndef PRODUCT
1834+ if (st != nullptr) {
1835+ if (PowerArchitecturePPC64 >= 9) {
1836+ st->print("%-7s %s, [R1_SP + #%d] \t// vector spill copy", "STXV", Matcher::regName[src_lo], dst_offset);
1837+ } else {
1838+ st->print("%-7s %s, R1_SP, %d \t// vector spill copy", "ADDI", Matcher::regName[src_lo], dst_offset);
1839+ st->print("%-7s %s, [R1_SP] \t// vector spill copy", "STXVD2X", Matcher::regName[src_lo]);
1840+ }
1841+ }
1842+ #endif // !PRODUCT
18281843 }
18291844 // Memory->VectorRegister Spill.
18301845 else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vec) {
@@ -1841,6 +1856,16 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
18411856 }
18421857 size += 8;
18431858 }
1859+ #ifndef PRODUCT
1860+ if (st != nullptr) {
1861+ if (PowerArchitecturePPC64 >= 9) {
1862+ st->print("%-7s %s, [R1_SP + #%d] \t// vector spill copy", "LXV", Matcher::regName[dst_lo], src_offset);
1863+ } else {
1864+ st->print("%-7s %s, R1_SP, %d \t// vector spill copy", "ADDI", Matcher::regName[src_lo], src_offset);
1865+ st->print("%-7s %s, [R1_SP] \t// vector spill copy", "LXVD2X", Matcher::regName[dst_lo]);
1866+ }
1867+ }
1868+ #endif // !PRODUCT
18441869 }
18451870 // VectorRegister->VectorRegister.
18461871 else if (src_lo_rc == rc_vec && dst_lo_rc == rc_vec) {
@@ -1850,6 +1875,12 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
18501875 __ xxlor(Rdst, Rsrc, Rsrc);
18511876 }
18521877 size += 4;
1878+ #ifndef PRODUCT
1879+ if (st != nullptr) {
1880+ st->print("%-7s %s, %s, %s\t// vector spill copy",
1881+ "XXLOR", Matcher::regName[dst_lo], Matcher::regName[src_lo], Matcher::regName[src_lo]);
1882+ }
1883+ #endif // !PRODUCT
18531884 }
18541885 else {
18551886 ShouldNotReachHere(); // No VR spill.
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