@@ -1834,6 +1834,12 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
18341834 }
18351835 size += 8;
18361836 }
1837+ #ifndef PRODUCT
1838+ if (!masm && !do_size) {
1839+ st->print("%-7s %s, [R1_SP + #%d] \t// vector spill copy%s",
1840+ "STX", Matcher::regName[src_lo], dst_offset, is_aligned(dst_offset, 16) ? "" : " (unaligned)");
1841+ }
1842+ #endif // !PRODUCT
18371843 }
18381844 // Memory->VectorRegister Spill.
18391845 else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vec) {
@@ -1860,6 +1866,12 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
18601866 }
18611867 size += 8;
18621868 }
1869+ #ifndef PRODUCT
1870+ if (!masm && !do_size) {
1871+ st->print("%-7s %s, [R1_SP + #%d] \t// vector spill copy%s",
1872+ "LXV", Matcher::regName[dst_lo], src_offset, is_aligned(src_offset, 16) ? "" : " (unaligned)");
1873+ }
1874+ #endif // !PRODUCT
18631875 }
18641876 // VectorRegister->VectorRegister.
18651877 else if (src_lo_rc == rc_vec && dst_lo_rc == rc_vec) {
@@ -1869,6 +1881,12 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
18691881 __ xxlor(Rdst, Rsrc, Rsrc);
18701882 }
18711883 size += 4;
1884+ #ifndef PRODUCT
1885+ if (!masm && !do_size) {
1886+ st->print("%-7s %s, %s, %s\t// vector spill copy",
1887+ "XXLOR", Matcher::regName[dst_lo], Matcher::regName[src_lo], Matcher::regName[src_lo]);
1888+ }
1889+ #endif // !PRODUCT
18721890 }
18731891 else {
18741892 ShouldNotReachHere(); // No VR spill.
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