diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a40eea7aee56..b758b3a1e027 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -185,6 +185,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     }
   }
 
+  if (Subtarget.hasExtXcvsimd()) {
+    addRegisterClass(MVT::v4i8, &RISCV::GPRRegClass);
+    addRegisterClass(MVT::v2i16, &RISCV::GPRRegClass);
+  }
+
   // Compute derived properties from the register classes.
   computeRegisterProperties(STI.getRegisterInfo());
 
@@ -980,6 +985,42 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     }
   }
 
+  if (Subtarget.hasExtXcvsimd()) {
+    const auto AddTypeForPOrXcvsimd = [&](MVT VT, MVT PromotedBitwiseVT) {
+      // Expand all builtin opcodes.
+      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
+        setOperationAction(Opc, VT, Expand);
+
+      setOperationAction(ISD::BITCAST, VT, Legal);
+
+      // Promote load and store operations.
+      setOperationAction(ISD::LOAD, VT, Promote);
+      AddPromotedToType(ISD::LOAD, VT, PromotedBitwiseVT);
+      setOperationAction(ISD::STORE, VT, Promote);
+      AddPromotedToType(ISD::STORE, VT, PromotedBitwiseVT);
+      setOperationAction(ISD::ADD, VT, Legal);
+    };
+
+    if (Subtarget.is64Bit()) {
+      AddTypeForPOrXcvsimd(MVT::v8i8, MVT::i64);
+      AddTypeForPOrXcvsimd(MVT::v4i16, MVT::i64);
+      AddTypeForPOrXcvsimd(MVT::v2i32, MVT::i64);
+    } else {
+      AddTypeForPOrXcvsimd(MVT::v4i8, MVT::i32);
+      AddTypeForPOrXcvsimd(MVT::v2i16, MVT::i32);
+    }
+
+    // Expand all truncating stores and extending loads.
+    for (MVT VT0 : MVT::vector_valuetypes()) {
+      for (MVT VT1 : MVT::vector_valuetypes()) {
+        setTruncStoreAction(VT0, VT1, Expand);
+        setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
+        setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
+        setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
+      }
+    }
+  }
+
   if (Subtarget.hasForcedAtomics()) {
     // Set atomic rmw/cas operations to expand to force __sync libcalls.
     setOperationAction(
@@ -1786,6 +1827,19 @@ static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT,
           useRVVForFixedLengthVectorVT(VT, Subtarget)) &&
          "Expected legal fixed length vector!");
 
+
+  if (Subtarget.hasExtXcvsimd()) {
+    MVT EltVT = VT.getVectorElementType();
+    switch (EltVT.SimpleTy) {
+    default:
+      llvm_unreachable("unexpected element type for Xcvsimd container");
+    case MVT::i8:
+      return MVT::getVectorVT(MVT::i8, 4);
+    case MVT::i16:
+      return MVT::getVectorVT(MVT::i16, 2);
+    }
+  }
+
   unsigned MinVLen = Subtarget.getRealMinVLen();
   unsigned MaxELen = Subtarget.getELEN();
 
@@ -6640,6 +6694,44 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG,
   return convertFromScalableVector(VT, VPOp, DAG, Subtarget);
 }
 
+SDValue RISCVTargetLowering::lowerVPOpForP(SDValue Op, SelectionDAG &DAG,
+                                       unsigned RISCVISDOpc,
+                                       bool HasMergeOp) const {
+  SDLoc DL(Op);
+  MVT VT = Op.getSimpleValueType();
+  SmallVector<SDValue, 4> Ops;
+
+  MVT ContainerVT = VT;
+  if (VT.isFixedLengthVector())
+    ContainerVT = getContainerForFixedLengthVector(VT);
+
+  for (const auto &OpIdx : enumerate(Op->ops())) {
+    SDValue V = OpIdx.value();
+    assert(!isa<VTSDNode>(V) && "Unexpected VTSDNode node!");
+    // Add dummy merge value before the mask.
+    if (HasMergeOp && *ISD::getVPMaskIdx(Op.getOpcode()) == OpIdx.index())
+      Ops.push_back(DAG.getUNDEF(ContainerVT));
+    // Pass through operands which aren't fixed-length vectors.
+    if (!V.getValueType().isFixedLengthVector()) {
+      Ops.push_back(V);
+      continue;
+    }
+    // "cast" fixed length vector to a scalable vector.
+    MVT OpVT = V.getSimpleValueType();
+    MVT ContainerVT = getContainerForFixedLengthVector(OpVT);
+    assert(useRVVForFixedLengthVectorVT(OpVT) &&
+           "Only fixed length vectors are supported!");
+    Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget));
+  }
+
+  if (!VT.isFixedLengthVector())
+    return DAG.getNode(RISCVISDOpc, DL, VT, Ops, Op->getFlags());
+
+  SDValue VPOp = DAG.getNode(RISCVISDOpc, DL, ContainerVT, Ops, Op->getFlags());
+
+  return convertFromScalableVector(VT, VPOp, DAG, Subtarget);
+}
+
 SDValue RISCVTargetLowering::lowerVPExtMaskOp(SDValue Op,
                                               SelectionDAG &DAG) const {
   SDLoc DL(Op);
@@ -10997,6 +11089,8 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   // UseGPRForF64 if targeting soft-float ABIs or an FLEN=32 ABI, if passing a
   // variadic argument, or if no F64 argument registers are available.
   bool UseGPRForF64 = true;
+  // UseGPRForV if targeting packed-simd ABIs.
+  bool UseGPRForV = TLI.getSubtarget().hasExtXcvsimd();
 
   switch (ABI) {
   default:
@@ -11124,7 +11218,7 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
     Reg = State.AllocateReg(ArgFPR32s);
   else if (ValVT == MVT::f64 && !UseGPRForF64)
     Reg = State.AllocateReg(ArgFPR64s);
-  else if (ValVT.isVector()) {
+  else if (ValVT.isVector() && !UseGPRForV) {
     Reg = allocateRVVReg(ValVT, ValNo, FirstMaskArgument, State, TLI);
     if (!Reg) {
       // For return values, the vector must be passed fully via registers or
@@ -11175,7 +11269,7 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   }
 
   assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT ||
-          (TLI.getSubtarget().hasVInstructions() && ValVT.isVector())) &&
+          ((UseGPRForV || TLI.getSubtarget().hasVInstructions()) && ValVT.isVector())) &&
          "Expected an XLenVT or vector types at this stage");
 
   if (Reg) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 419aef28277a..0769ed783e1f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -666,6 +666,8 @@ class RISCVTargetLowering : public TargetLowering {
                             bool HasMergeOp = false, bool HasMask = true) const;
   SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc,
                     bool HasMergeOp = false) const;
+  SDValue lowerVPOpForP(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc,
+                    bool HasMergeOp = false) const;
   SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
                          unsigned VecOpc) const;
   SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5558f359b543..bd283a524b5d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1156,9 +1156,9 @@ def : InstAlias<".insn_s $opcode, $funct3, $rs2, ${imm12}(${rs1})",
 /// Generic pattern classes
 
 class PatGpr<SDPatternOperator OpNode, RVInst Inst>
-    : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
+    : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1))), (Inst GPR:$rs1)>;
 class PatGprGpr<SDPatternOperator OpNode, RVInst Inst>
-    : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
+    : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), (XLenVT GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2)>;
 
 class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType>
     : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), ImmType:$imm)),
@@ -1240,7 +1240,7 @@ class shiftop<SDPatternOperator operator>
               (operator node:$val, (XLenVT (shiftMaskXLen node:$count)))>;
 class shiftopw<SDPatternOperator operator>
     : PatFrag<(ops node:$val, node:$count),
-              (operator node:$val, (i64 (shiftMask32 node:$count)))>;
+              (operator node:$val, (i64 (shiftMask32 (i64 node:$count))))>;
 
 def : PatGprGpr<shiftop<shl>, SLL>;
 def : PatGprGpr<shiftop<srl>, SRL>;
@@ -1257,7 +1257,7 @@ def PseudoAddTPRel : Pseudo<(outs GPR:$rd),
 
 /// FrameIndex calculations
 
-def : Pat<(FrameAddrRegImm GPR:$rs1, simm12:$imm12),
+def : Pat<(FrameAddrRegImm (XLenVT GPR:$rs1), simm12:$imm12),
           (ADDI GPR:$rs1, simm12:$imm12)>;
 
 /// HI and ADD_LO address nodes.
@@ -1293,19 +1293,20 @@ def : PatGprSimm12<setult, SLTIU>;
 
 // Define pattern expansions for setcc operations that aren't directly
 // handled by a RISC-V instruction.
-def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>;
-def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
-def : Pat<(seteq GPR:$rs1, simm12_plus1:$imm12),
+def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), 0)), (SLTIU GPR:$rs1, 1)>;
+def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), GPR:$rs2)),
+          (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
+def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), simm12_plus1:$imm12)),
           (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>;
-def : Pat<(seteq GPR:$rs1, -2048),
-          (SLTIU (XORI GPR:$rs1, -2048), 1)>;
-def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
-def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
-def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12),
-          (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;
-def : Pat<(setne GPR:$rs1, -2048),
-          (SLTU X0, (XORI GPR:$rs1, -2048))>;
-def : Pat<(setne GPR:$rs1, -1), (SLTIU GPR:$rs1, -1)>;
+def : Pat<(XLenVT (seteq (XLenVT GPR:$rs1), -2048)),
+          (SLTIU (XORI (XLenVT GPR:$rs1), -2048), 1)>;
+def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), 0)), (SLTU (XLenVT X0), GPR:$rs1)>;
+def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), GPR:$rs2)), (SLTU (XLenVT X0), (XOR GPR:$rs1, GPR:$rs2))>;
+def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), simm12_plus1:$imm12)),
+          (SLTU (XLenVT X0), (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;
+def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), -2048)),
+          (SLTU (XLenVT X0), (XORI (XLenVT GPR:$rs1), -2048))>;
+def : Pat<(XLenVT (setne (XLenVT GPR:$rs1), -1)), (SLTIU (XLenVT GPR:$rs1), -1)>;
 
 def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
@@ -1327,36 +1328,38 @@ let Predicates = [HasShortForwardBranchOpt],
 def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst),
                             (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
                              GPR:$falsev, GPR:$truev),
-                            [(set GPR:$dst,
-                              (riscv_selectcc_frag:$cc GPR:$lhs, GPR:$rhs,
-                                                       cond, GPR:$truev,
-                                                       GPR:$falsev))]>,
+                            [(set (XLenVT GPR:$dst),
+                              (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), (XLenVT GPR:$rhs),
+                                                       cond, (XLenVT GPR:$truev),
+                                                       (XLenVT GPR:$falsev)))]>,
                      Sched<[WriteSFB, ReadSFB, ReadSFB, ReadSFB, ReadSFB]>;
 }
 
-multiclass SelectCC_GPR_rrirr<RegisterClass valty> {
+multiclass SelectCC_GPR_rrirr<RegisterClass valty, ValueType valvt> {
   let usesCustomInserter = 1 in
   def _Using_CC_GPR : Pseudo<(outs valty:$dst),
                              (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
                               valty:$truev, valty:$falsev),
                              [(set valty:$dst,
-                               (riscv_selectcc_frag:$cc GPR:$lhs, GPR:$rhs, cond,
-                                                        valty:$truev, valty:$falsev))]>;
+                               (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
+                                                        (XLenVT GPR:$rhs), cond,
+                                                        (valvt valty:$truev),
+                                                        (valvt valty:$falsev)))]>;
   // Explicitly select 0 in the condition to X0. The register coalescer doesn't
   // always do it.
-  def : Pat<(riscv_selectcc_frag:$cc GPR:$lhs, 0, cond, valty:$truev,
-                                     valty:$falsev),
-            (!cast<Instruction>(NAME#"_Using_CC_GPR") GPR:$lhs, X0,
-             (IntCCtoRISCVCC $cc), valty:$truev, valty:$falsev)>;
+  def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), 0, cond, (valvt valty:$truev),
+                                                                 (valvt valty:$falsev)),
+            (!cast<Instruction>(NAME#"_Using_CC_GPR") (XLenVT GPR:$lhs), (XLenVT X0),
+             (IntCCtoRISCVCC $cc), (valvt valty:$truev), (valvt valty:$falsev))>;
 }
 
 let Predicates = [NoShortForwardBranchOpt] in
-defm Select_GPR : SelectCC_GPR_rrirr<GPR>;
+defm Select_GPR : SelectCC_GPR_rrirr<GPR, XLenVT>;
 
-class SelectCompressOpt<CondCode Cond>: Pat<(riscv_selectcc_frag:$select GPR:$lhs, simm12_no6:$Constant, Cond,
-                                                  GPR:$truev, GPR:$falsev),
-    (Select_GPR_Using_CC_GPR (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0,
-                          (IntCCtoRISCVCC $select), GPR:$truev, GPR:$falsev)>;
+class SelectCompressOpt<CondCode Cond>: Pat<(riscv_selectcc_frag:$select (XLenVT GPR:$lhs), simm12_no6:$Constant, Cond,
+                                                  (XLenVT GPR:$truev), (XLenVT GPR:$falsev)),
+    (Select_GPR_Using_CC_GPR (ADDI GPR:$lhs, (NegImm simm12:$Constant)), (XLenVT X0),
+                          (IntCCtoRISCVCC $select), (XLenVT GPR:$truev), (XLenVT GPR:$falsev))>;
 
 def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">;
 
@@ -1369,15 +1372,15 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
 
 // Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
 multiclass BccPat<CondCode Cond, RVInstB Inst> {
-  def : Pat<(riscv_brcc GPR:$rs1, GPR:$rs2, Cond, bb:$imm12),
+  def : Pat<(riscv_brcc (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), Cond, bb:$imm12),
             (Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
   // Explicitly select 0 to X0. The register coalescer doesn't always do it.
-  def : Pat<(riscv_brcc GPR:$rs1, 0, Cond, bb:$imm12),
-            (Inst GPR:$rs1, X0, simm13_lsb0:$imm12)>;
+  def : Pat<(riscv_brcc (XLenVT GPR:$rs1), 0, Cond, bb:$imm12),
+            (Inst GPR:$rs1, (XLenVT X0), simm13_lsb0:$imm12)>;
 }
 
 class BrccCompessOpt<CondCode Cond, RVInstB Inst> : Pat<(riscv_brcc GPR:$lhs, simm12_no6:$Constant, Cond, bb:$place),
-                              (Inst (ADDI GPR:$lhs, (NegImm simm12:$Constant)), X0, bb:$place)>;
+                              (Inst (ADDI GPR:$lhs, (NegImm simm12:$Constant)), (XLenVT X0), bb:$place)>;
 
 defm : BccPat<SETEQ, BEQ>;
 defm : BccPat<SETNE, BNE>;
@@ -1430,9 +1433,9 @@ def PseudoCALL : Pseudo<(outs), (ins call_symbol:$func), []>,
 def : Pat<(riscv_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>;
 def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
-def : Pat<(riscv_uret_flag), (URET X0, X0)>;
-def : Pat<(riscv_sret_flag), (SRET X0, X0)>;
-def : Pat<(riscv_mret_flag), (MRET X0, X0)>;
+def : Pat<(riscv_uret_flag), (URET (XLenVT X0), (XLenVT X0))>;
+def : Pat<(riscv_sret_flag), (SRET (XLenVT X0), (XLenVT X0))>;
+def : Pat<(riscv_mret_flag), (MRET (XLenVT X0), (XLenVT X0))>;
 
 let isCall = 1, Defs = [X1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
@@ -1485,14 +1488,14 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 0,
 def PseudoLA : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
                       "la", "$dst, $src">;
 
-def : Pat<(riscv_la tglobaladdr:$in), (PseudoLA tglobaladdr:$in)>;
+def : Pat<(XLenVT (riscv_la (XLenVT tglobaladdr:$in))), (PseudoLA tglobaladdr:$in)>;
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 0,
     isAsmParserOnly = 1 in
 def PseudoLA_TLS_IE : Pseudo<(outs GPR:$dst), (ins bare_symbol:$src), [],
                              "la.tls.ie", "$dst, $src">;
 
-def : Pat<(riscv_la_tls_ie tglobaltlsaddr:$in),
+def : Pat<(XLenVT (riscv_la_tls_ie (XLenVT tglobaltlsaddr:$in))),
           (PseudoLA_TLS_IE  tglobaltlsaddr:$in)>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, isCodeGenOnly = 0,
@@ -1524,7 +1527,7 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
 /// Loads
 
 multiclass LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT> {
-  def : Pat<(vt (LoadOp (AddrRegImm GPR:$rs1, simm12:$imm12))),
+  def : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
             (Inst GPR:$rs1, simm12:$imm12)>;
 }
 
@@ -1540,7 +1543,7 @@ defm : LdPat<zextloadi16, LHU>;
 
 multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
                  ValueType vt> {
-  def : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm GPR:$rs1, simm12:$imm12)),
+  def : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
             (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
 }
 
@@ -1576,7 +1579,7 @@ def : Pat<(atomic_fence (XLenVT 7), (timm)), (FENCE 0b11, 0b11)>;
 
 class ReadSysReg<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins),
-           [(set GPR:$rd, (riscv_read_csr (XLenVT SR.Encoding)))]>,
+           [(set (XLenVT GPR:$rd), (riscv_read_csr (XLenVT SR.Encoding)))]>,
     PseudoInstExpansion<(CSRRS GPR:$rd, SR.Encoding, X0)> {
   let hasSideEffects = 0;
   let Uses = Regs;
@@ -1584,7 +1587,7 @@ class ReadSysReg<SysReg SR, list<Register> Regs>
 
 class WriteSysReg<SysReg SR, list<Register> Regs>
   : Pseudo<(outs), (ins GPR:$val),
-           [(riscv_write_csr (XLenVT SR.Encoding), GPR:$val)]>,
+           [(riscv_write_csr (XLenVT SR.Encoding), (XLenVT GPR:$val))]>,
     PseudoInstExpansion<(CSRRW X0, SR.Encoding, GPR:$val)> {
   let hasSideEffects = 0;
   let Defs = Regs;
@@ -1600,7 +1603,7 @@ class WriteSysRegImm<SysReg SR, list<Register> Regs>
 
 class SwapSysReg<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins GPR:$val),
-           [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), GPR:$val))]>,
+           [(set GPR:$rd, (XLenVT (riscv_swap_csr (XLenVT SR.Encoding), GPR:$val)))]>,
     PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> {
   let hasSideEffects = 0;
   let Uses = Regs;
@@ -1609,7 +1612,7 @@ class SwapSysReg<SysReg SR, list<Register> Regs>
 
 class SwapSysRegImm<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins uimm5:$val),
-           [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val))]>,
+           [(set GPR:$rd, (XLenVT (riscv_swap_csr (XLenVT SR.Encoding), uimm5:$val)))]>,
     PseudoInstExpansion<(CSRRWI GPR:$rd, SR.Encoding, uimm5:$val)> {
   let hasSideEffects = 0;
   let Uses = Regs;
@@ -1734,7 +1737,7 @@ defm : StPat<store, SD, GPR, i64>;
 /// readcyclecounter
 // On RV64, we can directly read the 64-bit "cycle" CSR.
 let Predicates = [IsRV64] in
-def : Pat<(i64 (readcyclecounter)), (CSRRS CYCLE.Encoding, X0)>;
+def : Pat<(i64 (readcyclecounter)), (CSRRS CYCLE.Encoding, (XLenVT X0))>;
 // On RV32, ReadCycleWide will be expanded to the suggested loop reading both
 // halves of the 64-bit "cycle" CSR.
 let Predicates = [IsRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
@@ -1760,13 +1763,13 @@ def HWASAN_CHECK_MEMACCESS_SHORTGRANULES
                                                       (i32 timm:$accessinfo))]>;
 
 /// Simple optimization
-def : Pat<(add GPR:$rs1, (AddiPair:$rs2)),
+def : Pat<(add (XLenVT GPR:$rs1), (AddiPair:$rs2)),
           (ADDI (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),
                 (AddiPairImmSmall GPR:$rs2))>;
 
 let Predicates = [IsRV64] in {
 // Select W instructions if only the lower 32-bits of the result are used.
-def : Pat<(binop_allwusers<add> GPR:$rs1, (AddiPair:$rs2)),
+def : Pat<(binop_allwusers<add> (XLenVT GPR:$rs1), (AddiPair:$rs2)),
           (ADDIW (ADDIW GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),
                  (AddiPairImmSmall AddiPair:$rs2))>;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 5227acc1e504..8a26a361ceb9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -45,7 +45,7 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
 
 multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
                        ValueType vt = XLenVT> {
-  def : Pat<(StoreOp (AddrRegImm GPR:$rs1, simm12:$imm12), (vt StTy:$rs2)),
+  def : Pat<(StoreOp (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12), (vt StTy:$rs2)),
             (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
 }
 
@@ -150,16 +150,16 @@ defm : AMOPat<"atomic_load_min_32", "AMOMIN_W">;
 defm : AMOPat<"atomic_load_umax_32", "AMOMAXU_W">;
 defm : AMOPat<"atomic_load_umin_32", "AMOMINU_W">;
 
-def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr),
-          (AMOADD_W GPR:$addr, (SUB X0, GPR:$incr))>;
-def : Pat<(atomic_load_sub_32_acquire GPR:$addr, GPR:$incr),
-          (AMOADD_W_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
-def : Pat<(atomic_load_sub_32_release GPR:$addr, GPR:$incr),
-          (AMOADD_W_RL GPR:$addr, (SUB X0, GPR:$incr))>;
-def : Pat<(atomic_load_sub_32_acq_rel GPR:$addr, GPR:$incr),
-          (AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
-def : Pat<(atomic_load_sub_32_seq_cst GPR:$addr, GPR:$incr),
-          (AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
+def : Pat<(XLenVT (atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr)),
+          (AMOADD_W GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
+def : Pat<(XLenVT (atomic_load_sub_32_acquire GPR:$addr, GPR:$incr)),
+          (AMOADD_W_AQ GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
+def : Pat<(XLenVT (atomic_load_sub_32_release GPR:$addr, GPR:$incr)),
+          (AMOADD_W_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
+def : Pat<(XLenVT (atomic_load_sub_32_acq_rel GPR:$addr, GPR:$incr)),
+          (AMOADD_W_AQ_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
+def : Pat<(XLenVT (atomic_load_sub_32_seq_cst GPR:$addr, GPR:$incr)),
+          (AMOADD_W_AQ_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
 
 /// Pseudo AMOs
 
@@ -175,15 +175,15 @@ let Size = 20 in
 def PseudoAtomicLoadNand32 : PseudoAMO;
 // Ordering constants must be kept in sync with the AtomicOrdering enum in
 // AtomicOrdering.h.
-def : Pat<(atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr),
+def : Pat<(XLenVT (atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr)),
           (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>;
-def : Pat<(atomic_load_nand_32_acquire GPR:$addr, GPR:$incr),
+def : Pat<(XLenVT (atomic_load_nand_32_acquire GPR:$addr, GPR:$incr)),
           (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 4)>;
-def : Pat<(atomic_load_nand_32_release GPR:$addr, GPR:$incr),
+def : Pat<(XLenVT (atomic_load_nand_32_release GPR:$addr, GPR:$incr)),
           (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 5)>;
-def : Pat<(atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr),
+def : Pat<(XLenVT (atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr)),
           (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 6)>;
-def : Pat<(atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr),
+def : Pat<(XLenVT (atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr)),
           (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>;
 
 class PseudoMaskedAMO
@@ -274,15 +274,15 @@ class PseudoCmpXchg
 // Ordering constants must be kept in sync with the AtomicOrdering enum in
 // AtomicOrdering.h.
 multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst> {
-  def : Pat<(!cast<PatFrag>(Op#"_monotonic") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(XLenVT (!cast<PatFrag>(Op#"_monotonic") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 2)>;
-  def : Pat<(!cast<PatFrag>(Op#"_acquire") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(XLenVT (!cast<PatFrag>(Op#"_acquire") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 4)>;
-  def : Pat<(!cast<PatFrag>(Op#"_release") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(XLenVT (!cast<PatFrag>(Op#"_release") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 5)>;
-  def : Pat<(!cast<PatFrag>(Op#"_acq_rel") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(XLenVT (!cast<PatFrag>(Op#"_acq_rel") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 6)>;
-  def : Pat<(!cast<PatFrag>(Op#"_seq_cst") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(XLenVT (!cast<PatFrag>(Op#"_seq_cst") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 7)>;
 }
 
@@ -322,15 +322,15 @@ defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D">;
 /// 64-bit AMOs
 
 def : Pat<(i64 (atomic_load_sub_64_monotonic GPR:$addr, GPR:$incr)),
-          (AMOADD_D GPR:$addr, (SUB X0, GPR:$incr))>;
+          (AMOADD_D GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
 def : Pat<(i64 (atomic_load_sub_64_acquire GPR:$addr, GPR:$incr)),
-          (AMOADD_D_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
+          (AMOADD_D_AQ GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
 def : Pat<(i64 (atomic_load_sub_64_release GPR:$addr, GPR:$incr)),
-          (AMOADD_D_RL GPR:$addr, (SUB X0, GPR:$incr))>;
+          (AMOADD_D_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
 def : Pat<(i64 (atomic_load_sub_64_acq_rel GPR:$addr, GPR:$incr)),
-          (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
+          (AMOADD_D_AQ_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
 def : Pat<(i64 (atomic_load_sub_64_seq_cst GPR:$addr, GPR:$incr)),
-          (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
+          (AMOADD_D_AQ_RL GPR:$addr, (SUB (XLenVT X0), GPR:$incr))>;
 
 /// 64-bit pseudo AMOs
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
index 7ba6294de016..0718a6e5dede 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
@@ -766,53 +766,53 @@ class PatCoreVMacGprGprUimm5 <string intr, string asm>
 
 let Predicates = [HasExtXcvmac] in {
 
-  def : Pat<(add GPR:$rd, (mul GPR:$rs1, GPR:$rs2)),
+  def : Pat<(XLenVT (add GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
             (CV_MAC GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2)),
+  def : Pat<(XLenVT (sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
             (CV_MSU GPR:$rd, GPR:$rs1, GPR:$rs2)>;
 
-  def : Pat<(muls GPR:$rs1, GPR:$rs2),
+  def : Pat<(XLenVT (muls GPR:$rs1, GPR:$rs2)),
             (CV_MULSN GPR:$rs1, GPR:$rs2, 0)>;
-  def : Pat<(mulhhs GPR:$rs1, GPR:$rs2),
+  def : Pat<(XLenVT (mulhhs GPR:$rs1, GPR:$rs2)),
             (CV_MULHHSN GPR:$rs1, GPR:$rs2, 0)>;
-  def : Pat<(sra (muls GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (sra (muls GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MULSN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(sra (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (sra (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MULHHSN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(shiftRound (muls GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (shiftRound (muls GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MULSRN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(shiftRound (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (shiftRound (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MULHHSRN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
 
-  def : Pat<(mulu GPR:$rs1, GPR:$rs2),
+  def : Pat<(XLenVT (mulu GPR:$rs1, GPR:$rs2)),
             (CV_MULUN GPR:$rs1, GPR:$rs2, 0)>;
-  def : Pat<(mulhhu GPR:$rs1, GPR:$rs2),
+  def : Pat<(XLenVT (mulhhu GPR:$rs1, GPR:$rs2)),
             (CV_MULHHUN GPR:$rs1, GPR:$rs2, 0)>;
-  def : Pat<(srl (mulu GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (srl (mulu GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MULUN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(srl (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (srl (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MULHHUN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(ushiftRound (mulu GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (ushiftRound (mulu GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MULURN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(ushiftRound (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (ushiftRound (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MULHHURN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
 
-  def : Pat<(sra (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (sra (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MACSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(sra (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (sra (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MACHHSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(shiftRound (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (shiftRound (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MACSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(shiftRound (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (shiftRound (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MACHHSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
 
-  def : Pat<(srl (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (srl (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MACUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(srl (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (srl (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MACHHUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(ushiftRound (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (ushiftRound (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MACURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(ushiftRound (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (ushiftRound (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_MACHHURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
 
   def : PatCoreVMacGprGprGpr<"mac", "MAC">;
@@ -864,7 +864,7 @@ multiclass PatCoreVAluGprGprImm <Intrinsic intr> {
 
 let Predicates = [HasExtXcvalu] in {
 
-  def : Pat<(abs GPR:$rs1), (CV_ABS GPR:$rs1)>;
+  def : PatGpr<abs, CV_ABS>;
   def : PatGprGpr<setle, CV_SLE>;
   def : PatGprGpr<setule, CV_SLEU>;
   def : PatGprGpr<smin, CV_MIN>;
@@ -874,52 +874,52 @@ let Predicates = [HasExtXcvalu] in {
 
   def : Pat<(sext_inreg GPR:$rs1, i16), (CV_EXTHS GPR:$rs1)>;
   def : Pat<(sext_inreg GPR:$rs1, i8), (CV_EXTBS GPR:$rs1)>;
-  def : Pat<(and GPR:$rs1, 0xffff), (CV_EXTHZ GPR:$rs1)>;
-  def : Pat<(and GPR:$rs1, 0xff), (CV_EXTBZ GPR:$rs1)>;
+  def : Pat<(XLenVT (and GPR:$rs1, 0xffff)), (CV_EXTHZ GPR:$rs1)>;
+  def : Pat<(XLenVT (and GPR:$rs1, 0xff)), (CV_EXTBZ GPR:$rs1)>;
 
   def : Pat<(clip powerOf2Minus1:$upperBound, GPR:$rs1),
             (CV_CLIP GPR:$rs1, (trailing1sPlus1 imm:$upperBound))>;
-  def : Pat<(between (not GPR:$rs2), GPR:$rs2, GPR:$rs1),
+  def : Pat<(XLenVT (between (not GPR:$rs2), GPR:$rs2, GPR:$rs1)),
             (CV_CLIPR GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(betweenu powerOf2Minus1:$upperBound, GPR:$rs1),
+  def : Pat<(XLenVT (betweenu powerOf2Minus1:$upperBound, GPR:$rs1)),
             (CV_CLIPU GPR:$rs1, (trailing1sPlus1 imm:$upperBound))>;
-  def : Pat<(betweenu GPR:$rs2, GPR:$rs1),
+  def : Pat<(XLenVT (betweenu GPR:$rs2, GPR:$rs1)),
             (CV_CLIPUR GPR:$rs1, GPR:$rs2)>;
 
-  def : Pat<(sra (add GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (sra (add GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_ADDN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(srl (add GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (srl (add GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_ADDUN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(shiftRound (add GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (shiftRound (add GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_ADDRN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(ushiftRound (add GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (ushiftRound (add GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_ADDURN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
 
-  def : Pat<(sra (sub GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (sra (sub GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_SUBN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(srl (sub GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (srl (sub GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_SUBUN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(shiftRound (sub GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (shiftRound (sub GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_SUBRN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
-  def : Pat<(ushiftRound (sub GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+  def : Pat<(XLenVT (ushiftRound (sub GPR:$rs1, GPR:$rs2), uimm5:$imm5)),
             (CV_SUBURN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
 
-  def : Pat<(sra (add GPR:$rd, GPR:$rs1), GPR:$rs2),
+  def : Pat<(XLenVT (sra (add GPR:$rd, GPR:$rs1), (XLenVT GPR:$rs2))),
             (CV_ADDNR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(srl (add GPR:$rd, GPR:$rs1), GPR:$rs2),
+  def : Pat<(XLenVT (srl (add GPR:$rd, GPR:$rs1), (XLenVT GPR:$rs2))),
             (CV_ADDUNR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(sra (add (add GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), GPR:$rs2),
+  def : Pat<(XLenVT (sra (add (add GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), (XLenVT GPR:$rs2))),
             (CV_ADDRNR  GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(srl (add (add GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), GPR:$rs2),
+  def : Pat<(XLenVT (srl (add (add GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), (XLenVT GPR:$rs2))),
             (CV_ADDURNR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
 
-  def : Pat<(sra (sub GPR:$rd, GPR:$rs1), GPR:$rs2),
+  def : Pat<(XLenVT (sra (sub GPR:$rd, GPR:$rs1), (XLenVT GPR:$rs2))),
             (CV_SUBNR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(srl (sub GPR:$rd, GPR:$rs1), GPR:$rs2),
+  def : Pat<(XLenVT (srl (sub GPR:$rd, GPR:$rs1), (XLenVT GPR:$rs2))),
             (CV_SUBUNR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(sra (add (sub GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), GPR:$rs2),
+  def : Pat<(XLenVT (sra (add (sub GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), (XLenVT GPR:$rs2))),
             (CV_SUBRNR  GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-  def : Pat<(srl (add (sub GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), GPR:$rs2),
+  def : Pat<(XLenVT (srl (add (sub GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), (XLenVT GPR:$rs2))),
             (CV_SUBURNR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
 
   def : PatCoreVAluGprGpr<"slet", "SLE">;
@@ -963,40 +963,40 @@ let Predicates = [HasExtXcvbi] in {
 
 let Predicates = [HasExtXcvmem, IsRV32] in {
 
-  def : Pat<(sextloadi8 (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(XLenVT (sextloadi8 (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset)))),
             (CV_LB_rr GPR:$base, GPR:$offset)>;
-  def : Pat<(zextloadi8 (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(XLenVT (zextloadi8 (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset)))),
             (CV_LBU_rr GPR:$base, GPR:$offset)>;
-  def : Pat<(extloadi8 (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(XLenVT (extloadi8 (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset)))),
             (CV_LBU_rr GPR:$base, GPR:$offset)>;
-  def : Pat<(sextloadi16 (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(XLenVT (sextloadi16 (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset)))),
             (CV_LH_rr GPR:$base, GPR:$offset)>;
-  def : Pat<(zextloadi16 (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(XLenVT (zextloadi16 (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset)))),
             (CV_LHU_rr GPR:$base, GPR:$offset)>;
-  def : Pat<(extloadi16 (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(XLenVT (extloadi16 (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset)))),
             (CV_LHU_rr GPR:$base, GPR:$offset)>;
-  def : Pat<(i32 (load (AddrRegReg GPR:$base, GPR:$offset))),
+  def : Pat<(XLenVT (i32 (load (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset))))),
             (CV_LW_rr GPR:$base, GPR:$offset)>;
 
-  def : Pat<(post_truncsti8 GPR:$val, GPR:$base, simm12:$offset),
+  def : Pat<(XLenVT (post_truncsti8 (XLenVT GPR:$val), (XLenVT GPR:$base), simm12:$offset)),
             (CV_SB_ri_inc GPR:$val, GPR:$base, simm12:$offset)>;
-  def : Pat<(post_truncsti16 GPR:$val, GPR:$base, simm12:$offset),
+  def : Pat<(XLenVT (post_truncsti16 (XLenVT GPR:$val), (XLenVT GPR:$base), simm12:$offset)),
             (CV_SH_ri_inc GPR:$val, GPR:$base, simm12:$offset)>;
-  def : Pat<(post_store (i32 GPR:$val), GPR:$base, simm12:$offset),
+  def : Pat<(XLenVT (post_store (i32 GPR:$val), (XLenVT GPR:$base), simm12:$offset)),
             (CV_SW_ri_inc GPR:$val, GPR:$base, simm12:$offset)>;
 
-  def : Pat<(post_truncsti8 GPR:$val, GPR:$base, GPR:$offset),
+  def : Pat<(XLenVT (post_truncsti8 (XLenVT GPR:$val), (XLenVT GPR:$base), (XLenVT GPR:$offset))),
             (CV_SB_rr_inc GPR:$val, GPR:$base, GPR:$offset)>;
-  def : Pat<(post_truncsti16 GPR:$val, GPR:$base, GPR:$offset),
+  def : Pat<(XLenVT (post_truncsti16 (XLenVT GPR:$val), (XLenVT GPR:$base), (XLenVT GPR:$offset))),
             (CV_SH_rr_inc GPR:$val, GPR:$base, GPR:$offset)>;
-  def : Pat<(post_store (i32 GPR:$val), GPR:$base, GPR:$offset),
+  def : Pat<(XLenVT (post_store (i32 GPR:$val), (XLenVT GPR:$base), (XLenVT GPR:$offset))),
             (CV_SW_rr_inc GPR:$val, GPR:$base, GPR:$offset)>;
 
-  def : Pat<(truncstorei8 GPR:$val, (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(truncstorei8 (XLenVT GPR:$val), (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset))),
             (CV_SB_rr GPR:$val, GPR:$base, GPR:$offset)>;
-  def : Pat<(truncstorei16 GPR:$val, (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(truncstorei16 (XLenVT GPR:$val), (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset))),
             (CV_SH_rr GPR:$val, GPR:$base, GPR:$offset)>;
-  def : Pat<(store (i32 GPR:$val), (AddrRegReg GPR:$base, GPR:$offset)),
+  def : Pat<(store (i32 GPR:$val), (AddrRegReg (XLenVT GPR:$base), (XLenVT GPR:$offset))),
             (CV_SW_rr GPR:$val, GPR:$base, GPR:$offset)>;
 
 }
@@ -1005,6 +1005,21 @@ let Predicates = [HasExtXcvmem, IsRV32] in {
 // Patterns for SIMD operations
 //===----------------------------------------------------------------------===//
 
+class PatCoreVBitConvert<ValueType DstVT, ValueType SrcVT,
+                       RegisterClass DstRC, RegisterClass SrcRC>
+    : Pat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
+          (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
+
+let Predicates = [HasExtXcvsimd, IsRV32] in {
+def : PatCoreVBitConvert<XLenVT,   XVEI8VT,  GPR, GPR>;
+def : PatCoreVBitConvert<XLenVT,   XVEI16VT, GPR, GPR>;
+def : PatCoreVBitConvert<XVEI8VT,  XLenVT,   GPR, GPR>;
+def : PatCoreVBitConvert<XVEI16VT, XLenVT,   GPR, GPR>;
+
+def : PatCoreVBitConvert<XVEI8VT,  XVEI16VT, GPR, GPR>;
+def : PatCoreVBitConvert<XVEI16VT, XVEI8VT,  GPR, GPR>;
+} // Predicates = [HasExtXcvsimd, IsRV32]
+
 class PatCorevGprGpr <string intr, string asm> :
   PatGprGpr<!cast<Intrinsic>("int_riscv_cv_simd_" # intr),
             !cast<RVInst>("CV_" # asm)>;
@@ -1197,8 +1212,14 @@ let Predicates = [HasExtXcvsimd, IsRV32] in {
 
   defm ADD : PatCorevGprGprDivAll<int_riscv_cv_simd_add_h>;
   defm SUB : PatCorevGprGprDivAll<int_riscv_cv_simd_sub_h>;
+
+def: Pat<(v4i8 (add v4i8:$Rs, v4i8:$Rt)), (CV_ADD_B XVEI8VT:$Rs, XVEI8VT:$Rt)>;
 }
 
+//===----------------------------------------------------------------------===//
+// Patterns for BitManip operations
+//===----------------------------------------------------------------------===//
+
 multiclass PatCoreVBitManip <Intrinsic intr> {
   def "CV_" # NAME # "_PSEUDO" : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, cv_uimm10:$imm), []>;
   def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
@@ -1228,9 +1249,13 @@ let Predicates = [HasExtXcvbitmanip, IsRV32] in {
             (CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;
 }
 
+//===----------------------------------------------------------------------===//
+// Patterns for Elw operations
+//===----------------------------------------------------------------------===//
+
 let Predicates = [HasExtXcvelw, IsRV32] in {
   def : Pat<(int_riscv_cv_elw_elw GPR:$rs1), (PseudoCV_ELW GPR:$rs1)>;
-  def : Pat<(int_riscv_cv_elw_elw (AddrRegImm GPR:$rs1, simm12:$imm12)),
+  def : Pat<(int_riscv_cv_elw_elw (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
             (CV_ELW GPR:$rs1, simm12:$imm12)>;
 }
 
@@ -1262,7 +1287,7 @@ def loop_decrement_32
 def : Pat<(riscv_brcc (i32 (and (loop_decrement_32), 1)), 0, SETNE, bb:$branchDest),
           (HwlpBranch 0, 0, bb:$branchDest)>;
 
-def : Pat<(int_set_loop_iterations GPR:$rs1),
+def : Pat<(int_set_loop_iterations (XLenVT GPR:$rs1)),
           (HwlpSetup GPR:$rs1)>;
 
 def : Pat<(int_set_loop_iterations uimm12:$rs1),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index c29e7352d829..0e3782b525af 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -272,7 +272,7 @@ def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
 def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
 
-def : PatFprFpr<fcopysign, FSGNJ_D, FPR64>;
+def : PatFprFpr<fcopysign, FSGNJ_D, FPR64, f64>;
 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;
 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
@@ -301,8 +301,8 @@ def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)),
 // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
 // LLVM's fminnum and fmaxnum.
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
-def : PatFprFpr<fminnum, FMIN_D, FPR64>;
-def : PatFprFpr<fmaxnum, FMAX_D, FPR64>;
+def : PatFprFpr<fminnum, FMIN_D, FPR64, f64>;
+def : PatFprFpr<fmaxnum, FMAX_D, FPR64, f64>;
 
 /// Setcc
 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
@@ -317,16 +317,16 @@ def : PatSetCC<FPR64, strict_fsetcc, SETLE, PseudoQuietFLE_D>;
 def : PatSetCC<FPR64, strict_fsetcc, SETOLE, PseudoQuietFLE_D>;
 
 // Match signaling FEQ_D
-def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)),
           (AND (FLE_D $rs1, $rs2),
                (FLE_D $rs2, $rs1))>;
-def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)),
           (AND (FLE_D $rs1, $rs2),
                (FLE_D $rs2, $rs1))>;
 // If both operands are the same, use a single FLE.
-def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)),
           (FLE_D $rs1, $rs1)>;
-def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ)),
           (FLE_D $rs1, $rs1)>;
 
 def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D>;
@@ -334,7 +334,7 @@ def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D>;
 def : PatSetCC<FPR64, any_fsetccs, SETLE, FLE_D>;
 def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D>;
 
-defm Select_FPR64 : SelectCC_GPR_rrirr<FPR64>;
+defm Select_FPR64 : SelectCC_GPR_rrirr<FPR64, f64>;
 
 /// Loads
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 655b44c6d0e3..069fecc8a021 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -471,12 +471,12 @@ def fpimm0    : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
 
 /// Generic pattern classes
-class PatSetCC<RegisterClass Ty, SDPatternOperator OpNode, CondCode Cond, RVInst Inst>
-    : Pat<(OpNode Ty:$rs1, Ty:$rs2, Cond), (Inst $rs1, $rs2)>;
+class PatSetCC<RegisterClass Ty, SDPatternOperator OpNode, CondCode Cond, RVInst Inst, ValueType vt = XLenVT>
+    : Pat<(vt (OpNode Ty:$rs1, Ty:$rs2, Cond)), (Inst $rs1, $rs2)>;
 
 class PatFprFpr<SDPatternOperator OpNode, RVInstR Inst,
-                RegisterClass RegTy>
-    : Pat<(OpNode RegTy:$rs1, RegTy:$rs2), (Inst $rs1, $rs2)>;
+                RegisterClass RegTy, ValueType Vt = XLenVT>
+    : Pat<(Vt (OpNode RegTy:$rs1, RegTy:$rs2)), (Inst $rs1, $rs2)>;
 
 class PatFprFprDynFrm<SDPatternOperator OpNode, RVInstRFrm Inst,
                       RegisterClass RegTy>
@@ -485,8 +485,8 @@ class PatFprFprDynFrm<SDPatternOperator OpNode, RVInstRFrm Inst,
 let Predicates = [HasStdExtF] in {
 
 /// Float constants
-def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
-def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X X0), (FMV_W_X X0))>;
+def : Pat<(f32 (fpimm0)), (FMV_W_X (XLenVT X0))>;
+def : Pat<(f32 (fpimmneg0)), (FSGNJN_S (FMV_W_X (XLenVT X0)), (FMV_W_X (XLenVT X0)))>;
 
 /// Float conversion operations
 
@@ -505,7 +505,7 @@ def : Pat<(any_fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
 def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
 def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
 
-def : PatFprFpr<fcopysign, FSGNJ_S, FPR32>;
+def : PatFprFpr<fcopysign, FSGNJ_S, FPR32, f32>;
 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
 
 // fmadd: rs1 * rs2 + rs3
@@ -531,8 +531,8 @@ def : Pat<(fneg (any_fma_nsz FPR32:$rs1, FPR32:$rs2, FPR32:$rs3)),
 // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
 // LLVM's fminnum and fmaxnum
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
-def : PatFprFpr<fminnum, FMIN_S, FPR32>;
-def : PatFprFpr<fmaxnum, FMAX_S, FPR32>;
+def : PatFprFpr<fminnum, FMIN_S, FPR32, f32>;
+def : PatFprFpr<fmaxnum, FMAX_S, FPR32, f32>;
 
 /// Setcc
 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
@@ -547,16 +547,16 @@ def : PatSetCC<FPR32, strict_fsetcc, SETLE, PseudoQuietFLE_S>;
 def : PatSetCC<FPR32, strict_fsetcc, SETOLE, PseudoQuietFLE_S>;
 
 // Match signaling FEQ_S
-def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ)),
           (AND (FLE_S $rs1, $rs2),
                (FLE_S $rs2, $rs1))>;
-def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ)),
           (AND (FLE_S $rs1, $rs2),
                (FLE_S $rs2, $rs1))>;
 // If both operands are the same, use a single FLE.
-def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ)),
           (FLE_S $rs1, $rs1)>;
-def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETOEQ)),
           (FLE_S $rs1, $rs1)>;
 
 def : PatSetCC<FPR32, any_fsetccs, SETLT, FLT_S>;
@@ -564,7 +564,7 @@ def : PatSetCC<FPR32, any_fsetccs, SETOLT, FLT_S>;
 def : PatSetCC<FPR32, any_fsetccs, SETLE, FLE_S>;
 def : PatSetCC<FPR32, any_fsetccs, SETOLE, FLE_S>;
 
-defm Select_FPR32 : SelectCC_GPR_rrirr<FPR32>;
+defm Select_FPR32 : SelectCC_GPR_rrirr<FPR32, f32>;
 
 /// Loads
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
index 662604b138d2..d381e20410bb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
@@ -102,7 +102,7 @@ def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
 // Although the sexti32 operands may not have originated from an i32 srem,
 // this pattern is safe as it is impossible for two sign extended inputs to
 // produce a result where res[63:32]=0 and res[31]=1.
-def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
+def : Pat<(i64 (srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2)))),
           (REMW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtM, IsRV64]
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 7c765dd3548b..b4899db21b97 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -14,7 +14,7 @@
 //===----------------------------------------------------------------------===//
 
 def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S",
-                           SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>,
+                           SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVec<1>,
                                                 SDTCisInt<1>]>>;
 def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB",
                               SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;
@@ -5649,7 +5649,7 @@ foreach fvti = AllFloatVectors in {
   def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1),
                          (fvti.Scalar (fpimm0)), VLOpFrag)),
             (!cast<Instruction>("PseudoVMV_S_X_" # fvti.LMul.MX)
-             (fvti.Vector $rs1), X0, GPR:$vl, fvti.Log2SEW)>;
+             (fvti.Vector $rs1), (XLenVT X0), GPR:$vl, fvti.Log2SEW)>;
 }
 } // Predicates = [HasVInstructionsAnyF]
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index fa731fcfffa8..6985b2e31eca 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -101,7 +101,7 @@ class VPatBinarySDNode_XI<SDNode vop,
                           DAGOperand xop_kind> :
     Pat<(result_type (vop
                      (vop_type vop_reg_class:$rs1),
-                     (vop_type (SplatPatKind xop_kind:$rs2)))),
+                     (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))))),
         (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX)
                      vop_reg_class:$rs1,
                      xop_kind:$rs2,
@@ -202,7 +202,7 @@ multiclass VPatIntegerSetCCSDNode_XI<
   foreach vti = AllIntegerVectors in {
     defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
     def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
-                               (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
+                               (vti.Vector (SplatPatKind (XLenVT xop_kind:$rs2))), cc)),
               (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
   }
 }
@@ -217,9 +217,9 @@ multiclass VPatIntegerSetCCSDNode_XI_Swappable<string instruction_name,
   foreach vti = AllIntegerVectors in {
     defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
     def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
-                               (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
+                               (vti.Vector (SplatPatKind (XLenVT xop_kind:$rs2))), cc)),
               (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
-    def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind xop_kind:$rs2)),
+    def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind (XLenVT xop_kind:$rs2))),
                                (vti.Vector vti.RegClass:$rs1), invcc)),
               (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
   }
@@ -349,7 +349,7 @@ multiclass VPatWidenBinarySDNode_VV_VX<SDNode op, PatFrags extop1, PatFrags exto
               (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
                  vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
     def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))),
-                  (wti.Vector (extop2 (vti.Vector (SplatPat GPR:$rs1))))),
+                  (wti.Vector (extop2 (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
               (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
                  vti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>;
   }
@@ -366,7 +366,7 @@ multiclass VPatWidenBinarySDNode_WV_WX<SDNode op, PatFrags extop,
                  wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW,
                  TAIL_AGNOSTIC)>;
     def : Pat<(op (wti.Vector wti.RegClass:$rs2),
-                  (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))),
+                  (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
               (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
                  wti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>;
   }
@@ -398,7 +398,7 @@ multiclass VPatWidenMulAddSDNode_VX<PatFrags extop1, PatFrags extop2, string ins
     defvar wti = vtiToWti.Wti;
     def : Pat<
       (add (wti.Vector wti.RegClass:$rd),
-        (mul_oneuse (wti.Vector (extop1 (vti.Vector (SplatPat GPR:$rs1)))),
+        (mul_oneuse (wti.Vector (extop1 (vti.Vector (SplatPat (XLenVT GPR:$rs1))))),
                     (wti.Vector (extop2 (vti.Vector vti.RegClass:$rs2))))),
       (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
         wti.RegClass:$rd, GPR:$rs1, vti.RegClass:$rs2,
@@ -633,7 +633,7 @@ defm : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
 // Handle VRSUB specially since it's the only integer binary op with reversed
 // pattern operands
 foreach vti = AllIntegerVectors in {
-  def : Pat<(sub (vti.Vector (SplatPat GPR:$rs2)),
+  def : Pat<(sub (vti.Vector (SplatPat (XLenVT GPR:$rs2))),
                  (vti.Vector vti.RegClass:$rs1)),
             (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
                  vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 3b6140a902e4..5ff1bdc3a628 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -865,7 +865,7 @@ multiclass VPatBinaryExtVL_WV_WX<SDNode op, PatFrags extop, string instruction_n
       (vti.Vector
         (riscv_trunc_vector_vl
           (op (wti.Vector wti.RegClass:$rs2),
-              (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))),
+              (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
           (vti.Mask true_mask),
           VLOpFrag)),
       (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
@@ -987,7 +987,7 @@ multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruct
       (vti.Vector
         (riscv_trunc_vector_vl
           (op (wti.Vector wti.RegClass:$rs2),
-              (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1)),
+              (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1))),
                                  (vti.Mask true_mask), VLOpFrag)),
           srcvalue, (wti.Mask true_mask), VLOpFrag),
         (vti.Mask true_mask), VLOpFrag)),
@@ -1889,7 +1889,7 @@ foreach vti = AllFloatVectors in {
                                            (vti.Scalar (fpimm0)),
                                            VLOpFrag)),
             (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
-                vti.RegClass:$merge, X0, GPR:$vl, vti.Log2SEW)>;
+                vti.RegClass:$merge, (XLenVT X0), GPR:$vl, vti.Log2SEW)>;
   def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
                                            vti.ScalarRegClass:$rs1,
                                            VLOpFrag)),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 50ecd8b8da99..1d7e20e0cbc0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -510,9 +510,9 @@ def : InstAlias<"bext $rd, $rs1, $shamt",
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZbbOrZbkb] in {
-def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>;
-def : Pat<(or  GPR:$rs1, (not GPR:$rs2)), (ORN  GPR:$rs1, GPR:$rs2)>;
-def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
+def : Pat<(XLenVT (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
+def : Pat<(XLenVT (or  GPR:$rs1, (not GPR:$rs2))), (ORN  GPR:$rs1, GPR:$rs2)>;
+def : Pat<(XLenVT (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbkb]
 
 let Predicates = [HasStdExtZbbOrZbkb] in {
@@ -522,7 +522,7 @@ def : PatGprGpr<shiftop<rotr>, ROR>;
 def : PatGprImm<rotr, RORI, uimmlog2xlen>;
 // There's no encoding for roli in the the 'B' extension as it can be
 // implemented with rori by negating the immediate.
-def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
+def : Pat<(XLenVT (rotl GPR:$rs1, uimmlog2xlen:$shamt)),
           (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
 } // Predicates = [HasStdExtZbbOrZbkb]
 
@@ -535,18 +535,18 @@ def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
 } // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
 
 let Predicates = [HasStdExtZbs] in {
-def : Pat<(and (not (shiftop<shl> 1, GPR:$rs2)), GPR:$rs1),
+def : Pat<(XLenVT (and (not (shiftop<shl> 1, (XLenVT GPR:$rs2))), GPR:$rs1)),
           (BCLR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (BCLR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(or (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
+def : Pat<(XLenVT (and (rotl -2, (XLenVT GPR:$rs2)), GPR:$rs1)), (BCLR GPR:$rs1, GPR:$rs2)>;
+def : Pat<(XLenVT (or (shiftop<shl> 1, (XLenVT GPR:$rs2)), GPR:$rs1)),
           (BSET GPR:$rs1, GPR:$rs2)>;
-def : Pat<(xor (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
+def : Pat<(XLenVT (xor (shiftop<shl> 1, (XLenVT GPR:$rs2)), GPR:$rs1)),
           (BINV GPR:$rs1, GPR:$rs2)>;
-def : Pat<(and (shiftop<srl> GPR:$rs1, GPR:$rs2), 1),
+def : Pat<(XLenVT (and (shiftop<srl> GPR:$rs1, (XLenVT GPR:$rs2)), 1)),
           (BEXT GPR:$rs1, GPR:$rs2)>;
 
-def : Pat<(shiftop<shl> 1, GPR:$rs2),
-          (BSET X0, GPR:$rs2)>;
+def : Pat<(XLenVT (shiftop<shl> 1, (XLenVT GPR:$rs2))),
+          (BSET (XLenVT X0), GPR:$rs2)>;
 
 def : Pat<(and GPR:$rs1, BCLRMask:$mask),
           (BCLRI GPR:$rs1, BCLRMask:$mask)>;
@@ -558,35 +558,35 @@ def : Pat<(xor GPR:$rs1, SingleBitSetMask:$mask),
 def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
           (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
 
-def : Pat<(seteq (and GPR:$rs1, SingleBitSetMask:$mask), 0),
+def : Pat<(XLenVT (seteq (and GPR:$rs1, SingleBitSetMask:$mask), 0)),
           (BEXTI (XORI GPR:$rs1, -1), SingleBitSetMask:$mask)>;
 
-def : Pat<(or GPR:$r, BSETINVTwoBitsMask:$i),
+def : Pat<(XLenVT (or GPR:$r, BSETINVTwoBitsMask:$i)),
           (BSETI (BSETI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
-def : Pat<(xor GPR:$r, BSETINVTwoBitsMask:$i),
+def : Pat<(XLenVT (xor GPR:$r, BSETINVTwoBitsMask:$i)),
           (BINVI (BINVI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
-def : Pat<(or GPR:$r, BSETINVORIMask:$i),
+def : Pat<(XLenVT (or GPR:$r, BSETINVORIMask:$i)),
           (BSETI (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
-def : Pat<(xor GPR:$r, BSETINVORIMask:$i),
+def : Pat<(XLenVT (xor GPR:$r, BSETINVORIMask:$i)),
           (BINVI (XORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVORIMask:$i))>;
-def : Pat<(and GPR:$r, BCLRITwoBitsMask:$i),
+def : Pat<(XLenVT (and GPR:$r, BCLRITwoBitsMask:$i)),
           (BCLRI (BCLRI GPR:$r, (BCLRITwoBitsMaskLow BCLRITwoBitsMask:$i)),
                  (BCLRITwoBitsMaskHigh BCLRITwoBitsMask:$i))>;
-def : Pat<(and GPR:$r, BCLRIANDIMask:$i),
+def : Pat<(XLenVT (and GPR:$r, BCLRIANDIMask:$i)),
           (BCLRI (ANDI GPR:$r, (BCLRIANDIMaskLow BCLRIANDIMask:$i)),
                  (BCLRITwoBitsMaskHigh BCLRIANDIMask:$i))>;
 } // Predicates = [HasStdExtZbs]
 
 let Predicates = [HasStdExtZbb] in {
-def : Pat<(riscv_orc_b GPR:$rs1), (ORC_B GPR:$rs1)>;
+def : Pat<(XLenVT (riscv_orc_b GPR:$rs1)), (ORC_B GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb]
 
 let Predicates = [HasStdExtZbkb] in {
-def : Pat<(riscv_brev8 GPR:$rs1), (BREV8 GPR:$rs1)>;
+def : Pat<(XLenVT (riscv_brev8 GPR:$rs1)), (BREV8 GPR:$rs1)>;
 } // Predicates = [HasStdExtZbkb]
 
 let Predicates = [HasStdExtZbkb, IsRV32] in {
@@ -628,11 +628,11 @@ def : Pat<(i64 (bswap GPR:$rs1)), (REV8_RV64 GPR:$rs1)>;
 } // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
 
 let Predicates = [HasStdExtZbkb] in {
-def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
-              (and GPR:$rs1, 0x00FF)),
+def : Pat<(XLenVT (or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
+              (and GPR:$rs1, 0x00FF))),
           (PACKH GPR:$rs1, GPR:$rs2)>;
-def : Pat<(or (shl (and GPR:$rs2, 0x00FF), (XLenVT 8)),
-              (and GPR:$rs1, 0x00FF)),
+def : Pat<(XLenVT (or (shl (and GPR:$rs2, 0x00FF), (XLenVT 8)),
+              (and GPR:$rs1, 0x00FF))),
           (PACKH GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbkb]
 
@@ -693,20 +693,20 @@ def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
           (SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 
-def : Pat<(add GPR:$r, CSImm12MulBy4:$i),
-          (SH2ADD (ADDI X0, (SimmShiftRightBy2XForm CSImm12MulBy4:$i)),
+def : Pat<(XLenVT (add GPR:$r, CSImm12MulBy4:$i)),
+          (SH2ADD (ADDI (XLenVT X0), (SimmShiftRightBy2XForm CSImm12MulBy4:$i)),
                   GPR:$r)>;
-def : Pat<(add GPR:$r, CSImm12MulBy8:$i),
-          (SH3ADD (ADDI X0, (SimmShiftRightBy3XForm CSImm12MulBy8:$i)),
+def : Pat<(XLenVT (add GPR:$r, CSImm12MulBy8:$i)),
+          (SH3ADD (ADDI (XLenVT X0), (SimmShiftRightBy3XForm CSImm12MulBy8:$i)),
                   GPR:$r)>;
 
-def : Pat<(mul GPR:$r, C3LeftShift:$i),
+def : Pat<(XLenVT (mul GPR:$r, C3LeftShift:$i)),
           (SLLI (SH1ADD GPR:$r, GPR:$r),
                 (TrailingZerosXForm C3LeftShift:$i))>;
-def : Pat<(mul GPR:$r, C5LeftShift:$i),
+def : Pat<(XLenVT (mul GPR:$r, C5LeftShift:$i)),
           (SLLI (SH2ADD GPR:$r, GPR:$r),
                 (TrailingZerosXForm C5LeftShift:$i))>;
-def : Pat<(mul GPR:$r, C9LeftShift:$i),
+def : Pat<(XLenVT (mul GPR:$r, C9LeftShift:$i)),
           (SLLI (SH3ADD GPR:$r, GPR:$r),
                 (TrailingZerosXForm C9LeftShift:$i))>;
 
@@ -739,7 +739,7 @@ def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)),
           (SLLI_UW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(i64 (add (and GPR:$rs1, 0xFFFFFFFF), non_imm12:$rs2)),
           (ADD_UW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADD_UW GPR:$rs, X0)>;
+def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADD_UW GPR:$rs, (XLenVT X0))>;
 
 def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 1)), non_imm12:$rs2)),
           (SH1ADD_UW GPR:$rs1, GPR:$rs2)>;
@@ -770,13 +770,13 @@ def : Pat<(i64 (add (and GPR:$rs1, 0x3FFFFFFFC), non_imm12:$rs2)),
 def : Pat<(i64 (add (and GPR:$rs1, 0x7FFFFFFF8), non_imm12:$rs2)),
           (SH3ADD_UW (SRLI GPR:$rs1, 3), GPR:$rs2)>;
 
-def : Pat<(mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C3LeftShiftUW:$i),
+def : Pat<(XLenVT (mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C3LeftShiftUW:$i)),
           (SH1ADD (SLLI_UW GPR:$r, (TrailingZerosXForm C3LeftShiftUW:$i)),
                   (SLLI_UW GPR:$r, (TrailingZerosXForm C3LeftShiftUW:$i)))>;
-def : Pat<(mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C5LeftShiftUW:$i),
+def : Pat<(XLenVT (mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C5LeftShiftUW:$i)),
           (SH2ADD (SLLI_UW GPR:$r, (TrailingZerosXForm C5LeftShiftUW:$i)),
                   (SLLI_UW GPR:$r, (TrailingZerosXForm C5LeftShiftUW:$i)))>;
-def : Pat<(mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C9LeftShiftUW:$i),
+def : Pat<(XLenVT (mul (binop_oneuse<and> GPR:$r, 0xFFFFFFFF), C9LeftShiftUW:$i)),
           (SH3ADD (SLLI_UW GPR:$r, (TrailingZerosXForm C9LeftShiftUW:$i)),
                   (SLLI_UW GPR:$r, (TrailingZerosXForm C9LeftShiftUW:$i)))>;
 } // Predicates = [HasStdExtZba, IsRV64]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index ba1348a1f669..242abcb4c877 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -254,8 +254,8 @@ def : InstAlias<"fge.h $rd, $rs, $rt",
 let Predicates = [HasStdExtZfh] in {
 
 /// Float constants
-def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>;
-def : Pat<(f16 (fpimmneg0)), (FSGNJN_H (FMV_H_X X0), (FMV_H_X X0))>;
+def : Pat<(f16 (fpimm0)), (FMV_H_X (XLenVT X0))>;
+def : Pat<(f16 (fpimmneg0)), (FSGNJN_H (FMV_H_X (XLenVT X0)), (FMV_H_X (XLenVT X0)))>;
 
 /// Float conversion operations
 
@@ -274,7 +274,7 @@ def : Pat<(any_fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>;
 def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>;
 def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>;
 
-def : PatFprFpr<fcopysign, FSGNJ_H, FPR16>;
+def : PatFprFpr<fcopysign, FSGNJ_H, FPR16, f16>;
 def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>;
 def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2),
           (FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>;
@@ -303,8 +303,8 @@ def : Pat<(fneg (any_fma_nsz FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)),
 // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
 // LLVM's fminnum and fmaxnum
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
-def : PatFprFpr<fminnum, FMIN_H, FPR16>;
-def : PatFprFpr<fmaxnum, FMAX_H, FPR16>;
+def : PatFprFpr<fminnum, FMIN_H, FPR16, f16>;
+def : PatFprFpr<fmaxnum, FMAX_H, FPR16, f16>;
 
 /// Setcc
 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
@@ -319,16 +319,16 @@ def : PatSetCC<FPR16, strict_fsetcc, SETLE, PseudoQuietFLE_H>;
 def : PatSetCC<FPR16, strict_fsetcc, SETOLE, PseudoQuietFLE_H>;
 
 // Match signaling FEQ_H
-def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETEQ)),
           (AND (FLE_H $rs1, $rs2),
                (FLE_H $rs2, $rs1))>;
-def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETOEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETOEQ)),
           (AND (FLE_H $rs1, $rs2),
                (FLE_H $rs2, $rs1))>;
 // If both operands are the same, use a single FLE.
-def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETEQ)),
           (FLE_H $rs1, $rs1)>;
-def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETOEQ),
+def : Pat<(XLenVT (strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETOEQ)),
           (FLE_H $rs1, $rs1)>;
 
 def : PatSetCC<FPR16, any_fsetccs, SETLT, FLT_H>;
@@ -336,7 +336,7 @@ def : PatSetCC<FPR16, any_fsetccs, SETOLT, FLT_H>;
 def : PatSetCC<FPR16, any_fsetccs, SETLE, FLE_H>;
 def : PatSetCC<FPR16, any_fsetccs, SETOLE, FLE_H>;
 
-defm Select_FPR16 : SelectCC_GPR_rrirr<FPR16>;
+defm Select_FPR16 : SelectCC_GPR_rrirr<FPR16, f16>;
 } // Predicates = [HasStdExtZfh]
 
 let Predicates = [HasStdExtZfhOrZfhmin] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
index e4e07f4789a6..9e02759a589d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
@@ -134,7 +134,7 @@ def SM3P1 : RVKUnary<0b000100001001, 0b001, "sm3p1">;
 //===----------------------------------------------------------------------===//
 
 class PatGprGprByteSelect<SDPatternOperator OpNode, RVInst Inst>
-    : Pat<(OpNode GPR:$rs1, GPR:$rs2, i8:$imm),
+    : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), (XLenVT GPR:$rs2), i8:$imm)),
           (Inst GPR:$rs1, GPR:$rs2, byteselect:$imm)>;
 
 // Zknd
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 78252493449f..13804da9c89c 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -118,13 +118,23 @@ let RegAltNameIndices = [ABIRegAltName] in {
 
 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
                                [i32,  i64]>;
+
+def XVEI8VT : ValueTypeByHwMode<[RV32, RV64],
+                                [v4i8, v8i8]>;
+
+def XVEI16VT : ValueTypeByHwMode<[RV32,  RV64],
+                                 [v2i16, v4i16]>;
+
+def XVEI32VT : ValueTypeByHwMode<[RV32,  RV64],
+                                 [i32, v2i32]>;
+
 def XLenRI : RegInfoByHwMode<
       [RV32,              RV64],
       [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
 
 // The order of registers represents the preferred allocation sequence.
 // Registers are listed in the order caller-save, callee-save, specials.
-def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
+def GPR : RegisterClass<"RISCV", [XLenVT, XVEI8VT, XVEI16VT, XVEI32VT], 32, (add
     (sequence "X%u", 10, 17),
     (sequence "X%u", 5, 7),
     (sequence "X%u", 28, 31),
diff --git a/llvm/test/CodeGen/RISCV/corev/simd.ll b/llvm/test/CodeGen/RISCV/corev/simd.ll
index df164dee2dc0..945dec9fb183 100644
--- a/llvm/test/CodeGen/RISCV/corev/simd.ll
+++ b/llvm/test/CodeGen/RISCV/corev/simd.ll
@@ -1,6 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O0 -mtriple=riscv32 -mattr=+m -mattr=+xcvsimd -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
+
+define <4 x i8> @vadd_simd_v4i8(<4 x i8> %a, <4 x i8> %b) {
+; CHECK-LABEL: vadd_simd_v4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.add.b a0, a0, a1
+; CHECK-NEXT:    ret
+  %v = add <4 x i8> %a, %b;
+  ret <4 x i8> %v
+}
+
 declare i32 @llvm.riscv.cv.simd.add.h(i32, i32, i32)
 
 define i32 @test.cv.add.h(i32 %a, i32 %b) {