diff --git a/.gitignore b/.gitignore index befa90f..53e61e7 100644 --- a/.gitignore +++ b/.gitignore @@ -2,17 +2,6 @@ llvm-project/* veir/* xdsl/* build/* -benchmarks/LLC_ASM_globalisel -benchmarks/LLC_ASM_selectiondag -benchmarks/LLVM -benchmarks/LLVMIR -benchmarks/logs -benchmarks/MLIR_bb0 -benchmarks/MLIR_bb0_veir -benchmarks/MLIR_multi -benchmarks/MLIR_single -benchmarks/VEIR_ASM -benchmarks/XDSL_FUNC -benchmarks/XDSL_ASM + mca-analysis/results .lake/ \ No newline at end of file diff --git a/benchmarks/LLC_ASM_globalisel/3_function_0.s b/benchmarks/LLC_ASM_globalisel/3_function_0.s new file mode 100644 index 0000000..d822e25 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_0.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_1.s b/benchmarks/LLC_ASM_globalisel/3_function_1.s new file mode 100644 index 0000000..6cc015c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_1.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + remu a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_10.s b/benchmarks/LLC_ASM_globalisel/3_function_10.s new file mode 100644 index 0000000..87fe679 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_10.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_11.s b/benchmarks/LLC_ASM_globalisel/3_function_11.s new file mode 100644 index 0000000..07455d0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_11.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_12.s b/benchmarks/LLC_ASM_globalisel/3_function_12.s new file mode 100644 index 0000000..dff9083 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_12.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a1 + srl a0, a0, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_13.s b/benchmarks/LLC_ASM_globalisel/3_function_13.s new file mode 100644 index 0000000..58941d5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_13.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a1, a2 + and a1, a1, a2 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_14.s b/benchmarks/LLC_ASM_globalisel/3_function_14.s new file mode 100644 index 0000000..c1611e6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_14.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + rem a0, a2, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_15.s b/benchmarks/LLC_ASM_globalisel/3_function_15.s new file mode 100644 index 0000000..6256a1b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_15.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_16.s b/benchmarks/LLC_ASM_globalisel/3_function_16.s new file mode 100644 index 0000000..5e3d22c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_16.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, zero + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_17.s b/benchmarks/LLC_ASM_globalisel/3_function_17.s new file mode 100644 index 0000000..316e745 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_17.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + and a1, a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_18.s b/benchmarks/LLC_ASM_globalisel/3_function_18.s new file mode 100644 index 0000000..674ae91 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_18.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_19.s b/benchmarks/LLC_ASM_globalisel/3_function_19.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_19.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_2.s b/benchmarks/LLC_ASM_globalisel/3_function_2.s new file mode 100644 index 0000000..de95d3a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_2.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_20.s b/benchmarks/LLC_ASM_globalisel/3_function_20.s new file mode 100644 index 0000000..a64ad53 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_20.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_21.s b/benchmarks/LLC_ASM_globalisel/3_function_21.s new file mode 100644 index 0000000..f703d96 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_21.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + xor a0, a0, a1 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_22.s b/benchmarks/LLC_ASM_globalisel/3_function_22.s new file mode 100644 index 0000000..b9dc370 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_22.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_23.s b/benchmarks/LLC_ASM_globalisel/3_function_23.s new file mode 100644 index 0000000..d99e16f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_23.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + andi a3, a3, 1 + beqz a3, .LBB0_2 +# %bb.1: + or a0, a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_24.s b/benchmarks/LLC_ASM_globalisel/3_function_24.s new file mode 100644 index 0000000..290c4eb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_24.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + mv a0, a1 + bnez a2, .LBB0_2 +# %bb.1: + sext.w a0, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_25.s b/benchmarks/LLC_ASM_globalisel/3_function_25.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_25.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_26.s b/benchmarks/LLC_ASM_globalisel/3_function_26.s new file mode 100644 index 0000000..bcd6682 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_26.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a0 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_27.s b/benchmarks/LLC_ASM_globalisel/3_function_27.s new file mode 100644 index 0000000..675ce1f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_27.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_28.s b/benchmarks/LLC_ASM_globalisel/3_function_28.s new file mode 100644 index 0000000..a49ecec --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_28.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + or a1, a2, a1 +.LBB0_2: + xor a1, a1, a2 + seqz a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_29.s b/benchmarks/LLC_ASM_globalisel/3_function_29.s new file mode 100644 index 0000000..fbde7a2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_29.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_3.s b/benchmarks/LLC_ASM_globalisel/3_function_3.s new file mode 100644 index 0000000..1b01486 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_3.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + xor a2, a0, a2 + slt a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_30.s b/benchmarks/LLC_ASM_globalisel/3_function_30.s new file mode 100644 index 0000000..c7ce435 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_30.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + or a1, a0, a1 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_31.s b/benchmarks/LLC_ASM_globalisel/3_function_31.s new file mode 100644 index 0000000..22d8d77 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_31.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_32.s b/benchmarks/LLC_ASM_globalisel/3_function_32.s new file mode 100644 index 0000000..b05c66a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_32.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_33.s b/benchmarks/LLC_ASM_globalisel/3_function_33.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_33.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_34.s b/benchmarks/LLC_ASM_globalisel/3_function_34.s new file mode 100644 index 0000000..33ff17b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_34.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + div a1, a0, a0 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_35.s b/benchmarks/LLC_ASM_globalisel/3_function_35.s new file mode 100644 index 0000000..7f50d5e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_35.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + xor a1, a1, a2 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_36.s b/benchmarks/LLC_ASM_globalisel/3_function_36.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_36.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_37.s b/benchmarks/LLC_ASM_globalisel/3_function_37.s new file mode 100644 index 0000000..1de9989 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_37.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_38.s b/benchmarks/LLC_ASM_globalisel/3_function_38.s new file mode 100644 index 0000000..2027781 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_38.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + slt a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_39.s b/benchmarks/LLC_ASM_globalisel/3_function_39.s new file mode 100644 index 0000000..759a8c6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_39.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + andi a3, a3, 1 + bnez a3, .LBB0_2 +# %bb.1: + rem a0, a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_4.s b/benchmarks/LLC_ASM_globalisel/3_function_4.s new file mode 100644 index 0000000..f790059 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_4.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_40.s b/benchmarks/LLC_ASM_globalisel/3_function_40.s new file mode 100644 index 0000000..4258a8b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_40.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_41.s b/benchmarks/LLC_ASM_globalisel/3_function_41.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_41.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_42.s b/benchmarks/LLC_ASM_globalisel/3_function_42.s new file mode 100644 index 0000000..7fdc11e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_42.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_43.s b/benchmarks/LLC_ASM_globalisel/3_function_43.s new file mode 100644 index 0000000..23f295d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_43.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_44.s b/benchmarks/LLC_ASM_globalisel/3_function_44.s new file mode 100644 index 0000000..148391c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_44.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + sra a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_45.s b/benchmarks/LLC_ASM_globalisel/3_function_45.s new file mode 100644 index 0000000..ad6ce64 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_45.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a0 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_46.s b/benchmarks/LLC_ASM_globalisel/3_function_46.s new file mode 100644 index 0000000..047aa2e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_46.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + div a1, a2, a0 + xor a0, a0, a1 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_47.s b/benchmarks/LLC_ASM_globalisel/3_function_47.s new file mode 100644 index 0000000..d146647 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_47.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + div a1, a2, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_48.s b/benchmarks/LLC_ASM_globalisel/3_function_48.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_48.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_49.s b/benchmarks/LLC_ASM_globalisel/3_function_49.s new file mode 100644 index 0000000..e701cb4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_49.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a0 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_5.s b/benchmarks/LLC_ASM_globalisel/3_function_5.s new file mode 100644 index 0000000..c2132b2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_5.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a1, a2 + sra a0, a0, a2 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_50.s b/benchmarks/LLC_ASM_globalisel/3_function_50.s new file mode 100644 index 0000000..8d945dc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_50.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a0 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_51.s b/benchmarks/LLC_ASM_globalisel/3_function_51.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_51.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_52.s b/benchmarks/LLC_ASM_globalisel/3_function_52.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_52.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_53.s b/benchmarks/LLC_ASM_globalisel/3_function_53.s new file mode 100644 index 0000000..7f4aa0d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_53.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a0 + rem a0, a0, a2 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_54.s b/benchmarks/LLC_ASM_globalisel/3_function_54.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_54.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_55.s b/benchmarks/LLC_ASM_globalisel/3_function_55.s new file mode 100644 index 0000000..fac631f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_55.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_56.s b/benchmarks/LLC_ASM_globalisel/3_function_56.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_56.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_57.s b/benchmarks/LLC_ASM_globalisel/3_function_57.s new file mode 100644 index 0000000..4d90986 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_57.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sltu a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_58.s b/benchmarks/LLC_ASM_globalisel/3_function_58.s new file mode 100644 index 0000000..c33c4bc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_58.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_59.s b/benchmarks/LLC_ASM_globalisel/3_function_59.s new file mode 100644 index 0000000..6bc3076 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_59.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a1, a0 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_6.s b/benchmarks/LLC_ASM_globalisel/3_function_6.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_6.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_60.s b/benchmarks/LLC_ASM_globalisel/3_function_60.s new file mode 100644 index 0000000..46b1bad --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_60.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a0 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_61.s b/benchmarks/LLC_ASM_globalisel/3_function_61.s new file mode 100644 index 0000000..6c63c83 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_61.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a0, a0 + div a0, a0, a2 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_62.s b/benchmarks/LLC_ASM_globalisel/3_function_62.s new file mode 100644 index 0000000..add291d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_62.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a0 + srl a1, a0, a1 + remu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_63.s b/benchmarks/LLC_ASM_globalisel/3_function_63.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_63.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_64.s b/benchmarks/LLC_ASM_globalisel/3_function_64.s new file mode 100644 index 0000000..5dfa822 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_64.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a0 + sra a1, a0, a1 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_65.s b/benchmarks/LLC_ASM_globalisel/3_function_65.s new file mode 100644 index 0000000..467c277 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_65.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_66.s b/benchmarks/LLC_ASM_globalisel/3_function_66.s new file mode 100644 index 0000000..d6333ad --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_66.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_67.s b/benchmarks/LLC_ASM_globalisel/3_function_67.s new file mode 100644 index 0000000..cbf2456 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_67.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + or a1, a1, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_68.s b/benchmarks/LLC_ASM_globalisel/3_function_68.s new file mode 100644 index 0000000..a709765 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_68.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_69.s b/benchmarks/LLC_ASM_globalisel/3_function_69.s new file mode 100644 index 0000000..ee838e1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_69.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + xor a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_7.s b/benchmarks/LLC_ASM_globalisel/3_function_7.s new file mode 100644 index 0000000..0e5662b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_7.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a2 + srl a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_70.s b/benchmarks/LLC_ASM_globalisel/3_function_70.s new file mode 100644 index 0000000..9a0b92f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_70.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_71.s b/benchmarks/LLC_ASM_globalisel/3_function_71.s new file mode 100644 index 0000000..8d1b610 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_71.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remw a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_72.s b/benchmarks/LLC_ASM_globalisel/3_function_72.s new file mode 100644 index 0000000..3b9a86c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_72.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sgtz a0, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_73.s b/benchmarks/LLC_ASM_globalisel/3_function_73.s new file mode 100644 index 0000000..b6f393c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_73.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_74.s b/benchmarks/LLC_ASM_globalisel/3_function_74.s new file mode 100644 index 0000000..2061c9b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_74.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_75.s b/benchmarks/LLC_ASM_globalisel/3_function_75.s new file mode 100644 index 0000000..95bb821 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_75.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a0 + sra a1, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_76.s b/benchmarks/LLC_ASM_globalisel/3_function_76.s new file mode 100644 index 0000000..f47aca4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_76.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_77.s b/benchmarks/LLC_ASM_globalisel/3_function_77.s new file mode 100644 index 0000000..de083f8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_77.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a0 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_78.s b/benchmarks/LLC_ASM_globalisel/3_function_78.s new file mode 100644 index 0000000..6278291 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_78.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_79.s b/benchmarks/LLC_ASM_globalisel/3_function_79.s new file mode 100644 index 0000000..2cf5c90 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_79.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_8.s b/benchmarks/LLC_ASM_globalisel/3_function_8.s new file mode 100644 index 0000000..5dfbe69 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_8.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a0 + xor a1, a1, a2 + slt a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_80.s b/benchmarks/LLC_ASM_globalisel/3_function_80.s new file mode 100644 index 0000000..dadfe0a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_80.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + div a0, a0, a0 + slt a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_81.s b/benchmarks/LLC_ASM_globalisel/3_function_81.s new file mode 100644 index 0000000..1939fb5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_81.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bge a0, a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_82.s b/benchmarks/LLC_ASM_globalisel/3_function_82.s new file mode 100644 index 0000000..869b645 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_82.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_83.s b/benchmarks/LLC_ASM_globalisel/3_function_83.s new file mode 100644 index 0000000..7720494 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_83.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + bgeu a1, a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_84.s b/benchmarks/LLC_ASM_globalisel/3_function_84.s new file mode 100644 index 0000000..bd910af --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_84.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_85.s b/benchmarks/LLC_ASM_globalisel/3_function_85.s new file mode 100644 index 0000000..1ce9dbb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_85.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_86.s b/benchmarks/LLC_ASM_globalisel/3_function_86.s new file mode 100644 index 0000000..d11ed63 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_86.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + andi a3, a3, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_87.s b/benchmarks/LLC_ASM_globalisel/3_function_87.s new file mode 100644 index 0000000..eb1ebcf --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_87.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bltu a1, a0, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_88.s b/benchmarks/LLC_ASM_globalisel/3_function_88.s new file mode 100644 index 0000000..a10e5ff --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_88.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + divu a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_89.s b/benchmarks/LLC_ASM_globalisel/3_function_89.s new file mode 100644 index 0000000..0184ec1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_89.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + zext.w a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_9.s b/benchmarks/LLC_ASM_globalisel/3_function_9.s new file mode 100644 index 0000000..7eeda0a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_9.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + slt a0, a0, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_90.s b/benchmarks/LLC_ASM_globalisel/3_function_90.s new file mode 100644 index 0000000..65bc253 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_90.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_91.s b/benchmarks/LLC_ASM_globalisel/3_function_91.s new file mode 100644 index 0000000..11d4bc5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_91.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_92.s b/benchmarks/LLC_ASM_globalisel/3_function_92.s new file mode 100644 index 0000000..c7833b8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_92.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a0 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_93.s b/benchmarks/LLC_ASM_globalisel/3_function_93.s new file mode 100644 index 0000000..9b55a2b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_93.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bgeu a1, a0, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + slt a0, a0, a2 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_94.s b/benchmarks/LLC_ASM_globalisel/3_function_94.s new file mode 100644 index 0000000..2c5c07d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_94.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_95.s b/benchmarks/LLC_ASM_globalisel/3_function_95.s new file mode 100644 index 0000000..ff86cf2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_95.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a1, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_96.s b/benchmarks/LLC_ASM_globalisel/3_function_96.s new file mode 100644 index 0000000..455de36 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_96.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + sext.w a2, a2 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_97.s b/benchmarks/LLC_ASM_globalisel/3_function_97.s new file mode 100644 index 0000000..156f803 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_97.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + bnez a2, .LBB0_2 +# %bb.1: + or a0, a1, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_98.s b/benchmarks/LLC_ASM_globalisel/3_function_98.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_98.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/3_function_99.s b/benchmarks/LLC_ASM_globalisel/3_function_99.s new file mode 100644 index 0000000..0d84ef4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/3_function_99.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a1, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_0.s b/benchmarks/LLC_ASM_globalisel/4_function_0.s new file mode 100644 index 0000000..d3d2da6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_0.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + and a0, a0, a1 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_1.s b/benchmarks/LLC_ASM_globalisel/4_function_1.s new file mode 100644 index 0000000..9d26414 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_1.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_10.s b/benchmarks/LLC_ASM_globalisel/4_function_10.s new file mode 100644 index 0000000..18d4056 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_10.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_11.s b/benchmarks/LLC_ASM_globalisel/4_function_11.s new file mode 100644 index 0000000..bb85664 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_11.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_12.s b/benchmarks/LLC_ASM_globalisel/4_function_12.s new file mode 100644 index 0000000..5b60342 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_12.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_13.s b/benchmarks/LLC_ASM_globalisel/4_function_13.s new file mode 100644 index 0000000..e0b8044 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_13.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a0 + sext.w a1, a1 + sltu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_14.s b/benchmarks/LLC_ASM_globalisel/4_function_14.s new file mode 100644 index 0000000..c594503 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_14.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + remu a0, a0, a1 + divu a0, a2, a0 + remu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_15.s b/benchmarks/LLC_ASM_globalisel/4_function_15.s new file mode 100644 index 0000000..2ee8e28 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_15.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_16.s b/benchmarks/LLC_ASM_globalisel/4_function_16.s new file mode 100644 index 0000000..8cb8596 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_16.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + xor a1, a0, a1 + rem a0, a1, a0 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_17.s b/benchmarks/LLC_ASM_globalisel/4_function_17.s new file mode 100644 index 0000000..09c4acc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_17.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + sext.w a2, a2 + divu a0, a2, a1 +.LBB0_2: + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_18.s b/benchmarks/LLC_ASM_globalisel/4_function_18.s new file mode 100644 index 0000000..9dee7ce --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_18.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_19.s b/benchmarks/LLC_ASM_globalisel/4_function_19.s new file mode 100644 index 0000000..11ef7f8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_19.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_2.s b/benchmarks/LLC_ASM_globalisel/4_function_2.s new file mode 100644 index 0000000..afdca11 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_2.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_20.s b/benchmarks/LLC_ASM_globalisel/4_function_20.s new file mode 100644 index 0000000..e550875 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_20.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a1, 1 + li a1, 0 + bnez a2, .LBB0_2 +# %bb.1: + zext.w a1, a3 +.LBB0_2: + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_21.s b/benchmarks/LLC_ASM_globalisel/4_function_21.s new file mode 100644 index 0000000..ef5124f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_21.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a1, a1 + divu a2, a2, a3 + sra a1, a1, a2 + slt a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_22.s b/benchmarks/LLC_ASM_globalisel/4_function_22.s new file mode 100644 index 0000000..9568a56 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_22.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + srl a0, a0, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_23.s b/benchmarks/LLC_ASM_globalisel/4_function_23.s new file mode 100644 index 0000000..b2096da --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_23.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + sext.w a0, a0 + or a1, a1, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_24.s b/benchmarks/LLC_ASM_globalisel/4_function_24.s new file mode 100644 index 0000000..49f2724 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_24.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a0, a0 + rem a0, a3, a1 + andi a1, a0, 1 + mv a0, a2 + bnez a1, .LBB0_2 +# %bb.1: + mv a0, a3 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_25.s b/benchmarks/LLC_ASM_globalisel/4_function_25.s new file mode 100644 index 0000000..b0df429 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_25.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + beqz a1, .LBB0_2 +# %bb.1: + sra a2, a0, a2 +.LBB0_2: + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_26.s b/benchmarks/LLC_ASM_globalisel/4_function_26.s new file mode 100644 index 0000000..9400254 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_26.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + beqz a3, .LBB0_3 +# %bb.1: + bne a0, a2, .LBB0_4 +.LBB0_2: + xor a0, a0, a2 + ret +.LBB0_3: + mv a0, a2 + beq a2, a2, .LBB0_2 +.LBB0_4: + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_27.s b/benchmarks/LLC_ASM_globalisel/4_function_27.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_27.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_28.s b/benchmarks/LLC_ASM_globalisel/4_function_28.s new file mode 100644 index 0000000..328c5e1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_28.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a1 + zext.w a0, a0 + or a1, a0, a1 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_29.s b/benchmarks/LLC_ASM_globalisel/4_function_29.s new file mode 100644 index 0000000..b874e8a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_29.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a2 + rem a1, a0, a1 + xor a0, a1, a0 + slt a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_3.s b/benchmarks/LLC_ASM_globalisel/4_function_3.s new file mode 100644 index 0000000..68a2a54 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_3.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + andi a3, a2, 1 + mv a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + srl a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_30.s b/benchmarks/LLC_ASM_globalisel/4_function_30.s new file mode 100644 index 0000000..e066583 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_30.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + sext.w a0, a0 + sltu a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_31.s b/benchmarks/LLC_ASM_globalisel/4_function_31.s new file mode 100644 index 0000000..4dc8bd2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_31.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + sra a0, a0, a2 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_32.s b/benchmarks/LLC_ASM_globalisel/4_function_32.s new file mode 100644 index 0000000..c66e1a7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_32.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + remu a0, a0, a0 + ret +.LBB0_2: + sext.w a2, a2 + remu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_33.s b/benchmarks/LLC_ASM_globalisel/4_function_33.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_33.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_34.s b/benchmarks/LLC_ASM_globalisel/4_function_34.s new file mode 100644 index 0000000..14f86ec --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_34.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a0 + sra a1, a0, a1 + or a1, a0, a1 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_35.s b/benchmarks/LLC_ASM_globalisel/4_function_35.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_35.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_36.s b/benchmarks/LLC_ASM_globalisel/4_function_36.s new file mode 100644 index 0000000..578842b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_36.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + remu a2, a2, a2 + xor a0, a2, a0 + remu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_37.s b/benchmarks/LLC_ASM_globalisel/4_function_37.s new file mode 100644 index 0000000..fe9ec2e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_37.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a0 + and a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_38.s b/benchmarks/LLC_ASM_globalisel/4_function_38.s new file mode 100644 index 0000000..3b4c738 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_38.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + or a1, a0, a1 + remu a0, a0, a1 + sltu a0, a0, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_39.s b/benchmarks/LLC_ASM_globalisel/4_function_39.s new file mode 100644 index 0000000..d6d0ec5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_39.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a2, a1 + or a1, a1, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_4.s b/benchmarks/LLC_ASM_globalisel/4_function_4.s new file mode 100644 index 0000000..c9da28e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_4.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + zext.w a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_40.s b/benchmarks/LLC_ASM_globalisel/4_function_40.s new file mode 100644 index 0000000..08cecae --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_40.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + divu a0, a0, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_41.s b/benchmarks/LLC_ASM_globalisel/4_function_41.s new file mode 100644 index 0000000..9d79135 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_41.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a0 + rem a1, a1, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_42.s b/benchmarks/LLC_ASM_globalisel/4_function_42.s new file mode 100644 index 0000000..4267830 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_42.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + rem a1, a0, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_43.s b/benchmarks/LLC_ASM_globalisel/4_function_43.s new file mode 100644 index 0000000..587dc02 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_43.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_44.s b/benchmarks/LLC_ASM_globalisel/4_function_44.s new file mode 100644 index 0000000..f7f71b1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_44.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remw a0, a0, a0 + sext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_45.s b/benchmarks/LLC_ASM_globalisel/4_function_45.s new file mode 100644 index 0000000..56939e3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_45.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a2, 1 + or a1, a0, a1 + bnez a2, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_46.s b/benchmarks/LLC_ASM_globalisel/4_function_46.s new file mode 100644 index 0000000..a66f43b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_46.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + xor a1, a1, a2 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_47.s b/benchmarks/LLC_ASM_globalisel/4_function_47.s new file mode 100644 index 0000000..9d75750 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_47.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a0 + remu a1, a0, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_48.s b/benchmarks/LLC_ASM_globalisel/4_function_48.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_48.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_49.s b/benchmarks/LLC_ASM_globalisel/4_function_49.s new file mode 100644 index 0000000..10cdac0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_49.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a2 + srl a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_5.s b/benchmarks/LLC_ASM_globalisel/4_function_5.s new file mode 100644 index 0000000..d0fac87 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_5.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_50.s b/benchmarks/LLC_ASM_globalisel/4_function_50.s new file mode 100644 index 0000000..ea637df --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_50.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a0 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_51.s b/benchmarks/LLC_ASM_globalisel/4_function_51.s new file mode 100644 index 0000000..a827847 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_51.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + srl a0, a1, a0 + divu a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_52.s b/benchmarks/LLC_ASM_globalisel/4_function_52.s new file mode 100644 index 0000000..1a2cee7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_52.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a0 + xor a0, a0, a1 + srl a0, a0, a2 + slt a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_53.s b/benchmarks/LLC_ASM_globalisel/4_function_53.s new file mode 100644 index 0000000..5f14e48 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_53.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_54.s b/benchmarks/LLC_ASM_globalisel/4_function_54.s new file mode 100644 index 0000000..a94ed42 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_54.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a0, a2 + divu a1, a1, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_55.s b/benchmarks/LLC_ASM_globalisel/4_function_55.s new file mode 100644 index 0000000..d6a7823 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_55.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a2, a0 + and a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_56.s b/benchmarks/LLC_ASM_globalisel/4_function_56.s new file mode 100644 index 0000000..cea805a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_56.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + srl a1, a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a1 +.LBB0_2: + divu a1, a2, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_57.s b/benchmarks/LLC_ASM_globalisel/4_function_57.s new file mode 100644 index 0000000..f8fe0a6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_57.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + or a1, a1, a2 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_58.s b/benchmarks/LLC_ASM_globalisel/4_function_58.s new file mode 100644 index 0000000..f47cdc0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_58.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + xor a0, a0, a2 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_59.s b/benchmarks/LLC_ASM_globalisel/4_function_59.s new file mode 100644 index 0000000..4c2836d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_59.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_6.s b/benchmarks/LLC_ASM_globalisel/4_function_6.s new file mode 100644 index 0000000..3eaae18 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_6.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_60.s b/benchmarks/LLC_ASM_globalisel/4_function_60.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_60.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_61.s b/benchmarks/LLC_ASM_globalisel/4_function_61.s new file mode 100644 index 0000000..43fcf96 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_61.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + div a1, a1, a0 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_62.s b/benchmarks/LLC_ASM_globalisel/4_function_62.s new file mode 100644 index 0000000..9be739b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_62.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a0 + divu a1, a1, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_63.s b/benchmarks/LLC_ASM_globalisel/4_function_63.s new file mode 100644 index 0000000..1c56590 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_63.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + sra a2, a2, a2 + rem a1, a1, a2 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_64.s b/benchmarks/LLC_ASM_globalisel/4_function_64.s new file mode 100644 index 0000000..fb06534 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_64.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + andi a3, a3, 1 + beqz a3, .LBB0_2 +# %bb.1: + zext.w a0, a0 + sra a0, a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_65.s b/benchmarks/LLC_ASM_globalisel/4_function_65.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_65.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_66.s b/benchmarks/LLC_ASM_globalisel/4_function_66.s new file mode 100644 index 0000000..1de9989 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_66.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_67.s b/benchmarks/LLC_ASM_globalisel/4_function_67.s new file mode 100644 index 0000000..1ce9dbb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_67.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_68.s b/benchmarks/LLC_ASM_globalisel/4_function_68.s new file mode 100644 index 0000000..9ab30ca --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_68.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_69.s b/benchmarks/LLC_ASM_globalisel/4_function_69.s new file mode 100644 index 0000000..e0381e5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_69.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a1, a1 + sra a0, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_7.s b/benchmarks/LLC_ASM_globalisel/4_function_7.s new file mode 100644 index 0000000..675b918 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_7.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + xor a1, a0, a1 + mv a0, a2 + blt a1, a3, .LBB0_2 +# %bb.1: + divu a0, a1, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_70.s b/benchmarks/LLC_ASM_globalisel/4_function_70.s new file mode 100644 index 0000000..6ea0a2f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_70.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a0 + sra a0, a2, a0 + zext.w a1, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_71.s b/benchmarks/LLC_ASM_globalisel/4_function_71.s new file mode 100644 index 0000000..b2bebe4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_71.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a0, a0 + sra a0, a0, a0 + srl a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_72.s b/benchmarks/LLC_ASM_globalisel/4_function_72.s new file mode 100644 index 0000000..e9f5d08 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_72.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + sra a1, a0, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_73.s b/benchmarks/LLC_ASM_globalisel/4_function_73.s new file mode 100644 index 0000000..750c1f1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_73.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_74.s b/benchmarks/LLC_ASM_globalisel/4_function_74.s new file mode 100644 index 0000000..de26ea3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_74.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + maxu a1, a1, a0 + andi a3, a1, 1 + mv a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_75.s b/benchmarks/LLC_ASM_globalisel/4_function_75.s new file mode 100644 index 0000000..f790059 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_75.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_76.s b/benchmarks/LLC_ASM_globalisel/4_function_76.s new file mode 100644 index 0000000..d249848 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_76.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_77.s b/benchmarks/LLC_ASM_globalisel/4_function_77.s new file mode 100644 index 0000000..2bf54a8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_77.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + sext.w a1, a1 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_78.s b/benchmarks/LLC_ASM_globalisel/4_function_78.s new file mode 100644 index 0000000..2d94202 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_78.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_79.s b/benchmarks/LLC_ASM_globalisel/4_function_79.s new file mode 100644 index 0000000..9d26414 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_79.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_8.s b/benchmarks/LLC_ASM_globalisel/4_function_8.s new file mode 100644 index 0000000..bb5c1c7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_8.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_80.s b/benchmarks/LLC_ASM_globalisel/4_function_80.s new file mode 100644 index 0000000..4f4f16a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_80.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a0 + remu a0, a0, a1 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_81.s b/benchmarks/LLC_ASM_globalisel/4_function_81.s new file mode 100644 index 0000000..d6c01fd --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_81.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + or a1, a2, a1 + xor a0, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_82.s b/benchmarks/LLC_ASM_globalisel/4_function_82.s new file mode 100644 index 0000000..6343eca --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_82.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_83.s b/benchmarks/LLC_ASM_globalisel/4_function_83.s new file mode 100644 index 0000000..bb85664 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_83.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_84.s b/benchmarks/LLC_ASM_globalisel/4_function_84.s new file mode 100644 index 0000000..88815bb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_84.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_85.s b/benchmarks/LLC_ASM_globalisel/4_function_85.s new file mode 100644 index 0000000..7ca16a5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_85.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a2, a0, a1 + or a0, a2, a0 + srl a0, a2, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_86.s b/benchmarks/LLC_ASM_globalisel/4_function_86.s new file mode 100644 index 0000000..6062b45 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_86.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + bnez a2, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_87.s b/benchmarks/LLC_ASM_globalisel/4_function_87.s new file mode 100644 index 0000000..189d54d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_87.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_88.s b/benchmarks/LLC_ASM_globalisel/4_function_88.s new file mode 100644 index 0000000..76a353f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_88.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + and a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_89.s b/benchmarks/LLC_ASM_globalisel/4_function_89.s new file mode 100644 index 0000000..563e2eb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_89.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + xor a0, a0, a1 + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_9.s b/benchmarks/LLC_ASM_globalisel/4_function_9.s new file mode 100644 index 0000000..2f74c33 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_9.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + sra a1, a2, a0 + div a1, a2, a1 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_90.s b/benchmarks/LLC_ASM_globalisel/4_function_90.s new file mode 100644 index 0000000..cf90c91 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_90.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + remu a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_91.s b/benchmarks/LLC_ASM_globalisel/4_function_91.s new file mode 100644 index 0000000..fd12564 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_91.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a2 + or a0, a0, a2 + sra a1, a1, a2 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_92.s b/benchmarks/LLC_ASM_globalisel/4_function_92.s new file mode 100644 index 0000000..66585b3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_92.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + div a0, a0, a1 + andn a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_93.s b/benchmarks/LLC_ASM_globalisel/4_function_93.s new file mode 100644 index 0000000..e5da7b0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_93.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a1, a0 + or a1, a1, a0 + sltu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_94.s b/benchmarks/LLC_ASM_globalisel/4_function_94.s new file mode 100644 index 0000000..5cbe1d6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_94.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a0 + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + sltu a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_95.s b/benchmarks/LLC_ASM_globalisel/4_function_95.s new file mode 100644 index 0000000..5e2b3d9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_95.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a2 + sext.w a0, a0 + and a0, a0, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_96.s b/benchmarks/LLC_ASM_globalisel/4_function_96.s new file mode 100644 index 0000000..f0871e0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_96.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + and a0, a0, a1 + srl a1, a2, a2 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_97.s b/benchmarks/LLC_ASM_globalisel/4_function_97.s new file mode 100644 index 0000000..cb23456 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_97.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a1 + rem a1, a0, a1 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_98.s b/benchmarks/LLC_ASM_globalisel/4_function_98.s new file mode 100644 index 0000000..b6f393c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_98.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/4_function_99.s b/benchmarks/LLC_ASM_globalisel/4_function_99.s new file mode 100644 index 0000000..0a56b61 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/4_function_99.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_0.s b/benchmarks/LLC_ASM_globalisel/5_function_0.s new file mode 100644 index 0000000..5b92a3a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_0.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + remu a1, a0, a1 + div a0, a0, a1 + remu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_1.s b/benchmarks/LLC_ASM_globalisel/5_function_1.s new file mode 100644 index 0000000..e45ff70 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_1.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + sra a0, a1, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_10.s b/benchmarks/LLC_ASM_globalisel/5_function_10.s new file mode 100644 index 0000000..3e4bc7a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_10.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + srl a1, a2, a1 + rem a0, a1, a0 + remu a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_11.s b/benchmarks/LLC_ASM_globalisel/5_function_11.s new file mode 100644 index 0000000..dbd4faf --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_11.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + div a1, a1, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_12.s b/benchmarks/LLC_ASM_globalisel/5_function_12.s new file mode 100644 index 0000000..3f5cd13 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_12.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a1, a1 + div a0, a0, a3 + blt a2, a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_13.s b/benchmarks/LLC_ASM_globalisel/5_function_13.s new file mode 100644 index 0000000..2adcbd6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_13.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a1 + zext.w a1, a2 + srl a2, a1, a0 + div a1, a2, a1 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_14.s b/benchmarks/LLC_ASM_globalisel/5_function_14.s new file mode 100644 index 0000000..9b8e049 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_14.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + remu a0, a1, a0 + bgeu a3, a3, .LBB0_2 +# %bb.1: + remu a0, a2, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_15.s b/benchmarks/LLC_ASM_globalisel/5_function_15.s new file mode 100644 index 0000000..bdcc30c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_15.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a3, a0, a1 + mv a1, a2 + blt a3, a0, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + div a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_16.s b/benchmarks/LLC_ASM_globalisel/5_function_16.s new file mode 100644 index 0000000..2151b37 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_16.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a0 + div a0, a0, a1 + divu a0, a0, a0 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_17.s b/benchmarks/LLC_ASM_globalisel/5_function_17.s new file mode 100644 index 0000000..85cb5de --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_17.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a0 + or a0, a2, a0 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_18.s b/benchmarks/LLC_ASM_globalisel/5_function_18.s new file mode 100644 index 0000000..105dc7c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_18.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a0, a0 + rem a1, a2, a1 + div a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_19.s b/benchmarks/LLC_ASM_globalisel/5_function_19.s new file mode 100644 index 0000000..79e9ecd --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_19.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + sra a0, a0, a0 + remu a0, a1, a0 + zext.w a1, a2 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_2.s b/benchmarks/LLC_ASM_globalisel/5_function_2.s new file mode 100644 index 0000000..1a185c7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_2.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + divu a3, a1, a2 + and a2, a2, a3 + sra a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_20.s b/benchmarks/LLC_ASM_globalisel/5_function_20.s new file mode 100644 index 0000000..1825a2e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_20.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a2, a2, a0 + srl a2, a1, a2 + divu a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_21.s b/benchmarks/LLC_ASM_globalisel/5_function_21.s new file mode 100644 index 0000000..fbc198d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_21.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bext a1, a0, a0 + beqz a1, .LBB0_2 +# %bb.1: + srl a0, a0, a0 +.LBB0_2: + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_22.s b/benchmarks/LLC_ASM_globalisel/5_function_22.s new file mode 100644 index 0000000..614d25b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_22.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_23.s b/benchmarks/LLC_ASM_globalisel/5_function_23.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_23.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_24.s b/benchmarks/LLC_ASM_globalisel/5_function_24.s new file mode 100644 index 0000000..0c7bd7e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_24.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + xor a1, a2, a1 + and a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_25.s b/benchmarks/LLC_ASM_globalisel/5_function_25.s new file mode 100644 index 0000000..9857993 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_25.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a0 + remu a0, a1, a0 + and a0, a0, a2 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_26.s b/benchmarks/LLC_ASM_globalisel/5_function_26.s new file mode 100644 index 0000000..8510d11 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_26.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a0 + xor a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_27.s b/benchmarks/LLC_ASM_globalisel/5_function_27.s new file mode 100644 index 0000000..8728297 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_27.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a2 + and a2, a1, a2 + blt a2, a3, .LBB0_2 +# %bb.1: + rem a0, a1, a3 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_28.s b/benchmarks/LLC_ASM_globalisel/5_function_28.s new file mode 100644 index 0000000..45ebec6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_28.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a1 + div a1, a1, a1 + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + rem a1, a1, a2 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_29.s b/benchmarks/LLC_ASM_globalisel/5_function_29.s new file mode 100644 index 0000000..ac5583b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_29.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + div a0, a0, a2 + sext.w a1, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_3.s b/benchmarks/LLC_ASM_globalisel/5_function_3.s new file mode 100644 index 0000000..6540c60 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_3.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a0 + sra a0, a1, a0 + or a0, a1, a0 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_30.s b/benchmarks/LLC_ASM_globalisel/5_function_30.s new file mode 100644 index 0000000..65fbebf --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_30.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a2, a1 + divu a1, a1, a2 + div a1, a1, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_31.s b/benchmarks/LLC_ASM_globalisel/5_function_31.s new file mode 100644 index 0000000..5b573b1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_31.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a1, a2 + bge a0, a2, .LBB0_2 +# %bb.1: + zext.w a0, a3 +.LBB0_2: + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_32.s b/benchmarks/LLC_ASM_globalisel/5_function_32.s new file mode 100644 index 0000000..808271c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_32.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andn a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_33.s b/benchmarks/LLC_ASM_globalisel/5_function_33.s new file mode 100644 index 0000000..45c5e4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_33.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + divu a1, a2, a2 + and a1, a2, a1 +.LBB0_2: + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_34.s b/benchmarks/LLC_ASM_globalisel/5_function_34.s new file mode 100644 index 0000000..fa4286f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_34.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + xor a1, a1, a0 + xor a1, a0, a1 + or a0, a2, a0 + xor a0, a1, a0 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_35.s b/benchmarks/LLC_ASM_globalisel/5_function_35.s new file mode 100644 index 0000000..0883ab3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_35.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a3, a2, a1 + sra a2, a2, a3 + divu a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_36.s b/benchmarks/LLC_ASM_globalisel/5_function_36.s new file mode 100644 index 0000000..e7a8ade --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_36.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_37.s b/benchmarks/LLC_ASM_globalisel/5_function_37.s new file mode 100644 index 0000000..1b36b47 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_37.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + bnez a3, .LBB0_2 +# %bb.1: + zext.w a0, a2 + or a0, a1, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_38.s b/benchmarks/LLC_ASM_globalisel/5_function_38.s new file mode 100644 index 0000000..9b87797 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_38.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a0 + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + and a1, a0, a2 +.LBB0_2: + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_39.s b/benchmarks/LLC_ASM_globalisel/5_function_39.s new file mode 100644 index 0000000..6217760 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_39.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + andi a1, a0, 1 + bnez a1, .LBB0_2 +# %bb.1: + li a0, 0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_4.s b/benchmarks/LLC_ASM_globalisel/5_function_4.s new file mode 100644 index 0000000..23f539c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_4.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + div a1, a0, a1 + divu a0, a0, a1 + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_40.s b/benchmarks/LLC_ASM_globalisel/5_function_40.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_40.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_41.s b/benchmarks/LLC_ASM_globalisel/5_function_41.s new file mode 100644 index 0000000..d11ed63 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_41.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + andi a3, a3, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_42.s b/benchmarks/LLC_ASM_globalisel/5_function_42.s new file mode 100644 index 0000000..3ba1547 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_42.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a2 + sra a2, a0, a0 + xor a0, a2, a0 + or a0, a2, a0 + xor a0, a0, a1 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_43.s b/benchmarks/LLC_ASM_globalisel/5_function_43.s new file mode 100644 index 0000000..3536e63 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_43.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + rem a1, a0, a2 + remu a0, a0, a1 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_44.s b/benchmarks/LLC_ASM_globalisel/5_function_44.s new file mode 100644 index 0000000..652fa43 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_44.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + or a0, a0, a2 + or a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_45.s b/benchmarks/LLC_ASM_globalisel/5_function_45.s new file mode 100644 index 0000000..4c2f7a4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_45.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a2 + div a2, a1, a2 + xor a0, a0, a2 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_46.s b/benchmarks/LLC_ASM_globalisel/5_function_46.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_46.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_47.s b/benchmarks/LLC_ASM_globalisel/5_function_47.s new file mode 100644 index 0000000..b554293 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_47.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a2, a1 + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + remu a0, a1, a1 + rem a0, a2, a0 + xor a0, a1, a0 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_48.s b/benchmarks/LLC_ASM_globalisel/5_function_48.s new file mode 100644 index 0000000..6b6a1ec --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_48.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_49.s b/benchmarks/LLC_ASM_globalisel/5_function_49.s new file mode 100644 index 0000000..a41822a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_49.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a2, a0 + div a1, a1, a2 + xor a1, a0, a1 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_5.s b/benchmarks/LLC_ASM_globalisel/5_function_5.s new file mode 100644 index 0000000..9b5af2f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_5.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + divu a1, a1, a2 + divu a0, a1, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_50.s b/benchmarks/LLC_ASM_globalisel/5_function_50.s new file mode 100644 index 0000000..6baa6b0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_50.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_51.s b/benchmarks/LLC_ASM_globalisel/5_function_51.s new file mode 100644 index 0000000..5c05b0f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_51.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a2 + srl a1, a0, a1 + remu a1, a1, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_52.s b/benchmarks/LLC_ASM_globalisel/5_function_52.s new file mode 100644 index 0000000..f3f8f99 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_52.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a0 + srl a2, a2, a0 + div a0, a2, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_53.s b/benchmarks/LLC_ASM_globalisel/5_function_53.s new file mode 100644 index 0000000..af22d0a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_53.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a0, a0 + beq a2, a2, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_54.s b/benchmarks/LLC_ASM_globalisel/5_function_54.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_54.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_55.s b/benchmarks/LLC_ASM_globalisel/5_function_55.s new file mode 100644 index 0000000..7ecc3ed --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_55.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bge a0, a1, .LBB0_2 +# %bb.1: + remu a2, a2, a1 +.LBB0_2: + slt a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_56.s b/benchmarks/LLC_ASM_globalisel/5_function_56.s new file mode 100644 index 0000000..9f28594 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_56.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a1 + sext.w a0, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_57.s b/benchmarks/LLC_ASM_globalisel/5_function_57.s new file mode 100644 index 0000000..7312250 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_57.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a1, a0 + and a3, a0, a3 + sra a0, a0, a3 + andi a3, a0, 1 + mv a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_58.s b/benchmarks/LLC_ASM_globalisel/5_function_58.s new file mode 100644 index 0000000..fff1439 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_58.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + or a1, a1, a0 + xor a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_59.s b/benchmarks/LLC_ASM_globalisel/5_function_59.s new file mode 100644 index 0000000..fe29bf7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_59.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a1 + and a1, a2, a1 + divu a1, a2, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_6.s b/benchmarks/LLC_ASM_globalisel/5_function_6.s new file mode 100644 index 0000000..5c8c2da --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_6.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a0 + sext.w a1, a1 + xor a0, a0, a1 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_60.s b/benchmarks/LLC_ASM_globalisel/5_function_60.s new file mode 100644 index 0000000..382095b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_60.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + andi a1, a1, 1 + and a0, a0, a3 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + xor a0, a0, a2 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_61.s b/benchmarks/LLC_ASM_globalisel/5_function_61.s new file mode 100644 index 0000000..63229f0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_61.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + zext.w a1, a1 + div a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_62.s b/benchmarks/LLC_ASM_globalisel/5_function_62.s new file mode 100644 index 0000000..6375e63 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_62.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + andi a3, a2, 1 + mv a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + or a0, a0, a2 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_63.s b/benchmarks/LLC_ASM_globalisel/5_function_63.s new file mode 100644 index 0000000..33eec01 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_63.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + zext.w a1, a2 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_64.s b/benchmarks/LLC_ASM_globalisel/5_function_64.s new file mode 100644 index 0000000..1c7cdf7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_64.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a0 + or a2, a2, a0 + remu a1, a2, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_65.s b/benchmarks/LLC_ASM_globalisel/5_function_65.s new file mode 100644 index 0000000..9e76909 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_65.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + rem a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_66.s b/benchmarks/LLC_ASM_globalisel/5_function_66.s new file mode 100644 index 0000000..88815bb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_66.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_67.s b/benchmarks/LLC_ASM_globalisel/5_function_67.s new file mode 100644 index 0000000..d68beb2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_67.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a0, a0 + divu a1, a3, a1 + divu a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_68.s b/benchmarks/LLC_ASM_globalisel/5_function_68.s new file mode 100644 index 0000000..9453bc0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_68.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + div a0, a2, a0 + rem a0, a0, a0 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_69.s b/benchmarks/LLC_ASM_globalisel/5_function_69.s new file mode 100644 index 0000000..678556b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_69.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a2, a1, a2 + div a2, a2, a2 + and a1, a2, a1 + sltu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_7.s b/benchmarks/LLC_ASM_globalisel/5_function_7.s new file mode 100644 index 0000000..34f6dd1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_7.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a2 + or a1, a1, a2 + div a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_70.s b/benchmarks/LLC_ASM_globalisel/5_function_70.s new file mode 100644 index 0000000..166a67a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_70.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + mv a0, a1 + beqz a2, .LBB0_2 +# %bb.1: + srl a0, a0, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_71.s b/benchmarks/LLC_ASM_globalisel/5_function_71.s new file mode 100644 index 0000000..5a7ef12 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_71.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + sext.w a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_72.s b/benchmarks/LLC_ASM_globalisel/5_function_72.s new file mode 100644 index 0000000..0fd0e95 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_72.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + rem a1, a0, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_73.s b/benchmarks/LLC_ASM_globalisel/5_function_73.s new file mode 100644 index 0000000..d77da55 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_73.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + sra a0, a0, a1 + divu a1, a0, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_74.s b/benchmarks/LLC_ASM_globalisel/5_function_74.s new file mode 100644 index 0000000..fc33031 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_74.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + sext.w a1, a2 +.LBB0_2: + and a1, a0, a1 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_75.s b/benchmarks/LLC_ASM_globalisel/5_function_75.s new file mode 100644 index 0000000..928b336 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_75.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a1, zero + div a1, a1, a0 + remw a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_76.s b/benchmarks/LLC_ASM_globalisel/5_function_76.s new file mode 100644 index 0000000..9a34fd4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_76.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + divu a1, a0, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_77.s b/benchmarks/LLC_ASM_globalisel/5_function_77.s new file mode 100644 index 0000000..2aa8567 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_77.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + div a0, a0, a0 + and a0, a0, a2 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_78.s b/benchmarks/LLC_ASM_globalisel/5_function_78.s new file mode 100644 index 0000000..696daa2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_78.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a0 + srl a0, a0, a1 + zext.w a1, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_79.s b/benchmarks/LLC_ASM_globalisel/5_function_79.s new file mode 100644 index 0000000..d200bca --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_79.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + sext.w a1, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_8.s b/benchmarks/LLC_ASM_globalisel/5_function_8.s new file mode 100644 index 0000000..a18715c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_8.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a0, a2 + xor a1, a1, a2 + divu a0, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_80.s b/benchmarks/LLC_ASM_globalisel/5_function_80.s new file mode 100644 index 0000000..63a6590 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_80.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + sra a1, a0, a1 + sra a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_81.s b/benchmarks/LLC_ASM_globalisel/5_function_81.s new file mode 100644 index 0000000..66b8cc9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_81.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + sext.w a2, a2 + and a2, a0, a2 + sltu a0, a0, a2 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_82.s b/benchmarks/LLC_ASM_globalisel/5_function_82.s new file mode 100644 index 0000000..8716857 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_82.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + or a0, a3, a0 + srl a1, a1, a2 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_83.s b/benchmarks/LLC_ASM_globalisel/5_function_83.s new file mode 100644 index 0000000..65b7d4e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_83.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + sra a1, a1, a2 + div a0, a0, a1 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_84.s b/benchmarks/LLC_ASM_globalisel/5_function_84.s new file mode 100644 index 0000000..f8221bd --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_84.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + or a0, a0, a1 + and a2, a0, a2 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_85.s b/benchmarks/LLC_ASM_globalisel/5_function_85.s new file mode 100644 index 0000000..1fbe3f9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_85.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + srl a0, a1, a0 + div a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_86.s b/benchmarks/LLC_ASM_globalisel/5_function_86.s new file mode 100644 index 0000000..75ee426 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_86.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a0, a0 + andi a4, a1, 1 + mv a1, a3 + bnez a4, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + remu a0, a1, a2 + or a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_87.s b/benchmarks/LLC_ASM_globalisel/5_function_87.s new file mode 100644 index 0000000..4d3d6a6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_87.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + bnez a3, .LBB0_2 +# %bb.1: + div a2, a2, a1 +.LBB0_2: + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_88.s b/benchmarks/LLC_ASM_globalisel/5_function_88.s new file mode 100644 index 0000000..06c7038 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_88.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_89.s b/benchmarks/LLC_ASM_globalisel/5_function_89.s new file mode 100644 index 0000000..b77812a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_89.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + and a0, a2, a2 + ret +.LBB0_2: + sra a0, a1, a2 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_9.s b/benchmarks/LLC_ASM_globalisel/5_function_9.s new file mode 100644 index 0000000..3d4aed4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_9.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + sra a0, a1, a2 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_90.s b/benchmarks/LLC_ASM_globalisel/5_function_90.s new file mode 100644 index 0000000..a73acaa --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_90.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + sra a2, a0, a1 + sra a0, a1, a0 + rem a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_91.s b/benchmarks/LLC_ASM_globalisel/5_function_91.s new file mode 100644 index 0000000..45c9169 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_91.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a0 + zext.w a1, a1 + and a0, a0, a1 + and a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_92.s b/benchmarks/LLC_ASM_globalisel/5_function_92.s new file mode 100644 index 0000000..07388c5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_92.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, zero + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_93.s b/benchmarks/LLC_ASM_globalisel/5_function_93.s new file mode 100644 index 0000000..392d138 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_93.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + divu a1, a1, a2 + slt a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_94.s b/benchmarks/LLC_ASM_globalisel/5_function_94.s new file mode 100644 index 0000000..d2b8870 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_94.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + sext.w a1, a0 + srl a0, a2, a0 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_95.s b/benchmarks/LLC_ASM_globalisel/5_function_95.s new file mode 100644 index 0000000..7c1f02b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_95.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a0 + or a1, a1, a0 + srl a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_96.s b/benchmarks/LLC_ASM_globalisel/5_function_96.s new file mode 100644 index 0000000..30bd1ed --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_96.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a2 + srl a1, a1, a0 + and a1, a0, a1 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_97.s b/benchmarks/LLC_ASM_globalisel/5_function_97.s new file mode 100644 index 0000000..e177fce --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_97.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_98.s b/benchmarks/LLC_ASM_globalisel/5_function_98.s new file mode 100644 index 0000000..9d5160d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_98.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a1, a1 + div a0, a0, a1 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/5_function_99.s b/benchmarks/LLC_ASM_globalisel/5_function_99.s new file mode 100644 index 0000000..0497804 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/5_function_99.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a2, a2 + xor a1, a1, a2 + divu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_0.s b/benchmarks/LLC_ASM_globalisel/6_function_0.s new file mode 100644 index 0000000..000a848 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_0.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a0 + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + div a0, a3, a2 + remu a0, a0, a3 + or a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_1.s b/benchmarks/LLC_ASM_globalisel/6_function_1.s new file mode 100644 index 0000000..aa7fdf9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_1.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + zext.w a1, a1 + srl a0, a2, a0 + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_10.s b/benchmarks/LLC_ASM_globalisel/6_function_10.s new file mode 100644 index 0000000..8ae3c12 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_10.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a1, a2 + div a3, a1, a3 + xor a1, a1, a2 + divu a1, a1, a3 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_11.s b/benchmarks/LLC_ASM_globalisel/6_function_11.s new file mode 100644 index 0000000..ec18b9e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_11.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a1 + rem a1, a0, a0 + andi a4, a2, 1 + and a2, a1, a3 + bnez a4, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + srl a0, a2, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_12.s b/benchmarks/LLC_ASM_globalisel/6_function_12.s new file mode 100644 index 0000000..7239cd3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_12.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a0, a0 + sra a2, a2, a1 + remu a0, a0, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_13.s b/benchmarks/LLC_ASM_globalisel/6_function_13.s new file mode 100644 index 0000000..8804010 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_13.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + rem a0, a0, a1 + srl a1, a2, a2 + div a1, a2, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_14.s b/benchmarks/LLC_ASM_globalisel/6_function_14.s new file mode 100644 index 0000000..673c22a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_14.s @@ -0,0 +1,30 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a1, a1 + andi a4, a2, 1 + mv a2, a3 + bnez a4, .LBB0_2 +# %bb.1: + mv a2, a1 +.LBB0_2: + andi a0, a0, 1 + bnez a0, .LBB0_4 +# %bb.3: + mv a1, a2 +.LBB0_4: + rem a0, a1, a3 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_15.s b/benchmarks/LLC_ASM_globalisel/6_function_15.s new file mode 100644 index 0000000..12f24ff --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_15.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + srl a1, a1, a0 + rem a0, a0, a1 + remu a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_16.s b/benchmarks/LLC_ASM_globalisel/6_function_16.s new file mode 100644 index 0000000..0fa21a9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_16.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a1, a1 + div a0, a0, a1 + srl a1, a1, a2 + xor a0, a1, a0 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_17.s b/benchmarks/LLC_ASM_globalisel/6_function_17.s new file mode 100644 index 0000000..fb1294d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_17.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + xor a0, a0, a1 + sext.w a0, a0 + xor a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_18.s b/benchmarks/LLC_ASM_globalisel/6_function_18.s new file mode 100644 index 0000000..bc85990 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_18.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a0 + or a1, a0, a1 + srl a0, a0, a2 + xor a0, a1, a0 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_19.s b/benchmarks/LLC_ASM_globalisel/6_function_19.s new file mode 100644 index 0000000..a8e349e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_19.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + div a1, a2, a2 + andi a3, a1, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a1 +.LBB0_2: + div a0, a0, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_2.s b/benchmarks/LLC_ASM_globalisel/6_function_2.s new file mode 100644 index 0000000..b6addbd --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_2.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a0, a1 + rem a0, a0, a3 + xor a1, a1, a2 + xor a1, a1, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_20.s b/benchmarks/LLC_ASM_globalisel/6_function_20.s new file mode 100644 index 0000000..b05b932 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_20.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a0, a0 + sext.w a2, a2 + and a0, a0, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_21.s b/benchmarks/LLC_ASM_globalisel/6_function_21.s new file mode 100644 index 0000000..57d54f5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_21.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + sext.w a2, a2 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + div a2, a2, a2 + xor a0, a0, a2 + xor a1, a1, a2 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_22.s b/benchmarks/LLC_ASM_globalisel/6_function_22.s new file mode 100644 index 0000000..935fd36 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_22.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a2 + rem a1, a0, a1 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_23.s b/benchmarks/LLC_ASM_globalisel/6_function_23.s new file mode 100644 index 0000000..e287444 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_23.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a2, a2, a1 + srl a0, a2, a1 + remu a0, a2, a0 + rem a0, a0, a0 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_24.s b/benchmarks/LLC_ASM_globalisel/6_function_24.s new file mode 100644 index 0000000..a867d1f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_24.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a2, a1 + andi a3, a3, 1 + xor a0, a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_25.s b/benchmarks/LLC_ASM_globalisel/6_function_25.s new file mode 100644 index 0000000..388d07a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_25.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + rem a1, a0, a1 + remu a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_26.s b/benchmarks/LLC_ASM_globalisel/6_function_26.s new file mode 100644 index 0000000..3c0797f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_26.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_27.s b/benchmarks/LLC_ASM_globalisel/6_function_27.s new file mode 100644 index 0000000..18b56db --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_27.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a1 + and a0, a0, a3 + and a1, a2, a1 + or a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_28.s b/benchmarks/LLC_ASM_globalisel/6_function_28.s new file mode 100644 index 0000000..f8e5335 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_28.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a1, a2 + and a1, a2, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_29.s b/benchmarks/LLC_ASM_globalisel/6_function_29.s new file mode 100644 index 0000000..3ca1aea --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_29.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a0, a0 + srl a0, a0, a2 + zext.w a0, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_3.s b/benchmarks/LLC_ASM_globalisel/6_function_3.s new file mode 100644 index 0000000..6ac61b2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_3.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + bge a0, a0, .LBB0_2 +# %bb.1: + sext.w a1, a1 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_30.s b/benchmarks/LLC_ASM_globalisel/6_function_30.s new file mode 100644 index 0000000..3007241 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_30.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a0 + srl a1, a1, a2 + srl a1, a1, a1 + divu a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_31.s b/benchmarks/LLC_ASM_globalisel/6_function_31.s new file mode 100644 index 0000000..2dcabd4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_31.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a1 + zext.w a3, a1 + div a2, a2, a3 + sra a1, a2, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_32.s b/benchmarks/LLC_ASM_globalisel/6_function_32.s new file mode 100644 index 0000000..abec822 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_32.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a2 + divu a2, a2, a2 + zext.w a1, a1 + xor a0, a0, a1 + rem a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_33.s b/benchmarks/LLC_ASM_globalisel/6_function_33.s new file mode 100644 index 0000000..60df733 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_33.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + sext.w a1, a1 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_34.s b/benchmarks/LLC_ASM_globalisel/6_function_34.s new file mode 100644 index 0000000..5850323 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_34.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a2, 1 + li a0, 0 + bnez a2, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_35.s b/benchmarks/LLC_ASM_globalisel/6_function_35.s new file mode 100644 index 0000000..9ac9c12 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_35.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a2, a0 + sext.w a3, a1 + divu a2, a3, a2 + srl a1, a2, a1 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_36.s b/benchmarks/LLC_ASM_globalisel/6_function_36.s new file mode 100644 index 0000000..928118a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_36.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_37.s b/benchmarks/LLC_ASM_globalisel/6_function_37.s new file mode 100644 index 0000000..9ef42fb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_37.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + div a1, a1, a2 + remu a0, a0, a0 + div a0, a1, a0 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_38.s b/benchmarks/LLC_ASM_globalisel/6_function_38.s new file mode 100644 index 0000000..4ba23f9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_38.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + remu a1, a0, a1 + srl a0, a0, a1 + zext.w a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_39.s b/benchmarks/LLC_ASM_globalisel/6_function_39.s new file mode 100644 index 0000000..5d8fe2a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_39.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + sext.w a1, a2 + rem a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_4.s b/benchmarks/LLC_ASM_globalisel/6_function_4.s new file mode 100644 index 0000000..628c71a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_4.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + zext.w a1, a1 + sra a0, a1, a0 + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_40.s b/benchmarks/LLC_ASM_globalisel/6_function_40.s new file mode 100644 index 0000000..2ebb9b1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_40.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a0 + divu a1, a0, a1 + rem a1, a0, a1 + xor a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_41.s b/benchmarks/LLC_ASM_globalisel/6_function_41.s new file mode 100644 index 0000000..f37e2a9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_41.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + divu a0, a0, a1 + remu a1, a2, a2 + rem a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_42.s b/benchmarks/LLC_ASM_globalisel/6_function_42.s new file mode 100644 index 0000000..9f190c7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_42.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + remu a0, a0, a2 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_43.s b/benchmarks/LLC_ASM_globalisel/6_function_43.s new file mode 100644 index 0000000..b2a0f13 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_43.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + rem a3, a0, a1 + sra a0, a2, a1 + blt a3, a0, .LBB0_4 +# %bb.3: + mv a0, a1 +.LBB0_4: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_44.s b/benchmarks/LLC_ASM_globalisel/6_function_44.s new file mode 100644 index 0000000..e292a4e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_44.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + and a1, a0, a1 + divu a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_45.s b/benchmarks/LLC_ASM_globalisel/6_function_45.s new file mode 100644 index 0000000..d063616 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_45.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + zext.w a1, a0 + slt a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_46.s b/benchmarks/LLC_ASM_globalisel/6_function_46.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_46.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_47.s b/benchmarks/LLC_ASM_globalisel/6_function_47.s new file mode 100644 index 0000000..2bd268c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_47.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + xor a2, a0, a2 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_48.s b/benchmarks/LLC_ASM_globalisel/6_function_48.s new file mode 100644 index 0000000..2c83948 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_48.s @@ -0,0 +1,31 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a2, a2 + andi a3, a0, 1 + mv a0, a1 + beqz a3, .LBB0_3 +# %bb.1: + andi a2, a0, 1 + beqz a2, .LBB0_4 +.LBB0_2: + mv a0, a1 + ret +.LBB0_3: + rem a0, a2, a1 + andi a2, a0, 1 + bnez a2, .LBB0_2 +.LBB0_4: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_49.s b/benchmarks/LLC_ASM_globalisel/6_function_49.s new file mode 100644 index 0000000..1f61ef9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_49.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a0 + remu a0, a2, a0 + zext.w a1, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_5.s b/benchmarks/LLC_ASM_globalisel/6_function_5.s new file mode 100644 index 0000000..6abe101 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_5.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + zext.w a1, a0 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_50.s b/benchmarks/LLC_ASM_globalisel/6_function_50.s new file mode 100644 index 0000000..42f3533 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_50.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a0, a0 + sra a1, a3, a1 + andi a3, a2, 1 + zext.w a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + remu a0, a2, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_51.s b/benchmarks/LLC_ASM_globalisel/6_function_51.s new file mode 100644 index 0000000..f46adb9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_51.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + rem a0, a0, a0 + remu a1, a1, a2 + and a1, a0, a1 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_52.s b/benchmarks/LLC_ASM_globalisel/6_function_52.s new file mode 100644 index 0000000..0a813bc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_52.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a0 + or a1, a1, a2 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_53.s b/benchmarks/LLC_ASM_globalisel/6_function_53.s new file mode 100644 index 0000000..744e668 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_53.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + div a1, a1, zero + remu a0, a0, a1 + divu a0, a0, zero + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_54.s b/benchmarks/LLC_ASM_globalisel/6_function_54.s new file mode 100644 index 0000000..033d726 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_54.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + sext.w a0, a0 + srl a1, a1, a0 + remu a0, a1, a0 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_55.s b/benchmarks/LLC_ASM_globalisel/6_function_55.s new file mode 100644 index 0000000..4e7d9e3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_55.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a0, a0 + remu a0, a0, a1 + rem a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_56.s b/benchmarks/LLC_ASM_globalisel/6_function_56.s new file mode 100644 index 0000000..4069dc4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_56.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a2 + and a1, a0, a1 + zext.w a2, a1 + and a1, a2, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_57.s b/benchmarks/LLC_ASM_globalisel/6_function_57.s new file mode 100644 index 0000000..cdd06dd --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_57.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a2 + sra a1, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_58.s b/benchmarks/LLC_ASM_globalisel/6_function_58.s new file mode 100644 index 0000000..4fb063a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_58.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bltu a0, a0, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_59.s b/benchmarks/LLC_ASM_globalisel/6_function_59.s new file mode 100644 index 0000000..1c07594 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_59.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_6.s b/benchmarks/LLC_ASM_globalisel/6_function_6.s new file mode 100644 index 0000000..9b6d6cc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_6.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a0 + div a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_60.s b/benchmarks/LLC_ASM_globalisel/6_function_60.s new file mode 100644 index 0000000..d94e11f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_60.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a0 + sext.w a2, a0 + div a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_61.s b/benchmarks/LLC_ASM_globalisel/6_function_61.s new file mode 100644 index 0000000..735cada --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_61.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, zero + zext.w a2, a2 + and a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_62.s b/benchmarks/LLC_ASM_globalisel/6_function_62.s new file mode 100644 index 0000000..115bc99 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_62.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + xor a1, a0, a2 + sra a1, a0, a1 + andi a3, a1, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + remu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_63.s b/benchmarks/LLC_ASM_globalisel/6_function_63.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_63.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_64.s b/benchmarks/LLC_ASM_globalisel/6_function_64.s new file mode 100644 index 0000000..cbeb320 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_64.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a0 + rem a3, a3, a0 + sra a2, a2, a2 + rem a2, a3, a2 + or a0, a0, a1 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_65.s b/benchmarks/LLC_ASM_globalisel/6_function_65.s new file mode 100644 index 0000000..810a2d8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_65.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + zext.w a1, a0 + sext.w a0, a0 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_66.s b/benchmarks/LLC_ASM_globalisel/6_function_66.s new file mode 100644 index 0000000..e5aa959 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_66.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + div a0, a0, a1 + zext.w a1, a2 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_67.s b/benchmarks/LLC_ASM_globalisel/6_function_67.s new file mode 100644 index 0000000..aa378f1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_67.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a3, a0, a1 + xor a2, a2, a3 + rem a1, a1, a2 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_68.s b/benchmarks/LLC_ASM_globalisel/6_function_68.s new file mode 100644 index 0000000..514470c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_68.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a0, a0 + sra a0, a2, a0 + divu a1, a0, a1 + zext.w a0, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_69.s b/benchmarks/LLC_ASM_globalisel/6_function_69.s new file mode 100644 index 0000000..8dbf838 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_69.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + beq a0, a0, .LBB0_2 +# %bb.1: + zext.w a0, a3 + div a0, a0, a1 + ret +.LBB0_2: + rem a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_7.s b/benchmarks/LLC_ASM_globalisel/6_function_7.s new file mode 100644 index 0000000..e7ff880 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_7.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + divu a0, a0, a2 + zext.w a0, a0 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_70.s b/benchmarks/LLC_ASM_globalisel/6_function_70.s new file mode 100644 index 0000000..64116b8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_70.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a0 + remu a0, a0, a0 + remu a1, a2, a2 + sra a0, a0, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_71.s b/benchmarks/LLC_ASM_globalisel/6_function_71.s new file mode 100644 index 0000000..bc673f1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_71.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + divu a1, a1, a2 + sra a1, a0, a1 + srl a1, a1, a2 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_72.s b/benchmarks/LLC_ASM_globalisel/6_function_72.s new file mode 100644 index 0000000..be6cbc4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_72.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a2, a2 + divu a2, a0, a2 + xor a0, a0, a1 + div a1, a0, a2 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_73.s b/benchmarks/LLC_ASM_globalisel/6_function_73.s new file mode 100644 index 0000000..f6c6201 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_73.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_74.s b/benchmarks/LLC_ASM_globalisel/6_function_74.s new file mode 100644 index 0000000..0a1a3ef --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_74.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a2, a2 + divu a1, a1, a2 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_75.s b/benchmarks/LLC_ASM_globalisel/6_function_75.s new file mode 100644 index 0000000..45d25ec --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_75.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a1 + srl a0, a0, a1 + sext.w a0, a0 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_76.s b/benchmarks/LLC_ASM_globalisel/6_function_76.s new file mode 100644 index 0000000..f240906 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_76.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a0, a0 + bltu a3, a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + remu a0, a2, a3 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_77.s b/benchmarks/LLC_ASM_globalisel/6_function_77.s new file mode 100644 index 0000000..66ed929 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_77.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a2 + divu a2, a1, a2 + srl a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_78.s b/benchmarks/LLC_ASM_globalisel/6_function_78.s new file mode 100644 index 0000000..7e52285 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_78.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + divu a1, a1, a2 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_79.s b/benchmarks/LLC_ASM_globalisel/6_function_79.s new file mode 100644 index 0000000..a835538 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_79.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a0, a2 + j .LBB0_3 +.LBB0_2: + mv a0, a1 + mv a1, a2 +.LBB0_3: + zext.w a1, a1 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_8.s b/benchmarks/LLC_ASM_globalisel/6_function_8.s new file mode 100644 index 0000000..cdae185 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_8.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a2, a2 + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a3 +.LBB0_2: + div a0, a2, a3 + rem a0, a0, a2 + srl a1, a1, a2 + slt a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_80.s b/benchmarks/LLC_ASM_globalisel/6_function_80.s new file mode 100644 index 0000000..2edfd19 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_80.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + zext.w a0, a2 +.LBB0_2: + xor a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_81.s b/benchmarks/LLC_ASM_globalisel/6_function_81.s new file mode 100644 index 0000000..6ba570c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_81.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a1, a2 + and a1, a1, a2 + sra a0, a0, a1 + srl a1, a0, a1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_82.s b/benchmarks/LLC_ASM_globalisel/6_function_82.s new file mode 100644 index 0000000..da455aa --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_82.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a2, a0 + bgeu a3, a1, .LBB0_2 +# %bb.1: + remu a2, a2, a2 +.LBB0_2: + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_83.s b/benchmarks/LLC_ASM_globalisel/6_function_83.s new file mode 100644 index 0000000..a028c9d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_83.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + blt a1, a0, .LBB0_2 +# %bb.1: + sra a0, a1, a1 + rem a1, a0, a2 +.LBB0_2: + sra a0, a1, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_84.s b/benchmarks/LLC_ASM_globalisel/6_function_84.s new file mode 100644 index 0000000..02f5b88 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_84.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a0 + div a0, a0, a1 + srl a0, a0, a2 + sext.w a3, a3 + bgeu a3, a0, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_85.s b/benchmarks/LLC_ASM_globalisel/6_function_85.s new file mode 100644 index 0000000..ae4aecf --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_85.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + sra a0, a2, a1 + beqz a3, .LBB0_2 +# %bb.1: + and a0, a1, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_86.s b/benchmarks/LLC_ASM_globalisel/6_function_86.s new file mode 100644 index 0000000..71e219f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_86.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + and a1, a0, a1 + xor a0, a0, a1 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_87.s b/benchmarks/LLC_ASM_globalisel/6_function_87.s new file mode 100644 index 0000000..a525305 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_87.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a0, a0 + or a2, a0, a2 + or a1, a1, a0 + divu a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_88.s b/benchmarks/LLC_ASM_globalisel/6_function_88.s new file mode 100644 index 0000000..24a480c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_88.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + rem a0, a2, a0 + xor a0, a2, a0 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_89.s b/benchmarks/LLC_ASM_globalisel/6_function_89.s new file mode 100644 index 0000000..f13e6a9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_89.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a0 + zext.w a0, a0 + and a1, a0, a1 + divu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_9.s b/benchmarks/LLC_ASM_globalisel/6_function_9.s new file mode 100644 index 0000000..1780cfc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_9.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a2, a0 + mv a0, a1 + andi a2, a2, 1 + bnez a2, .LBB0_2 +# %bb.1: + sext.w a0, a3 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_90.s b/benchmarks/LLC_ASM_globalisel/6_function_90.s new file mode 100644 index 0000000..f2f14cc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_90.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a2 + andi a4, a1, 1 + srl a1, a3, a2 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a1 +.LBB0_2: + and a1, a1, a2 + or a1, a3, a1 + sltu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_91.s b/benchmarks/LLC_ASM_globalisel/6_function_91.s new file mode 100644 index 0000000..489073c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_91.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a2 + div a2, a0, a2 + or a1, a0, a1 + sra a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_92.s b/benchmarks/LLC_ASM_globalisel/6_function_92.s new file mode 100644 index 0000000..093aee0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_92.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a2 + bltu a1, a3, .LBB0_2 +# %bb.1: + rem a0, a3, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_93.s b/benchmarks/LLC_ASM_globalisel/6_function_93.s new file mode 100644 index 0000000..de2927f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_93.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a2, a0 + srl a3, a0, a2 + rem a1, a1, a3 + rem a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_94.s b/benchmarks/LLC_ASM_globalisel/6_function_94.s new file mode 100644 index 0000000..17869b5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_94.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + remu a0, a2, a2 + or a0, a0, a2 + divu a0, a0, a1 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_95.s b/benchmarks/LLC_ASM_globalisel/6_function_95.s new file mode 100644 index 0000000..ac4e3ec --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_95.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a0 + rem a1, a1, a0 + sext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_96.s b/benchmarks/LLC_ASM_globalisel/6_function_96.s new file mode 100644 index 0000000..19394c8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_96.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a0, 1 + bnez a4, .LBB0_2 +# %bb.1: + mv a0, a2 + ret +.LBB0_2: + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_97.s b/benchmarks/LLC_ASM_globalisel/6_function_97.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_97.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_98.s b/benchmarks/LLC_ASM_globalisel/6_function_98.s new file mode 100644 index 0000000..cab4b57 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_98.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/6_function_99.s b/benchmarks/LLC_ASM_globalisel/6_function_99.s new file mode 100644 index 0000000..a40bf9f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/6_function_99.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + beq a2, a0, .LBB0_2 +# %bb.1: + mv a3, a0 + j .LBB0_3 +.LBB0_2: + sext.w a3, a3 +.LBB0_3: + remu a1, a1, a3 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_0.s b/benchmarks/LLC_ASM_globalisel/7_function_0.s new file mode 100644 index 0000000..5cc67e5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_0.s @@ -0,0 +1,37 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + beqz a3, .LBB0_4 +# %bb.1: + andi a3, a2, 1 + beqz a3, .LBB0_5 +.LBB0_2: + or a2, a0, a2 + beqz a3, .LBB0_6 +.LBB0_3: + div a0, a2, a1 + ret +.LBB0_4: + mv a0, a2 + andi a3, a2, 1 + bnez a3, .LBB0_2 +.LBB0_5: + or a2, a0, a0 + bnez a3, .LBB0_3 +.LBB0_6: + div a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_1.s b/benchmarks/LLC_ASM_globalisel/7_function_1.s new file mode 100644 index 0000000..ed6daab --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_1.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + zext.w a2, a2 + div a0, a2, a0 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_10.s b/benchmarks/LLC_ASM_globalisel/7_function_10.s new file mode 100644 index 0000000..2152833 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_10.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a0 + srl a0, a3, a0 + divu a3, a0, a0 + rem a2, a2, a3 + remu a1, a1, a2 + remu a0, a0, a1 + slt a0, a0, a3 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_11.s b/benchmarks/LLC_ASM_globalisel/7_function_11.s new file mode 100644 index 0000000..bc55579 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_11.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a0 + srl a0, a2, a0 + xor a1, a3, a1 + zext.w a0, a0 + div a0, a1, a0 + rem a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_12.s b/benchmarks/LLC_ASM_globalisel/7_function_12.s new file mode 100644 index 0000000..34c5780 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_12.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + or a2, a2, a3 + div a2, a3, a2 + divu a1, a1, a2 + sra a0, a3, a0 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_13.s b/benchmarks/LLC_ASM_globalisel/7_function_13.s new file mode 100644 index 0000000..b3343cf --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_13.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a3, a0, a1 + divu a1, a3, a1 + bgeu a2, a1, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_14.s b/benchmarks/LLC_ASM_globalisel/7_function_14.s new file mode 100644 index 0000000..2334e1e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_14.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + and a0, a0, a1 + zext.w a0, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_15.s b/benchmarks/LLC_ASM_globalisel/7_function_15.s new file mode 100644 index 0000000..42923c2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_15.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a1 + rem a1, a2, a3 + div a1, a2, a1 + bgeu a3, a0, .LBB0_2 +# %bb.1: + srl a1, a0, a1 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_16.s b/benchmarks/LLC_ASM_globalisel/7_function_16.s new file mode 100644 index 0000000..6f5f9be --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_16.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a1, a2 + sra a0, a0, a3 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_17.s b/benchmarks/LLC_ASM_globalisel/7_function_17.s new file mode 100644 index 0000000..115f4c1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_17.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a2, a0 + mv a1, a1 + or a2, a2, a3 + xor a0, a0, a1 + xor a0, a0, a2 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_18.s b/benchmarks/LLC_ASM_globalisel/7_function_18.s new file mode 100644 index 0000000..1a878c2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_18.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a0, a0 + divu a3, a2, a2 + div a3, a0, a3 + or a2, a2, a3 + remu a1, a1, a2 + sra a0, a0, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_19.s b/benchmarks/LLC_ASM_globalisel/7_function_19.s new file mode 100644 index 0000000..b953359 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_19.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a2, a1, a2 + remu a0, a2, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_2.s b/benchmarks/LLC_ASM_globalisel/7_function_2.s new file mode 100644 index 0000000..044e850 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_2.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a0, a1 + sra a0, a0, a2 + remu a0, a0, a1 + div a1, a0, a1 + srl a0, a0, a1 + xor a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_20.s b/benchmarks/LLC_ASM_globalisel/7_function_20.s new file mode 100644 index 0000000..4498974 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_20.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a0, a0 + mv a4, a0 + bge a3, a1, .LBB0_2 +# %bb.1: + remu a1, a2, a1 + rem a4, a3, a1 +.LBB0_2: + div a1, a3, a4 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_21.s b/benchmarks/LLC_ASM_globalisel/7_function_21.s new file mode 100644 index 0000000..f83aba8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_21.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + divu a2, a1, a2 + minu a1, a1, a2 + and a0, a0, a1 + xor a1, a1, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_22.s b/benchmarks/LLC_ASM_globalisel/7_function_22.s new file mode 100644 index 0000000..85685f1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_22.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_23.s b/benchmarks/LLC_ASM_globalisel/7_function_23.s new file mode 100644 index 0000000..7bfb752 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_23.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a1, a2 + div a1, a0, a1 + sra a0, a0, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_24.s b/benchmarks/LLC_ASM_globalisel/7_function_24.s new file mode 100644 index 0000000..7f30114 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_24.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a0 + srl a2, a0, a1 + or a0, a0, a2 + rem a1, a0, a1 + sext.w a0, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_25.s b/benchmarks/LLC_ASM_globalisel/7_function_25.s new file mode 100644 index 0000000..028c217 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_25.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + andi a1, a0, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + andi a1, a2, 1 + bnez a1, .LBB0_4 +# %bb.3: + remu a0, a2, a0 + ret +.LBB0_4: + zext.w a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_26.s b/benchmarks/LLC_ASM_globalisel/7_function_26.s new file mode 100644 index 0000000..b9df145 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_26.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + remu a2, a2, a0 + div a2, a2, a0 + andn a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_27.s b/benchmarks/LLC_ASM_globalisel/7_function_27.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_27.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_28.s b/benchmarks/LLC_ASM_globalisel/7_function_28.s new file mode 100644 index 0000000..8d39fdd --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_28.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a2 + rem a2, a2, a2 + rem a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_29.s b/benchmarks/LLC_ASM_globalisel/7_function_29.s new file mode 100644 index 0000000..fc39489 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_29.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a3, a0, a3 + sra a2, a2, a3 + and a0, a1, a0 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_3.s b/benchmarks/LLC_ASM_globalisel/7_function_3.s new file mode 100644 index 0000000..cac338d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_3.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a0 + or a0, a0, a1 + zext.w a1, a2 + rem a0, a0, a1 + sext.w a2, a2 + sra a1, a2, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_30.s b/benchmarks/LLC_ASM_globalisel/7_function_30.s new file mode 100644 index 0000000..c074d0a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_30.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a1 + srl a1, a0, a1 + and a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_31.s b/benchmarks/LLC_ASM_globalisel/7_function_31.s new file mode 100644 index 0000000..af528e7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_31.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + sext.w a2, a2 + sltu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_32.s b/benchmarks/LLC_ASM_globalisel/7_function_32.s new file mode 100644 index 0000000..39b7aaf --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_32.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + zext.w a0, a0 + xor a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_33.s b/benchmarks/LLC_ASM_globalisel/7_function_33.s new file mode 100644 index 0000000..94edc6a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_33.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a0 + sext.w a1, a1 + rem a1, a1, a0 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_34.s b/benchmarks/LLC_ASM_globalisel/7_function_34.s new file mode 100644 index 0000000..ef01412 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_34.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + zext.w a1, a2 + xor a1, a1, a2 +.LBB0_2: + srl a0, a1, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_35.s b/benchmarks/LLC_ASM_globalisel/7_function_35.s new file mode 100644 index 0000000..4e3a9af --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_35.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + sra a2, a2, a0 + srl a1, a2, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_36.s b/benchmarks/LLC_ASM_globalisel/7_function_36.s new file mode 100644 index 0000000..fa02f48 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_36.s @@ -0,0 +1,30 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a0, 1 + sra a3, a1, a2 + mv a0, a3 + bnez a4, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + mv a2, a0 + bgeu a3, a1, .LBB0_4 +# %bb.3: + mv a2, a3 +.LBB0_4: + divu a1, a2, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_37.s b/benchmarks/LLC_ASM_globalisel/7_function_37.s new file mode 100644 index 0000000..eb12cc4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_37.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + srl a1, a2, a0 + rem a1, a0, a1 + and a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_38.s b/benchmarks/LLC_ASM_globalisel/7_function_38.s new file mode 100644 index 0000000..195d07c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_38.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a1 + and a0, a0, a3 + remu a4, a0, a3 + beq a4, a2, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + or a0, a3, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_39.s b/benchmarks/LLC_ASM_globalisel/7_function_39.s new file mode 100644 index 0000000..45a4a64 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_39.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + sext.w a0, a0 + remu a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_4.s b/benchmarks/LLC_ASM_globalisel/7_function_4.s new file mode 100644 index 0000000..75a8089 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_4.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a0, a1 + srl a3, a3, a3 + divu a3, a3, a1 + and a3, a2, a3 + sra a2, a2, a3 + and a1, a1, a2 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_40.s b/benchmarks/LLC_ASM_globalisel/7_function_40.s new file mode 100644 index 0000000..6676b7b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_40.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + sext.w a2, a2 + rem a3, a2, a1 + srl a0, a0, a1 + srl a1, a3, a2 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_41.s b/benchmarks/LLC_ASM_globalisel/7_function_41.s new file mode 100644 index 0000000..462953e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_41.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + and a1, a1, a0 + srl a1, a2, a1 + srl a1, a0, a1 + and a0, a0, a2 + divu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_42.s b/benchmarks/LLC_ASM_globalisel/7_function_42.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_42.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_43.s b/benchmarks/LLC_ASM_globalisel/7_function_43.s new file mode 100644 index 0000000..692f099 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_43.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + sra a0, a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 + j .LBB0_3 +.LBB0_2: + mv a2, a0 +.LBB0_3: + sext.w a2, a2 + remu a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_44.s b/benchmarks/LLC_ASM_globalisel/7_function_44.s new file mode 100644 index 0000000..1ac34c2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_44.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a0, a0 + remu a1, a3, a1 + andi a2, a2, 1 + bnez a2, .LBB0_2 +# %bb.1: + mv a0, a3 +.LBB0_2: + xor a2, a0, a1 + div a0, a2, a0 + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_45.s b/benchmarks/LLC_ASM_globalisel/7_function_45.s new file mode 100644 index 0000000..4ad164e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_45.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a2, a1 + xor a1, a1, a2 + and a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_46.s b/benchmarks/LLC_ASM_globalisel/7_function_46.s new file mode 100644 index 0000000..85c2627 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_46.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bge a0, a0, .LBB0_2 +# %bb.1: + remu a0, a0, a2 + sra a0, a1, a0 + ret +.LBB0_2: + sra a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_47.s b/benchmarks/LLC_ASM_globalisel/7_function_47.s new file mode 100644 index 0000000..26eeeaf --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_47.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a4, a0 + sra a1, a1, a2 + andi a3, a3, 1 + xor a1, a4, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a4 +.LBB0_2: + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_48.s b/benchmarks/LLC_ASM_globalisel/7_function_48.s new file mode 100644 index 0000000..4f1883e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_48.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + divu a0, a0, a1 + rem a1, a2, a0 + xor a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_49.s b/benchmarks/LLC_ASM_globalisel/7_function_49.s new file mode 100644 index 0000000..38a780d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_49.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + div a1, a0, a1 + sra a0, a0, a1 + remu a2, a0, a2 + srl a0, a0, a1 + or a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_5.s b/benchmarks/LLC_ASM_globalisel/7_function_5.s new file mode 100644 index 0000000..43e0073 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_5.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_50.s b/benchmarks/LLC_ASM_globalisel/7_function_50.s new file mode 100644 index 0000000..dd61f86 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_50.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a3, a2, a0 + srl a2, a3, a2 + divu a2, a1, a2 + div a0, a0, a2 + divu a1, a2, a1 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_51.s b/benchmarks/LLC_ASM_globalisel/7_function_51.s new file mode 100644 index 0000000..4573881 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_51.s @@ -0,0 +1,33 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a3, 1 + mv a3, a1 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a2 +.LBB0_2: + or a0, a0, a1 + mv a5, a3 + bnez a4, .LBB0_4 +# %bb.3: + mv a5, a1 +.LBB0_4: + divu a1, a5, a3 + xor a1, a2, a1 + divu a1, a2, a1 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_52.s b/benchmarks/LLC_ASM_globalisel/7_function_52.s new file mode 100644 index 0000000..79bd7b2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_52.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a0 + rem a2, a3, a2 + or a1, a1, a2 + sext.w a0, a0 + and a0, a1, a0 + divu a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_53.s b/benchmarks/LLC_ASM_globalisel/7_function_53.s new file mode 100644 index 0000000..93c0c1b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_53.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a2, a2 + remu a2, a2, a1 + divu a1, a1, a2 + sext.w a0, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_54.s b/benchmarks/LLC_ASM_globalisel/7_function_54.s new file mode 100644 index 0000000..a3756ab --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_54.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + sext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_55.s b/benchmarks/LLC_ASM_globalisel/7_function_55.s new file mode 100644 index 0000000..9763b01 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_55.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a0 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_56.s b/benchmarks/LLC_ASM_globalisel/7_function_56.s new file mode 100644 index 0000000..5d5ff02 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_56.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + sext.w a1, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_57.s b/benchmarks/LLC_ASM_globalisel/7_function_57.s new file mode 100644 index 0000000..5990f57 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_57.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a0 + rem a0, a0, a1 + and a0, a0, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_58.s b/benchmarks/LLC_ASM_globalisel/7_function_58.s new file mode 100644 index 0000000..769b96c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_58.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a2, a2, a1 + remu a2, a2, a1 + xor a0, a0, a1 + rem a0, a0, a2 + rem a1, a0, a2 + and a1, a2, a1 + slt a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_59.s b/benchmarks/LLC_ASM_globalisel/7_function_59.s new file mode 100644 index 0000000..6568f7d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_59.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + srl a1, a1, a0 + sra a1, a0, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_6.s b/benchmarks/LLC_ASM_globalisel/7_function_6.s new file mode 100644 index 0000000..faa8774 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_6.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a0, a0 + or a0, a3, a0 + xor a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_60.s b/benchmarks/LLC_ASM_globalisel/7_function_60.s new file mode 100644 index 0000000..d293959 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_60.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a1 + or a2, a2, a0 + or a1, a1, a2 + div a1, a0, a1 + xor a1, a1, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_61.s b/benchmarks/LLC_ASM_globalisel/7_function_61.s new file mode 100644 index 0000000..97daa86 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_61.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a1 + zext.w a0, a2 + mv a2, a0 + blt a1, a3, .LBB0_2 +# %bb.1: + mv a2, a1 +.LBB0_2: + sltu a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_62.s b/benchmarks/LLC_ASM_globalisel/7_function_62.s new file mode 100644 index 0000000..83d53a5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_62.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + xor a1, a1, a2 + or a1, a3, a1 + xor a0, a0, a1 + remu a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_63.s b/benchmarks/LLC_ASM_globalisel/7_function_63.s new file mode 100644 index 0000000..8b65510 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_63.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a0, a1 + srl a2, a2, a2 + divu a1, a1, a2 + sext.w a1, a1 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_64.s b/benchmarks/LLC_ASM_globalisel/7_function_64.s new file mode 100644 index 0000000..1467607 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_64.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_65.s b/benchmarks/LLC_ASM_globalisel/7_function_65.s new file mode 100644 index 0000000..1370650 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_65.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + and a0, a0, a1 + and a1, a0, a1 + div a1, a0, a1 + sra a0, a0, a1 + rem a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_66.s b/benchmarks/LLC_ASM_globalisel/7_function_66.s new file mode 100644 index 0000000..7bc255f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_66.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + sext.w a3, a3 + remu a1, a3, a1 + bgeu a1, a3, .LBB0_2 +# %bb.1: + divu a1, a0, a2 + remu a0, a1, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_67.s b/benchmarks/LLC_ASM_globalisel/7_function_67.s new file mode 100644 index 0000000..35778b3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_67.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a2 + divu a2, a1, zero + remu a1, a2, a1 + divu a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_68.s b/benchmarks/LLC_ASM_globalisel/7_function_68.s new file mode 100644 index 0000000..5108e0c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_68.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a1 + blt a0, a0, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + rem a0, a3, a0 + andi a3, a0, 1 + bnez a3, .LBB0_4 +# %bb.3: + xor a0, a1, a2 +.LBB0_4: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_69.s b/benchmarks/LLC_ASM_globalisel/7_function_69.s new file mode 100644 index 0000000..fd2daa9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_69.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + and a2, a1, a2 + sra a0, a0, a2 + sext.w a2, a0 + or a0, a0, a1 + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_7.s b/benchmarks/LLC_ASM_globalisel/7_function_7.s new file mode 100644 index 0000000..0246d35 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_7.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a0 + and a1, a1, a2 + srl a0, a0, a1 + remu a0, a0, a1 + sext.w a3, a3 + or a3, a3, a0 + sltu a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_70.s b/benchmarks/LLC_ASM_globalisel/7_function_70.s new file mode 100644 index 0000000..4bbfed3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_70.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a0, a0 + div a2, a0, a2 + rem a0, a0, a1 + zext.w a0, a0 + xor a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_71.s b/benchmarks/LLC_ASM_globalisel/7_function_71.s new file mode 100644 index 0000000..4d9879b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_71.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a0, a0 + rem a4, a1, a2 + divu a0, a0, a4 + or a0, a0, a2 + xor a0, a3, a0 + xor a1, a2, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_72.s b/benchmarks/LLC_ASM_globalisel/7_function_72.s new file mode 100644 index 0000000..7cc8af7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_72.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a1 + zext.w a2, a2 + div a1, a1, a2 + divu a0, a0, a1 + rem a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_73.s b/benchmarks/LLC_ASM_globalisel/7_function_73.s new file mode 100644 index 0000000..dc9dc8a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_73.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + and a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_74.s b/benchmarks/LLC_ASM_globalisel/7_function_74.s new file mode 100644 index 0000000..68a15d9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_74.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a1, a2 + divu a3, a2, a0 + xor a0, a0, a2 + xor a0, a0, a1 + xor a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_75.s b/benchmarks/LLC_ASM_globalisel/7_function_75.s new file mode 100644 index 0000000..2cd0830 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_75.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + andi a3, a1, 1 + bnez a3, .LBB0_2 +# %bb.1: + divu a2, a0, a0 + rem a0, a1, a0 + xor a2, a2, a0 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_76.s b/benchmarks/LLC_ASM_globalisel/7_function_76.s new file mode 100644 index 0000000..a11d3d2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_76.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a4, a0, a1 + divu a5, a4, a4 + divu a2, a5, a2 + andi a3, a3, 1 + or a0, a2, a0 + bnez a3, .LBB0_2 +# %bb.1: + mv a4, a1 +.LBB0_2: + or a0, a0, a4 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_77.s b/benchmarks/LLC_ASM_globalisel/7_function_77.s new file mode 100644 index 0000000..baa33b7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_77.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a4, a0, a0 + sra a0, a4, a0 + xor a1, a0, a1 + andi a3, a3, 1 + and a1, a1, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + divu a0, a0, a4 + divu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_78.s b/benchmarks/LLC_ASM_globalisel/7_function_78.s new file mode 100644 index 0000000..2139cdb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_78.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a0 + sext.w a1, a1 + divu a2, a1, a0 + or a1, a2, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_79.s b/benchmarks/LLC_ASM_globalisel/7_function_79.s new file mode 100644 index 0000000..6a406b9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_79.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + rem a1, a0, a2 + zext.w a1, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_8.s b/benchmarks/LLC_ASM_globalisel/7_function_8.s new file mode 100644 index 0000000..35739fa --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_8.s @@ -0,0 +1,32 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a2 + bgeu a1, a1, .LBB0_2 +# %bb.1: + mv a3, a1 +.LBB0_2: + andi a4, a0, 1 + mv a0, a1 + bnez a4, .LBB0_4 +# %bb.3: + mv a0, a3 +.LBB0_4: + or a1, a2, a1 + remu a2, a3, a1 + or a1, a2, a1 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_80.s b/benchmarks/LLC_ASM_globalisel/7_function_80.s new file mode 100644 index 0000000..4fc6442 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_80.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a2 + beq a0, a1, .LBB0_2 +# %bb.1: + divu a3, a2, a1 +.LBB0_2: + or a4, a0, a2 + mv a2, a3 + bltu a1, a4, .LBB0_4 +# %bb.3: + mv a2, a0 +.LBB0_4: + sra a0, a3, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_81.s b/benchmarks/LLC_ASM_globalisel/7_function_81.s new file mode 100644 index 0000000..d0c064b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_81.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + srl a1, a0, a1 + xor a2, a2, a0 + rem a2, a1, a2 + srl a0, a0, a1 + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_82.s b/benchmarks/LLC_ASM_globalisel/7_function_82.s new file mode 100644 index 0000000..7db0a96 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_82.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a2 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_83.s b/benchmarks/LLC_ASM_globalisel/7_function_83.s new file mode 100644 index 0000000..94f3118 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_83.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + sext.w a0, a0 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_84.s b/benchmarks/LLC_ASM_globalisel/7_function_84.s new file mode 100644 index 0000000..c14b64e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_84.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a3, a0, a1 + or a0, a3, a0 + and a0, a2, a0 + xor a0, a0, a1 + and a0, a3, a0 + rem a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_85.s b/benchmarks/LLC_ASM_globalisel/7_function_85.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_85.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_86.s b/benchmarks/LLC_ASM_globalisel/7_function_86.s new file mode 100644 index 0000000..2e9114b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_86.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + rem a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_87.s b/benchmarks/LLC_ASM_globalisel/7_function_87.s new file mode 100644 index 0000000..f5b6ffc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_87.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + remu a3, a1, a1 + divu a0, a0, a3 + sra a1, a1, a3 + xor a2, a1, a2 + srl a1, a1, a2 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_88.s b/benchmarks/LLC_ASM_globalisel/7_function_88.s new file mode 100644 index 0000000..43f3185 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_88.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + sext.w a1, a2 +.LBB0_2: + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_89.s b/benchmarks/LLC_ASM_globalisel/7_function_89.s new file mode 100644 index 0000000..3f72e59 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_89.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a2 + divu a2, a2, a1 + and a0, a0, a1 + divu a0, a0, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_9.s b/benchmarks/LLC_ASM_globalisel/7_function_9.s new file mode 100644 index 0000000..7b956f6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_9.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + and a2, a1, a2 + remu a1, a2, a1 + srl a1, a0, a1 + or a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_90.s b/benchmarks/LLC_ASM_globalisel/7_function_90.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_90.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_91.s b/benchmarks/LLC_ASM_globalisel/7_function_91.s new file mode 100644 index 0000000..8dd7093 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_91.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a0, a1 + sra a1, a0, a1 + rem a0, a0, a1 + rem a0, a0, a2 + sext.w a3, a3 + remu a1, a3, a3 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_92.s b/benchmarks/LLC_ASM_globalisel/7_function_92.s new file mode 100644 index 0000000..77f300e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_92.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + and a0, a1, a0 + xor a0, a3, a0 + andi a1, a0, 1 + mv a0, a2 + bnez a1, .LBB0_2 +# %bb.1: + mv a0, a3 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_93.s b/benchmarks/LLC_ASM_globalisel/7_function_93.s new file mode 100644 index 0000000..619ef55 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_93.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + divu a0, a0, a1 + sext.w a0, a0 + xor a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_94.s b/benchmarks/LLC_ASM_globalisel/7_function_94.s new file mode 100644 index 0000000..923ae98 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_94.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + rem a2, a2, a2 + div a2, a2, a0 + rem a2, a0, a2 + srl a0, a2, a0 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_95.s b/benchmarks/LLC_ASM_globalisel/7_function_95.s new file mode 100644 index 0000000..583ed34 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_95.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a0, a0 + xor a0, a3, a0 + sra a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_96.s b/benchmarks/LLC_ASM_globalisel/7_function_96.s new file mode 100644 index 0000000..339e699 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_96.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a0, a0 + sra a3, a2, a0 + sra a3, a0, a3 + div a0, a0, a3 + xor a1, a2, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_97.s b/benchmarks/LLC_ASM_globalisel/7_function_97.s new file mode 100644 index 0000000..5c012b8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_97.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a0, a0 + srl a1, a2, a1 + xor a1, a2, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_98.s b/benchmarks/LLC_ASM_globalisel/7_function_98.s new file mode 100644 index 0000000..330e75c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_98.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a0 + bge a0, a3, .LBB0_2 +# %bb.1: + sra a2, a0, a1 +.LBB0_2: + and a0, a0, a2 + sra a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/7_function_99.s b/benchmarks/LLC_ASM_globalisel/7_function_99.s new file mode 100644 index 0000000..aeeb5b2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/7_function_99.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + div a1, a3, a1 + and a2, a0, a2 + div a2, a1, a2 + andi a2, a2, 1 + bnez a2, .LBB0_2 +# %bb.1: + sext.w a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_0.s b/benchmarks/LLC_ASM_globalisel/8_function_0.s new file mode 100644 index 0000000..c2fa0aa --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_0.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a0 + or a1, a1, a2 + divu a1, a1, a2 + sra a0, a0, a3 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_1.s b/benchmarks/LLC_ASM_globalisel/8_function_1.s new file mode 100644 index 0000000..bd7483e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_1.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a0 + rem a0, a3, a3 + andi a2, a2, 1 + sext.w a1, a1 + bnez a2, .LBB0_2 +# %bb.1: + mv a3, a1 +.LBB0_2: + rem a1, a1, a3 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_10.s b/benchmarks/LLC_ASM_globalisel/8_function_10.s new file mode 100644 index 0000000..6895722 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_10.s @@ -0,0 +1,33 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + divu a0, a0, a1 + or a1, a3, a0 + xor a1, a1, a2 + srl a3, a0, a2 + bge a3, a1, .LBB0_3 +# %bb.1: + andi a1, a1, 1 + beqz a1, .LBB0_4 +.LBB0_2: + ret +.LBB0_3: + mv a0, a1 + andi a1, a1, 1 + bnez a1, .LBB0_2 +.LBB0_4: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_11.s b/benchmarks/LLC_ASM_globalisel/8_function_11.s new file mode 100644 index 0000000..99e649f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_11.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a0, a2 + remu a2, a0, a2 + srl a0, a0, a1 + remu a1, a2, a0 + div a0, a0, a1 + zext.w a1, a3 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_12.s b/benchmarks/LLC_ASM_globalisel/8_function_12.s new file mode 100644 index 0000000..282950e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_12.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a1 + and a0, a0, a3 + div a0, a1, a0 + srl a1, a3, a2 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_13.s b/benchmarks/LLC_ASM_globalisel/8_function_13.s new file mode 100644 index 0000000..0e5c667 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_13.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a0, a0 + or a1, a2, a1 + and a0, a0, a1 + xor a0, a2, a0 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_14.s b/benchmarks/LLC_ASM_globalisel/8_function_14.s new file mode 100644 index 0000000..03a1be2 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_14.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a2 + divu a2, a0, a2 + remu a4, a2, a0 + andi a3, a3, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + srl a0, a1, a4 + remu a0, a4, a0 + sltu a0, a0, a2 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_15.s b/benchmarks/LLC_ASM_globalisel/8_function_15.s new file mode 100644 index 0000000..fc98646 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_15.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a4, a0, a1 + remu a1, a4, a1 + bltu a0, a1, .LBB0_2 +# %bb.1: + div a2, a0, a4 +.LBB0_2: + zext.w a0, a3 + and a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_16.s b/benchmarks/LLC_ASM_globalisel/8_function_16.s new file mode 100644 index 0000000..4d62b9f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_16.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + rem a3, a1, a2 + zext.w a3, a3 + remu a3, a0, a3 + remu a2, a3, a2 + or a0, a0, a1 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_17.s b/benchmarks/LLC_ASM_globalisel/8_function_17.s new file mode 100644 index 0000000..5c26205 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_17.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + remu a3, a0, a1 + remu a4, a1, a0 + div a0, a2, a0 + and a0, a4, a0 + xor a0, a1, a0 + sra a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_18.s b/benchmarks/LLC_ASM_globalisel/8_function_18.s new file mode 100644 index 0000000..e280863 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_18.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + srl a1, a1, a2 + remu a1, a0, a1 + srl a0, a0, a1 + zext.w a1, a2 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_19.s b/benchmarks/LLC_ASM_globalisel/8_function_19.s new file mode 100644 index 0000000..eba64ab --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_19.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + or a1, a0, a2 + remu a0, a1, a0 + andi a1, a0, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + sext.w a0, a2 + sltu a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_2.s b/benchmarks/LLC_ASM_globalisel/8_function_2.s new file mode 100644 index 0000000..3a7b862 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_2.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + remu a2, a2, a1 + srl a1, a1, a2 + and a0, a0, a1 + remu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_20.s b/benchmarks/LLC_ASM_globalisel/8_function_20.s new file mode 100644 index 0000000..28b8c01 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_20.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a1 + rem a2, a1, a2 + zext.w a3, a2 + srl a2, a3, a2 + divu a1, a1, a2 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_21.s b/benchmarks/LLC_ASM_globalisel/8_function_21.s new file mode 100644 index 0000000..001ad1f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_21.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a1 + rem a0, a0, a3 + divu a1, a2, a1 + and a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_22.s b/benchmarks/LLC_ASM_globalisel/8_function_22.s new file mode 100644 index 0000000..df67321 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_22.s @@ -0,0 +1,31 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a0, 1 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a0 + bnez a4, .LBB0_3 + j .LBB0_4 +.LBB0_2: + srl a3, a2, a1 + beqz a4, .LBB0_4 +.LBB0_3: + srl a0, a0, a0 + sra a0, a0, a2 + remu a3, a1, a0 +.LBB0_4: + mv a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_23.s b/benchmarks/LLC_ASM_globalisel/8_function_23.s new file mode 100644 index 0000000..e9399b7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_23.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + divu a0, a2, a0 + div a1, a1, a2 + zext.w a1, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_24.s b/benchmarks/LLC_ASM_globalisel/8_function_24.s new file mode 100644 index 0000000..1a3a5b4 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_24.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a2 + divu a2, a2, a3 + zext.w a1, a1 + srl a1, a1, a2 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_25.s b/benchmarks/LLC_ASM_globalisel/8_function_25.s new file mode 100644 index 0000000..3c6f913 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_25.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a1, 1 + mv a1, a0 + bnez a4, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + div a0, a0, a1 + srl a0, a0, a3 + srl a0, a0, a3 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_26.s b/benchmarks/LLC_ASM_globalisel/8_function_26.s new file mode 100644 index 0000000..62a826e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_26.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + divu a1, a0, a1 + and a2, a1, a2 + sra a2, a2, a1 + divu a1, a1, a2 + sra a0, a0, a1 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_27.s b/benchmarks/LLC_ASM_globalisel/8_function_27.s new file mode 100644 index 0000000..7028522 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_27.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + sra a1, a1, a0 + and a1, a0, a1 + srl a2, a0, a0 + sra a1, a1, a2 + sext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_28.s b/benchmarks/LLC_ASM_globalisel/8_function_28.s new file mode 100644 index 0000000..8763fef --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_28.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a0, a2 + j .LBB0_3 +.LBB0_2: + zext.w a0, a1 +.LBB0_3: + sra a0, a0, a1 + zext.w a1, a2 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_29.s b/benchmarks/LLC_ASM_globalisel/8_function_29.s new file mode 100644 index 0000000..6c33699 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_29.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a5, a2, a0 + and a4, a0, a1 + andi a6, a3, 1 + xor a3, a4, a5 + bnez a6, .LBB0_2 +# %bb.1: + xor a4, a2, a1 +.LBB0_2: + rem a1, a3, a4 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_3.s b/benchmarks/LLC_ASM_globalisel/8_function_3.s new file mode 100644 index 0000000..4e579ae --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_3.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + sra a1, a2, a1 + zext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_30.s b/benchmarks/LLC_ASM_globalisel/8_function_30.s new file mode 100644 index 0000000..689c43e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_30.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sgtz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_31.s b/benchmarks/LLC_ASM_globalisel/8_function_31.s new file mode 100644 index 0000000..69f7c13 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_31.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a2 + rem a1, a1, a3 + divu a3, a3, a1 + sext.w a2, a3 + srl a3, a3, a0 + bltu a2, a3, .LBB0_2 +# %bb.1: + rem a0, a2, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_32.s b/benchmarks/LLC_ASM_globalisel/8_function_32.s new file mode 100644 index 0000000..083122b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_32.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a0, 1 + mv a0, a2 + beqz a1, .LBB0_2 +# %bb.1: + srl a1, a0, a0 + srl a0, a0, a1 + sext.w a0, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_33.s b/benchmarks/LLC_ASM_globalisel/8_function_33.s new file mode 100644 index 0000000..141c7b6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_33.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + remu a1, a0, a1 + remu a0, a1, a2 + srl a1, a0, a1 + mv a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + remu a1, a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_34.s b/benchmarks/LLC_ASM_globalisel/8_function_34.s new file mode 100644 index 0000000..b5964d9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_34.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + rem a1, a0, a1 + div a1, a2, a1 + div a2, a0, a1 + or a0, a0, a1 + rem a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_35.s b/benchmarks/LLC_ASM_globalisel/8_function_35.s new file mode 100644 index 0000000..ce9c97d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_35.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a0 + div a1, a1, a2 + srl a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_36.s b/benchmarks/LLC_ASM_globalisel/8_function_36.s new file mode 100644 index 0000000..70c419b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_36.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a1, a2 + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + zext.w a0, a3 + remu a0, a0, a0 + xor a0, a1, a0 + rem a0, a0, a2 + div a2, a1, a0 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_37.s b/benchmarks/LLC_ASM_globalisel/8_function_37.s new file mode 100644 index 0000000..ca3cf75 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_37.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a3, a0, a1 + rem a0, a3, a0 + divu a1, a1, a0 + or a1, a2, a1 + xor a0, a0, a1 + remu a0, a3, a0 + remu a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_38.s b/benchmarks/LLC_ASM_globalisel/8_function_38.s new file mode 100644 index 0000000..aaac42b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_38.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bgeu a1, a0, .LBB0_2 +# %bb.1: + zext.w a0, a3 + ret +.LBB0_2: + divu a2, a1, a2 + or a1, a0, a1 + xor a1, a1, a2 + xor a0, a0, a1 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_39.s b/benchmarks/LLC_ASM_globalisel/8_function_39.s new file mode 100644 index 0000000..4f7b9be --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_39.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + sra a1, a0, a0 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + divu a0, a2, a2 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_4.s b/benchmarks/LLC_ASM_globalisel/8_function_4.s new file mode 100644 index 0000000..f4cde0a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_4.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a4, a0, a1 + srl a1, a2, a1 + andi a5, a3, 1 + sra a1, a4, a1 + mv a3, a2 + bnez a5, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + sra a0, a3, a1 + or a0, a1, a0 + remu a1, a2, a0 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_40.s b/benchmarks/LLC_ASM_globalisel/8_function_40.s new file mode 100644 index 0000000..b9ba493 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_40.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a2, a2 + or a1, a1, a2 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_41.s b/benchmarks/LLC_ASM_globalisel/8_function_41.s new file mode 100644 index 0000000..8660c3a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_41.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a2 + bge a0, a1, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + sra a2, a2, a3 + and a2, a0, a2 + bge a0, a1, .LBB0_4 +# %bb.3: + xor a2, a3, a2 + remu a2, a3, a2 +.LBB0_4: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_42.s b/benchmarks/LLC_ASM_globalisel/8_function_42.s new file mode 100644 index 0000000..60840ae --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_42.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + andi a3, a1, 1 + mv a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + srl a0, a1, a0 + zext.w a2, a0 + rem a1, a1, a2 + srl a0, a1, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_43.s b/benchmarks/LLC_ASM_globalisel/8_function_43.s new file mode 100644 index 0000000..e6cfb88 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_43.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + sext.w a0, a0 + mv a1, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + remu a2, a0, a2 + sra a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_44.s b/benchmarks/LLC_ASM_globalisel/8_function_44.s new file mode 100644 index 0000000..2d3dcd1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_44.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a0, a1 + remu a4, a3, a3 + div a0, a1, a0 + and a2, a2, a4 + zext.w a1, a3 + or a0, a2, a0 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_45.s b/benchmarks/LLC_ASM_globalisel/8_function_45.s new file mode 100644 index 0000000..79520df --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_45.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a0 + srl a0, a0, a0 + remu a0, a3, a0 + rem a2, a2, a0 + sra a0, a0, a1 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_46.s b/benchmarks/LLC_ASM_globalisel/8_function_46.s new file mode 100644 index 0000000..4d96e93 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_46.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a2 + div a1, a0, a1 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_47.s b/benchmarks/LLC_ASM_globalisel/8_function_47.s new file mode 100644 index 0000000..1bd17d3 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_47.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + beqz a2, .LBB0_2 +# %bb.1: + remw a1, a0, a0 +.LBB0_2: + rem a0, a1, zero + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_48.s b/benchmarks/LLC_ASM_globalisel/8_function_48.s new file mode 100644 index 0000000..139405d --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_48.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + div a4, a0, a3 + divu a0, a0, a2 + remu a2, a3, a1 + srl a0, a1, a0 + xor a0, a0, a2 + rem a0, a4, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_49.s b/benchmarks/LLC_ASM_globalisel/8_function_49.s new file mode 100644 index 0000000..f8d6435 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_49.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a3 + divu a3, a0, a3 + and a1, a1, a3 + andi a3, a2, 1 + mv a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + and a1, a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_5.s b/benchmarks/LLC_ASM_globalisel/8_function_5.s new file mode 100644 index 0000000..1756cec --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_5.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a3, a1, a1 + srl a1, a1, a2 + sext.w a1, a1 + rem a1, a3, a1 + sext.w a1, a1 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_50.s b/benchmarks/LLC_ASM_globalisel/8_function_50.s new file mode 100644 index 0000000..6d55fe0 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_50.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a1, a2 + sra a1, a0, a0 + divu a0, a1, a2 + andi a3, a3, 1 + bnez a3, .LBB0_2 +# %bb.1: + srl a0, a0, a0 + ret +.LBB0_2: + or a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_51.s b/benchmarks/LLC_ASM_globalisel/8_function_51.s new file mode 100644 index 0000000..01d424e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_51.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + div a0, a0, zero + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_52.s b/benchmarks/LLC_ASM_globalisel/8_function_52.s new file mode 100644 index 0000000..969d8f8 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_52.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + sext.w a1, a1 + remu a1, a0, a1 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_53.s b/benchmarks/LLC_ASM_globalisel/8_function_53.s new file mode 100644 index 0000000..0edc425 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_53.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + or a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_54.s b/benchmarks/LLC_ASM_globalisel/8_function_54.s new file mode 100644 index 0000000..41f93bd --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_54.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + sext.w a2, a2 + remu a1, a1, a2 + and a1, a1, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_55.s b/benchmarks/LLC_ASM_globalisel/8_function_55.s new file mode 100644 index 0000000..f6d685b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_55.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + divu a3, a2, a1 + or a2, a1, a2 + div a2, a2, a3 + divu a0, a0, a2 + remu a0, a1, a0 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_56.s b/benchmarks/LLC_ASM_globalisel/8_function_56.s new file mode 100644 index 0000000..1b35097 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_56.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a3, a1, a0 + div a1, a0, a1 + remu a2, a2, a3 + zext.w a0, a0 + div a0, a0, a2 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_57.s b/benchmarks/LLC_ASM_globalisel/8_function_57.s new file mode 100644 index 0000000..78546e7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_57.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a0, a1 + and a2, a0, a1 + bltu a2, a1, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + or a0, a1, a0 + slt a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_58.s b/benchmarks/LLC_ASM_globalisel/8_function_58.s new file mode 100644 index 0000000..0eab13b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_58.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a0 + and a0, a0, a1 + remu a1, a1, a0 + sext.w a0, a0 + zext.w a1, a1 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_59.s b/benchmarks/LLC_ASM_globalisel/8_function_59.s new file mode 100644 index 0000000..8ca94f6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_59.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a3, a0, a1 + divu a0, a2, a0 + sext.w a3, a3 + divu a2, a3, a0 + rem a0, a0, a1 + rem a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_6.s b/benchmarks/LLC_ASM_globalisel/8_function_6.s new file mode 100644 index 0000000..db5fbd1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_6.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a3, 1 + zext.w a0, a0 + mv a3, a2 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + or a2, a2, a3 + rem a3, a2, a3 + xor a3, a2, a3 + divu a2, a3, a2 + rem a1, a1, a2 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_60.s b/benchmarks/LLC_ASM_globalisel/8_function_60.s new file mode 100644 index 0000000..5020772 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_60.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a1, 1 + sext.w a3, a0 + bnez a4, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + rem a1, a1, a2 + xor a0, a0, a1 + div a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_61.s b/benchmarks/LLC_ASM_globalisel/8_function_61.s new file mode 100644 index 0000000..72d636a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_61.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + rem a3, a0, a1 + xor a1, a1, a2 + xor a1, a1, a3 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_62.s b/benchmarks/LLC_ASM_globalisel/8_function_62.s new file mode 100644 index 0000000..b3619ff --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_62.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a2 + div a1, a1, a2 + zext.w a0, a0 + xor a0, a0, a1 + sra a0, a0, a2 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_63.s b/benchmarks/LLC_ASM_globalisel/8_function_63.s new file mode 100644 index 0000000..d85768e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_63.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a4, a1, a0 + srl a3, a1, a2 + div a3, a4, a3 + bgeu a2, a4, .LBB0_2 +# %bb.1: + mv a1, a3 +.LBB0_2: + remu a0, a0, a1 + srl a1, a3, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_64.s b/benchmarks/LLC_ASM_globalisel/8_function_64.s new file mode 100644 index 0000000..1b5c062 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_64.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a3, a2, a0 + div a3, a3, a2 + divu a2, a1, a2 + remu a2, a2, a3 + srl a0, a0, a1 + rem a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_65.s b/benchmarks/LLC_ASM_globalisel/8_function_65.s new file mode 100644 index 0000000..804e8e6 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_65.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + srl a0, a0, a1 + zext.w a0, a0 + rem a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_66.s b/benchmarks/LLC_ASM_globalisel/8_function_66.s new file mode 100644 index 0000000..d0af19b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_66.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + rem a0, a0, a0 + div a2, a0, a2 + zext.w a2, a2 + rem a1, a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_67.s b/benchmarks/LLC_ASM_globalisel/8_function_67.s new file mode 100644 index 0000000..a16b5df --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_67.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + and a0, a2, a0 + or a0, a2, a0 + or a0, a0, a1 + div a2, a1, a0 + and a0, a0, a2 + or a0, a1, a0 + sltu a0, a0, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_68.s b/benchmarks/LLC_ASM_globalisel/8_function_68.s new file mode 100644 index 0000000..6a1b55f --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_68.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a0, a0 + divu a0, a0, a2 + rem a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_69.s b/benchmarks/LLC_ASM_globalisel/8_function_69.s new file mode 100644 index 0000000..5b5d371 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_69.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + divu a1, a2, a2 + div a3, a0, a1 + rem a0, a0, a0 + or a0, a1, a0 + div a0, a1, a0 + div a0, a0, a2 + rem a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_7.s b/benchmarks/LLC_ASM_globalisel/8_function_7.s new file mode 100644 index 0000000..b84ec79 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_7.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + and a4, a1, a0 + remu a0, a0, a4 + andi a3, a3, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a4, a0 +.LBB0_2: + and a1, a1, a4 + and a1, a0, a1 + remu a1, a2, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_70.s b/benchmarks/LLC_ASM_globalisel/8_function_70.s new file mode 100644 index 0000000..beec40a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_70.s @@ -0,0 +1,32 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a2 + mv a2, a3 + bne a3, a0, .LBB0_3 +# %bb.1: + andi a1, a1, 1 + beqz a1, .LBB0_4 +.LBB0_2: + srl a0, a0, a2 + ret +.LBB0_3: + mv a2, a0 + andi a1, a1, 1 + bnez a1, .LBB0_2 +.LBB0_4: + srl a2, a0, a3 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_71.s b/benchmarks/LLC_ASM_globalisel/8_function_71.s new file mode 100644 index 0000000..a98ceec --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_71.s @@ -0,0 +1,34 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + bge a1, a0, .LBB0_4 +# %bb.1: + andi a1, a0, 1 + beqz a1, .LBB0_5 +.LBB0_2: + beqz a1, .LBB0_6 +.LBB0_3: + ret +.LBB0_4: + mv a0, a2 + andi a1, a2, 1 + bnez a1, .LBB0_2 +.LBB0_5: + srl a2, a3, a0 + bnez a1, .LBB0_3 +.LBB0_6: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_72.s b/benchmarks/LLC_ASM_globalisel/8_function_72.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_72.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_73.s b/benchmarks/LLC_ASM_globalisel/8_function_73.s new file mode 100644 index 0000000..79a4d4a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_73.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + sext.w a1, a1 + divu a0, a0, a1 + divu a1, a0, a0 + xor a1, a1, a0 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_74.s b/benchmarks/LLC_ASM_globalisel/8_function_74.s new file mode 100644 index 0000000..c8b4c21 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_74.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a0 + andi a3, a0, 1 + bnez a3, .LBB0_2 +# %bb.1: + and a0, a1, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_75.s b/benchmarks/LLC_ASM_globalisel/8_function_75.s new file mode 100644 index 0000000..9a9fef9 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_75.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_76.s b/benchmarks/LLC_ASM_globalisel/8_function_76.s new file mode 100644 index 0000000..e7c4a3b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_76.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a0 + div a1, a3, a1 + andi a3, a2, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_77.s b/benchmarks/LLC_ASM_globalisel/8_function_77.s new file mode 100644 index 0000000..114d654 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_77.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + xor a3, a3, a1 + andi a4, a2, 1 + mv a2, a3 + bnez a4, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + div a1, a1, a0 + rem a1, a2, a1 + or a0, a0, a1 + xor a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_78.s b/benchmarks/LLC_ASM_globalisel/8_function_78.s new file mode 100644 index 0000000..30239d5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_78.s @@ -0,0 +1,32 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a3, 1 + mv a3, a1 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a2 +.LBB0_2: + zext.w a0, a0 + or a1, a1, a2 + bnez a4, .LBB0_4 +# %bb.3: + mv a2, a3 +.LBB0_4: + div a3, a3, a0 + srl a2, a2, a3 + remu a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_79.s b/benchmarks/LLC_ASM_globalisel/8_function_79.s new file mode 100644 index 0000000..6cb1ba5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_79.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a0 + andi a4, a2, 1 + sext.w a2, a3 + bnez a4, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + zext.w a0, a0 + div a0, a1, a0 + sltu a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_8.s b/benchmarks/LLC_ASM_globalisel/8_function_8.s new file mode 100644 index 0000000..1160601 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_8.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a4, a0, a1 + zext.w a3, a3 + and a4, a0, a4 + and a0, a3, a0 + xor a2, a4, a2 + or a0, a1, a0 + xor a0, a2, a0 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_80.s b/benchmarks/LLC_ASM_globalisel/8_function_80.s new file mode 100644 index 0000000..2551106 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_80.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + remu a3, a2, a2 + srl a2, a2, a3 + rem a1, a1, a2 + srl a1, a2, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_81.s b/benchmarks/LLC_ASM_globalisel/8_function_81.s new file mode 100644 index 0000000..fa5e210 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_81.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + div a2, a2, a1 + sra a2, a0, a2 + and a0, a2, a0 + div a1, a0, a1 + div a1, a2, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_82.s b/benchmarks/LLC_ASM_globalisel/8_function_82.s new file mode 100644 index 0000000..05bb698 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_82.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + min a0, a1, a0 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_83.s b/benchmarks/LLC_ASM_globalisel/8_function_83.s new file mode 100644 index 0000000..c40c58a --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_83.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a0 + div a0, a0, a1 + remu a1, a2, a0 + sra a0, a2, a0 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_84.s b/benchmarks/LLC_ASM_globalisel/8_function_84.s new file mode 100644 index 0000000..ef143c5 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_84.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + rem a1, a0, a1 + sext.w a0, a0 + sext.w a1, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_85.s b/benchmarks/LLC_ASM_globalisel/8_function_85.s new file mode 100644 index 0000000..6ec9855 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_85.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + remu a1, a0, a2 + divu a0, a2, a0 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_86.s b/benchmarks/LLC_ASM_globalisel/8_function_86.s new file mode 100644 index 0000000..c018750 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_86.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + srl a0, a0, a2 + and a1, a1, a0 + sext.w a1, a1 + xor a0, a0, a1 + slt a0, a0, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_87.s b/benchmarks/LLC_ASM_globalisel/8_function_87.s new file mode 100644 index 0000000..eb09cd7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_87.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + remu a0, a0, a1 + srl a0, a0, a1 + sra a0, a0, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_88.s b/benchmarks/LLC_ASM_globalisel/8_function_88.s new file mode 100644 index 0000000..345cf1c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_88.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a0 + xor a4, a1, a2 + xor a5, a0, a3 + xor a3, a3, a4 + div a3, a5, a3 + rem a1, a3, a1 + xor a0, a2, a0 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_89.s b/benchmarks/LLC_ASM_globalisel/8_function_89.s new file mode 100644 index 0000000..6e437cc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_89.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a0, a1 + and a0, a1, a0 + div a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_9.s b/benchmarks/LLC_ASM_globalisel/8_function_9.s new file mode 100644 index 0000000..491fbdb --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_9.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + sext.w a2, a2 + remu a2, a2, a0 + and a1, a0, a1 + divu a2, a2, a1 + rem a1, a2, a1 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_90.s b/benchmarks/LLC_ASM_globalisel/8_function_90.s new file mode 100644 index 0000000..7f3523e --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_90.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a1 + sext.w a1, a3 + beq a3, a1, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_91.s b/benchmarks/LLC_ASM_globalisel/8_function_91.s new file mode 100644 index 0000000..5e7fe57 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_91.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a0, a0 + or a2, a0, a2 + xor a0, a2, a0 + divu a0, a2, a0 + div a0, a0, a1 + sext.w a0, a0 + slt a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_92.s b/benchmarks/LLC_ASM_globalisel/8_function_92.s new file mode 100644 index 0000000..7844393 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_92.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + mv a0, a1 + bnez a2, .LBB0_2 +# %bb.1: + divu a0, a1, a1 + or a0, a1, a0 +.LBB0_2: + sext.w a0, a0 + and a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_93.s b/benchmarks/LLC_ASM_globalisel/8_function_93.s new file mode 100644 index 0000000..4467cec --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_93.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a1, a2 + andi a3, a0, 1 + sext.w a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + divu a0, a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_94.s b/benchmarks/LLC_ASM_globalisel/8_function_94.s new file mode 100644 index 0000000..f13f3b1 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_94.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a1 + sext.w a3, a3 + blt a1, a0, .LBB0_2 +# %bb.1: + sra a0, a2, a0 + rem a0, a0, a3 +.LBB0_2: + rem a1, a2, a3 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_95.s b/benchmarks/LLC_ASM_globalisel/8_function_95.s new file mode 100644 index 0000000..58ce6bc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_95.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a3, a0, a1 + mv a0, a1 + bgeu a3, a2, .LBB0_2 +# %bb.1: + remu a0, a2, a1 +.LBB0_2: + divu a1, a1, a3 + sra a1, a0, a1 + divu a1, a0, a1 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_96.s b/benchmarks/LLC_ASM_globalisel/8_function_96.s new file mode 100644 index 0000000..a7d560b --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_96.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + rem a0, a0, a1 + remu a1, a2, a2 + zext.w a0, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_97.s b/benchmarks/LLC_ASM_globalisel/8_function_97.s new file mode 100644 index 0000000..14d9de7 --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_97.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + zext.w a3, a2 + remu a3, a3, a1 + xor a0, a0, a1 + or a0, a0, a3 + sext.w a2, a2 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_98.s b/benchmarks/LLC_ASM_globalisel/8_function_98.s new file mode 100644 index 0000000..2a9e6cc --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_98.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + rem a3, a0, a1 + divu a1, a1, a2 + xor a3, a3, a0 + sra a1, a3, a1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_globalisel/8_function_99.s b/benchmarks/LLC_ASM_globalisel/8_function_99.s new file mode 100644 index 0000000..b52a68c --- /dev/null +++ b/benchmarks/LLC_ASM_globalisel/8_function_99.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a2 + srl a3, a1, a0 + div a1, a1, a3 + mv a3, a1 + bltu a0, a0, .LBB0_2 +# %bb.1: + mv a3, a2 +.LBB0_2: + xor a0, a3, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_0.s b/benchmarks/LLC_ASM_selectiondag/3_function_0.s new file mode 100644 index 0000000..d822e25 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_0.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_1.s b/benchmarks/LLC_ASM_selectiondag/3_function_1.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_1.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_10.s b/benchmarks/LLC_ASM_selectiondag/3_function_10.s new file mode 100644 index 0000000..87fe679 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_10.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_11.s b/benchmarks/LLC_ASM_selectiondag/3_function_11.s new file mode 100644 index 0000000..07455d0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_11.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_12.s b/benchmarks/LLC_ASM_selectiondag/3_function_12.s new file mode 100644 index 0000000..f078b2e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_12.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bext a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_13.s b/benchmarks/LLC_ASM_selectiondag/3_function_13.s new file mode 100644 index 0000000..58941d5 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_13.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a1, a2 + and a1, a1, a2 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_14.s b/benchmarks/LLC_ASM_selectiondag/3_function_14.s new file mode 100644 index 0000000..c1611e6 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_14.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + rem a0, a2, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_15.s b/benchmarks/LLC_ASM_selectiondag/3_function_15.s new file mode 100644 index 0000000..6256a1b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_15.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_16.s b/benchmarks/LLC_ASM_selectiondag/3_function_16.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_16.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_17.s b/benchmarks/LLC_ASM_selectiondag/3_function_17.s new file mode 100644 index 0000000..0a370b0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_17.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a1, a2 + sext.w a0, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_18.s b/benchmarks/LLC_ASM_selectiondag/3_function_18.s new file mode 100644 index 0000000..674ae91 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_18.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_19.s b/benchmarks/LLC_ASM_selectiondag/3_function_19.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_19.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_2.s b/benchmarks/LLC_ASM_selectiondag/3_function_2.s new file mode 100644 index 0000000..de95d3a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_2.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_20.s b/benchmarks/LLC_ASM_selectiondag/3_function_20.s new file mode 100644 index 0000000..a64ad53 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_20.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_21.s b/benchmarks/LLC_ASM_selectiondag/3_function_21.s new file mode 100644 index 0000000..f703d96 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_21.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + xor a0, a0, a1 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_22.s b/benchmarks/LLC_ASM_selectiondag/3_function_22.s new file mode 100644 index 0000000..b9dc370 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_22.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_23.s b/benchmarks/LLC_ASM_selectiondag/3_function_23.s new file mode 100644 index 0000000..7412212 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_23.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + slli a0, a0, 63 + srai a0, a0, 63 + and a0, a0, a2 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_24.s b/benchmarks/LLC_ASM_selectiondag/3_function_24.s new file mode 100644 index 0000000..290c4eb --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_24.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + mv a0, a1 + bnez a2, .LBB0_2 +# %bb.1: + sext.w a0, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_25.s b/benchmarks/LLC_ASM_selectiondag/3_function_25.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_25.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_26.s b/benchmarks/LLC_ASM_selectiondag/3_function_26.s new file mode 100644 index 0000000..bcd6682 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_26.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a0 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_27.s b/benchmarks/LLC_ASM_selectiondag/3_function_27.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_27.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_28.s b/benchmarks/LLC_ASM_selectiondag/3_function_28.s new file mode 100644 index 0000000..e8a16ca --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_28.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + addi a0, a0, -1 + and a0, a0, a2 + or a0, a1, a0 + xor a0, a0, a2 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_29.s b/benchmarks/LLC_ASM_selectiondag/3_function_29.s new file mode 100644 index 0000000..fbde7a2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_29.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_3.s b/benchmarks/LLC_ASM_selectiondag/3_function_3.s new file mode 100644 index 0000000..1b01486 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_3.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + xor a2, a0, a2 + slt a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_30.s b/benchmarks/LLC_ASM_selectiondag/3_function_30.s new file mode 100644 index 0000000..c7ce435 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_30.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + or a1, a0, a1 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_31.s b/benchmarks/LLC_ASM_selectiondag/3_function_31.s new file mode 100644 index 0000000..22d8d77 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_31.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_32.s b/benchmarks/LLC_ASM_selectiondag/3_function_32.s new file mode 100644 index 0000000..b05c66a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_32.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_33.s b/benchmarks/LLC_ASM_selectiondag/3_function_33.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_33.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_34.s b/benchmarks/LLC_ASM_selectiondag/3_function_34.s new file mode 100644 index 0000000..986d8b9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_34.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_35.s b/benchmarks/LLC_ASM_selectiondag/3_function_35.s new file mode 100644 index 0000000..7f50d5e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_35.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + xor a1, a1, a2 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_36.s b/benchmarks/LLC_ASM_selectiondag/3_function_36.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_36.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_37.s b/benchmarks/LLC_ASM_selectiondag/3_function_37.s new file mode 100644 index 0000000..1de9989 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_37.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_38.s b/benchmarks/LLC_ASM_selectiondag/3_function_38.s new file mode 100644 index 0000000..2027781 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_38.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + slt a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_39.s b/benchmarks/LLC_ASM_selectiondag/3_function_39.s new file mode 100644 index 0000000..fb3371f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_39.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + rem a0, a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_4.s b/benchmarks/LLC_ASM_selectiondag/3_function_4.s new file mode 100644 index 0000000..f790059 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_4.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_40.s b/benchmarks/LLC_ASM_selectiondag/3_function_40.s new file mode 100644 index 0000000..4258a8b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_40.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_41.s b/benchmarks/LLC_ASM_selectiondag/3_function_41.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_41.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_42.s b/benchmarks/LLC_ASM_selectiondag/3_function_42.s new file mode 100644 index 0000000..7fdc11e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_42.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_43.s b/benchmarks/LLC_ASM_selectiondag/3_function_43.s new file mode 100644 index 0000000..23f295d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_43.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_44.s b/benchmarks/LLC_ASM_selectiondag/3_function_44.s new file mode 100644 index 0000000..148391c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_44.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + sra a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_45.s b/benchmarks/LLC_ASM_selectiondag/3_function_45.s new file mode 100644 index 0000000..ad6ce64 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_45.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a0 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_46.s b/benchmarks/LLC_ASM_selectiondag/3_function_46.s new file mode 100644 index 0000000..047aa2e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_46.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + div a1, a2, a0 + xor a0, a0, a1 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_47.s b/benchmarks/LLC_ASM_selectiondag/3_function_47.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_47.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_48.s b/benchmarks/LLC_ASM_selectiondag/3_function_48.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_48.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_49.s b/benchmarks/LLC_ASM_selectiondag/3_function_49.s new file mode 100644 index 0000000..4ad50ab --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_49.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xori a0, a1, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_5.s b/benchmarks/LLC_ASM_selectiondag/3_function_5.s new file mode 100644 index 0000000..c2132b2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_5.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a1, a2 + sra a0, a0, a2 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_50.s b/benchmarks/LLC_ASM_selectiondag/3_function_50.s new file mode 100644 index 0000000..e1fb2c9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_50.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_51.s b/benchmarks/LLC_ASM_selectiondag/3_function_51.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_51.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_52.s b/benchmarks/LLC_ASM_selectiondag/3_function_52.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_52.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_53.s b/benchmarks/LLC_ASM_selectiondag/3_function_53.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_53.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_54.s b/benchmarks/LLC_ASM_selectiondag/3_function_54.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_54.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_55.s b/benchmarks/LLC_ASM_selectiondag/3_function_55.s new file mode 100644 index 0000000..fac631f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_55.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_56.s b/benchmarks/LLC_ASM_selectiondag/3_function_56.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_56.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_57.s b/benchmarks/LLC_ASM_selectiondag/3_function_57.s new file mode 100644 index 0000000..4d90986 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_57.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sltu a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_58.s b/benchmarks/LLC_ASM_selectiondag/3_function_58.s new file mode 100644 index 0000000..c33c4bc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_58.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_59.s b/benchmarks/LLC_ASM_selectiondag/3_function_59.s new file mode 100644 index 0000000..6bc3076 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_59.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a1, a0 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_6.s b/benchmarks/LLC_ASM_selectiondag/3_function_6.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_6.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_60.s b/benchmarks/LLC_ASM_selectiondag/3_function_60.s new file mode 100644 index 0000000..46b1bad --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_60.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a0 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_61.s b/benchmarks/LLC_ASM_selectiondag/3_function_61.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_61.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_62.s b/benchmarks/LLC_ASM_selectiondag/3_function_62.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_62.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_63.s b/benchmarks/LLC_ASM_selectiondag/3_function_63.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_63.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_64.s b/benchmarks/LLC_ASM_selectiondag/3_function_64.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_64.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_65.s b/benchmarks/LLC_ASM_selectiondag/3_function_65.s new file mode 100644 index 0000000..467c277 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_65.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_66.s b/benchmarks/LLC_ASM_selectiondag/3_function_66.s new file mode 100644 index 0000000..d6333ad --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_66.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_67.s b/benchmarks/LLC_ASM_selectiondag/3_function_67.s new file mode 100644 index 0000000..cbf2456 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_67.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + or a1, a1, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_68.s b/benchmarks/LLC_ASM_selectiondag/3_function_68.s new file mode 100644 index 0000000..a709765 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_68.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_69.s b/benchmarks/LLC_ASM_selectiondag/3_function_69.s new file mode 100644 index 0000000..ee838e1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_69.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + xor a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_7.s b/benchmarks/LLC_ASM_selectiondag/3_function_7.s new file mode 100644 index 0000000..0e5662b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_7.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a2 + srl a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_70.s b/benchmarks/LLC_ASM_selectiondag/3_function_70.s new file mode 100644 index 0000000..9a0b92f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_70.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_71.s b/benchmarks/LLC_ASM_selectiondag/3_function_71.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_71.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_72.s b/benchmarks/LLC_ASM_selectiondag/3_function_72.s new file mode 100644 index 0000000..a98ad00 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_72.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + slti a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_73.s b/benchmarks/LLC_ASM_selectiondag/3_function_73.s new file mode 100644 index 0000000..b6f393c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_73.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_74.s b/benchmarks/LLC_ASM_selectiondag/3_function_74.s new file mode 100644 index 0000000..2061c9b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_74.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_75.s b/benchmarks/LLC_ASM_selectiondag/3_function_75.s new file mode 100644 index 0000000..c2a765d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_75.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + srl a0, a0, a1 + addi a0, a0, -1 + andi a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_76.s b/benchmarks/LLC_ASM_selectiondag/3_function_76.s new file mode 100644 index 0000000..f47aca4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_76.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_77.s b/benchmarks/LLC_ASM_selectiondag/3_function_77.s new file mode 100644 index 0000000..de083f8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_77.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a0 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_78.s b/benchmarks/LLC_ASM_selectiondag/3_function_78.s new file mode 100644 index 0000000..297a7fe --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_78.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_79.s b/benchmarks/LLC_ASM_selectiondag/3_function_79.s new file mode 100644 index 0000000..2cf5c90 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_79.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_8.s b/benchmarks/LLC_ASM_selectiondag/3_function_8.s new file mode 100644 index 0000000..a86073c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_8.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a1, a2 + slti a0, a1, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_80.s b/benchmarks/LLC_ASM_selectiondag/3_function_80.s new file mode 100644 index 0000000..9b323ea --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_80.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + slti a0, a1, 2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_81.s b/benchmarks/LLC_ASM_selectiondag/3_function_81.s new file mode 100644 index 0000000..e4e1693 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_81.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a2 + bge a3, a1, .LBB0_2 +# %bb.1: + mv a0, a3 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_82.s b/benchmarks/LLC_ASM_selectiondag/3_function_82.s new file mode 100644 index 0000000..869b645 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_82.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_83.s b/benchmarks/LLC_ASM_selectiondag/3_function_83.s new file mode 100644 index 0000000..33a9a84 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_83.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bgeu a1, a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_84.s b/benchmarks/LLC_ASM_selectiondag/3_function_84.s new file mode 100644 index 0000000..bd910af --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_84.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_85.s b/benchmarks/LLC_ASM_selectiondag/3_function_85.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_85.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_86.s b/benchmarks/LLC_ASM_selectiondag/3_function_86.s new file mode 100644 index 0000000..d467cd4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_86.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + beqz a0, .LBB0_2 +# %bb.1: + zext.w a2, a1 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_87.s b/benchmarks/LLC_ASM_selectiondag/3_function_87.s new file mode 100644 index 0000000..eb1ebcf --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_87.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bltu a1, a0, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_88.s b/benchmarks/LLC_ASM_selectiondag/3_function_88.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_88.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_89.s b/benchmarks/LLC_ASM_selectiondag/3_function_89.s new file mode 100644 index 0000000..0184ec1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_89.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + zext.w a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_9.s b/benchmarks/LLC_ASM_selectiondag/3_function_9.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_9.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_90.s b/benchmarks/LLC_ASM_selectiondag/3_function_90.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_90.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_91.s b/benchmarks/LLC_ASM_selectiondag/3_function_91.s new file mode 100644 index 0000000..11d4bc5 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_91.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_92.s b/benchmarks/LLC_ASM_selectiondag/3_function_92.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_92.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_93.s b/benchmarks/LLC_ASM_selectiondag/3_function_93.s new file mode 100644 index 0000000..9b55a2b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_93.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bgeu a1, a0, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + slt a0, a0, a2 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_94.s b/benchmarks/LLC_ASM_selectiondag/3_function_94.s new file mode 100644 index 0000000..2c5c07d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_94.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_95.s b/benchmarks/LLC_ASM_selectiondag/3_function_95.s new file mode 100644 index 0000000..ff86cf2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_95.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a1, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_96.s b/benchmarks/LLC_ASM_selectiondag/3_function_96.s new file mode 100644 index 0000000..455de36 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_96.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + sext.w a2, a2 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_97.s b/benchmarks/LLC_ASM_selectiondag/3_function_97.s new file mode 100644 index 0000000..e261c80 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_97.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + addi a2, a2, -1 + and a1, a2, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_98.s b/benchmarks/LLC_ASM_selectiondag/3_function_98.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_98.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/3_function_99.s b/benchmarks/LLC_ASM_selectiondag/3_function_99.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/3_function_99.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_0.s b/benchmarks/LLC_ASM_selectiondag/4_function_0.s new file mode 100644 index 0000000..d3d2da6 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_0.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + and a0, a0, a1 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_1.s b/benchmarks/LLC_ASM_selectiondag/4_function_1.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_1.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_10.s b/benchmarks/LLC_ASM_selectiondag/4_function_10.s new file mode 100644 index 0000000..b4c706d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_10.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_11.s b/benchmarks/LLC_ASM_selectiondag/4_function_11.s new file mode 100644 index 0000000..bb85664 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_11.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_12.s b/benchmarks/LLC_ASM_selectiondag/4_function_12.s new file mode 100644 index 0000000..5b60342 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_12.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_13.s b/benchmarks/LLC_ASM_selectiondag/4_function_13.s new file mode 100644 index 0000000..dd492bf --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_13.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sltiu a0, a0, 2 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_14.s b/benchmarks/LLC_ASM_selectiondag/4_function_14.s new file mode 100644 index 0000000..c594503 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_14.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + remu a0, a0, a1 + divu a0, a2, a0 + remu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_15.s b/benchmarks/LLC_ASM_selectiondag/4_function_15.s new file mode 100644 index 0000000..2ee8e28 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_15.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_16.s b/benchmarks/LLC_ASM_selectiondag/4_function_16.s new file mode 100644 index 0000000..8cb8596 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_16.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + xor a1, a0, a1 + rem a0, a1, a0 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_17.s b/benchmarks/LLC_ASM_selectiondag/4_function_17.s new file mode 100644 index 0000000..09c4acc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_17.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + sext.w a2, a2 + divu a0, a2, a1 +.LBB0_2: + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_18.s b/benchmarks/LLC_ASM_selectiondag/4_function_18.s new file mode 100644 index 0000000..9dee7ce --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_18.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_19.s b/benchmarks/LLC_ASM_selectiondag/4_function_19.s new file mode 100644 index 0000000..11ef7f8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_19.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_2.s b/benchmarks/LLC_ASM_selectiondag/4_function_2.s new file mode 100644 index 0000000..1194267 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_2.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_20.s b/benchmarks/LLC_ASM_selectiondag/4_function_20.s new file mode 100644 index 0000000..b03ad8f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_20.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + addi a1, a1, -1 + and a1, a3, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_21.s b/benchmarks/LLC_ASM_selectiondag/4_function_21.s new file mode 100644 index 0000000..9c00977 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_21.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a2 + slt a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_22.s b/benchmarks/LLC_ASM_selectiondag/4_function_22.s new file mode 100644 index 0000000..9568a56 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_22.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + srl a0, a0, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_23.s b/benchmarks/LLC_ASM_selectiondag/4_function_23.s new file mode 100644 index 0000000..4f0db18 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_23.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + add.uw a1, a1, a2 + sext.w a0, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_24.s b/benchmarks/LLC_ASM_selectiondag/4_function_24.s new file mode 100644 index 0000000..40793da --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_24.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + rem a1, a0, a1 + mv a0, a2 + bnez a1, .LBB0_2 +# %bb.1: + li a0, 1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_25.s b/benchmarks/LLC_ASM_selectiondag/4_function_25.s new file mode 100644 index 0000000..b0df429 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_25.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + beqz a1, .LBB0_2 +# %bb.1: + sra a2, a0, a2 +.LBB0_2: + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_26.s b/benchmarks/LLC_ASM_selectiondag/4_function_26.s new file mode 100644 index 0000000..9400254 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_26.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + beqz a3, .LBB0_3 +# %bb.1: + bne a0, a2, .LBB0_4 +.LBB0_2: + xor a0, a0, a2 + ret +.LBB0_3: + mv a0, a2 + beq a2, a2, .LBB0_2 +.LBB0_4: + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_27.s b/benchmarks/LLC_ASM_selectiondag/4_function_27.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_27.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_28.s b/benchmarks/LLC_ASM_selectiondag/4_function_28.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_28.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_29.s b/benchmarks/LLC_ASM_selectiondag/4_function_29.s new file mode 100644 index 0000000..b874e8a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_29.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a2 + rem a1, a0, a1 + xor a0, a1, a0 + slt a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_3.s b/benchmarks/LLC_ASM_selectiondag/4_function_3.s new file mode 100644 index 0000000..68a2a54 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_3.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + andi a3, a2, 1 + mv a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + srl a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_30.s b/benchmarks/LLC_ASM_selectiondag/4_function_30.s new file mode 100644 index 0000000..e066583 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_30.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + sext.w a0, a0 + sltu a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_31.s b/benchmarks/LLC_ASM_selectiondag/4_function_31.s new file mode 100644 index 0000000..4dc8bd2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_31.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + sra a0, a0, a2 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_32.s b/benchmarks/LLC_ASM_selectiondag/4_function_32.s new file mode 100644 index 0000000..c66e1a7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_32.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + remu a0, a0, a0 + ret +.LBB0_2: + sext.w a2, a2 + remu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_33.s b/benchmarks/LLC_ASM_selectiondag/4_function_33.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_33.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_34.s b/benchmarks/LLC_ASM_selectiondag/4_function_34.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_34.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_35.s b/benchmarks/LLC_ASM_selectiondag/4_function_35.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_35.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_36.s b/benchmarks/LLC_ASM_selectiondag/4_function_36.s new file mode 100644 index 0000000..3c6288a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_36.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + remu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_37.s b/benchmarks/LLC_ASM_selectiondag/4_function_37.s new file mode 100644 index 0000000..fe9ec2e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_37.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a0 + and a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_38.s b/benchmarks/LLC_ASM_selectiondag/4_function_38.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_38.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_39.s b/benchmarks/LLC_ASM_selectiondag/4_function_39.s new file mode 100644 index 0000000..e74486e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_39.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_4.s b/benchmarks/LLC_ASM_selectiondag/4_function_4.s new file mode 100644 index 0000000..6648ca2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_4.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a2 + or a0, a0, a1 + xor a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_40.s b/benchmarks/LLC_ASM_selectiondag/4_function_40.s new file mode 100644 index 0000000..08cecae --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_40.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + divu a0, a0, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_41.s b/benchmarks/LLC_ASM_selectiondag/4_function_41.s new file mode 100644 index 0000000..9d79135 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_41.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a0 + rem a1, a1, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_42.s b/benchmarks/LLC_ASM_selectiondag/4_function_42.s new file mode 100644 index 0000000..4267830 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_42.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + rem a1, a0, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_43.s b/benchmarks/LLC_ASM_selectiondag/4_function_43.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_43.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_44.s b/benchmarks/LLC_ASM_selectiondag/4_function_44.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_44.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_45.s b/benchmarks/LLC_ASM_selectiondag/4_function_45.s new file mode 100644 index 0000000..56939e3 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_45.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a2, 1 + or a1, a0, a1 + bnez a2, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_46.s b/benchmarks/LLC_ASM_selectiondag/4_function_46.s new file mode 100644 index 0000000..a66f43b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_46.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + xor a1, a1, a2 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_47.s b/benchmarks/LLC_ASM_selectiondag/4_function_47.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_47.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_48.s b/benchmarks/LLC_ASM_selectiondag/4_function_48.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_48.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_49.s b/benchmarks/LLC_ASM_selectiondag/4_function_49.s new file mode 100644 index 0000000..10cdac0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_49.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a2 + srl a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_5.s b/benchmarks/LLC_ASM_selectiondag/4_function_5.s new file mode 100644 index 0000000..d0fac87 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_5.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_50.s b/benchmarks/LLC_ASM_selectiondag/4_function_50.s new file mode 100644 index 0000000..ea637df --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_50.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a0 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_51.s b/benchmarks/LLC_ASM_selectiondag/4_function_51.s new file mode 100644 index 0000000..a827847 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_51.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + srl a0, a1, a0 + divu a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_52.s b/benchmarks/LLC_ASM_selectiondag/4_function_52.s new file mode 100644 index 0000000..d97a6aa --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_52.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + srl a0, a0, a2 + srli a0, a0, 63 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_53.s b/benchmarks/LLC_ASM_selectiondag/4_function_53.s new file mode 100644 index 0000000..5f14e48 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_53.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_54.s b/benchmarks/LLC_ASM_selectiondag/4_function_54.s new file mode 100644 index 0000000..a94ed42 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_54.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a0, a2 + divu a1, a1, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_55.s b/benchmarks/LLC_ASM_selectiondag/4_function_55.s new file mode 100644 index 0000000..d6a7823 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_55.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a2, a0 + and a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_56.s b/benchmarks/LLC_ASM_selectiondag/4_function_56.s new file mode 100644 index 0000000..cea805a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_56.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + srl a1, a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a1 +.LBB0_2: + divu a1, a2, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_57.s b/benchmarks/LLC_ASM_selectiondag/4_function_57.s new file mode 100644 index 0000000..a3baf5f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_57.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a2 + sext.w a0, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_58.s b/benchmarks/LLC_ASM_selectiondag/4_function_58.s new file mode 100644 index 0000000..f47cdc0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_58.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + xor a0, a0, a2 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_59.s b/benchmarks/LLC_ASM_selectiondag/4_function_59.s new file mode 100644 index 0000000..c6d9d7d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_59.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_6.s b/benchmarks/LLC_ASM_selectiondag/4_function_6.s new file mode 100644 index 0000000..3eaae18 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_6.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_60.s b/benchmarks/LLC_ASM_selectiondag/4_function_60.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_60.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_61.s b/benchmarks/LLC_ASM_selectiondag/4_function_61.s new file mode 100644 index 0000000..43fcf96 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_61.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + div a1, a1, a0 + or a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_62.s b/benchmarks/LLC_ASM_selectiondag/4_function_62.s new file mode 100644 index 0000000..9be739b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_62.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a0 + divu a1, a1, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_63.s b/benchmarks/LLC_ASM_selectiondag/4_function_63.s new file mode 100644 index 0000000..1c56590 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_63.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + sra a2, a2, a2 + rem a1, a1, a2 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_64.s b/benchmarks/LLC_ASM_selectiondag/4_function_64.s new file mode 100644 index 0000000..0179e76 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_64.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + beqz a3, .LBB0_2 +# %bb.1: + zext.w a0, a0 + srl a0, a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_65.s b/benchmarks/LLC_ASM_selectiondag/4_function_65.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_65.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_66.s b/benchmarks/LLC_ASM_selectiondag/4_function_66.s new file mode 100644 index 0000000..f93815f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_66.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_67.s b/benchmarks/LLC_ASM_selectiondag/4_function_67.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_67.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_68.s b/benchmarks/LLC_ASM_selectiondag/4_function_68.s new file mode 100644 index 0000000..11ef7f8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_68.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_69.s b/benchmarks/LLC_ASM_selectiondag/4_function_69.s new file mode 100644 index 0000000..3ba6fad --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_69.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a1, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_7.s b/benchmarks/LLC_ASM_selectiondag/4_function_7.s new file mode 100644 index 0000000..62fdcde --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_7.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + xor a1, a0, a1 + mv a0, a2 + blt a1, a3, .LBB0_2 +# %bb.1: + li a0, 1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_70.s b/benchmarks/LLC_ASM_selectiondag/4_function_70.s new file mode 100644 index 0000000..493b221 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_70.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a2, 1 + srl a0, a2, a0 + zext.w a1, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_71.s b/benchmarks/LLC_ASM_selectiondag/4_function_71.s new file mode 100644 index 0000000..20f20c5 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_71.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_72.s b/benchmarks/LLC_ASM_selectiondag/4_function_72.s new file mode 100644 index 0000000..e9f5d08 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_72.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + sra a1, a0, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_73.s b/benchmarks/LLC_ASM_selectiondag/4_function_73.s new file mode 100644 index 0000000..750c1f1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_73.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_74.s b/benchmarks/LLC_ASM_selectiondag/4_function_74.s new file mode 100644 index 0000000..6e094f1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_74.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + maxu a1, a0, a1 + andi a3, a1, 1 + mv a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_75.s b/benchmarks/LLC_ASM_selectiondag/4_function_75.s new file mode 100644 index 0000000..f790059 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_75.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_76.s b/benchmarks/LLC_ASM_selectiondag/4_function_76.s new file mode 100644 index 0000000..d249848 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_76.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_77.s b/benchmarks/LLC_ASM_selectiondag/4_function_77.s new file mode 100644 index 0000000..2bf54a8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_77.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + sext.w a1, a1 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_78.s b/benchmarks/LLC_ASM_selectiondag/4_function_78.s new file mode 100644 index 0000000..e00d137 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_78.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_79.s b/benchmarks/LLC_ASM_selectiondag/4_function_79.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_79.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_8.s b/benchmarks/LLC_ASM_selectiondag/4_function_8.s new file mode 100644 index 0000000..bb5c1c7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_8.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_80.s b/benchmarks/LLC_ASM_selectiondag/4_function_80.s new file mode 100644 index 0000000..4f4f16a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_80.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a0 + remu a0, a0, a1 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_81.s b/benchmarks/LLC_ASM_selectiondag/4_function_81.s new file mode 100644 index 0000000..d6c01fd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_81.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + or a1, a2, a1 + xor a0, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_82.s b/benchmarks/LLC_ASM_selectiondag/4_function_82.s new file mode 100644 index 0000000..6343eca --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_82.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_83.s b/benchmarks/LLC_ASM_selectiondag/4_function_83.s new file mode 100644 index 0000000..bb85664 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_83.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_84.s b/benchmarks/LLC_ASM_selectiondag/4_function_84.s new file mode 100644 index 0000000..88815bb --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_84.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_85.s b/benchmarks/LLC_ASM_selectiondag/4_function_85.s new file mode 100644 index 0000000..16db514 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_85.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + srl a0, a0, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_86.s b/benchmarks/LLC_ASM_selectiondag/4_function_86.s new file mode 100644 index 0000000..6062b45 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_86.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + bnez a2, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_87.s b/benchmarks/LLC_ASM_selectiondag/4_function_87.s new file mode 100644 index 0000000..b6f393c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_87.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_88.s b/benchmarks/LLC_ASM_selectiondag/4_function_88.s new file mode 100644 index 0000000..76a353f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_88.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + and a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_89.s b/benchmarks/LLC_ASM_selectiondag/4_function_89.s new file mode 100644 index 0000000..563e2eb --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_89.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + xor a0, a0, a1 + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_9.s b/benchmarks/LLC_ASM_selectiondag/4_function_9.s new file mode 100644 index 0000000..2f74c33 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_9.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + sra a1, a2, a0 + div a1, a2, a1 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_90.s b/benchmarks/LLC_ASM_selectiondag/4_function_90.s new file mode 100644 index 0000000..cf90c91 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_90.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + remu a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_91.s b/benchmarks/LLC_ASM_selectiondag/4_function_91.s new file mode 100644 index 0000000..fd12564 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_91.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a2 + or a0, a0, a2 + sra a1, a1, a2 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_92.s b/benchmarks/LLC_ASM_selectiondag/4_function_92.s new file mode 100644 index 0000000..c2fb2e4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_92.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + div a0, a0, a1 + and a2, a0, a2 + xor a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_93.s b/benchmarks/LLC_ASM_selectiondag/4_function_93.s new file mode 100644 index 0000000..bcd2ba9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_93.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a0 + sltu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_94.s b/benchmarks/LLC_ASM_selectiondag/4_function_94.s new file mode 100644 index 0000000..8698571 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_94.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + li a2, 1 +.LBB0_2: + seqz a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_95.s b/benchmarks/LLC_ASM_selectiondag/4_function_95.s new file mode 100644 index 0000000..5e2b3d9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_95.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a2 + sext.w a0, a0 + and a0, a0, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_96.s b/benchmarks/LLC_ASM_selectiondag/4_function_96.s new file mode 100644 index 0000000..d712d92 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_96.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a2 + and a0, a1, a0 + zext.w a0, a0 + slt a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_97.s b/benchmarks/LLC_ASM_selectiondag/4_function_97.s new file mode 100644 index 0000000..cb23456 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_97.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a1 + rem a1, a0, a1 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_98.s b/benchmarks/LLC_ASM_selectiondag/4_function_98.s new file mode 100644 index 0000000..b6f393c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_98.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/4_function_99.s b/benchmarks/LLC_ASM_selectiondag/4_function_99.s new file mode 100644 index 0000000..0a56b61 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/4_function_99.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_0.s b/benchmarks/LLC_ASM_selectiondag/5_function_0.s new file mode 100644 index 0000000..5b92a3a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_0.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + remu a1, a0, a1 + div a0, a0, a1 + remu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_1.s b/benchmarks/LLC_ASM_selectiondag/5_function_1.s new file mode 100644 index 0000000..c51e709 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_1.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + srl a0, a1, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_10.s b/benchmarks/LLC_ASM_selectiondag/5_function_10.s new file mode 100644 index 0000000..3e4bc7a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_10.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + srl a1, a2, a1 + rem a0, a1, a0 + remu a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_11.s b/benchmarks/LLC_ASM_selectiondag/5_function_11.s new file mode 100644 index 0000000..dbd4faf --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_11.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + div a1, a1, a0 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_12.s b/benchmarks/LLC_ASM_selectiondag/5_function_12.s new file mode 100644 index 0000000..3f5cd13 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_12.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a1, a1 + div a0, a0, a3 + blt a2, a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_13.s b/benchmarks/LLC_ASM_selectiondag/5_function_13.s new file mode 100644 index 0000000..bc28872 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_13.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a1 + zext.w a1, a2 + srl a2, a1, a0 + divu a1, a2, a1 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_14.s b/benchmarks/LLC_ASM_selectiondag/5_function_14.s new file mode 100644 index 0000000..334e5ad --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_14.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_15.s b/benchmarks/LLC_ASM_selectiondag/5_function_15.s new file mode 100644 index 0000000..bdcc30c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_15.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a3, a0, a1 + mv a1, a2 + blt a3, a0, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + div a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_16.s b/benchmarks/LLC_ASM_selectiondag/5_function_16.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_16.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_17.s b/benchmarks/LLC_ASM_selectiondag/5_function_17.s new file mode 100644 index 0000000..b791159 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_17.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ori a0, a0, 1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_18.s b/benchmarks/LLC_ASM_selectiondag/5_function_18.s new file mode 100644 index 0000000..105dc7c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_18.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a0, a0 + rem a1, a2, a1 + div a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_19.s b/benchmarks/LLC_ASM_selectiondag/5_function_19.s new file mode 100644 index 0000000..79e9ecd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_19.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + sra a0, a0, a0 + remu a0, a1, a0 + zext.w a1, a2 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_2.s b/benchmarks/LLC_ASM_selectiondag/5_function_2.s new file mode 100644 index 0000000..1a185c7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_2.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + divu a3, a1, a2 + and a2, a2, a3 + sra a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_20.s b/benchmarks/LLC_ASM_selectiondag/5_function_20.s new file mode 100644 index 0000000..1825a2e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_20.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a2, a2, a0 + srl a2, a1, a2 + divu a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_21.s b/benchmarks/LLC_ASM_selectiondag/5_function_21.s new file mode 100644 index 0000000..fbc198d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_21.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bext a1, a0, a0 + beqz a1, .LBB0_2 +# %bb.1: + srl a0, a0, a0 +.LBB0_2: + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_22.s b/benchmarks/LLC_ASM_selectiondag/5_function_22.s new file mode 100644 index 0000000..614d25b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_22.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_23.s b/benchmarks/LLC_ASM_selectiondag/5_function_23.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_23.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_24.s b/benchmarks/LLC_ASM_selectiondag/5_function_24.s new file mode 100644 index 0000000..0c7bd7e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_24.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + xor a1, a2, a1 + and a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_25.s b/benchmarks/LLC_ASM_selectiondag/5_function_25.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_25.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_26.s b/benchmarks/LLC_ASM_selectiondag/5_function_26.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_26.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_27.s b/benchmarks/LLC_ASM_selectiondag/5_function_27.s new file mode 100644 index 0000000..044f400 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_27.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a3, a1, a2 + blt a3, a0, .LBB0_2 +# %bb.1: + rem a2, a1, a0 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_28.s b/benchmarks/LLC_ASM_selectiondag/5_function_28.s new file mode 100644 index 0000000..da75a11 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_28.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a0, 1 + li a0, 1 + bnez a1, .LBB0_2 +# %bb.1: + rem a0, a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_29.s b/benchmarks/LLC_ASM_selectiondag/5_function_29.s new file mode 100644 index 0000000..ac5583b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_29.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + div a0, a0, a2 + sext.w a1, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_3.s b/benchmarks/LLC_ASM_selectiondag/5_function_3.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_3.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_30.s b/benchmarks/LLC_ASM_selectiondag/5_function_30.s new file mode 100644 index 0000000..1379a6f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_30.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + addi a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_31.s b/benchmarks/LLC_ASM_selectiondag/5_function_31.s new file mode 100644 index 0000000..5b573b1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_31.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a1, a2 + bge a0, a2, .LBB0_2 +# %bb.1: + zext.w a0, a3 +.LBB0_2: + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_32.s b/benchmarks/LLC_ASM_selectiondag/5_function_32.s new file mode 100644 index 0000000..8e5d4a8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_32.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a0, a1 + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_33.s b/benchmarks/LLC_ASM_selectiondag/5_function_33.s new file mode 100644 index 0000000..a8feb73 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_33.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + andi a1, a2, 1 +.LBB0_2: + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_34.s b/benchmarks/LLC_ASM_selectiondag/5_function_34.s new file mode 100644 index 0000000..79dc586 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_34.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + add.uw a0, a0, a2 + xor a0, a1, a0 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_35.s b/benchmarks/LLC_ASM_selectiondag/5_function_35.s new file mode 100644 index 0000000..0883ab3 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_35.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a3, a2, a1 + sra a2, a2, a3 + divu a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_36.s b/benchmarks/LLC_ASM_selectiondag/5_function_36.s new file mode 100644 index 0000000..e7a8ade --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_36.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_37.s b/benchmarks/LLC_ASM_selectiondag/5_function_37.s new file mode 100644 index 0000000..e822500 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_37.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + bnez a3, .LBB0_2 +# %bb.1: + add.uw a0, a2, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_38.s b/benchmarks/LLC_ASM_selectiondag/5_function_38.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_38.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_39.s b/benchmarks/LLC_ASM_selectiondag/5_function_39.s new file mode 100644 index 0000000..4d6a3d3 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_39.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a0, 1 + zext.w a0, a0 + addi a1, a1, -1 + and a1, a1, a0 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_4.s b/benchmarks/LLC_ASM_selectiondag/5_function_4.s new file mode 100644 index 0000000..23f539c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_4.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + div a1, a0, a1 + divu a0, a0, a1 + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_40.s b/benchmarks/LLC_ASM_selectiondag/5_function_40.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_40.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_41.s b/benchmarks/LLC_ASM_selectiondag/5_function_41.s new file mode 100644 index 0000000..0184ec1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_41.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + zext.w a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_42.s b/benchmarks/LLC_ASM_selectiondag/5_function_42.s new file mode 100644 index 0000000..a50b503 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_42.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a2 + sra a2, a0, a0 + or a0, a0, a2 + xor a0, a0, a1 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_43.s b/benchmarks/LLC_ASM_selectiondag/5_function_43.s new file mode 100644 index 0000000..3536e63 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_43.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + rem a1, a0, a2 + remu a0, a0, a1 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_44.s b/benchmarks/LLC_ASM_selectiondag/5_function_44.s new file mode 100644 index 0000000..652fa43 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_44.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + or a0, a0, a2 + or a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_45.s b/benchmarks/LLC_ASM_selectiondag/5_function_45.s new file mode 100644 index 0000000..4c2f7a4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_45.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a2 + div a2, a1, a2 + xor a0, a0, a2 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_46.s b/benchmarks/LLC_ASM_selectiondag/5_function_46.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_46.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_47.s b/benchmarks/LLC_ASM_selectiondag/5_function_47.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_47.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_48.s b/benchmarks/LLC_ASM_selectiondag/5_function_48.s new file mode 100644 index 0000000..6b6a1ec --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_48.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_49.s b/benchmarks/LLC_ASM_selectiondag/5_function_49.s new file mode 100644 index 0000000..a41822a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_49.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a2, a0 + div a1, a1, a2 + xor a1, a0, a1 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_5.s b/benchmarks/LLC_ASM_selectiondag/5_function_5.s new file mode 100644 index 0000000..9b5af2f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_5.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + divu a1, a1, a2 + divu a0, a1, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_50.s b/benchmarks/LLC_ASM_selectiondag/5_function_50.s new file mode 100644 index 0000000..6baa6b0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_50.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_51.s b/benchmarks/LLC_ASM_selectiondag/5_function_51.s new file mode 100644 index 0000000..5c05b0f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_51.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a2 + srl a1, a0, a1 + remu a1, a1, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_52.s b/benchmarks/LLC_ASM_selectiondag/5_function_52.s new file mode 100644 index 0000000..f3f8f99 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_52.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a0 + srl a2, a2, a0 + div a0, a2, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_53.s b/benchmarks/LLC_ASM_selectiondag/5_function_53.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_53.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_54.s b/benchmarks/LLC_ASM_selectiondag/5_function_54.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_54.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_55.s b/benchmarks/LLC_ASM_selectiondag/5_function_55.s new file mode 100644 index 0000000..7ecc3ed --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_55.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bge a0, a1, .LBB0_2 +# %bb.1: + remu a2, a2, a1 +.LBB0_2: + slt a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_56.s b/benchmarks/LLC_ASM_selectiondag/5_function_56.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_56.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_57.s b/benchmarks/LLC_ASM_selectiondag/5_function_57.s new file mode 100644 index 0000000..752c679 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_57.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a1, a0 + and a3, a0, a3 + bext a3, a0, a3 + mv a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_58.s b/benchmarks/LLC_ASM_selectiondag/5_function_58.s new file mode 100644 index 0000000..cc7d9c2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_58.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a0 + xor a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_59.s b/benchmarks/LLC_ASM_selectiondag/5_function_59.s new file mode 100644 index 0000000..fe29bf7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_59.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a1 + and a1, a2, a1 + divu a1, a2, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_6.s b/benchmarks/LLC_ASM_selectiondag/5_function_6.s new file mode 100644 index 0000000..c2c99d1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_6.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_60.s b/benchmarks/LLC_ASM_selectiondag/5_function_60.s new file mode 100644 index 0000000..620e87d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_60.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + sext.w a3, a0 + and a0, a0, a3 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + xor a0, a0, a2 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_61.s b/benchmarks/LLC_ASM_selectiondag/5_function_61.s new file mode 100644 index 0000000..63229f0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_61.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + zext.w a1, a1 + div a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_62.s b/benchmarks/LLC_ASM_selectiondag/5_function_62.s new file mode 100644 index 0000000..4e42cf5 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_62.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a2, 1 + srl a1, a0, a1 + mv a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + or a0, a0, a2 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_63.s b/benchmarks/LLC_ASM_selectiondag/5_function_63.s new file mode 100644 index 0000000..a9bffb2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_63.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a2 + xor a0, a0, a1 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_64.s b/benchmarks/LLC_ASM_selectiondag/5_function_64.s new file mode 100644 index 0000000..68738a8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_64.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ori a2, a0, 1 + remu a1, a2, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_65.s b/benchmarks/LLC_ASM_selectiondag/5_function_65.s new file mode 100644 index 0000000..9e76909 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_65.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + rem a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_66.s b/benchmarks/LLC_ASM_selectiondag/5_function_66.s new file mode 100644 index 0000000..88815bb --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_66.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_67.s b/benchmarks/LLC_ASM_selectiondag/5_function_67.s new file mode 100644 index 0000000..d68beb2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_67.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a0, a0 + divu a1, a3, a1 + divu a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_68.s b/benchmarks/LLC_ASM_selectiondag/5_function_68.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_68.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_69.s b/benchmarks/LLC_ASM_selectiondag/5_function_69.s new file mode 100644 index 0000000..376d698 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_69.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + sltu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_7.s b/benchmarks/LLC_ASM_selectiondag/5_function_7.s new file mode 100644 index 0000000..34f6dd1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_7.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a2 + or a1, a1, a2 + div a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_70.s b/benchmarks/LLC_ASM_selectiondag/5_function_70.s new file mode 100644 index 0000000..2ed1846 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_70.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + slli a0, a0, 63 + srai a0, a0, 63 + and a0, a1, a0 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_71.s b/benchmarks/LLC_ASM_selectiondag/5_function_71.s new file mode 100644 index 0000000..5a7ef12 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_71.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + sext.w a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_72.s b/benchmarks/LLC_ASM_selectiondag/5_function_72.s new file mode 100644 index 0000000..0fd0e95 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_72.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a0 + rem a1, a0, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_73.s b/benchmarks/LLC_ASM_selectiondag/5_function_73.s new file mode 100644 index 0000000..d77da55 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_73.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + sra a0, a0, a1 + divu a1, a0, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_74.s b/benchmarks/LLC_ASM_selectiondag/5_function_74.s new file mode 100644 index 0000000..fc33031 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_74.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + sext.w a1, a2 +.LBB0_2: + and a1, a0, a1 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_75.s b/benchmarks/LLC_ASM_selectiondag/5_function_75.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_75.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_76.s b/benchmarks/LLC_ASM_selectiondag/5_function_76.s new file mode 100644 index 0000000..9a34fd4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_76.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + divu a1, a0, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_77.s b/benchmarks/LLC_ASM_selectiondag/5_function_77.s new file mode 100644 index 0000000..900ed1c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_77.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a2, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_78.s b/benchmarks/LLC_ASM_selectiondag/5_function_78.s new file mode 100644 index 0000000..db2c45a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_78.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + zext.w a1, a2 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_79.s b/benchmarks/LLC_ASM_selectiondag/5_function_79.s new file mode 100644 index 0000000..d200bca --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_79.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + sext.w a1, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_8.s b/benchmarks/LLC_ASM_selectiondag/5_function_8.s new file mode 100644 index 0000000..a18715c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_8.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a0, a2 + xor a1, a1, a2 + divu a0, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_80.s b/benchmarks/LLC_ASM_selectiondag/5_function_80.s new file mode 100644 index 0000000..63a6590 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_80.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + sra a1, a0, a1 + sra a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_81.s b/benchmarks/LLC_ASM_selectiondag/5_function_81.s new file mode 100644 index 0000000..66b8cc9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_81.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + sext.w a2, a2 + and a2, a0, a2 + sltu a0, a0, a2 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_82.s b/benchmarks/LLC_ASM_selectiondag/5_function_82.s new file mode 100644 index 0000000..4b0dd1f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_82.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + sext.w a2, a0 + or a0, a2, a0 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_83.s b/benchmarks/LLC_ASM_selectiondag/5_function_83.s new file mode 100644 index 0000000..65b7d4e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_83.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + sra a1, a1, a2 + div a0, a0, a1 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_84.s b/benchmarks/LLC_ASM_selectiondag/5_function_84.s new file mode 100644 index 0000000..f8221bd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_84.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + or a0, a0, a1 + and a2, a0, a2 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_85.s b/benchmarks/LLC_ASM_selectiondag/5_function_85.s new file mode 100644 index 0000000..1fbe3f9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_85.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + srl a0, a1, a0 + div a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_86.s b/benchmarks/LLC_ASM_selectiondag/5_function_86.s new file mode 100644 index 0000000..ba5f6f9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_86.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + beqz a1, .LBB0_2 +# %bb.1: + li a0, 1 +.LBB0_2: + remu a0, a0, a2 + ori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_87.s b/benchmarks/LLC_ASM_selectiondag/5_function_87.s new file mode 100644 index 0000000..4d3d6a6 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_87.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + bnez a3, .LBB0_2 +# %bb.1: + div a2, a2, a1 +.LBB0_2: + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_88.s b/benchmarks/LLC_ASM_selectiondag/5_function_88.s new file mode 100644 index 0000000..2001a99 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_88.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_89.s b/benchmarks/LLC_ASM_selectiondag/5_function_89.s new file mode 100644 index 0000000..b77812a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_89.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + and a0, a2, a2 + ret +.LBB0_2: + sra a0, a1, a2 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_9.s b/benchmarks/LLC_ASM_selectiondag/5_function_9.s new file mode 100644 index 0000000..3d4aed4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_9.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + sra a0, a1, a2 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_90.s b/benchmarks/LLC_ASM_selectiondag/5_function_90.s new file mode 100644 index 0000000..a73acaa --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_90.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + sra a2, a0, a1 + sra a0, a1, a0 + rem a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_91.s b/benchmarks/LLC_ASM_selectiondag/5_function_91.s new file mode 100644 index 0000000..ac416f9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_91.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a1, a0 + andi a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_92.s b/benchmarks/LLC_ASM_selectiondag/5_function_92.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_92.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_93.s b/benchmarks/LLC_ASM_selectiondag/5_function_93.s new file mode 100644 index 0000000..392d138 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_93.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + divu a1, a1, a2 + slt a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_94.s b/benchmarks/LLC_ASM_selectiondag/5_function_94.s new file mode 100644 index 0000000..d2b8870 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_94.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + sext.w a1, a0 + srl a0, a2, a0 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_95.s b/benchmarks/LLC_ASM_selectiondag/5_function_95.s new file mode 100644 index 0000000..d7f4562 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_95.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a0 + srl a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_96.s b/benchmarks/LLC_ASM_selectiondag/5_function_96.s new file mode 100644 index 0000000..30bd1ed --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_96.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a2 + srl a1, a1, a0 + and a1, a0, a1 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_97.s b/benchmarks/LLC_ASM_selectiondag/5_function_97.s new file mode 100644 index 0000000..e177fce --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_97.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_98.s b/benchmarks/LLC_ASM_selectiondag/5_function_98.s new file mode 100644 index 0000000..9d5160d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_98.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a1, a1 + div a0, a0, a1 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/5_function_99.s b/benchmarks/LLC_ASM_selectiondag/5_function_99.s new file mode 100644 index 0000000..c6f54fa --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/5_function_99.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_0.s b/benchmarks/LLC_ASM_selectiondag/6_function_0.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_0.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_1.s b/benchmarks/LLC_ASM_selectiondag/6_function_1.s new file mode 100644 index 0000000..aa7fdf9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_1.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + zext.w a1, a1 + srl a0, a2, a0 + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_10.s b/benchmarks/LLC_ASM_selectiondag/6_function_10.s new file mode 100644 index 0000000..8ae3c12 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_10.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a1, a2 + div a3, a1, a3 + xor a1, a1, a2 + divu a1, a1, a3 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_11.s b/benchmarks/LLC_ASM_selectiondag/6_function_11.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_11.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_12.s b/benchmarks/LLC_ASM_selectiondag/6_function_12.s new file mode 100644 index 0000000..c270aea --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_12.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a2, 1 + srl a2, a2, a1 + addi a2, a2, -1 + and a0, a0, a1 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_13.s b/benchmarks/LLC_ASM_selectiondag/6_function_13.s new file mode 100644 index 0000000..8804010 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_13.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + rem a0, a0, a1 + srl a1, a2, a2 + div a1, a2, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_14.s b/benchmarks/LLC_ASM_selectiondag/6_function_14.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_14.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_15.s b/benchmarks/LLC_ASM_selectiondag/6_function_15.s new file mode 100644 index 0000000..12f24ff --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_15.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + srl a1, a1, a0 + rem a0, a0, a1 + remu a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_16.s b/benchmarks/LLC_ASM_selectiondag/6_function_16.s new file mode 100644 index 0000000..7359e8d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_16.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a1, a2 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_17.s b/benchmarks/LLC_ASM_selectiondag/6_function_17.s new file mode 100644 index 0000000..fb1294d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_17.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + xor a0, a0, a1 + sext.w a0, a0 + xor a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_18.s b/benchmarks/LLC_ASM_selectiondag/6_function_18.s new file mode 100644 index 0000000..bc85990 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_18.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a0 + or a1, a0, a1 + srl a0, a0, a2 + xor a0, a1, a0 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_19.s b/benchmarks/LLC_ASM_selectiondag/6_function_19.s new file mode 100644 index 0000000..37c4b83 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_19.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + div a0, a0, a2 + srli a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_2.s b/benchmarks/LLC_ASM_selectiondag/6_function_2.s new file mode 100644 index 0000000..b6addbd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_2.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a0, a1 + rem a0, a0, a3 + xor a1, a1, a2 + xor a1, a1, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_20.s b/benchmarks/LLC_ASM_selectiondag/6_function_20.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_20.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_21.s b/benchmarks/LLC_ASM_selectiondag/6_function_21.s new file mode 100644 index 0000000..dc9c7a3 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_21.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + sext.w a0, a2 +.LBB0_2: + xori a0, a0, 1 + xori a1, a1, 1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_22.s b/benchmarks/LLC_ASM_selectiondag/6_function_22.s new file mode 100644 index 0000000..935fd36 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_22.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a2 + rem a1, a0, a1 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_23.s b/benchmarks/LLC_ASM_selectiondag/6_function_23.s new file mode 100644 index 0000000..50aff60 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_23.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srli a1, a1, 63 + xori a0, a1, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_24.s b/benchmarks/LLC_ASM_selectiondag/6_function_24.s new file mode 100644 index 0000000..a867d1f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_24.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a2, a1 + andi a3, a3, 1 + xor a0, a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_25.s b/benchmarks/LLC_ASM_selectiondag/6_function_25.s new file mode 100644 index 0000000..388d07a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_25.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + rem a1, a0, a1 + remu a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_26.s b/benchmarks/LLC_ASM_selectiondag/6_function_26.s new file mode 100644 index 0000000..3c0797f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_26.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_27.s b/benchmarks/LLC_ASM_selectiondag/6_function_27.s new file mode 100644 index 0000000..42b739a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_27.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a2, a2, a1 + rem a1, a0, a1 + and a0, a0, a1 + or a0, a0, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_28.s b/benchmarks/LLC_ASM_selectiondag/6_function_28.s new file mode 100644 index 0000000..f8e5335 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_28.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a1, a2 + and a1, a2, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_29.s b/benchmarks/LLC_ASM_selectiondag/6_function_29.s new file mode 100644 index 0000000..f1c4c8d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_29.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + slli a0, a0, 31 + srli a0, a0, 32 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_3.s b/benchmarks/LLC_ASM_selectiondag/6_function_3.s new file mode 100644 index 0000000..8043b91 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_3.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_30.s b/benchmarks/LLC_ASM_selectiondag/6_function_30.s new file mode 100644 index 0000000..3007241 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_30.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a0 + srl a1, a1, a2 + srl a1, a1, a1 + divu a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_31.s b/benchmarks/LLC_ASM_selectiondag/6_function_31.s new file mode 100644 index 0000000..2dcabd4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_31.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a1 + zext.w a3, a1 + div a2, a2, a3 + sra a1, a2, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_32.s b/benchmarks/LLC_ASM_selectiondag/6_function_32.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_32.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_33.s b/benchmarks/LLC_ASM_selectiondag/6_function_33.s new file mode 100644 index 0000000..60df733 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_33.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a0, a1 + sext.w a1, a1 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_34.s b/benchmarks/LLC_ASM_selectiondag/6_function_34.s new file mode 100644 index 0000000..7006502 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_34.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a2, 1 + addi a2, a2, -1 + and a2, a2, a1 + rem a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_35.s b/benchmarks/LLC_ASM_selectiondag/6_function_35.s new file mode 100644 index 0000000..9ac9c12 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_35.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a2, a0 + sext.w a3, a1 + divu a2, a3, a2 + srl a1, a2, a1 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_36.s b/benchmarks/LLC_ASM_selectiondag/6_function_36.s new file mode 100644 index 0000000..928118a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_36.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_37.s b/benchmarks/LLC_ASM_selectiondag/6_function_37.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_37.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_38.s b/benchmarks/LLC_ASM_selectiondag/6_function_38.s new file mode 100644 index 0000000..5f45f70 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_38.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + remu a1, a0, a1 + srl a0, a0, a1 + and a0, a2, a0 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_39.s b/benchmarks/LLC_ASM_selectiondag/6_function_39.s new file mode 100644 index 0000000..5d8fe2a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_39.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + sext.w a1, a2 + rem a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_4.s b/benchmarks/LLC_ASM_selectiondag/6_function_4.s new file mode 100644 index 0000000..9307210 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_4.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + zext.w a1, a1 + srl a0, a1, a0 + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_40.s b/benchmarks/LLC_ASM_selectiondag/6_function_40.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_40.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_41.s b/benchmarks/LLC_ASM_selectiondag/6_function_41.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_41.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_42.s b/benchmarks/LLC_ASM_selectiondag/6_function_42.s new file mode 100644 index 0000000..9f190c7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_42.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + remu a0, a0, a2 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_43.s b/benchmarks/LLC_ASM_selectiondag/6_function_43.s new file mode 100644 index 0000000..b2a0f13 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_43.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + rem a3, a0, a1 + sra a0, a2, a1 + blt a3, a0, .LBB0_4 +# %bb.3: + mv a0, a1 +.LBB0_4: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_44.s b/benchmarks/LLC_ASM_selectiondag/6_function_44.s new file mode 100644 index 0000000..e292a4e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_44.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a0, a1 + and a1, a0, a1 + divu a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_45.s b/benchmarks/LLC_ASM_selectiondag/6_function_45.s new file mode 100644 index 0000000..f913986 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_45.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + zext.w a0, a0 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_46.s b/benchmarks/LLC_ASM_selectiondag/6_function_46.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_46.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_47.s b/benchmarks/LLC_ASM_selectiondag/6_function_47.s new file mode 100644 index 0000000..2bd268c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_47.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + xor a2, a0, a2 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_48.s b/benchmarks/LLC_ASM_selectiondag/6_function_48.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_48.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_49.s b/benchmarks/LLC_ASM_selectiondag/6_function_49.s new file mode 100644 index 0000000..d1bad0f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_49.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a0 + remu a0, a2, a0 + add.uw a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_5.s b/benchmarks/LLC_ASM_selectiondag/6_function_5.s new file mode 100644 index 0000000..6f67998 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_5.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + zext.w a0, a0 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_50.s b/benchmarks/LLC_ASM_selectiondag/6_function_50.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_50.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_51.s b/benchmarks/LLC_ASM_selectiondag/6_function_51.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_51.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_52.s b/benchmarks/LLC_ASM_selectiondag/6_function_52.s new file mode 100644 index 0000000..0a813bc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_52.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a0 + or a1, a1, a2 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_53.s b/benchmarks/LLC_ASM_selectiondag/6_function_53.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_53.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_54.s b/benchmarks/LLC_ASM_selectiondag/6_function_54.s new file mode 100644 index 0000000..033d726 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_54.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a0, a1 + sext.w a0, a0 + srl a1, a1, a0 + remu a0, a1, a0 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_55.s b/benchmarks/LLC_ASM_selectiondag/6_function_55.s new file mode 100644 index 0000000..8826cd1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_55.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + li a1, 1 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_56.s b/benchmarks/LLC_ASM_selectiondag/6_function_56.s new file mode 100644 index 0000000..6f0e8f3 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_56.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a2 + and a1, a0, a1 + zext.w a1, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_57.s b/benchmarks/LLC_ASM_selectiondag/6_function_57.s new file mode 100644 index 0000000..cdd06dd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_57.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a2 + sra a1, a0, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_58.s b/benchmarks/LLC_ASM_selectiondag/6_function_58.s new file mode 100644 index 0000000..f790059 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_58.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_59.s b/benchmarks/LLC_ASM_selectiondag/6_function_59.s new file mode 100644 index 0000000..1c07594 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_59.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_6.s b/benchmarks/LLC_ASM_selectiondag/6_function_6.s new file mode 100644 index 0000000..9b6d6cc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_6.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a0 + div a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_60.s b/benchmarks/LLC_ASM_selectiondag/6_function_60.s new file mode 100644 index 0000000..b5f4f05 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_60.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a1, 1 + sext.w a2, a0 + div a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_61.s b/benchmarks/LLC_ASM_selectiondag/6_function_61.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_61.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_62.s b/benchmarks/LLC_ASM_selectiondag/6_function_62.s new file mode 100644 index 0000000..115bc99 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_62.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + xor a1, a0, a2 + sra a1, a0, a1 + andi a3, a1, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + remu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_63.s b/benchmarks/LLC_ASM_selectiondag/6_function_63.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_63.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_64.s b/benchmarks/LLC_ASM_selectiondag/6_function_64.s new file mode 100644 index 0000000..92bffb2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_64.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a3, 1 + rem a3, a3, a0 + sra a2, a2, a2 + rem a2, a3, a2 + or a0, a0, a1 + srl a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_65.s b/benchmarks/LLC_ASM_selectiondag/6_function_65.s new file mode 100644 index 0000000..810a2d8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_65.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + zext.w a1, a0 + sext.w a0, a0 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_66.s b/benchmarks/LLC_ASM_selectiondag/6_function_66.s new file mode 100644 index 0000000..e5aa959 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_66.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + div a0, a0, a1 + zext.w a1, a2 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_67.s b/benchmarks/LLC_ASM_selectiondag/6_function_67.s new file mode 100644 index 0000000..aa378f1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_67.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a3, a0, a1 + xor a2, a2, a3 + rem a1, a1, a2 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_68.s b/benchmarks/LLC_ASM_selectiondag/6_function_68.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_68.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_69.s b/benchmarks/LLC_ASM_selectiondag/6_function_69.s new file mode 100644 index 0000000..8043b91 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_69.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_7.s b/benchmarks/LLC_ASM_selectiondag/6_function_7.s new file mode 100644 index 0000000..a2370c2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_7.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + divu a0, a0, a2 + zext.w a0, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_70.s b/benchmarks/LLC_ASM_selectiondag/6_function_70.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_70.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_71.s b/benchmarks/LLC_ASM_selectiondag/6_function_71.s new file mode 100644 index 0000000..bc673f1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_71.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + divu a1, a1, a2 + sra a1, a0, a1 + srl a1, a1, a2 + sra a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_72.s b/benchmarks/LLC_ASM_selectiondag/6_function_72.s new file mode 100644 index 0000000..fe19b75 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_72.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a0, a1 + div a0, a1, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_73.s b/benchmarks/LLC_ASM_selectiondag/6_function_73.s new file mode 100644 index 0000000..ab9f645 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_73.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_74.s b/benchmarks/LLC_ASM_selectiondag/6_function_74.s new file mode 100644 index 0000000..928118a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_74.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_75.s b/benchmarks/LLC_ASM_selectiondag/6_function_75.s new file mode 100644 index 0000000..45d25ec --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_75.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a1 + srl a0, a0, a1 + sext.w a0, a0 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_76.s b/benchmarks/LLC_ASM_selectiondag/6_function_76.s new file mode 100644 index 0000000..f240906 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_76.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a3, a0, a0 + bltu a3, a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + remu a0, a2, a3 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_77.s b/benchmarks/LLC_ASM_selectiondag/6_function_77.s new file mode 100644 index 0000000..66ed929 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_77.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a2 + divu a2, a1, a2 + srl a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_78.s b/benchmarks/LLC_ASM_selectiondag/6_function_78.s new file mode 100644 index 0000000..7e52285 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_78.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + divu a1, a1, a2 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_79.s b/benchmarks/LLC_ASM_selectiondag/6_function_79.s new file mode 100644 index 0000000..a835538 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_79.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a0, a2 + j .LBB0_3 +.LBB0_2: + mv a0, a1 + mv a1, a2 +.LBB0_3: + zext.w a1, a1 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_8.s b/benchmarks/LLC_ASM_selectiondag/6_function_8.s new file mode 100644 index 0000000..8a7c97f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_8.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + li a1, 1 +.LBB0_2: + srl a0, a1, a2 + srli a0, a0, 63 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_80.s b/benchmarks/LLC_ASM_selectiondag/6_function_80.s new file mode 100644 index 0000000..2edfd19 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_80.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + zext.w a0, a2 +.LBB0_2: + xor a1, a1, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_81.s b/benchmarks/LLC_ASM_selectiondag/6_function_81.s new file mode 100644 index 0000000..6ba570c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_81.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a1, a2 + and a1, a1, a2 + sra a0, a0, a1 + srl a1, a0, a1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_82.s b/benchmarks/LLC_ASM_selectiondag/6_function_82.s new file mode 100644 index 0000000..60c1b0a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_82.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a2, a0 + sltu a1, a3, a1 + addi a1, a1, -1 + and a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_83.s b/benchmarks/LLC_ASM_selectiondag/6_function_83.s new file mode 100644 index 0000000..a028c9d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_83.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + blt a1, a0, .LBB0_2 +# %bb.1: + sra a0, a1, a1 + rem a1, a0, a2 +.LBB0_2: + sra a0, a1, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_84.s b/benchmarks/LLC_ASM_selectiondag/6_function_84.s new file mode 100644 index 0000000..02f5b88 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_84.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a0 + div a0, a0, a1 + srl a0, a0, a2 + sext.w a3, a3 + bgeu a3, a0, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_85.s b/benchmarks/LLC_ASM_selectiondag/6_function_85.s new file mode 100644 index 0000000..edc7880 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_85.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + sra a0, a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + zext.w a0, a0 + ret +.LBB0_2: + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_86.s b/benchmarks/LLC_ASM_selectiondag/6_function_86.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_86.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_87.s b/benchmarks/LLC_ASM_selectiondag/6_function_87.s new file mode 100644 index 0000000..426e6f2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_87.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a0 + divu a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_88.s b/benchmarks/LLC_ASM_selectiondag/6_function_88.s new file mode 100644 index 0000000..24a480c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_88.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + rem a0, a2, a0 + xor a0, a2, a0 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_89.s b/benchmarks/LLC_ASM_selectiondag/6_function_89.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_89.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_9.s b/benchmarks/LLC_ASM_selectiondag/6_function_9.s new file mode 100644 index 0000000..a047dd9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_9.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a0, 1 + mv a0, a1 + bnez a2, .LBB0_2 +# %bb.1: + sext.w a0, a3 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_90.s b/benchmarks/LLC_ASM_selectiondag/6_function_90.s new file mode 100644 index 0000000..f2f14cc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_90.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a2 + andi a4, a1, 1 + srl a1, a3, a2 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a1 +.LBB0_2: + and a1, a1, a2 + or a1, a3, a1 + sltu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_91.s b/benchmarks/LLC_ASM_selectiondag/6_function_91.s new file mode 100644 index 0000000..489073c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_91.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a0, a2 + div a2, a0, a2 + or a1, a0, a1 + sra a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_92.s b/benchmarks/LLC_ASM_selectiondag/6_function_92.s new file mode 100644 index 0000000..093aee0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_92.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a0, a2 + bltu a1, a3, .LBB0_2 +# %bb.1: + rem a0, a3, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_93.s b/benchmarks/LLC_ASM_selectiondag/6_function_93.s new file mode 100644 index 0000000..de2927f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_93.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a2, a0 + srl a3, a0, a2 + rem a1, a1, a3 + rem a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_94.s b/benchmarks/LLC_ASM_selectiondag/6_function_94.s new file mode 100644 index 0000000..dfd1b29 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_94.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + divu a0, a2, a1 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_95.s b/benchmarks/LLC_ASM_selectiondag/6_function_95.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_95.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_96.s b/benchmarks/LLC_ASM_selectiondag/6_function_96.s new file mode 100644 index 0000000..dbea67c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_96.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + bnez a3, .LBB0_2 +# %bb.1: + zext.w a0, a2 + ret +.LBB0_2: + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_97.s b/benchmarks/LLC_ASM_selectiondag/6_function_97.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_97.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_98.s b/benchmarks/LLC_ASM_selectiondag/6_function_98.s new file mode 100644 index 0000000..cab4b57 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_98.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/6_function_99.s b/benchmarks/LLC_ASM_selectiondag/6_function_99.s new file mode 100644 index 0000000..a40bf9f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/6_function_99.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + beq a2, a0, .LBB0_2 +# %bb.1: + mv a3, a0 + j .LBB0_3 +.LBB0_2: + sext.w a3, a3 +.LBB0_3: + remu a1, a1, a3 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_0.s b/benchmarks/LLC_ASM_selectiondag/7_function_0.s new file mode 100644 index 0000000..5cc67e5 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_0.s @@ -0,0 +1,37 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + beqz a3, .LBB0_4 +# %bb.1: + andi a3, a2, 1 + beqz a3, .LBB0_5 +.LBB0_2: + or a2, a0, a2 + beqz a3, .LBB0_6 +.LBB0_3: + div a0, a2, a1 + ret +.LBB0_4: + mv a0, a2 + andi a3, a2, 1 + bnez a3, .LBB0_2 +.LBB0_5: + or a2, a0, a0 + bnez a3, .LBB0_3 +.LBB0_6: + div a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_1.s b/benchmarks/LLC_ASM_selectiondag/7_function_1.s new file mode 100644 index 0000000..220822b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_1.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a2 + rem a1, a0, a1 + div a0, a2, a0 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_10.s b/benchmarks/LLC_ASM_selectiondag/7_function_10.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_10.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_11.s b/benchmarks/LLC_ASM_selectiondag/7_function_11.s new file mode 100644 index 0000000..bc55579 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_11.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a0 + srl a0, a2, a0 + xor a1, a3, a1 + zext.w a0, a0 + div a0, a1, a0 + rem a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_12.s b/benchmarks/LLC_ASM_selectiondag/7_function_12.s new file mode 100644 index 0000000..34c5780 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_12.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + or a2, a2, a3 + div a2, a3, a2 + divu a1, a1, a2 + sra a0, a3, a0 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_13.s b/benchmarks/LLC_ASM_selectiondag/7_function_13.s new file mode 100644 index 0000000..b3343cf --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_13.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a3, a0, a1 + divu a1, a3, a1 + bgeu a2, a1, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_14.s b/benchmarks/LLC_ASM_selectiondag/7_function_14.s new file mode 100644 index 0000000..03707a5 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_14.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + sext.w a1, a1 + zext.w a0, a0 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_15.s b/benchmarks/LLC_ASM_selectiondag/7_function_15.s new file mode 100644 index 0000000..42923c2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_15.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a1 + rem a1, a2, a3 + div a1, a2, a1 + bgeu a3, a0, .LBB0_2 +# %bb.1: + srl a1, a0, a1 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_16.s b/benchmarks/LLC_ASM_selectiondag/7_function_16.s new file mode 100644 index 0000000..4d3436f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_16.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a1, a2 + sra a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_17.s b/benchmarks/LLC_ASM_selectiondag/7_function_17.s new file mode 100644 index 0000000..b2442bb --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_17.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a2, a0 + or a2, a2, a3 + xor a0, a0, a1 + xor a0, a0, a2 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_18.s b/benchmarks/LLC_ASM_selectiondag/7_function_18.s new file mode 100644 index 0000000..3039e52 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_18.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a1, a0 + sra a0, a0, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_19.s b/benchmarks/LLC_ASM_selectiondag/7_function_19.s new file mode 100644 index 0000000..b953359 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_19.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a2, a1, a2 + remu a0, a2, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_2.s b/benchmarks/LLC_ASM_selectiondag/7_function_2.s new file mode 100644 index 0000000..044e850 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_2.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a3, a0, a1 + sra a0, a0, a2 + remu a0, a0, a1 + div a1, a0, a1 + srl a0, a0, a1 + xor a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_20.s b/benchmarks/LLC_ASM_selectiondag/7_function_20.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_20.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_21.s b/benchmarks/LLC_ASM_selectiondag/7_function_21.s new file mode 100644 index 0000000..5bf77ff --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_21.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a1, a2 + sext.w a0, a0 + minu a1, a2, a1 + and a0, a0, a1 + xor a1, a1, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_22.s b/benchmarks/LLC_ASM_selectiondag/7_function_22.s new file mode 100644 index 0000000..85685f1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_22.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_23.s b/benchmarks/LLC_ASM_selectiondag/7_function_23.s new file mode 100644 index 0000000..7bfb752 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_23.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a1, a2 + div a1, a0, a1 + sra a0, a0, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_24.s b/benchmarks/LLC_ASM_selectiondag/7_function_24.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_24.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_25.s b/benchmarks/LLC_ASM_selectiondag/7_function_25.s new file mode 100644 index 0000000..028c217 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_25.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + andi a1, a0, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + andi a1, a2, 1 + bnez a1, .LBB0_4 +# %bb.3: + remu a0, a2, a0 + ret +.LBB0_4: + zext.w a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_26.s b/benchmarks/LLC_ASM_selectiondag/7_function_26.s new file mode 100644 index 0000000..494a363 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_26.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a0 + remu a2, a2, a0 + div a2, a2, a0 + and a1, a1, a0 + xor a0, a0, a1 + sra a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_27.s b/benchmarks/LLC_ASM_selectiondag/7_function_27.s new file mode 100644 index 0000000..535edcd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_27.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + addi a1, a1, -1 + and a1, a1, a2 + bgtz a1, .LBB0_2 +# %bb.1: + zext.w a0, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_28.s b/benchmarks/LLC_ASM_selectiondag/7_function_28.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_28.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_29.s b/benchmarks/LLC_ASM_selectiondag/7_function_29.s new file mode 100644 index 0000000..fc39489 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_29.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a3, a0, a3 + sra a2, a2, a3 + and a0, a1, a0 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_3.s b/benchmarks/LLC_ASM_selectiondag/7_function_3.s new file mode 100644 index 0000000..c25220f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_3.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ori a0, a1, 1 + zext.w a1, a2 + rem a0, a0, a1 + sext.w a2, a2 + sra a1, a2, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_30.s b/benchmarks/LLC_ASM_selectiondag/7_function_30.s new file mode 100644 index 0000000..c074d0a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_30.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a1 + srl a1, a0, a1 + and a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_31.s b/benchmarks/LLC_ASM_selectiondag/7_function_31.s new file mode 100644 index 0000000..af528e7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_31.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + sext.w a2, a2 + sltu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_32.s b/benchmarks/LLC_ASM_selectiondag/7_function_32.s new file mode 100644 index 0000000..41d0b41 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_32.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a1, a2 + sra a0, a0, a0 + zext.w a0, a0 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_33.s b/benchmarks/LLC_ASM_selectiondag/7_function_33.s new file mode 100644 index 0000000..83ec05c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_33.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srli a0, a0, 63 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_34.s b/benchmarks/LLC_ASM_selectiondag/7_function_34.s new file mode 100644 index 0000000..ef01412 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_34.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + zext.w a1, a2 + xor a1, a1, a2 +.LBB0_2: + srl a0, a1, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_35.s b/benchmarks/LLC_ASM_selectiondag/7_function_35.s new file mode 100644 index 0000000..5614b20 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_35.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + srl a2, a2, a0 + srl a1, a2, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_36.s b/benchmarks/LLC_ASM_selectiondag/7_function_36.s new file mode 100644 index 0000000..16bef6f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_36.s @@ -0,0 +1,30 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a3, a1, a2 + andi a4, a0, 1 + mv a0, a3 + bnez a4, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + mv a2, a0 + bgeu a3, a1, .LBB0_4 +# %bb.3: + mv a2, a3 +.LBB0_4: + divu a1, a2, a0 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_37.s b/benchmarks/LLC_ASM_selectiondag/7_function_37.s new file mode 100644 index 0000000..eb12cc4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_37.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + srl a1, a2, a0 + rem a1, a0, a1 + and a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_38.s b/benchmarks/LLC_ASM_selectiondag/7_function_38.s new file mode 100644 index 0000000..195d07c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_38.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a1 + and a0, a0, a3 + remu a4, a0, a3 + beq a4, a2, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + or a0, a3, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_39.s b/benchmarks/LLC_ASM_selectiondag/7_function_39.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_39.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_4.s b/benchmarks/LLC_ASM_selectiondag/7_function_4.s new file mode 100644 index 0000000..75a8089 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_4.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a0, a1 + srl a3, a3, a3 + divu a3, a3, a1 + and a3, a2, a3 + sra a2, a2, a3 + and a1, a1, a2 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_40.s b/benchmarks/LLC_ASM_selectiondag/7_function_40.s new file mode 100644 index 0000000..6847e41 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_40.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a2 + rem a3, a2, a1 + zext.w a0, a0 + srl a0, a0, a1 + srl a1, a3, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_41.s b/benchmarks/LLC_ASM_selectiondag/7_function_41.s new file mode 100644 index 0000000..462953e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_41.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a0, a1 + and a1, a1, a0 + srl a1, a2, a1 + srl a1, a0, a1 + and a0, a0, a2 + divu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_42.s b/benchmarks/LLC_ASM_selectiondag/7_function_42.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_42.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_43.s b/benchmarks/LLC_ASM_selectiondag/7_function_43.s new file mode 100644 index 0000000..692f099 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_43.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + sra a0, a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 + j .LBB0_3 +.LBB0_2: + mv a2, a0 +.LBB0_3: + sext.w a2, a2 + remu a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_44.s b/benchmarks/LLC_ASM_selectiondag/7_function_44.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_44.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_45.s b/benchmarks/LLC_ASM_selectiondag/7_function_45.s new file mode 100644 index 0000000..4ad164e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_45.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a2, a1 + xor a1, a1, a2 + and a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_46.s b/benchmarks/LLC_ASM_selectiondag/7_function_46.s new file mode 100644 index 0000000..1194267 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_46.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_47.s b/benchmarks/LLC_ASM_selectiondag/7_function_47.s new file mode 100644 index 0000000..1e74fa0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_47.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a3, 1 + zext.w a3, a0 + sra a1, a1, a2 + xor a1, a3, a1 + bnez a4, .LBB0_2 +# %bb.1: + mv a0, a3 +.LBB0_2: + xor a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_48.s b/benchmarks/LLC_ASM_selectiondag/7_function_48.s new file mode 100644 index 0000000..83c2d62 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_48.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + divu a0, a0, a1 + rem a1, a2, a0 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_49.s b/benchmarks/LLC_ASM_selectiondag/7_function_49.s new file mode 100644 index 0000000..38a780d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_49.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + div a1, a0, a1 + sra a0, a0, a1 + remu a2, a0, a2 + srl a0, a0, a1 + or a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_5.s b/benchmarks/LLC_ASM_selectiondag/7_function_5.s new file mode 100644 index 0000000..43e0073 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_5.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a0 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_50.s b/benchmarks/LLC_ASM_selectiondag/7_function_50.s new file mode 100644 index 0000000..dd61f86 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_50.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a3, a2, a0 + srl a2, a3, a2 + divu a2, a1, a2 + div a0, a0, a2 + divu a1, a2, a1 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_51.s b/benchmarks/LLC_ASM_selectiondag/7_function_51.s new file mode 100644 index 0000000..4573881 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_51.s @@ -0,0 +1,33 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a3, 1 + mv a3, a1 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a2 +.LBB0_2: + or a0, a0, a1 + mv a5, a3 + bnez a4, .LBB0_4 +# %bb.3: + mv a5, a1 +.LBB0_4: + divu a1, a5, a3 + xor a1, a2, a1 + divu a1, a2, a1 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_52.s b/benchmarks/LLC_ASM_selectiondag/7_function_52.s new file mode 100644 index 0000000..79bd7b2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_52.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a0 + rem a2, a3, a2 + or a1, a1, a2 + sext.w a0, a0 + and a0, a1, a0 + divu a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_53.s b/benchmarks/LLC_ASM_selectiondag/7_function_53.s new file mode 100644 index 0000000..248529f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_53.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, -1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_54.s b/benchmarks/LLC_ASM_selectiondag/7_function_54.s new file mode 100644 index 0000000..a3756ab --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_54.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + sext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_55.s b/benchmarks/LLC_ASM_selectiondag/7_function_55.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_55.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_56.s b/benchmarks/LLC_ASM_selectiondag/7_function_56.s new file mode 100644 index 0000000..5d5ff02 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_56.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + sext.w a1, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_57.s b/benchmarks/LLC_ASM_selectiondag/7_function_57.s new file mode 100644 index 0000000..ef88aa7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_57.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a0 + rem a0, a0, a1 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_58.s b/benchmarks/LLC_ASM_selectiondag/7_function_58.s new file mode 100644 index 0000000..769b96c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_58.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a2, a2, a1 + remu a2, a2, a1 + xor a0, a0, a1 + rem a0, a0, a2 + rem a1, a0, a2 + and a1, a2, a1 + slt a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_59.s b/benchmarks/LLC_ASM_selectiondag/7_function_59.s new file mode 100644 index 0000000..6568f7d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_59.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + srl a1, a1, a0 + sra a1, a0, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_6.s b/benchmarks/LLC_ASM_selectiondag/7_function_6.s new file mode 100644 index 0000000..8527848 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_6.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a1, a1, a2 + srl a2, a0, a0 + or a0, a2, a0 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_60.s b/benchmarks/LLC_ASM_selectiondag/7_function_60.s new file mode 100644 index 0000000..0e500bd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_60.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a2, a2, a0 + ori a1, a2, 1 + div a1, a0, a1 + xor a1, a1, a0 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_61.s b/benchmarks/LLC_ASM_selectiondag/7_function_61.s new file mode 100644 index 0000000..97daa86 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_61.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a3, a0, a1 + zext.w a0, a2 + mv a2, a0 + blt a1, a3, .LBB0_2 +# %bb.1: + mv a2, a1 +.LBB0_2: + sltu a0, a2, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_62.s b/benchmarks/LLC_ASM_selectiondag/7_function_62.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_62.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_63.s b/benchmarks/LLC_ASM_selectiondag/7_function_63.s new file mode 100644 index 0000000..542fcd4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_63.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a2 + and a1, a0, a1 + divu a1, a1, a2 + sext.w a1, a1 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_64.s b/benchmarks/LLC_ASM_selectiondag/7_function_64.s new file mode 100644 index 0000000..1467607 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_64.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a2 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_65.s b/benchmarks/LLC_ASM_selectiondag/7_function_65.s new file mode 100644 index 0000000..3a21f61 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_65.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + and a0, a0, a1 + srai a0, a0, 1 + rem a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_66.s b/benchmarks/LLC_ASM_selectiondag/7_function_66.s new file mode 100644 index 0000000..568d0e0 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_66.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + remu a3, a0, a1 + bgeu a3, a0, .LBB0_2 +# %bb.1: + divu a0, a1, a2 + remu a1, a0, a1 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_67.s b/benchmarks/LLC_ASM_selectiondag/7_function_67.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_67.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_68.s b/benchmarks/LLC_ASM_selectiondag/7_function_68.s new file mode 100644 index 0000000..c6f54fa --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_68.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a0, a1, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_69.s b/benchmarks/LLC_ASM_selectiondag/7_function_69.s new file mode 100644 index 0000000..fd2daa9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_69.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + and a2, a1, a2 + sra a0, a0, a2 + sext.w a2, a0 + or a0, a0, a1 + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_7.s b/benchmarks/LLC_ASM_selectiondag/7_function_7.s new file mode 100644 index 0000000..0246d35 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_7.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a2, a0 + and a1, a1, a2 + srl a0, a0, a1 + remu a0, a0, a1 + sext.w a3, a3 + or a3, a3, a0 + sltu a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_70.s b/benchmarks/LLC_ASM_selectiondag/7_function_70.s new file mode 100644 index 0000000..4bbfed3 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_70.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a0, a0 + div a2, a0, a2 + rem a0, a0, a1 + zext.w a0, a0 + xor a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_71.s b/benchmarks/LLC_ASM_selectiondag/7_function_71.s new file mode 100644 index 0000000..2553e39 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_71.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a3, a2, a1 + rem a1, a1, a2 + divu a0, a0, a1 + or a0, a0, a2 + rem a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_72.s b/benchmarks/LLC_ASM_selectiondag/7_function_72.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_72.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_73.s b/benchmarks/LLC_ASM_selectiondag/7_function_73.s new file mode 100644 index 0000000..297a7fe --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_73.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_74.s b/benchmarks/LLC_ASM_selectiondag/7_function_74.s new file mode 100644 index 0000000..68a15d9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_74.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a1, a2 + divu a3, a2, a0 + xor a0, a0, a2 + xor a0, a0, a1 + xor a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_75.s b/benchmarks/LLC_ASM_selectiondag/7_function_75.s new file mode 100644 index 0000000..8b0874a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_75.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a1, a0, a1 + andi a3, a1, 1 + bnez a3, .LBB0_2 +# %bb.1: + rem a0, a1, a0 + xori a2, a0, 1 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_76.s b/benchmarks/LLC_ASM_selectiondag/7_function_76.s new file mode 100644 index 0000000..31e072c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_76.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a4, 1 + divu a2, a4, a2 + andi a3, a3, 1 + or a2, a2, a0 + beqz a3, .LBB0_2 +# %bb.1: + divu a1, a0, a1 +.LBB0_2: + or a0, a2, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_77.s b/benchmarks/LLC_ASM_selectiondag/7_function_77.s new file mode 100644 index 0000000..7626ea5 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_77.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a4, 1 + srl a0, a4, a0 + andi a3, a3, 1 + xor a1, a0, a1 + and a1, a1, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + divu a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_78.s b/benchmarks/LLC_ASM_selectiondag/7_function_78.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_78.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_79.s b/benchmarks/LLC_ASM_selectiondag/7_function_79.s new file mode 100644 index 0000000..6a406b9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_79.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + rem a1, a0, a2 + zext.w a1, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_8.s b/benchmarks/LLC_ASM_selectiondag/7_function_8.s new file mode 100644 index 0000000..c382f8a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_8.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + mv a0, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + or a1, a2, a1 + remu a2, a2, a1 + or a1, a2, a1 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_80.s b/benchmarks/LLC_ASM_selectiondag/7_function_80.s new file mode 100644 index 0000000..4fc6442 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_80.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a2 + beq a0, a1, .LBB0_2 +# %bb.1: + divu a3, a2, a1 +.LBB0_2: + or a4, a0, a2 + mv a2, a3 + bltu a1, a4, .LBB0_4 +# %bb.3: + mv a2, a0 +.LBB0_4: + sra a0, a3, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_81.s b/benchmarks/LLC_ASM_selectiondag/7_function_81.s new file mode 100644 index 0000000..d0c064b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_81.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + srl a1, a0, a1 + xor a2, a2, a0 + rem a2, a1, a2 + srl a0, a0, a1 + or a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_82.s b/benchmarks/LLC_ASM_selectiondag/7_function_82.s new file mode 100644 index 0000000..7db0a96 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_82.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a2 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_83.s b/benchmarks/LLC_ASM_selectiondag/7_function_83.s new file mode 100644 index 0000000..94f3118 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_83.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + sext.w a0, a0 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_84.s b/benchmarks/LLC_ASM_selectiondag/7_function_84.s new file mode 100644 index 0000000..55379ee --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_84.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + and a2, a2, a0 + xor a1, a2, a1 + and a1, a0, a1 + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_85.s b/benchmarks/LLC_ASM_selectiondag/7_function_85.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_85.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_86.s b/benchmarks/LLC_ASM_selectiondag/7_function_86.s new file mode 100644 index 0000000..2e9114b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_86.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + rem a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_87.s b/benchmarks/LLC_ASM_selectiondag/7_function_87.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_87.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_88.s b/benchmarks/LLC_ASM_selectiondag/7_function_88.s new file mode 100644 index 0000000..43f3185 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_88.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + sext.w a1, a2 +.LBB0_2: + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_89.s b/benchmarks/LLC_ASM_selectiondag/7_function_89.s new file mode 100644 index 0000000..7098c54 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_89.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a2 + divu a2, a2, a1 + and a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_9.s b/benchmarks/LLC_ASM_selectiondag/7_function_9.s new file mode 100644 index 0000000..7b956f6 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_9.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + and a2, a1, a2 + remu a1, a2, a1 + srl a1, a0, a1 + or a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_90.s b/benchmarks/LLC_ASM_selectiondag/7_function_90.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_90.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_91.s b/benchmarks/LLC_ASM_selectiondag/7_function_91.s new file mode 100644 index 0000000..e11442b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_91.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a0, a1 + sra a1, a0, a1 + rem a0, a0, a1 + rem a0, a0, a2 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_92.s b/benchmarks/LLC_ASM_selectiondag/7_function_92.s new file mode 100644 index 0000000..08087c3 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_92.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a1, a1, a0 + xor a1, a0, a1 + andi a1, a1, 1 + bnez a1, .LBB0_2 +# %bb.1: + sext.w a2, a0 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_93.s b/benchmarks/LLC_ASM_selectiondag/7_function_93.s new file mode 100644 index 0000000..d1383bc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_93.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a1, a2 + sext.w a0, a0 + divu a0, a0, a1 + sext.w a0, a0 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_94.s b/benchmarks/LLC_ASM_selectiondag/7_function_94.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_94.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_95.s b/benchmarks/LLC_ASM_selectiondag/7_function_95.s new file mode 100644 index 0000000..0e6e05a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_95.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a1, a2 + xori a0, a0, 1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_96.s b/benchmarks/LLC_ASM_selectiondag/7_function_96.s new file mode 100644 index 0000000..339e699 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_96.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a0, a0 + sra a3, a2, a0 + sra a3, a0, a3 + div a0, a0, a3 + xor a1, a2, a1 + xor a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_97.s b/benchmarks/LLC_ASM_selectiondag/7_function_97.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_97.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_98.s b/benchmarks/LLC_ASM_selectiondag/7_function_98.s new file mode 100644 index 0000000..52785f2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_98.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bgtz a0, .LBB0_2 +# %bb.1: + sra a2, a0, a1 +.LBB0_2: + and a0, a0, a2 + srai a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/7_function_99.s b/benchmarks/LLC_ASM_selectiondag/7_function_99.s new file mode 100644 index 0000000..bdd4cd1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/7_function_99.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a1 + and a2, a1, a2 + div a2, a0, a2 + andi a2, a2, 1 + bnez a2, .LBB0_2 +# %bb.1: + sext.w a1, a0 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_0.s b/benchmarks/LLC_ASM_selectiondag/8_function_0.s new file mode 100644 index 0000000..4839eb7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_0.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a2 + divu a1, a1, a2 + srai a0, a0, 1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_1.s b/benchmarks/LLC_ASM_selectiondag/8_function_1.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_1.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_10.s b/benchmarks/LLC_ASM_selectiondag/8_function_10.s new file mode 100644 index 0000000..70f5ee8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_10.s @@ -0,0 +1,32 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + divu a0, a0, a1 + or a3, a3, a0 + xor a3, a3, a2 + srl a4, a0, a2 + andi a1, a3, 1 + bge a4, a3, .LBB0_3 +# %bb.1: + beqz a1, .LBB0_4 +.LBB0_2: + ret +.LBB0_3: + mv a0, a3 + bnez a1, .LBB0_2 +.LBB0_4: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_11.s b/benchmarks/LLC_ASM_selectiondag/8_function_11.s new file mode 100644 index 0000000..ee39ace --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_11.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a0, a2 + remu a2, a0, a2 + srl a0, a0, a1 + remu a1, a2, a0 + div a0, a0, a1 + and a0, a3, a0 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_12.s b/benchmarks/LLC_ASM_selectiondag/8_function_12.s new file mode 100644 index 0000000..282950e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_12.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a3, a0, a1 + and a0, a0, a3 + div a0, a1, a0 + srl a1, a3, a2 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_13.s b/benchmarks/LLC_ASM_selectiondag/8_function_13.s new file mode 100644 index 0000000..297a7fe --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_13.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + and a0, a0, a1 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_14.s b/benchmarks/LLC_ASM_selectiondag/8_function_14.s new file mode 100644 index 0000000..03a1be2 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_14.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a1, a2 + divu a2, a0, a2 + remu a4, a2, a0 + andi a3, a3, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + srl a0, a1, a4 + remu a0, a4, a0 + sltu a0, a0, a2 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_15.s b/benchmarks/LLC_ASM_selectiondag/8_function_15.s new file mode 100644 index 0000000..7333c9f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_15.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a4, a0, a1 + remu a1, a4, a1 + bltu a0, a1, .LBB0_2 +# %bb.1: + div a2, a0, a4 +.LBB0_2: + and a2, a3, a2 + zext.w a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_16.s b/benchmarks/LLC_ASM_selectiondag/8_function_16.s new file mode 100644 index 0000000..4d62b9f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_16.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + rem a3, a1, a2 + zext.w a3, a3 + remu a3, a0, a3 + remu a2, a3, a2 + or a0, a0, a1 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_17.s b/benchmarks/LLC_ASM_selectiondag/8_function_17.s new file mode 100644 index 0000000..7b77c93 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_17.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + remu a3, a0, a1 + remu a4, a1, a0 + div a0, a2, a0 + and a0, a4, a0 + xor a0, a1, a0 + srl a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_18.s b/benchmarks/LLC_ASM_selectiondag/8_function_18.s new file mode 100644 index 0000000..98535a9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_18.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + zext.w a0, a0 + remu a1, a0, a1 + srl a0, a0, a1 + zext.w a1, a2 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_19.s b/benchmarks/LLC_ASM_selectiondag/8_function_19.s new file mode 100644 index 0000000..eba64ab --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_19.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a0, a0, a1 + or a1, a0, a2 + remu a0, a1, a0 + andi a1, a0, 1 + bnez a1, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + sext.w a0, a2 + sltu a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_2.s b/benchmarks/LLC_ASM_selectiondag/8_function_2.s new file mode 100644 index 0000000..3a7b862 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_2.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + remu a2, a2, a1 + srl a1, a1, a2 + and a0, a0, a1 + remu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_20.s b/benchmarks/LLC_ASM_selectiondag/8_function_20.s new file mode 100644 index 0000000..28b8c01 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_20.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a1, a0, a1 + rem a2, a1, a2 + zext.w a3, a2 + srl a2, a3, a2 + divu a1, a1, a2 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_21.s b/benchmarks/LLC_ASM_selectiondag/8_function_21.s new file mode 100644 index 0000000..05bb69e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_21.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a1 + rem a0, a0, a3 + divu a1, a2, a1 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_22.s b/benchmarks/LLC_ASM_selectiondag/8_function_22.s new file mode 100644 index 0000000..df67321 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_22.s @@ -0,0 +1,31 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a0, 1 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a0 + bnez a4, .LBB0_3 + j .LBB0_4 +.LBB0_2: + srl a3, a2, a1 + beqz a4, .LBB0_4 +.LBB0_3: + srl a0, a0, a0 + sra a0, a0, a2 + remu a3, a1, a0 +.LBB0_4: + mv a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_23.s b/benchmarks/LLC_ASM_selectiondag/8_function_23.s new file mode 100644 index 0000000..4284b59 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_23.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + divu a0, a2, a0 + div a1, a1, a2 + zext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_24.s b/benchmarks/LLC_ASM_selectiondag/8_function_24.s new file mode 100644 index 0000000..1a3a5b4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_24.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a2 + divu a2, a2, a3 + zext.w a1, a1 + srl a1, a1, a2 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_25.s b/benchmarks/LLC_ASM_selectiondag/8_function_25.s new file mode 100644 index 0000000..d9c8024 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_25.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a1, 1 + mv a1, a0 + bnez a4, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + div a0, a0, a1 + srl a0, a0, a3 + srl a0, a0, a3 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_26.s b/benchmarks/LLC_ASM_selectiondag/8_function_26.s new file mode 100644 index 0000000..62a826e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_26.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a1, a1 + divu a1, a0, a1 + and a2, a1, a2 + sra a2, a2, a1 + divu a1, a1, a2 + sra a0, a0, a1 + div a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_27.s b/benchmarks/LLC_ASM_selectiondag/8_function_27.s new file mode 100644 index 0000000..7028522 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_27.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + mv a1, a0 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a2 +.LBB0_2: + sra a1, a1, a0 + and a1, a0, a1 + srl a2, a0, a0 + sra a1, a1, a2 + sext.w a1, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_28.s b/benchmarks/LLC_ASM_selectiondag/8_function_28.s new file mode 100644 index 0000000..8763fef --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_28.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + mv a0, a2 + j .LBB0_3 +.LBB0_2: + zext.w a0, a1 +.LBB0_3: + sra a0, a0, a1 + zext.w a1, a2 + sltu a0, a0, a1 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_29.s b/benchmarks/LLC_ASM_selectiondag/8_function_29.s new file mode 100644 index 0000000..9858af9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_29.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a5, a2, a0 + andi a6, a3, 1 + and a4, a0, a1 + xor a3, a4, a5 + bnez a6, .LBB0_2 +# %bb.1: + xor a4, a2, a1 +.LBB0_2: + rem a1, a3, a4 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_3.s b/benchmarks/LLC_ASM_selectiondag/8_function_3.s new file mode 100644 index 0000000..ce59e5c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_3.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a2, a0 + srl a1, a2, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_30.s b/benchmarks/LLC_ASM_selectiondag/8_function_30.s new file mode 100644 index 0000000..689c43e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_30.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sgtz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_31.s b/benchmarks/LLC_ASM_selectiondag/8_function_31.s new file mode 100644 index 0000000..8b84306 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_31.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a0 + divu a3, a0, a1 + sext.w a0, a3 + srl a3, a3, a2 + bltu a0, a3, .LBB0_2 +# %bb.1: + rem a2, a0, a1 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_32.s b/benchmarks/LLC_ASM_selectiondag/8_function_32.s new file mode 100644 index 0000000..083122b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_32.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a1, a0, 1 + mv a0, a2 + beqz a1, .LBB0_2 +# %bb.1: + srl a1, a0, a0 + srl a0, a0, a1 + sext.w a0, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_33.s b/benchmarks/LLC_ASM_selectiondag/8_function_33.s new file mode 100644 index 0000000..141c7b6 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_33.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + remu a1, a0, a1 + remu a0, a1, a2 + srl a1, a0, a1 + mv a2, a1 + bnez a3, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + remu a1, a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_34.s b/benchmarks/LLC_ASM_selectiondag/8_function_34.s new file mode 100644 index 0000000..b5964d9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_34.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a1 + rem a1, a0, a1 + div a1, a2, a1 + div a2, a0, a1 + or a0, a0, a1 + rem a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_35.s b/benchmarks/LLC_ASM_selectiondag/8_function_35.s new file mode 100644 index 0000000..e7c61af --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_35.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a0 + div a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_36.s b/benchmarks/LLC_ASM_selectiondag/8_function_36.s new file mode 100644 index 0000000..4760aac --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_36.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a2, a1, a2 + andi a0, a0, 1 + bnez a0, .LBB0_2 +# %bb.1: + rem a0, a1, a2 + div a2, a1, a0 +.LBB0_2: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_37.s b/benchmarks/LLC_ASM_selectiondag/8_function_37.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_37.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_38.s b/benchmarks/LLC_ASM_selectiondag/8_function_38.s new file mode 100644 index 0000000..aaac42b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_38.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + bgeu a1, a0, .LBB0_2 +# %bb.1: + zext.w a0, a3 + ret +.LBB0_2: + divu a2, a1, a2 + or a1, a0, a1 + xor a1, a1, a2 + xor a0, a0, a1 + and a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_39.s b/benchmarks/LLC_ASM_selectiondag/8_function_39.s new file mode 100644 index 0000000..8e2caf9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_39.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a0, a0, a0 + addi a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_4.s b/benchmarks/LLC_ASM_selectiondag/8_function_4.s new file mode 100644 index 0000000..eaefe90 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_4.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a4, a0, a1 + andi a5, a3, 1 + srl a1, a2, a1 + sra a1, a4, a1 + mv a3, a2 + bnez a5, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + sra a0, a3, a1 + or a0, a1, a0 + remu a1, a2, a0 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_40.s b/benchmarks/LLC_ASM_selectiondag/8_function_40.s new file mode 100644 index 0000000..b9ba493 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_40.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a2, a2, a2 + or a1, a1, a2 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_41.s b/benchmarks/LLC_ASM_selectiondag/8_function_41.s new file mode 100644 index 0000000..83ec999 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_41.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + mv a4, a2 + bge a0, a1, .LBB0_2 +# %bb.1: + mv a4, a3 +.LBB0_2: + sra a0, a2, a4 + and a0, a3, a0 + bge a3, a1, .LBB0_4 +# %bb.3: + xor a0, a4, a0 + remu a0, a4, a0 +.LBB0_4: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_42.s b/benchmarks/LLC_ASM_selectiondag/8_function_42.s new file mode 100644 index 0000000..60840ae --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_42.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + andi a3, a1, 1 + mv a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + srl a0, a1, a0 + zext.w a2, a0 + rem a1, a1, a2 + srl a0, a1, a0 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_43.s b/benchmarks/LLC_ASM_selectiondag/8_function_43.s new file mode 100644 index 0000000..e6cfb88 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_43.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a1, 1 + sext.w a0, a0 + mv a1, a2 + bnez a3, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + remu a2, a0, a2 + sra a0, a0, a1 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_44.s b/benchmarks/LLC_ASM_selectiondag/8_function_44.s new file mode 100644 index 0000000..be6ff0c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_44.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a2, a0, a1 + div a0, a1, a0 + zext.w a1, a2 + slt a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_45.s b/benchmarks/LLC_ASM_selectiondag/8_function_45.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_45.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_46.s b/benchmarks/LLC_ASM_selectiondag/8_function_46.s new file mode 100644 index 0000000..4d96e93 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_46.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a2 + div a1, a0, a1 + div a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_47.s b/benchmarks/LLC_ASM_selectiondag/8_function_47.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_47.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_48.s b/benchmarks/LLC_ASM_selectiondag/8_function_48.s new file mode 100644 index 0000000..139405d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_48.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a0 + div a4, a0, a3 + divu a0, a0, a2 + remu a2, a3, a1 + srl a0, a1, a0 + xor a0, a0, a2 + rem a0, a4, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_49.s b/benchmarks/LLC_ASM_selectiondag/8_function_49.s new file mode 100644 index 0000000..da8934e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_49.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a3, a3 + divu a3, a0, a3 + andi a4, a2, 1 + and a1, a1, a3 + mv a2, a1 + bnez a4, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + and a1, a1, a2 + and a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_5.s b/benchmarks/LLC_ASM_selectiondag/8_function_5.s new file mode 100644 index 0000000..dc9e7df --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_5.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a2, a1, a2 + sra a1, a1, a1 + sext.w a2, a2 + rem a1, a1, a2 + sext.w a1, a1 + xor a0, a0, a1 + snez a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_50.s b/benchmarks/LLC_ASM_selectiondag/8_function_50.s new file mode 100644 index 0000000..fb36ced --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_50.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a2 + sra a0, a0, a0 + divu a1, a0, a1 + slli a3, a3, 63 + srai a3, a3, 63 + and a0, a3, a0 + or a0, a1, a0 + srl a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_51.s b/benchmarks/LLC_ASM_selectiondag/8_function_51.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_51.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_52.s b/benchmarks/LLC_ASM_selectiondag/8_function_52.s new file mode 100644 index 0000000..969d8f8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_52.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a0, a1 + sext.w a1, a1 + remu a1, a0, a1 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_53.s b/benchmarks/LLC_ASM_selectiondag/8_function_53.s new file mode 100644 index 0000000..6be161a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_53.s @@ -0,0 +1,18 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a0, a0, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_54.s b/benchmarks/LLC_ASM_selectiondag/8_function_54.s new file mode 100644 index 0000000..41f93bd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_54.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srl a1, a1, a2 + sext.w a2, a2 + remu a1, a1, a2 + and a1, a1, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_55.s b/benchmarks/LLC_ASM_selectiondag/8_function_55.s new file mode 100644 index 0000000..f6d685b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_55.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a0, a1 + divu a3, a2, a1 + or a2, a1, a2 + div a2, a2, a3 + divu a0, a0, a2 + remu a0, a1, a0 + zext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_56.s b/benchmarks/LLC_ASM_selectiondag/8_function_56.s new file mode 100644 index 0000000..35703ca --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_56.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a3, a0, a1 + or a1, a1, a0 + remu a1, a2, a1 + zext.w a0, a0 + div a0, a0, a1 + rem a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_57.s b/benchmarks/LLC_ASM_selectiondag/8_function_57.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_57.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_58.s b/benchmarks/LLC_ASM_selectiondag/8_function_58.s new file mode 100644 index 0000000..0eab13b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_58.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a1, a1, a0 + and a0, a0, a1 + remu a1, a1, a0 + sext.w a0, a0 + zext.w a1, a1 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_59.s b/benchmarks/LLC_ASM_selectiondag/8_function_59.s new file mode 100644 index 0000000..b909e40 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_59.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a2, a2, a0 + and a0, a0, a1 + sext.w a0, a0 + divu a0, a0, a2 + rem a1, a2, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_6.s b/benchmarks/LLC_ASM_selectiondag/8_function_6.s new file mode 100644 index 0000000..ad04066 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_6.s @@ -0,0 +1,29 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a3, 1 + zext.w a0, a0 + mv a3, a2 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + or a2, a2, a3 + rem a3, a2, a3 + xor a3, a2, a3 + divu a2, a3, a2 + rem a1, a1, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_60.s b/benchmarks/LLC_ASM_selectiondag/8_function_60.s new file mode 100644 index 0000000..5020772 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_60.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a1, 1 + sext.w a3, a0 + bnez a4, .LBB0_2 +# %bb.1: + mv a2, a0 +.LBB0_2: + rem a1, a1, a2 + xor a0, a0, a1 + div a0, a3, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_61.s b/benchmarks/LLC_ASM_selectiondag/8_function_61.s new file mode 100644 index 0000000..72d636a --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_61.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + rem a3, a0, a1 + xor a1, a1, a2 + xor a1, a1, a3 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_62.s b/benchmarks/LLC_ASM_selectiondag/8_function_62.s new file mode 100644 index 0000000..b3619ff --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_62.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a1, a1, a2 + div a1, a1, a2 + zext.w a0, a0 + xor a0, a0, a1 + sra a0, a0, a2 + and a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_63.s b/benchmarks/LLC_ASM_selectiondag/8_function_63.s new file mode 100644 index 0000000..d85768e --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_63.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a4, a1, a0 + srl a3, a1, a2 + div a3, a4, a3 + bgeu a2, a4, .LBB0_2 +# %bb.1: + mv a1, a3 +.LBB0_2: + remu a0, a0, a1 + srl a1, a3, a1 + sltu a0, a1, a0 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_64.s b/benchmarks/LLC_ASM_selectiondag/8_function_64.s new file mode 100644 index 0000000..1b5c062 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_64.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a3, a2, a0 + div a3, a3, a2 + divu a2, a1, a2 + remu a2, a2, a3 + srl a0, a0, a1 + rem a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_65.s b/benchmarks/LLC_ASM_selectiondag/8_function_65.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_65.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_66.s b/benchmarks/LLC_ASM_selectiondag/8_function_66.s new file mode 100644 index 0000000..b118b4d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_66.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_67.s b/benchmarks/LLC_ASM_selectiondag/8_function_67.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_67.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_68.s b/benchmarks/LLC_ASM_selectiondag/8_function_68.s new file mode 100644 index 0000000..f93815f --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_68.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_69.s b/benchmarks/LLC_ASM_selectiondag/8_function_69.s new file mode 100644 index 0000000..3c1dd44 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_69.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a3, 1 + rem a0, a0, a1 + div a1, a3, a2 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_7.s b/benchmarks/LLC_ASM_selectiondag/8_function_7.s new file mode 100644 index 0000000..b84ec79 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_7.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + and a4, a1, a0 + remu a0, a0, a4 + andi a3, a3, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a4, a0 +.LBB0_2: + and a1, a1, a4 + and a1, a0, a1 + remu a1, a2, a1 + or a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_70.s b/benchmarks/LLC_ASM_selectiondag/8_function_70.s new file mode 100644 index 0000000..113afeb --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_70.s @@ -0,0 +1,31 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a2 + andi a3, a1, 1 + mv a1, a2 + bne a2, a0, .LBB0_3 +# %bb.1: + beqz a3, .LBB0_4 +.LBB0_2: + srl a0, a0, a1 + ret +.LBB0_3: + mv a1, a0 + bnez a3, .LBB0_2 +.LBB0_4: + srl a1, a0, a2 + srl a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_71.s b/benchmarks/LLC_ASM_selectiondag/8_function_71.s new file mode 100644 index 0000000..a98ceec --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_71.s @@ -0,0 +1,34 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + bge a1, a0, .LBB0_4 +# %bb.1: + andi a1, a0, 1 + beqz a1, .LBB0_5 +.LBB0_2: + beqz a1, .LBB0_6 +.LBB0_3: + ret +.LBB0_4: + mv a0, a2 + andi a1, a2, 1 + bnez a1, .LBB0_2 +.LBB0_5: + srl a2, a3, a0 + bnez a1, .LBB0_3 +.LBB0_6: + mv a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_72.s b/benchmarks/LLC_ASM_selectiondag/8_function_72.s new file mode 100644 index 0000000..8bc4976 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_72.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_73.s b/benchmarks/LLC_ASM_selectiondag/8_function_73.s new file mode 100644 index 0000000..9307797 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_73.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a1, a1, a2 + sext.w a1, a1 + divu a0, a0, a1 + xori a1, a0, 1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_74.s b/benchmarks/LLC_ASM_selectiondag/8_function_74.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_74.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_75.s b/benchmarks/LLC_ASM_selectiondag/8_function_75.s new file mode 100644 index 0000000..9a9fef9 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_75.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_76.s b/benchmarks/LLC_ASM_selectiondag/8_function_76.s new file mode 100644 index 0000000..69e879d --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_76.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a3, 1 + div a1, a3, a1 + andi a3, a2, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + rem a0, a1, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_77.s b/benchmarks/LLC_ASM_selectiondag/8_function_77.s new file mode 100644 index 0000000..c010613 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_77.s @@ -0,0 +1,28 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a2, 1 + sext.w a2, a0 + xor a2, a2, a1 + mv a3, a2 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a0 +.LBB0_2: + div a1, a1, a0 + rem a1, a3, a1 + or a0, a0, a1 + xor a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_78.s b/benchmarks/LLC_ASM_selectiondag/8_function_78.s new file mode 100644 index 0000000..30239d5 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_78.s @@ -0,0 +1,32 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a4, a3, 1 + mv a3, a1 + bnez a4, .LBB0_2 +# %bb.1: + mv a3, a2 +.LBB0_2: + zext.w a0, a0 + or a1, a1, a2 + bnez a4, .LBB0_4 +# %bb.3: + mv a2, a3 +.LBB0_4: + div a3, a3, a0 + srl a2, a2, a3 + remu a1, a1, a2 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_79.s b/benchmarks/LLC_ASM_selectiondag/8_function_79.s new file mode 100644 index 0000000..465b640 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_79.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a2, a2, 1 + bnez a2, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + zext.w a0, a0 + div a0, a1, a0 + sltiu a0, a0, 2 + xori a0, a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_8.s b/benchmarks/LLC_ASM_selectiondag/8_function_8.s new file mode 100644 index 0000000..0850b9b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_8.s @@ -0,0 +1,24 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a4, a0, a1 + and a3, a3, a0 + and a0, a0, a4 + zext.w a3, a3 + xor a0, a0, a2 + or a1, a1, a3 + xor a0, a0, a1 + seqz a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_80.s b/benchmarks/LLC_ASM_selectiondag/8_function_80.s new file mode 100644 index 0000000..3d23ba6 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_80.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + rem a1, a1, a2 + srl a1, a2, a1 + rem a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_81.s b/benchmarks/LLC_ASM_selectiondag/8_function_81.s new file mode 100644 index 0000000..fa5e210 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_81.s @@ -0,0 +1,27 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + andi a3, a0, 1 + bnez a3, .LBB0_2 +# %bb.1: + mv a0, a1 +.LBB0_2: + div a2, a2, a1 + sra a2, a0, a2 + and a0, a2, a0 + div a1, a0, a1 + div a1, a2, a1 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_82.s b/benchmarks/LLC_ASM_selectiondag/8_function_82.s new file mode 100644 index 0000000..0885ee8 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_82.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + remu a0, a0, a1 + blt a1, a0, .LBB0_2 +# %bb.1: + mv a1, a0 +.LBB0_2: + mv a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_83.s b/benchmarks/LLC_ASM_selectiondag/8_function_83.s new file mode 100644 index 0000000..de3cfdd --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_83.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a1 + li a1, 1 + remu a2, a1, a0 + srl a0, a1, a0 + srl a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_84.s b/benchmarks/LLC_ASM_selectiondag/8_function_84.s new file mode 100644 index 0000000..b47c119 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_84.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a1, a1 + rem a1, a0, a1 + and a0, a0, a1 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_85.s b/benchmarks/LLC_ASM_selectiondag/8_function_85.s new file mode 100644 index 0000000..6ec9855 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_85.s @@ -0,0 +1,20 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a0, a0 + remu a1, a0, a2 + divu a0, a2, a0 + slt a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_86.s b/benchmarks/LLC_ASM_selectiondag/8_function_86.s new file mode 100644 index 0000000..ba24389 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_86.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a0, 1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_87.s b/benchmarks/LLC_ASM_selectiondag/8_function_87.s new file mode 100644 index 0000000..eb09cd7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_87.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a0, a0 + remu a0, a0, a1 + srl a0, a0, a1 + sra a0, a0, a2 + sext.w a0, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_88.s b/benchmarks/LLC_ASM_selectiondag/8_function_88.s new file mode 100644 index 0000000..8d2b737 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_88.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a3, a1, a2 + div a3, a0, a3 + rem a1, a3, a1 + xor a0, a2, a0 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_89.s b/benchmarks/LLC_ASM_selectiondag/8_function_89.s new file mode 100644 index 0000000..6e437cc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_89.s @@ -0,0 +1,19 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + xor a2, a0, a1 + and a0, a1, a0 + div a0, a2, a0 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_9.s b/benchmarks/LLC_ASM_selectiondag/8_function_9.s new file mode 100644 index 0000000..39fcdc4 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_9.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sext.w a2, a2 + sra a0, a0, a1 + remu a2, a2, a0 + and a1, a0, a1 + divu a2, a2, a1 + rem a1, a2, a1 + div a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_90.s b/benchmarks/LLC_ASM_selectiondag/8_function_90.s new file mode 100644 index 0000000..5cbf046 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_90.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + mv a3, a0 + sext.w a4, a0 + mv a0, a1 + beq a3, a4, .LBB0_2 +# %bb.1: + mv a0, a2 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_91.s b/benchmarks/LLC_ASM_selectiondag/8_function_91.s new file mode 100644 index 0000000..83ec05c --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_91.s @@ -0,0 +1,17 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + srli a0, a0, 63 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_92.s b/benchmarks/LLC_ASM_selectiondag/8_function_92.s new file mode 100644 index 0000000..de94492 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_92.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + li a2, 1 + andn a0, a2, a0 + or a0, a1, a0 + sext.w a0, a0 + and a1, a0, a1 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_93.s b/benchmarks/LLC_ASM_selectiondag/8_function_93.s new file mode 100644 index 0000000..4467cec --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_93.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + rem a2, a1, a2 + andi a3, a0, 1 + sext.w a0, a2 + bnez a3, .LBB0_2 +# %bb.1: + divu a0, a0, a1 +.LBB0_2: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_94.s b/benchmarks/LLC_ASM_selectiondag/8_function_94.s new file mode 100644 index 0000000..f13f3b1 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_94.s @@ -0,0 +1,25 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + div a0, a0, a1 + sext.w a3, a3 + blt a1, a0, .LBB0_2 +# %bb.1: + sra a0, a2, a0 + rem a0, a0, a3 +.LBB0_2: + rem a1, a2, a3 + sra a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_95.s b/benchmarks/LLC_ASM_selectiondag/8_function_95.s new file mode 100644 index 0000000..58ce6bc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_95.s @@ -0,0 +1,26 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + sra a3, a0, a1 + mv a0, a1 + bgeu a3, a2, .LBB0_2 +# %bb.1: + remu a0, a2, a1 +.LBB0_2: + divu a1, a1, a3 + sra a1, a0, a1 + divu a1, a0, a1 + sltu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_96.s b/benchmarks/LLC_ASM_selectiondag/8_function_96.s new file mode 100644 index 0000000..0804f4b --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_96.s @@ -0,0 +1,16 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_97.s b/benchmarks/LLC_ASM_selectiondag/8_function_97.s new file mode 100644 index 0000000..10494f7 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_97.s @@ -0,0 +1,23 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + zext.w a3, a2 + remu a3, a3, a1 + sext.w a0, a0 + xor a0, a0, a1 + or a0, a0, a3 + sext.w a2, a2 + divu a0, a0, a2 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_98.s b/benchmarks/LLC_ASM_selectiondag/8_function_98.s new file mode 100644 index 0000000..2a9e6cc --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_98.s @@ -0,0 +1,22 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + divu a0, a0, a1 + rem a3, a0, a1 + divu a1, a1, a2 + xor a3, a3, a0 + sra a1, a3, a1 + divu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLC_ASM_selectiondag/8_function_99.s b/benchmarks/LLC_ASM_selectiondag/8_function_99.s new file mode 100644 index 0000000..491d240 --- /dev/null +++ b/benchmarks/LLC_ASM_selectiondag/8_function_99.s @@ -0,0 +1,21 @@ + .attribute 4, 16 + .attribute 5, "rv64i2p1_m2p0_b1p0_zmmul1p0_zba1p0_zbb1p0_zbs1p0" + .file "LLVMDialectModule" + .text + .globl main # -- Begin function main + .p2align 2 + .type main,@function +main: # @main + .cfi_startproc +# %bb.0: + or a1, a1, a2 + srl a3, a1, a0 + div a1, a1, a3 + xor a0, a2, a0 + remu a0, a0, a1 + ret +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section ".note.GNU-stack","",@progbits diff --git a/benchmarks/LLVM/3_function_0.ll b/benchmarks/LLVM/3_function_0.ll new file mode 100644 index 0000000..fd5b009 --- /dev/null +++ b/benchmarks/LLVM/3_function_0.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_1.ll b/benchmarks/LLVM/3_function_1.ll new file mode 100644 index 0000000..c56ae45 --- /dev/null +++ b/benchmarks/LLVM/3_function_1.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_10.ll b/benchmarks/LLVM/3_function_10.ll new file mode 100644 index 0000000..53b9c70 --- /dev/null +++ b/benchmarks/LLVM/3_function_10.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_11.ll b/benchmarks/LLVM/3_function_11.ll new file mode 100644 index 0000000..3e9e734 --- /dev/null +++ b/benchmarks/LLVM/3_function_11.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_12.ll b/benchmarks/LLVM/3_function_12.ll new file mode 100644 index 0000000..c3a8279 --- /dev/null +++ b/benchmarks/LLVM/3_function_12.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_13.ll b/benchmarks/LLVM/3_function_13.ll new file mode 100644 index 0000000..e0bb2f2 --- /dev/null +++ b/benchmarks/LLVM/3_function_13.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_14.ll b/benchmarks/LLVM/3_function_14.ll new file mode 100644 index 0000000..f1ac1b8 --- /dev/null +++ b/benchmarks/LLVM/3_function_14.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_15.ll b/benchmarks/LLVM/3_function_15.ll new file mode 100644 index 0000000..1223c6f --- /dev/null +++ b/benchmarks/LLVM/3_function_15.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_16.ll b/benchmarks/LLVM/3_function_16.ll new file mode 100644 index 0000000..f913921 --- /dev/null +++ b/benchmarks/LLVM/3_function_16.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_17.ll b/benchmarks/LLVM/3_function_17.ll new file mode 100644 index 0000000..003a859 --- /dev/null +++ b/benchmarks/LLVM/3_function_17.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_18.ll b/benchmarks/LLVM/3_function_18.ll new file mode 100644 index 0000000..cc6906c --- /dev/null +++ b/benchmarks/LLVM/3_function_18.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_19.ll b/benchmarks/LLVM/3_function_19.ll new file mode 100644 index 0000000..2a7e49d --- /dev/null +++ b/benchmarks/LLVM/3_function_19.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_2.ll b/benchmarks/LLVM/3_function_2.ll new file mode 100644 index 0000000..6d62ba1 --- /dev/null +++ b/benchmarks/LLVM/3_function_2.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_20.ll b/benchmarks/LLVM/3_function_20.ll new file mode 100644 index 0000000..ef0b718 --- /dev/null +++ b/benchmarks/LLVM/3_function_20.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_21.ll b/benchmarks/LLVM/3_function_21.ll new file mode 100644 index 0000000..ec78c24 --- /dev/null +++ b/benchmarks/LLVM/3_function_21.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_22.ll b/benchmarks/LLVM/3_function_22.ll new file mode 100644 index 0000000..69d30db --- /dev/null +++ b/benchmarks/LLVM/3_function_22.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_23.ll b/benchmarks/LLVM/3_function_23.ll new file mode 100644 index 0000000..3fa14fe --- /dev/null +++ b/benchmarks/LLVM/3_function_23.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_24.ll b/benchmarks/LLVM/3_function_24.ll new file mode 100644 index 0000000..e6c5111 --- /dev/null +++ b/benchmarks/LLVM/3_function_24.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_25.ll b/benchmarks/LLVM/3_function_25.ll new file mode 100644 index 0000000..6f650d9 --- /dev/null +++ b/benchmarks/LLVM/3_function_25.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_26.ll b/benchmarks/LLVM/3_function_26.ll new file mode 100644 index 0000000..452a3a4 --- /dev/null +++ b/benchmarks/LLVM/3_function_26.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_27.ll b/benchmarks/LLVM/3_function_27.ll new file mode 100644 index 0000000..6092159 --- /dev/null +++ b/benchmarks/LLVM/3_function_27.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.or"(%arg0, %1) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_28.ll b/benchmarks/LLVM/3_function_28.ll new file mode 100644 index 0000000..976dab7 --- /dev/null +++ b/benchmarks/LLVM/3_function_28.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg2, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_29.ll b/benchmarks/LLVM/3_function_29.ll new file mode 100644 index 0000000..3d66268 --- /dev/null +++ b/benchmarks/LLVM/3_function_29.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%1, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_3.ll b/benchmarks/LLVM/3_function_3.ll new file mode 100644 index 0000000..e013abe --- /dev/null +++ b/benchmarks/LLVM/3_function_3.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_30.ll b/benchmarks/LLVM/3_function_30.ll new file mode 100644 index 0000000..f0040f2 --- /dev/null +++ b/benchmarks/LLVM/3_function_30.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_31.ll b/benchmarks/LLVM/3_function_31.ll new file mode 100644 index 0000000..19f578f --- /dev/null +++ b/benchmarks/LLVM/3_function_31.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_32.ll b/benchmarks/LLVM/3_function_32.ll new file mode 100644 index 0000000..8d3187a --- /dev/null +++ b/benchmarks/LLVM/3_function_32.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_33.ll b/benchmarks/LLVM/3_function_33.ll new file mode 100644 index 0000000..42bce5b --- /dev/null +++ b/benchmarks/LLVM/3_function_33.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_34.ll b/benchmarks/LLVM/3_function_34.ll new file mode 100644 index 0000000..8c2fd76 --- /dev/null +++ b/benchmarks/LLVM/3_function_34.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_35.ll b/benchmarks/LLVM/3_function_35.ll new file mode 100644 index 0000000..0669a3c --- /dev/null +++ b/benchmarks/LLVM/3_function_35.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_36.ll b/benchmarks/LLVM/3_function_36.ll new file mode 100644 index 0000000..6f650d9 --- /dev/null +++ b/benchmarks/LLVM/3_function_36.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_37.ll b/benchmarks/LLVM/3_function_37.ll new file mode 100644 index 0000000..c159e87 --- /dev/null +++ b/benchmarks/LLVM/3_function_37.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_38.ll b/benchmarks/LLVM/3_function_38.ll new file mode 100644 index 0000000..172a3bb --- /dev/null +++ b/benchmarks/LLVM/3_function_38.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%1, %arg0) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_39.ll b/benchmarks/LLVM/3_function_39.ll new file mode 100644 index 0000000..3917497 --- /dev/null +++ b/benchmarks/LLVM/3_function_39.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_4.ll b/benchmarks/LLVM/3_function_4.ll new file mode 100644 index 0000000..5b51f5c --- /dev/null +++ b/benchmarks/LLVM/3_function_4.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_40.ll b/benchmarks/LLVM/3_function_40.ll new file mode 100644 index 0000000..5f80d56 --- /dev/null +++ b/benchmarks/LLVM/3_function_40.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_41.ll b/benchmarks/LLVM/3_function_41.ll new file mode 100644 index 0000000..2a7e49d --- /dev/null +++ b/benchmarks/LLVM/3_function_41.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_42.ll b/benchmarks/LLVM/3_function_42.ll new file mode 100644 index 0000000..a2cb2ee --- /dev/null +++ b/benchmarks/LLVM/3_function_42.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_43.ll b/benchmarks/LLVM/3_function_43.ll new file mode 100644 index 0000000..ae0ed0e --- /dev/null +++ b/benchmarks/LLVM/3_function_43.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_44.ll b/benchmarks/LLVM/3_function_44.ll new file mode 100644 index 0000000..b085223 --- /dev/null +++ b/benchmarks/LLVM/3_function_44.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.ashr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_45.ll b/benchmarks/LLVM/3_function_45.ll new file mode 100644 index 0000000..48af98a --- /dev/null +++ b/benchmarks/LLVM/3_function_45.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_46.ll b/benchmarks/LLVM/3_function_46.ll new file mode 100644 index 0000000..c524fe2 --- /dev/null +++ b/benchmarks/LLVM/3_function_46.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_47.ll b/benchmarks/LLVM/3_function_47.ll new file mode 100644 index 0000000..63540d0 --- /dev/null +++ b/benchmarks/LLVM/3_function_47.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_48.ll b/benchmarks/LLVM/3_function_48.ll new file mode 100644 index 0000000..42bce5b --- /dev/null +++ b/benchmarks/LLVM/3_function_48.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_49.ll b/benchmarks/LLVM/3_function_49.ll new file mode 100644 index 0000000..75220f2 --- /dev/null +++ b/benchmarks/LLVM/3_function_49.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_5.ll b/benchmarks/LLVM/3_function_5.ll new file mode 100644 index 0000000..5aecbf6 --- /dev/null +++ b/benchmarks/LLVM/3_function_5.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_50.ll b/benchmarks/LLVM/3_function_50.ll new file mode 100644 index 0000000..ae90949 --- /dev/null +++ b/benchmarks/LLVM/3_function_50.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_51.ll b/benchmarks/LLVM/3_function_51.ll new file mode 100644 index 0000000..6884bb2 --- /dev/null +++ b/benchmarks/LLVM/3_function_51.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_52.ll b/benchmarks/LLVM/3_function_52.ll new file mode 100644 index 0000000..42bce5b --- /dev/null +++ b/benchmarks/LLVM/3_function_52.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_53.ll b/benchmarks/LLVM/3_function_53.ll new file mode 100644 index 0000000..2a90b60 --- /dev/null +++ b/benchmarks/LLVM/3_function_53.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_54.ll b/benchmarks/LLVM/3_function_54.ll new file mode 100644 index 0000000..935a9e0 --- /dev/null +++ b/benchmarks/LLVM/3_function_54.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_55.ll b/benchmarks/LLVM/3_function_55.ll new file mode 100644 index 0000000..a20a7e6 --- /dev/null +++ b/benchmarks/LLVM/3_function_55.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_56.ll b/benchmarks/LLVM/3_function_56.ll new file mode 100644 index 0000000..6f650d9 --- /dev/null +++ b/benchmarks/LLVM/3_function_56.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_57.ll b/benchmarks/LLVM/3_function_57.ll new file mode 100644 index 0000000..a0d7d77 --- /dev/null +++ b/benchmarks/LLVM/3_function_57.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_58.ll b/benchmarks/LLVM/3_function_58.ll new file mode 100644 index 0000000..e5e4496 --- /dev/null +++ b/benchmarks/LLVM/3_function_58.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_59.ll b/benchmarks/LLVM/3_function_59.ll new file mode 100644 index 0000000..1130496 --- /dev/null +++ b/benchmarks/LLVM/3_function_59.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_6.ll b/benchmarks/LLVM/3_function_6.ll new file mode 100644 index 0000000..6884bb2 --- /dev/null +++ b/benchmarks/LLVM/3_function_6.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_60.ll b/benchmarks/LLVM/3_function_60.ll new file mode 100644 index 0000000..ae49752 --- /dev/null +++ b/benchmarks/LLVM/3_function_60.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_61.ll b/benchmarks/LLVM/3_function_61.ll new file mode 100644 index 0000000..6fbe043 --- /dev/null +++ b/benchmarks/LLVM/3_function_61.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_62.ll b/benchmarks/LLVM/3_function_62.ll new file mode 100644 index 0000000..4152aa2 --- /dev/null +++ b/benchmarks/LLVM/3_function_62.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %0) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_63.ll b/benchmarks/LLVM/3_function_63.ll new file mode 100644 index 0000000..6f650d9 --- /dev/null +++ b/benchmarks/LLVM/3_function_63.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_64.ll b/benchmarks/LLVM/3_function_64.ll new file mode 100644 index 0000000..9a6ccd1 --- /dev/null +++ b/benchmarks/LLVM/3_function_64.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_65.ll b/benchmarks/LLVM/3_function_65.ll new file mode 100644 index 0000000..80c8c1e --- /dev/null +++ b/benchmarks/LLVM/3_function_65.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_66.ll b/benchmarks/LLVM/3_function_66.ll new file mode 100644 index 0000000..03d1baa --- /dev/null +++ b/benchmarks/LLVM/3_function_66.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_67.ll b/benchmarks/LLVM/3_function_67.ll new file mode 100644 index 0000000..509ec34 --- /dev/null +++ b/benchmarks/LLVM/3_function_67.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_68.ll b/benchmarks/LLVM/3_function_68.ll new file mode 100644 index 0000000..c93fbe6 --- /dev/null +++ b/benchmarks/LLVM/3_function_68.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_69.ll b/benchmarks/LLVM/3_function_69.ll new file mode 100644 index 0000000..114785f --- /dev/null +++ b/benchmarks/LLVM/3_function_69.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_7.ll b/benchmarks/LLVM/3_function_7.ll new file mode 100644 index 0000000..f6911aa --- /dev/null +++ b/benchmarks/LLVM/3_function_7.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_70.ll b/benchmarks/LLVM/3_function_70.ll new file mode 100644 index 0000000..a19ac12 --- /dev/null +++ b/benchmarks/LLVM/3_function_70.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_71.ll b/benchmarks/LLVM/3_function_71.ll new file mode 100644 index 0000000..3fbcb13 --- /dev/null +++ b/benchmarks/LLVM/3_function_71.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_72.ll b/benchmarks/LLVM/3_function_72.ll new file mode 100644 index 0000000..b4cfb62 --- /dev/null +++ b/benchmarks/LLVM/3_function_72.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.xor"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_73.ll b/benchmarks/LLVM/3_function_73.ll new file mode 100644 index 0000000..aa6c100 --- /dev/null +++ b/benchmarks/LLVM/3_function_73.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_74.ll b/benchmarks/LLVM/3_function_74.ll new file mode 100644 index 0000000..50c26f2 --- /dev/null +++ b/benchmarks/LLVM/3_function_74.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_75.ll b/benchmarks/LLVM/3_function_75.ll new file mode 100644 index 0000000..ec714ac --- /dev/null +++ b/benchmarks/LLVM/3_function_75.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_76.ll b/benchmarks/LLVM/3_function_76.ll new file mode 100644 index 0000000..91227fa --- /dev/null +++ b/benchmarks/LLVM/3_function_76.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.or"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_77.ll b/benchmarks/LLVM/3_function_77.ll new file mode 100644 index 0000000..25d5736 --- /dev/null +++ b/benchmarks/LLVM/3_function_77.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_78.ll b/benchmarks/LLVM/3_function_78.ll new file mode 100644 index 0000000..e1ffcd4 --- /dev/null +++ b/benchmarks/LLVM/3_function_78.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_79.ll b/benchmarks/LLVM/3_function_79.ll new file mode 100644 index 0000000..254ffb8 --- /dev/null +++ b/benchmarks/LLVM/3_function_79.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_8.ll b/benchmarks/LLVM/3_function_8.ll new file mode 100644 index 0000000..392c405 --- /dev/null +++ b/benchmarks/LLVM/3_function_8.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_80.ll b/benchmarks/LLVM/3_function_80.ll new file mode 100644 index 0000000..04aa223 --- /dev/null +++ b/benchmarks/LLVM/3_function_80.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.sdiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_81.ll b/benchmarks/LLVM/3_function_81.ll new file mode 100644 index 0000000..9b9f2e3 --- /dev/null +++ b/benchmarks/LLVM/3_function_81.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_82.ll b/benchmarks/LLVM/3_function_82.ll new file mode 100644 index 0000000..fa022df --- /dev/null +++ b/benchmarks/LLVM/3_function_82.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_83.ll b/benchmarks/LLVM/3_function_83.ll new file mode 100644 index 0000000..52ae0f2 --- /dev/null +++ b/benchmarks/LLVM/3_function_83.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_84.ll b/benchmarks/LLVM/3_function_84.ll new file mode 100644 index 0000000..254189f --- /dev/null +++ b/benchmarks/LLVM/3_function_84.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_85.ll b/benchmarks/LLVM/3_function_85.ll new file mode 100644 index 0000000..f06beed --- /dev/null +++ b/benchmarks/LLVM/3_function_85.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_86.ll b/benchmarks/LLVM/3_function_86.ll new file mode 100644 index 0000000..fa14c92 --- /dev/null +++ b/benchmarks/LLVM/3_function_86.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i32, %arg2: i64): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_87.ll b/benchmarks/LLVM/3_function_87.ll new file mode 100644 index 0000000..fe09647 --- /dev/null +++ b/benchmarks/LLVM/3_function_87.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_88.ll b/benchmarks/LLVM/3_function_88.ll new file mode 100644 index 0000000..b38810e --- /dev/null +++ b/benchmarks/LLVM/3_function_88.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.udiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_89.ll b/benchmarks/LLVM/3_function_89.ll new file mode 100644 index 0000000..340c735 --- /dev/null +++ b/benchmarks/LLVM/3_function_89.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_9.ll b/benchmarks/LLVM/3_function_9.ll new file mode 100644 index 0000000..8afadb8 --- /dev/null +++ b/benchmarks/LLVM/3_function_9.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 1 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg0) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_90.ll b/benchmarks/LLVM/3_function_90.ll new file mode 100644 index 0000000..314fb65 --- /dev/null +++ b/benchmarks/LLVM/3_function_90.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_91.ll b/benchmarks/LLVM/3_function_91.ll new file mode 100644 index 0000000..0d6f017 --- /dev/null +++ b/benchmarks/LLVM/3_function_91.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_92.ll b/benchmarks/LLVM/3_function_92.ll new file mode 100644 index 0000000..86a5a1f --- /dev/null +++ b/benchmarks/LLVM/3_function_92.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_93.ll b/benchmarks/LLVM/3_function_93.ll new file mode 100644 index 0000000..94c7fe7 --- /dev/null +++ b/benchmarks/LLVM/3_function_93.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_94.ll b/benchmarks/LLVM/3_function_94.ll new file mode 100644 index 0000000..85f701b --- /dev/null +++ b/benchmarks/LLVM/3_function_94.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_95.ll b/benchmarks/LLVM/3_function_95.ll new file mode 100644 index 0000000..2bfc3de --- /dev/null +++ b/benchmarks/LLVM/3_function_95.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_96.ll b/benchmarks/LLVM/3_function_96.ll new file mode 100644 index 0000000..42533a9 --- /dev/null +++ b/benchmarks/LLVM/3_function_96.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg2) : (i32) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_97.ll b/benchmarks/LLVM/3_function_97.ll new file mode 100644 index 0000000..368c1a3 --- /dev/null +++ b/benchmarks/LLVM/3_function_97.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %arg0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%2) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_98.ll b/benchmarks/LLVM/3_function_98.ll new file mode 100644 index 0000000..6884bb2 --- /dev/null +++ b/benchmarks/LLVM/3_function_98.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%2) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/3_function_99.ll b/benchmarks/LLVM/3_function_99.ll new file mode 100644 index 0000000..c1985f3 --- /dev/null +++ b/benchmarks/LLVM/3_function_99.ll @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.sdiv"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%2) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_0.ll b/benchmarks/LLVM/4_function_0.ll new file mode 100644 index 0000000..0e78bc5 --- /dev/null +++ b/benchmarks/LLVM/4_function_0.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_1.ll b/benchmarks/LLVM/4_function_1.ll new file mode 100644 index 0000000..40869a5 --- /dev/null +++ b/benchmarks/LLVM/4_function_1.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_10.ll b/benchmarks/LLVM/4_function_10.ll new file mode 100644 index 0000000..e88b714 --- /dev/null +++ b/benchmarks/LLVM/4_function_10.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_11.ll b/benchmarks/LLVM/4_function_11.ll new file mode 100644 index 0000000..6208e24 --- /dev/null +++ b/benchmarks/LLVM/4_function_11.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_12.ll b/benchmarks/LLVM/4_function_12.ll new file mode 100644 index 0000000..42c656b --- /dev/null +++ b/benchmarks/LLVM/4_function_12.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_13.ll b/benchmarks/LLVM/4_function_13.ll new file mode 100644 index 0000000..cf39a50 --- /dev/null +++ b/benchmarks/LLVM/4_function_13.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.icmp"(%arg0, %2) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_14.ll b/benchmarks/LLVM/4_function_14.ll new file mode 100644 index 0000000..e8917b8 --- /dev/null +++ b/benchmarks/LLVM/4_function_14.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_15.ll b/benchmarks/LLVM/4_function_15.ll new file mode 100644 index 0000000..57bb26e --- /dev/null +++ b/benchmarks/LLVM/4_function_15.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_16.ll b/benchmarks/LLVM/4_function_16.ll new file mode 100644 index 0000000..92f6dcb --- /dev/null +++ b/benchmarks/LLVM/4_function_16.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_17.ll b/benchmarks/LLVM/4_function_17.ll new file mode 100644 index 0000000..7bb828b --- /dev/null +++ b/benchmarks/LLVM/4_function_17.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg1) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_18.ll b/benchmarks/LLVM/4_function_18.ll new file mode 100644 index 0000000..cec3051 --- /dev/null +++ b/benchmarks/LLVM/4_function_18.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_19.ll b/benchmarks/LLVM/4_function_19.ll new file mode 100644 index 0000000..590a4ab --- /dev/null +++ b/benchmarks/LLVM/4_function_19.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_2.ll b/benchmarks/LLVM/4_function_2.ll new file mode 100644 index 0000000..8a89286 --- /dev/null +++ b/benchmarks/LLVM/4_function_2.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_20.ll b/benchmarks/LLVM/4_function_20.ll new file mode 100644 index 0000000..03edefa --- /dev/null +++ b/benchmarks/LLVM/4_function_20.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64, %arg3: i32): + %0 = "llvm.xor"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg3) : (i32) -> i64 + %2 = "llvm.select"(%arg1, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.ashr"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_21.ll b/benchmarks/LLVM/4_function_21.ll new file mode 100644 index 0000000..3ae7a60 --- /dev/null +++ b/benchmarks/LLVM/4_function_21.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%arg0, %2) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_22.ll b/benchmarks/LLVM/4_function_22.ll new file mode 100644 index 0000000..d4d8791 --- /dev/null +++ b/benchmarks/LLVM/4_function_22.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_23.ll b/benchmarks/LLVM/4_function_23.ll new file mode 100644 index 0000000..6b633f7 --- /dev/null +++ b/benchmarks/LLVM/4_function_23.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.or"(%1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_24.ll b/benchmarks/LLVM/4_function_24.ll new file mode 100644 index 0000000..bbe7d49 --- /dev/null +++ b/benchmarks/LLVM/4_function_24.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_25.ll b/benchmarks/LLVM/4_function_25.ll new file mode 100644 index 0000000..4db321e --- /dev/null +++ b/benchmarks/LLVM/4_function_25.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_26.ll b/benchmarks/LLVM/4_function_26.ll new file mode 100644 index 0000000..29dd234 --- /dev/null +++ b/benchmarks/LLVM/4_function_26.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.xor"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_27.ll b/benchmarks/LLVM/4_function_27.ll new file mode 100644 index 0000000..fe7ee52 --- /dev/null +++ b/benchmarks/LLVM/4_function_27.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_28.ll b/benchmarks/LLVM/4_function_28.ll new file mode 100644 index 0000000..f73174b --- /dev/null +++ b/benchmarks/LLVM/4_function_28.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_29.ll b/benchmarks/LLVM/4_function_29.ll new file mode 100644 index 0000000..6c43887 --- /dev/null +++ b/benchmarks/LLVM/4_function_29.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_3.ll b/benchmarks/LLVM/4_function_3.ll new file mode 100644 index 0000000..93067e0 --- /dev/null +++ b/benchmarks/LLVM/4_function_3.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_30.ll b/benchmarks/LLVM/4_function_30.ll new file mode 100644 index 0000000..576b59b --- /dev/null +++ b/benchmarks/LLVM/4_function_30.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.icmp"(%2, %arg2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_31.ll b/benchmarks/LLVM/4_function_31.ll new file mode 100644 index 0000000..8170909 --- /dev/null +++ b/benchmarks/LLVM/4_function_31.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_32.ll b/benchmarks/LLVM/4_function_32.ll new file mode 100644 index 0000000..403bcdc --- /dev/null +++ b/benchmarks/LLVM/4_function_32.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg1, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_33.ll b/benchmarks/LLVM/4_function_33.ll new file mode 100644 index 0000000..65361f7 --- /dev/null +++ b/benchmarks/LLVM/4_function_33.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg1, %arg2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_34.ll b/benchmarks/LLVM/4_function_34.ll new file mode 100644 index 0000000..3fa612b --- /dev/null +++ b/benchmarks/LLVM/4_function_34.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_35.ll b/benchmarks/LLVM/4_function_35.ll new file mode 100644 index 0000000..dc41c0a --- /dev/null +++ b/benchmarks/LLVM/4_function_35.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_36.ll b/benchmarks/LLVM/4_function_36.ll new file mode 100644 index 0000000..e47bf8f --- /dev/null +++ b/benchmarks/LLVM/4_function_36.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.urem"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_37.ll b/benchmarks/LLVM/4_function_37.ll new file mode 100644 index 0000000..9a0b9a1 --- /dev/null +++ b/benchmarks/LLVM/4_function_37.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_38.ll b/benchmarks/LLVM/4_function_38.ll new file mode 100644 index 0000000..829bee4 --- /dev/null +++ b/benchmarks/LLVM/4_function_38.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%2, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_39.ll b/benchmarks/LLVM/4_function_39.ll new file mode 100644 index 0000000..88ccb37 --- /dev/null +++ b/benchmarks/LLVM/4_function_39.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_4.ll b/benchmarks/LLVM/4_function_4.ll new file mode 100644 index 0000000..42eb88e --- /dev/null +++ b/benchmarks/LLVM/4_function_4.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_40.ll b/benchmarks/LLVM/4_function_40.ll new file mode 100644 index 0000000..48cda89 --- /dev/null +++ b/benchmarks/LLVM/4_function_40.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_41.ll b/benchmarks/LLVM/4_function_41.ll new file mode 100644 index 0000000..30dff32 --- /dev/null +++ b/benchmarks/LLVM/4_function_41.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_42.ll b/benchmarks/LLVM/4_function_42.ll new file mode 100644 index 0000000..6a5b19d --- /dev/null +++ b/benchmarks/LLVM/4_function_42.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i1, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_43.ll b/benchmarks/LLVM/4_function_43.ll new file mode 100644 index 0000000..4b16f44 --- /dev/null +++ b/benchmarks/LLVM/4_function_43.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1): + %0 = "llvm.select"(%arg1, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_44.ll b/benchmarks/LLVM/4_function_44.ll new file mode 100644 index 0000000..62133d8 --- /dev/null +++ b/benchmarks/LLVM/4_function_44.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.sext"(%arg1) : (i32) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_45.ll b/benchmarks/LLVM/4_function_45.ll new file mode 100644 index 0000000..aef3ad3 --- /dev/null +++ b/benchmarks/LLVM/4_function_45.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %arg0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_46.ll b/benchmarks/LLVM/4_function_46.ll new file mode 100644 index 0000000..e42909d --- /dev/null +++ b/benchmarks/LLVM/4_function_46.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_47.ll b/benchmarks/LLVM/4_function_47.ll new file mode 100644 index 0000000..a22ace1 --- /dev/null +++ b/benchmarks/LLVM/4_function_47.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_48.ll b/benchmarks/LLVM/4_function_48.ll new file mode 100644 index 0000000..8fa2787 --- /dev/null +++ b/benchmarks/LLVM/4_function_48.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_49.ll b/benchmarks/LLVM/4_function_49.ll new file mode 100644 index 0000000..1bdb9d4 --- /dev/null +++ b/benchmarks/LLVM/4_function_49.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_5.ll b/benchmarks/LLVM/4_function_5.ll new file mode 100644 index 0000000..3e12912 --- /dev/null +++ b/benchmarks/LLVM/4_function_5.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_50.ll b/benchmarks/LLVM/4_function_50.ll new file mode 100644 index 0000000..4283cb6 --- /dev/null +++ b/benchmarks/LLVM/4_function_50.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %0) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_51.ll b/benchmarks/LLVM/4_function_51.ll new file mode 100644 index 0000000..185247a --- /dev/null +++ b/benchmarks/LLVM/4_function_51.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_52.ll b/benchmarks/LLVM/4_function_52.ll new file mode 100644 index 0000000..4358fcb --- /dev/null +++ b/benchmarks/LLVM/4_function_52.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_53.ll b/benchmarks/LLVM/4_function_53.ll new file mode 100644 index 0000000..062870c --- /dev/null +++ b/benchmarks/LLVM/4_function_53.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_54.ll b/benchmarks/LLVM/4_function_54.ll new file mode 100644 index 0000000..961bdd5 --- /dev/null +++ b/benchmarks/LLVM/4_function_54.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg2) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_55.ll b/benchmarks/LLVM/4_function_55.ll new file mode 100644 index 0000000..8b232aa --- /dev/null +++ b/benchmarks/LLVM/4_function_55.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_56.ll b/benchmarks/LLVM/4_function_56.ll new file mode 100644 index 0000000..f913a00 --- /dev/null +++ b/benchmarks/LLVM/4_function_56.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.srem"(%arg0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_57.ll b/benchmarks/LLVM/4_function_57.ll new file mode 100644 index 0000000..cd43a62 --- /dev/null +++ b/benchmarks/LLVM/4_function_57.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.or"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_58.ll b/benchmarks/LLVM/4_function_58.ll new file mode 100644 index 0000000..a752016 --- /dev/null +++ b/benchmarks/LLVM/4_function_58.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_59.ll b/benchmarks/LLVM/4_function_59.ll new file mode 100644 index 0000000..38a86e7 --- /dev/null +++ b/benchmarks/LLVM/4_function_59.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_6.ll b/benchmarks/LLVM/4_function_6.ll new file mode 100644 index 0000000..89573e3 --- /dev/null +++ b/benchmarks/LLVM/4_function_6.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%2, %2) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_60.ll b/benchmarks/LLVM/4_function_60.ll new file mode 100644 index 0000000..dc41c0a --- /dev/null +++ b/benchmarks/LLVM/4_function_60.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_61.ll b/benchmarks/LLVM/4_function_61.ll new file mode 100644 index 0000000..886f671 --- /dev/null +++ b/benchmarks/LLVM/4_function_61.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_62.ll b/benchmarks/LLVM/4_function_62.ll new file mode 100644 index 0000000..02bd58e --- /dev/null +++ b/benchmarks/LLVM/4_function_62.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg2, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_63.ll b/benchmarks/LLVM/4_function_63.ll new file mode 100644 index 0000000..da658ed --- /dev/null +++ b/benchmarks/LLVM/4_function_63.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.ashr"(%arg2, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_64.ll b/benchmarks/LLVM/4_function_64.ll new file mode 100644 index 0000000..e47b2c1 --- /dev/null +++ b/benchmarks/LLVM/4_function_64.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_65.ll b/benchmarks/LLVM/4_function_65.ll new file mode 100644 index 0000000..2e6a970 --- /dev/null +++ b/benchmarks/LLVM/4_function_65.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_66.ll b/benchmarks/LLVM/4_function_66.ll new file mode 100644 index 0000000..86a3ff0 --- /dev/null +++ b/benchmarks/LLVM/4_function_66.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_67.ll b/benchmarks/LLVM/4_function_67.ll new file mode 100644 index 0000000..e478069 --- /dev/null +++ b/benchmarks/LLVM/4_function_67.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_68.ll b/benchmarks/LLVM/4_function_68.ll new file mode 100644 index 0000000..912c99a --- /dev/null +++ b/benchmarks/LLVM/4_function_68.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_69.ll b/benchmarks/LLVM/4_function_69.ll new file mode 100644 index 0000000..d250c0d --- /dev/null +++ b/benchmarks/LLVM/4_function_69.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.urem"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_7.ll b/benchmarks/LLVM/4_function_7.ll new file mode 100644 index 0000000..d32e5df --- /dev/null +++ b/benchmarks/LLVM/4_function_7.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%arg0, %0) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.udiv"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_70.ll b/benchmarks/LLVM/4_function_70.ll new file mode 100644 index 0000000..97715bf --- /dev/null +++ b/benchmarks/LLVM/4_function_70.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg1) : (i32) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_71.ll b/benchmarks/LLVM/4_function_71.ll new file mode 100644 index 0000000..62238e8 --- /dev/null +++ b/benchmarks/LLVM/4_function_71.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_72.ll b/benchmarks/LLVM/4_function_72.ll new file mode 100644 index 0000000..56531d4 --- /dev/null +++ b/benchmarks/LLVM/4_function_72.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_73.ll b/benchmarks/LLVM/4_function_73.ll new file mode 100644 index 0000000..00f902b --- /dev/null +++ b/benchmarks/LLVM/4_function_73.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_74.ll b/benchmarks/LLVM/4_function_74.ll new file mode 100644 index 0000000..9fa803f --- /dev/null +++ b/benchmarks/LLVM/4_function_74.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_75.ll b/benchmarks/LLVM/4_function_75.ll new file mode 100644 index 0000000..9f27cc0 --- /dev/null +++ b/benchmarks/LLVM/4_function_75.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_76.ll b/benchmarks/LLVM/4_function_76.ll new file mode 100644 index 0000000..ebd4fab --- /dev/null +++ b/benchmarks/LLVM/4_function_76.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_77.ll b/benchmarks/LLVM/4_function_77.ll new file mode 100644 index 0000000..ca0e168 --- /dev/null +++ b/benchmarks/LLVM/4_function_77.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%0, %2) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_78.ll b/benchmarks/LLVM/4_function_78.ll new file mode 100644 index 0000000..58a548c --- /dev/null +++ b/benchmarks/LLVM/4_function_78.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_79.ll b/benchmarks/LLVM/4_function_79.ll new file mode 100644 index 0000000..40869a5 --- /dev/null +++ b/benchmarks/LLVM/4_function_79.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_8.ll b/benchmarks/LLVM/4_function_8.ll new file mode 100644 index 0000000..6b360c9 --- /dev/null +++ b/benchmarks/LLVM/4_function_8.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.xor"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_80.ll b/benchmarks/LLVM/4_function_80.ll new file mode 100644 index 0000000..cddfd97 --- /dev/null +++ b/benchmarks/LLVM/4_function_80.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_81.ll b/benchmarks/LLVM/4_function_81.ll new file mode 100644 index 0000000..719d6eb --- /dev/null +++ b/benchmarks/LLVM/4_function_81.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg2, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %1) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_82.ll b/benchmarks/LLVM/4_function_82.ll new file mode 100644 index 0000000..01bc137 --- /dev/null +++ b/benchmarks/LLVM/4_function_82.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.xor"(%0, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_83.ll b/benchmarks/LLVM/4_function_83.ll new file mode 100644 index 0000000..2672a72 --- /dev/null +++ b/benchmarks/LLVM/4_function_83.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_84.ll b/benchmarks/LLVM/4_function_84.ll new file mode 100644 index 0000000..9105e29 --- /dev/null +++ b/benchmarks/LLVM/4_function_84.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_85.ll b/benchmarks/LLVM/4_function_85.ll new file mode 100644 index 0000000..a4bfa68 --- /dev/null +++ b/benchmarks/LLVM/4_function_85.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg1) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_86.ll b/benchmarks/LLVM/4_function_86.ll new file mode 100644 index 0000000..4ca5540 --- /dev/null +++ b/benchmarks/LLVM/4_function_86.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_87.ll b/benchmarks/LLVM/4_function_87.ll new file mode 100644 index 0000000..6148d76 --- /dev/null +++ b/benchmarks/LLVM/4_function_87.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_88.ll b/benchmarks/LLVM/4_function_88.ll new file mode 100644 index 0000000..eae9202 --- /dev/null +++ b/benchmarks/LLVM/4_function_88.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_89.ll b/benchmarks/LLVM/4_function_89.ll new file mode 100644 index 0000000..6bebddc --- /dev/null +++ b/benchmarks/LLVM/4_function_89.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_9.ll b/benchmarks/LLVM/4_function_9.ll new file mode 100644 index 0000000..d82fca8 --- /dev/null +++ b/benchmarks/LLVM/4_function_9.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg2, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_90.ll b/benchmarks/LLVM/4_function_90.ll new file mode 100644 index 0000000..898da6b --- /dev/null +++ b/benchmarks/LLVM/4_function_90.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_91.ll b/benchmarks/LLVM/4_function_91.ll new file mode 100644 index 0000000..be7136b --- /dev/null +++ b/benchmarks/LLVM/4_function_91.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_92.ll b/benchmarks/LLVM/4_function_92.ll new file mode 100644 index 0000000..4662276 --- /dev/null +++ b/benchmarks/LLVM/4_function_92.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.sdiv"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_93.ll b/benchmarks/LLVM/4_function_93.ll new file mode 100644 index 0000000..ba400e4 --- /dev/null +++ b/benchmarks/LLVM/4_function_93.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_94.ll b/benchmarks/LLVM/4_function_94.ll new file mode 100644 index 0000000..390de75 --- /dev/null +++ b/benchmarks/LLVM/4_function_94.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_95.ll b/benchmarks/LLVM/4_function_95.ll new file mode 100644 index 0000000..f649718 --- /dev/null +++ b/benchmarks/LLVM/4_function_95.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%2, %1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_96.ll b/benchmarks/LLVM/4_function_96.ll new file mode 100644 index 0000000..32cb78d --- /dev/null +++ b/benchmarks/LLVM/4_function_96.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_97.ll b/benchmarks/LLVM/4_function_97.ll new file mode 100644 index 0000000..1efd910 --- /dev/null +++ b/benchmarks/LLVM/4_function_97.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%1, %arg0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%3) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_98.ll b/benchmarks/LLVM/4_function_98.ll new file mode 100644 index 0000000..324cac5 --- /dev/null +++ b/benchmarks/LLVM/4_function_98.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + "llvm.return"(%3) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/4_function_99.ll b/benchmarks/LLVM/4_function_99.ll new file mode 100644 index 0000000..783e5f0 --- /dev/null +++ b/benchmarks/LLVM/4_function_99.ll @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.or"(%1, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%3) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_0.ll b/benchmarks/LLVM/5_function_0.ll new file mode 100644 index 0000000..7b7cb84 --- /dev/null +++ b/benchmarks/LLVM/5_function_0.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_1.ll b/benchmarks/LLVM/5_function_1.ll new file mode 100644 index 0000000..1bf4df9 --- /dev/null +++ b/benchmarks/LLVM/5_function_1.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.ashr"(%0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg0) : (i32) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_10.ll b/benchmarks/LLVM/5_function_10.ll new file mode 100644 index 0000000..7ac9033 --- /dev/null +++ b/benchmarks/LLVM/5_function_10.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.urem"(%1, %3) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_11.ll b/benchmarks/LLVM/5_function_11.ll new file mode 100644 index 0000000..06f3b97 --- /dev/null +++ b/benchmarks/LLVM/5_function_11.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_12.ll b/benchmarks/LLVM/5_function_12.ll new file mode 100644 index 0000000..7dc04fa --- /dev/null +++ b/benchmarks/LLVM/5_function_12.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg2) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%1, %3) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_13.ll b/benchmarks/LLVM/5_function_13.ll new file mode 100644 index 0000000..bc92f71 --- /dev/null +++ b/benchmarks/LLVM/5_function_13.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.lshr"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%0, %3) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_14.ll b/benchmarks/LLVM/5_function_14.ll new file mode 100644 index 0000000..b533e3a --- /dev/null +++ b/benchmarks/LLVM/5_function_14.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 9 : i64}> : (i64, i64) -> i1 + %1 = "llvm.urem"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_15.ll b/benchmarks/LLVM/5_function_15.ll new file mode 100644 index 0000000..858f4eb --- /dev/null +++ b/benchmarks/LLVM/5_function_15.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg0) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.sdiv"(%2, %arg2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_16.ll b/benchmarks/LLVM/5_function_16.ll new file mode 100644 index 0000000..dac93f4 --- /dev/null +++ b/benchmarks/LLVM/5_function_16.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_17.ll b/benchmarks/LLVM/5_function_17.ll new file mode 100644 index 0000000..8b679b9 --- /dev/null +++ b/benchmarks/LLVM/5_function_17.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg1) : (i32) -> i64 + %3 = "llvm.ashr"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_18.ll b/benchmarks/LLVM/5_function_18.ll new file mode 100644 index 0000000..85ebb20 --- /dev/null +++ b/benchmarks/LLVM/5_function_18.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_19.ll b/benchmarks/LLVM/5_function_19.ll new file mode 100644 index 0000000..51afc16 --- /dev/null +++ b/benchmarks/LLVM/5_function_19.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg2) : (i32) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_2.ll b/benchmarks/LLVM/5_function_2.ll new file mode 100644 index 0000000..586b32d --- /dev/null +++ b/benchmarks/LLVM/5_function_2.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%2, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.urem"(%arg0, %3) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_20.ll b/benchmarks/LLVM/5_function_20.ll new file mode 100644 index 0000000..96ca81c --- /dev/null +++ b/benchmarks/LLVM/5_function_20.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg2, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_21.ll b/benchmarks/LLVM/5_function_21.ll new file mode 100644 index 0000000..428e08b --- /dev/null +++ b/benchmarks/LLVM/5_function_21.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_22.ll b/benchmarks/LLVM/5_function_22.ll new file mode 100644 index 0000000..7e11956 --- /dev/null +++ b/benchmarks/LLVM/5_function_22.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_23.ll b/benchmarks/LLVM/5_function_23.ll new file mode 100644 index 0000000..7665d81 --- /dev/null +++ b/benchmarks/LLVM/5_function_23.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_24.ll b/benchmarks/LLVM/5_function_24.ll new file mode 100644 index 0000000..2ac4514 --- /dev/null +++ b/benchmarks/LLVM/5_function_24.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_25.ll b/benchmarks/LLVM/5_function_25.ll new file mode 100644 index 0000000..15bb26a --- /dev/null +++ b/benchmarks/LLVM/5_function_25.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.or"(%0, %3) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_26.ll b/benchmarks/LLVM/5_function_26.ll new file mode 100644 index 0000000..978a50c --- /dev/null +++ b/benchmarks/LLVM/5_function_26.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_27.ll b/benchmarks/LLVM/5_function_27.ll new file mode 100644 index 0000000..de0ebe3 --- /dev/null +++ b/benchmarks/LLVM/5_function_27.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%arg0, %0) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_28.ll b/benchmarks/LLVM/5_function_28.ll new file mode 100644 index 0000000..c5f2e00 --- /dev/null +++ b/benchmarks/LLVM/5_function_28.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_29.ll b/benchmarks/LLVM/5_function_29.ll new file mode 100644 index 0000000..25fb802 --- /dev/null +++ b/benchmarks/LLVM/5_function_29.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.srem"(%1, %3) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_3.ll b/benchmarks/LLVM/5_function_3.ll new file mode 100644 index 0000000..83152d2 --- /dev/null +++ b/benchmarks/LLVM/5_function_3.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_30.ll b/benchmarks/LLVM/5_function_30.ll new file mode 100644 index 0000000..260bcfe --- /dev/null +++ b/benchmarks/LLVM/5_function_30.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_31.ll b/benchmarks/LLVM/5_function_31.ll new file mode 100644 index 0000000..98163e3 --- /dev/null +++ b/benchmarks/LLVM/5_function_31.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.lshr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.icmp"(%arg0, %0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %2 = "llvm.zext"(%arg3) : (i32) -> i64 + %3 = "llvm.select"(%1, %arg0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.xor"(%3, %arg1) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_32.ll b/benchmarks/LLVM/5_function_32.ll new file mode 100644 index 0000000..656c1ef --- /dev/null +++ b/benchmarks/LLVM/5_function_32.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_33.ll b/benchmarks/LLVM/5_function_33.ll new file mode 100644 index 0000000..3773d3f --- /dev/null +++ b/benchmarks/LLVM/5_function_33.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.udiv"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %arg0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_34.ll b/benchmarks/LLVM/5_function_34.ll new file mode 100644 index 0000000..39a34c2 --- /dev/null +++ b/benchmarks/LLVM/5_function_34.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.xor"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %0) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_35.ll b/benchmarks/LLVM/5_function_35.ll new file mode 100644 index 0000000..3039f92 --- /dev/null +++ b/benchmarks/LLVM/5_function_35.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_36.ll b/benchmarks/LLVM/5_function_36.ll new file mode 100644 index 0000000..ec5be05 --- /dev/null +++ b/benchmarks/LLVM/5_function_36.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_37.ll b/benchmarks/LLVM/5_function_37.ll new file mode 100644 index 0000000..44a0afa --- /dev/null +++ b/benchmarks/LLVM/5_function_37.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.or"(%arg1, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.select"(%0, %arg0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_38.ll b/benchmarks/LLVM/5_function_38.ll new file mode 100644 index 0000000..97f536f --- /dev/null +++ b/benchmarks/LLVM/5_function_38.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_39.ll b/benchmarks/LLVM/5_function_39.ll new file mode 100644 index 0000000..9db1821 --- /dev/null +++ b/benchmarks/LLVM/5_function_39.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.xor"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_4.ll b/benchmarks/LLVM/5_function_4.ll new file mode 100644 index 0000000..2e73547 --- /dev/null +++ b/benchmarks/LLVM/5_function_4.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_40.ll b/benchmarks/LLVM/5_function_40.ll new file mode 100644 index 0000000..f8cb339 --- /dev/null +++ b/benchmarks/LLVM/5_function_40.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.ashr"(%2, %3) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_41.ll b/benchmarks/LLVM/5_function_41.ll new file mode 100644 index 0000000..61e7195 --- /dev/null +++ b/benchmarks/LLVM/5_function_41.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.or"(%2, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_42.ll b/benchmarks/LLVM/5_function_42.ll new file mode 100644 index 0000000..a6af324 --- /dev/null +++ b/benchmarks/LLVM/5_function_42.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_43.ll b/benchmarks/LLVM/5_function_43.ll new file mode 100644 index 0000000..3192730 --- /dev/null +++ b/benchmarks/LLVM/5_function_43.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_44.ll b/benchmarks/LLVM/5_function_44.ll new file mode 100644 index 0000000..56a0c56 --- /dev/null +++ b/benchmarks/LLVM/5_function_44.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_45.ll b/benchmarks/LLVM/5_function_45.ll new file mode 100644 index 0000000..1a5d432 --- /dev/null +++ b/benchmarks/LLVM/5_function_45.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.sdiv"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_46.ll b/benchmarks/LLVM/5_function_46.ll new file mode 100644 index 0000000..3b8ba6d --- /dev/null +++ b/benchmarks/LLVM/5_function_46.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_47.ll b/benchmarks/LLVM/5_function_47.ll new file mode 100644 index 0000000..b1798a1 --- /dev/null +++ b/benchmarks/LLVM/5_function_47.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%1, %3) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_48.ll b/benchmarks/LLVM/5_function_48.ll new file mode 100644 index 0000000..f807068 --- /dev/null +++ b/benchmarks/LLVM/5_function_48.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_49.ll b/benchmarks/LLVM/5_function_49.ll new file mode 100644 index 0000000..b6133c2 --- /dev/null +++ b/benchmarks/LLVM/5_function_49.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_5.ll b/benchmarks/LLVM/5_function_5.ll new file mode 100644 index 0000000..594ca9d --- /dev/null +++ b/benchmarks/LLVM/5_function_5.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_50.ll b/benchmarks/LLVM/5_function_50.ll new file mode 100644 index 0000000..0bad5d0 --- /dev/null +++ b/benchmarks/LLVM/5_function_50.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_51.ll b/benchmarks/LLVM/5_function_51.ll new file mode 100644 index 0000000..9e9b1fd --- /dev/null +++ b/benchmarks/LLVM/5_function_51.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_52.ll b/benchmarks/LLVM/5_function_52.ll new file mode 100644 index 0000000..6583e79 --- /dev/null +++ b/benchmarks/LLVM/5_function_52.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_53.ll b/benchmarks/LLVM/5_function_53.ll new file mode 100644 index 0000000..f5a4bf7 --- /dev/null +++ b/benchmarks/LLVM/5_function_53.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %0) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_54.ll b/benchmarks/LLVM/5_function_54.ll new file mode 100644 index 0000000..62c5132 --- /dev/null +++ b/benchmarks/LLVM/5_function_54.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_55.ll b/benchmarks/LLVM/5_function_55.ll new file mode 100644 index 0000000..9941ae3 --- /dev/null +++ b/benchmarks/LLVM/5_function_55.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.select"(%0, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%3, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_56.ll b/benchmarks/LLVM/5_function_56.ll new file mode 100644 index 0000000..91b2f93 --- /dev/null +++ b/benchmarks/LLVM/5_function_56.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_57.ll b/benchmarks/LLVM/5_function_57.ll new file mode 100644 index 0000000..8993c46 --- /dev/null +++ b/benchmarks/LLVM/5_function_57.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.select"(%3, %arg2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_58.ll b/benchmarks/LLVM/5_function_58.ll new file mode 100644 index 0000000..bdb9bfa --- /dev/null +++ b/benchmarks/LLVM/5_function_58.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.or"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_59.ll b/benchmarks/LLVM/5_function_59.ll new file mode 100644 index 0000000..efc39f2 --- /dev/null +++ b/benchmarks/LLVM/5_function_59.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_6.ll b/benchmarks/LLVM/5_function_6.ll new file mode 100644 index 0000000..3da96cb --- /dev/null +++ b/benchmarks/LLVM/5_function_6.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.icmp"(%arg0, %3) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_60.ll b/benchmarks/LLVM/5_function_60.ll new file mode 100644 index 0000000..7310c82 --- /dev/null +++ b/benchmarks/LLVM/5_function_60.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg1, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_61.ll b/benchmarks/LLVM/5_function_61.ll new file mode 100644 index 0000000..27646b2 --- /dev/null +++ b/benchmarks/LLVM/5_function_61.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.sdiv"(%1, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_62.ll b/benchmarks/LLVM/5_function_62.ll new file mode 100644 index 0000000..01e6650 --- /dev/null +++ b/benchmarks/LLVM/5_function_62.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_63.ll b/benchmarks/LLVM/5_function_63.ll new file mode 100644 index 0000000..cc52881 --- /dev/null +++ b/benchmarks/LLVM/5_function_63.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_64.ll b/benchmarks/LLVM/5_function_64.ll new file mode 100644 index 0000000..fbbc439 --- /dev/null +++ b/benchmarks/LLVM/5_function_64.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_65.ll b/benchmarks/LLVM/5_function_65.ll new file mode 100644 index 0000000..2df5490 --- /dev/null +++ b/benchmarks/LLVM/5_function_65.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_66.ll b/benchmarks/LLVM/5_function_66.ll new file mode 100644 index 0000000..ee3a52a --- /dev/null +++ b/benchmarks/LLVM/5_function_66.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.urem"(%arg0, %3) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_67.ll b/benchmarks/LLVM/5_function_67.ll new file mode 100644 index 0000000..9dbbe1a --- /dev/null +++ b/benchmarks/LLVM/5_function_67.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_68.ll b/benchmarks/LLVM/5_function_68.ll new file mode 100644 index 0000000..2dd68af --- /dev/null +++ b/benchmarks/LLVM/5_function_68.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_69.ll b/benchmarks/LLVM/5_function_69.ll new file mode 100644 index 0000000..19369ff --- /dev/null +++ b/benchmarks/LLVM/5_function_69.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%arg0, %3) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_7.ll b/benchmarks/LLVM/5_function_7.ll new file mode 100644 index 0000000..cd16cb1 --- /dev/null +++ b/benchmarks/LLVM/5_function_7.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_70.ll b/benchmarks/LLVM/5_function_70.ll new file mode 100644 index 0000000..e9fbc8a --- /dev/null +++ b/benchmarks/LLVM/5_function_70.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_71.ll b/benchmarks/LLVM/5_function_71.ll new file mode 100644 index 0000000..cb2fa5b --- /dev/null +++ b/benchmarks/LLVM/5_function_71.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_72.ll b/benchmarks/LLVM/5_function_72.ll new file mode 100644 index 0000000..5f5180c --- /dev/null +++ b/benchmarks/LLVM/5_function_72.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_73.ll b/benchmarks/LLVM/5_function_73.ll new file mode 100644 index 0000000..a331941 --- /dev/null +++ b/benchmarks/LLVM/5_function_73.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_74.ll b/benchmarks/LLVM/5_function_74.ll new file mode 100644 index 0000000..d35fd61 --- /dev/null +++ b/benchmarks/LLVM/5_function_74.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg1, %arg0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_75.ll b/benchmarks/LLVM/5_function_75.ll new file mode 100644 index 0000000..8cd16fd --- /dev/null +++ b/benchmarks/LLVM/5_function_75.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg1, %1) : (i64, i64) -> i64 + %4 = "llvm.srem"(%2, %3) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_76.ll b/benchmarks/LLVM/5_function_76.ll new file mode 100644 index 0000000..10b2551 --- /dev/null +++ b/benchmarks/LLVM/5_function_76.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_77.ll b/benchmarks/LLVM/5_function_77.ll new file mode 100644 index 0000000..fb34657 --- /dev/null +++ b/benchmarks/LLVM/5_function_77.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_78.ll b/benchmarks/LLVM/5_function_78.ll new file mode 100644 index 0000000..fe2bbf7 --- /dev/null +++ b/benchmarks/LLVM/5_function_78.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg2) : (i32) -> i64 + %3 = "llvm.srem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_79.ll b/benchmarks/LLVM/5_function_79.ll new file mode 100644 index 0000000..8e9ed9d --- /dev/null +++ b/benchmarks/LLVM/5_function_79.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.icmp"(%1, %3) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_8.ll b/benchmarks/LLVM/5_function_8.ll new file mode 100644 index 0000000..f040d0f --- /dev/null +++ b/benchmarks/LLVM/5_function_8.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_80.ll b/benchmarks/LLVM/5_function_80.ll new file mode 100644 index 0000000..956f8cb --- /dev/null +++ b/benchmarks/LLVM/5_function_80.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_81.ll b/benchmarks/LLVM/5_function_81.ll new file mode 100644 index 0000000..9db2d3b --- /dev/null +++ b/benchmarks/LLVM/5_function_81.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%3, %0) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_82.ll b/benchmarks/LLVM/5_function_82.ll new file mode 100644 index 0000000..25e7059 --- /dev/null +++ b/benchmarks/LLVM/5_function_82.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.or"(%1, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_83.ll b/benchmarks/LLVM/5_function_83.ll new file mode 100644 index 0000000..dd8240c --- /dev/null +++ b/benchmarks/LLVM/5_function_83.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg2) : (i32) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_84.ll b/benchmarks/LLVM/5_function_84.ll new file mode 100644 index 0000000..39e7afd --- /dev/null +++ b/benchmarks/LLVM/5_function_84.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_85.ll b/benchmarks/LLVM/5_function_85.ll new file mode 100644 index 0000000..a7bca81 --- /dev/null +++ b/benchmarks/LLVM/5_function_85.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.zext"(%0) : (i32) -> i64 + %3 = "llvm.lshr"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%1, %3) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_86.ll b/benchmarks/LLVM/5_function_86.ll new file mode 100644 index 0000000..7a237bf --- /dev/null +++ b/benchmarks/LLVM/5_function_86.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.or"(%0, %3) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_87.ll b/benchmarks/LLVM/5_function_87.ll new file mode 100644 index 0000000..711ed10 --- /dev/null +++ b/benchmarks/LLVM/5_function_87.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.sdiv"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_88.ll b/benchmarks/LLVM/5_function_88.ll new file mode 100644 index 0000000..761acf6 --- /dev/null +++ b/benchmarks/LLVM/5_function_88.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_89.ll b/benchmarks/LLVM/5_function_89.ll new file mode 100644 index 0000000..3f9c701 --- /dev/null +++ b/benchmarks/LLVM/5_function_89.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_9.ll b/benchmarks/LLVM/5_function_9.ll new file mode 100644 index 0000000..bdfa4fd --- /dev/null +++ b/benchmarks/LLVM/5_function_9.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_90.ll b/benchmarks/LLVM/5_function_90.ll new file mode 100644 index 0000000..c7d306f --- /dev/null +++ b/benchmarks/LLVM/5_function_90.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_91.ll b/benchmarks/LLVM/5_function_91.ll new file mode 100644 index 0000000..f4e4c5b --- /dev/null +++ b/benchmarks/LLVM/5_function_91.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_92.ll b/benchmarks/LLVM/5_function_92.ll new file mode 100644 index 0000000..1c39df0 --- /dev/null +++ b/benchmarks/LLVM/5_function_92.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_93.ll b/benchmarks/LLVM/5_function_93.ll new file mode 100644 index 0000000..c3bcca9 --- /dev/null +++ b/benchmarks/LLVM/5_function_93.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.udiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%arg0, %3) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_94.ll b/benchmarks/LLVM/5_function_94.ll new file mode 100644 index 0000000..6fd2112 --- /dev/null +++ b/benchmarks/LLVM/5_function_94.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.lshr"(%arg2, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%2, %3) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_95.ll b/benchmarks/LLVM/5_function_95.ll new file mode 100644 index 0000000..4506d7d --- /dev/null +++ b/benchmarks/LLVM/5_function_95.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_96.ll b/benchmarks/LLVM/5_function_96.ll new file mode 100644 index 0000000..244d8c3 --- /dev/null +++ b/benchmarks/LLVM/5_function_96.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_97.ll b/benchmarks/LLVM/5_function_97.ll new file mode 100644 index 0000000..eb41195 --- /dev/null +++ b/benchmarks/LLVM/5_function_97.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.sext"(%0) : (i32) -> i64 + %3 = "llvm.or"(%1, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %arg1) : (i64, i64) -> i64 + "llvm.return"(%4) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_98.ll b/benchmarks/LLVM/5_function_98.ll new file mode 100644 index 0000000..3598002 --- /dev/null +++ b/benchmarks/LLVM/5_function_98.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%4) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/5_function_99.ll b/benchmarks/LLVM/5_function_99.ll new file mode 100644 index 0000000..4ed0eb2 --- /dev/null +++ b/benchmarks/LLVM/5_function_99.ll @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%4) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_0.ll b/benchmarks/LLVM/6_function_0.ll new file mode 100644 index 0000000..4a1be71 --- /dev/null +++ b/benchmarks/LLVM/6_function_0.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.urem"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.or"(%4, %1) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_1.ll b/benchmarks/LLVM/6_function_1.ll new file mode 100644 index 0000000..886a1f1 --- /dev/null +++ b/benchmarks/LLVM/6_function_1.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.lshr"(%arg2, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_10.ll b/benchmarks/LLVM/6_function_10.ll new file mode 100644 index 0000000..d163c54 --- /dev/null +++ b/benchmarks/LLVM/6_function_10.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_11.ll b/benchmarks/LLVM/6_function_11.ll new file mode 100644 index 0000000..6474fb5 --- /dev/null +++ b/benchmarks/LLVM/6_function_11.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg2, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_12.ll b/benchmarks/LLVM/6_function_12.ll new file mode 100644 index 0000000..aac0e06 --- /dev/null +++ b/benchmarks/LLVM/6_function_12.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_13.ll b/benchmarks/LLVM/6_function_13.ll new file mode 100644 index 0000000..d573ee0 --- /dev/null +++ b/benchmarks/LLVM/6_function_13.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_14.ll b/benchmarks/LLVM/6_function_14.ll new file mode 100644 index 0000000..54bd287 --- /dev/null +++ b/benchmarks/LLVM/6_function_14.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i1): + %0 = "llvm.srem"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.srem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_15.ll b/benchmarks/LLVM/6_function_15.ll new file mode 100644 index 0000000..c0e6a1e --- /dev/null +++ b/benchmarks/LLVM/6_function_15.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg2, %1) : (i64, i64) -> i64 + %4 = "llvm.urem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_16.ll b/benchmarks/LLVM/6_function_16.ll new file mode 100644 index 0000000..8d6c5a0 --- /dev/null +++ b/benchmarks/LLVM/6_function_16.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sext"(%arg2) : (i32) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%2, %4) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_17.ll b/benchmarks/LLVM/6_function_17.ll new file mode 100644 index 0000000..bbdc6eb --- /dev/null +++ b/benchmarks/LLVM/6_function_17.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %5 = "llvm.xor"(%3, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_18.ll b/benchmarks/LLVM/6_function_18.ll new file mode 100644 index 0000000..29b2702 --- /dev/null +++ b/benchmarks/LLVM/6_function_18.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg2, %2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%0, %4) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_19.ll b/benchmarks/LLVM/6_function_19.ll new file mode 100644 index 0000000..5f5bbdd --- /dev/null +++ b/benchmarks/LLVM/6_function_19.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.sdiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%4, %1) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_2.ll b/benchmarks/LLVM/6_function_2.ll new file mode 100644 index 0000000..b4164f0 --- /dev/null +++ b/benchmarks/LLVM/6_function_2.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.srem"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_20.ll b/benchmarks/LLVM/6_function_20.ll new file mode 100644 index 0000000..a164b66b --- /dev/null +++ b/benchmarks/LLVM/6_function_20.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_21.ll b/benchmarks/LLVM/6_function_21.ll new file mode 100644 index 0000000..a0256ca --- /dev/null +++ b/benchmarks/LLVM/6_function_21.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg1, %2) : (i64, i64) -> i64 + %5 = "llvm.or"(%3, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_22.ll b/benchmarks/LLVM/6_function_22.ll new file mode 100644 index 0000000..b21a944 --- /dev/null +++ b/benchmarks/LLVM/6_function_22.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_23.ll b/benchmarks/LLVM/6_function_23.ll new file mode 100644 index 0000000..8f4cb53 --- /dev/null +++ b/benchmarks/LLVM/6_function_23.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.or"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %3) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%0, %4) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_24.ll b/benchmarks/LLVM/6_function_24.ll new file mode 100644 index 0000000..588ffb8 --- /dev/null +++ b/benchmarks/LLVM/6_function_24.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.udiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_25.ll b/benchmarks/LLVM/6_function_25.ll new file mode 100644 index 0000000..cf65ec5 --- /dev/null +++ b/benchmarks/LLVM/6_function_25.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.ashr"(%2, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_26.ll b/benchmarks/LLVM/6_function_26.ll new file mode 100644 index 0000000..3b922e1 --- /dev/null +++ b/benchmarks/LLVM/6_function_26.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.srem"(%arg0, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_27.ll b/benchmarks/LLVM/6_function_27.ll new file mode 100644 index 0000000..00802c7 --- /dev/null +++ b/benchmarks/LLVM/6_function_27.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%arg2, %arg1) : (i64, i64) -> i64 + %3 = "llvm.or"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_28.ll b/benchmarks/LLVM/6_function_28.ll new file mode 100644 index 0000000..9219aed --- /dev/null +++ b/benchmarks/LLVM/6_function_28.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.ashr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_29.ll b/benchmarks/LLVM/6_function_29.ll new file mode 100644 index 0000000..d4a3a46 --- /dev/null +++ b/benchmarks/LLVM/6_function_29.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.or"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_3.ll b/benchmarks/LLVM/6_function_3.ll new file mode 100644 index 0000000..7c99a72 --- /dev/null +++ b/benchmarks/LLVM/6_function_3.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_30.ll b/benchmarks/LLVM/6_function_30.ll new file mode 100644 index 0000000..194e985 --- /dev/null +++ b/benchmarks/LLVM/6_function_30.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_31.ll b/benchmarks/LLVM/6_function_31.ll new file mode 100644 index 0000000..dde7ea0 --- /dev/null +++ b/benchmarks/LLVM/6_function_31.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.zext"(%0) : (i32) -> i64 + %3 = "llvm.sdiv"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.ashr"(%3, %2) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.icmp"(%arg0, %4) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_32.ll b/benchmarks/LLVM/6_function_32.ll new file mode 100644 index 0000000..39521b6 --- /dev/null +++ b/benchmarks/LLVM/6_function_32.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i32): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.sext"(%arg2) : (i32) -> i64 + %3 = "llvm.udiv"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_33.ll b/benchmarks/LLVM/6_function_33.ll new file mode 100644 index 0000000..671697b --- /dev/null +++ b/benchmarks/LLVM/6_function_33.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.ashr"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_34.ll b/benchmarks/LLVM/6_function_34.ll new file mode 100644 index 0000000..6e65d00 --- /dev/null +++ b/benchmarks/LLVM/6_function_34.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.select"(%arg2, %0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.srem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_35.ll b/benchmarks/LLVM/6_function_35.ll new file mode 100644 index 0000000..58d3ca9 --- /dev/null +++ b/benchmarks/LLVM/6_function_35.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.srem"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg1) : (i32) -> i64 + %4 = "llvm.lshr"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%arg0, %4) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_36.ll b/benchmarks/LLVM/6_function_36.ll new file mode 100644 index 0000000..a4ac9dc --- /dev/null +++ b/benchmarks/LLVM/6_function_36.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.xor"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_37.ll b/benchmarks/LLVM/6_function_37.ll new file mode 100644 index 0000000..d22a073 --- /dev/null +++ b/benchmarks/LLVM/6_function_37.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_38.ll b/benchmarks/LLVM/6_function_38.ll new file mode 100644 index 0000000..caa3272 --- /dev/null +++ b/benchmarks/LLVM/6_function_38.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg2) : (i32) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_39.ll b/benchmarks/LLVM/6_function_39.ll new file mode 100644 index 0000000..01ed8c6 --- /dev/null +++ b/benchmarks/LLVM/6_function_39.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_4.ll b/benchmarks/LLVM/6_function_4.ll new file mode 100644 index 0000000..0cf02e8 --- /dev/null +++ b/benchmarks/LLVM/6_function_4.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.ashr"(%2, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_40.ll b/benchmarks/LLVM/6_function_40.ll new file mode 100644 index 0000000..d6882e2 --- /dev/null +++ b/benchmarks/LLVM/6_function_40.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_41.ll b/benchmarks/LLVM/6_function_41.ll new file mode 100644 index 0000000..73fa648 --- /dev/null +++ b/benchmarks/LLVM/6_function_41.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.srem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_42.ll b/benchmarks/LLVM/6_function_42.ll new file mode 100644 index 0000000..bcd8064 --- /dev/null +++ b/benchmarks/LLVM/6_function_42.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.lshr"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_43.ll b/benchmarks/LLVM/6_function_43.ll new file mode 100644 index 0000000..7fc085c --- /dev/null +++ b/benchmarks/LLVM/6_function_43.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %4 = "llvm.select"(%3, %2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_44.ll b/benchmarks/LLVM/6_function_44.ll new file mode 100644 index 0000000..bea3666 --- /dev/null +++ b/benchmarks/LLVM/6_function_44.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.lshr"(%arg0, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_45.ll b/benchmarks/LLVM/6_function_45.ll new file mode 100644 index 0000000..bc53a5e --- /dev/null +++ b/benchmarks/LLVM/6_function_45.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.select"(%arg1, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.icmp"(%1, %4) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_46.ll b/benchmarks/LLVM/6_function_46.ll new file mode 100644 index 0000000..b295711 --- /dev/null +++ b/benchmarks/LLVM/6_function_46.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 3 : i64}> : (i64, i64) -> i1 + %1 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%1, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%0, %2, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_47.ll b/benchmarks/LLVM/6_function_47.ll new file mode 100644 index 0000000..d23de44 --- /dev/null +++ b/benchmarks/LLVM/6_function_47.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_48.ll b/benchmarks/LLVM/6_function_48.ll new file mode 100644 index 0000000..c1487bf --- /dev/null +++ b/benchmarks/LLVM/6_function_48.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i1, %arg2: i64): + %0 = "llvm.srem"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.srem"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %5 = "llvm.select"(%4, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_49.ll b/benchmarks/LLVM/6_function_49.ll new file mode 100644 index 0000000..3bb1720 --- /dev/null +++ b/benchmarks/LLVM/6_function_49.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.urem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.or"(%2, %4) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_5.ll b/benchmarks/LLVM/6_function_5.ll new file mode 100644 index 0000000..b033eae --- /dev/null +++ b/benchmarks/LLVM/6_function_5.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.icmp"(%0, %4) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_50.ll b/benchmarks/LLVM/6_function_50.ll new file mode 100644 index 0000000..7b3a159 --- /dev/null +++ b/benchmarks/LLVM/6_function_50.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%arg2, %1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.urem"(%3, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_51.ll b/benchmarks/LLVM/6_function_51.ll new file mode 100644 index 0000000..7239ff9 --- /dev/null +++ b/benchmarks/LLVM/6_function_51.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.and"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%0, %4) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_52.ll b/benchmarks/LLVM/6_function_52.ll new file mode 100644 index 0000000..05bca91 --- /dev/null +++ b/benchmarks/LLVM/6_function_52.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_53.ll b/benchmarks/LLVM/6_function_53.ll new file mode 100644 index 0000000..d67a021 --- /dev/null +++ b/benchmarks/LLVM/6_function_53.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.xor"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %0) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%3, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_54.ll b/benchmarks/LLVM/6_function_54.ll new file mode 100644 index 0000000..fdbd950 --- /dev/null +++ b/benchmarks/LLVM/6_function_54.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.urem"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%3, %4) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_55.ll b/benchmarks/LLVM/6_function_55.ll new file mode 100644 index 0000000..d2e95f8 --- /dev/null +++ b/benchmarks/LLVM/6_function_55.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_56.ll b/benchmarks/LLVM/6_function_56.ll new file mode 100644 index 0000000..01bd153 --- /dev/null +++ b/benchmarks/LLVM/6_function_56.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.and"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg0, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_57.ll b/benchmarks/LLVM/6_function_57.ll new file mode 100644 index 0000000..60efa1f --- /dev/null +++ b/benchmarks/LLVM/6_function_57.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_58.ll b/benchmarks/LLVM/6_function_58.ll new file mode 100644 index 0000000..0d89237 --- /dev/null +++ b/benchmarks/LLVM/6_function_58.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%0, %arg0, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_59.ll b/benchmarks/LLVM/6_function_59.ll new file mode 100644 index 0000000..be527bc --- /dev/null +++ b/benchmarks/LLVM/6_function_59.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_6.ll b/benchmarks/LLVM/6_function_6.ll new file mode 100644 index 0000000..2ba5777 --- /dev/null +++ b/benchmarks/LLVM/6_function_6.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_60.ll b/benchmarks/LLVM/6_function_60.ll new file mode 100644 index 0000000..3ba1a41 --- /dev/null +++ b/benchmarks/LLVM/6_function_60.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_61.ll b/benchmarks/LLVM/6_function_61.ll new file mode 100644 index 0000000..a97d2fb --- /dev/null +++ b/benchmarks/LLVM/6_function_61.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.and"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%1, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_62.ll b/benchmarks/LLVM/6_function_62.ll new file mode 100644 index 0000000..5918696 --- /dev/null +++ b/benchmarks/LLVM/6_function_62.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.select"(%3, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_63.ll b/benchmarks/LLVM/6_function_63.ll new file mode 100644 index 0000000..fc7c4a2 --- /dev/null +++ b/benchmarks/LLVM/6_function_63.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_64.ll b/benchmarks/LLVM/6_function_64.ll new file mode 100644 index 0000000..03ad79f --- /dev/null +++ b/benchmarks/LLVM/6_function_64.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%arg2, %arg2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.srem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%0, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_65.ll b/benchmarks/LLVM/6_function_65.ll new file mode 100644 index 0000000..7a2efd3 --- /dev/null +++ b/benchmarks/LLVM/6_function_65.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.sext"(%1) : (i32) -> i64 + %4 = "llvm.sdiv"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_66.ll b/benchmarks/LLVM/6_function_66.ll new file mode 100644 index 0000000..cdb534a --- /dev/null +++ b/benchmarks/LLVM/6_function_66.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.sdiv"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_67.ll b/benchmarks/LLVM/6_function_67.ll new file mode 100644 index 0000000..07a98e4 --- /dev/null +++ b/benchmarks/LLVM/6_function_67.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%arg0, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_68.ll b/benchmarks/LLVM/6_function_68.ll new file mode 100644 index 0000000..d6e1e5c --- /dev/null +++ b/benchmarks/LLVM/6_function_68.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.udiv"(%1, %arg1) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_69.ll b/benchmarks/LLVM/6_function_69.ll new file mode 100644 index 0000000..b48740b --- /dev/null +++ b/benchmarks/LLVM/6_function_69.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg3) : (i32) -> i64 + %3 = "llvm.sdiv"(%2, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.select"(%0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_7.ll b/benchmarks/LLVM/6_function_7.ll new file mode 100644 index 0000000..74a2d30 --- /dev/null +++ b/benchmarks/LLVM/6_function_7.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.ashr"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_70.ll b/benchmarks/LLVM/6_function_70.ll new file mode 100644 index 0000000..2451892 --- /dev/null +++ b/benchmarks/LLVM/6_function_70.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.ashr"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_71.ll b/benchmarks/LLVM/6_function_71.ll new file mode 100644 index 0000000..a2faf58 --- /dev/null +++ b/benchmarks/LLVM/6_function_71.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%3, %0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_72.ll b/benchmarks/LLVM/6_function_72.ll new file mode 100644 index 0000000..81c8fed --- /dev/null +++ b/benchmarks/LLVM/6_function_72.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %0) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_73.ll b/benchmarks/LLVM/6_function_73.ll new file mode 100644 index 0000000..d5de2e8 --- /dev/null +++ b/benchmarks/LLVM/6_function_73.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_74.ll b/benchmarks/LLVM/6_function_74.ll new file mode 100644 index 0000000..364fa99 --- /dev/null +++ b/benchmarks/LLVM/6_function_74.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_75.ll b/benchmarks/LLVM/6_function_75.ll new file mode 100644 index 0000000..a1995e3 --- /dev/null +++ b/benchmarks/LLVM/6_function_75.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.ashr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.sext"(%arg2) : (i32) -> i64 + %5 = "llvm.ashr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_76.ll b/benchmarks/LLVM/6_function_76.ll new file mode 100644 index 0000000..10c0033 --- /dev/null +++ b/benchmarks/LLVM/6_function_76.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg0) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.urem"(%arg2, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_77.ll b/benchmarks/LLVM/6_function_77.ll new file mode 100644 index 0000000..c44789e --- /dev/null +++ b/benchmarks/LLVM/6_function_77.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.udiv"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_78.ll b/benchmarks/LLVM/6_function_78.ll new file mode 100644 index 0000000..3d940c4 --- /dev/null +++ b/benchmarks/LLVM/6_function_78.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.udiv"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%1, %4) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_79.ll b/benchmarks/LLVM/6_function_79.ll new file mode 100644 index 0000000..be0b7e4 --- /dev/null +++ b/benchmarks/LLVM/6_function_79.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.icmp"(%1, %4) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_8.ll b/benchmarks/LLVM/6_function_8.ll new file mode 100644 index 0000000..1d046a4 --- /dev/null +++ b/benchmarks/LLVM/6_function_8.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%2, %4) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_80.ll b/benchmarks/LLVM/6_function_80.ll new file mode 100644 index 0000000..7259514 --- /dev/null +++ b/benchmarks/LLVM/6_function_80.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_81.ll b/benchmarks/LLVM/6_function_81.ll new file mode 100644 index 0000000..dfe065f --- /dev/null +++ b/benchmarks/LLVM/6_function_81.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.udiv"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_82.ll b/benchmarks/LLVM/6_function_82.ll new file mode 100644 index 0000000..131f33f --- /dev/null +++ b/benchmarks/LLVM/6_function_82.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%arg1, %0) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %2 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.udiv"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_83.ll b/benchmarks/LLVM/6_function_83.ll new file mode 100644 index 0000000..05013de --- /dev/null +++ b/benchmarks/LLVM/6_function_83.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.ashr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.select"(%1, %arg1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.ashr"(%4, %4) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_84.ll b/benchmarks/LLVM/6_function_84.ll new file mode 100644 index 0000000..08b8e9e --- /dev/null +++ b/benchmarks/LLVM/6_function_84.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.lshr"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg3) : (i32) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %5 = "llvm.select"(%4, %2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_85.ll b/benchmarks/LLVM/6_function_85.ll new file mode 100644 index 0000000..970172f --- /dev/null +++ b/benchmarks/LLVM/6_function_85.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%arg0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_86.ll b/benchmarks/LLVM/6_function_86.ll new file mode 100644 index 0000000..e553028 --- /dev/null +++ b/benchmarks/LLVM/6_function_86.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg2, %2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.xor"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.or"(%2, %4) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_87.ll b/benchmarks/LLVM/6_function_87.ll new file mode 100644 index 0000000..ecced08 --- /dev/null +++ b/benchmarks/LLVM/6_function_87.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.urem"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_88.ll b/benchmarks/LLVM/6_function_88.ll new file mode 100644 index 0000000..b43bc58 --- /dev/null +++ b/benchmarks/LLVM/6_function_88.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.or"(%0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.srem"(%3, %arg0) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%3, %4) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_89.ll b/benchmarks/LLVM/6_function_89.ll new file mode 100644 index 0000000..b020e1d --- /dev/null +++ b/benchmarks/LLVM/6_function_89.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.and"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_9.ll b/benchmarks/LLVM/6_function_9.ll new file mode 100644 index 0000000..8a594eb --- /dev/null +++ b/benchmarks/LLVM/6_function_9.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i1, %arg3: i32): + %0 = "llvm.sext"(%arg3) : (i32) -> i64 + %1 = "llvm.select"(%arg2, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_90.ll b/benchmarks/LLVM/6_function_90.ll new file mode 100644 index 0000000..dcfe746 --- /dev/null +++ b/benchmarks/LLVM/6_function_90.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %4 = "llvm.or"(%2, %3) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.icmp"(%arg0, %4) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_91.ll b/benchmarks/LLVM/6_function_91.ll new file mode 100644 index 0000000..61a68aa --- /dev/null +++ b/benchmarks/LLVM/6_function_91.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_92.ll b/benchmarks/LLVM/6_function_92.ll new file mode 100644 index 0000000..2138de8 --- /dev/null +++ b/benchmarks/LLVM/6_function_92.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.srem"(%arg0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_93.ll b/benchmarks/LLVM/6_function_93.ll new file mode 100644 index 0000000..f4d3cb6 --- /dev/null +++ b/benchmarks/LLVM/6_function_93.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_94.ll b/benchmarks/LLVM/6_function_94.ll new file mode 100644 index 0000000..82d802b --- /dev/null +++ b/benchmarks/LLVM/6_function_94.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%3, %0) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%0, %4) : (i64, i64) -> i64 + "llvm.return"(%5) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_95.ll b/benchmarks/LLVM/6_function_95.ll new file mode 100644 index 0000000..11c90d2 --- /dev/null +++ b/benchmarks/LLVM/6_function_95.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.urem"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_96.ll b/benchmarks/LLVM/6_function_96.ll new file mode 100644 index 0000000..d77b0f3 --- /dev/null +++ b/benchmarks/LLVM/6_function_96.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.lshr"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_97.ll b/benchmarks/LLVM/6_function_97.ll new file mode 100644 index 0000000..b601173 --- /dev/null +++ b/benchmarks/LLVM/6_function_97.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.and"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%5) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_98.ll b/benchmarks/LLVM/6_function_98.ll new file mode 100644 index 0000000..1e82f79 --- /dev/null +++ b/benchmarks/LLVM/6_function_98.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.icmp"(%2, %4) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/6_function_99.ll b/benchmarks/LLVM/6_function_99.ll new file mode 100644 index 0000000..ff2e1af --- /dev/null +++ b/benchmarks/LLVM/6_function_99.ll @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.icmp"(%arg2, %arg0) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.sext"(%arg3) : (i32) -> i64 + %2 = "llvm.select"(%0, %1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.urem"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%5) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_0.ll b/benchmarks/LLVM/7_function_0.ll new file mode 100644 index 0000000..6e613ef --- /dev/null +++ b/benchmarks/LLVM/7_function_0.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.select"(%1, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.sdiv"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_1.ll b/benchmarks/LLVM/7_function_1.ll new file mode 100644 index 0000000..01006d7 --- /dev/null +++ b/benchmarks/LLVM/7_function_1.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.sdiv"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_10.ll b/benchmarks/LLVM/7_function_10.ll new file mode 100644 index 0000000..2943109 --- /dev/null +++ b/benchmarks/LLVM/7_function_10.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.lshr"(%0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.urem"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%2, %5) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_11.ll b/benchmarks/LLVM/7_function_11.ll new file mode 100644 index 0000000..eda75d4 --- /dev/null +++ b/benchmarks/LLVM/7_function_11.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.xor"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.sdiv"(%1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_12.ll b/benchmarks/LLVM/7_function_12.ll new file mode 100644 index 0000000..b215203 --- /dev/null +++ b/benchmarks/LLVM/7_function_12.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %arg0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %1) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%arg1, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%2, %5) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_13.ll b/benchmarks/LLVM/7_function_13.ll new file mode 100644 index 0000000..53de435 --- /dev/null +++ b/benchmarks/LLVM/7_function_13.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_14.ll b/benchmarks/LLVM/7_function_14.ll new file mode 100644 index 0000000..85738df --- /dev/null +++ b/benchmarks/LLVM/7_function_14.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i1): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%arg2, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.or"(%3, %4) <{isDisjoint}> : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_15.ll b/benchmarks/LLVM/7_function_15.ll new file mode 100644 index 0000000..e0409ef --- /dev/null +++ b/benchmarks/LLVM/7_function_15.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.icmp"(%arg0, %0) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %2 = "llvm.srem"(%arg2, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.select"(%1, %3, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_16.ll b/benchmarks/LLVM/7_function_16.ll new file mode 100644 index 0000000..f7a1dc4 --- /dev/null +++ b/benchmarks/LLVM/7_function_16.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg3) : (i32) -> i64 + %3 = "llvm.ashr"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_17.ll b/benchmarks/LLVM/7_function_17.ll new file mode 100644 index 0000000..fc35246 --- /dev/null +++ b/benchmarks/LLVM/7_function_17.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg2, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg1, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%arg0, %5) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_18.ll b/benchmarks/LLVM/7_function_18.ll new file mode 100644 index 0000000..f650862 --- /dev/null +++ b/benchmarks/LLVM/7_function_18.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.or"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%arg1, %3) : (i64, i64) -> i64 + %6 = "llvm.and"(%4, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_19.ll b/benchmarks/LLVM/7_function_19.ll new file mode 100644 index 0000000..75a8e0c --- /dev/null +++ b/benchmarks/LLVM/7_function_19.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%3, %0) : (i64, i64) -> i64 + %5 = "llvm.urem"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_2.ll b/benchmarks/LLVM/7_function_2.ll new file mode 100644 index 0000000..8b6e4cc --- /dev/null +++ b/benchmarks/LLVM/7_function_2.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_20.ll b/benchmarks/LLVM/7_function_20.ll new file mode 100644 index 0000000..3865b81 --- /dev/null +++ b/benchmarks/LLVM/7_function_20.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %2 = "llvm.urem"(%arg2, %arg1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%1, %arg0, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.sdiv"(%0, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.lshr"(%arg0, %5) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_21.ll b/benchmarks/LLVM/7_function_21.ll new file mode 100644 index 0000000..17f10e7 --- /dev/null +++ b/benchmarks/LLVM/7_function_21.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 9 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.and"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%4, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_22.ll b/benchmarks/LLVM/7_function_22.ll new file mode 100644 index 0000000..146361e --- /dev/null +++ b/benchmarks/LLVM/7_function_22.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.lshr"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_23.ll b/benchmarks/LLVM/7_function_23.ll new file mode 100644 index 0000000..b48a01a --- /dev/null +++ b/benchmarks/LLVM/7_function_23.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_24.ll b/benchmarks/LLVM/7_function_24.ll new file mode 100644 index 0000000..0baea6e --- /dev/null +++ b/benchmarks/LLVM/7_function_24.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.srem"(%2, %0) : (i64, i64) -> i64 + %6 = "llvm.urem"(%4, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_25.ll b/benchmarks/LLVM/7_function_25.ll new file mode 100644 index 0000000..aa6295b --- /dev/null +++ b/benchmarks/LLVM/7_function_25.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.zext"(%arg3) : (i32) -> i64 + %5 = "llvm.urem"(%2, %0) : (i64, i64) -> i64 + %6 = "llvm.select"(%3, %4, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_26.ll b/benchmarks/LLVM/7_function_26.ll new file mode 100644 index 0000000..c126cc8 --- /dev/null +++ b/benchmarks/LLVM/7_function_26.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg2, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.ashr"(%2, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_27.ll b/benchmarks/LLVM/7_function_27.ll new file mode 100644 index 0000000..58c0228 --- /dev/null +++ b/benchmarks/LLVM/7_function_27.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg1, %2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %5 = "llvm.select"(%4, %arg0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_28.ll b/benchmarks/LLVM/7_function_28.ll new file mode 100644 index 0000000..7a51918 --- /dev/null +++ b/benchmarks/LLVM/7_function_28.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.srem"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_29.ll b/benchmarks/LLVM/7_function_29.ll new file mode 100644 index 0000000..5ba7012 --- /dev/null +++ b/benchmarks/LLVM/7_function_29.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.select"(%0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.sext"(%arg3) : (i32) -> i64 + %3 = "llvm.xor"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%arg2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.and"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.and"(%5, %arg0) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_3.ll b/benchmarks/LLVM/7_function_3.ll new file mode 100644 index 0000000..d3f7a4a --- /dev/null +++ b/benchmarks/LLVM/7_function_3.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg2) : (i32) -> i64 + %3 = "llvm.srem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.sext"(%arg2) : (i32) -> i64 + %5 = "llvm.ashr"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%3, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_30.ll b/benchmarks/LLVM/7_function_30.ll new file mode 100644 index 0000000..65dc23f --- /dev/null +++ b/benchmarks/LLVM/7_function_30.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.select"(%arg0, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.lshr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_31.ll b/benchmarks/LLVM/7_function_31.ll new file mode 100644 index 0000000..2b04549 --- /dev/null +++ b/benchmarks/LLVM/7_function_31.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.and"(%4, %2) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%arg0, %5) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_32.ll b/benchmarks/LLVM/7_function_32.ll new file mode 100644 index 0000000..15fc086 --- /dev/null +++ b/benchmarks/LLVM/7_function_32.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %6 = "llvm.xor"(%4, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_33.ll b/benchmarks/LLVM/7_function_33.ll new file mode 100644 index 0000000..8e20593 --- /dev/null +++ b/benchmarks/LLVM/7_function_33.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.srem"(%4, %arg0) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%arg0, %5) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_34.ll b/benchmarks/LLVM/7_function_34.ll new file mode 100644 index 0000000..8aa0085 --- /dev/null +++ b/benchmarks/LLVM/7_function_34.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %arg1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.lshr"(%3, %1) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_35.ll b/benchmarks/LLVM/7_function_35.ll new file mode 100644 index 0000000..7e45d4c --- /dev/null +++ b/benchmarks/LLVM/7_function_35.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.zext"(%0) : (i32) -> i64 + %3 = "llvm.ashr"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.lshr"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.and"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_36.ll b/benchmarks/LLVM/7_function_36.ll new file mode 100644 index 0000000..fff5555 --- /dev/null +++ b/benchmarks/LLVM/7_function_36.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%arg1, %0) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %3 = "llvm.or"(%1, %1) : (i64, i64) -> i64 + %4 = "llvm.select"(%2, %3, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%1, %5) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_37.ll b/benchmarks/LLVM/7_function_37.ll new file mode 100644 index 0000000..9089be8 --- /dev/null +++ b/benchmarks/LLVM/7_function_37.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.srem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_38.ll b/benchmarks/LLVM/7_function_38.ll new file mode 100644 index 0000000..83f0240 --- /dev/null +++ b/benchmarks/LLVM/7_function_38.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%2, %arg2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %4 = "llvm.select"(%3, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.or"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_39.ll b/benchmarks/LLVM/7_function_39.ll new file mode 100644 index 0000000..50dd37a --- /dev/null +++ b/benchmarks/LLVM/7_function_39.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_4.ll b/benchmarks/LLVM/7_function_4.ll new file mode 100644 index 0000000..8d9e3e5 --- /dev/null +++ b/benchmarks/LLVM/7_function_4.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%arg1, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%arg0, %5) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_40.ll b/benchmarks/LLVM/7_function_40.ll new file mode 100644 index 0000000..e4bd1dd --- /dev/null +++ b/benchmarks/LLVM/7_function_40.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg2) : (i32) -> i64 + %4 = "llvm.srem"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%4, %3) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.ashr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_41.ll b/benchmarks/LLVM/7_function_41.ll new file mode 100644 index 0000000..0a02499 --- /dev/null +++ b/benchmarks/LLVM/7_function_41.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%0, %arg2) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_42.ll b/benchmarks/LLVM/7_function_42.ll new file mode 100644 index 0000000..f5fb331 --- /dev/null +++ b/benchmarks/LLVM/7_function_42.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg1, %arg0) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_43.ll b/benchmarks/LLVM/7_function_43.ll new file mode 100644 index 0000000..a3f0ef8 --- /dev/null +++ b/benchmarks/LLVM/7_function_43.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_44.ll b/benchmarks/LLVM/7_function_44.ll new file mode 100644 index 0000000..2f14267 --- /dev/null +++ b/benchmarks/LLVM/7_function_44.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg2, %arg0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.xor"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_45.ll b/benchmarks/LLVM/7_function_45.ll new file mode 100644 index 0000000..10c03ba --- /dev/null +++ b/benchmarks/LLVM/7_function_45.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.and"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_46.ll b/benchmarks/LLVM/7_function_46.ll new file mode 100644 index 0000000..4170cc4 --- /dev/null +++ b/benchmarks/LLVM/7_function_46.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.ashr"(%arg1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.select"(%0, %1, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_47.ll b/benchmarks/LLVM/7_function_47.ll new file mode 100644 index 0000000..2cf8158 --- /dev/null +++ b/benchmarks/LLVM/7_function_47.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %arg0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.xor"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_48.ll b/benchmarks/LLVM/7_function_48.ll new file mode 100644 index 0000000..d0a9951 --- /dev/null +++ b/benchmarks/LLVM/7_function_48.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_49.ll b/benchmarks/LLVM/7_function_49.ll new file mode 100644 index 0000000..81707be --- /dev/null +++ b/benchmarks/LLVM/7_function_49.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%2, %1) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.or"(%3, %4) <{isDisjoint}> : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_5.ll b/benchmarks/LLVM/7_function_5.ll new file mode 100644 index 0000000..e3a91c6 --- /dev/null +++ b/benchmarks/LLVM/7_function_5.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_50.ll b/benchmarks/LLVM/7_function_50.ll new file mode 100644 index 0000000..45a3cbc --- /dev/null +++ b/benchmarks/LLVM/7_function_50.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg2, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%2, %arg1) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_51.ll b/benchmarks/LLVM/7_function_51.ll new file mode 100644 index 0000000..7d78372 --- /dev/null +++ b/benchmarks/LLVM/7_function_51.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg3, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg3, %1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.udiv"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%arg2, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%0, %5) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_52.ll b/benchmarks/LLVM/7_function_52.ll new file mode 100644 index 0000000..0d0399e --- /dev/null +++ b/benchmarks/LLVM/7_function_52.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.sext"(%0) : (i32) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%1, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_53.ll b/benchmarks/LLVM/7_function_53.ll new file mode 100644 index 0000000..1a46272 --- /dev/null +++ b/benchmarks/LLVM/7_function_53.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.or"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_54.ll b/benchmarks/LLVM/7_function_54.ll new file mode 100644 index 0000000..c72df5e --- /dev/null +++ b/benchmarks/LLVM/7_function_54.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_55.ll b/benchmarks/LLVM/7_function_55.ll new file mode 100644 index 0000000..853c785 --- /dev/null +++ b/benchmarks/LLVM/7_function_55.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_56.ll b/benchmarks/LLVM/7_function_56.ll new file mode 100644 index 0000000..c3365f7 --- /dev/null +++ b/benchmarks/LLVM/7_function_56.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.or"(%1, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_57.ll b/benchmarks/LLVM/7_function_57.ll new file mode 100644 index 0000000..b6b390b --- /dev/null +++ b/benchmarks/LLVM/7_function_57.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.and"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_58.ll b/benchmarks/LLVM/7_function_58.ll new file mode 100644 index 0000000..86175fc --- /dev/null +++ b/benchmarks/LLVM/7_function_58.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.and"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%3, %5) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_59.ll b/benchmarks/LLVM/7_function_59.ll new file mode 100644 index 0000000..468286b --- /dev/null +++ b/benchmarks/LLVM/7_function_59.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_6.ll b/benchmarks/LLVM/7_function_6.ll new file mode 100644 index 0000000..9db3749 --- /dev/null +++ b/benchmarks/LLVM/7_function_6.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_60.ll b/benchmarks/LLVM/7_function_60.ll new file mode 100644 index 0000000..317c65a --- /dev/null +++ b/benchmarks/LLVM/7_function_60.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%3, %arg0) : (i64, i64) -> i64 + %5 = "llvm.srem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_61.ll b/benchmarks/LLVM/7_function_61.ll new file mode 100644 index 0000000..d4c52c7 --- /dev/null +++ b/benchmarks/LLVM/7_function_61.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.zext"(%arg2) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.select"(%1, %4, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.icmp"(%5, %4) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_62.ll b/benchmarks/LLVM/7_function_62.ll new file mode 100644 index 0000000..2ab96d7 --- /dev/null +++ b/benchmarks/LLVM/7_function_62.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.or"(%1, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_63.ll b/benchmarks/LLVM/7_function_63.ll new file mode 100644 index 0000000..e66e172 --- /dev/null +++ b/benchmarks/LLVM/7_function_63.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.sdiv"(%4, %arg0) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_64.ll b/benchmarks/LLVM/7_function_64.ll new file mode 100644 index 0000000..f80a201 --- /dev/null +++ b/benchmarks/LLVM/7_function_64.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_65.ll b/benchmarks/LLVM/7_function_65.ll new file mode 100644 index 0000000..1209ff0 --- /dev/null +++ b/benchmarks/LLVM/7_function_65.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%4, %arg2) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_66.ll b/benchmarks/LLVM/7_function_66.ll new file mode 100644 index 0000000..7daceb8 --- /dev/null +++ b/benchmarks/LLVM/7_function_66.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %4 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %5 = "llvm.urem"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.select"(%3, %arg1, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_67.ll b/benchmarks/LLVM/7_function_67.ll new file mode 100644 index 0000000..b3e364d --- /dev/null +++ b/benchmarks/LLVM/7_function_67.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%4, %2) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_68.ll b/benchmarks/LLVM/7_function_68.ll new file mode 100644 index 0000000..e31d282 --- /dev/null +++ b/benchmarks/LLVM/7_function_68.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %5 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %6 = "llvm.select"(%4, %3, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_69.ll b/benchmarks/LLVM/7_function_69.ll new file mode 100644 index 0000000..33bd95e --- /dev/null +++ b/benchmarks/LLVM/7_function_69.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.or"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.or"(%2, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_7.ll b/benchmarks/LLVM/7_function_7.ll new file mode 100644 index 0000000..4b05de4 --- /dev/null +++ b/benchmarks/LLVM/7_function_7.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.lshr"(%arg2, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.sext"(%arg3) : (i32) -> i64 + %5 = "llvm.or"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%3, %5) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_70.ll b/benchmarks/LLVM/7_function_70.ll new file mode 100644 index 0000000..a7c9f3c --- /dev/null +++ b/benchmarks/LLVM/7_function_70.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.xor"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_71.ll b/benchmarks/LLVM/7_function_71.ll new file mode 100644 index 0000000..f87b16f --- /dev/null +++ b/benchmarks/LLVM/7_function_71.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %6 = "llvm.srem"(%4, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_72.ll b/benchmarks/LLVM/7_function_72.ll new file mode 100644 index 0000000..3c21b1d --- /dev/null +++ b/benchmarks/LLVM/7_function_72.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_73.ll b/benchmarks/LLVM/7_function_73.ll new file mode 100644 index 0000000..2ef524a --- /dev/null +++ b/benchmarks/LLVM/7_function_73.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_74.ll b/benchmarks/LLVM/7_function_74.ll new file mode 100644 index 0000000..9fb383d --- /dev/null +++ b/benchmarks/LLVM/7_function_74.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.lshr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_75.ll b/benchmarks/LLVM/7_function_75.ll new file mode 100644 index 0000000..fe8eb21 --- /dev/null +++ b/benchmarks/LLVM/7_function_75.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %arg0) : (i64, i64) -> i64 + %4 = "llvm.xor"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.select"(%1, %arg2, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_76.ll b/benchmarks/LLVM/7_function_76.ll new file mode 100644 index 0000000..5be9215 --- /dev/null +++ b/benchmarks/LLVM/7_function_76.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.or"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_77.ll b/benchmarks/LLVM/7_function_77.ll new file mode 100644 index 0000000..b2fc783 --- /dev/null +++ b/benchmarks/LLVM/7_function_77.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %0) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%3, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_78.ll b/benchmarks/LLVM/7_function_78.ll new file mode 100644 index 0000000..083c53f --- /dev/null +++ b/benchmarks/LLVM/7_function_78.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg1) : (i32) -> i64 + %2 = "llvm.udiv"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.or"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%0, %5) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_79.ll b/benchmarks/LLVM/7_function_79.ll new file mode 100644 index 0000000..b893429 --- /dev/null +++ b/benchmarks/LLVM/7_function_79.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.or"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_8.ll b/benchmarks/LLVM/7_function_8.ll new file mode 100644 index 0000000..aecf3f3 --- /dev/null +++ b/benchmarks/LLVM/7_function_8.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg1, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.urem"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.or"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%2, %5) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_80.ll b/benchmarks/LLVM/7_function_80.ll new file mode 100644 index 0000000..18d7044 --- /dev/null +++ b/benchmarks/LLVM/7_function_80.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.udiv"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %arg2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%arg1, %3) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %5 = "llvm.select"(%4, %2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.ashr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_81.ll b/benchmarks/LLVM/7_function_81.ll new file mode 100644 index 0000000..c727ddc --- /dev/null +++ b/benchmarks/LLVM/7_function_81.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.lshr"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg0) : (i32) -> i64 + %4 = "llvm.xor"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.or"(%2, %5) <{isDisjoint}> : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_82.ll b/benchmarks/LLVM/7_function_82.ll new file mode 100644 index 0000000..2b5be3d --- /dev/null +++ b/benchmarks/LLVM/7_function_82.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.ashr"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.or"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_83.ll b/benchmarks/LLVM/7_function_83.ll new file mode 100644 index 0000000..6a92e7f --- /dev/null +++ b/benchmarks/LLVM/7_function_83.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.sdiv"(%4, %arg2) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_84.ll b/benchmarks/LLVM/7_function_84.ll new file mode 100644 index 0000000..d42ba33 --- /dev/null +++ b/benchmarks/LLVM/7_function_84.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.and"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.and"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%4, %0) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_85.ll b/benchmarks/LLVM/7_function_85.ll new file mode 100644 index 0000000..5b70f85 --- /dev/null +++ b/benchmarks/LLVM/7_function_85.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %5 = "llvm.urem"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_86.ll b/benchmarks/LLVM/7_function_86.ll new file mode 100644 index 0000000..e75f7fa --- /dev/null +++ b/benchmarks/LLVM/7_function_86.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.or"(%0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.srem"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_87.ll b/benchmarks/LLVM/7_function_87.ll new file mode 100644 index 0000000..eda1724 --- /dev/null +++ b/benchmarks/LLVM/7_function_87.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.icmp"(%2, %5) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_88.ll b/benchmarks/LLVM/7_function_88.ll new file mode 100644 index 0000000..fbbffcb --- /dev/null +++ b/benchmarks/LLVM/7_function_88.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg1, %arg0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_89.ll b/benchmarks/LLVM/7_function_89.ll new file mode 100644 index 0000000..36050a0 --- /dev/null +++ b/benchmarks/LLVM/7_function_89.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg2) : (i32) -> i64 + %2 = "llvm.udiv"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_9.ll b/benchmarks/LLVM/7_function_9.ll new file mode 100644 index 0000000..741c764 --- /dev/null +++ b/benchmarks/LLVM/7_function_9.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.or"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_90.ll b/benchmarks/LLVM/7_function_90.ll new file mode 100644 index 0000000..1bde7a3 --- /dev/null +++ b/benchmarks/LLVM/7_function_90.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_91.ll b/benchmarks/LLVM/7_function_91.ll new file mode 100644 index 0000000..a18a5a2 --- /dev/null +++ b/benchmarks/LLVM/7_function_91.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.sext"(%arg3) : (i32) -> i64 + %5 = "llvm.urem"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%3, %5) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_92.ll b/benchmarks/LLVM/7_function_92.ll new file mode 100644 index 0000000..84c93bb --- /dev/null +++ b/benchmarks/LLVM/7_function_92.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.and"(%arg1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %5 = "llvm.select"(%4, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_93.ll b/benchmarks/LLVM/7_function_93.ll new file mode 100644 index 0000000..0a9b213 --- /dev/null +++ b/benchmarks/LLVM/7_function_93.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_94.ll b/benchmarks/LLVM/7_function_94.ll new file mode 100644 index 0000000..310152f --- /dev/null +++ b/benchmarks/LLVM/7_function_94.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%3, %arg0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%6) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_95.ll b/benchmarks/LLVM/7_function_95.ll new file mode 100644 index 0000000..53de64b --- /dev/null +++ b/benchmarks/LLVM/7_function_95.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_96.ll b/benchmarks/LLVM/7_function_96.ll new file mode 100644 index 0000000..2ffb1db --- /dev/null +++ b/benchmarks/LLVM/7_function_96.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%0, %arg1) : (i64, i64) -> i64 + %5 = "llvm.xor"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%6) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_97.ll b/benchmarks/LLVM/7_function_97.ll new file mode 100644 index 0000000..4ccc39e --- /dev/null +++ b/benchmarks/LLVM/7_function_97.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.xor"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%arg0, %5) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_98.ll b/benchmarks/LLVM/7_function_98.ll new file mode 100644 index 0000000..b1a5d12 --- /dev/null +++ b/benchmarks/LLVM/7_function_98.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %0) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %3 = "llvm.ashr"(%0, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%2, %3, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.and"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%5, %1) : (i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/7_function_99.ll b/benchmarks/LLVM/7_function_99.ll new file mode 100644 index 0000000..c93e7ed --- /dev/null +++ b/benchmarks/LLVM/7_function_99.ll @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.select"(%3, %arg1, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%6) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_0.ll b/benchmarks/LLVM/8_function_0.ll new file mode 100644 index 0000000..5b4c4cf --- /dev/null +++ b/benchmarks/LLVM/8_function_0.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.ashr"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.or"(%arg1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %arg2) : (i64, i64) -> i64 + %6 = "llvm.and"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_1.ll b/benchmarks/LLVM/8_function_1.ll new file mode 100644 index 0000000..ed8f440 --- /dev/null +++ b/benchmarks/LLVM/8_function_1.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i32, %arg2: i1): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.sext"(%arg1) : (i32) -> i64 + %5 = "llvm.select"(%arg2, %0, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.srem"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.srem"(%3, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_10.ll b/benchmarks/LLVM/8_function_10.ll new file mode 100644 index 0000000..0434243 --- /dev/null +++ b/benchmarks/LLVM/8_function_10.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.lshr"(%0, %arg2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%4, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %6 = "llvm.select"(%5, %0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.select"(%3, %6, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_11.ll b/benchmarks/LLVM/8_function_11.ll new file mode 100644 index 0000000..3cbdb5f --- /dev/null +++ b/benchmarks/LLVM/8_function_11.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.zext"(%arg3) : (i32) -> i64 + %6 = "llvm.and"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_12.ll b/benchmarks/LLVM/8_function_12.ll new file mode 100644 index 0000000..20fd9af --- /dev/null +++ b/benchmarks/LLVM/8_function_12.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%arg1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.lshr"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_13.ll b/benchmarks/LLVM/8_function_13.ll new file mode 100644 index 0000000..df40a7e --- /dev/null +++ b/benchmarks/LLVM/8_function_13.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.or"(%0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.and"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %7 = "llvm.zext"(%6) : (i32) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_14.ll b/benchmarks/LLVM/8_function_14.ll new file mode 100644 index 0000000..3dde64c --- /dev/null +++ b/benchmarks/LLVM/8_function_14.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32, %arg3: i1): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.ashr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %arg1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.lshr"(%4, %3) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.urem"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_15.ll b/benchmarks/LLVM/8_function_15.ll new file mode 100644 index 0000000..10e55fd --- /dev/null +++ b/benchmarks/LLVM/8_function_15.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %3 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %4 = "llvm.select"(%2, %arg2, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.zext"(%arg3) : (i32) -> i64 + %6 = "llvm.and"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_16.ll b/benchmarks/LLVM/8_function_16.ll new file mode 100644 index 0000000..9720ea7 --- /dev/null +++ b/benchmarks/LLVM/8_function_16.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%5, %arg2) : (i64, i64) -> i64 + %7 = "llvm.sdiv"(%1, %6) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_17.ll b/benchmarks/LLVM/8_function_17.ll new file mode 100644 index 0000000..0c8410b --- /dev/null +++ b/benchmarks/LLVM/8_function_17.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg1, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg1, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_18.ll b/benchmarks/LLVM/8_function_18.ll new file mode 100644 index 0000000..d340815 --- /dev/null +++ b/benchmarks/LLVM/8_function_18.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%4, %6) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_19.ll b/benchmarks/LLVM/8_function_19.ll new file mode 100644 index 0000000..b89865b --- /dev/null +++ b/benchmarks/LLVM/8_function_19.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.select"(%3, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%6, %4) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_2.ll b/benchmarks/LLVM/8_function_2.ll new file mode 100644 index 0000000..3828a02 --- /dev/null +++ b/benchmarks/LLVM/8_function_2.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.and"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.sext"(%arg1) : (i32) -> i64 + %3 = "llvm.urem"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.and"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%arg2, %0) : (i64, i64) -> i64 + %7 = "llvm.urem"(%5, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_20.ll b/benchmarks/LLVM/8_function_20.ll new file mode 100644 index 0000000..a37ce93 --- /dev/null +++ b/benchmarks/LLVM/8_function_20.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.lshr"(%3, %1) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.and"(%5, %arg0) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_21.ll b/benchmarks/LLVM/8_function_21.ll new file mode 100644 index 0000000..c2ccabe --- /dev/null +++ b/benchmarks/LLVM/8_function_21.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%arg2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_22.ll b/benchmarks/LLVM/8_function_22.ll new file mode 100644 index 0000000..a63b5e2 --- /dev/null +++ b/benchmarks/LLVM/8_function_22.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg2, %arg1) : (i64, i64) -> i64 + %5 = "llvm.select"(%0, %4, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.select"(%0, %3, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_23.ll b/benchmarks/LLVM/8_function_23.ll new file mode 100644 index 0000000..37486f8 --- /dev/null +++ b/benchmarks/LLVM/8_function_23.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.udiv"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg1, %1) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.srem"(%2, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_24.ll b/benchmarks/LLVM/8_function_24.ll new file mode 100644 index 0000000..8f48fad --- /dev/null +++ b/benchmarks/LLVM/8_function_24.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.udiv"(%arg2, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%0, %6) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_25.ll b/benchmarks/LLVM/8_function_25.ll new file mode 100644 index 0000000..3ec9e51 --- /dev/null +++ b/benchmarks/LLVM/8_function_25.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64, %arg3: i32): + %0 = "llvm.select"(%arg1, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.sext"(%arg3) : (i32) -> i64 + %3 = "llvm.lshr"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.lshr"(%3, %2) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_26.ll b/benchmarks/LLVM/8_function_26.ll new file mode 100644 index 0000000..c883489 --- /dev/null +++ b/benchmarks/LLVM/8_function_26.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg1) : (i32) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%3, %2) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.sdiv"(%6, %4) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_27.ll b/benchmarks/LLVM/8_function_27.ll new file mode 100644 index 0000000..f3636a6 --- /dev/null +++ b/benchmarks/LLVM/8_function_27.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.ashr"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.urem"(%arg0, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_28.ll b/benchmarks/LLVM/8_function_28.ll new file mode 100644 index 0000000..11e86ee --- /dev/null +++ b/benchmarks/LLVM/8_function_28.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.select"(%0, %1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.zext"(%arg1) : (i32) -> i64 + %4 = "llvm.ashr"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%4, %6) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_29.ll b/benchmarks/LLVM/8_function_29.ll new file mode 100644 index 0000000..72250b2 --- /dev/null +++ b/benchmarks/LLVM/8_function_29.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %0, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.srem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%5, %arg0) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_3.ll b/benchmarks/LLVM/8_function_3.ll new file mode 100644 index 0000000..b21f361 --- /dev/null +++ b/benchmarks/LLVM/8_function_3.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.urem"(%arg0, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_30.ll b/benchmarks/LLVM/8_function_30.ll new file mode 100644 index 0000000..d642fcb --- /dev/null +++ b/benchmarks/LLVM/8_function_30.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_31.ll b/benchmarks/LLVM/8_function_31.ll new file mode 100644 index 0000000..2bc08e5 --- /dev/null +++ b/benchmarks/LLVM/8_function_31.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.lshr"(%1, %arg2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%3, %4) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %6 = "llvm.srem"(%3, %0) : (i64, i64) -> i64 + %7 = "llvm.select"(%5, %arg2, %6) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_32.ll b/benchmarks/LLVM/8_function_32.ll new file mode 100644 index 0000000..5603784 --- /dev/null +++ b/benchmarks/LLVM/8_function_32.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.select"(%arg0, %5, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_33.ll b/benchmarks/LLVM/8_function_33.ll new file mode 100644 index 0000000..84a4b14 --- /dev/null +++ b/benchmarks/LLVM/8_function_33.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.select"(%3, %2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.and"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_34.ll b/benchmarks/LLVM/8_function_34.ll new file mode 100644 index 0000000..45b815f --- /dev/null +++ b/benchmarks/LLVM/8_function_34.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg2, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.or"(%0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.or"(%0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%4, %2) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.srem"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_35.ll b/benchmarks/LLVM/8_function_35.ll new file mode 100644 index 0000000..5d18785 --- /dev/null +++ b/benchmarks/LLVM/8_function_35.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_36.ll b/benchmarks/LLVM/8_function_36.ll new file mode 100644 index 0000000..7f47086 --- /dev/null +++ b/benchmarks/LLVM/8_function_36.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.urem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg3) : (i32) -> i64 + %2 = "llvm.urem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %0) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%arg1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.select"(%arg0, %0, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_37.ll b/benchmarks/LLVM/8_function_37.ll new file mode 100644 index 0000000..a4626e3 --- /dev/null +++ b/benchmarks/LLVM/8_function_37.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%5, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_38.ll b/benchmarks/LLVM/8_function_38.ll new file mode 100644 index 0000000..ba5b700 --- /dev/null +++ b/benchmarks/LLVM/8_function_38.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %1 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.zext"(%arg3) : (i32) -> i64 + %7 = "llvm.select"(%0, %5, %6) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_39.ll b/benchmarks/LLVM/8_function_39.ll new file mode 100644 index 0000000..416e2d0 --- /dev/null +++ b/benchmarks/LLVM/8_function_39.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %2) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.or"(%1, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_4.ll b/benchmarks/LLVM/8_function_4.ll new file mode 100644 index 0000000..6945d92 --- /dev/null +++ b/benchmarks/LLVM/8_function_4.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.select"(%arg3, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.ashr"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.or"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%arg2, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%5, %6) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_40.ll b/benchmarks/LLVM/8_function_40.ll new file mode 100644 index 0000000..33e1826 --- /dev/null +++ b/benchmarks/LLVM/8_function_40.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%1, %1) <{predicate = 9 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.or"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%arg2, %arg2) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.or"(%arg1, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.ashr"(%4, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_41.ll b/benchmarks/LLVM/8_function_41.ll new file mode 100644 index 0000000..e4dcd2d --- /dev/null +++ b/benchmarks/LLVM/8_function_41.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.ashr"(%arg2, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.select"(%0, %3, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_42.ll b/benchmarks/LLVM/8_function_42.ll new file mode 100644 index 0000000..6c316e8 --- /dev/null +++ b/benchmarks/LLVM/8_function_42.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.lshr"(%0, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.srem"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%5, %2) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.select"(%1, %arg2, %6) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_43.ll b/benchmarks/LLVM/8_function_43.ll new file mode 100644 index 0000000..fea520b --- /dev/null +++ b/benchmarks/LLVM/8_function_43.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i1, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_44.ll b/benchmarks/LLVM/8_function_44.ll new file mode 100644 index 0000000..ff04894 --- /dev/null +++ b/benchmarks/LLVM/8_function_44.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %4 = "llvm.and"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.or"(%4, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_45.ll b/benchmarks/LLVM/8_function_45.ll new file mode 100644 index 0000000..b726fd0 --- /dev/null +++ b/benchmarks/LLVM/8_function_45.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg1) : (i32) -> i64 + %4 = "llvm.ashr"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%arg2, %arg2) : (i64, i64) -> i64 + %6 = "llvm.srem"(%5, %2) : (i64, i64) -> i64 + %7 = "llvm.lshr"(%4, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_46.ll b/benchmarks/LLVM/8_function_46.ll new file mode 100644 index 0000000..8f0236f --- /dev/null +++ b/benchmarks/LLVM/8_function_46.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %arg2) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %arg0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_47.ll b/benchmarks/LLVM/8_function_47.ll new file mode 100644 index 0000000..aadb174 --- /dev/null +++ b/benchmarks/LLVM/8_function_47.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.srem"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.xor"(%arg1, %arg1) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %arg2) : (i64, i64) -> i64 + %6 = "llvm.srem"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_48.ll b/benchmarks/LLVM/8_function_48.ll new file mode 100644 index 0000000..3f9101c --- /dev/null +++ b/benchmarks/LLVM/8_function_48.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%arg0, %arg2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %6 = "llvm.xor"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.srem"(%2, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_49.ll b/benchmarks/LLVM/8_function_49.ll new file mode 100644 index 0000000..70662fa --- /dev/null +++ b/benchmarks/LLVM/8_function_49.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1, %arg3: i32): + %0 = "llvm.select"(%arg2, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sext"(%arg3) : (i32) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg2, %3, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.and"(%arg0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_5.ll b/benchmarks/LLVM/8_function_5.ll new file mode 100644 index 0000000..4db7332 --- /dev/null +++ b/benchmarks/LLVM/8_function_5.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.srem"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%arg0, %6) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_50.ll b/benchmarks/LLVM/8_function_50.ll new file mode 100644 index 0000000..7dd4b98 --- /dev/null +++ b/benchmarks/LLVM/8_function_50.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %3) : (i64, i64) -> i64 + %5 = "llvm.select"(%arg3, %4, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.lshr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_51.ll b/benchmarks/LLVM/8_function_51.ll new file mode 100644 index 0000000..35e2595 --- /dev/null +++ b/benchmarks/LLVM/8_function_51.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.zext"(%arg3) : (i32) -> i64 + %5 = "llvm.lshr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.sdiv"(%2, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_52.ll b/benchmarks/LLVM/8_function_52.ll new file mode 100644 index 0000000..e487323 --- /dev/null +++ b/benchmarks/LLVM/8_function_52.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_53.ll b/benchmarks/LLVM/8_function_53.ll new file mode 100644 index 0000000..c73d323 --- /dev/null +++ b/benchmarks/LLVM/8_function_53.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_54.ll b/benchmarks/LLVM/8_function_54.ll new file mode 100644 index 0000000..94eb3b4 --- /dev/null +++ b/benchmarks/LLVM/8_function_54.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.lshr"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg2) : (i32) -> i64 + %4 = "llvm.urem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_55.ll b/benchmarks/LLVM/8_function_55.ll new file mode 100644 index 0000000..aabf860 --- /dev/null +++ b/benchmarks/LLVM/8_function_55.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg2, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %7 = "llvm.zext"(%6) : (i32) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_56.ll b/benchmarks/LLVM/8_function_56.ll new file mode 100644 index 0000000..aeb90d6 --- /dev/null +++ b/benchmarks/LLVM/8_function_56.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %4 = "llvm.urem"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_57.ll b/benchmarks/LLVM/8_function_57.ll new file mode 100644 index 0000000..57411c3 --- /dev/null +++ b/benchmarks/LLVM/8_function_57.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg1, %arg2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%3, %1) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %5 = "llvm.select"(%4, %arg0, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.or"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%1, %6) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_58.ll b/benchmarks/LLVM/8_function_58.ll new file mode 100644 index 0000000..599e3c5 --- /dev/null +++ b/benchmarks/LLVM/8_function_58.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%3, %6) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_59.ll b/benchmarks/LLVM/8_function_59.ll new file mode 100644 index 0000000..0d9f9aa --- /dev/null +++ b/benchmarks/LLVM/8_function_59.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.udiv"(%arg2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%3, %arg1) : (i64, i64) -> i64 + %6 = "llvm.srem"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_6.ll b/benchmarks/LLVM/8_function_6.ll new file mode 100644 index 0000000..f7d614d --- /dev/null +++ b/benchmarks/LLVM/8_function_6.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.select"(%arg3, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.or"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.xor"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %2) : (i64, i64) -> i64 + %6 = "llvm.srem"(%arg1, %5) : (i64, i64) -> i64 + %7 = "llvm.ashr"(%0, %6) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_60.ll b/benchmarks/LLVM/8_function_60.ll new file mode 100644 index 0000000..fa728f9 --- /dev/null +++ b/benchmarks/LLVM/8_function_60.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.srem"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.sdiv"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_61.ll b/benchmarks/LLVM/8_function_61.ll new file mode 100644 index 0000000..b2f6fe4 --- /dev/null +++ b/benchmarks/LLVM/8_function_61.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.xor"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%arg0, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_62.ll b/benchmarks/LLVM/8_function_62.ll new file mode 100644 index 0000000..a76e551 --- /dev/null +++ b/benchmarks/LLVM/8_function_62.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.ashr"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.and"(%6, %arg2) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_63.ll b/benchmarks/LLVM/8_function_63.ll new file mode 100644 index 0000000..8923ab0 --- /dev/null +++ b/benchmarks/LLVM/8_function_63.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %2 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.select"(%1, %arg1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.urem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%5, %6) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_64.ll b/benchmarks/LLVM/8_function_64.ll new file mode 100644 index 0000000..060a8bb --- /dev/null +++ b/benchmarks/LLVM/8_function_64.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %arg2) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_65.ll b/benchmarks/LLVM/8_function_65.ll new file mode 100644 index 0000000..e7a75e0 --- /dev/null +++ b/benchmarks/LLVM/8_function_65.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.srem"(%5, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_66.ll b/benchmarks/LLVM/8_function_66.ll new file mode 100644 index 0000000..368c2e0 --- /dev/null +++ b/benchmarks/LLVM/8_function_66.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.srem"(%2, %5) : (i64, i64) -> i64 + %7 = "llvm.and"(%0, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_67.ll b/benchmarks/LLVM/8_function_67.ll new file mode 100644 index 0000000..a4e6041 --- /dev/null +++ b/benchmarks/LLVM/8_function_67.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.or"(%0, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%6, %6) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_68.ll b/benchmarks/LLVM/8_function_68.ll new file mode 100644 index 0000000..3339b4a --- /dev/null +++ b/benchmarks/LLVM/8_function_68.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_69.ll b/benchmarks/LLVM/8_function_69.ll new file mode 100644 index 0000000..97abc7c --- /dev/null +++ b/benchmarks/LLVM/8_function_69.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %0) : (i64, i64) -> i64 + %4 = "llvm.or"(%1, %3) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.sdiv"(%5, %arg2) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.srem"(%2, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_7.ll b/benchmarks/LLVM/8_function_7.ll new file mode 100644 index 0000000..a52256b --- /dev/null +++ b/benchmarks/LLVM/8_function_7.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg3, %1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.and"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%arg2, %5) : (i64, i64) -> i64 + %7 = "llvm.or"(%2, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_70.ll b/benchmarks/LLVM/8_function_70.ll new file mode 100644 index 0000000..f732ac9 --- /dev/null +++ b/benchmarks/LLVM/8_function_70.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.icmp"(%0, %arg0) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%arg1, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.select"(%1, %0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.select"(%arg1, %3, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.lshr"(%arg0, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_71.ll b/benchmarks/LLVM/8_function_71.ll new file mode 100644 index 0000000..fde854a --- /dev/null +++ b/benchmarks/LLVM/8_function_71.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %5 = "llvm.lshr"(%arg0, %2) : (i64, i64) -> i64 + %6 = "llvm.select"(%4, %arg2, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.select"(%3, %2, %6) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_72.ll b/benchmarks/LLVM/8_function_72.ll new file mode 100644 index 0000000..afad6bb --- /dev/null +++ b/benchmarks/LLVM/8_function_72.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.udiv"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_73.ll b/benchmarks/LLVM/8_function_73.ll new file mode 100644 index 0000000..07dcffe --- /dev/null +++ b/benchmarks/LLVM/8_function_73.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.udiv"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%3, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_74.ll b/benchmarks/LLVM/8_function_74.ll new file mode 100644 index 0000000..a8657f4 --- /dev/null +++ b/benchmarks/LLVM/8_function_74.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %6 = "llvm.select"(%2, %4, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_75.ll b/benchmarks/LLVM/8_function_75.ll new file mode 100644 index 0000000..79bf244 --- /dev/null +++ b/benchmarks/LLVM/8_function_75.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.xor"(%arg2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.or"(%4, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_76.ll b/benchmarks/LLVM/8_function_76.ll new file mode 100644 index 0000000..ee6953b --- /dev/null +++ b/benchmarks/LLVM/8_function_76.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.srem"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_77.ll b/benchmarks/LLVM/8_function_77.ll new file mode 100644 index 0000000..e201008 --- /dev/null +++ b/benchmarks/LLVM/8_function_77.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg2, %2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.sdiv"(%arg1, %arg0) : (i64, i64) -> i64 + %5 = "llvm.srem"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.or"(%arg0, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.xor"(%2, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_78.ll b/benchmarks/LLVM/8_function_78.ll new file mode 100644 index 0000000..02d8092 --- /dev/null +++ b/benchmarks/LLVM/8_function_78.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.or"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg3, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.select"(%arg3, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.sdiv"(%2, %0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.udiv"(%0, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_79.ll b/benchmarks/LLVM/8_function_79.ll new file mode 100644 index 0000000..817a179 --- /dev/null +++ b/benchmarks/LLVM/8_function_79.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.select"(%arg2, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.sdiv"(%arg1, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_8.ll b/benchmarks/LLVM/8_function_8.ll new file mode 100644 index 0000000..1663f80 --- /dev/null +++ b/benchmarks/LLVM/8_function_8.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %4 = "llvm.zext"(%arg3) : (i32) -> i64 + %5 = "llvm.and"(%4, %arg0) : (i64, i64) -> i64 + %6 = "llvm.or"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_80.ll b/benchmarks/LLVM/8_function_80.ll new file mode 100644 index 0000000..4170ae7 --- /dev/null +++ b/benchmarks/LLVM/8_function_80.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg1, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%2, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_81.ll b/benchmarks/LLVM/8_function_81.ll new file mode 100644 index 0000000..bcc5379 --- /dev/null +++ b/benchmarks/LLVM/8_function_81.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.ashr"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.and"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%4, %arg1) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.sdiv"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.ashr"(%4, %6) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_82.ll b/benchmarks/LLVM/8_function_82.ll new file mode 100644 index 0000000..ecbe5f6 --- /dev/null +++ b/benchmarks/LLVM/8_function_82.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %3 = "llvm.or"(%arg1, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%2, %3, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_83.ll b/benchmarks/LLVM/8_function_83.ll new file mode 100644 index 0000000..1d590e5 --- /dev/null +++ b/benchmarks/LLVM/8_function_83.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.lshr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_84.ll b/benchmarks/LLVM/8_function_84.ll new file mode 100644 index 0000000..9eb3022 --- /dev/null +++ b/benchmarks/LLVM/8_function_84.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.zext"(%arg1) : (i32) -> i64 + %3 = "llvm.srem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.and"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_85.ll b/benchmarks/LLVM/8_function_85.ll new file mode 100644 index 0000000..d18d4a8 --- /dev/null +++ b/benchmarks/LLVM/8_function_85.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.urem"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.select"(%1, %4, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.udiv"(%arg2, %3) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%5, %6) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_86.ll b/benchmarks/LLVM/8_function_86.ll new file mode 100644 index 0000000..48ef532 --- /dev/null +++ b/benchmarks/LLVM/8_function_86.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.lshr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.xor"(%2, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%6, %6) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_87.ll b/benchmarks/LLVM/8_function_87.ll new file mode 100644 index 0000000..e7dc8f2 --- /dev/null +++ b/benchmarks/LLVM/8_function_87.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.ashr"(%2, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %7 = "llvm.sext"(%6) : (i32) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_88.ll b/benchmarks/LLVM/8_function_88.ll new file mode 100644 index 0000000..4b05952 --- /dev/null +++ b/benchmarks/LLVM/8_function_88.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.xor"(%arg2, %arg0) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%5, %6) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_89.ll b/benchmarks/LLVM/8_function_89.ll new file mode 100644 index 0000000..7c42493 --- /dev/null +++ b/benchmarks/LLVM/8_function_89.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_9.ll b/benchmarks/LLVM/8_function_9.ll new file mode 100644 index 0000000..9187f74 --- /dev/null +++ b/benchmarks/LLVM/8_function_9.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.urem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.srem"(%5, %4) : (i64, i64) -> i64 + %7 = "llvm.sdiv"(%0, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_90.ll b/benchmarks/LLVM/8_function_90.ll new file mode 100644 index 0000000..2aedb69 --- /dev/null +++ b/benchmarks/LLVM/8_function_90.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.icmp"(%arg0, %2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %4 = "llvm.select"(%3, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_91.ll b/benchmarks/LLVM/8_function_91.ll new file mode 100644 index 0000000..5f209f0 --- /dev/null +++ b/benchmarks/LLVM/8_function_91.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%6, %1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_92.ll b/benchmarks/LLVM/8_function_92.ll new file mode 100644 index 0000000..35affdd --- /dev/null +++ b/benchmarks/LLVM/8_function_92.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %arg1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.and"(%5, %arg1) : (i64, i64) -> i64 + %7 = "llvm.urem"(%5, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_93.ll b/benchmarks/LLVM/8_function_93.ll new file mode 100644 index 0000000..2b8fafb --- /dev/null +++ b/benchmarks/LLVM/8_function_93.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.udiv"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg0, %2, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_94.ll b/benchmarks/LLVM/8_function_94.ll new file mode 100644 index 0000000..30f9c70 --- /dev/null +++ b/benchmarks/LLVM/8_function_94.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.ashr"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg3) : (i32) -> i64 + %4 = "llvm.srem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.select"(%1, %0, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.srem"(%arg2, %3) : (i64, i64) -> i64 + %7 = "llvm.ashr"(%5, %6) <{isExact}> : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_95.ll b/benchmarks/LLVM/8_function_95.ll new file mode 100644 index 0000000..e3c915a --- /dev/null +++ b/benchmarks/LLVM/8_function_95.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg2) <{predicate = 9 : i64}> : (i64, i64) -> i1 + %2 = "llvm.urem"(%arg2, %arg1) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %arg1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.udiv"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%6, %3) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_96.ll b/benchmarks/LLVM/8_function_96.ll new file mode 100644 index 0000000..571eb25 --- /dev/null +++ b/benchmarks/LLVM/8_function_96.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %7 = "llvm.udiv"(%5, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_97.ll b/benchmarks/LLVM/8_function_97.ll new file mode 100644 index 0000000..5b8a11b --- /dev/null +++ b/benchmarks/LLVM/8_function_97.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg2) : (i32) -> i64 + %4 = "llvm.urem"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.or"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.sext"(%arg2) : (i32) -> i64 + %7 = "llvm.udiv"(%5, %6) : (i64, i64) -> i64 + "llvm.return"(%7) : (i64) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_98.ll b/benchmarks/LLVM/8_function_98.ll new file mode 100644 index 0000000..50f21a2 --- /dev/null +++ b/benchmarks/LLVM/8_function_98.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.udiv"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "llvm.return"(%7) : (i32) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVM/8_function_99.ll b/benchmarks/LLVM/8_function_99.ll new file mode 100644 index 0000000..dfddeca --- /dev/null +++ b/benchmarks/LLVM/8_function_99.ll @@ -0,0 +1,15 @@ +"builtin.module"() ({ + "llvm.func"() <{CConv = #llvm.cconv, function_type = !llvm.func, linkage = #llvm.linkage, sym_name = "main", visibility_ = 0 : i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.or"(%arg1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.select"(%0, %3, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.xor"(%4, %arg0) : (i64, i64) -> i64 + %6 = "llvm.urem"(%5, %3) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "llvm.return"(%7) : (i1) -> () + }) : () -> () +}) : () -> () + diff --git a/benchmarks/LLVMIR/3_function_0.mlir b/benchmarks/LLVMIR/3_function_0.mlir new file mode 100644 index 0000000..206cf98 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_0.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = urem i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = zext i32 %4 to i64 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_1.mlir b/benchmarks/LLVMIR/3_function_1.mlir new file mode 100644 index 0000000..3b0bfde --- /dev/null +++ b/benchmarks/LLVMIR/3_function_1.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0) { + %2 = sext i32 %0 to i64 + %3 = urem i64 %2, %2 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_10.mlir b/benchmarks/LLVMIR/3_function_10.mlir new file mode 100644 index 0000000..070aab7 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_10.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %1 + %4 = srem i64 %3, %1 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_11.mlir b/benchmarks/LLVMIR/3_function_11.mlir new file mode 100644 index 0000000..febd1fa --- /dev/null +++ b/benchmarks/LLVMIR/3_function_11.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = and i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_12.mlir b/benchmarks/LLVMIR/3_function_12.mlir new file mode 100644 index 0000000..35990ad --- /dev/null +++ b/benchmarks/LLVMIR/3_function_12.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = lshr i64 %0, %0 + %4 = udiv i64 %1, %1 + %5 = and i64 %3, %4 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_13.mlir b/benchmarks/LLVMIR/3_function_13.mlir new file mode 100644 index 0000000..a02dd6d --- /dev/null +++ b/benchmarks/LLVMIR/3_function_13.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %1, %2 + %5 = and i64 %1, %4 + %6 = icmp sle i64 %0, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_14.mlir b/benchmarks/LLVMIR/3_function_14.mlir new file mode 100644 index 0000000..5a98ac7 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_14.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %1 + %5 = xor i64 %4, %2 + %6 = srem i64 %5, %1 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_15.mlir b/benchmarks/LLVMIR/3_function_15.mlir new file mode 100644 index 0000000..e055b4b --- /dev/null +++ b/benchmarks/LLVMIR/3_function_15.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = and i64 %0, %0 + %4 = or disjoint i64 %0, %3 + %5 = icmp ult i64 %4, %1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_16.mlir b/benchmarks/LLVMIR/3_function_16.mlir new file mode 100644 index 0000000..3db3161 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_16.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = xor i64 %0, %0 + %3 = sdiv i64 %0, %2 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_17.mlir b/benchmarks/LLVMIR/3_function_17.mlir new file mode 100644 index 0000000..666297b --- /dev/null +++ b/benchmarks/LLVMIR/3_function_17.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = and i64 %4, %1 + %6 = and i64 %5, %2 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_18.mlir b/benchmarks/LLVMIR/3_function_18.mlir new file mode 100644 index 0000000..e7c1d3f --- /dev/null +++ b/benchmarks/LLVMIR/3_function_18.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = lshr i64 %1, %0 + %4 = sdiv exact i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_19.mlir b/benchmarks/LLVMIR/3_function_19.mlir new file mode 100644 index 0000000..8b372d4 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_19.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_2.mlir b/benchmarks/LLVMIR/3_function_2.mlir new file mode 100644 index 0000000..5b68c79 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_2.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = lshr exact i64 %1, %1 + %4 = and i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_20.mlir b/benchmarks/LLVMIR/3_function_20.mlir new file mode 100644 index 0000000..156ce2c --- /dev/null +++ b/benchmarks/LLVMIR/3_function_20.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = lshr exact i64 %1, %0 + %4 = lshr exact i64 %0, %3 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_21.mlir b/benchmarks/LLVMIR/3_function_21.mlir new file mode 100644 index 0000000..08a5291 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_21.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = icmp eq i64 %0, %3 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_22.mlir b/benchmarks/LLVMIR/3_function_22.mlir new file mode 100644 index 0000000..102e15d --- /dev/null +++ b/benchmarks/LLVMIR/3_function_22.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = ashr i64 %4, %2 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_23.mlir b/benchmarks/LLVMIR/3_function_23.mlir new file mode 100644 index 0000000..91f6e3a --- /dev/null +++ b/benchmarks/LLVMIR/3_function_23.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = or i64 %1, %2 + %5 = select i1 %0, i64 %4, i64 %1 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_24.mlir b/benchmarks/LLVMIR/3_function_24.mlir new file mode 100644 index 0000000..d429b90 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_24.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1) { + %3 = trunc i64 %1 to i32 + %4 = sext i32 %3 to i64 + %5 = select i1 %0, i64 %1, i64 %4 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_25.mlir b/benchmarks/LLVMIR/3_function_25.mlir new file mode 100644 index 0000000..6acfcc0 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_25.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_26.mlir b/benchmarks/LLVMIR/3_function_26.mlir new file mode 100644 index 0000000..1e7f33c --- /dev/null +++ b/benchmarks/LLVMIR/3_function_26.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = ashr exact i64 %0, %0 + %3 = and i64 %2, %0 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_27.mlir b/benchmarks/LLVMIR/3_function_27.mlir new file mode 100644 index 0000000..7a200d5 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_27.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = or disjoint i64 %0, %3 + ret i64 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_28.mlir b/benchmarks/LLVMIR/3_function_28.mlir new file mode 100644 index 0000000..3c6cfe4 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_28.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %2, %1 + %5 = select i1 %0, i64 %1, i64 %4 + %6 = icmp eq i64 %5, %2 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_29.mlir b/benchmarks/LLVMIR/3_function_29.mlir new file mode 100644 index 0000000..6d9b87b --- /dev/null +++ b/benchmarks/LLVMIR/3_function_29.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = icmp sge i64 %3, %0 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_3.mlir b/benchmarks/LLVMIR/3_function_3.mlir new file mode 100644 index 0000000..75c47cf --- /dev/null +++ b/benchmarks/LLVMIR/3_function_3.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = xor i64 %4, %2 + %6 = icmp sle i64 %4, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_30.mlir b/benchmarks/LLVMIR/3_function_30.mlir new file mode 100644 index 0000000..06dc811 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_30.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %1 + %4 = or i64 %0, %3 + %5 = icmp sle i64 %0, %4 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_31.mlir b/benchmarks/LLVMIR/3_function_31.mlir new file mode 100644 index 0000000..7aaa0aa --- /dev/null +++ b/benchmarks/LLVMIR/3_function_31.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = ashr exact i64 %4, %2 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_32.mlir b/benchmarks/LLVMIR/3_function_32.mlir new file mode 100644 index 0000000..ddbd103 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_32.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %0, %1 + %5 = sdiv exact i64 %4, %2 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_33.mlir b/benchmarks/LLVMIR/3_function_33.mlir new file mode 100644 index 0000000..db17744 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_33.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_34.mlir b/benchmarks/LLVMIR/3_function_34.mlir new file mode 100644 index 0000000..1ff4c85 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_34.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = ashr i64 %0, %0 + %3 = sdiv i64 %2, %2 + %4 = xor i64 %2, %3 + ret i64 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_35.mlir b/benchmarks/LLVMIR/3_function_35.mlir new file mode 100644 index 0000000..46bda64 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_35.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv exact i64 %0, %1 + %5 = xor i64 %4, %2 + %6 = icmp ult i64 %0, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_36.mlir b/benchmarks/LLVMIR/3_function_36.mlir new file mode 100644 index 0000000..6acfcc0 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_36.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_37.mlir b/benchmarks/LLVMIR/3_function_37.mlir new file mode 100644 index 0000000..43addef --- /dev/null +++ b/benchmarks/LLVMIR/3_function_37.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_38.mlir b/benchmarks/LLVMIR/3_function_38.mlir new file mode 100644 index 0000000..0ede607 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_38.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = icmp sle i64 %3, %0 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_39.mlir b/benchmarks/LLVMIR/3_function_39.mlir new file mode 100644 index 0000000..7916263 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_39.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %2 + %5 = select i1 %0, i64 %1, i64 %4 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_4.mlir b/benchmarks/LLVMIR/3_function_4.mlir new file mode 100644 index 0000000..7b0003c --- /dev/null +++ b/benchmarks/LLVMIR/3_function_4.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = xor i64 %0, %0 + %4 = xor i64 %3, %1 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_40.mlir b/benchmarks/LLVMIR/3_function_40.mlir new file mode 100644 index 0000000..6e68655 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_40.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = and i64 %0, %0 + %4 = or i64 %1, %0 + %5 = srem i64 %3, %4 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_41.mlir b/benchmarks/LLVMIR/3_function_41.mlir new file mode 100644 index 0000000..8b372d4 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_41.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_42.mlir b/benchmarks/LLVMIR/3_function_42.mlir new file mode 100644 index 0000000..33f92d0 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_42.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_43.mlir b/benchmarks/LLVMIR/3_function_43.mlir new file mode 100644 index 0000000..0250440 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_43.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %1, %2 + %5 = xor i64 %0, %4 + %6 = and i64 %5, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_44.mlir b/benchmarks/LLVMIR/3_function_44.mlir new file mode 100644 index 0000000..e3ef83c --- /dev/null +++ b/benchmarks/LLVMIR/3_function_44.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = ashr exact i64 %1, %4 + %6 = lshr i64 %4, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_45.mlir b/benchmarks/LLVMIR/3_function_45.mlir new file mode 100644 index 0000000..0866afb --- /dev/null +++ b/benchmarks/LLVMIR/3_function_45.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = ashr i64 %0, %0 + %3 = srem i64 %2, %0 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_46.mlir b/benchmarks/LLVMIR/3_function_46.mlir new file mode 100644 index 0000000..56343d2 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_46.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr i64 %0, %1 + %5 = sdiv i64 %2, %4 + %6 = icmp eq i64 %4, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_47.mlir b/benchmarks/LLVMIR/3_function_47.mlir new file mode 100644 index 0000000..b4fdc17 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_47.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = sdiv exact i64 %2, %2 + %6 = urem i64 %4, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_48.mlir b/benchmarks/LLVMIR/3_function_48.mlir new file mode 100644 index 0000000..db17744 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_48.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_49.mlir b/benchmarks/LLVMIR/3_function_49.mlir new file mode 100644 index 0000000..e98c55f --- /dev/null +++ b/benchmarks/LLVMIR/3_function_49.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = sdiv i64 %0, %0 + %4 = xor i64 %3, %1 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_5.mlir b/benchmarks/LLVMIR/3_function_5.mlir new file mode 100644 index 0000000..c24b363 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_5.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %1, %2 + %5 = ashr exact i64 %0, %4 + %6 = icmp ne i64 %5, %1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_50.mlir b/benchmarks/LLVMIR/3_function_50.mlir new file mode 100644 index 0000000..a62f128 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_50.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = udiv i64 %0, %0 + %3 = or i64 %2, %0 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_51.mlir b/benchmarks/LLVMIR/3_function_51.mlir new file mode 100644 index 0000000..8416359 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_51.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_52.mlir b/benchmarks/LLVMIR/3_function_52.mlir new file mode 100644 index 0000000..db17744 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_52.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_53.mlir b/benchmarks/LLVMIR/3_function_53.mlir new file mode 100644 index 0000000..7d3dafa --- /dev/null +++ b/benchmarks/LLVMIR/3_function_53.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %0 + %4 = srem i64 %0, %3 + %5 = sdiv i64 %4, %1 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_54.mlir b/benchmarks/LLVMIR/3_function_54.mlir new file mode 100644 index 0000000..2b042fd --- /dev/null +++ b/benchmarks/LLVMIR/3_function_54.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = icmp sge i64 %0, %0 + %3 = select i1 %2, i64 %0, i64 %0 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_55.mlir b/benchmarks/LLVMIR/3_function_55.mlir new file mode 100644 index 0000000..76cc0be --- /dev/null +++ b/benchmarks/LLVMIR/3_function_55.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = urem i64 %1, %0 + %4 = and i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_56.mlir b/benchmarks/LLVMIR/3_function_56.mlir new file mode 100644 index 0000000..6acfcc0 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_56.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_57.mlir b/benchmarks/LLVMIR/3_function_57.mlir new file mode 100644 index 0000000..2955bc5 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_57.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %1 to i1 + %5 = select i1 %4, i64 %2, i64 %2 + %6 = icmp ule i64 %0, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_58.mlir b/benchmarks/LLVMIR/3_function_58.mlir new file mode 100644 index 0000000..bdbd6d1 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_58.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = icmp ule i64 %4, %1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_59.mlir b/benchmarks/LLVMIR/3_function_59.mlir new file mode 100644 index 0000000..03e413a --- /dev/null +++ b/benchmarks/LLVMIR/3_function_59.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = xor i64 %1, %0 + %4 = ashr i64 %0, %3 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_6.mlir b/benchmarks/LLVMIR/3_function_6.mlir new file mode 100644 index 0000000..8416359 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_6.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_60.mlir b/benchmarks/LLVMIR/3_function_60.mlir new file mode 100644 index 0000000..f71b3e4 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_60.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = sdiv exact i64 %1, %0 + %4 = xor i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_61.mlir b/benchmarks/LLVMIR/3_function_61.mlir new file mode 100644 index 0000000..30d4759 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_61.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = urem i64 %0, %0 + %4 = sdiv exact i64 %0, %3 + %5 = sdiv exact i64 %4, %1 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_62.mlir b/benchmarks/LLVMIR/3_function_62.mlir new file mode 100644 index 0000000..58508bb --- /dev/null +++ b/benchmarks/LLVMIR/3_function_62.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = sdiv i64 %0, %0 + %4 = lshr i64 %3, %1 + %5 = urem i64 %4, %3 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_63.mlir b/benchmarks/LLVMIR/3_function_63.mlir new file mode 100644 index 0000000..6acfcc0 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_63.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_64.mlir b/benchmarks/LLVMIR/3_function_64.mlir new file mode 100644 index 0000000..2c55ab8 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_64.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %0 + %4 = ashr exact i64 %3, %1 + %5 = lshr exact i64 %3, %4 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_65.mlir b/benchmarks/LLVMIR/3_function_65.mlir new file mode 100644 index 0000000..80500c7 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_65.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = ashr exact i64 %0, %1 + %4 = urem i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_66.mlir b/benchmarks/LLVMIR/3_function_66.mlir new file mode 100644 index 0000000..29a7d15 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_66.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i32 %2) { + %4 = lshr exact i64 %0, %1 + %5 = zext i32 %2 to i64 + %6 = ashr i64 %4, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_67.mlir b/benchmarks/LLVMIR/3_function_67.mlir new file mode 100644 index 0000000..3c921eb --- /dev/null +++ b/benchmarks/LLVMIR/3_function_67.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = ashr i64 %0, %0 + %4 = or disjoint i64 %1, %3 + %5 = udiv i64 %3, %4 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_68.mlir b/benchmarks/LLVMIR/3_function_68.mlir new file mode 100644 index 0000000..e93d68f --- /dev/null +++ b/benchmarks/LLVMIR/3_function_68.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %2 + %5 = and i64 %0, %4 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_69.mlir b/benchmarks/LLVMIR/3_function_69.mlir new file mode 100644 index 0000000..9202dd5 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_69.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = xor i64 %4, %2 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_7.mlir b/benchmarks/LLVMIR/3_function_7.mlir new file mode 100644 index 0000000..f4a2374 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_7.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %2, %2 + %5 = lshr exact i64 %1, %4 + %6 = lshr i64 %0, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_70.mlir b/benchmarks/LLVMIR/3_function_70.mlir new file mode 100644 index 0000000..ecdb11d --- /dev/null +++ b/benchmarks/LLVMIR/3_function_70.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr i64 %0, %1 + %5 = ashr i64 %4, %2 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_71.mlir b/benchmarks/LLVMIR/3_function_71.mlir new file mode 100644 index 0000000..884b410 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_71.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0) { + %2 = sext i32 %0 to i64 + %3 = srem i64 %2, %2 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_72.mlir b/benchmarks/LLVMIR/3_function_72.mlir new file mode 100644 index 0000000..0be420e --- /dev/null +++ b/benchmarks/LLVMIR/3_function_72.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1) { + %3 = zext i32 %1 to i64 + %4 = xor i64 %3, %3 + %5 = icmp sle i64 %0, %4 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_73.mlir b/benchmarks/LLVMIR/3_function_73.mlir new file mode 100644 index 0000000..fdfd143 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_73.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = and i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = zext i32 %3 to i64 + ret i64 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_74.mlir b/benchmarks/LLVMIR/3_function_74.mlir new file mode 100644 index 0000000..46cb2dd --- /dev/null +++ b/benchmarks/LLVMIR/3_function_74.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = ashr exact i64 %1, %1 + %4 = ashr i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_75.mlir b/benchmarks/LLVMIR/3_function_75.mlir new file mode 100644 index 0000000..ba60aca --- /dev/null +++ b/benchmarks/LLVMIR/3_function_75.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = sdiv exact i64 %0, %0 + %4 = ashr i64 %3, %1 + %5 = srem i64 %3, %4 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_76.mlir b/benchmarks/LLVMIR/3_function_76.mlir new file mode 100644 index 0000000..7534d71 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_76.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1) { + %3 = zext i32 %1 to i64 + %4 = or i64 %0, %3 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_77.mlir b/benchmarks/LLVMIR/3_function_77.mlir new file mode 100644 index 0000000..8f7c3fd --- /dev/null +++ b/benchmarks/LLVMIR/3_function_77.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = and i64 %0, %0 + %3 = lshr i64 %0, %0 + %4 = icmp ule i64 %2, %3 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_78.mlir b/benchmarks/LLVMIR/3_function_78.mlir new file mode 100644 index 0000000..1175d39 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_78.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0, i64 %1) { + %3 = zext i32 %0 to i64 + %4 = and i64 %3, %1 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_79.mlir b/benchmarks/LLVMIR/3_function_79.mlir new file mode 100644 index 0000000..753ac5f --- /dev/null +++ b/benchmarks/LLVMIR/3_function_79.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0, i64 %1) { + %3 = zext i32 %0 to i64 + %4 = urem i64 %3, %1 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_8.mlir b/benchmarks/LLVMIR/3_function_8.mlir new file mode 100644 index 0000000..f71c2bb --- /dev/null +++ b/benchmarks/LLVMIR/3_function_8.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %0 + %5 = xor i64 %1, %2 + %6 = icmp sge i64 %4, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_80.mlir b/benchmarks/LLVMIR/3_function_80.mlir new file mode 100644 index 0000000..f40c5a5 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_80.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0, i64 %1) { + %3 = zext i32 %0 to i64 + %4 = sdiv i64 %3, %3 + %5 = icmp sge i64 %4, %1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_81.mlir b/benchmarks/LLVMIR/3_function_81.mlir new file mode 100644 index 0000000..e4ff836 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_81.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp sge i64 %0, %1 + %5 = select i1 %4, i64 %2, i64 %0 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_82.mlir b/benchmarks/LLVMIR/3_function_82.mlir new file mode 100644 index 0000000..dcdce02 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_82.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %1, %2 + %5 = lshr i64 %0, %4 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_83.mlir b/benchmarks/LLVMIR/3_function_83.mlir new file mode 100644 index 0000000..07b43ff --- /dev/null +++ b/benchmarks/LLVMIR/3_function_83.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp ule i64 %0, %1 + %5 = select i1 %4, i64 %1, i64 %2 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_84.mlir b/benchmarks/LLVMIR/3_function_84.mlir new file mode 100644 index 0000000..dadf115 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_84.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = srem i64 %4, %1 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_85.mlir b/benchmarks/LLVMIR/3_function_85.mlir new file mode 100644 index 0000000..a3889d3 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_85.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = and i64 %0, %0 + %3 = or i64 %0, %2 + %4 = sdiv exact i64 %0, %3 + ret i64 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_86.mlir b/benchmarks/LLVMIR/3_function_86.mlir new file mode 100644 index 0000000..1f44be4 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_86.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i32 %1, i64 %2) { + %4 = zext i32 %1 to i64 + %5 = select i1 %0, i64 %4, i64 %2 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_87.mlir b/benchmarks/LLVMIR/3_function_87.mlir new file mode 100644 index 0000000..316334e --- /dev/null +++ b/benchmarks/LLVMIR/3_function_87.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp ugt i64 %0, %1 + %5 = select i1 %4, i64 %0, i64 %2 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_88.mlir b/benchmarks/LLVMIR/3_function_88.mlir new file mode 100644 index 0000000..30e1bf4 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_88.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0) { + %2 = zext i32 %0 to i64 + %3 = udiv i64 %2, %2 + %4 = trunc i64 %3 to i32 + ret i32 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_89.mlir b/benchmarks/LLVMIR/3_function_89.mlir new file mode 100644 index 0000000..80a2d44 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_89.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_9.mlir b/benchmarks/LLVMIR/3_function_9.mlir new file mode 100644 index 0000000..e63ad24 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_9.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = icmp ne i64 %0, %0 + %3 = select i1 %2, i64 %0, i64 %0 + %4 = icmp sle i64 %3, %0 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_90.mlir b/benchmarks/LLVMIR/3_function_90.mlir new file mode 100644 index 0000000..6cc3d3b --- /dev/null +++ b/benchmarks/LLVMIR/3_function_90.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = srem i64 %1, %1 + %4 = xor i64 %0, %3 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_91.mlir b/benchmarks/LLVMIR/3_function_91.mlir new file mode 100644 index 0000000..f7179e2 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_91.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = urem i64 %0, %1 + %4 = udiv i64 %0, %3 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_92.mlir b/benchmarks/LLVMIR/3_function_92.mlir new file mode 100644 index 0000000..c289e7e --- /dev/null +++ b/benchmarks/LLVMIR/3_function_92.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = urem i64 %0, %0 + %3 = ashr exact i64 %2, %0 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_93.mlir b/benchmarks/LLVMIR/3_function_93.mlir new file mode 100644 index 0000000..d308fd6 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_93.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp ule i64 %0, %1 + %5 = select i1 %4, i64 %2, i64 %0 + %6 = icmp sge i64 %0, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_94.mlir b/benchmarks/LLVMIR/3_function_94.mlir new file mode 100644 index 0000000..e23e16f --- /dev/null +++ b/benchmarks/LLVMIR/3_function_94.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1) { + %3 = zext i32 %1 to i64 + %4 = xor i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_95.mlir b/benchmarks/LLVMIR/3_function_95.mlir new file mode 100644 index 0000000..459aa57 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_95.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = and i64 %1, %0 + %4 = sdiv i64 %0, %3 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_96.mlir b/benchmarks/LLVMIR/3_function_96.mlir new file mode 100644 index 0000000..2fe9048 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_96.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i32 %2) { + %4 = srem i64 %0, %1 + %5 = sext i32 %2 to i64 + %6 = udiv i64 %4, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_97.mlir b/benchmarks/LLVMIR/3_function_97.mlir new file mode 100644 index 0000000..2f7ee90 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_97.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i1 + %4 = or i64 %1, %0 + %5 = select i1 %3, i64 %0, i64 %4 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_98.mlir b/benchmarks/LLVMIR/3_function_98.mlir new file mode 100644 index 0000000..8416359 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_98.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i1 + ret i1 %4 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/3_function_99.mlir b/benchmarks/LLVMIR/3_function_99.mlir new file mode 100644 index 0000000..e8baf51 --- /dev/null +++ b/benchmarks/LLVMIR/3_function_99.mlir @@ -0,0 +1,13 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1) { + %3 = sdiv i64 %1, %1 + %4 = select i1 %0, i64 %3, i64 %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_0.mlir b/benchmarks/LLVMIR/4_function_0.mlir new file mode 100644 index 0000000..3203f93 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_0.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = and i64 %0, %4 + %6 = lshr exact i64 %5, %2 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_1.mlir b/benchmarks/LLVMIR/4_function_1.mlir new file mode 100644 index 0000000..537e594 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_1.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = srem i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = zext i32 %3 to i64 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_10.mlir b/benchmarks/LLVMIR/4_function_10.mlir new file mode 100644 index 0000000..71f63f3 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_10.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = sdiv exact i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_11.mlir b/benchmarks/LLVMIR/4_function_11.mlir new file mode 100644 index 0000000..bda6355 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_11.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = sdiv exact i64 %4, %1 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_12.mlir b/benchmarks/LLVMIR/4_function_12.mlir new file mode 100644 index 0000000..c67f7d7 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_12.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = and i64 %0, %0 + %5 = icmp ule i64 %3, %4 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_13.mlir b/benchmarks/LLVMIR/4_function_13.mlir new file mode 100644 index 0000000..a1d182c --- /dev/null +++ b/benchmarks/LLVMIR/4_function_13.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = sdiv exact i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = sext i32 %3 to i64 + %5 = icmp ugt i64 %0, %4 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_14.mlir b/benchmarks/LLVMIR/4_function_14.mlir new file mode 100644 index 0000000..83be14d --- /dev/null +++ b/benchmarks/LLVMIR/4_function_14.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = urem i64 %0, %4 + %6 = udiv i64 %2, %5 + %7 = urem i64 %4, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_15.mlir b/benchmarks/LLVMIR/4_function_15.mlir new file mode 100644 index 0000000..2edb23b --- /dev/null +++ b/benchmarks/LLVMIR/4_function_15.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %1 + %5 = urem i64 %4, %2 + %6 = lshr exact i64 %5, %1 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_16.mlir b/benchmarks/LLVMIR/4_function_16.mlir new file mode 100644 index 0000000..4430073 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_16.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %1, %2 + %5 = xor i64 %0, %4 + %6 = srem i64 %5, %0 + %7 = icmp ule i64 %5, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_17.mlir b/benchmarks/LLVMIR/4_function_17.mlir new file mode 100644 index 0000000..f2301ae --- /dev/null +++ b/benchmarks/LLVMIR/4_function_17.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i32 %2) { + %4 = sext i32 %2 to i64 + %5 = udiv i64 %4, %1 + %6 = select i1 %0, i64 %1, i64 %5 + %7 = srem i64 %6, %1 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_18.mlir b/benchmarks/LLVMIR/4_function_18.mlir new file mode 100644 index 0000000..d0eb9e6 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_18.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %1, %1 + %5 = xor i64 %2, %1 + %6 = or disjoint i64 %4, %5 + %7 = urem i64 %0, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_19.mlir b/benchmarks/LLVMIR/4_function_19.mlir new file mode 100644 index 0000000..738a5f6 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_19.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = zext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_2.mlir b/benchmarks/LLVMIR/4_function_2.mlir new file mode 100644 index 0000000..2e4b647 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_2.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = ashr i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = sext i32 %3 to i64 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_20.mlir b/benchmarks/LLVMIR/4_function_20.mlir new file mode 100644 index 0000000..f3584e4 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_20.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2, i32 %3) { + %5 = xor i64 %2, %2 + %6 = zext i32 %3 to i64 + %7 = select i1 %1, i64 %5, i64 %6 + %8 = ashr exact i64 %0, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_21.mlir b/benchmarks/LLVMIR/4_function_21.mlir new file mode 100644 index 0000000..9cb9f6e --- /dev/null +++ b/benchmarks/LLVMIR/4_function_21.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv exact i64 %1, %1 + %5 = udiv i64 %2, %4 + %6 = ashr exact i64 %1, %5 + %7 = icmp sgt i64 %0, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_22.mlir b/benchmarks/LLVMIR/4_function_22.mlir new file mode 100644 index 0000000..dc2bc6c --- /dev/null +++ b/benchmarks/LLVMIR/4_function_22.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %1 + %4 = lshr i64 %3, %3 + %5 = urem i64 %4, %1 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_23.mlir b/benchmarks/LLVMIR/4_function_23.mlir new file mode 100644 index 0000000..32000f1 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_23.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i32 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = zext i32 %1 to i64 + %6 = or disjoint i64 %5, %2 + %7 = urem i64 %4, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_24.mlir b/benchmarks/LLVMIR/4_function_24.mlir new file mode 100644 index 0000000..22e3f4c --- /dev/null +++ b/benchmarks/LLVMIR/4_function_24.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %0, %0 + %5 = srem i64 %4, %1 + %6 = trunc i64 %5 to i1 + %7 = select i1 %6, i64 %2, i64 %4 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_25.mlir b/benchmarks/LLVMIR/4_function_25.mlir new file mode 100644 index 0000000..cf32bff --- /dev/null +++ b/benchmarks/LLVMIR/4_function_25.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = ashr exact i64 %0, %2 + %5 = select i1 %1, i64 %4, i64 %2 + %6 = lshr exact i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_26.mlir b/benchmarks/LLVMIR/4_function_26.mlir new file mode 100644 index 0000000..35fb09a --- /dev/null +++ b/benchmarks/LLVMIR/4_function_26.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = icmp eq i64 %4, %2 + %6 = select i1 %5, i64 %2, i64 %1 + %7 = xor i64 %4, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_27.mlir b/benchmarks/LLVMIR/4_function_27.mlir new file mode 100644 index 0000000..dac4983 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_27.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = and i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = sext i32 %3 to i64 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_28.mlir b/benchmarks/LLVMIR/4_function_28.mlir new file mode 100644 index 0000000..8079382 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_28.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1) { + %3 = zext i32 %0 to i64 + %4 = srem i64 %1, %1 + %5 = or i64 %3, %4 + %6 = sdiv i64 %3, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_29.mlir b/benchmarks/LLVMIR/4_function_29.mlir new file mode 100644 index 0000000..15047df --- /dev/null +++ b/benchmarks/LLVMIR/4_function_29.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv exact i64 %1, %2 + %5 = srem i64 %0, %4 + %6 = xor i64 %5, %0 + %7 = icmp slt i64 %5, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_3.mlir b/benchmarks/LLVMIR/4_function_3.mlir new file mode 100644 index 0000000..8e973da --- /dev/null +++ b/benchmarks/LLVMIR/4_function_3.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = trunc i64 %2 to i1 + %6 = select i1 %5, i64 %4, i64 %0 + %7 = lshr i64 %4, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_30.mlir b/benchmarks/LLVMIR/4_function_30.mlir new file mode 100644 index 0000000..31ad633 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_30.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = icmp ule i64 %6, %2 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_31.mlir b/benchmarks/LLVMIR/4_function_31.mlir new file mode 100644 index 0000000..0c36ff0 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_31.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = ashr i64 %4, %2 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_32.mlir b/benchmarks/LLVMIR/4_function_32.mlir new file mode 100644 index 0000000..8126f50 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_32.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i32 %2) { + %4 = sext i32 %2 to i64 + %5 = select i1 %1, i64 %4, i64 %0 + %6 = urem i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_33.mlir b/benchmarks/LLVMIR/4_function_33.mlir new file mode 100644 index 0000000..399862f --- /dev/null +++ b/benchmarks/LLVMIR/4_function_33.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp eq i64 %1, %2 + %5 = select i1 %4, i64 %0, i64 %0 + %6 = xor i64 %0, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_34.mlir b/benchmarks/LLVMIR/4_function_34.mlir new file mode 100644 index 0000000..c42e862 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_34.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %0 + %4 = ashr exact i64 %3, %1 + %5 = or i64 %3, %4 + %6 = lshr i64 %3, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_35.mlir b/benchmarks/LLVMIR/4_function_35.mlir new file mode 100644 index 0000000..12444dc --- /dev/null +++ b/benchmarks/LLVMIR/4_function_35.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_36.mlir b/benchmarks/LLVMIR/4_function_36.mlir new file mode 100644 index 0000000..b420ac7 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_36.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %0, %1 + %5 = urem i64 %2, %2 + %6 = xor i64 %5, %0 + %7 = urem i64 %4, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_37.mlir b/benchmarks/LLVMIR/4_function_37.mlir new file mode 100644 index 0000000..018c9f2 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_37.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = srem i64 %1, %0 + %4 = and i64 %0, %3 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_38.mlir b/benchmarks/LLVMIR/4_function_38.mlir new file mode 100644 index 0000000..125de25 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_38.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1) { + %3 = sext i32 %1 to i64 + %4 = or disjoint i64 %0, %3 + %5 = urem i64 %0, %4 + %6 = icmp ule i64 %5, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_39.mlir b/benchmarks/LLVMIR/4_function_39.mlir new file mode 100644 index 0000000..8ee5b9d --- /dev/null +++ b/benchmarks/LLVMIR/4_function_39.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %2, %1 + %5 = or disjoint i64 %1, %4 + %6 = urem i64 %0, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_4.mlir b/benchmarks/LLVMIR/4_function_4.mlir new file mode 100644 index 0000000..f0ad784 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_4.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i32 %2) { + %4 = or disjoint i64 %0, %1 + %5 = zext i32 %2 to i64 + %6 = xor i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_40.mlir b/benchmarks/LLVMIR/4_function_40.mlir new file mode 100644 index 0000000..5950b68 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_40.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %2, i64 %0 + %5 = udiv i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_41.mlir b/benchmarks/LLVMIR/4_function_41.mlir new file mode 100644 index 0000000..6c5d289 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_41.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %1, %0 + %5 = srem i64 %4, %2 + %6 = srem i64 %0, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_42.mlir b/benchmarks/LLVMIR/4_function_42.mlir new file mode 100644 index 0000000..b6345ee --- /dev/null +++ b/benchmarks/LLVMIR/4_function_42.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i1 %1, i64 %2) { + %4 = zext i32 %0 to i64 + %5 = srem i64 %4, %2 + %6 = select i1 %1, i64 %5, i64 %5 + %7 = and i64 %4, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_43.mlir b/benchmarks/LLVMIR/4_function_43.mlir new file mode 100644 index 0000000..e18abb7 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_43.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1) { + %3 = select i1 %1, i64 %0, i64 %0 + %4 = urem i64 %3, %0 + %5 = or i64 %0, %4 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_44.mlir b/benchmarks/LLVMIR/4_function_44.mlir new file mode 100644 index 0000000..3b6e487 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_44.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i32 %1) { + %3 = sext i32 %0 to i64 + %4 = srem i64 %3, %3 + %5 = sext i32 %1 to i64 + %6 = urem i64 %4, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_45.mlir b/benchmarks/LLVMIR/4_function_45.mlir new file mode 100644 index 0000000..6fe755f --- /dev/null +++ b/benchmarks/LLVMIR/4_function_45.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i1 %2) { + %4 = or disjoint i64 %0, %1 + %5 = select i1 %2, i64 %0, i64 %4 + %6 = lshr i64 %4, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_46.mlir b/benchmarks/LLVMIR/4_function_46.mlir new file mode 100644 index 0000000..1cd43c8 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_46.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = or i64 %0, %0 + %5 = or disjoint i64 %0, %1 + %6 = xor i64 %5, %2 + %7 = icmp ule i64 %4, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_47.mlir b/benchmarks/LLVMIR/4_function_47.mlir new file mode 100644 index 0000000..ac06b89 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_47.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = srem i64 %0, %0 + %3 = urem i64 %0, %2 + %4 = ashr exact i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_48.mlir b/benchmarks/LLVMIR/4_function_48.mlir new file mode 100644 index 0000000..1a209f4 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_48.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0) { + %2 = zext i32 %0 to i64 + %3 = trunc i64 %2 to i32 + %4 = zext i32 %3 to i64 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_49.mlir b/benchmarks/LLVMIR/4_function_49.mlir new file mode 100644 index 0000000..205ff3f --- /dev/null +++ b/benchmarks/LLVMIR/4_function_49.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %2 + %5 = lshr exact i64 %1, %4 + %6 = lshr exact i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_5.mlir b/benchmarks/LLVMIR/4_function_5.mlir new file mode 100644 index 0000000..7fde0d9 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_5.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1, i64 %2) { + %4 = ashr i64 %0, %0 + %5 = select i1 %1, i64 %2, i64 %2 + %6 = ashr i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_50.mlir b/benchmarks/LLVMIR/4_function_50.mlir new file mode 100644 index 0000000..5245bea --- /dev/null +++ b/benchmarks/LLVMIR/4_function_50.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = and i64 %0, %0 + %3 = ashr i64 %0, %2 + %4 = or disjoint i64 %3, %2 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_51.mlir b/benchmarks/LLVMIR/4_function_51.mlir new file mode 100644 index 0000000..266dbed --- /dev/null +++ b/benchmarks/LLVMIR/4_function_51.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0, i64 %1) { + %3 = zext i32 %0 to i64 + %4 = lshr i64 %1, %3 + %5 = udiv i64 %3, %4 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_52.mlir b/benchmarks/LLVMIR/4_function_52.mlir new file mode 100644 index 0000000..141cf3a --- /dev/null +++ b/benchmarks/LLVMIR/4_function_52.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %0 + %5 = xor i64 %0, %1 + %6 = lshr exact i64 %5, %2 + %7 = icmp sgt i64 %4, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_53.mlir b/benchmarks/LLVMIR/4_function_53.mlir new file mode 100644 index 0000000..d051440 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_53.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = and i64 %0, %0 + %4 = ashr i64 %0, %3 + %5 = sdiv exact i64 %4, %1 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_54.mlir b/benchmarks/LLVMIR/4_function_54.mlir new file mode 100644 index 0000000..fa522c3 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_54.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %2 + %5 = udiv i64 %1, %4 + %6 = urem i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_55.mlir b/benchmarks/LLVMIR/4_function_55.mlir new file mode 100644 index 0000000..decf171 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_55.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = urem i64 %2, %0 + %6 = udiv i64 %4, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_56.mlir b/benchmarks/LLVMIR/4_function_56.mlir new file mode 100644 index 0000000..a84986f --- /dev/null +++ b/benchmarks/LLVMIR/4_function_56.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = lshr exact i64 %0, %2 + %5 = select i1 %1, i64 %2, i64 %4 + %6 = udiv i64 %5, %4 + %7 = srem i64 %0, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_57.mlir b/benchmarks/LLVMIR/4_function_57.mlir new file mode 100644 index 0000000..1e6c01d --- /dev/null +++ b/benchmarks/LLVMIR/4_function_57.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = or i64 %5, %1 + %7 = or disjoint i64 %6, %2 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_58.mlir b/benchmarks/LLVMIR/4_function_58.mlir new file mode 100644 index 0000000..5c5d7c8 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_58.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = xor i64 %0, %2 + %6 = sdiv i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_59.mlir b/benchmarks/LLVMIR/4_function_59.mlir new file mode 100644 index 0000000..1d4b34b --- /dev/null +++ b/benchmarks/LLVMIR/4_function_59.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = ashr exact i64 %3, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_6.mlir b/benchmarks/LLVMIR/4_function_6.mlir new file mode 100644 index 0000000..12752d8 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_6.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i32 %2) { + %4 = zext i32 %2 to i64 + %5 = lshr i64 %1, %4 + %6 = select i1 %0, i64 %5, i64 %5 + %7 = or disjoint i64 %6, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_60.mlir b/benchmarks/LLVMIR/4_function_60.mlir new file mode 100644 index 0000000..12444dc --- /dev/null +++ b/benchmarks/LLVMIR/4_function_60.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_61.mlir b/benchmarks/LLVMIR/4_function_61.mlir new file mode 100644 index 0000000..fc5831a --- /dev/null +++ b/benchmarks/LLVMIR/4_function_61.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = or i64 %0, %1 + %4 = sdiv exact i64 %3, %0 + %5 = or i64 %4, %4 + %6 = or disjoint i64 %5, %0 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_62.mlir b/benchmarks/LLVMIR/4_function_62.mlir new file mode 100644 index 0000000..dbae42a --- /dev/null +++ b/benchmarks/LLVMIR/4_function_62.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr exact i64 %2, %0 + %5 = udiv i64 %1, %4 + %6 = urem i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_63.mlir b/benchmarks/LLVMIR/4_function_63.mlir new file mode 100644 index 0000000..50536c3 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_63.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = ashr exact i64 %2, %2 + %6 = srem i64 %1, %5 + %7 = icmp ne i64 %4, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_64.mlir b/benchmarks/LLVMIR/4_function_64.mlir new file mode 100644 index 0000000..918cee9 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_64.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = trunc i64 %1 to i32 + %5 = zext i32 %4 to i64 + %6 = ashr exact i64 %5, %2 + %7 = select i1 %0, i64 %6, i64 %1 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_65.mlir b/benchmarks/LLVMIR/4_function_65.mlir new file mode 100644 index 0000000..f67c796 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_65.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = srem i64 %0, %0 + %3 = urem i64 %0, %2 + %4 = xor i64 %3, %3 + %5 = icmp ult i64 %3, %4 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_66.mlir b/benchmarks/LLVMIR/4_function_66.mlir new file mode 100644 index 0000000..2176d7b --- /dev/null +++ b/benchmarks/LLVMIR/4_function_66.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_67.mlir b/benchmarks/LLVMIR/4_function_67.mlir new file mode 100644 index 0000000..a3a9222 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_67.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = sdiv i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = zext i32 %3 to i64 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_68.mlir b/benchmarks/LLVMIR/4_function_68.mlir new file mode 100644 index 0000000..1951142 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_68.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_69.mlir b/benchmarks/LLVMIR/4_function_69.mlir new file mode 100644 index 0000000..dcce221 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_69.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1) { + %3 = urem i64 %1, %1 + %4 = ashr exact i64 %1, %3 + %5 = lshr i64 %4, %1 + %6 = select i1 %0, i64 %5, i64 %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_7.mlir b/benchmarks/LLVMIR/4_function_7.mlir new file mode 100644 index 0000000..8a68178 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_7.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = icmp sgt i64 %0, %4 + %6 = udiv i64 %4, %4 + %7 = select i1 %5, i64 %2, i64 %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_70.mlir b/benchmarks/LLVMIR/4_function_70.mlir new file mode 100644 index 0000000..56b1eb4 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_70.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i32 %1) { + %3 = udiv i64 %0, %0 + %4 = ashr i64 %3, %0 + %5 = zext i32 %1 to i64 + %6 = xor i64 %4, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_71.mlir b/benchmarks/LLVMIR/4_function_71.mlir new file mode 100644 index 0000000..7dbfe08 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_71.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = ashr exact i64 %0, %0 + %4 = lshr i64 %3, %1 + %5 = sdiv i64 %0, %0 + %6 = udiv i64 %4, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_72.mlir b/benchmarks/LLVMIR/4_function_72.mlir new file mode 100644 index 0000000..973484e --- /dev/null +++ b/benchmarks/LLVMIR/4_function_72.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %0, %1 + %5 = ashr exact i64 %4, %2 + %6 = lshr exact i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_73.mlir b/benchmarks/LLVMIR/4_function_73.mlir new file mode 100644 index 0000000..a915187 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_73.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %1 to i1 + %5 = select i1 %4, i64 %2, i64 %2 + %6 = xor i64 %0, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_74.mlir b/benchmarks/LLVMIR/4_function_74.mlir new file mode 100644 index 0000000..84d9e8f --- /dev/null +++ b/benchmarks/LLVMIR/4_function_74.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp ult i64 %0, %1 + %5 = select i1 %4, i64 %1, i64 %0 + %6 = trunc i64 %5 to i1 + %7 = select i1 %6, i64 %2, i64 %5 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_75.mlir b/benchmarks/LLVMIR/4_function_75.mlir new file mode 100644 index 0000000..55ede56 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_75.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i32 %2) { + %4 = select i1 %0, i64 %1, i64 %1 + %5 = zext i32 %2 to i64 + %6 = icmp eq i64 %4, %5 + %7 = select i1 %6, i64 %1, i64 %4 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_76.mlir b/benchmarks/LLVMIR/4_function_76.mlir new file mode 100644 index 0000000..34e8b03 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_76.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %1 to i32 + %4 = zext i32 %3 to i64 + %5 = lshr exact i64 %0, %4 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_77.mlir b/benchmarks/LLVMIR/4_function_77.mlir new file mode 100644 index 0000000..ec48079 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_77.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = lshr exact i64 %0, %0 + %4 = trunc i64 %1 to i32 + %5 = sext i32 %4 to i64 + %6 = sdiv exact i64 %3, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_78.mlir b/benchmarks/LLVMIR/4_function_78.mlir new file mode 100644 index 0000000..4c2aa33 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_78.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = ashr exact i64 %4, %1 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_79.mlir b/benchmarks/LLVMIR/4_function_79.mlir new file mode 100644 index 0000000..537e594 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_79.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = srem i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = zext i32 %3 to i64 + %5 = trunc i64 %4 to i1 + ret i1 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_8.mlir b/benchmarks/LLVMIR/4_function_8.mlir new file mode 100644 index 0000000..c7517e6 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_8.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = icmp eq i64 %0, %1 + %4 = xor i64 %1, %0 + %5 = select i1 %3, i64 %4, i64 %4 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_80.mlir b/benchmarks/LLVMIR/4_function_80.mlir new file mode 100644 index 0000000..3af1e55 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_80.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = ashr exact i64 %0, %0 + %3 = urem i64 %0, %2 + %4 = and i64 %2, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_81.mlir b/benchmarks/LLVMIR/4_function_81.mlir new file mode 100644 index 0000000..72cce79 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_81.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = or disjoint i64 %2, %1 + %6 = xor i64 %4, %5 + %7 = srem i64 %6, %5 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_82.mlir b/benchmarks/LLVMIR/4_function_82.mlir new file mode 100644 index 0000000..c2578a3 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_82.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %0 + %4 = trunc i64 %1 to i32 + %5 = sext i32 %4 to i64 + %6 = xor i64 %3, %5 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_83.mlir b/benchmarks/LLVMIR/4_function_83.mlir new file mode 100644 index 0000000..b55de6b --- /dev/null +++ b/benchmarks/LLVMIR/4_function_83.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = sdiv exact i64 %4, %1 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_84.mlir b/benchmarks/LLVMIR/4_function_84.mlir new file mode 100644 index 0000000..b0e7f3b --- /dev/null +++ b/benchmarks/LLVMIR/4_function_84.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %1 to i32 + %4 = zext i32 %3 to i64 + %5 = urem i64 %0, %4 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_85.mlir b/benchmarks/LLVMIR/4_function_85.mlir new file mode 100644 index 0000000..112e165 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_85.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %1 + %4 = or i64 %3, %0 + %5 = lshr exact i64 %3, %4 + %6 = lshr i64 %5, %1 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_86.mlir b/benchmarks/LLVMIR/4_function_86.mlir new file mode 100644 index 0000000..cc4993f --- /dev/null +++ b/benchmarks/LLVMIR/4_function_86.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %0 + %4 = trunc i64 %3 to i1 + %5 = select i1 %4, i64 %0, i64 %1 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_87.mlir b/benchmarks/LLVMIR/4_function_87.mlir new file mode 100644 index 0000000..9f5eced --- /dev/null +++ b/benchmarks/LLVMIR/4_function_87.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = and i64 %0, %3 + %5 = trunc i64 %4 to i32 + ret i32 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_88.mlir b/benchmarks/LLVMIR/4_function_88.mlir new file mode 100644 index 0000000..a3a5728 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_88.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %1 + %4 = and i64 %3, %1 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_89.mlir b/benchmarks/LLVMIR/4_function_89.mlir new file mode 100644 index 0000000..8e1bb89 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_89.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %1, %2 + %5 = xor i64 %0, %4 + %6 = or disjoint i64 %5, %2 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_9.mlir b/benchmarks/LLVMIR/4_function_9.mlir new file mode 100644 index 0000000..ebdf3db --- /dev/null +++ b/benchmarks/LLVMIR/4_function_9.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = or i64 %0, %1 + %5 = ashr exact i64 %2, %4 + %6 = sdiv exact i64 %2, %5 + %7 = icmp slt i64 %4, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_90.mlir b/benchmarks/LLVMIR/4_function_90.mlir new file mode 100644 index 0000000..a1d337b --- /dev/null +++ b/benchmarks/LLVMIR/4_function_90.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %1, %2 + %5 = urem i64 %4, %2 + %6 = xor i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_91.mlir b/benchmarks/LLVMIR/4_function_91.mlir new file mode 100644 index 0000000..71be196 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_91.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %1, %2 + %5 = or disjoint i64 %0, %4 + %6 = ashr i64 %1, %4 + %7 = sdiv i64 %5, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_92.mlir b/benchmarks/LLVMIR/4_function_92.mlir new file mode 100644 index 0000000..a84e260 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_92.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = sdiv exact i64 %4, %1 + %6 = and i64 %5, %2 + %7 = xor i64 %6, %5 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_93.mlir b/benchmarks/LLVMIR/4_function_93.mlir new file mode 100644 index 0000000..8b8c6fb --- /dev/null +++ b/benchmarks/LLVMIR/4_function_93.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = and i64 %0, %0 + %4 = xor i64 %1, %3 + %5 = or disjoint i64 %4, %0 + %6 = icmp ugt i64 %3, %5 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_94.mlir b/benchmarks/LLVMIR/4_function_94.mlir new file mode 100644 index 0000000..b3e2c68 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_94.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %0 + %5 = trunc i64 %1 to i1 + %6 = select i1 %5, i64 %2, i64 %4 + %7 = icmp ugt i64 %4, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_95.mlir b/benchmarks/LLVMIR/4_function_95.mlir new file mode 100644 index 0000000..232729e --- /dev/null +++ b/benchmarks/LLVMIR/4_function_95.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = urem i64 %1, %2 + %6 = and i64 %4, %5 + %7 = icmp ule i64 %6, %5 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_96.mlir b/benchmarks/LLVMIR/4_function_96.mlir new file mode 100644 index 0000000..8bcab1c --- /dev/null +++ b/benchmarks/LLVMIR/4_function_96.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1, i64 %2) { + %4 = zext i32 %1 to i64 + %5 = and i64 %0, %4 + %6 = lshr i64 %2, %2 + %7 = icmp slt i64 %5, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_97.mlir b/benchmarks/LLVMIR/4_function_97.mlir new file mode 100644 index 0000000..a6c7224 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_97.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = ashr i64 %0, %1 + %4 = srem i64 %0, %3 + %5 = ashr exact i64 %4, %0 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_98.mlir b/benchmarks/LLVMIR/4_function_98.mlir new file mode 100644 index 0000000..4148373 --- /dev/null +++ b/benchmarks/LLVMIR/4_function_98.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + %5 = zext i32 %4 to i64 + ret i64 %5 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/4_function_99.mlir b/benchmarks/LLVMIR/4_function_99.mlir new file mode 100644 index 0000000..f5a289d --- /dev/null +++ b/benchmarks/LLVMIR/4_function_99.mlir @@ -0,0 +1,14 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = or disjoint i64 %4, %1 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_0.mlir b/benchmarks/LLVMIR/5_function_0.mlir new file mode 100644 index 0000000..27ac0f4 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_0.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = urem i64 %4, %1 + %6 = sdiv i64 %4, %5 + %7 = urem i64 %6, %2 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_1.mlir b/benchmarks/LLVMIR/5_function_1.mlir new file mode 100644 index 0000000..16c4464 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_1.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0) { + %2 = zext i32 %0 to i64 + %3 = ashr exact i64 %2, %2 + %4 = zext i32 %0 to i64 + %5 = urem i64 %3, %4 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_10.mlir b/benchmarks/LLVMIR/5_function_10.mlir new file mode 100644 index 0000000..6ee4356 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_10.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = lshr exact i64 %4, %1 + %6 = srem i64 %5, %0 + %7 = urem i64 %4, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_11.mlir b/benchmarks/LLVMIR/5_function_11.mlir new file mode 100644 index 0000000..e7ccda2 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_11.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = sdiv i64 %1, %4 + %6 = sdiv i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_12.mlir b/benchmarks/LLVMIR/5_function_12.mlir new file mode 100644 index 0000000..ff3c099 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_12.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr exact i64 %1, %1 + %5 = sdiv i64 %0, %4 + %6 = icmp sgt i64 %5, %2 + %7 = select i1 %6, i64 %1, i64 %2 + %8 = icmp sle i64 %5, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_13.mlir b/benchmarks/LLVMIR/5_function_13.mlir new file mode 100644 index 0000000..5d0fdfe --- /dev/null +++ b/benchmarks/LLVMIR/5_function_13.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i32 %2) { + %4 = sdiv exact i64 %0, %1 + %5 = zext i32 %2 to i64 + %6 = lshr i64 %5, %4 + %7 = sdiv i64 %6, %5 + %8 = icmp slt i64 %4, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_14.mlir b/benchmarks/LLVMIR/5_function_14.mlir new file mode 100644 index 0000000..65d0df8 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_14.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp uge i64 %0, %0 + %5 = urem i64 %1, %0 + %6 = or disjoint i64 %5, %5 + %7 = urem i64 %2, %6 + %8 = select i1 %4, i64 %5, i64 %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_15.mlir b/benchmarks/LLVMIR/5_function_15.mlir new file mode 100644 index 0000000..84d616d --- /dev/null +++ b/benchmarks/LLVMIR/5_function_15.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = or i64 %0, %1 + %5 = icmp slt i64 %4, %0 + %6 = select i1 %5, i64 %2, i64 %0 + %7 = sdiv exact i64 %6, %2 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_16.mlir b/benchmarks/LLVMIR/5_function_16.mlir new file mode 100644 index 0000000..86d3191 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_16.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = udiv i64 %0, %0 + %3 = sdiv exact i64 %0, %2 + %4 = udiv i64 %3, %3 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_17.mlir b/benchmarks/LLVMIR/5_function_17.mlir new file mode 100644 index 0000000..374f846 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_17.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1) { + %3 = udiv i64 %0, %0 + %4 = or i64 %3, %0 + %5 = zext i32 %1 to i64 + %6 = ashr i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_18.mlir b/benchmarks/LLVMIR/5_function_18.mlir new file mode 100644 index 0000000..41074ef --- /dev/null +++ b/benchmarks/LLVMIR/5_function_18.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = ashr exact i64 %0, %0 + %4 = srem i64 %3, %1 + %5 = sdiv exact i64 %3, %4 + %6 = urem i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_19.mlir b/benchmarks/LLVMIR/5_function_19.mlir new file mode 100644 index 0000000..0eeec49 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_19.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i32 %2) { + %4 = or disjoint i64 %0, %1 + %5 = ashr exact i64 %0, %0 + %6 = urem i64 %4, %5 + %7 = zext i32 %2 to i64 + %8 = icmp ult i64 %6, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_2.mlir b/benchmarks/LLVMIR/5_function_2.mlir new file mode 100644 index 0000000..f65a301 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_2.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %1, %2 + %5 = udiv i64 %1, %4 + %6 = and i64 %4, %5 + %7 = ashr exact i64 %6, %1 + %8 = urem i64 %0, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_20.mlir b/benchmarks/LLVMIR/5_function_20.mlir new file mode 100644 index 0000000..b804de4 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_20.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %2, %0 + %5 = lshr i64 %1, %4 + %6 = udiv i64 %1, %5 + %7 = xor i64 %0, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_21.mlir b/benchmarks/LLVMIR/5_function_21.mlir new file mode 100644 index 0000000..62e0386 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_21.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = lshr i64 %0, %0 + %3 = trunc i64 %2 to i1 + %4 = select i1 %3, i64 %2, i64 %0 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_22.mlir b/benchmarks/LLVMIR/5_function_22.mlir new file mode 100644 index 0000000..58e64e4 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_22.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = xor i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_23.mlir b/benchmarks/LLVMIR/5_function_23.mlir new file mode 100644 index 0000000..da59f07 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_23.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + %5 = zext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_24.mlir b/benchmarks/LLVMIR/5_function_24.mlir new file mode 100644 index 0000000..2baeda5 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_24.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = xor i64 %2, %1 + %6 = and i64 %5, %2 + %7 = lshr i64 %4, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_25.mlir b/benchmarks/LLVMIR/5_function_25.mlir new file mode 100644 index 0000000..b7b8b5b --- /dev/null +++ b/benchmarks/LLVMIR/5_function_25.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = sdiv exact i64 %0, %0 + %5 = select i1 %1, i64 %0, i64 %0 + %6 = urem i64 %4, %5 + %7 = and i64 %6, %2 + %8 = or disjoint i64 %4, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_26.mlir b/benchmarks/LLVMIR/5_function_26.mlir new file mode 100644 index 0000000..77717eb --- /dev/null +++ b/benchmarks/LLVMIR/5_function_26.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = urem i64 %0, %0 + %3 = xor i64 %0, %2 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_27.mlir b/benchmarks/LLVMIR/5_function_27.mlir new file mode 100644 index 0000000..5e09c82 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_27.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %1, %2 + %5 = icmp sgt i64 %0, %4 + %6 = srem i64 %1, %0 + %7 = select i1 %5, i64 %2, i64 %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_28.mlir b/benchmarks/LLVMIR/5_function_28.mlir new file mode 100644 index 0000000..b4e1cd3 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_28.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = udiv i64 %1, %1 + %5 = sdiv i64 %4, %4 + %6 = srem i64 %5, %2 + %7 = select i1 %0, i64 %5, i64 %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_29.mlir b/benchmarks/LLVMIR/5_function_29.mlir new file mode 100644 index 0000000..1263e19 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_29.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = sdiv exact i64 %4, %2 + %6 = trunc i64 %1 to i32 + %7 = sext i32 %6 to i64 + %8 = srem i64 %5, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_3.mlir b/benchmarks/LLVMIR/5_function_3.mlir new file mode 100644 index 0000000..3d5307d --- /dev/null +++ b/benchmarks/LLVMIR/5_function_3.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = srem i64 %0, %0 + %3 = ashr i64 %2, %0 + %4 = or disjoint i64 %2, %3 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_30.mlir b/benchmarks/LLVMIR/5_function_30.mlir new file mode 100644 index 0000000..5edfe0d --- /dev/null +++ b/benchmarks/LLVMIR/5_function_30.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv exact i64 %2, %1 + %5 = udiv i64 %1, %4 + %6 = sdiv exact i64 %5, %5 + %7 = or disjoint i64 %0, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_31.mlir b/benchmarks/LLVMIR/5_function_31.mlir new file mode 100644 index 0000000..4482e0a --- /dev/null +++ b/benchmarks/LLVMIR/5_function_31.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = lshr exact i64 %1, %2 + %6 = icmp sge i64 %0, %5 + %7 = zext i32 %3 to i64 + %8 = select i1 %6, i64 %0, i64 %7 + %9 = xor i64 %8, %1 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_32.mlir b/benchmarks/LLVMIR/5_function_32.mlir new file mode 100644 index 0000000..e46eea4 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_32.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = and i64 %0, %1 + %4 = xor i64 %3, %0 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_33.mlir b/benchmarks/LLVMIR/5_function_33.mlir new file mode 100644 index 0000000..9aff63c --- /dev/null +++ b/benchmarks/LLVMIR/5_function_33.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = udiv i64 %2, %2 + %5 = and i64 %2, %4 + %6 = select i1 %1, i64 %0, i64 %5 + %7 = and i64 %0, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_34.mlir b/benchmarks/LLVMIR/5_function_34.mlir new file mode 100644 index 0000000..4539c78 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_34.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0, i64 %1, i64 %2) { + %4 = zext i32 %0 to i64 + %5 = xor i64 %1, %4 + %6 = xor i64 %4, %5 + %7 = or disjoint i64 %2, %4 + %8 = icmp ne i64 %6, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_35.mlir b/benchmarks/LLVMIR/5_function_35.mlir new file mode 100644 index 0000000..1bc5d6f --- /dev/null +++ b/benchmarks/LLVMIR/5_function_35.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %2, %1 + %5 = ashr exact i64 %2, %4 + %6 = udiv i64 %1, %5 + %7 = lshr i64 %0, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_36.mlir b/benchmarks/LLVMIR/5_function_36.mlir new file mode 100644 index 0000000..c5cd8b4 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_36.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = lshr exact i64 %4, %2 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_37.mlir b/benchmarks/LLVMIR/5_function_37.mlir new file mode 100644 index 0000000..a5df8d2 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_37.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i32 %2) { + %4 = trunc i64 %0 to i1 + %5 = zext i32 %2 to i64 + %6 = or disjoint i64 %1, %5 + %7 = select i1 %4, i64 %0, i64 %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_38.mlir b/benchmarks/LLVMIR/5_function_38.mlir new file mode 100644 index 0000000..99f8035 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_38.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1, i64 %2) { + %4 = srem i64 %0, %0 + %5 = and i64 %4, %2 + %6 = select i1 %1, i64 %4, i64 %5 + %7 = sdiv i64 %4, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_39.mlir b/benchmarks/LLVMIR/5_function_39.mlir new file mode 100644 index 0000000..343bb62 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_39.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0) { + %2 = zext i32 %0 to i64 + %3 = trunc i64 %2 to i1 + %4 = xor i64 %2, %2 + %5 = select i1 %3, i64 %2, i64 %4 + %6 = trunc i64 %5 to i1 + ret i1 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_4.mlir b/benchmarks/LLVMIR/5_function_4.mlir new file mode 100644 index 0000000..4553d20 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_4.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1, i64 %2) { + %4 = sext i32 %1 to i64 + %5 = sdiv i64 %0, %4 + %6 = udiv i64 %0, %5 + %7 = or disjoint i64 %6, %2 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_40.mlir b/benchmarks/LLVMIR/5_function_40.mlir new file mode 100644 index 0000000..0677fb3 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_40.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %0 + %5 = and i64 %1, %1 + %6 = urem i64 %4, %5 + %7 = ashr exact i64 %2, %1 + %8 = ashr i64 %6, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_41.mlir b/benchmarks/LLVMIR/5_function_41.mlir new file mode 100644 index 0000000..8b1d684 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_41.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = or disjoint i64 %6, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_42.mlir b/benchmarks/LLVMIR/5_function_42.mlir new file mode 100644 index 0000000..24529bf --- /dev/null +++ b/benchmarks/LLVMIR/5_function_42.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %0, %0 + %5 = xor i64 %4, %0 + %6 = or disjoint i64 %4, %5 + %7 = udiv i64 %1, %2 + %8 = icmp eq i64 %6, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_43.mlir b/benchmarks/LLVMIR/5_function_43.mlir new file mode 100644 index 0000000..beb8e5a --- /dev/null +++ b/benchmarks/LLVMIR/5_function_43.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %0, %1 + %5 = srem i64 %4, %2 + %6 = urem i64 %4, %5 + %7 = and i64 %6, %2 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_44.mlir b/benchmarks/LLVMIR/5_function_44.mlir new file mode 100644 index 0000000..b3320e1 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_44.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = or disjoint i64 %4, %2 + %6 = or i64 %0, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_45.mlir b/benchmarks/LLVMIR/5_function_45.mlir new file mode 100644 index 0000000..d2549e5 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_45.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i32 %2) { + %4 = zext i32 %2 to i64 + %5 = sdiv exact i64 %1, %4 + %6 = xor i64 %0, %5 + %7 = or i64 %6, %1 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_46.mlir b/benchmarks/LLVMIR/5_function_46.mlir new file mode 100644 index 0000000..40ba9ef --- /dev/null +++ b/benchmarks/LLVMIR/5_function_46.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_47.mlir b/benchmarks/LLVMIR/5_function_47.mlir new file mode 100644 index 0000000..859f7ba --- /dev/null +++ b/benchmarks/LLVMIR/5_function_47.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = udiv i64 %2, %1 + %5 = select i1 %0, i64 %1, i64 %4 + %6 = urem i64 %5, %5 + %7 = srem i64 %4, %6 + %8 = icmp eq i64 %5, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_48.mlir b/benchmarks/LLVMIR/5_function_48.mlir new file mode 100644 index 0000000..1a45627 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_48.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = xor i64 %0, %1 + %4 = udiv i64 %0, %3 + %5 = xor i64 %3, %3 + %6 = ashr i64 %4, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_49.mlir b/benchmarks/LLVMIR/5_function_49.mlir new file mode 100644 index 0000000..908420b --- /dev/null +++ b/benchmarks/LLVMIR/5_function_49.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %2, %0 + %5 = sdiv exact i64 %1, %4 + %6 = xor i64 %0, %5 + %7 = lshr exact i64 %6, %0 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_5.mlir b/benchmarks/LLVMIR/5_function_5.mlir new file mode 100644 index 0000000..67bd1e6 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_5.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = udiv i64 %4, %2 + %6 = udiv i64 %5, %0 + %7 = udiv i64 %6, %5 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_50.mlir b/benchmarks/LLVMIR/5_function_50.mlir new file mode 100644 index 0000000..f2c8671 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_50.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = lshr i64 %0, %1 + %4 = and i64 %3, %0 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_51.mlir b/benchmarks/LLVMIR/5_function_51.mlir new file mode 100644 index 0000000..92451a8 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_51.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %1, %2 + %5 = lshr exact i64 %0, %4 + %6 = urem i64 %5, %0 + %7 = and i64 %0, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_52.mlir b/benchmarks/LLVMIR/5_function_52.mlir new file mode 100644 index 0000000..954122f --- /dev/null +++ b/benchmarks/LLVMIR/5_function_52.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = lshr i64 %4, %0 + %6 = sdiv i64 %5, %0 + %7 = or disjoint i64 %6, %1 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_53.mlir b/benchmarks/LLVMIR/5_function_53.mlir new file mode 100644 index 0000000..39cd997 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_53.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %0 + %4 = icmp eq i64 %3, %3 + %5 = select i1 %4, i64 %0, i64 %1 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_54.mlir b/benchmarks/LLVMIR/5_function_54.mlir new file mode 100644 index 0000000..1e54026 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_54.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = xor i64 %0, %0 + %4 = sdiv exact i64 %0, %1 + %5 = udiv i64 %3, %4 + %6 = and i64 %5, %3 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_55.mlir b/benchmarks/LLVMIR/5_function_55.mlir new file mode 100644 index 0000000..bf65aa8 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_55.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp sge i64 %0, %1 + %5 = select i1 %4, i64 %2, i64 %2 + %6 = urem i64 %5, %1 + %7 = select i1 %4, i64 %2, i64 %6 + %8 = icmp sge i64 %7, %0 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_56.mlir b/benchmarks/LLVMIR/5_function_56.mlir new file mode 100644 index 0000000..bf32ae1 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_56.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = sdiv exact i64 %1, %1 + %6 = udiv i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_57.mlir b/benchmarks/LLVMIR/5_function_57.mlir new file mode 100644 index 0000000..a45f096 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_57.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr exact i64 %1, %0 + %5 = and i64 %0, %4 + %6 = ashr i64 %0, %5 + %7 = trunc i64 %6 to i1 + %8 = select i1 %7, i64 %2, i64 %1 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_58.mlir b/benchmarks/LLVMIR/5_function_58.mlir new file mode 100644 index 0000000..29d05a2 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_58.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1) { + %3 = zext i32 %0 to i64 + %4 = or i64 %1, %3 + %5 = xor i64 %3, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_59.mlir b/benchmarks/LLVMIR/5_function_59.mlir new file mode 100644 index 0000000..3373239 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_59.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = ashr i64 %1, %1 + %4 = and i64 %3, %1 + %5 = udiv i64 %3, %4 + %6 = and i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_6.mlir b/benchmarks/LLVMIR/5_function_6.mlir new file mode 100644 index 0000000..9d29b0f --- /dev/null +++ b/benchmarks/LLVMIR/5_function_6.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1) { + %3 = srem i64 %0, %0 + %4 = select i1 %1, i64 %3, i64 %3 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = icmp eq i64 %0, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_60.mlir b/benchmarks/LLVMIR/5_function_60.mlir new file mode 100644 index 0000000..4229bbb --- /dev/null +++ b/benchmarks/LLVMIR/5_function_60.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = and i64 %0, %5 + %7 = select i1 %1, i64 %2, i64 %6 + %8 = icmp eq i64 %6, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_61.mlir b/benchmarks/LLVMIR/5_function_61.mlir new file mode 100644 index 0000000..d956d45 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_61.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0, i32 %1) { + %3 = sext i32 %0 to i64 + %4 = zext i32 %1 to i64 + %5 = sdiv exact i64 %4, %3 + %6 = lshr i64 %3, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_62.mlir b/benchmarks/LLVMIR/5_function_62.mlir new file mode 100644 index 0000000..5f7811a --- /dev/null +++ b/benchmarks/LLVMIR/5_function_62.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i1 %2) { + %4 = lshr exact i64 %0, %1 + %5 = select i1 %2, i64 %4, i64 %0 + %6 = or i64 %0, %5 + %7 = srem i64 %4, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_63.mlir b/benchmarks/LLVMIR/5_function_63.mlir new file mode 100644 index 0000000..37df7eb --- /dev/null +++ b/benchmarks/LLVMIR/5_function_63.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = trunc i64 %2 to i32 + %6 = zext i32 %5 to i64 + %7 = sdiv i64 %4, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_64.mlir b/benchmarks/LLVMIR/5_function_64.mlir new file mode 100644 index 0000000..e32ef05 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_64.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %0 + %4 = or i64 %3, %0 + %5 = urem i64 %4, %1 + %6 = or i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_65.mlir b/benchmarks/LLVMIR/5_function_65.mlir new file mode 100644 index 0000000..9ebc8a3 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_65.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = srem i64 %0, %3 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_66.mlir b/benchmarks/LLVMIR/5_function_66.mlir new file mode 100644 index 0000000..4381369 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_66.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = trunc i64 %1 to i32 + %4 = zext i32 %3 to i64 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = urem i64 %0, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_67.mlir b/benchmarks/LLVMIR/5_function_67.mlir new file mode 100644 index 0000000..316bdc1 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_67.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %0, %0 + %5 = udiv i64 %4, %1 + %6 = udiv i64 %5, %2 + %7 = lshr i64 %0, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_68.mlir b/benchmarks/LLVMIR/5_function_68.mlir new file mode 100644 index 0000000..35bc3b6 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_68.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = sdiv i64 %2, %0 + %6 = srem i64 %5, %5 + %7 = sdiv exact i64 %4, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_69.mlir b/benchmarks/LLVMIR/5_function_69.mlir new file mode 100644 index 0000000..ef488dc --- /dev/null +++ b/benchmarks/LLVMIR/5_function_69.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = or i64 %1, %2 + %5 = or i64 %2, %1 + %6 = sdiv exact i64 %4, %5 + %7 = and i64 %6, %1 + %8 = icmp ugt i64 %0, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_7.mlir b/benchmarks/LLVMIR/5_function_7.mlir new file mode 100644 index 0000000..7a5d5a4 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_7.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %1, %2 + %5 = or i64 %1, %4 + %6 = sdiv exact i64 %4, %5 + %7 = urem i64 %0, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_70.mlir b/benchmarks/LLVMIR/5_function_70.mlir new file mode 100644 index 0000000..56c1f26 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_70.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1) { + %3 = trunc i64 %1 to i32 + %4 = zext i32 %3 to i64 + %5 = lshr exact i64 %1, %4 + %6 = select i1 %0, i64 %5, i64 %1 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_71.mlir b/benchmarks/LLVMIR/5_function_71.mlir new file mode 100644 index 0000000..d498d04 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_71.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_72.mlir b/benchmarks/LLVMIR/5_function_72.mlir new file mode 100644 index 0000000..65fd943 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_72.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = srem i64 %0, %3 + %5 = or i64 %0, %4 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_73.mlir b/benchmarks/LLVMIR/5_function_73.mlir new file mode 100644 index 0000000..8fc31b2 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_73.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = ashr i64 %0, %4 + %6 = udiv i64 %5, %2 + %7 = urem i64 %5, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_74.mlir b/benchmarks/LLVMIR/5_function_74.mlir new file mode 100644 index 0000000..835c3b3 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_74.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1, i32 %2) { + %4 = sext i32 %2 to i64 + %5 = select i1 %1, i64 %0, i64 %4 + %6 = and i64 %0, %5 + %7 = lshr exact i64 %6, %0 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_75.mlir b/benchmarks/LLVMIR/5_function_75.mlir new file mode 100644 index 0000000..ab757f7 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_75.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = xor i64 %0, %0 + %4 = sdiv i64 %1, %3 + %5 = and i64 %0, %4 + %6 = sdiv i64 %1, %4 + %7 = srem i64 %5, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_76.mlir b/benchmarks/LLVMIR/5_function_76.mlir new file mode 100644 index 0000000..daa8c95 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_76.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1) { + %3 = or i64 %0, %0 + %4 = zext i32 %1 to i64 + %5 = udiv i64 %3, %4 + %6 = ashr exact i64 %3, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_77.mlir b/benchmarks/LLVMIR/5_function_77.mlir new file mode 100644 index 0000000..f48ccf0 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_77.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %0, %1 + %5 = sdiv i64 %4, %4 + %6 = and i64 %5, %2 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_78.mlir b/benchmarks/LLVMIR/5_function_78.mlir new file mode 100644 index 0000000..d542748 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_78.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i32 %2) { + %4 = sdiv i64 %0, %0 + %5 = lshr exact i64 %4, %1 + %6 = zext i32 %2 to i64 + %7 = srem i64 %5, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_79.mlir b/benchmarks/LLVMIR/5_function_79.mlir new file mode 100644 index 0000000..7a8a04d --- /dev/null +++ b/benchmarks/LLVMIR/5_function_79.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %0 + %4 = lshr i64 %3, %0 + %5 = trunc i64 %1 to i32 + %6 = sext i32 %5 to i64 + %7 = icmp ule i64 %4, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_8.mlir b/benchmarks/LLVMIR/5_function_8.mlir new file mode 100644 index 0000000..9d110c0 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_8.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %0, %2 + %5 = xor i64 %1, %4 + %6 = udiv i64 %0, %5 + %7 = srem i64 %6, %5 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_80.mlir b/benchmarks/LLVMIR/5_function_80.mlir new file mode 100644 index 0000000..269ede7 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_80.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = sdiv exact i64 %0, %1 + %4 = ashr exact i64 %0, %3 + %5 = ashr exact i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_81.mlir b/benchmarks/LLVMIR/5_function_81.mlir new file mode 100644 index 0000000..f8f961d --- /dev/null +++ b/benchmarks/LLVMIR/5_function_81.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = trunc i64 %2 to i32 + %6 = sext i32 %5 to i64 + %7 = and i64 %4, %6 + %8 = icmp ule i64 %7, %4 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_82.mlir b/benchmarks/LLVMIR/5_function_82.mlir new file mode 100644 index 0000000..62c9c75 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_82.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = or disjoint i64 %5, %0 + %7 = lshr exact i64 %1, %2 + %8 = icmp uge i64 %6, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_83.mlir b/benchmarks/LLVMIR/5_function_83.mlir new file mode 100644 index 0000000..6d8a203 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_83.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i32 %2) { + %4 = or i64 %0, %1 + %5 = sext i32 %2 to i64 + %6 = ashr i64 %4, %5 + %7 = sdiv exact i64 %0, %6 + %8 = icmp sge i64 %6, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_84.mlir b/benchmarks/LLVMIR/5_function_84.mlir new file mode 100644 index 0000000..9882df4 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_84.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %2, i64 %0 + %5 = or disjoint i64 %0, %4 + %6 = and i64 %5, %2 + %7 = ashr i64 %5, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_85.mlir b/benchmarks/LLVMIR/5_function_85.mlir new file mode 100644 index 0000000..13b5803 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_85.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = zext i32 %3 to i64 + %6 = lshr i64 %1, %5 + %7 = sdiv exact i64 %4, %6 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_86.mlir b/benchmarks/LLVMIR/5_function_86.mlir new file mode 100644 index 0000000..47c88ac --- /dev/null +++ b/benchmarks/LLVMIR/5_function_86.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = sdiv exact i64 %0, %0 + %5 = and i64 %0, %0 + %6 = select i1 %1, i64 %4, i64 %5 + %7 = urem i64 %6, %2 + %8 = or i64 %4, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_87.mlir b/benchmarks/LLVMIR/5_function_87.mlir new file mode 100644 index 0000000..0a6225a --- /dev/null +++ b/benchmarks/LLVMIR/5_function_87.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %1 to i1 + %5 = sdiv i64 %2, %1 + %6 = select i1 %4, i64 %2, i64 %5 + %7 = or disjoint i64 %0, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_88.mlir b/benchmarks/LLVMIR/5_function_88.mlir new file mode 100644 index 0000000..25bb039 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_88.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = or disjoint i64 %0, %0 + %3 = lshr exact i64 %0, %2 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_89.mlir b/benchmarks/LLVMIR/5_function_89.mlir new file mode 100644 index 0000000..1b3d472 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_89.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = ashr i64 %1, %2 + %5 = select i1 %0, i64 %4, i64 %2 + %6 = select i1 %0, i64 %2, i64 %2 + %7 = and i64 %5, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_9.mlir b/benchmarks/LLVMIR/5_function_9.mlir new file mode 100644 index 0000000..8e68661 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_9.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %1 + %5 = xor i64 %1, %2 + %6 = ashr exact i64 %1, %5 + %7 = ashr i64 %4, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_90.mlir b/benchmarks/LLVMIR/5_function_90.mlir new file mode 100644 index 0000000..6007993 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_90.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %1 + %4 = ashr i64 %3, %1 + %5 = ashr exact i64 %1, %3 + %6 = srem i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_91.mlir b/benchmarks/LLVMIR/5_function_91.mlir new file mode 100644 index 0000000..05b6e0a --- /dev/null +++ b/benchmarks/LLVMIR/5_function_91.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1) { + %3 = udiv i64 %0, %0 + %4 = zext i32 %1 to i64 + %5 = and i64 %0, %4 + %6 = and i64 %3, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_92.mlir b/benchmarks/LLVMIR/5_function_92.mlir new file mode 100644 index 0000000..3210366 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_92.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = xor i64 %0, %3 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + ret i64 %6 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_93.mlir b/benchmarks/LLVMIR/5_function_93.mlir new file mode 100644 index 0000000..ea665a1 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_93.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %2 + %5 = trunc i64 %0 to i1 + %6 = select i1 %5, i64 %2, i64 %2 + %7 = udiv i64 %4, %6 + %8 = icmp sge i64 %0, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_94.mlir b/benchmarks/LLVMIR/5_function_94.mlir new file mode 100644 index 0000000..3246448 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_94.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = lshr i64 %2, %4 + %8 = sdiv exact i64 %6, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_95.mlir b/benchmarks/LLVMIR/5_function_95.mlir new file mode 100644 index 0000000..7504a36 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_95.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = or i64 %1, %0 + %5 = or disjoint i64 %4, %0 + %6 = lshr exact i64 %5, %2 + %7 = lshr exact i64 %0, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_96.mlir b/benchmarks/LLVMIR/5_function_96.mlir new file mode 100644 index 0000000..27cc759 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_96.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %1, %2 + %5 = lshr exact i64 %4, %0 + %6 = and i64 %0, %5 + %7 = srem i64 %6, %0 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_97.mlir b/benchmarks/LLVMIR/5_function_97.mlir new file mode 100644 index 0000000..52a73dd --- /dev/null +++ b/benchmarks/LLVMIR/5_function_97.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = sext i32 %3 to i64 + %6 = or disjoint i64 %4, %5 + %7 = srem i64 %6, %1 + ret i64 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_98.mlir b/benchmarks/LLVMIR/5_function_98.mlir new file mode 100644 index 0000000..b51b458 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_98.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1) { + %3 = select i1 %0, i64 %1, i64 %1 + %4 = lshr i64 %1, %3 + %5 = sdiv exact i64 %4, %1 + %6 = and i64 %3, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/5_function_99.mlir b/benchmarks/LLVMIR/5_function_99.mlir new file mode 100644 index 0000000..fc245c2 --- /dev/null +++ b/benchmarks/LLVMIR/5_function_99.mlir @@ -0,0 +1,15 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %1 + %5 = xor i64 %4, %2 + %6 = sdiv i64 %2, %2 + %7 = udiv i64 %5, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_0.mlir b/benchmarks/LLVMIR/6_function_0.mlir new file mode 100644 index 0000000..80d27bc --- /dev/null +++ b/benchmarks/LLVMIR/6_function_0.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %0, i64 %0 + %5 = srem i64 %0, %4 + %6 = select i1 %1, i64 %2, i64 %0 + %7 = sdiv i64 %5, %6 + %8 = urem i64 %7, %5 + %9 = or i64 %8, %5 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_1.mlir b/benchmarks/LLVMIR/6_function_1.mlir new file mode 100644 index 0000000..ec50861 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_1.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = lshr exact i64 %2, %0 + %8 = xor i64 %6, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_10.mlir b/benchmarks/LLVMIR/6_function_10.mlir new file mode 100644 index 0000000..81ef3c4 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_10.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %1, %2 + %5 = sdiv exact i64 %1, %2 + %6 = sdiv i64 %1, %5 + %7 = udiv i64 %4, %6 + %8 = lshr i64 %0, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_11.mlir b/benchmarks/LLVMIR/6_function_11.mlir new file mode 100644 index 0000000..46d4585 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_11.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i1 %2) { + %4 = srem i64 %0, %0 + %5 = trunc i64 %1 to i32 + %6 = sext i32 %5 to i64 + %7 = and i64 %4, %6 + %8 = select i1 %2, i64 %4, i64 %0 + %9 = lshr i64 %7, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_12.mlir b/benchmarks/LLVMIR/6_function_12.mlir new file mode 100644 index 0000000..9d15571 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_12.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = sdiv i64 %0, %0 + %4 = and i64 %1, %1 + %5 = ashr exact i64 %3, %4 + %6 = urem i64 %0, %5 + %7 = and i64 %6, %1 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_13.mlir b/benchmarks/LLVMIR/6_function_13.mlir new file mode 100644 index 0000000..44833d6 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_13.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1, i64 %2) { + %4 = zext i32 %1 to i64 + %5 = srem i64 %0, %4 + %6 = lshr i64 %2, %2 + %7 = sdiv i64 %2, %6 + %8 = ashr i64 %5, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_14.mlir b/benchmarks/LLVMIR/6_function_14.mlir new file mode 100644 index 0000000..64c8540 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_14.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i1 %2) { + %4 = srem i64 %1, %1 + %5 = select i1 %2, i64 %4, i64 %1 + %6 = select i1 %0, i64 %1, i64 %5 + %7 = srem i64 %6, %4 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_15.mlir b/benchmarks/LLVMIR/6_function_15.mlir new file mode 100644 index 0000000..2f0e074 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_15.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %0, %1 + %5 = lshr i64 %4, %0 + %6 = srem i64 %0, %5 + %7 = urem i64 %2, %5 + %8 = urem i64 %6, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_16.mlir b/benchmarks/LLVMIR/6_function_16.mlir new file mode 100644 index 0000000..db9f289 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_16.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i32 %2) { + %4 = select i1 %0, i64 %1, i64 %1 + %5 = sext i32 %2 to i64 + %6 = lshr exact i64 %4, %5 + %7 = urem i64 %4, %4 + %8 = sdiv i64 %7, %1 + %9 = icmp eq i64 %6, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_17.mlir b/benchmarks/LLVMIR/6_function_17.mlir new file mode 100644 index 0000000..b765ee1 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_17.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = xor i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = xor i64 %4, %2 + %9 = xor i64 %7, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_18.mlir b/benchmarks/LLVMIR/6_function_18.mlir new file mode 100644 index 0000000..a3efa2d --- /dev/null +++ b/benchmarks/LLVMIR/6_function_18.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i1 %2) { + %4 = or i64 %0, %1 + %5 = select i1 %2, i64 %0, i64 %0 + %6 = ashr i64 %1, %0 + %7 = select i1 %2, i64 %6, i64 %6 + %8 = lshr i64 %5, %7 + %9 = icmp ne i64 %4, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_19.mlir b/benchmarks/LLVMIR/6_function_19.mlir new file mode 100644 index 0000000..f87c5bd --- /dev/null +++ b/benchmarks/LLVMIR/6_function_19.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = sdiv i64 %2, %2 + %6 = trunc i64 %5 to i1 + %7 = select i1 %6, i64 %2, i64 %5 + %8 = sdiv i64 %4, %7 + %9 = lshr exact i64 %8, %5 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_2.mlir b/benchmarks/LLVMIR/6_function_2.mlir new file mode 100644 index 0000000..f609f3d --- /dev/null +++ b/benchmarks/LLVMIR/6_function_2.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = srem i64 %0, %4 + %6 = xor i64 %1, %2 + %7 = xor i64 %6, %5 + %8 = srem i64 %5, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_20.mlir b/benchmarks/LLVMIR/6_function_20.mlir new file mode 100644 index 0000000..c08efb1 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_20.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %0 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = and i64 %0, %5 + %7 = srem i64 %6, %1 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_21.mlir b/benchmarks/LLVMIR/6_function_21.mlir new file mode 100644 index 0000000..47e08c8 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_21.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i32 %2) { + %4 = sext i32 %2 to i64 + %5 = select i1 %0, i64 %1, i64 %4 + %6 = sdiv exact i64 %4, %4 + %7 = xor i64 %5, %6 + %8 = xor i64 %1, %6 + %9 = or i64 %7, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_22.mlir b/benchmarks/LLVMIR/6_function_22.mlir new file mode 100644 index 0000000..3a65d26 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_22.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %1, %2 + %5 = srem i64 %0, %4 + %6 = srem i64 %5, %0 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_23.mlir b/benchmarks/LLVMIR/6_function_23.mlir new file mode 100644 index 0000000..47e71f6 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_23.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %1 + %5 = or i64 %2, %4 + %6 = lshr i64 %5, %1 + %7 = urem i64 %5, %6 + %8 = srem i64 %7, %7 + %9 = icmp sge i64 %4, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_24.mlir b/benchmarks/LLVMIR/6_function_24.mlir new file mode 100644 index 0000000..6447032 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_24.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = sdiv i64 %2, %1 + %6 = trunc i64 %5 to i1 + %7 = select i1 %6, i64 %2, i64 %4 + %8 = udiv i64 %4, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_25.mlir b/benchmarks/LLVMIR/6_function_25.mlir new file mode 100644 index 0000000..01cb7e0 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_25.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = srem i64 %4, %1 + %6 = urem i64 %4, %5 + %7 = trunc i64 %2 to i32 + %8 = sext i32 %7 to i64 + %9 = ashr i64 %6, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_26.mlir b/benchmarks/LLVMIR/6_function_26.mlir new file mode 100644 index 0000000..85fc582 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_26.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %2, i64 %2 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = srem i64 %0, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_27.mlir b/benchmarks/LLVMIR/6_function_27.mlir new file mode 100644 index 0000000..8d0d3dd --- /dev/null +++ b/benchmarks/LLVMIR/6_function_27.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = and i64 %0, %4 + %6 = and i64 %2, %1 + %7 = or i64 %5, %6 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_28.mlir b/benchmarks/LLVMIR/6_function_28.mlir new file mode 100644 index 0000000..69747cf --- /dev/null +++ b/benchmarks/LLVMIR/6_function_28.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %1, %2 + %5 = and i64 %4, %1 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = ashr exact i64 %0, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_29.mlir b/benchmarks/LLVMIR/6_function_29.mlir new file mode 100644 index 0000000..54b6086 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_29.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = sdiv exact i64 %0, %0 + %4 = lshr exact i64 %0, %3 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = or i64 %6, %1 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_3.mlir b/benchmarks/LLVMIR/6_function_3.mlir new file mode 100644 index 0000000..f8541db --- /dev/null +++ b/benchmarks/LLVMIR/6_function_3.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp sge i64 %0, %0 + %5 = srem i64 %1, %2 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = select i1 %4, i64 %5, i64 %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_30.mlir b/benchmarks/LLVMIR/6_function_30.mlir new file mode 100644 index 0000000..c04a3e5 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_30.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %1, %0 + %5 = lshr i64 %4, %2 + %6 = lshr i64 %5, %5 + %7 = udiv i64 %0, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_31.mlir b/benchmarks/LLVMIR/6_function_31.mlir new file mode 100644 index 0000000..ff0dc67 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_31.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = trunc i64 %1 to i32 + %4 = sext i32 %3 to i64 + %5 = zext i32 %3 to i64 + %6 = sdiv exact i64 %4, %5 + %7 = ashr exact i64 %6, %5 + %8 = icmp ule i64 %0, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_32.mlir b/benchmarks/LLVMIR/6_function_32.mlir new file mode 100644 index 0000000..8fb24f4 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_32.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1, i32 %2) { + %4 = zext i32 %1 to i64 + %5 = xor i64 %0, %4 + %6 = sext i32 %2 to i64 + %7 = udiv i64 %6, %6 + %8 = srem i64 %5, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_33.mlir b/benchmarks/LLVMIR/6_function_33.mlir new file mode 100644 index 0000000..7b94b83 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_33.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = or disjoint i64 %0, %0 + %7 = ashr exact i64 %5, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_34.mlir b/benchmarks/LLVMIR/6_function_34.mlir new file mode 100644 index 0000000..3dfa35d --- /dev/null +++ b/benchmarks/LLVMIR/6_function_34.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i1 %2) { + %4 = xor i64 %0, %0 + %5 = trunc i64 %4 to i1 + %6 = select i1 %5, i64 %0, i64 %1 + %7 = select i1 %2, i64 %4, i64 %1 + %8 = srem i64 %6, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_35.mlir b/benchmarks/LLVMIR/6_function_35.mlir new file mode 100644 index 0000000..2ecea17 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_35.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i32 %1, i64 %2) { + %4 = sext i32 %1 to i64 + %5 = srem i64 %2, %0 + %6 = udiv i64 %4, %5 + %7 = zext i32 %1 to i64 + %8 = lshr i64 %6, %7 + %9 = sdiv exact i64 %0, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_36.mlir b/benchmarks/LLVMIR/6_function_36.mlir new file mode 100644 index 0000000..640a786 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_36.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = or disjoint i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = xor i64 %5, %5 + %7 = lshr exact i64 %3, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_37.mlir b/benchmarks/LLVMIR/6_function_37.mlir new file mode 100644 index 0000000..4b64015 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_37.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = sdiv exact i64 %4, %2 + %6 = urem i64 %0, %0 + %7 = sdiv i64 %5, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_38.mlir b/benchmarks/LLVMIR/6_function_38.mlir new file mode 100644 index 0000000..4b67eb6 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_38.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i32 %2) { + %4 = xor i64 %0, %1 + %5 = urem i64 %0, %4 + %6 = lshr i64 %0, %5 + %7 = zext i32 %2 to i64 + %8 = and i64 %6, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_39.mlir b/benchmarks/LLVMIR/6_function_39.mlir new file mode 100644 index 0000000..a809a18 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_39.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = trunc i64 %2 to i32 + %6 = sext i32 %5 to i64 + %7 = srem i64 %4, %6 + %8 = udiv i64 %7, %2 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_4.mlir b/benchmarks/LLVMIR/6_function_4.mlir new file mode 100644 index 0000000..8441f9c --- /dev/null +++ b/benchmarks/LLVMIR/6_function_4.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = lshr exact i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = zext i32 %4 to i64 + %6 = ashr exact i64 %5, %0 + %7 = xor i64 %5, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_40.mlir b/benchmarks/LLVMIR/6_function_40.mlir new file mode 100644 index 0000000..13cef2e --- /dev/null +++ b/benchmarks/LLVMIR/6_function_40.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %0 + %5 = udiv i64 %4, %1 + %6 = srem i64 %4, %5 + %7 = xor i64 %6, %2 + %8 = udiv i64 %4, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_41.mlir b/benchmarks/LLVMIR/6_function_41.mlir new file mode 100644 index 0000000..33e1c1f --- /dev/null +++ b/benchmarks/LLVMIR/6_function_41.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %0, i64 %2 + %5 = udiv i64 %0, %4 + %6 = urem i64 %2, %2 + %7 = srem i64 %5, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_42.mlir b/benchmarks/LLVMIR/6_function_42.mlir new file mode 100644 index 0000000..42aae63 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_42.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr i64 %0, %1 + %5 = urem i64 %4, %2 + %6 = trunc i64 %2 to i32 + %7 = zext i32 %6 to i64 + %8 = lshr exact i64 %5, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_43.mlir b/benchmarks/LLVMIR/6_function_43.mlir new file mode 100644 index 0000000..c011764 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_43.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = srem i64 %4, %1 + %6 = ashr exact i64 %2, %1 + %7 = icmp slt i64 %5, %6 + %8 = select i1 %7, i64 %6, i64 %1 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_44.mlir b/benchmarks/LLVMIR/6_function_44.mlir new file mode 100644 index 0000000..c5d612c --- /dev/null +++ b/benchmarks/LLVMIR/6_function_44.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = and i64 %0, %4 + %6 = udiv i64 %5, %2 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = lshr i64 %0, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_45.mlir b/benchmarks/LLVMIR/6_function_45.mlir new file mode 100644 index 0000000..07701e6 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_45.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = select i1 %1, i64 %4, i64 %4 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = icmp sgt i64 %4, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_46.mlir b/benchmarks/LLVMIR/6_function_46.mlir new file mode 100644 index 0000000..e5dd9ce --- /dev/null +++ b/benchmarks/LLVMIR/6_function_46.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = icmp sle i64 %0, %0 + %4 = xor i64 %0, %0 + %5 = urem i64 %4, %4 + %6 = and i64 %4, %1 + %7 = select i1 %3, i64 %5, i64 %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_47.mlir b/benchmarks/LLVMIR/6_function_47.mlir new file mode 100644 index 0000000..bea5bae --- /dev/null +++ b/benchmarks/LLVMIR/6_function_47.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = xor i64 %4, %2 + %6 = udiv i64 %4, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_48.mlir b/benchmarks/LLVMIR/6_function_48.mlir new file mode 100644 index 0000000..77850c7 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_48.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i1 %1, i64 %2) { + %4 = srem i64 %2, %2 + %5 = select i1 %1, i64 %4, i64 %4 + %6 = srem i64 %2, %5 + %7 = select i1 %0, i64 %5, i64 %6 + %8 = trunc i64 %7 to i1 + %9 = select i1 %8, i64 %5, i64 %7 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_49.mlir b/benchmarks/LLVMIR/6_function_49.mlir new file mode 100644 index 0000000..025dd6b --- /dev/null +++ b/benchmarks/LLVMIR/6_function_49.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = urem i64 %4, %0 + %6 = trunc i64 %1 to i32 + %7 = zext i32 %6 to i64 + %8 = or disjoint i64 %5, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_5.mlir b/benchmarks/LLVMIR/6_function_5.mlir new file mode 100644 index 0000000..294fcb7 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_5.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0) { + %2 = sext i32 %0 to i64 + %3 = trunc i64 %2 to i1 + %4 = select i1 %3, i64 %2, i64 %2 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = icmp uge i64 %2, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_50.mlir b/benchmarks/LLVMIR/6_function_50.mlir new file mode 100644 index 0000000..c3913b8 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_50.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i1 %2) { + %4 = urem i64 %0, %0 + %5 = ashr i64 %4, %1 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = select i1 %2, i64 %5, i64 %0 + %9 = urem i64 %7, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_51.mlir b/benchmarks/LLVMIR/6_function_51.mlir new file mode 100644 index 0000000..c1223d9 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_51.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %0 + %5 = trunc i64 %1 to i32 + %6 = zext i32 %5 to i64 + %7 = urem i64 %6, %2 + %8 = and i64 %4, %7 + %9 = icmp ult i64 %4, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_52.mlir b/benchmarks/LLVMIR/6_function_52.mlir new file mode 100644 index 0000000..1c4a1e3 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_52.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %2, %0 + %5 = or disjoint i64 %1, %4 + %6 = ashr i64 %0, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_53.mlir b/benchmarks/LLVMIR/6_function_53.mlir new file mode 100644 index 0000000..d0cbf3e --- /dev/null +++ b/benchmarks/LLVMIR/6_function_53.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i32 %1, i64 %2) { + %4 = zext i32 %1 to i64 + %5 = xor i64 %2, %2 + %6 = sdiv i64 %4, %5 + %7 = urem i64 %0, %6 + %8 = lshr i64 %5, %4 + %9 = udiv i64 %7, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_54.mlir b/benchmarks/LLVMIR/6_function_54.mlir new file mode 100644 index 0000000..523ba20 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_54.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = lshr i64 %0, %1 + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = lshr i64 %3, %5 + %7 = urem i64 %6, %5 + %8 = icmp ule i64 %6, %7 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_55.mlir b/benchmarks/LLVMIR/6_function_55.mlir new file mode 100644 index 0000000..f55a953 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_55.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = sdiv exact i64 %0, %0 + %4 = urem i64 %0, %1 + %5 = srem i64 %3, %4 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_56.mlir b/benchmarks/LLVMIR/6_function_56.mlir new file mode 100644 index 0000000..2de50ba --- /dev/null +++ b/benchmarks/LLVMIR/6_function_56.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %1, %2 + %5 = and i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = and i64 %7, %5 + %9 = xor i64 %0, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_57.mlir b/benchmarks/LLVMIR/6_function_57.mlir new file mode 100644 index 0000000..2518adf --- /dev/null +++ b/benchmarks/LLVMIR/6_function_57.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %1, %2 + %5 = ashr i64 %0, %4 + %6 = srem i64 %0, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_58.mlir b/benchmarks/LLVMIR/6_function_58.mlir new file mode 100644 index 0000000..0459cac --- /dev/null +++ b/benchmarks/LLVMIR/6_function_58.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1) { + %3 = icmp ugt i64 %0, %0 + %4 = zext i32 %1 to i64 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = select i1 %3, i64 %0, i64 %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_59.mlir b/benchmarks/LLVMIR/6_function_59.mlir new file mode 100644 index 0000000..1992c00 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_59.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = and i64 %2, %2 + %6 = udiv i64 %4, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_6.mlir b/benchmarks/LLVMIR/6_function_6.mlir new file mode 100644 index 0000000..44e97b0 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_6.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %1, %0 + %5 = sdiv i64 %4, %2 + %6 = lshr exact i64 %0, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_60.mlir b/benchmarks/LLVMIR/6_function_60.mlir new file mode 100644 index 0000000..8961606 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_60.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = sdiv exact i64 %0, %0 + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = sdiv exact i64 %2, %4 + %6 = lshr exact i64 %0, %5 + %7 = trunc i64 %6 to i1 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_61.mlir b/benchmarks/LLVMIR/6_function_61.mlir new file mode 100644 index 0000000..0926d2a --- /dev/null +++ b/benchmarks/LLVMIR/6_function_61.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %0 + %5 = srem i64 %0, %4 + %6 = trunc i64 %2 to i32 + %7 = zext i32 %6 to i64 + %8 = and i64 %1, %7 + %9 = lshr i64 %5, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_62.mlir b/benchmarks/LLVMIR/6_function_62.mlir new file mode 100644 index 0000000..e90f545 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_62.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr exact i64 %0, %1 + %5 = xor i64 %4, %2 + %6 = ashr i64 %4, %5 + %7 = trunc i64 %6 to i1 + %8 = select i1 %7, i64 %4, i64 %2 + %9 = urem i64 %6, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_63.mlir b/benchmarks/LLVMIR/6_function_63.mlir new file mode 100644 index 0000000..0d35021 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_63.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = xor i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = sext i32 %3 to i64 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_64.mlir b/benchmarks/LLVMIR/6_function_64.mlir new file mode 100644 index 0000000..8d4a9d9 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_64.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %0, %1 + %5 = udiv i64 %0, %0 + %6 = srem i64 %5, %0 + %7 = ashr exact i64 %2, %2 + %8 = srem i64 %6, %7 + %9 = lshr i64 %4, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_65.mlir b/benchmarks/LLVMIR/6_function_65.mlir new file mode 100644 index 0000000..bb935f5 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_65.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = lshr i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = zext i32 %3 to i64 + %5 = sext i32 %3 to i64 + %6 = sdiv exact i64 %4, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_66.mlir b/benchmarks/LLVMIR/6_function_66.mlir new file mode 100644 index 0000000..2041264 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_66.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %0, i64 %2 + %5 = sdiv i64 %0, %4 + %6 = trunc i64 %2 to i32 + %7 = zext i32 %6 to i64 + %8 = sdiv exact i64 %5, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_67.mlir b/benchmarks/LLVMIR/6_function_67.mlir new file mode 100644 index 0000000..740a137 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_67.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %1, %1 + %5 = lshr exact i64 %1, %4 + %6 = and i64 %0, %5 + %7 = xor i64 %2, %6 + %8 = srem i64 %1, %7 + %9 = ashr i64 %0, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_68.mlir b/benchmarks/LLVMIR/6_function_68.mlir new file mode 100644 index 0000000..4ac1bb8 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_68.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %0 + %4 = ashr i64 %3, %0 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = udiv i64 %4, %1 + %8 = lshr exact i64 %6, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_69.mlir b/benchmarks/LLVMIR/6_function_69.mlir new file mode 100644 index 0000000..a71a249 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_69.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = icmp eq i64 %0, %0 + %6 = srem i64 %1, %2 + %7 = zext i32 %3 to i64 + %8 = sdiv exact i64 %7, %1 + %9 = select i1 %5, i64 %6, i64 %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_7.mlir b/benchmarks/LLVMIR/6_function_7.mlir new file mode 100644 index 0000000..e3c4282 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_7.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = udiv i64 %4, %2 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = ashr i64 %7, %1 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_70.mlir b/benchmarks/LLVMIR/6_function_70.mlir new file mode 100644 index 0000000..21fbb46 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_70.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = urem i64 %0, %0 + %5 = urem i64 %4, %4 + %6 = select i1 %1, i64 %2, i64 %2 + %7 = ashr exact i64 %5, %6 + %8 = urem i64 %6, %2 + %9 = and i64 %7, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_71.mlir b/benchmarks/LLVMIR/6_function_71.mlir new file mode 100644 index 0000000..17f9782 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_71.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = udiv i64 %1, %2 + %6 = ashr exact i64 %4, %5 + %7 = lshr i64 %6, %2 + %8 = ashr exact i64 %7, %4 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_72.mlir b/benchmarks/LLVMIR/6_function_72.mlir new file mode 100644 index 0000000..3ea1555 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_72.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = sdiv i64 %2, %2 + %6 = udiv i64 %0, %5 + %7 = sdiv i64 %4, %6 + %8 = srem i64 %7, %4 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_73.mlir b/benchmarks/LLVMIR/6_function_73.mlir new file mode 100644 index 0000000..bcd5de6 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_73.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = urem i64 %0, %1 + %4 = or disjoint i64 %3, %3 + %5 = and i64 %4, %3 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_74.mlir b/benchmarks/LLVMIR/6_function_74.mlir new file mode 100644 index 0000000..1dac157 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_74.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %2, %2 + %5 = udiv i64 %1, %4 + %6 = or disjoint i64 %0, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_75.mlir b/benchmarks/LLVMIR/6_function_75.mlir new file mode 100644 index 0000000..cdbdf7f --- /dev/null +++ b/benchmarks/LLVMIR/6_function_75.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i32 %2) { + %4 = ashr exact i64 %0, %1 + %5 = lshr exact i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = sext i32 %2 to i64 + %9 = ashr exact i64 %7, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_76.mlir b/benchmarks/LLVMIR/6_function_76.mlir new file mode 100644 index 0000000..5ddd636 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_76.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %0, %0 + %5 = icmp ult i64 %4, %0 + %6 = select i1 %5, i64 %1, i64 %2 + %7 = urem i64 %2, %4 + %8 = sdiv exact i64 %6, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_77.mlir b/benchmarks/LLVMIR/6_function_77.mlir new file mode 100644 index 0000000..c57769e --- /dev/null +++ b/benchmarks/LLVMIR/6_function_77.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %0, %1 + %5 = trunc i64 %2 to i32 + %6 = sext i32 %5 to i64 + %7 = udiv i64 %1, %6 + %8 = ashr exact i64 %4, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_78.mlir b/benchmarks/LLVMIR/6_function_78.mlir new file mode 100644 index 0000000..8041cda --- /dev/null +++ b/benchmarks/LLVMIR/6_function_78.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = or i64 %0, %0 + %5 = and i64 %4, %0 + %6 = trunc i64 %1 to i32 + %7 = zext i32 %6 to i64 + %8 = udiv i64 %7, %2 + %9 = icmp ne i64 %5, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_79.mlir b/benchmarks/LLVMIR/6_function_79.mlir new file mode 100644 index 0000000..71c3cdb --- /dev/null +++ b/benchmarks/LLVMIR/6_function_79.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %2 + %5 = select i1 %0, i64 %4, i64 %2 + %6 = select i1 %0, i64 %2, i64 %4 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = icmp slt i64 %5, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_8.mlir b/benchmarks/LLVMIR/6_function_8.mlir new file mode 100644 index 0000000..73faf25 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_8.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = udiv i64 %2, %2 + %5 = select i1 %0, i64 %1, i64 %4 + %6 = lshr i64 %5, %2 + %7 = sdiv exact i64 %2, %4 + %8 = srem i64 %7, %2 + %9 = icmp slt i64 %6, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_80.mlir b/benchmarks/LLVMIR/6_function_80.mlir new file mode 100644 index 0000000..f8d85fb --- /dev/null +++ b/benchmarks/LLVMIR/6_function_80.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i32 %2) { + %4 = zext i32 %2 to i64 + %5 = select i1 %0, i64 %1, i64 %4 + %6 = and i64 %1, %1 + %7 = xor i64 %6, %5 + %8 = lshr exact i64 %5, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_81.mlir b/benchmarks/LLVMIR/6_function_81.mlir new file mode 100644 index 0000000..634af84 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_81.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %2 + %5 = and i64 %1, %4 + %6 = ashr exact i64 %0, %5 + %7 = lshr exact i64 %6, %5 + %8 = udiv i64 %6, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_82.mlir b/benchmarks/LLVMIR/6_function_82.mlir new file mode 100644 index 0000000..dde61da --- /dev/null +++ b/benchmarks/LLVMIR/6_function_82.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %2, %0 + %5 = icmp ugt i64 %1, %4 + %6 = urem i64 %2, %2 + %7 = select i1 %5, i64 %6, i64 %2 + %8 = udiv i64 %0, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_83.mlir b/benchmarks/LLVMIR/6_function_83.mlir new file mode 100644 index 0000000..9fa429c --- /dev/null +++ b/benchmarks/LLVMIR/6_function_83.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = icmp sgt i64 %4, %1 + %6 = ashr exact i64 %1, %1 + %7 = srem i64 %6, %2 + %8 = select i1 %5, i64 %1, i64 %7 + %9 = ashr exact i64 %8, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_84.mlir b/benchmarks/LLVMIR/6_function_84.mlir new file mode 100644 index 0000000..c70e363 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_84.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = lshr i64 %1, %0 + %6 = sdiv exact i64 %0, %5 + %7 = lshr exact i64 %6, %2 + %8 = sext i32 %3 to i64 + %9 = icmp ule i64 %7, %8 + %10 = select i1 %9, i64 %7, i64 %2 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_85.mlir b/benchmarks/LLVMIR/6_function_85.mlir new file mode 100644 index 0000000..d8225b1 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_85.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = ashr i64 %2, %1 + %5 = and i64 %1, %4 + %6 = trunc i64 %4 to i32 + %7 = zext i32 %6 to i64 + %8 = select i1 %0, i64 %5, i64 %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_86.mlir b/benchmarks/LLVMIR/6_function_86.mlir new file mode 100644 index 0000000..4d08a90 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_86.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i1 %2) { + %4 = or i64 %0, %0 + %5 = or disjoint i64 %4, %1 + %6 = and i64 %4, %5 + %7 = select i1 %2, i64 %6, i64 %6 + %8 = xor i64 %0, %7 + %9 = or disjoint i64 %6, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_87.mlir b/benchmarks/LLVMIR/6_function_87.mlir new file mode 100644 index 0000000..c67ea76 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_87.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %0 + %4 = or disjoint i64 %0, %3 + %5 = or i64 %1, %0 + %6 = udiv i64 %4, %5 + %7 = urem i64 %0, %6 + %8 = trunc i64 %7 to i1 + ret i1 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_88.mlir b/benchmarks/LLVMIR/6_function_88.mlir new file mode 100644 index 0000000..9e2e625 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_88.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %2, i64 %0 + %5 = or disjoint i64 %4, %4 + %6 = icmp slt i64 %0, %5 + %7 = select i1 %6, i64 %5, i64 %4 + %8 = srem i64 %7, %0 + %9 = icmp eq i64 %7, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_89.mlir b/benchmarks/LLVMIR/6_function_89.mlir new file mode 100644 index 0000000..80fddb1 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_89.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = srem i64 %0, %0 + %5 = and i64 %3, %4 + %6 = udiv i64 %5, %3 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_9.mlir b/benchmarks/LLVMIR/6_function_9.mlir new file mode 100644 index 0000000..e7bc185 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_9.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i1 %2, i32 %3) { + %5 = sext i32 %3 to i64 + %6 = select i1 %2, i64 %5, i64 %5 + %7 = select i1 %0, i64 %1, i64 %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_90.mlir b/benchmarks/LLVMIR/6_function_90.mlir new file mode 100644 index 0000000..d504215 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_90.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = srem i64 %0, %2 + %5 = lshr exact i64 %4, %2 + %6 = select i1 %1, i64 %4, i64 %5 + %7 = and i64 %5, %2 + %8 = or disjoint i64 %6, %7 + %9 = icmp ugt i64 %0, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_91.mlir b/benchmarks/LLVMIR/6_function_91.mlir new file mode 100644 index 0000000..631d06f --- /dev/null +++ b/benchmarks/LLVMIR/6_function_91.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %0, %1 + %5 = udiv i64 %0, %2 + %6 = sdiv i64 %0, %5 + %7 = ashr i64 %4, %6 + %8 = lshr exact i64 %0, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_92.mlir b/benchmarks/LLVMIR/6_function_92.mlir new file mode 100644 index 0000000..afbeb8e --- /dev/null +++ b/benchmarks/LLVMIR/6_function_92.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp ugt i64 %0, %1 + %5 = srem i64 %0, %2 + %6 = select i1 %4, i64 %2, i64 %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_93.mlir b/benchmarks/LLVMIR/6_function_93.mlir new file mode 100644 index 0000000..dddb6a3 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_93.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %2, %0 + %5 = lshr i64 %0, %4 + %6 = srem i64 %1, %5 + %7 = srem i64 %6, %4 + %8 = lshr exact i64 %0, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_94.mlir b/benchmarks/LLVMIR/6_function_94.mlir new file mode 100644 index 0000000..cf794f2 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_94.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = select i1 %0, i64 %2, i64 %2 + %6 = urem i64 %5, %5 + %7 = or i64 %6, %5 + %8 = udiv i64 %7, %4 + %9 = sdiv i64 %4, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_95.mlir b/benchmarks/LLVMIR/6_function_95.mlir new file mode 100644 index 0000000..24a5dea --- /dev/null +++ b/benchmarks/LLVMIR/6_function_95.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = urem i64 %0, %0 + %4 = srem i64 %1, %3 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = urem i64 %3, %6 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_96.mlir b/benchmarks/LLVMIR/6_function_96.mlir new file mode 100644 index 0000000..5e4d4da --- /dev/null +++ b/benchmarks/LLVMIR/6_function_96.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i1 + %5 = lshr i64 %1, %0 + %6 = trunc i64 %2 to i32 + %7 = zext i32 %6 to i64 + %8 = select i1 %4, i64 %5, i64 %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_97.mlir b/benchmarks/LLVMIR/6_function_97.mlir new file mode 100644 index 0000000..79b0b45 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_97.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = sext i32 %2 to i64 + %4 = trunc i64 %3 to i1 + %5 = select i1 %4, i64 %3, i64 %3 + %6 = and i64 %3, %5 + %7 = trunc i64 %6 to i32 + ret i32 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_98.mlir b/benchmarks/LLVMIR/6_function_98.mlir new file mode 100644 index 0000000..06a80d6 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_98.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0) { + %2 = udiv i64 %0, %0 + %3 = and i64 %2, %0 + %4 = or i64 %0, %3 + %5 = trunc i64 %0 to i32 + %6 = sext i32 %5 to i64 + %7 = icmp ne i64 %4, %6 + ret i1 %7 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/6_function_99.mlir b/benchmarks/LLVMIR/6_function_99.mlir new file mode 100644 index 0000000..2aaa9c9 --- /dev/null +++ b/benchmarks/LLVMIR/6_function_99.mlir @@ -0,0 +1,16 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = icmp eq i64 %2, %0 + %6 = sext i32 %3 to i64 + %7 = select i1 %5, i64 %6, i64 %0 + %8 = urem i64 %1, %7 + %9 = and i64 %0, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_0.mlir b/benchmarks/LLVMIR/7_function_0.mlir new file mode 100644 index 0000000..0f65c6d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_0.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = trunc i64 %2 to i1 + %6 = select i1 %5, i64 %2, i64 %4 + %7 = or disjoint i64 %4, %6 + %8 = select i1 %5, i64 %1, i64 %4 + %9 = sdiv i64 %7, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_1.mlir b/benchmarks/LLVMIR/7_function_1.mlir new file mode 100644 index 0000000..0435af9 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_1.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i32 %2) { + %4 = srem i64 %0, %1 + %5 = zext i32 %2 to i64 + %6 = sdiv i64 %5, %0 + %7 = lshr exact i64 %4, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_10.mlir b/benchmarks/LLVMIR/7_function_10.mlir new file mode 100644 index 0000000..bd68c3c --- /dev/null +++ b/benchmarks/LLVMIR/7_function_10.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0, i64 %1, i64 %2) { + %4 = zext i32 %0 to i64 + %5 = lshr exact i64 %4, %4 + %6 = udiv i64 %5, %5 + %7 = srem i64 %2, %6 + %8 = urem i64 %1, %7 + %9 = urem i64 %5, %8 + %10 = icmp sle i64 %6, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_11.mlir b/benchmarks/LLVMIR/7_function_11.mlir new file mode 100644 index 0000000..804737e --- /dev/null +++ b/benchmarks/LLVMIR/7_function_11.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = zext i32 %0 to i64 + %5 = xor i64 %4, %1 + %6 = lshr exact i64 %2, %4 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = sdiv exact i64 %5, %8 + %10 = srem i64 %4, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_12.mlir b/benchmarks/LLVMIR/7_function_12.mlir new file mode 100644 index 0000000..976e930 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_12.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = ashr exact i64 %5, %0 + %7 = or i64 %2, %5 + %8 = sdiv exact i64 %5, %7 + %9 = udiv i64 %1, %8 + %10 = icmp sle i64 %6, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_13.mlir b/benchmarks/LLVMIR/7_function_13.mlir new file mode 100644 index 0000000..6d0afc4 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_13.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = udiv i64 %4, %1 + %6 = icmp ule i64 %5, %2 + %7 = select i1 %6, i64 %5, i64 %0 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_14.mlir b/benchmarks/LLVMIR/7_function_14.mlir new file mode 100644 index 0000000..72e8b09 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_14.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1, i1 %2) { + %4 = sext i32 %1 to i64 + %5 = and i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = select i1 %2, i64 %4, i64 %4 + %9 = or disjoint i64 %7, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_15.mlir b/benchmarks/LLVMIR/7_function_15.mlir new file mode 100644 index 0000000..a7ff0ae --- /dev/null +++ b/benchmarks/LLVMIR/7_function_15.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1, i64 %2) { + %4 = sext i32 %1 to i64 + %5 = icmp ule i64 %0, %4 + %6 = srem i64 %2, %4 + %7 = sdiv i64 %2, %6 + %8 = lshr i64 %0, %7 + %9 = select i1 %5, i64 %7, i64 %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_16.mlir b/benchmarks/LLVMIR/7_function_16.mlir new file mode 100644 index 0000000..5d80318 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_16.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2, i32 %3) { + %5 = select i1 %0, i64 %1, i64 %1 + %6 = sdiv i64 %5, %2 + %7 = zext i32 %3 to i64 + %8 = ashr i64 %6, %7 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_17.mlir b/benchmarks/LLVMIR/7_function_17.mlir new file mode 100644 index 0000000..6e5667c --- /dev/null +++ b/benchmarks/LLVMIR/7_function_17.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %2, %0 + %5 = or disjoint i64 %2, %4 + %6 = xor i64 %5, %2 + %7 = and i64 %6, %6 + %8 = xor i64 %2, %7 + %9 = xor i64 %1, %8 + %10 = icmp ne i64 %0, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_18.mlir b/benchmarks/LLVMIR/7_function_18.mlir new file mode 100644 index 0000000..4765e90 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_18.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %0 + %4 = udiv i64 %3, %3 + %5 = sdiv exact i64 %0, %4 + %6 = or i64 %3, %5 + %7 = ashr i64 %0, %6 + %8 = urem i64 %1, %6 + %9 = and i64 %7, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_19.mlir b/benchmarks/LLVMIR/7_function_19.mlir new file mode 100644 index 0000000..86e9b01 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_19.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %1, %2 + %5 = lshr i64 %0, %4 + %6 = urem i64 %5, %1 + %7 = xor i64 %6, %6 + %8 = xor i64 %7, %4 + %9 = urem i64 %8, %1 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_2.mlir b/benchmarks/LLVMIR/7_function_2.mlir new file mode 100644 index 0000000..68f3ed8 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_2.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = ashr exact i64 %0, %2 + %6 = urem i64 %5, %1 + %7 = sdiv i64 %6, %1 + %8 = lshr i64 %6, %7 + %9 = xor i64 %4, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_20.mlir b/benchmarks/LLVMIR/7_function_20.mlir new file mode 100644 index 0000000..69a76a9 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_20.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %0 + %5 = icmp sge i64 %4, %1 + %6 = urem i64 %2, %1 + %7 = srem i64 %4, %6 + %8 = select i1 %5, i64 %0, i64 %7 + %9 = sdiv exact i64 %4, %8 + %10 = lshr exact i64 %0, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_21.mlir b/benchmarks/LLVMIR/7_function_21.mlir new file mode 100644 index 0000000..a312b07 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_21.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = udiv i64 %1, %2 + %6 = icmp uge i64 %5, %1 + %7 = select i1 %6, i64 %1, i64 %5 + %8 = and i64 %4, %7 + %9 = xor i64 %7, %8 + %10 = udiv i64 %8, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_22.mlir b/benchmarks/LLVMIR/7_function_22.mlir new file mode 100644 index 0000000..b82547c --- /dev/null +++ b/benchmarks/LLVMIR/7_function_22.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %1, %2 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = lshr i64 %0, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_23.mlir b/benchmarks/LLVMIR/7_function_23.mlir new file mode 100644 index 0000000..7b9a7dc --- /dev/null +++ b/benchmarks/LLVMIR/7_function_23.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %0, %0 + %5 = and i64 %1, %2 + %6 = sdiv exact i64 %0, %5 + %7 = udiv i64 %4, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_24.mlir b/benchmarks/LLVMIR/7_function_24.mlir new file mode 100644 index 0000000..8d9f5d4 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_24.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = srem i64 %0, %0 + %3 = lshr exact i64 %0, %2 + %4 = or i64 %0, %3 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = srem i64 %4, %2 + %8 = urem i64 %6, %7 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_25.mlir b/benchmarks/LLVMIR/7_function_25.mlir new file mode 100644 index 0000000..0ee5334 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_25.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = udiv i64 %0, %1 + %6 = trunc i64 %5 to i1 + %7 = select i1 %6, i64 %2, i64 %5 + %8 = trunc i64 %7 to i1 + %9 = zext i32 %3 to i64 + %10 = urem i64 %7, %5 + %11 = select i1 %8, i64 %9, i64 %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_26.mlir b/benchmarks/LLVMIR/7_function_26.mlir new file mode 100644 index 0000000..0ba4ea3 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_26.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr exact i64 %0, %0 + %5 = and i64 %1, %4 + %6 = xor i64 %4, %5 + %7 = urem i64 %2, %4 + %8 = sdiv exact i64 %7, %4 + %9 = ashr exact i64 %6, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_27.mlir b/benchmarks/LLVMIR/7_function_27.mlir new file mode 100644 index 0000000..eb3b06e --- /dev/null +++ b/benchmarks/LLVMIR/7_function_27.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = zext i32 %4 to i64 + %6 = xor i64 %5, %5 + %7 = select i1 %1, i64 %6, i64 %2 + %8 = icmp slt i64 %6, %7 + %9 = select i1 %8, i64 %0, i64 %5 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_28.mlir b/benchmarks/LLVMIR/7_function_28.mlir new file mode 100644 index 0000000..bbbdba1 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_28.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i32 %2) { + %4 = zext i32 %2 to i64 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = srem i64 %6, %6 + %8 = srem i64 %1, %7 + %9 = udiv i64 %0, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_29.mlir b/benchmarks/LLVMIR/7_function_29.mlir new file mode 100644 index 0000000..c3b44c4 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_29.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = trunc i64 %0 to i1 + %6 = select i1 %5, i64 %1, i64 %1 + %7 = sext i32 %3 to i64 + %8 = xor i64 %0, %7 + %9 = ashr exact i64 %2, %8 + %10 = and i64 %6, %9 + %11 = and i64 %10, %0 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_3.mlir b/benchmarks/LLVMIR/7_function_3.mlir new file mode 100644 index 0000000..aa4fbc6 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_3.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i32 %2) { + %4 = sdiv i64 %0, %0 + %5 = or i64 %4, %1 + %6 = zext i32 %2 to i64 + %7 = srem i64 %5, %6 + %8 = sext i32 %2 to i64 + %9 = ashr i64 %8, %8 + %10 = udiv i64 %7, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_30.mlir b/benchmarks/LLVMIR/7_function_30.mlir new file mode 100644 index 0000000..a7a7d14 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_30.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1) { + %3 = trunc i64 %1 to i32 + %4 = sext i32 %3 to i64 + %5 = select i1 %0, i64 %4, i64 %4 + %6 = lshr exact i64 %4, %1 + %7 = and i64 %5, %6 + %8 = urem i64 %5, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_31.mlir b/benchmarks/LLVMIR/7_function_31.mlir new file mode 100644 index 0000000..c2aa0e7 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_31.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %2, i64 %0 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = and i64 %8, %6 + %10 = icmp ult i64 %0, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_32.mlir b/benchmarks/LLVMIR/7_function_32.mlir new file mode 100644 index 0000000..ac94081 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_32.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = ashr i64 %0, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = xor i64 %1, %2 + %10 = xor i64 %8, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_33.mlir b/benchmarks/LLVMIR/7_function_33.mlir new file mode 100644 index 0000000..a6318ec --- /dev/null +++ b/benchmarks/LLVMIR/7_function_33.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = urem i64 %0, %0 + %4 = xor i64 %1, %1 + %5 = or disjoint i64 %3, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = srem i64 %7, %0 + %9 = icmp slt i64 %0, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_34.mlir b/benchmarks/LLVMIR/7_function_34.mlir new file mode 100644 index 0000000..9d097f2 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_34.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = trunc i64 %2 to i32 + %5 = zext i32 %4 to i64 + %6 = xor i64 %5, %2 + %7 = select i1 %0, i64 %1, i64 %6 + %8 = lshr exact i64 %7, %5 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_35.mlir b/benchmarks/LLVMIR/7_function_35.mlir new file mode 100644 index 0000000..2905436 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_35.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = zext i32 %3 to i64 + %6 = ashr exact i64 %4, %5 + %7 = lshr i64 %6, %1 + %8 = and i64 %0, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_36.mlir b/benchmarks/LLVMIR/7_function_36.mlir new file mode 100644 index 0000000..44e9f4d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_36.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %1, %2 + %5 = select i1 %0, i64 %4, i64 %2 + %6 = icmp ule i64 %1, %4 + %7 = or i64 %5, %5 + %8 = select i1 %6, i64 %7, i64 %4 + %9 = udiv i64 %8, %7 + %10 = lshr exact i64 %5, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_37.mlir b/benchmarks/LLVMIR/7_function_37.mlir new file mode 100644 index 0000000..ec9cb9a --- /dev/null +++ b/benchmarks/LLVMIR/7_function_37.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1, i64 %2) { + %4 = or disjoint i64 %0, %0 + %5 = select i1 %1, i64 %2, i64 %4 + %6 = lshr i64 %5, %0 + %7 = srem i64 %0, %6 + %8 = and i64 %7, %5 + %9 = xor i64 %0, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_38.mlir b/benchmarks/LLVMIR/7_function_38.mlir new file mode 100644 index 0000000..7ed46b7 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_38.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = and i64 %0, %4 + %6 = urem i64 %5, %4 + %7 = icmp eq i64 %6, %2 + %8 = select i1 %7, i64 %4, i64 %5 + %9 = or i64 %8, %1 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_39.mlir b/benchmarks/LLVMIR/7_function_39.mlir new file mode 100644 index 0000000..4a48613 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_39.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = urem i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = urem i64 %5, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_4.mlir b/benchmarks/LLVMIR/7_function_4.mlir new file mode 100644 index 0000000..f7cc417 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_4.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %0, %1 + %5 = lshr exact i64 %4, %4 + %6 = udiv i64 %5, %1 + %7 = and i64 %2, %6 + %8 = ashr i64 %2, %7 + %9 = and i64 %1, %8 + %10 = icmp slt i64 %0, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_40.mlir b/benchmarks/LLVMIR/7_function_40.mlir new file mode 100644 index 0000000..3539213 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_40.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i32 %2) { + %4 = trunc i64 %0 to i32 + %5 = zext i32 %4 to i64 + %6 = lshr i64 %5, %1 + %7 = sext i32 %2 to i64 + %8 = srem i64 %7, %1 + %9 = lshr exact i64 %8, %7 + %10 = ashr exact i64 %6, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_41.mlir b/benchmarks/LLVMIR/7_function_41.mlir new file mode 100644 index 0000000..1531eef --- /dev/null +++ b/benchmarks/LLVMIR/7_function_41.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = and i64 %1, %4 + %6 = lshr i64 %2, %5 + %7 = lshr i64 %4, %6 + %8 = and i64 %4, %2 + %9 = udiv i64 %7, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_42.mlir b/benchmarks/LLVMIR/7_function_42.mlir new file mode 100644 index 0000000..6d1301f --- /dev/null +++ b/benchmarks/LLVMIR/7_function_42.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %0 + %5 = ashr i64 %1, %2 + %6 = ashr i64 %4, %5 + %7 = xor i64 %1, %0 + %8 = ashr exact i64 %6, %7 + %9 = trunc i64 %8 to i32 + %10 = zext i32 %9 to i64 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_43.mlir b/benchmarks/LLVMIR/7_function_43.mlir new file mode 100644 index 0000000..255560e --- /dev/null +++ b/benchmarks/LLVMIR/7_function_43.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = ashr i64 %2, %1 + %5 = select i1 %0, i64 %1, i64 %4 + %6 = select i1 %0, i64 %4, i64 %2 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = urem i64 %5, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_44.mlir b/benchmarks/LLVMIR/7_function_44.mlir new file mode 100644 index 0000000..5de6449 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_44.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i1 %2) { + %4 = urem i64 %0, %0 + %5 = urem i64 %4, %1 + %6 = select i1 %2, i64 %0, i64 %4 + %7 = xor i64 %6, %5 + %8 = sdiv i64 %7, %6 + %9 = xor i64 %5, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_45.mlir b/benchmarks/LLVMIR/7_function_45.mlir new file mode 100644 index 0000000..f9f7fdd --- /dev/null +++ b/benchmarks/LLVMIR/7_function_45.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %2, %1 + %5 = xor i64 %1, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = and i64 %0, %7 + %9 = trunc i64 %8 to i32 + %10 = zext i32 %9 to i64 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_46.mlir b/benchmarks/LLVMIR/7_function_46.mlir new file mode 100644 index 0000000..1f98742 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_46.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp sge i64 %0, %0 + %5 = ashr exact i64 %0, %0 + %6 = urem i64 %0, %2 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = ashr exact i64 %1, %8 + %10 = select i1 %4, i64 %5, i64 %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_47.mlir b/benchmarks/LLVMIR/7_function_47.mlir new file mode 100644 index 0000000..dbdf69d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_47.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2, i1 %3) { + %5 = trunc i64 %0 to i32 + %6 = zext i32 %5 to i64 + %7 = ashr i64 %1, %2 + %8 = xor i64 %6, %7 + %9 = select i1 %3, i64 %0, i64 %6 + %10 = xor i64 %8, %9 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_48.mlir b/benchmarks/LLVMIR/7_function_48.mlir new file mode 100644 index 0000000..0b3eacb --- /dev/null +++ b/benchmarks/LLVMIR/7_function_48.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = udiv i64 %4, %1 + %6 = srem i64 %2, %5 + %7 = xor i64 %5, %6 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_49.mlir b/benchmarks/LLVMIR/7_function_49.mlir new file mode 100644 index 0000000..b00d606 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_49.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = sdiv i64 %0, %4 + %6 = ashr i64 %0, %5 + %7 = urem i64 %6, %2 + %8 = lshr exact i64 %6, %5 + %9 = or disjoint i64 %7, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_5.mlir b/benchmarks/LLVMIR/7_function_5.mlir new file mode 100644 index 0000000..0f190f5 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_5.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = and i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = sext i32 %3 to i64 + %5 = and i64 %2, %4 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_50.mlir b/benchmarks/LLVMIR/7_function_50.mlir new file mode 100644 index 0000000..65ad9b7 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_50.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %2, %0 + %5 = lshr exact i64 %4, %2 + %6 = udiv i64 %1, %5 + %7 = sdiv i64 %0, %6 + %8 = udiv i64 %6, %1 + %9 = lshr i64 %7, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_51.mlir b/benchmarks/LLVMIR/7_function_51.mlir new file mode 100644 index 0000000..b27b2db --- /dev/null +++ b/benchmarks/LLVMIR/7_function_51.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2, i1 %3) { + %5 = or i64 %0, %1 + %6 = select i1 %3, i64 %1, i64 %2 + %7 = select i1 %3, i64 %6, i64 %1 + %8 = udiv i64 %7, %6 + %9 = xor i64 %2, %8 + %10 = udiv i64 %2, %9 + %11 = icmp uge i64 %5, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_52.mlir b/benchmarks/LLVMIR/7_function_52.mlir new file mode 100644 index 0000000..34f7057 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_52.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = zext i32 %4 to i64 + %6 = srem i64 %5, %2 + %7 = or i64 %1, %6 + %8 = sext i32 %4 to i64 + %9 = and i64 %7, %8 + %10 = udiv i64 %5, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_53.mlir b/benchmarks/LLVMIR/7_function_53.mlir new file mode 100644 index 0000000..58e79fa --- /dev/null +++ b/benchmarks/LLVMIR/7_function_53.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = srem i64 %2, %2 + %7 = urem i64 %6, %1 + %8 = udiv i64 %1, %7 + %9 = or i64 %5, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_54.mlir b/benchmarks/LLVMIR/7_function_54.mlir new file mode 100644 index 0000000..57a2b51 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_54.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %2 to i32 + %5 = zext i32 %4 to i64 + %6 = lshr exact i64 %1, %5 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = urem i64 %0, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_55.mlir b/benchmarks/LLVMIR/7_function_55.mlir new file mode 100644 index 0000000..7f4f3f8 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_55.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0) { + %2 = srem i64 %0, %0 + %3 = trunc i64 %2 to i32 + %4 = sext i32 %3 to i64 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + ret i64 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_56.mlir b/benchmarks/LLVMIR/7_function_56.mlir new file mode 100644 index 0000000..0383b1d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_56.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1) { + %3 = zext i32 %0 to i64 + %4 = and i64 %3, %3 + %5 = trunc i64 %1 to i32 + %6 = sext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = or i64 %4, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_57.mlir b/benchmarks/LLVMIR/7_function_57.mlir new file mode 100644 index 0000000..86cb9f7 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_57.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %1, %0 + %5 = srem i64 %0, %4 + %6 = or i64 %2, %2 + %7 = and i64 %5, %6 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_58.mlir b/benchmarks/LLVMIR/7_function_58.mlir new file mode 100644 index 0000000..cc8eb3f --- /dev/null +++ b/benchmarks/LLVMIR/7_function_58.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = and i64 %2, %1 + %6 = urem i64 %5, %1 + %7 = srem i64 %4, %6 + %8 = srem i64 %7, %6 + %9 = and i64 %6, %8 + %10 = icmp sge i64 %7, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_59.mlir b/benchmarks/LLVMIR/7_function_59.mlir new file mode 100644 index 0000000..c43991c --- /dev/null +++ b/benchmarks/LLVMIR/7_function_59.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = lshr i64 %1, %4 + %6 = ashr exact i64 %4, %5 + %7 = and i64 %4, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_6.mlir b/benchmarks/LLVMIR/7_function_6.mlir new file mode 100644 index 0000000..7e3713c --- /dev/null +++ b/benchmarks/LLVMIR/7_function_6.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr i64 %0, %0 + %5 = or disjoint i64 %4, %0 + %6 = xor i64 %1, %2 + %7 = udiv i64 %5, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_60.mlir b/benchmarks/LLVMIR/7_function_60.mlir new file mode 100644 index 0000000..e537e1d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_60.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %1, %1 + %5 = or i64 %4, %2 + %6 = or i64 %5, %0 + %7 = sdiv exact i64 %0, %6 + %8 = xor i64 %7, %0 + %9 = srem i64 %0, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_61.mlir b/benchmarks/LLVMIR/7_function_61.mlir new file mode 100644 index 0000000..2e8da0d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_61.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i32 %2) { + %4 = udiv i64 %0, %1 + %5 = icmp sgt i64 %4, %1 + %6 = zext i32 %2 to i64 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = select i1 %5, i64 %8, i64 %1 + %10 = icmp uge i64 %9, %8 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_62.mlir b/benchmarks/LLVMIR/7_function_62.mlir new file mode 100644 index 0000000..6261876 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_62.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = xor i64 %1, %2 + %7 = or disjoint i64 %5, %6 + %8 = xor i64 %0, %7 + %9 = urem i64 %8, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_63.mlir b/benchmarks/LLVMIR/7_function_63.mlir new file mode 100644 index 0000000..858d834 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_63.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = lshr i64 %2, %2 + %6 = udiv i64 %4, %5 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = sdiv i64 %8, %0 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_64.mlir b/benchmarks/LLVMIR/7_function_64.mlir new file mode 100644 index 0000000..63472a9 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_64.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %2 to i32 + %5 = zext i32 %4 to i64 + %6 = ashr exact i64 %1, %5 + %7 = xor i64 %0, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_65.mlir b/benchmarks/LLVMIR/7_function_65.mlir new file mode 100644 index 0000000..98d95d1 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_65.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = and i64 %4, %1 + %6 = and i64 %5, %1 + %7 = sdiv i64 %5, %6 + %8 = ashr i64 %5, %7 + %9 = srem i64 %8, %2 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_66.mlir b/benchmarks/LLVMIR/7_function_66.mlir new file mode 100644 index 0000000..1be499a --- /dev/null +++ b/benchmarks/LLVMIR/7_function_66.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = urem i64 %5, %1 + %7 = icmp ule i64 %5, %6 + %8 = udiv i64 %1, %2 + %9 = urem i64 %8, %1 + %10 = select i1 %7, i64 %1, i64 %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_67.mlir b/benchmarks/LLVMIR/7_function_67.mlir new file mode 100644 index 0000000..89ef304 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_67.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %1, %2 + %5 = xor i64 %4, %4 + %6 = udiv i64 %4, %5 + %7 = urem i64 %6, %4 + %8 = udiv i64 %0, %7 + %9 = ashr i64 %8, %6 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_68.mlir b/benchmarks/LLVMIR/7_function_68.mlir new file mode 100644 index 0000000..696ace0 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_68.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp slt i64 %0, %0 + %5 = select i1 %4, i64 %1, i64 %0 + %6 = srem i64 %5, %0 + %7 = and i64 %6, %6 + %8 = trunc i64 %7 to i1 + %9 = xor i64 %1, %2 + %10 = select i1 %8, i64 %7, i64 %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_69.mlir b/benchmarks/LLVMIR/7_function_69.mlir new file mode 100644 index 0000000..2ae7b03 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_69.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %2 + %5 = and i64 %1, %2 + %6 = ashr i64 %4, %5 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = or i64 %8, %1 + %10 = or i64 %6, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_7.mlir b/benchmarks/LLVMIR/7_function_7.mlir new file mode 100644 index 0000000..34ecf1d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_7.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = lshr exact i64 %2, %0 + %6 = and i64 %1, %5 + %7 = lshr exact i64 %0, %6 + %8 = urem i64 %7, %6 + %9 = sext i32 %3 to i64 + %10 = or i64 %9, %8 + %11 = icmp ult i64 %8, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_70.mlir b/benchmarks/LLVMIR/7_function_70.mlir new file mode 100644 index 0000000..0c96d8c --- /dev/null +++ b/benchmarks/LLVMIR/7_function_70.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = ashr exact i64 %0, %0 + %4 = sdiv exact i64 %0, %3 + %5 = srem i64 %0, %1 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = xor i64 %4, %7 + %9 = trunc i64 %8 to i1 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_71.mlir b/benchmarks/LLVMIR/7_function_71.mlir new file mode 100644 index 0000000..b19b641 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_71.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %0 + %5 = srem i64 %1, %2 + %6 = udiv i64 %0, %5 + %7 = or i64 %6, %2 + %8 = xor i64 %4, %7 + %9 = xor i64 %2, %1 + %10 = srem i64 %8, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_72.mlir b/benchmarks/LLVMIR/7_function_72.mlir new file mode 100644 index 0000000..7e8bd9d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_72.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr exact i64 %2, %1 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = sdiv i64 %1, %6 + %8 = udiv i64 %0, %7 + %9 = srem i64 %8, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_73.mlir b/benchmarks/LLVMIR/7_function_73.mlir new file mode 100644 index 0000000..70b6880 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_73.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0, i64 %1) { + %3 = zext i32 %0 to i64 + %4 = and i64 %3, %1 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_74.mlir b/benchmarks/LLVMIR/7_function_74.mlir new file mode 100644 index 0000000..20aa01d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_74.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i32 %2) { + %4 = zext i32 %2 to i64 + %5 = lshr exact i64 %1, %4 + %6 = udiv i64 %5, %0 + %7 = xor i64 %6, %5 + %8 = xor i64 %0, %7 + %9 = xor i64 %8, %1 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_75.mlir b/benchmarks/LLVMIR/7_function_75.mlir new file mode 100644 index 0000000..614fc8e --- /dev/null +++ b/benchmarks/LLVMIR/7_function_75.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = trunc i64 %4 to i1 + %6 = udiv i64 %0, %0 + %7 = srem i64 %4, %0 + %8 = xor i64 %6, %7 + %9 = select i1 %5, i64 %2, i64 %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_76.mlir b/benchmarks/LLVMIR/7_function_76.mlir new file mode 100644 index 0000000..8f738e1 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_76.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2, i1 %3) { + %5 = udiv i64 %0, %1 + %6 = udiv i64 %5, %5 + %7 = udiv i64 %6, %2 + %8 = or i64 %7, %0 + %9 = select i1 %3, i64 %5, i64 %1 + %10 = or i64 %8, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_77.mlir b/benchmarks/LLVMIR/7_function_77.mlir new file mode 100644 index 0000000..5885a9a --- /dev/null +++ b/benchmarks/LLVMIR/7_function_77.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2, i1 %3) { + %5 = sdiv exact i64 %0, %0 + %6 = ashr i64 %5, %0 + %7 = xor i64 %6, %1 + %8 = and i64 %7, %2 + %9 = select i1 %3, i64 %6, i64 %8 + %10 = udiv i64 %9, %5 + %11 = udiv i64 %8, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_78.mlir b/benchmarks/LLVMIR/7_function_78.mlir new file mode 100644 index 0000000..a39164f --- /dev/null +++ b/benchmarks/LLVMIR/7_function_78.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1) { + %3 = srem i64 %0, %0 + %4 = sext i32 %1 to i64 + %5 = udiv i64 %4, %3 + %6 = trunc i64 %4 to i32 + %7 = sext i32 %6 to i64 + %8 = or i64 %5, %7 + %9 = icmp ule i64 %3, %8 + ret i1 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_79.mlir b/benchmarks/LLVMIR/7_function_79.mlir new file mode 100644 index 0000000..677906a --- /dev/null +++ b/benchmarks/LLVMIR/7_function_79.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = or disjoint i64 %0, %0 + %5 = select i1 %1, i64 %2, i64 %4 + %6 = srem i64 %4, %5 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = or i64 %0, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_8.mlir b/benchmarks/LLVMIR/7_function_8.mlir new file mode 100644 index 0000000..78d5f74 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_8.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i1 %0, i64 %1, i64 %2) { + %4 = icmp ule i64 %1, %1 + %5 = select i1 %4, i64 %2, i64 %1 + %6 = select i1 %0, i64 %1, i64 %5 + %7 = or disjoint i64 %2, %1 + %8 = urem i64 %5, %7 + %9 = or i64 %8, %7 + %10 = icmp ne i64 %6, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_80.mlir b/benchmarks/LLVMIR/7_function_80.mlir new file mode 100644 index 0000000..013fb11 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_80.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp eq i64 %0, %1 + %5 = udiv i64 %2, %1 + %6 = select i1 %4, i64 %2, i64 %5 + %7 = or i64 %0, %2 + %8 = icmp ult i64 %1, %7 + %9 = select i1 %8, i64 %6, i64 %0 + %10 = ashr exact i64 %6, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_81.mlir b/benchmarks/LLVMIR/7_function_81.mlir new file mode 100644 index 0000000..76e60d4 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_81.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = zext i32 %0 to i64 + %5 = lshr exact i64 %4, %1 + %6 = lshr exact i64 %4, %5 + %7 = zext i32 %0 to i64 + %8 = xor i64 %2, %7 + %9 = srem i64 %5, %8 + %10 = or disjoint i64 %6, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_82.mlir b/benchmarks/LLVMIR/7_function_82.mlir new file mode 100644 index 0000000..a041d02 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_82.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %2 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = ashr i64 %1, %7 + %9 = or i64 %0, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_83.mlir b/benchmarks/LLVMIR/7_function_83.mlir new file mode 100644 index 0000000..6b96484 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_83.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = sdiv i64 %8, %2 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_84.mlir b/benchmarks/LLVMIR/7_function_84.mlir new file mode 100644 index 0000000..c128bae --- /dev/null +++ b/benchmarks/LLVMIR/7_function_84.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %0, %1 + %5 = or disjoint i64 %4, %0 + %6 = and i64 %2, %5 + %7 = xor i64 %6, %1 + %8 = and i64 %4, %7 + %9 = srem i64 %8, %4 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_85.mlir b/benchmarks/LLVMIR/7_function_85.mlir new file mode 100644 index 0000000..85650cc --- /dev/null +++ b/benchmarks/LLVMIR/7_function_85.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = select i1 %0, i64 %1, i64 %1 + %5 = xor i64 %4, %2 + %6 = xor i64 %5, %5 + %7 = and i64 %4, %6 + %8 = xor i64 %4, %2 + %9 = urem i64 %7, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_86.mlir b/benchmarks/LLVMIR/7_function_86.mlir new file mode 100644 index 0000000..118407c --- /dev/null +++ b/benchmarks/LLVMIR/7_function_86.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1, i64 %2) { + %4 = sext i32 %1 to i64 + %5 = or disjoint i64 %4, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = srem i64 %7, %2 + %9 = udiv i64 %0, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_87.mlir b/benchmarks/LLVMIR/7_function_87.mlir new file mode 100644 index 0000000..46f54b7 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_87.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %2, i64 %0 + %5 = urem i64 %4, %4 + %6 = udiv i64 %0, %5 + %7 = ashr exact i64 %4, %5 + %8 = xor i64 %7, %2 + %9 = lshr exact i64 %7, %8 + %10 = icmp slt i64 %6, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_88.mlir b/benchmarks/LLVMIR/7_function_88.mlir new file mode 100644 index 0000000..dfe23f8 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_88.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1, i32 %2) { + %4 = sext i32 %2 to i64 + %5 = select i1 %1, i64 %0, i64 %4 + %6 = srem i64 %0, %5 + %7 = or i64 %6, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_89.mlir b/benchmarks/LLVMIR/7_function_89.mlir new file mode 100644 index 0000000..7264f28 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_89.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i32 %2) { + %4 = and i64 %0, %1 + %5 = sext i32 %2 to i64 + %6 = udiv i64 %5, %1 + %7 = udiv i64 %4, %6 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_9.mlir b/benchmarks/LLVMIR/7_function_9.mlir new file mode 100644 index 0000000..0dde962 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_9.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %1, %2 + %5 = and i64 %1, %4 + %6 = urem i64 %5, %1 + %7 = lshr i64 %0, %6 + %8 = or i64 %0, %7 + %9 = urem i64 %0, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_90.mlir b/benchmarks/LLVMIR/7_function_90.mlir new file mode 100644 index 0000000..6967012 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_90.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0) { + %2 = trunc i64 %0 to i32 + %3 = zext i32 %2 to i64 + %4 = trunc i64 %3 to i32 + %5 = zext i32 %4 to i64 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = trunc i64 %7 to i32 + ret i32 %8 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_91.mlir b/benchmarks/LLVMIR/7_function_91.mlir new file mode 100644 index 0000000..b6aae56 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_91.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = and i64 %0, %1 + %6 = ashr exact i64 %0, %5 + %7 = srem i64 %0, %6 + %8 = srem i64 %7, %2 + %9 = sext i32 %3 to i64 + %10 = urem i64 %9, %9 + %11 = icmp ne i64 %8, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_92.mlir b/benchmarks/LLVMIR/7_function_92.mlir new file mode 100644 index 0000000..642db0e --- /dev/null +++ b/benchmarks/LLVMIR/7_function_92.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = and i64 %1, %0 + %7 = xor i64 %5, %6 + %8 = trunc i64 %7 to i1 + %9 = select i1 %8, i64 %2, i64 %5 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_93.mlir b/benchmarks/LLVMIR/7_function_93.mlir new file mode 100644 index 0000000..09eb89f --- /dev/null +++ b/benchmarks/LLVMIR/7_function_93.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = udiv i64 %4, %1 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = xor i64 %1, %2 + %9 = udiv i64 %7, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_94.mlir b/benchmarks/LLVMIR/7_function_94.mlir new file mode 100644 index 0000000..7761140 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_94.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv exact i64 %0, %1 + %5 = srem i64 %2, %2 + %6 = sdiv exact i64 %5, %0 + %7 = srem i64 %0, %6 + %8 = lshr exact i64 %7, %0 + %9 = sdiv i64 %4, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_95.mlir b/benchmarks/LLVMIR/7_function_95.mlir new file mode 100644 index 0000000..097ce2b --- /dev/null +++ b/benchmarks/LLVMIR/7_function_95.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %0, %0 + %5 = xor i64 %4, %0 + %6 = ashr exact i64 %1, %2 + %7 = udiv i64 %5, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_96.mlir b/benchmarks/LLVMIR/7_function_96.mlir new file mode 100644 index 0000000..c436860 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_96.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = ashr exact i64 %0, %0 + %4 = ashr i64 %3, %0 + %5 = ashr exact i64 %0, %4 + %6 = sdiv i64 %0, %5 + %7 = xor i64 %3, %1 + %8 = xor i64 %6, %7 + %9 = trunc i64 %8 to i32 + ret i32 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_97.mlir b/benchmarks/LLVMIR/7_function_97.mlir new file mode 100644 index 0000000..487a79d --- /dev/null +++ b/benchmarks/LLVMIR/7_function_97.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i32 %1) { + %3 = urem i64 %0, %0 + %4 = zext i32 %1 to i64 + %5 = lshr exact i64 %3, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = xor i64 %3, %7 + %9 = ashr i64 %0, %8 + ret i64 %9 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_98.mlir b/benchmarks/LLVMIR/7_function_98.mlir new file mode 100644 index 0000000..1bacc0c --- /dev/null +++ b/benchmarks/LLVMIR/7_function_98.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = or i64 %0, %0 + %5 = udiv i64 %0, %4 + %6 = icmp sgt i64 %5, %4 + %7 = ashr i64 %4, %1 + %8 = select i1 %6, i64 %7, i64 %2 + %9 = and i64 %0, %8 + %10 = ashr i64 %9, %5 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/7_function_99.mlir b/benchmarks/LLVMIR/7_function_99.mlir new file mode 100644 index 0000000..ca4a108 --- /dev/null +++ b/benchmarks/LLVMIR/7_function_99.mlir @@ -0,0 +1,17 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %0, %1 + %5 = and i64 %1, %2 + %6 = sdiv exact i64 %4, %5 + %7 = trunc i64 %6 to i1 + %8 = trunc i64 %4 to i32 + %9 = sext i32 %8 to i64 + %10 = select i1 %7, i64 %1, i64 %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_0.mlir b/benchmarks/LLVMIR/8_function_0.mlir new file mode 100644 index 0000000..41fa52c --- /dev/null +++ b/benchmarks/LLVMIR/8_function_0.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %0 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = ashr exact i64 %0, %6 + %8 = or disjoint i64 %1, %2 + %9 = udiv i64 %8, %2 + %10 = and i64 %7, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_1.mlir b/benchmarks/LLVMIR/8_function_1.mlir new file mode 100644 index 0000000..8c8e2db --- /dev/null +++ b/benchmarks/LLVMIR/8_function_1.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i32 %1, i1 %2) { + %4 = zext i32 %0 to i64 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = srem i64 %4, %6 + %8 = sext i32 %1 to i64 + %9 = select i1 %2, i64 %4, i64 %8 + %10 = srem i64 %8, %9 + %11 = srem i64 %7, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_10.mlir b/benchmarks/LLVMIR/8_function_10.mlir new file mode 100644 index 0000000..b9ea92e --- /dev/null +++ b/benchmarks/LLVMIR/8_function_10.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = or i64 %0, %4 + %6 = xor i64 %5, %2 + %7 = trunc i64 %6 to i1 + %8 = lshr i64 %4, %2 + %9 = icmp slt i64 %8, %6 + %10 = select i1 %9, i64 %4, i64 %6 + %11 = select i1 %7, i64 %10, i64 %2 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_11.mlir b/benchmarks/LLVMIR/8_function_11.mlir new file mode 100644 index 0000000..bad0c23 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_11.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = lshr i64 %0, %1 + %6 = ashr i64 %0, %2 + %7 = urem i64 %0, %6 + %8 = urem i64 %7, %5 + %9 = sdiv i64 %5, %8 + %10 = zext i32 %3 to i64 + %11 = and i64 %9, %10 + %12 = trunc i64 %11 to i32 + ret i32 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_12.mlir b/benchmarks/LLVMIR/8_function_12.mlir new file mode 100644 index 0000000..c23a44a --- /dev/null +++ b/benchmarks/LLVMIR/8_function_12.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = trunc i64 %2 to i32 + %6 = sext i32 %5 to i64 + %7 = lshr i64 %4, %6 + %8 = and i64 %0, %4 + %9 = sdiv exact i64 %1, %8 + %10 = lshr i64 %7, %9 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_13.mlir b/benchmarks/LLVMIR/8_function_13.mlir new file mode 100644 index 0000000..969bd7a --- /dev/null +++ b/benchmarks/LLVMIR/8_function_13.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = urem i64 %0, %0 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = or disjoint i64 %3, %1 + %7 = and i64 %0, %6 + %8 = xor i64 %5, %7 + %9 = trunc i64 %8 to i32 + %10 = zext i32 %9 to i64 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_14.mlir b/benchmarks/LLVMIR/8_function_14.mlir new file mode 100644 index 0000000..16f2f34 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_14.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i32 %2, i1 %3) { + %5 = sext i32 %2 to i64 + %6 = ashr exact i64 %1, %5 + %7 = udiv i64 %0, %6 + %8 = urem i64 %7, %0 + %9 = select i1 %3, i64 %1, i64 %0 + %10 = lshr exact i64 %9, %8 + %11 = urem i64 %8, %10 + %12 = icmp ule i64 %7, %11 + ret i1 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_15.mlir b/benchmarks/LLVMIR/8_function_15.mlir new file mode 100644 index 0000000..1a19638 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_15.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = ashr i64 %0, %1 + %6 = urem i64 %5, %1 + %7 = icmp ult i64 %0, %6 + %8 = sdiv i64 %0, %5 + %9 = select i1 %7, i64 %2, i64 %8 + %10 = zext i32 %3 to i64 + %11 = and i64 %9, %10 + %12 = trunc i64 %11 to i32 + ret i32 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_16.mlir b/benchmarks/LLVMIR/8_function_16.mlir new file mode 100644 index 0000000..f6662d4 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_16.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i32 %1, i64 %2) { + %4 = sext i32 %1 to i64 + %5 = or disjoint i64 %0, %4 + %6 = srem i64 %4, %2 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = urem i64 %0, %8 + %10 = urem i64 %9, %2 + %11 = sdiv exact i64 %5, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_17.mlir b/benchmarks/LLVMIR/8_function_17.mlir new file mode 100644 index 0000000..57a951c --- /dev/null +++ b/benchmarks/LLVMIR/8_function_17.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0, i64 %1, i64 %2) { + %4 = zext i32 %0 to i64 + %5 = urem i64 %4, %1 + %6 = urem i64 %1, %4 + %7 = sdiv exact i64 %2, %4 + %8 = and i64 %6, %7 + %9 = xor i64 %1, %8 + %10 = ashr i64 %5, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_18.mlir b/benchmarks/LLVMIR/8_function_18.mlir new file mode 100644 index 0000000..705e822 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_18.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = zext i32 %4 to i64 + %6 = lshr exact i64 %1, %2 + %7 = urem i64 %5, %6 + %8 = lshr exact i64 %5, %7 + %9 = trunc i64 %2 to i32 + %10 = zext i32 %9 to i64 + %11 = icmp ult i64 %8, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_19.mlir b/benchmarks/LLVMIR/8_function_19.mlir new file mode 100644 index 0000000..43a7901 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_19.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = or i64 %0, %1 + %5 = or disjoint i64 %4, %2 + %6 = urem i64 %5, %4 + %7 = trunc i64 %6 to i1 + %8 = select i1 %7, i64 %2, i64 %6 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + %11 = icmp ugt i64 %10, %8 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_2.mlir b/benchmarks/LLVMIR/8_function_2.mlir new file mode 100644 index 0000000..4268979 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_2.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i32 %1, i64 %2) { + %4 = sext i32 %1 to i64 + %5 = and i64 %4, %4 + %6 = sext i32 %1 to i64 + %7 = urem i64 %2, %6 + %8 = lshr exact i64 %5, %7 + %9 = and i64 %0, %8 + %10 = urem i64 %2, %4 + %11 = urem i64 %9, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_20.mlir b/benchmarks/LLVMIR/8_function_20.mlir new file mode 100644 index 0000000..bae93b6 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_20.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr i64 %0, %1 + %5 = srem i64 %4, %2 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = lshr exact i64 %7, %5 + %9 = udiv i64 %4, %8 + %10 = and i64 %9, %0 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_21.mlir b/benchmarks/LLVMIR/8_function_21.mlir new file mode 100644 index 0000000..c17d5a4 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_21.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %1 to i32 + %5 = zext i32 %4 to i64 + %6 = srem i64 %0, %5 + %7 = udiv i64 %2, %1 + %8 = and i64 %6, %7 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_22.mlir b/benchmarks/LLVMIR/8_function_22.mlir new file mode 100644 index 0000000..79ac201 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_22.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i1 + %5 = lshr i64 %0, %0 + %6 = ashr exact i64 %5, %2 + %7 = urem i64 %1, %6 + %8 = lshr i64 %2, %1 + %9 = select i1 %4, i64 %8, i64 %0 + %10 = select i1 %4, i64 %7, i64 %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_23.mlir b/benchmarks/LLVMIR/8_function_23.mlir new file mode 100644 index 0000000..fb3627d --- /dev/null +++ b/benchmarks/LLVMIR/8_function_23.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = udiv i64 %4, %0 + %6 = sdiv i64 %1, %4 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = srem i64 %5, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_24.mlir b/benchmarks/LLVMIR/8_function_24.mlir new file mode 100644 index 0000000..ed2ebb0 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_24.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %0 + %5 = trunc i64 %1 to i32 + %6 = zext i32 %5 to i64 + %7 = trunc i64 %2 to i32 + %8 = sext i32 %7 to i64 + %9 = udiv i64 %2, %8 + %10 = lshr exact i64 %6, %9 + %11 = icmp sle i64 %4, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_25.mlir b/benchmarks/LLVMIR/8_function_25.mlir new file mode 100644 index 0000000..a803cba --- /dev/null +++ b/benchmarks/LLVMIR/8_function_25.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i64 %2, i32 %3) { + %5 = select i1 %1, i64 %0, i64 %2 + %6 = sdiv exact i64 %0, %5 + %7 = sext i32 %3 to i64 + %8 = lshr exact i64 %6, %7 + %9 = lshr exact i64 %8, %7 + %10 = trunc i64 %9 to i32 + %11 = sext i32 %10 to i64 + %12 = trunc i64 %11 to i1 + ret i1 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_26.mlir b/benchmarks/LLVMIR/8_function_26.mlir new file mode 100644 index 0000000..be736d4 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_26.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i32 %1, i64 %2) { + %4 = and i64 %0, %0 + %5 = sext i32 %1 to i64 + %6 = udiv i64 %0, %5 + %7 = and i64 %6, %2 + %8 = ashr exact i64 %7, %6 + %9 = udiv i64 %6, %8 + %10 = ashr i64 %4, %9 + %11 = sdiv i64 %10, %8 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_27.mlir b/benchmarks/LLVMIR/8_function_27.mlir new file mode 100644 index 0000000..6b74228 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_27.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %0, i64 %2 + %5 = ashr exact i64 %4, %0 + %6 = and i64 %0, %5 + %7 = lshr exact i64 %0, %0 + %8 = ashr exact i64 %6, %7 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + %11 = urem i64 %0, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_28.mlir b/benchmarks/LLVMIR/8_function_28.mlir new file mode 100644 index 0000000..11697c4 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_28.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1, i64 %2) { + %4 = trunc i64 %0 to i1 + %5 = zext i32 %1 to i64 + %6 = select i1 %4, i64 %5, i64 %2 + %7 = zext i32 %1 to i64 + %8 = ashr exact i64 %6, %7 + %9 = trunc i64 %2 to i32 + %10 = zext i32 %9 to i64 + %11 = icmp uge i64 %8, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_29.mlir b/benchmarks/LLVMIR/8_function_29.mlir new file mode 100644 index 0000000..9fd484d --- /dev/null +++ b/benchmarks/LLVMIR/8_function_29.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2, i1 %3) { + %5 = and i64 %0, %1 + %6 = srem i64 %2, %0 + %7 = xor i64 %5, %6 + %8 = xor i64 %2, %1 + %9 = select i1 %3, i64 %5, i64 %8 + %10 = srem i64 %7, %9 + %11 = lshr i64 %10, %0 + %12 = trunc i64 %11 to i32 + ret i32 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_3.mlir b/benchmarks/LLVMIR/8_function_3.mlir new file mode 100644 index 0000000..e272b6e --- /dev/null +++ b/benchmarks/LLVMIR/8_function_3.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = zext i32 %3 to i64 + %5 = ashr exact i64 %4, %1 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = urem i64 %0, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_30.mlir b/benchmarks/LLVMIR/8_function_30.mlir new file mode 100644 index 0000000..a6259dd --- /dev/null +++ b/benchmarks/LLVMIR/8_function_30.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i32 %1, i64 %2) { + %4 = xor i64 %0, %0 + %5 = zext i32 %1 to i64 + %6 = and i64 %4, %5 + %7 = ashr i64 %0, %6 + %8 = and i64 %7, %2 + %9 = lshr i64 %6, %8 + %10 = ashr i64 %7, %9 + %11 = icmp slt i64 %6, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_31.mlir b/benchmarks/LLVMIR/8_function_31.mlir new file mode 100644 index 0000000..51ca86b --- /dev/null +++ b/benchmarks/LLVMIR/8_function_31.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %0 + %5 = udiv i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = lshr i64 %5, %2 + %9 = icmp ult i64 %7, %8 + %10 = srem i64 %7, %4 + %11 = select i1 %9, i64 %2, i64 %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_32.mlir b/benchmarks/LLVMIR/8_function_32.mlir new file mode 100644 index 0000000..2ddbbad --- /dev/null +++ b/benchmarks/LLVMIR/8_function_32.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i1 %1, i64 %2) { + %4 = select i1 %1, i64 %2, i64 %2 + %5 = and i64 %2, %4 + %6 = lshr i64 %5, %4 + %7 = lshr i64 %4, %6 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + %10 = select i1 %0, i64 %9, i64 %2 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_33.mlir b/benchmarks/LLVMIR/8_function_33.mlir new file mode 100644 index 0000000..4455a9a --- /dev/null +++ b/benchmarks/LLVMIR/8_function_33.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = urem i64 %4, %2 + %6 = lshr i64 %5, %4 + %7 = trunc i64 %1 to i1 + %8 = select i1 %7, i64 %6, i64 %5 + %9 = urem i64 %6, %8 + %10 = and i64 %5, %9 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_34.mlir b/benchmarks/LLVMIR/8_function_34.mlir new file mode 100644 index 0000000..9a42b19 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_34.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr i64 %0, %1 + %5 = srem i64 %4, %1 + %6 = sdiv exact i64 %2, %5 + %7 = or disjoint i64 %4, %6 + %8 = or disjoint i64 %4, %4 + %9 = sdiv exact i64 %8, %6 + %10 = srem i64 %7, %9 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_35.mlir b/benchmarks/LLVMIR/8_function_35.mlir new file mode 100644 index 0000000..d9f72e1 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_35.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %0 + %5 = sdiv i64 %4, %2 + %6 = lshr exact i64 %0, %5 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_36.mlir b/benchmarks/LLVMIR/8_function_36.mlir new file mode 100644 index 0000000..3d4dbce --- /dev/null +++ b/benchmarks/LLVMIR/8_function_36.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2, i32 %3) { + %5 = urem i64 %1, %2 + %6 = zext i32 %3 to i64 + %7 = urem i64 %6, %6 + %8 = xor i64 %1, %7 + %9 = srem i64 %8, %5 + %10 = sdiv exact i64 %1, %9 + %11 = select i1 %0, i64 %5, i64 %10 + %12 = trunc i64 %11 to i32 + ret i32 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_37.mlir b/benchmarks/LLVMIR/8_function_37.mlir new file mode 100644 index 0000000..6cc3ce4 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_37.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = xor i64 %0, %1 + %5 = srem i64 %4, %0 + %6 = udiv i64 %1, %5 + %7 = or i64 %2, %6 + %8 = xor i64 %5, %7 + %9 = urem i64 %4, %8 + %10 = urem i64 %9, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_38.mlir b/benchmarks/LLVMIR/8_function_38.mlir new file mode 100644 index 0000000..5d11107 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_38.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = icmp ule i64 %0, %1 + %6 = or i64 %0, %1 + %7 = udiv i64 %1, %2 + %8 = xor i64 %6, %7 + %9 = xor i64 %0, %8 + %10 = and i64 %8, %9 + %11 = zext i32 %3 to i64 + %12 = select i1 %5, i64 %10, i64 %11 + ret i64 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_39.mlir b/benchmarks/LLVMIR/8_function_39.mlir new file mode 100644 index 0000000..7829f7e --- /dev/null +++ b/benchmarks/LLVMIR/8_function_39.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i1 %1, i64 %2) { + %4 = or i64 %0, %0 + %5 = ashr exact i64 %0, %4 + %6 = select i1 %1, i64 %2, i64 %0 + %7 = and i64 %6, %0 + %8 = or disjoint i64 %7, %6 + %9 = udiv i64 %8, %8 + %10 = or disjoint i64 %5, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_4.mlir b/benchmarks/LLVMIR/8_function_4.mlir new file mode 100644 index 0000000..0be9384 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_4.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2, i1 %3) { + %5 = udiv i64 %0, %1 + %6 = lshr exact i64 %2, %1 + %7 = ashr exact i64 %5, %6 + %8 = select i1 %3, i64 %2, i64 %0 + %9 = ashr i64 %8, %7 + %10 = or i64 %7, %9 + %11 = urem i64 %2, %10 + %12 = icmp ult i64 %10, %11 + ret i1 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_40.mlir b/benchmarks/LLVMIR/8_function_40.mlir new file mode 100644 index 0000000..ad934fb --- /dev/null +++ b/benchmarks/LLVMIR/8_function_40.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = zext i32 %4 to i64 + %6 = icmp uge i64 %5, %5 + %7 = select i1 %6, i64 %0, i64 %0 + %8 = or i64 %0, %7 + %9 = ashr exact i64 %2, %2 + %10 = or disjoint i64 %1, %9 + %11 = ashr i64 %8, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_41.mlir b/benchmarks/LLVMIR/8_function_41.mlir new file mode 100644 index 0000000..7c6c7b0 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_41.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp sge i64 %0, %1 + %5 = select i1 %4, i64 %2, i64 %0 + %6 = ashr exact i64 %2, %5 + %7 = and i64 %0, %6 + %8 = xor i64 %5, %7 + %9 = urem i64 %5, %8 + %10 = select i1 %4, i64 %7, i64 %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_42.mlir b/benchmarks/LLVMIR/8_function_42.mlir new file mode 100644 index 0000000..89db0af --- /dev/null +++ b/benchmarks/LLVMIR/8_function_42.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv exact i64 %0, %1 + %5 = trunc i64 %4 to i1 + %6 = lshr i64 %4, %2 + %7 = trunc i64 %6 to i32 + %8 = zext i32 %7 to i64 + %9 = srem i64 %4, %8 + %10 = lshr exact i64 %9, %6 + %11 = select i1 %5, i64 %2, i64 %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_43.mlir b/benchmarks/LLVMIR/8_function_43.mlir new file mode 100644 index 0000000..3de7666 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_43.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i32 %0, i1 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = select i1 %1, i64 %2, i64 %4 + %6 = ashr exact i64 %4, %5 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = urem i64 %4, %2 + %10 = udiv i64 %8, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_44.mlir b/benchmarks/LLVMIR/8_function_44.mlir new file mode 100644 index 0000000..bcda530 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_44.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv i64 %0, %1 + %5 = trunc i64 %4 to i32 + %6 = zext i32 %5 to i64 + %7 = urem i64 %4, %4 + %8 = and i64 %2, %7 + %9 = sdiv exact i64 %1, %0 + %10 = or disjoint i64 %8, %9 + %11 = icmp sge i64 %6, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_45.mlir b/benchmarks/LLVMIR/8_function_45.mlir new file mode 100644 index 0000000..750b0ad --- /dev/null +++ b/benchmarks/LLVMIR/8_function_45.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i32 %1, i64 %2) { + %4 = srem i64 %0, %0 + %5 = lshr exact i64 %0, %0 + %6 = urem i64 %4, %5 + %7 = sext i32 %1 to i64 + %8 = ashr i64 %6, %7 + %9 = and i64 %2, %2 + %10 = srem i64 %9, %6 + %11 = lshr i64 %8, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_46.mlir b/benchmarks/LLVMIR/8_function_46.mlir new file mode 100644 index 0000000..0b21310 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_46.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp ugt i64 %0, %1 + %5 = select i1 %4, i64 %0, i64 %0 + %6 = udiv i64 %0, %2 + %7 = sdiv i64 %5, %6 + %8 = sdiv exact i64 %7, %0 + %9 = trunc i64 %8 to i32 + %10 = zext i32 %9 to i64 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_47.mlir b/benchmarks/LLVMIR/8_function_47.mlir new file mode 100644 index 0000000..d0ffbf9 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_47.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = trunc i64 %4 to i1 + %6 = srem i64 %4, %4 + %7 = select i1 %5, i64 %6, i64 %1 + %8 = xor i64 %1, %1 + %9 = udiv i64 %8, %2 + %10 = srem i64 %7, %9 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_48.mlir b/benchmarks/LLVMIR/8_function_48.mlir new file mode 100644 index 0000000..d2fce51 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_48.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = sdiv exact i64 %0, %5 + %7 = udiv i64 %0, %2 + %8 = lshr exact i64 %1, %7 + %9 = urem i64 %5, %1 + %10 = xor i64 %8, %9 + %11 = srem i64 %6, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_49.mlir b/benchmarks/LLVMIR/8_function_49.mlir new file mode 100644 index 0000000..8d01ca2 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_49.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i1 %2, i32 %3) { + %5 = select i1 %2, i64 %0, i64 %0 + %6 = sext i32 %3 to i64 + %7 = udiv i64 %5, %6 + %8 = and i64 %1, %7 + %9 = select i1 %2, i64 %8, i64 %0 + %10 = and i64 %8, %9 + %11 = and i64 %0, %10 + %12 = trunc i64 %11 to i32 + ret i32 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_5.mlir b/benchmarks/LLVMIR/8_function_5.mlir new file mode 100644 index 0000000..6c3daf0 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_5.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %1, %1 + %5 = lshr exact i64 %1, %2 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = srem i64 %4, %7 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + %11 = icmp ne i64 %0, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_50.mlir b/benchmarks/LLVMIR/8_function_50.mlir new file mode 100644 index 0000000..897cc25 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_50.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2, i1 %3) { + %5 = ashr exact i64 %0, %0 + %6 = sdiv i64 %1, %2 + %7 = udiv i64 %5, %6 + %8 = or disjoint i64 %5, %7 + %9 = or i64 %8, %8 + %10 = select i1 %3, i64 %9, i64 %7 + %11 = lshr exact i64 %7, %10 + %12 = trunc i64 %11 to i1 + ret i1 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_51.mlir b/benchmarks/LLVMIR/8_function_51.mlir new file mode 100644 index 0000000..c7645f7 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_51.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = ashr i64 %0, %1 + %6 = and i64 %5, %5 + %7 = or disjoint i64 %5, %6 + %8 = xor i64 %2, %2 + %9 = zext i32 %3 to i64 + %10 = lshr exact i64 %8, %9 + %11 = sdiv exact i64 %7, %10 + %12 = trunc i64 %11 to i32 + ret i32 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_52.mlir b/benchmarks/LLVMIR/8_function_52.mlir new file mode 100644 index 0000000..b5093bd --- /dev/null +++ b/benchmarks/LLVMIR/8_function_52.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = sdiv i64 %0, %1 + %4 = trunc i64 %3 to i32 + %5 = sext i32 %4 to i64 + %6 = urem i64 %0, %5 + %7 = lshr exact i64 %0, %6 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_53.mlir b/benchmarks/LLVMIR/8_function_53.mlir new file mode 100644 index 0000000..c32f87a --- /dev/null +++ b/benchmarks/LLVMIR/8_function_53.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i1 + %4 = and i64 %0, %0 + %5 = select i1 %3, i64 %4, i64 %4 + %6 = lshr exact i64 %5, %1 + %7 = or i64 %6, %1 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_54.mlir b/benchmarks/LLVMIR/8_function_54.mlir new file mode 100644 index 0000000..767fcec --- /dev/null +++ b/benchmarks/LLVMIR/8_function_54.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i32 %2) { + %4 = or i64 %0, %0 + %5 = zext i32 %2 to i64 + %6 = lshr i64 %1, %5 + %7 = sext i32 %2 to i64 + %8 = urem i64 %6, %7 + %9 = and i64 %8, %7 + %10 = srem i64 %4, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_55.mlir b/benchmarks/LLVMIR/8_function_55.mlir new file mode 100644 index 0000000..df719f9 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_55.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = or i64 %4, %2 + %6 = udiv i64 %2, %4 + %7 = sdiv exact i64 %5, %6 + %8 = udiv i64 %0, %7 + %9 = urem i64 %4, %8 + %10 = trunc i64 %9 to i32 + %11 = zext i32 %10 to i64 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_56.mlir b/benchmarks/LLVMIR/8_function_56.mlir new file mode 100644 index 0000000..54a225e --- /dev/null +++ b/benchmarks/LLVMIR/8_function_56.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = sdiv exact i64 %0, %1 + %5 = trunc i64 %0 to i32 + %6 = zext i32 %5 to i64 + %7 = or i64 %1, %0 + %8 = urem i64 %2, %7 + %9 = sdiv i64 %6, %8 + %10 = srem i64 %4, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_57.mlir b/benchmarks/LLVMIR/8_function_57.mlir new file mode 100644 index 0000000..bad29a0 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_57.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = and i64 %0, %4 + %6 = icmp slt i64 %1, %2 + %7 = select i1 %6, i64 %4, i64 %4 + %8 = icmp ugt i64 %7, %5 + %9 = select i1 %8, i64 %0, i64 %7 + %10 = or i64 %7, %9 + %11 = icmp sgt i64 %5, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_58.mlir b/benchmarks/LLVMIR/8_function_58.mlir new file mode 100644 index 0000000..55831e0 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_58.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = sdiv i64 %1, %0 + %4 = and i64 %0, %3 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = urem i64 %3, %4 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = icmp slt i64 %6, %9 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_59.mlir b/benchmarks/LLVMIR/8_function_59.mlir new file mode 100644 index 0000000..a27234e --- /dev/null +++ b/benchmarks/LLVMIR/8_function_59.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = udiv i64 %2, %0 + %8 = udiv i64 %6, %7 + %9 = srem i64 %7, %1 + %10 = srem i64 %8, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_6.mlir b/benchmarks/LLVMIR/8_function_6.mlir new file mode 100644 index 0000000..b73f3a5 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_6.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2, i1 %3) { + %5 = zext i32 %0 to i64 + %6 = select i1 %3, i64 %2, i64 %5 + %7 = or i64 %2, %6 + %8 = srem i64 %7, %6 + %9 = xor i64 %7, %8 + %10 = udiv i64 %9, %7 + %11 = srem i64 %1, %10 + %12 = ashr exact i64 %5, %11 + ret i64 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_60.mlir b/benchmarks/LLVMIR/8_function_60.mlir new file mode 100644 index 0000000..a4a0376 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_60.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = trunc i64 %1 to i1 + %7 = select i1 %6, i64 %2, i64 %0 + %8 = srem i64 %1, %7 + %9 = xor i64 %0, %8 + %10 = sdiv i64 %5, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_61.mlir b/benchmarks/LLVMIR/8_function_61.mlir new file mode 100644 index 0000000..a53cb99 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_61.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %1 to i32 + %5 = zext i32 %4 to i64 + %6 = xor i64 %5, %2 + %7 = or i64 %0, %0 + %8 = srem i64 %7, %5 + %9 = xor i64 %6, %8 + %10 = lshr exact i64 %0, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_62.mlir b/benchmarks/LLVMIR/8_function_62.mlir new file mode 100644 index 0000000..ea9cea9 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_62.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = zext i32 %0 to i64 + %5 = udiv i64 %1, %2 + %6 = sdiv i64 %5, %2 + %7 = xor i64 %4, %6 + %8 = trunc i64 %2 to i32 + %9 = sext i32 %8 to i64 + %10 = ashr i64 %7, %9 + %11 = and i64 %10, %2 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_63.mlir b/benchmarks/LLVMIR/8_function_63.mlir new file mode 100644 index 0000000..505cd44 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_63.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %0 + %5 = icmp ule i64 %4, %2 + %6 = lshr i64 %1, %2 + %7 = sdiv exact i64 %4, %6 + %8 = select i1 %5, i64 %1, i64 %7 + %9 = urem i64 %0, %8 + %10 = lshr exact i64 %7, %8 + %11 = icmp ule i64 %9, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_64.mlir b/benchmarks/LLVMIR/8_function_64.mlir new file mode 100644 index 0000000..a02db30 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_64.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = lshr exact i64 %0, %1 + %5 = or disjoint i64 %1, %1 + %6 = udiv i64 %5, %2 + %7 = xor i64 %2, %0 + %8 = sdiv exact i64 %7, %2 + %9 = urem i64 %6, %8 + %10 = srem i64 %4, %9 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_65.mlir b/benchmarks/LLVMIR/8_function_65.mlir new file mode 100644 index 0000000..238aac6 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_65.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %2 + %5 = lshr i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = srem i64 %9, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_66.mlir b/benchmarks/LLVMIR/8_function_66.mlir new file mode 100644 index 0000000..4dc5d36 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_66.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %0 + %5 = trunc i64 %1 to i32 + %6 = sext i32 %5 to i64 + %7 = sdiv exact i64 %4, %2 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = srem i64 %6, %9 + %11 = and i64 %4, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_67.mlir b/benchmarks/LLVMIR/8_function_67.mlir new file mode 100644 index 0000000..8b31f5a --- /dev/null +++ b/benchmarks/LLVMIR/8_function_67.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = and i64 %2, %0 + %6 = or i64 %4, %5 + %7 = or i64 %2, %6 + %8 = sdiv i64 %4, %7 + %9 = and i64 %7, %8 + %10 = or disjoint i64 %4, %9 + %11 = icmp uge i64 %10, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_68.mlir b/benchmarks/LLVMIR/8_function_68.mlir new file mode 100644 index 0000000..8cb8abd --- /dev/null +++ b/benchmarks/LLVMIR/8_function_68.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = sdiv i64 %0, %0 + %4 = udiv i64 %0, %3 + %5 = srem i64 %4, %1 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_69.mlir b/benchmarks/LLVMIR/8_function_69.mlir new file mode 100644 index 0000000..3df46a8 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_69.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %1 + %5 = udiv i64 %2, %2 + %6 = sdiv exact i64 %4, %5 + %7 = srem i64 %4, %4 + %8 = or disjoint i64 %5, %7 + %9 = sdiv exact i64 %5, %8 + %10 = sdiv exact i64 %9, %2 + %11 = srem i64 %6, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_7.mlir b/benchmarks/LLVMIR/8_function_7.mlir new file mode 100644 index 0000000..cbc5cf7 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_7.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2, i1 %3) { + %5 = sext i32 %0 to i64 + %6 = and i64 %1, %5 + %7 = urem i64 %5, %6 + %8 = select i1 %3, i64 %6, i64 %7 + %9 = and i64 %1, %8 + %10 = and i64 %7, %9 + %11 = urem i64 %2, %10 + %12 = or i64 %7, %11 + ret i64 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_70.mlir b/benchmarks/LLVMIR/8_function_70.mlir new file mode 100644 index 0000000..375aa38 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_70.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i1 %1, i32 %2) { + %4 = sext i32 %2 to i64 + %5 = icmp eq i64 %4, %0 + %6 = select i1 %1, i64 %0, i64 %0 + %7 = select i1 %5, i64 %4, i64 %6 + %8 = lshr exact i64 %0, %4 + %9 = select i1 %1, i64 %7, i64 %8 + %10 = lshr exact i64 %0, %9 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_71.mlir b/benchmarks/LLVMIR/8_function_71.mlir new file mode 100644 index 0000000..6ee2bc5 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_71.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = or disjoint i64 %0, %0 + %5 = icmp sgt i64 %4, %1 + %6 = select i1 %5, i64 %4, i64 %2 + %7 = trunc i64 %6 to i1 + %8 = trunc i64 %6 to i1 + %9 = lshr i64 %0, %6 + %10 = select i1 %8, i64 %2, i64 %9 + %11 = select i1 %7, i64 %6, i64 %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_72.mlir b/benchmarks/LLVMIR/8_function_72.mlir new file mode 100644 index 0000000..8fc1cab --- /dev/null +++ b/benchmarks/LLVMIR/8_function_72.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = xor i64 %0, %0 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = udiv i64 %7, %1 + %9 = ashr i64 %4, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_73.mlir b/benchmarks/LLVMIR/8_function_73.mlir new file mode 100644 index 0000000..56c4021 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_73.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %2 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = udiv i64 %0, %6 + %8 = udiv i64 %7, %7 + %9 = xor i64 %8, %7 + %10 = ashr i64 %7, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_74.mlir b/benchmarks/LLVMIR/8_function_74.mlir new file mode 100644 index 0000000..e92059b --- /dev/null +++ b/benchmarks/LLVMIR/8_function_74.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %0 + %5 = and i64 %4, %4 + %6 = trunc i64 %5 to i1 + %7 = udiv i64 %0, %0 + %8 = or i64 %7, %5 + %9 = and i64 %1, %2 + %10 = select i1 %6, i64 %8, i64 %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_75.mlir b/benchmarks/LLVMIR/8_function_75.mlir new file mode 100644 index 0000000..ff1804b --- /dev/null +++ b/benchmarks/LLVMIR/8_function_75.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = urem i64 %0, %1 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = xor i64 %2, %2 + %8 = and i64 %6, %7 + %9 = trunc i64 %2 to i32 + %10 = sext i32 %9 to i64 + %11 = or i64 %8, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_76.mlir b/benchmarks/LLVMIR/8_function_76.mlir new file mode 100644 index 0000000..f2c04ef --- /dev/null +++ b/benchmarks/LLVMIR/8_function_76.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %0 + %5 = sdiv i64 %4, %1 + %6 = trunc i64 %2 to i1 + %7 = select i1 %6, i64 %0, i64 %2 + %8 = srem i64 %5, %7 + %9 = trunc i64 %8 to i32 + %10 = zext i32 %9 to i64 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_77.mlir b/benchmarks/LLVMIR/8_function_77.mlir new file mode 100644 index 0000000..6728a7e --- /dev/null +++ b/benchmarks/LLVMIR/8_function_77.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i1 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = xor i64 %5, %1 + %7 = select i1 %2, i64 %6, i64 %0 + %8 = sdiv i64 %1, %0 + %9 = srem i64 %7, %8 + %10 = or disjoint i64 %0, %9 + %11 = xor i64 %6, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_78.mlir b/benchmarks/LLVMIR/8_function_78.mlir new file mode 100644 index 0000000..c1f067f --- /dev/null +++ b/benchmarks/LLVMIR/8_function_78.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2, i1 %3) { + %5 = zext i32 %0 to i64 + %6 = or i64 %1, %2 + %7 = select i1 %3, i64 %1, i64 %2 + %8 = select i1 %3, i64 %2, i64 %7 + %9 = sdiv exact i64 %7, %5 + %10 = lshr i64 %8, %9 + %11 = urem i64 %6, %10 + %12 = udiv i64 %5, %11 + ret i64 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_79.mlir b/benchmarks/LLVMIR/8_function_79.mlir new file mode 100644 index 0000000..d348356 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_79.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i1 %2) { + %4 = udiv i64 %0, %0 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = select i1 %2, i64 %0, i64 %1 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = sdiv exact i64 %1, %9 + %11 = icmp ult i64 %6, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_8.mlir b/benchmarks/LLVMIR/8_function_8.mlir new file mode 100644 index 0000000..25bc002 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_8.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = or disjoint i64 %0, %1 + %6 = and i64 %0, %5 + %7 = xor i64 %6, %2 + %8 = and i64 %1, %1 + %9 = zext i32 %3 to i64 + %10 = and i64 %9, %0 + %11 = or i64 %8, %10 + %12 = icmp eq i64 %7, %11 + ret i1 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_80.mlir b/benchmarks/LLVMIR/8_function_80.mlir new file mode 100644 index 0000000..3cc6092 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_80.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = urem i64 %2, %2 + %6 = lshr i64 %2, %5 + %7 = or disjoint i64 %1, %1 + %8 = srem i64 %7, %6 + %9 = lshr exact i64 %6, %8 + %10 = srem i64 %4, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_81.mlir b/benchmarks/LLVMIR/8_function_81.mlir new file mode 100644 index 0000000..774efa2 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_81.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = trunc i64 %0 to i1 + %5 = select i1 %4, i64 %0, i64 %1 + %6 = sdiv exact i64 %2, %1 + %7 = ashr exact i64 %5, %6 + %8 = and i64 %7, %5 + %9 = sdiv exact i64 %8, %1 + %10 = sdiv i64 %7, %9 + %11 = ashr exact i64 %8, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_82.mlir b/benchmarks/LLVMIR/8_function_82.mlir new file mode 100644 index 0000000..47dbe02 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_82.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i1 %2) { + %4 = urem i64 %0, %1 + %5 = select i1 %2, i64 %1, i64 %1 + %6 = icmp sgt i64 %4, %5 + %7 = or i64 %1, %1 + %8 = select i1 %6, i64 %7, i64 %4 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_83.mlir b/benchmarks/LLVMIR/8_function_83.mlir new file mode 100644 index 0000000..b1de02a --- /dev/null +++ b/benchmarks/LLVMIR/8_function_83.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = udiv i64 %0, %0 + %4 = sdiv exact i64 %0, %1 + %5 = urem i64 %3, %4 + %6 = ashr exact i64 %3, %4 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = lshr exact i64 %5, %8 + %10 = trunc i64 %9 to i1 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_84.mlir b/benchmarks/LLVMIR/8_function_84.mlir new file mode 100644 index 0000000..353b9d0 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_84.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i32 %1) { + %3 = trunc i64 %0 to i32 + %4 = sext i32 %3 to i64 + %5 = zext i32 %1 to i64 + %6 = srem i64 %0, %5 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = and i64 %4, %8 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_85.mlir b/benchmarks/LLVMIR/8_function_85.mlir new file mode 100644 index 0000000..6475463 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_85.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %1 + %5 = trunc i64 %4 to i1 + %6 = trunc i64 %0 to i32 + %7 = zext i32 %6 to i64 + %8 = urem i64 %7, %2 + %9 = select i1 %5, i64 %8, i64 %8 + %10 = udiv i64 %2, %7 + %11 = icmp sgt i64 %9, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_86.mlir b/benchmarks/LLVMIR/8_function_86.mlir new file mode 100644 index 0000000..13d40f8 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_86.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i32 %2) { + %4 = udiv i64 %0, %1 + %5 = zext i32 %2 to i64 + %6 = lshr i64 %4, %5 + %7 = and i64 %1, %6 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + %10 = xor i64 %6, %9 + %11 = icmp sle i64 %10, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_87.mlir b/benchmarks/LLVMIR/8_function_87.mlir new file mode 100644 index 0000000..7c64866 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_87.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i32 %0, i64 %1, i64 %2) { + %4 = sext i32 %0 to i64 + %5 = urem i64 %4, %1 + %6 = lshr i64 %5, %1 + %7 = trunc i64 %2 to i32 + %8 = zext i32 %7 to i64 + %9 = ashr exact i64 %6, %8 + %10 = trunc i64 %9 to i32 + %11 = sext i32 %10 to i64 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_88.mlir b/benchmarks/LLVMIR/8_function_88.mlir new file mode 100644 index 0000000..31d5695 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_88.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = srem i64 %0, %0 + %5 = xor i64 %0, %4 + %6 = xor i64 %1, %2 + %7 = xor i64 %4, %6 + %8 = sdiv i64 %5, %7 + %9 = srem i64 %8, %1 + %10 = xor i64 %2, %0 + %11 = icmp ugt i64 %9, %10 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_89.mlir b/benchmarks/LLVMIR/8_function_89.mlir new file mode 100644 index 0000000..1bb7f35 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_89.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1) { + %3 = xor i64 %0, %1 + %4 = and i64 %1, %0 + %5 = sdiv exact i64 %3, %4 + %6 = trunc i64 %5 to i32 + %7 = zext i32 %6 to i64 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = trunc i64 %9 to i32 + ret i32 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_9.mlir b/benchmarks/LLVMIR/8_function_9.mlir new file mode 100644 index 0000000..917c50a --- /dev/null +++ b/benchmarks/LLVMIR/8_function_9.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr exact i64 %0, %1 + %5 = trunc i64 %2 to i32 + %6 = sext i32 %5 to i64 + %7 = urem i64 %6, %4 + %8 = and i64 %4, %1 + %9 = udiv i64 %7, %8 + %10 = srem i64 %9, %8 + %11 = sdiv i64 %4, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_90.mlir b/benchmarks/LLVMIR/8_function_90.mlir new file mode 100644 index 0000000..5dfe51d --- /dev/null +++ b/benchmarks/LLVMIR/8_function_90.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = and i64 %0, %0 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = icmp eq i64 %0, %6 + %8 = select i1 %7, i64 %1, i64 %2 + %9 = trunc i64 %8 to i32 + %10 = zext i32 %9 to i64 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_91.mlir b/benchmarks/LLVMIR/8_function_91.mlir new file mode 100644 index 0000000..cda5127 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_91.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1) { + %3 = srem i64 %0, %0 + %4 = or disjoint i64 %0, %3 + %5 = xor i64 %4, %0 + %6 = udiv i64 %4, %5 + %7 = sdiv i64 %6, %1 + %8 = trunc i64 %7 to i32 + %9 = sext i32 %8 to i64 + %10 = icmp sgt i64 %9, %4 + ret i1 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_92.mlir b/benchmarks/LLVMIR/8_function_92.mlir new file mode 100644 index 0000000..5dae0b0 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_92.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i1 %0, i64 %1) { + %3 = and i64 %1, %1 + %4 = udiv i64 %1, %3 + %5 = or i64 %3, %4 + %6 = select i1 %0, i64 %1, i64 %5 + %7 = trunc i64 %6 to i32 + %8 = sext i32 %7 to i64 + %9 = and i64 %8, %1 + %10 = urem i64 %8, %9 + ret i64 %10 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_93.mlir b/benchmarks/LLVMIR/8_function_93.mlir new file mode 100644 index 0000000..3ecdc56 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_93.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i1 %0, i64 %1, i64 %2) { + %4 = srem i64 %1, %2 + %5 = trunc i64 %4 to i32 + %6 = sext i32 %5 to i64 + %7 = udiv i64 %6, %1 + %8 = select i1 %0, i64 %6, i64 %7 + %9 = trunc i64 %8 to i32 + %10 = sext i32 %9 to i64 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_94.mlir b/benchmarks/LLVMIR/8_function_94.mlir new file mode 100644 index 0000000..eb68244 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_94.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2, i32 %3) { + %5 = sdiv exact i64 %0, %1 + %6 = icmp sgt i64 %5, %1 + %7 = ashr exact i64 %2, %5 + %8 = sext i32 %3 to i64 + %9 = srem i64 %7, %8 + %10 = select i1 %6, i64 %5, i64 %9 + %11 = srem i64 %2, %8 + %12 = ashr exact i64 %10, %11 + ret i64 %12 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_95.mlir b/benchmarks/LLVMIR/8_function_95.mlir new file mode 100644 index 0000000..2d0a6be --- /dev/null +++ b/benchmarks/LLVMIR/8_function_95.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = ashr i64 %0, %1 + %5 = icmp uge i64 %4, %2 + %6 = urem i64 %2, %1 + %7 = select i1 %5, i64 %1, i64 %6 + %8 = udiv i64 %1, %4 + %9 = ashr exact i64 %7, %8 + %10 = udiv i64 %7, %9 + %11 = icmp ugt i64 %10, %7 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_96.mlir b/benchmarks/LLVMIR/8_function_96.mlir new file mode 100644 index 0000000..0015cbc --- /dev/null +++ b/benchmarks/LLVMIR/8_function_96.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = srem i64 %0, %4 + %6 = trunc i64 %5 to i32 + %7 = sext i32 %6 to i64 + %8 = trunc i64 %7 to i32 + %9 = zext i32 %8 to i64 + %10 = urem i64 %2, %2 + %11 = udiv i64 %9, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_97.mlir b/benchmarks/LLVMIR/8_function_97.mlir new file mode 100644 index 0000000..1013c65 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_97.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i64 @main(i64 %0, i64 %1, i32 %2) { + %4 = trunc i64 %0 to i32 + %5 = sext i32 %4 to i64 + %6 = xor i64 %5, %1 + %7 = zext i32 %2 to i64 + %8 = urem i64 %7, %1 + %9 = or i64 %6, %8 + %10 = sext i32 %2 to i64 + %11 = udiv i64 %9, %10 + ret i64 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_98.mlir b/benchmarks/LLVMIR/8_function_98.mlir new file mode 100644 index 0000000..3f868ff --- /dev/null +++ b/benchmarks/LLVMIR/8_function_98.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i32 @main(i64 %0, i64 %1, i64 %2) { + %4 = udiv i64 %0, %1 + %5 = srem i64 %4, %1 + %6 = or i64 %4, %4 + %7 = xor i64 %5, %6 + %8 = udiv i64 %1, %2 + %9 = ashr exact i64 %7, %8 + %10 = udiv i64 %4, %9 + %11 = trunc i64 %10 to i32 + ret i32 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/LLVMIR/8_function_99.mlir b/benchmarks/LLVMIR/8_function_99.mlir new file mode 100644 index 0000000..dec6dd4 --- /dev/null +++ b/benchmarks/LLVMIR/8_function_99.mlir @@ -0,0 +1,18 @@ +; ModuleID = 'LLVMDialectModule' +source_filename = "LLVMDialectModule" + +define i1 @main(i64 %0, i64 %1, i64 %2) { + %4 = icmp ugt i64 %0, %0 + %5 = or disjoint i64 %1, %2 + %6 = lshr exact i64 %5, %0 + %7 = sdiv exact i64 %5, %6 + %8 = select i1 %4, i64 %7, i64 %2 + %9 = xor i64 %8, %0 + %10 = urem i64 %9, %7 + %11 = trunc i64 %10 to i1 + ret i1 %11 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/benchmarks/MLIR_bb0_veir/3_function_0.mlir b/benchmarks/MLIR_bb0_veir/3_function_0.mlir new file mode 100644 index 0000000..f04856d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_0.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_1.mlir b/benchmarks/MLIR_bb0_veir/3_function_1.mlir new file mode 100644 index 0000000..0318ce4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_1.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_10.mlir b/benchmarks/MLIR_bb0_veir/3_function_10.mlir new file mode 100644 index 0000000..9227d67 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_10.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_11.mlir b/benchmarks/MLIR_bb0_veir/3_function_11.mlir new file mode 100644 index 0000000..411ddfa --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_11.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_12.mlir b/benchmarks/MLIR_bb0_veir/3_function_12.mlir new file mode 100644 index 0000000..c315eeb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_12.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_13.mlir b/benchmarks/MLIR_bb0_veir/3_function_13.mlir new file mode 100644 index 0000000..1805f88 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_13.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_14.mlir b/benchmarks/MLIR_bb0_veir/3_function_14.mlir new file mode 100644 index 0000000..a6c29dc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_14.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_15.mlir b/benchmarks/MLIR_bb0_veir/3_function_15.mlir new file mode 100644 index 0000000..e6bb1b6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_15.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_16.mlir b/benchmarks/MLIR_bb0_veir/3_function_16.mlir new file mode 100644 index 0000000..63ebfe0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_16.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_17.mlir b/benchmarks/MLIR_bb0_veir/3_function_17.mlir new file mode 100644 index 0000000..4e2c89a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_17.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_18.mlir b/benchmarks/MLIR_bb0_veir/3_function_18.mlir new file mode 100644 index 0000000..38ef38c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_18.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_19.mlir b/benchmarks/MLIR_bb0_veir/3_function_19.mlir new file mode 100644 index 0000000..d499a94 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_19.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_2.mlir b/benchmarks/MLIR_bb0_veir/3_function_2.mlir new file mode 100644 index 0000000..b1c402c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_2.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_20.mlir b/benchmarks/MLIR_bb0_veir/3_function_20.mlir new file mode 100644 index 0000000..8ba42f0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_20.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_21.mlir b/benchmarks/MLIR_bb0_veir/3_function_21.mlir new file mode 100644 index 0000000..78856ea --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_21.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_22.mlir b/benchmarks/MLIR_bb0_veir/3_function_22.mlir new file mode 100644 index 0000000..21d29cb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_22.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_23.mlir b/benchmarks/MLIR_bb0_veir/3_function_23.mlir new file mode 100644 index 0000000..fa10b3d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_23.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_24.mlir b/benchmarks/MLIR_bb0_veir/3_function_24.mlir new file mode 100644 index 0000000..9db3c33 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_24.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_25.mlir b/benchmarks/MLIR_bb0_veir/3_function_25.mlir new file mode 100644 index 0000000..0f2474e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_25.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_26.mlir b/benchmarks/MLIR_bb0_veir/3_function_26.mlir new file mode 100644 index 0000000..8db2467 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_26.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_27.mlir b/benchmarks/MLIR_bb0_veir/3_function_27.mlir new file mode 100644 index 0000000..c710800 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_27.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.or"(%arg0, %1) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_28.mlir b/benchmarks/MLIR_bb0_veir/3_function_28.mlir new file mode 100644 index 0000000..c461f2d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_28.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg2, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_29.mlir b/benchmarks/MLIR_bb0_veir/3_function_29.mlir new file mode 100644 index 0000000..28b68d0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_29.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%1, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_3.mlir b/benchmarks/MLIR_bb0_veir/3_function_3.mlir new file mode 100644 index 0000000..d906f28 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_3.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_30.mlir b/benchmarks/MLIR_bb0_veir/3_function_30.mlir new file mode 100644 index 0000000..1202b11 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_30.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_31.mlir b/benchmarks/MLIR_bb0_veir/3_function_31.mlir new file mode 100644 index 0000000..820fdba --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_31.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_32.mlir b/benchmarks/MLIR_bb0_veir/3_function_32.mlir new file mode 100644 index 0000000..47bc3f8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_32.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_33.mlir b/benchmarks/MLIR_bb0_veir/3_function_33.mlir new file mode 100644 index 0000000..c7e45e6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_33.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_34.mlir b/benchmarks/MLIR_bb0_veir/3_function_34.mlir new file mode 100644 index 0000000..251f091 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_34.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_35.mlir b/benchmarks/MLIR_bb0_veir/3_function_35.mlir new file mode 100644 index 0000000..1b1b9f0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_35.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_36.mlir b/benchmarks/MLIR_bb0_veir/3_function_36.mlir new file mode 100644 index 0000000..0f2474e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_36.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_37.mlir b/benchmarks/MLIR_bb0_veir/3_function_37.mlir new file mode 100644 index 0000000..a956848 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_37.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_38.mlir b/benchmarks/MLIR_bb0_veir/3_function_38.mlir new file mode 100644 index 0000000..e93149a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_38.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%1, %arg0) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_39.mlir b/benchmarks/MLIR_bb0_veir/3_function_39.mlir new file mode 100644 index 0000000..7de3183 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_39.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_4.mlir b/benchmarks/MLIR_bb0_veir/3_function_4.mlir new file mode 100644 index 0000000..a1ef129 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_4.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_40.mlir b/benchmarks/MLIR_bb0_veir/3_function_40.mlir new file mode 100644 index 0000000..5a36e0c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_40.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_41.mlir b/benchmarks/MLIR_bb0_veir/3_function_41.mlir new file mode 100644 index 0000000..d499a94 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_41.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_42.mlir b/benchmarks/MLIR_bb0_veir/3_function_42.mlir new file mode 100644 index 0000000..d3d85f6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_42.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_43.mlir b/benchmarks/MLIR_bb0_veir/3_function_43.mlir new file mode 100644 index 0000000..84e93fb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_43.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_44.mlir b/benchmarks/MLIR_bb0_veir/3_function_44.mlir new file mode 100644 index 0000000..5702448 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_44.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.ashr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_45.mlir b/benchmarks/MLIR_bb0_veir/3_function_45.mlir new file mode 100644 index 0000000..1955180 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_45.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_46.mlir b/benchmarks/MLIR_bb0_veir/3_function_46.mlir new file mode 100644 index 0000000..c4a0dbd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_46.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_47.mlir b/benchmarks/MLIR_bb0_veir/3_function_47.mlir new file mode 100644 index 0000000..08fbae6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_47.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_48.mlir b/benchmarks/MLIR_bb0_veir/3_function_48.mlir new file mode 100644 index 0000000..c7e45e6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_48.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_49.mlir b/benchmarks/MLIR_bb0_veir/3_function_49.mlir new file mode 100644 index 0000000..dbf765c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_49.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_5.mlir b/benchmarks/MLIR_bb0_veir/3_function_5.mlir new file mode 100644 index 0000000..9cb7a91 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_5.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_50.mlir b/benchmarks/MLIR_bb0_veir/3_function_50.mlir new file mode 100644 index 0000000..8d2d5e6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_50.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_51.mlir b/benchmarks/MLIR_bb0_veir/3_function_51.mlir new file mode 100644 index 0000000..16157ff --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_51.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_52.mlir b/benchmarks/MLIR_bb0_veir/3_function_52.mlir new file mode 100644 index 0000000..c7e45e6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_52.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_53.mlir b/benchmarks/MLIR_bb0_veir/3_function_53.mlir new file mode 100644 index 0000000..01a908f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_53.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_54.mlir b/benchmarks/MLIR_bb0_veir/3_function_54.mlir new file mode 100644 index 0000000..a3048b8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_54.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_55.mlir b/benchmarks/MLIR_bb0_veir/3_function_55.mlir new file mode 100644 index 0000000..da0c7c4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_55.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_56.mlir b/benchmarks/MLIR_bb0_veir/3_function_56.mlir new file mode 100644 index 0000000..0f2474e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_56.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_57.mlir b/benchmarks/MLIR_bb0_veir/3_function_57.mlir new file mode 100644 index 0000000..dfc8ba6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_57.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_58.mlir b/benchmarks/MLIR_bb0_veir/3_function_58.mlir new file mode 100644 index 0000000..3b5417a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_58.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_59.mlir b/benchmarks/MLIR_bb0_veir/3_function_59.mlir new file mode 100644 index 0000000..537688c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_59.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_6.mlir b/benchmarks/MLIR_bb0_veir/3_function_6.mlir new file mode 100644 index 0000000..16157ff --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_6.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_60.mlir b/benchmarks/MLIR_bb0_veir/3_function_60.mlir new file mode 100644 index 0000000..3c1d8ff --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_60.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_61.mlir b/benchmarks/MLIR_bb0_veir/3_function_61.mlir new file mode 100644 index 0000000..ca85646 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_61.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_62.mlir b/benchmarks/MLIR_bb0_veir/3_function_62.mlir new file mode 100644 index 0000000..3b85ded --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_62.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %0) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_63.mlir b/benchmarks/MLIR_bb0_veir/3_function_63.mlir new file mode 100644 index 0000000..0f2474e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_63.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_64.mlir b/benchmarks/MLIR_bb0_veir/3_function_64.mlir new file mode 100644 index 0000000..d59c500 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_64.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_65.mlir b/benchmarks/MLIR_bb0_veir/3_function_65.mlir new file mode 100644 index 0000000..9adb24f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_65.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_66.mlir b/benchmarks/MLIR_bb0_veir/3_function_66.mlir new file mode 100644 index 0000000..23923ce --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_66.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_67.mlir b/benchmarks/MLIR_bb0_veir/3_function_67.mlir new file mode 100644 index 0000000..9c2b1ad --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_67.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_68.mlir b/benchmarks/MLIR_bb0_veir/3_function_68.mlir new file mode 100644 index 0000000..13611f2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_68.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_69.mlir b/benchmarks/MLIR_bb0_veir/3_function_69.mlir new file mode 100644 index 0000000..77b6c07 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_69.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_7.mlir b/benchmarks/MLIR_bb0_veir/3_function_7.mlir new file mode 100644 index 0000000..887f21f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_7.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_70.mlir b/benchmarks/MLIR_bb0_veir/3_function_70.mlir new file mode 100644 index 0000000..5a00d2d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_70.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_71.mlir b/benchmarks/MLIR_bb0_veir/3_function_71.mlir new file mode 100644 index 0000000..5da77e0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_71.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_72.mlir b/benchmarks/MLIR_bb0_veir/3_function_72.mlir new file mode 100644 index 0000000..56cda5c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_72.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.xor"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_73.mlir b/benchmarks/MLIR_bb0_veir/3_function_73.mlir new file mode 100644 index 0000000..cf01020 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_73.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_74.mlir b/benchmarks/MLIR_bb0_veir/3_function_74.mlir new file mode 100644 index 0000000..8138feb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_74.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_75.mlir b/benchmarks/MLIR_bb0_veir/3_function_75.mlir new file mode 100644 index 0000000..d41f9b5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_75.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_76.mlir b/benchmarks/MLIR_bb0_veir/3_function_76.mlir new file mode 100644 index 0000000..cd46e1a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_76.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.or"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_77.mlir b/benchmarks/MLIR_bb0_veir/3_function_77.mlir new file mode 100644 index 0000000..86f37be --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_77.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_78.mlir b/benchmarks/MLIR_bb0_veir/3_function_78.mlir new file mode 100644 index 0000000..4e28538 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_78.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_79.mlir b/benchmarks/MLIR_bb0_veir/3_function_79.mlir new file mode 100644 index 0000000..eb6308f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_79.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_8.mlir b/benchmarks/MLIR_bb0_veir/3_function_8.mlir new file mode 100644 index 0000000..d22b15a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_8.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_80.mlir b/benchmarks/MLIR_bb0_veir/3_function_80.mlir new file mode 100644 index 0000000..5ab3d76 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_80.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.sdiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_81.mlir b/benchmarks/MLIR_bb0_veir/3_function_81.mlir new file mode 100644 index 0000000..973e212 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_81.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_82.mlir b/benchmarks/MLIR_bb0_veir/3_function_82.mlir new file mode 100644 index 0000000..be35a28 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_82.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_83.mlir b/benchmarks/MLIR_bb0_veir/3_function_83.mlir new file mode 100644 index 0000000..dbf9dff --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_83.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_84.mlir b/benchmarks/MLIR_bb0_veir/3_function_84.mlir new file mode 100644 index 0000000..c78f889 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_84.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_85.mlir b/benchmarks/MLIR_bb0_veir/3_function_85.mlir new file mode 100644 index 0000000..dd05942 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_85.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_86.mlir b/benchmarks/MLIR_bb0_veir/3_function_86.mlir new file mode 100644 index 0000000..8d92784 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_86.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i32, %arg2: i64): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_87.mlir b/benchmarks/MLIR_bb0_veir/3_function_87.mlir new file mode 100644 index 0000000..c0e89e3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_87.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_88.mlir b/benchmarks/MLIR_bb0_veir/3_function_88.mlir new file mode 100644 index 0000000..3d260f2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_88.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.udiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_89.mlir b/benchmarks/MLIR_bb0_veir/3_function_89.mlir new file mode 100644 index 0000000..66d9824 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_89.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_9.mlir b/benchmarks/MLIR_bb0_veir/3_function_9.mlir new file mode 100644 index 0000000..c1f6dc0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_9.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 1 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg0) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_90.mlir b/benchmarks/MLIR_bb0_veir/3_function_90.mlir new file mode 100644 index 0000000..b1db9d0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_90.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_91.mlir b/benchmarks/MLIR_bb0_veir/3_function_91.mlir new file mode 100644 index 0000000..4bee054 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_91.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_92.mlir b/benchmarks/MLIR_bb0_veir/3_function_92.mlir new file mode 100644 index 0000000..c6a22b9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_92.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_93.mlir b/benchmarks/MLIR_bb0_veir/3_function_93.mlir new file mode 100644 index 0000000..d185eee --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_93.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_94.mlir b/benchmarks/MLIR_bb0_veir/3_function_94.mlir new file mode 100644 index 0000000..1d09264 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_94.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_95.mlir b/benchmarks/MLIR_bb0_veir/3_function_95.mlir new file mode 100644 index 0000000..dd97b70 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_95.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_96.mlir b/benchmarks/MLIR_bb0_veir/3_function_96.mlir new file mode 100644 index 0000000..eaa7f51 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_96.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg2) : (i32) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_97.mlir b/benchmarks/MLIR_bb0_veir/3_function_97.mlir new file mode 100644 index 0000000..9cbc08f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_97.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %arg0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%2) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_98.mlir b/benchmarks/MLIR_bb0_veir/3_function_98.mlir new file mode 100644 index 0000000..16157ff --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_98.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%2) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/3_function_99.mlir b/benchmarks/MLIR_bb0_veir/3_function_99.mlir new file mode 100644 index 0000000..ba1a9cd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/3_function_99.mlir @@ -0,0 +1,9 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.sdiv"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%2) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_0.mlir b/benchmarks/MLIR_bb0_veir/4_function_0.mlir new file mode 100644 index 0000000..7de5979 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_0.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_1.mlir b/benchmarks/MLIR_bb0_veir/4_function_1.mlir new file mode 100644 index 0000000..5374333 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_1.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_10.mlir b/benchmarks/MLIR_bb0_veir/4_function_10.mlir new file mode 100644 index 0000000..7d589a0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_10.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_11.mlir b/benchmarks/MLIR_bb0_veir/4_function_11.mlir new file mode 100644 index 0000000..09b2f56 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_11.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_12.mlir b/benchmarks/MLIR_bb0_veir/4_function_12.mlir new file mode 100644 index 0000000..e3a451e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_12.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_13.mlir b/benchmarks/MLIR_bb0_veir/4_function_13.mlir new file mode 100644 index 0000000..dc3db54 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_13.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.icmp"(%arg0, %2) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_14.mlir b/benchmarks/MLIR_bb0_veir/4_function_14.mlir new file mode 100644 index 0000000..1dde590 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_14.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_15.mlir b/benchmarks/MLIR_bb0_veir/4_function_15.mlir new file mode 100644 index 0000000..27d521f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_15.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_16.mlir b/benchmarks/MLIR_bb0_veir/4_function_16.mlir new file mode 100644 index 0000000..cdcb44b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_16.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_17.mlir b/benchmarks/MLIR_bb0_veir/4_function_17.mlir new file mode 100644 index 0000000..4a6229f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_17.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg1) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_18.mlir b/benchmarks/MLIR_bb0_veir/4_function_18.mlir new file mode 100644 index 0000000..e284498 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_18.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_19.mlir b/benchmarks/MLIR_bb0_veir/4_function_19.mlir new file mode 100644 index 0000000..7638ef7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_19.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_2.mlir b/benchmarks/MLIR_bb0_veir/4_function_2.mlir new file mode 100644 index 0000000..222e2ed --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_2.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_20.mlir b/benchmarks/MLIR_bb0_veir/4_function_20.mlir new file mode 100644 index 0000000..f2939bb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_20.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64, %arg3: i32): + %0 = "llvm.xor"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg3) : (i32) -> i64 + %2 = "llvm.select"(%arg1, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.ashr"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_21.mlir b/benchmarks/MLIR_bb0_veir/4_function_21.mlir new file mode 100644 index 0000000..408b425 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_21.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%arg0, %2) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_22.mlir b/benchmarks/MLIR_bb0_veir/4_function_22.mlir new file mode 100644 index 0000000..fd985b0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_22.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_23.mlir b/benchmarks/MLIR_bb0_veir/4_function_23.mlir new file mode 100644 index 0000000..0f6b242 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_23.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.or"(%1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_24.mlir b/benchmarks/MLIR_bb0_veir/4_function_24.mlir new file mode 100644 index 0000000..427b952 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_24.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_25.mlir b/benchmarks/MLIR_bb0_veir/4_function_25.mlir new file mode 100644 index 0000000..421e74b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_25.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_26.mlir b/benchmarks/MLIR_bb0_veir/4_function_26.mlir new file mode 100644 index 0000000..c3782f7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_26.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.xor"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_27.mlir b/benchmarks/MLIR_bb0_veir/4_function_27.mlir new file mode 100644 index 0000000..f814b0e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_27.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_28.mlir b/benchmarks/MLIR_bb0_veir/4_function_28.mlir new file mode 100644 index 0000000..ac08145 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_28.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_29.mlir b/benchmarks/MLIR_bb0_veir/4_function_29.mlir new file mode 100644 index 0000000..fecff90 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_29.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_3.mlir b/benchmarks/MLIR_bb0_veir/4_function_3.mlir new file mode 100644 index 0000000..1617ada --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_3.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_30.mlir b/benchmarks/MLIR_bb0_veir/4_function_30.mlir new file mode 100644 index 0000000..b74f3d8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_30.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.icmp"(%2, %arg2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_31.mlir b/benchmarks/MLIR_bb0_veir/4_function_31.mlir new file mode 100644 index 0000000..cc820a9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_31.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_32.mlir b/benchmarks/MLIR_bb0_veir/4_function_32.mlir new file mode 100644 index 0000000..d504c47 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_32.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg1, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_33.mlir b/benchmarks/MLIR_bb0_veir/4_function_33.mlir new file mode 100644 index 0000000..cc2f40c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_33.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg1, %arg2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_34.mlir b/benchmarks/MLIR_bb0_veir/4_function_34.mlir new file mode 100644 index 0000000..4e71f38 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_34.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_35.mlir b/benchmarks/MLIR_bb0_veir/4_function_35.mlir new file mode 100644 index 0000000..6de6a9c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_35.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_36.mlir b/benchmarks/MLIR_bb0_veir/4_function_36.mlir new file mode 100644 index 0000000..2141caf --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_36.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.urem"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_37.mlir b/benchmarks/MLIR_bb0_veir/4_function_37.mlir new file mode 100644 index 0000000..99ac33f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_37.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_38.mlir b/benchmarks/MLIR_bb0_veir/4_function_38.mlir new file mode 100644 index 0000000..e8fa9be --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_38.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%2, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_39.mlir b/benchmarks/MLIR_bb0_veir/4_function_39.mlir new file mode 100644 index 0000000..baff1fb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_39.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_4.mlir b/benchmarks/MLIR_bb0_veir/4_function_4.mlir new file mode 100644 index 0000000..1d2a217 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_4.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_40.mlir b/benchmarks/MLIR_bb0_veir/4_function_40.mlir new file mode 100644 index 0000000..97030d7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_40.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_41.mlir b/benchmarks/MLIR_bb0_veir/4_function_41.mlir new file mode 100644 index 0000000..1862943 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_41.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_42.mlir b/benchmarks/MLIR_bb0_veir/4_function_42.mlir new file mode 100644 index 0000000..a356acc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_42.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i1, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_43.mlir b/benchmarks/MLIR_bb0_veir/4_function_43.mlir new file mode 100644 index 0000000..087e872 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_43.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1): + %0 = "llvm.select"(%arg1, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_44.mlir b/benchmarks/MLIR_bb0_veir/4_function_44.mlir new file mode 100644 index 0000000..628ddce --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_44.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.sext"(%arg1) : (i32) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_45.mlir b/benchmarks/MLIR_bb0_veir/4_function_45.mlir new file mode 100644 index 0000000..51f714a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_45.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %arg0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_46.mlir b/benchmarks/MLIR_bb0_veir/4_function_46.mlir new file mode 100644 index 0000000..63802c7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_46.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_47.mlir b/benchmarks/MLIR_bb0_veir/4_function_47.mlir new file mode 100644 index 0000000..ce440dc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_47.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_48.mlir b/benchmarks/MLIR_bb0_veir/4_function_48.mlir new file mode 100644 index 0000000..832d2a4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_48.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_49.mlir b/benchmarks/MLIR_bb0_veir/4_function_49.mlir new file mode 100644 index 0000000..669d7e2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_49.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_5.mlir b/benchmarks/MLIR_bb0_veir/4_function_5.mlir new file mode 100644 index 0000000..259fd8a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_5.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_50.mlir b/benchmarks/MLIR_bb0_veir/4_function_50.mlir new file mode 100644 index 0000000..fa28d95 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_50.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %0) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_51.mlir b/benchmarks/MLIR_bb0_veir/4_function_51.mlir new file mode 100644 index 0000000..ed08167 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_51.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_52.mlir b/benchmarks/MLIR_bb0_veir/4_function_52.mlir new file mode 100644 index 0000000..3859fcb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_52.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_53.mlir b/benchmarks/MLIR_bb0_veir/4_function_53.mlir new file mode 100644 index 0000000..b8c0425 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_53.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_54.mlir b/benchmarks/MLIR_bb0_veir/4_function_54.mlir new file mode 100644 index 0000000..f6f942c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_54.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg2) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_55.mlir b/benchmarks/MLIR_bb0_veir/4_function_55.mlir new file mode 100644 index 0000000..c8c9a75 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_55.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_56.mlir b/benchmarks/MLIR_bb0_veir/4_function_56.mlir new file mode 100644 index 0000000..6b36f45 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_56.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.srem"(%arg0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_57.mlir b/benchmarks/MLIR_bb0_veir/4_function_57.mlir new file mode 100644 index 0000000..152768a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_57.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.or"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_58.mlir b/benchmarks/MLIR_bb0_veir/4_function_58.mlir new file mode 100644 index 0000000..6b2ee58 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_58.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_59.mlir b/benchmarks/MLIR_bb0_veir/4_function_59.mlir new file mode 100644 index 0000000..a4c76f7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_59.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_6.mlir b/benchmarks/MLIR_bb0_veir/4_function_6.mlir new file mode 100644 index 0000000..d0e832c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_6.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%2, %2) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_60.mlir b/benchmarks/MLIR_bb0_veir/4_function_60.mlir new file mode 100644 index 0000000..6de6a9c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_60.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_61.mlir b/benchmarks/MLIR_bb0_veir/4_function_61.mlir new file mode 100644 index 0000000..21afa82 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_61.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_62.mlir b/benchmarks/MLIR_bb0_veir/4_function_62.mlir new file mode 100644 index 0000000..7e30eba --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_62.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg2, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_63.mlir b/benchmarks/MLIR_bb0_veir/4_function_63.mlir new file mode 100644 index 0000000..ef33c92 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_63.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.ashr"(%arg2, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_64.mlir b/benchmarks/MLIR_bb0_veir/4_function_64.mlir new file mode 100644 index 0000000..5ab355c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_64.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_65.mlir b/benchmarks/MLIR_bb0_veir/4_function_65.mlir new file mode 100644 index 0000000..883e1a5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_65.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_66.mlir b/benchmarks/MLIR_bb0_veir/4_function_66.mlir new file mode 100644 index 0000000..79fc5a9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_66.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_67.mlir b/benchmarks/MLIR_bb0_veir/4_function_67.mlir new file mode 100644 index 0000000..0809277 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_67.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_68.mlir b/benchmarks/MLIR_bb0_veir/4_function_68.mlir new file mode 100644 index 0000000..8cb6dc7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_68.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_69.mlir b/benchmarks/MLIR_bb0_veir/4_function_69.mlir new file mode 100644 index 0000000..faecb43 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_69.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.urem"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_7.mlir b/benchmarks/MLIR_bb0_veir/4_function_7.mlir new file mode 100644 index 0000000..6ec1bdf --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_7.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%arg0, %0) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.udiv"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_70.mlir b/benchmarks/MLIR_bb0_veir/4_function_70.mlir new file mode 100644 index 0000000..ab4e863 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_70.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg1) : (i32) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_71.mlir b/benchmarks/MLIR_bb0_veir/4_function_71.mlir new file mode 100644 index 0000000..a954e5e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_71.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_72.mlir b/benchmarks/MLIR_bb0_veir/4_function_72.mlir new file mode 100644 index 0000000..6d7b775 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_72.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_73.mlir b/benchmarks/MLIR_bb0_veir/4_function_73.mlir new file mode 100644 index 0000000..0fdf121 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_73.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_74.mlir b/benchmarks/MLIR_bb0_veir/4_function_74.mlir new file mode 100644 index 0000000..a861ac6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_74.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_75.mlir b/benchmarks/MLIR_bb0_veir/4_function_75.mlir new file mode 100644 index 0000000..6507a8c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_75.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_76.mlir b/benchmarks/MLIR_bb0_veir/4_function_76.mlir new file mode 100644 index 0000000..a3bc859 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_76.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_77.mlir b/benchmarks/MLIR_bb0_veir/4_function_77.mlir new file mode 100644 index 0000000..73a2907 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_77.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%0, %2) <{isExact}> : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_78.mlir b/benchmarks/MLIR_bb0_veir/4_function_78.mlir new file mode 100644 index 0000000..c0dd56e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_78.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_79.mlir b/benchmarks/MLIR_bb0_veir/4_function_79.mlir new file mode 100644 index 0000000..5374333 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_79.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_8.mlir b/benchmarks/MLIR_bb0_veir/4_function_8.mlir new file mode 100644 index 0000000..b1f1c79 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_8.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.xor"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_80.mlir b/benchmarks/MLIR_bb0_veir/4_function_80.mlir new file mode 100644 index 0000000..3b57742 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_80.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_81.mlir b/benchmarks/MLIR_bb0_veir/4_function_81.mlir new file mode 100644 index 0000000..a6be620 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_81.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg2, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %1) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_82.mlir b/benchmarks/MLIR_bb0_veir/4_function_82.mlir new file mode 100644 index 0000000..7cd1e2d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_82.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.xor"(%0, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_83.mlir b/benchmarks/MLIR_bb0_veir/4_function_83.mlir new file mode 100644 index 0000000..c4338be --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_83.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_84.mlir b/benchmarks/MLIR_bb0_veir/4_function_84.mlir new file mode 100644 index 0000000..e65b8f7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_84.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_85.mlir b/benchmarks/MLIR_bb0_veir/4_function_85.mlir new file mode 100644 index 0000000..a459151 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_85.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg1) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_86.mlir b/benchmarks/MLIR_bb0_veir/4_function_86.mlir new file mode 100644 index 0000000..52d51fc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_86.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_87.mlir b/benchmarks/MLIR_bb0_veir/4_function_87.mlir new file mode 100644 index 0000000..958dd18 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_87.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_88.mlir b/benchmarks/MLIR_bb0_veir/4_function_88.mlir new file mode 100644 index 0000000..7ce7a57 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_88.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_89.mlir b/benchmarks/MLIR_bb0_veir/4_function_89.mlir new file mode 100644 index 0000000..dc125c9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_89.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_9.mlir b/benchmarks/MLIR_bb0_veir/4_function_9.mlir new file mode 100644 index 0000000..a075580 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_9.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg2, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_90.mlir b/benchmarks/MLIR_bb0_veir/4_function_90.mlir new file mode 100644 index 0000000..0a15985 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_90.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_91.mlir b/benchmarks/MLIR_bb0_veir/4_function_91.mlir new file mode 100644 index 0000000..2e0e3b4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_91.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_92.mlir b/benchmarks/MLIR_bb0_veir/4_function_92.mlir new file mode 100644 index 0000000..b1b8a1b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_92.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.sdiv"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_93.mlir b/benchmarks/MLIR_bb0_veir/4_function_93.mlir new file mode 100644 index 0000000..26f9291 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_93.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_94.mlir b/benchmarks/MLIR_bb0_veir/4_function_94.mlir new file mode 100644 index 0000000..552919c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_94.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.icmp"(%0, %2) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_95.mlir b/benchmarks/MLIR_bb0_veir/4_function_95.mlir new file mode 100644 index 0000000..618cfca --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_95.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%2, %1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_96.mlir b/benchmarks/MLIR_bb0_veir/4_function_96.mlir new file mode 100644 index 0000000..77c4db7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_96.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_97.mlir b/benchmarks/MLIR_bb0_veir/4_function_97.mlir new file mode 100644 index 0000000..fd458bc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_97.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%1, %arg0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%3) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_98.mlir b/benchmarks/MLIR_bb0_veir/4_function_98.mlir new file mode 100644 index 0000000..5d3486b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_98.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + "func.return"(%3) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/4_function_99.mlir b/benchmarks/MLIR_bb0_veir/4_function_99.mlir new file mode 100644 index 0000000..ef4ba04 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/4_function_99.mlir @@ -0,0 +1,10 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.or"(%1, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%3) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_0.mlir b/benchmarks/MLIR_bb0_veir/5_function_0.mlir new file mode 100644 index 0000000..b8ec81d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_0.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_1.mlir b/benchmarks/MLIR_bb0_veir/5_function_1.mlir new file mode 100644 index 0000000..89d2d80 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_1.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.ashr"(%0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg0) : (i32) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_10.mlir b/benchmarks/MLIR_bb0_veir/5_function_10.mlir new file mode 100644 index 0000000..3470d51 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_10.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.urem"(%1, %3) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_11.mlir b/benchmarks/MLIR_bb0_veir/5_function_11.mlir new file mode 100644 index 0000000..508620f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_11.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_12.mlir b/benchmarks/MLIR_bb0_veir/5_function_12.mlir new file mode 100644 index 0000000..3b91355 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_12.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg2) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%1, %3) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_13.mlir b/benchmarks/MLIR_bb0_veir/5_function_13.mlir new file mode 100644 index 0000000..05d0472 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_13.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.lshr"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%0, %3) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_14.mlir b/benchmarks/MLIR_bb0_veir/5_function_14.mlir new file mode 100644 index 0000000..3c0db7e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_14.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 9 : i64}> : (i64, i64) -> i1 + %1 = "llvm.urem"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_15.mlir b/benchmarks/MLIR_bb0_veir/5_function_15.mlir new file mode 100644 index 0000000..3ec10ce --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_15.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg0) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.sdiv"(%2, %arg2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_16.mlir b/benchmarks/MLIR_bb0_veir/5_function_16.mlir new file mode 100644 index 0000000..c9fb138 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_16.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_17.mlir b/benchmarks/MLIR_bb0_veir/5_function_17.mlir new file mode 100644 index 0000000..fd46de3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_17.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg1) : (i32) -> i64 + %3 = "llvm.ashr"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_18.mlir b/benchmarks/MLIR_bb0_veir/5_function_18.mlir new file mode 100644 index 0000000..2c03f55 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_18.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_19.mlir b/benchmarks/MLIR_bb0_veir/5_function_19.mlir new file mode 100644 index 0000000..1dbc127 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_19.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg2) : (i32) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_2.mlir b/benchmarks/MLIR_bb0_veir/5_function_2.mlir new file mode 100644 index 0000000..4ae0e6e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_2.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%2, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.urem"(%arg0, %3) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_20.mlir b/benchmarks/MLIR_bb0_veir/5_function_20.mlir new file mode 100644 index 0000000..55ac4a1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_20.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg2, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_21.mlir b/benchmarks/MLIR_bb0_veir/5_function_21.mlir new file mode 100644 index 0000000..a1e694c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_21.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_22.mlir b/benchmarks/MLIR_bb0_veir/5_function_22.mlir new file mode 100644 index 0000000..b249211 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_22.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_23.mlir b/benchmarks/MLIR_bb0_veir/5_function_23.mlir new file mode 100644 index 0000000..4be3552 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_23.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_24.mlir b/benchmarks/MLIR_bb0_veir/5_function_24.mlir new file mode 100644 index 0000000..c00471a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_24.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_25.mlir b/benchmarks/MLIR_bb0_veir/5_function_25.mlir new file mode 100644 index 0000000..3e7267b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_25.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.or"(%0, %3) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_26.mlir b/benchmarks/MLIR_bb0_veir/5_function_26.mlir new file mode 100644 index 0000000..b286bfe --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_26.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_27.mlir b/benchmarks/MLIR_bb0_veir/5_function_27.mlir new file mode 100644 index 0000000..6c49f0d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_27.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%arg0, %0) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_28.mlir b/benchmarks/MLIR_bb0_veir/5_function_28.mlir new file mode 100644 index 0000000..f8fb8a2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_28.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_29.mlir b/benchmarks/MLIR_bb0_veir/5_function_29.mlir new file mode 100644 index 0000000..7f63496 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_29.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.srem"(%1, %3) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_3.mlir b/benchmarks/MLIR_bb0_veir/5_function_3.mlir new file mode 100644 index 0000000..8f9c675 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_3.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_30.mlir b/benchmarks/MLIR_bb0_veir/5_function_30.mlir new file mode 100644 index 0000000..dbfbe69 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_30.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_31.mlir b/benchmarks/MLIR_bb0_veir/5_function_31.mlir new file mode 100644 index 0000000..bfd5010 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_31.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.lshr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.icmp"(%arg0, %0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %2 = "llvm.zext"(%arg3) : (i32) -> i64 + %3 = "llvm.select"(%1, %arg0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.xor"(%3, %arg1) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_32.mlir b/benchmarks/MLIR_bb0_veir/5_function_32.mlir new file mode 100644 index 0000000..c87f6e8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_32.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_33.mlir b/benchmarks/MLIR_bb0_veir/5_function_33.mlir new file mode 100644 index 0000000..60227e4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_33.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.udiv"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %arg0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_34.mlir b/benchmarks/MLIR_bb0_veir/5_function_34.mlir new file mode 100644 index 0000000..a71b9f1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_34.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.xor"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %0) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_35.mlir b/benchmarks/MLIR_bb0_veir/5_function_35.mlir new file mode 100644 index 0000000..4f9d232 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_35.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_36.mlir b/benchmarks/MLIR_bb0_veir/5_function_36.mlir new file mode 100644 index 0000000..1be7d7b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_36.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_37.mlir b/benchmarks/MLIR_bb0_veir/5_function_37.mlir new file mode 100644 index 0000000..b5a133e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_37.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.or"(%arg1, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.select"(%0, %arg0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_38.mlir b/benchmarks/MLIR_bb0_veir/5_function_38.mlir new file mode 100644 index 0000000..13d71b6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_38.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_39.mlir b/benchmarks/MLIR_bb0_veir/5_function_39.mlir new file mode 100644 index 0000000..25c7318 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_39.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.xor"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_4.mlir b/benchmarks/MLIR_bb0_veir/5_function_4.mlir new file mode 100644 index 0000000..5c1fe44 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_4.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_40.mlir b/benchmarks/MLIR_bb0_veir/5_function_40.mlir new file mode 100644 index 0000000..62a6543 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_40.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.ashr"(%2, %3) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_41.mlir b/benchmarks/MLIR_bb0_veir/5_function_41.mlir new file mode 100644 index 0000000..cb587de --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_41.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.or"(%2, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_42.mlir b/benchmarks/MLIR_bb0_veir/5_function_42.mlir new file mode 100644 index 0000000..d24a0cb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_42.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_43.mlir b/benchmarks/MLIR_bb0_veir/5_function_43.mlir new file mode 100644 index 0000000..06b3d55 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_43.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_44.mlir b/benchmarks/MLIR_bb0_veir/5_function_44.mlir new file mode 100644 index 0000000..34ebeb7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_44.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_45.mlir b/benchmarks/MLIR_bb0_veir/5_function_45.mlir new file mode 100644 index 0000000..e9256a4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_45.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.sdiv"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_46.mlir b/benchmarks/MLIR_bb0_veir/5_function_46.mlir new file mode 100644 index 0000000..65226a0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_46.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_47.mlir b/benchmarks/MLIR_bb0_veir/5_function_47.mlir new file mode 100644 index 0000000..9e95c7e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_47.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%1, %3) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_48.mlir b/benchmarks/MLIR_bb0_veir/5_function_48.mlir new file mode 100644 index 0000000..693d6b9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_48.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_49.mlir b/benchmarks/MLIR_bb0_veir/5_function_49.mlir new file mode 100644 index 0000000..d4d52d1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_49.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_5.mlir b/benchmarks/MLIR_bb0_veir/5_function_5.mlir new file mode 100644 index 0000000..270b0c8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_5.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_50.mlir b/benchmarks/MLIR_bb0_veir/5_function_50.mlir new file mode 100644 index 0000000..e4ea164 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_50.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_51.mlir b/benchmarks/MLIR_bb0_veir/5_function_51.mlir new file mode 100644 index 0000000..84221a5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_51.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_52.mlir b/benchmarks/MLIR_bb0_veir/5_function_52.mlir new file mode 100644 index 0000000..dfa2ec0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_52.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_53.mlir b/benchmarks/MLIR_bb0_veir/5_function_53.mlir new file mode 100644 index 0000000..a7c9a3c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_53.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %0) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_54.mlir b/benchmarks/MLIR_bb0_veir/5_function_54.mlir new file mode 100644 index 0000000..6aad199 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_54.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_55.mlir b/benchmarks/MLIR_bb0_veir/5_function_55.mlir new file mode 100644 index 0000000..9c00b54 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_55.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.select"(%0, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%3, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_56.mlir b/benchmarks/MLIR_bb0_veir/5_function_56.mlir new file mode 100644 index 0000000..fc5490b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_56.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_57.mlir b/benchmarks/MLIR_bb0_veir/5_function_57.mlir new file mode 100644 index 0000000..1689fac --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_57.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.select"(%3, %arg2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_58.mlir b/benchmarks/MLIR_bb0_veir/5_function_58.mlir new file mode 100644 index 0000000..8f87c53 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_58.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.or"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_59.mlir b/benchmarks/MLIR_bb0_veir/5_function_59.mlir new file mode 100644 index 0000000..955d02e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_59.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_6.mlir b/benchmarks/MLIR_bb0_veir/5_function_6.mlir new file mode 100644 index 0000000..44db105 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_6.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.icmp"(%arg0, %3) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_60.mlir b/benchmarks/MLIR_bb0_veir/5_function_60.mlir new file mode 100644 index 0000000..595e0c1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_60.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg1, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_61.mlir b/benchmarks/MLIR_bb0_veir/5_function_61.mlir new file mode 100644 index 0000000..6e5b1fa --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_61.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32, %arg1: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.sdiv"(%1, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_62.mlir b/benchmarks/MLIR_bb0_veir/5_function_62.mlir new file mode 100644 index 0000000..eec819a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_62.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_63.mlir b/benchmarks/MLIR_bb0_veir/5_function_63.mlir new file mode 100644 index 0000000..c510398 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_63.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_64.mlir b/benchmarks/MLIR_bb0_veir/5_function_64.mlir new file mode 100644 index 0000000..5845a3a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_64.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_65.mlir b/benchmarks/MLIR_bb0_veir/5_function_65.mlir new file mode 100644 index 0000000..3dd4c2b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_65.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_66.mlir b/benchmarks/MLIR_bb0_veir/5_function_66.mlir new file mode 100644 index 0000000..f1a9d83 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_66.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.urem"(%arg0, %3) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_67.mlir b/benchmarks/MLIR_bb0_veir/5_function_67.mlir new file mode 100644 index 0000000..378edf0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_67.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_68.mlir b/benchmarks/MLIR_bb0_veir/5_function_68.mlir new file mode 100644 index 0000000..e1dfb1c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_68.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_69.mlir b/benchmarks/MLIR_bb0_veir/5_function_69.mlir new file mode 100644 index 0000000..7311c9c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_69.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%arg0, %3) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_7.mlir b/benchmarks/MLIR_bb0_veir/5_function_7.mlir new file mode 100644 index 0000000..479e524 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_7.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_70.mlir b/benchmarks/MLIR_bb0_veir/5_function_70.mlir new file mode 100644 index 0000000..8433239 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_70.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_71.mlir b/benchmarks/MLIR_bb0_veir/5_function_71.mlir new file mode 100644 index 0000000..d8f5002 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_71.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_72.mlir b/benchmarks/MLIR_bb0_veir/5_function_72.mlir new file mode 100644 index 0000000..58782b8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_72.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_73.mlir b/benchmarks/MLIR_bb0_veir/5_function_73.mlir new file mode 100644 index 0000000..2dd5f10 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_73.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_74.mlir b/benchmarks/MLIR_bb0_veir/5_function_74.mlir new file mode 100644 index 0000000..e1c366c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_74.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg1, %arg0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_75.mlir b/benchmarks/MLIR_bb0_veir/5_function_75.mlir new file mode 100644 index 0000000..6ac007c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_75.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg1, %1) : (i64, i64) -> i64 + %4 = "llvm.srem"(%2, %3) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_76.mlir b/benchmarks/MLIR_bb0_veir/5_function_76.mlir new file mode 100644 index 0000000..afc9c35 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_76.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_77.mlir b/benchmarks/MLIR_bb0_veir/5_function_77.mlir new file mode 100644 index 0000000..9a8600b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_77.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_78.mlir b/benchmarks/MLIR_bb0_veir/5_function_78.mlir new file mode 100644 index 0000000..d64d18d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_78.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg2) : (i32) -> i64 + %3 = "llvm.srem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_79.mlir b/benchmarks/MLIR_bb0_veir/5_function_79.mlir new file mode 100644 index 0000000..10cc284 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_79.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.icmp"(%1, %3) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_8.mlir b/benchmarks/MLIR_bb0_veir/5_function_8.mlir new file mode 100644 index 0000000..54d068c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_8.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_80.mlir b/benchmarks/MLIR_bb0_veir/5_function_80.mlir new file mode 100644 index 0000000..3d5c9b5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_80.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_81.mlir b/benchmarks/MLIR_bb0_veir/5_function_81.mlir new file mode 100644 index 0000000..91935d5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_81.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%3, %0) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_82.mlir b/benchmarks/MLIR_bb0_veir/5_function_82.mlir new file mode 100644 index 0000000..e012ff5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_82.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.or"(%1, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_83.mlir b/benchmarks/MLIR_bb0_veir/5_function_83.mlir new file mode 100644 index 0000000..99ac853 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_83.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg2) : (i32) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_84.mlir b/benchmarks/MLIR_bb0_veir/5_function_84.mlir new file mode 100644 index 0000000..73cc5b8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_84.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_85.mlir b/benchmarks/MLIR_bb0_veir/5_function_85.mlir new file mode 100644 index 0000000..d8f156a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_85.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.zext"(%0) : (i32) -> i64 + %3 = "llvm.lshr"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%1, %3) <{isExact}> : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_86.mlir b/benchmarks/MLIR_bb0_veir/5_function_86.mlir new file mode 100644 index 0000000..4dd7ff6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_86.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.or"(%0, %3) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_87.mlir b/benchmarks/MLIR_bb0_veir/5_function_87.mlir new file mode 100644 index 0000000..5d600c7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_87.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.sdiv"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_88.mlir b/benchmarks/MLIR_bb0_veir/5_function_88.mlir new file mode 100644 index 0000000..bbecb48 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_88.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_89.mlir b/benchmarks/MLIR_bb0_veir/5_function_89.mlir new file mode 100644 index 0000000..450480f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_89.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_9.mlir b/benchmarks/MLIR_bb0_veir/5_function_9.mlir new file mode 100644 index 0000000..5e5db28 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_9.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_90.mlir b/benchmarks/MLIR_bb0_veir/5_function_90.mlir new file mode 100644 index 0000000..60c504b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_90.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_91.mlir b/benchmarks/MLIR_bb0_veir/5_function_91.mlir new file mode 100644 index 0000000..48b0e28 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_91.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_92.mlir b/benchmarks/MLIR_bb0_veir/5_function_92.mlir new file mode 100644 index 0000000..2549d20 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_92.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_93.mlir b/benchmarks/MLIR_bb0_veir/5_function_93.mlir new file mode 100644 index 0000000..8ca681d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_93.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.udiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%arg0, %3) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_94.mlir b/benchmarks/MLIR_bb0_veir/5_function_94.mlir new file mode 100644 index 0000000..26ed88b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_94.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.lshr"(%arg2, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%2, %3) <{isExact}> : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_95.mlir b/benchmarks/MLIR_bb0_veir/5_function_95.mlir new file mode 100644 index 0000000..a26abd3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_95.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_96.mlir b/benchmarks/MLIR_bb0_veir/5_function_96.mlir new file mode 100644 index 0000000..4adbd40 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_96.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_97.mlir b/benchmarks/MLIR_bb0_veir/5_function_97.mlir new file mode 100644 index 0000000..e1f8b39 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_97.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.sext"(%0) : (i32) -> i64 + %3 = "llvm.or"(%1, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %arg1) : (i64, i64) -> i64 + "func.return"(%4) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_98.mlir b/benchmarks/MLIR_bb0_veir/5_function_98.mlir new file mode 100644 index 0000000..9498a60 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_98.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%4) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/5_function_99.mlir b/benchmarks/MLIR_bb0_veir/5_function_99.mlir new file mode 100644 index 0000000..fe49ba7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/5_function_99.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%4) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_0.mlir b/benchmarks/MLIR_bb0_veir/6_function_0.mlir new file mode 100644 index 0000000..770d370 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_0.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.urem"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.or"(%4, %1) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_1.mlir b/benchmarks/MLIR_bb0_veir/6_function_1.mlir new file mode 100644 index 0000000..362792e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_1.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.lshr"(%arg2, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_10.mlir b/benchmarks/MLIR_bb0_veir/6_function_10.mlir new file mode 100644 index 0000000..9f1465d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_10.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_11.mlir b/benchmarks/MLIR_bb0_veir/6_function_11.mlir new file mode 100644 index 0000000..af95f2c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_11.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg2, %0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_12.mlir b/benchmarks/MLIR_bb0_veir/6_function_12.mlir new file mode 100644 index 0000000..0943a55 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_12.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_13.mlir b/benchmarks/MLIR_bb0_veir/6_function_13.mlir new file mode 100644 index 0000000..cc57b25 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_13.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_14.mlir b/benchmarks/MLIR_bb0_veir/6_function_14.mlir new file mode 100644 index 0000000..0af866c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_14.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i1): + %0 = "llvm.srem"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.srem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_15.mlir b/benchmarks/MLIR_bb0_veir/6_function_15.mlir new file mode 100644 index 0000000..35c89b9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_15.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg2, %1) : (i64, i64) -> i64 + %4 = "llvm.urem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_16.mlir b/benchmarks/MLIR_bb0_veir/6_function_16.mlir new file mode 100644 index 0000000..7cf0544 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_16.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sext"(%arg2) : (i32) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%2, %4) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_17.mlir b/benchmarks/MLIR_bb0_veir/6_function_17.mlir new file mode 100644 index 0000000..ce77a0d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_17.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %5 = "llvm.xor"(%3, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_18.mlir b/benchmarks/MLIR_bb0_veir/6_function_18.mlir new file mode 100644 index 0000000..7b6a718 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_18.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg2, %2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%0, %4) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_19.mlir b/benchmarks/MLIR_bb0_veir/6_function_19.mlir new file mode 100644 index 0000000..44e1f1f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_19.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.sdiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%4, %1) <{isExact}> : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_2.mlir b/benchmarks/MLIR_bb0_veir/6_function_2.mlir new file mode 100644 index 0000000..6816915 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_2.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.srem"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_20.mlir b/benchmarks/MLIR_bb0_veir/6_function_20.mlir new file mode 100644 index 0000000..7733a20 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_20.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_21.mlir b/benchmarks/MLIR_bb0_veir/6_function_21.mlir new file mode 100644 index 0000000..f2aec01 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_21.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg1, %2) : (i64, i64) -> i64 + %5 = "llvm.or"(%3, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_22.mlir b/benchmarks/MLIR_bb0_veir/6_function_22.mlir new file mode 100644 index 0000000..21a773c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_22.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_23.mlir b/benchmarks/MLIR_bb0_veir/6_function_23.mlir new file mode 100644 index 0000000..e83ca36 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_23.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.or"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %3) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%0, %4) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_24.mlir b/benchmarks/MLIR_bb0_veir/6_function_24.mlir new file mode 100644 index 0000000..00023e0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_24.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.udiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_25.mlir b/benchmarks/MLIR_bb0_veir/6_function_25.mlir new file mode 100644 index 0000000..035192d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_25.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.ashr"(%2, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_26.mlir b/benchmarks/MLIR_bb0_veir/6_function_26.mlir new file mode 100644 index 0000000..e5c996a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_26.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.srem"(%arg0, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_27.mlir b/benchmarks/MLIR_bb0_veir/6_function_27.mlir new file mode 100644 index 0000000..d209ca1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_27.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.and"(%arg2, %arg1) : (i64, i64) -> i64 + %3 = "llvm.or"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_28.mlir b/benchmarks/MLIR_bb0_veir/6_function_28.mlir new file mode 100644 index 0000000..505b9f9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_28.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.ashr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_29.mlir b/benchmarks/MLIR_bb0_veir/6_function_29.mlir new file mode 100644 index 0000000..c52aefa --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_29.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.or"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_3.mlir b/benchmarks/MLIR_bb0_veir/6_function_3.mlir new file mode 100644 index 0000000..41dde33 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_3.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_30.mlir b/benchmarks/MLIR_bb0_veir/6_function_30.mlir new file mode 100644 index 0000000..9541845 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_30.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_31.mlir b/benchmarks/MLIR_bb0_veir/6_function_31.mlir new file mode 100644 index 0000000..6e5c9d0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_31.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.zext"(%0) : (i32) -> i64 + %3 = "llvm.sdiv"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.ashr"(%3, %2) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.icmp"(%arg0, %4) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_32.mlir b/benchmarks/MLIR_bb0_veir/6_function_32.mlir new file mode 100644 index 0000000..329d357 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_32.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i32): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.sext"(%arg2) : (i32) -> i64 + %3 = "llvm.udiv"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_33.mlir b/benchmarks/MLIR_bb0_veir/6_function_33.mlir new file mode 100644 index 0000000..61fee56 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_33.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.ashr"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_34.mlir b/benchmarks/MLIR_bb0_veir/6_function_34.mlir new file mode 100644 index 0000000..ec7e5a2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_34.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.select"(%arg2, %0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.srem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_35.mlir b/benchmarks/MLIR_bb0_veir/6_function_35.mlir new file mode 100644 index 0000000..af180c2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_35.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.srem"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg1) : (i32) -> i64 + %4 = "llvm.lshr"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%arg0, %4) <{isExact}> : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_36.mlir b/benchmarks/MLIR_bb0_veir/6_function_36.mlir new file mode 100644 index 0000000..b626331 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_36.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.xor"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_37.mlir b/benchmarks/MLIR_bb0_veir/6_function_37.mlir new file mode 100644 index 0000000..e18fc3e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_37.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_38.mlir b/benchmarks/MLIR_bb0_veir/6_function_38.mlir new file mode 100644 index 0000000..8c9fd91 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_38.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg2) : (i32) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_39.mlir b/benchmarks/MLIR_bb0_veir/6_function_39.mlir new file mode 100644 index 0000000..c5c13d0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_39.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_4.mlir b/benchmarks/MLIR_bb0_veir/6_function_4.mlir new file mode 100644 index 0000000..6ddda98 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_4.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.ashr"(%2, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_40.mlir b/benchmarks/MLIR_bb0_veir/6_function_40.mlir new file mode 100644 index 0000000..7a86313 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_40.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_41.mlir b/benchmarks/MLIR_bb0_veir/6_function_41.mlir new file mode 100644 index 0000000..6f7ab38 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_41.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.srem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_42.mlir b/benchmarks/MLIR_bb0_veir/6_function_42.mlir new file mode 100644 index 0000000..5d5749e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_42.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.lshr"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_43.mlir b/benchmarks/MLIR_bb0_veir/6_function_43.mlir new file mode 100644 index 0000000..4b684f8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_43.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %4 = "llvm.select"(%3, %2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_44.mlir b/benchmarks/MLIR_bb0_veir/6_function_44.mlir new file mode 100644 index 0000000..7c1589c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_44.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.lshr"(%arg0, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_45.mlir b/benchmarks/MLIR_bb0_veir/6_function_45.mlir new file mode 100644 index 0000000..a561344 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_45.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.select"(%arg1, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.icmp"(%1, %4) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_46.mlir b/benchmarks/MLIR_bb0_veir/6_function_46.mlir new file mode 100644 index 0000000..0cd5467 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_46.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 3 : i64}> : (i64, i64) -> i1 + %1 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%1, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%0, %2, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_47.mlir b/benchmarks/MLIR_bb0_veir/6_function_47.mlir new file mode 100644 index 0000000..509fdf2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_47.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_48.mlir b/benchmarks/MLIR_bb0_veir/6_function_48.mlir new file mode 100644 index 0000000..cd6f1a2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_48.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i1, %arg2: i64): + %0 = "llvm.srem"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.srem"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %5 = "llvm.select"(%4, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_49.mlir b/benchmarks/MLIR_bb0_veir/6_function_49.mlir new file mode 100644 index 0000000..8cc4c08 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_49.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.urem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.or"(%2, %4) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_5.mlir b/benchmarks/MLIR_bb0_veir/6_function_5.mlir new file mode 100644 index 0000000..03e1c64 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_5.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.icmp"(%0, %4) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_50.mlir b/benchmarks/MLIR_bb0_veir/6_function_50.mlir new file mode 100644 index 0000000..b3600a9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_50.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%arg2, %1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.urem"(%3, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_51.mlir b/benchmarks/MLIR_bb0_veir/6_function_51.mlir new file mode 100644 index 0000000..18bf964 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_51.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.and"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%0, %4) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_52.mlir b/benchmarks/MLIR_bb0_veir/6_function_52.mlir new file mode 100644 index 0000000..a7b13d9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_52.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_53.mlir b/benchmarks/MLIR_bb0_veir/6_function_53.mlir new file mode 100644 index 0000000..a3f0cac --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_53.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.zext"(%arg1) : (i32) -> i64 + %1 = "llvm.xor"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %0) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%3, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_54.mlir b/benchmarks/MLIR_bb0_veir/6_function_54.mlir new file mode 100644 index 0000000..3f5f7c5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_54.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.urem"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%3, %4) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_55.mlir b/benchmarks/MLIR_bb0_veir/6_function_55.mlir new file mode 100644 index 0000000..dd376ad --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_55.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_56.mlir b/benchmarks/MLIR_bb0_veir/6_function_56.mlir new file mode 100644 index 0000000..3b2d699 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_56.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.and"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg0, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_57.mlir b/benchmarks/MLIR_bb0_veir/6_function_57.mlir new file mode 100644 index 0000000..ab701a6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_57.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_58.mlir b/benchmarks/MLIR_bb0_veir/6_function_58.mlir new file mode 100644 index 0000000..3fd0525 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_58.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%0, %arg0, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_59.mlir b/benchmarks/MLIR_bb0_veir/6_function_59.mlir new file mode 100644 index 0000000..2787e3e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_59.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_6.mlir b/benchmarks/MLIR_bb0_veir/6_function_6.mlir new file mode 100644 index 0000000..435e9cb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_6.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_60.mlir b/benchmarks/MLIR_bb0_veir/6_function_60.mlir new file mode 100644 index 0000000..28f2fce --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_60.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_61.mlir b/benchmarks/MLIR_bb0_veir/6_function_61.mlir new file mode 100644 index 0000000..770a2a8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_61.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.and"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%1, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_62.mlir b/benchmarks/MLIR_bb0_veir/6_function_62.mlir new file mode 100644 index 0000000..9da655c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_62.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.select"(%3, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_63.mlir b/benchmarks/MLIR_bb0_veir/6_function_63.mlir new file mode 100644 index 0000000..ae41e1d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_63.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_64.mlir b/benchmarks/MLIR_bb0_veir/6_function_64.mlir new file mode 100644 index 0000000..654545f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_64.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%arg2, %arg2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.srem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%0, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_65.mlir b/benchmarks/MLIR_bb0_veir/6_function_65.mlir new file mode 100644 index 0000000..4d3a7b3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_65.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.sext"(%1) : (i32) -> i64 + %4 = "llvm.sdiv"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_66.mlir b/benchmarks/MLIR_bb0_veir/6_function_66.mlir new file mode 100644 index 0000000..c527bf9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_66.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.sdiv"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_67.mlir b/benchmarks/MLIR_bb0_veir/6_function_67.mlir new file mode 100644 index 0000000..8457c5e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_67.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%arg0, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_68.mlir b/benchmarks/MLIR_bb0_veir/6_function_68.mlir new file mode 100644 index 0000000..872f15f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_68.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.udiv"(%1, %arg1) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_69.mlir b/benchmarks/MLIR_bb0_veir/6_function_69.mlir new file mode 100644 index 0000000..3818401 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_69.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg3) : (i32) -> i64 + %3 = "llvm.sdiv"(%2, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.select"(%0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_7.mlir b/benchmarks/MLIR_bb0_veir/6_function_7.mlir new file mode 100644 index 0000000..e741c34 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_7.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.ashr"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_70.mlir b/benchmarks/MLIR_bb0_veir/6_function_70.mlir new file mode 100644 index 0000000..4988e4c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_70.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.ashr"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_71.mlir b/benchmarks/MLIR_bb0_veir/6_function_71.mlir new file mode 100644 index 0000000..c9aaa26 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_71.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%3, %0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_72.mlir b/benchmarks/MLIR_bb0_veir/6_function_72.mlir new file mode 100644 index 0000000..b5c2812 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_72.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %0) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_73.mlir b/benchmarks/MLIR_bb0_veir/6_function_73.mlir new file mode 100644 index 0000000..22e39fa --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_73.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_74.mlir b/benchmarks/MLIR_bb0_veir/6_function_74.mlir new file mode 100644 index 0000000..54e88c8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_74.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_75.mlir b/benchmarks/MLIR_bb0_veir/6_function_75.mlir new file mode 100644 index 0000000..3ae3f11 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_75.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.ashr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.sext"(%arg2) : (i32) -> i64 + %5 = "llvm.ashr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_76.mlir b/benchmarks/MLIR_bb0_veir/6_function_76.mlir new file mode 100644 index 0000000..c8bd714 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_76.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg0) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.urem"(%arg2, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_77.mlir b/benchmarks/MLIR_bb0_veir/6_function_77.mlir new file mode 100644 index 0000000..8688bb8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_77.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.udiv"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_78.mlir b/benchmarks/MLIR_bb0_veir/6_function_78.mlir new file mode 100644 index 0000000..ea6acb8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_78.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.udiv"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%1, %4) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_79.mlir b/benchmarks/MLIR_bb0_veir/6_function_79.mlir new file mode 100644 index 0000000..56580f4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_79.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.icmp"(%1, %4) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_8.mlir b/benchmarks/MLIR_bb0_veir/6_function_8.mlir new file mode 100644 index 0000000..f0414a2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_8.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg2, %arg2) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%2, %4) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_80.mlir b/benchmarks/MLIR_bb0_veir/6_function_80.mlir new file mode 100644 index 0000000..c230535 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_80.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_81.mlir b/benchmarks/MLIR_bb0_veir/6_function_81.mlir new file mode 100644 index 0000000..7a9cc85 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_81.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.udiv"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_82.mlir b/benchmarks/MLIR_bb0_veir/6_function_82.mlir new file mode 100644 index 0000000..09b09a2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_82.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%arg1, %0) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %2 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.udiv"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_83.mlir b/benchmarks/MLIR_bb0_veir/6_function_83.mlir new file mode 100644 index 0000000..3cb5c4c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_83.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.ashr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.select"(%1, %arg1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.ashr"(%4, %4) <{isExact}> : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_84.mlir b/benchmarks/MLIR_bb0_veir/6_function_84.mlir new file mode 100644 index 0000000..b122a4f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_84.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.lshr"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg3) : (i32) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %5 = "llvm.select"(%4, %2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_85.mlir b/benchmarks/MLIR_bb0_veir/6_function_85.mlir new file mode 100644 index 0000000..5d8640a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_85.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%arg0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_86.mlir b/benchmarks/MLIR_bb0_veir/6_function_86.mlir new file mode 100644 index 0000000..25e5e62 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_86.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg2, %2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.xor"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.or"(%2, %4) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_87.mlir b/benchmarks/MLIR_bb0_veir/6_function_87.mlir new file mode 100644 index 0000000..ca42e3a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_87.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.urem"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_88.mlir b/benchmarks/MLIR_bb0_veir/6_function_88.mlir new file mode 100644 index 0000000..f0ec5b0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_88.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.or"(%0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.srem"(%3, %arg0) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%3, %4) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_89.mlir b/benchmarks/MLIR_bb0_veir/6_function_89.mlir new file mode 100644 index 0000000..715b307 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_89.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.and"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_9.mlir b/benchmarks/MLIR_bb0_veir/6_function_9.mlir new file mode 100644 index 0000000..ee401f5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_9.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i1, %arg3: i32): + %0 = "llvm.sext"(%arg3) : (i32) -> i64 + %1 = "llvm.select"(%arg2, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_90.mlir b/benchmarks/MLIR_bb0_veir/6_function_90.mlir new file mode 100644 index 0000000..6b3170c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_90.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%1, %arg2) : (i64, i64) -> i64 + %4 = "llvm.or"(%2, %3) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.icmp"(%arg0, %4) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_91.mlir b/benchmarks/MLIR_bb0_veir/6_function_91.mlir new file mode 100644 index 0000000..b4c58a8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_91.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_92.mlir b/benchmarks/MLIR_bb0_veir/6_function_92.mlir new file mode 100644 index 0000000..dbeb827 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_92.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.srem"(%arg0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_93.mlir b/benchmarks/MLIR_bb0_veir/6_function_93.mlir new file mode 100644 index 0000000..f5165d1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_93.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_94.mlir b/benchmarks/MLIR_bb0_veir/6_function_94.mlir new file mode 100644 index 0000000..d7d9aa1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_94.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.urem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%3, %0) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%0, %4) : (i64, i64) -> i64 + "func.return"(%5) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_95.mlir b/benchmarks/MLIR_bb0_veir/6_function_95.mlir new file mode 100644 index 0000000..dcb0858 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_95.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.urem"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_96.mlir b/benchmarks/MLIR_bb0_veir/6_function_96.mlir new file mode 100644 index 0000000..1e3bfd4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_96.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.lshr"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%0, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_97.mlir b/benchmarks/MLIR_bb0_veir/6_function_97.mlir new file mode 100644 index 0000000..e6a4e31 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_97.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.and"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%5) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_98.mlir b/benchmarks/MLIR_bb0_veir/6_function_98.mlir new file mode 100644 index 0000000..da7fd5e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_98.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.icmp"(%2, %4) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/6_function_99.mlir b/benchmarks/MLIR_bb0_veir/6_function_99.mlir new file mode 100644 index 0000000..fb800b3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/6_function_99.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.icmp"(%arg2, %arg0) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.sext"(%arg3) : (i32) -> i64 + %2 = "llvm.select"(%0, %1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.urem"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%5) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_0.mlir b/benchmarks/MLIR_bb0_veir/7_function_0.mlir new file mode 100644 index 0000000..b237861 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_0.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.select"(%1, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.sdiv"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_1.mlir b/benchmarks/MLIR_bb0_veir/7_function_1.mlir new file mode 100644 index 0000000..3edd2bc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_1.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.sdiv"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_10.mlir b/benchmarks/MLIR_bb0_veir/7_function_10.mlir new file mode 100644 index 0000000..2d16d85 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_10.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.lshr"(%0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.urem"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%2, %5) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_11.mlir b/benchmarks/MLIR_bb0_veir/7_function_11.mlir new file mode 100644 index 0000000..3f96cbd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_11.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.xor"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.sdiv"(%1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_12.mlir b/benchmarks/MLIR_bb0_veir/7_function_12.mlir new file mode 100644 index 0000000..3d22dc5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_12.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %arg0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %1) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%arg1, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%2, %5) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_13.mlir b/benchmarks/MLIR_bb0_veir/7_function_13.mlir new file mode 100644 index 0000000..dd000f1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_13.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_14.mlir b/benchmarks/MLIR_bb0_veir/7_function_14.mlir new file mode 100644 index 0000000..1a01450 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_14.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i1): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.select"(%arg2, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.or"(%3, %4) <{isDisjoint}> : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_15.mlir b/benchmarks/MLIR_bb0_veir/7_function_15.mlir new file mode 100644 index 0000000..800154d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_15.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.icmp"(%arg0, %0) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %2 = "llvm.srem"(%arg2, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.select"(%1, %3, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_16.mlir b/benchmarks/MLIR_bb0_veir/7_function_16.mlir new file mode 100644 index 0000000..8052161 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_16.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg3) : (i32) -> i64 + %3 = "llvm.ashr"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_17.mlir b/benchmarks/MLIR_bb0_veir/7_function_17.mlir new file mode 100644 index 0000000..2aa9cdb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_17.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg2, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg2, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg1, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%arg0, %5) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_18.mlir b/benchmarks/MLIR_bb0_veir/7_function_18.mlir new file mode 100644 index 0000000..288a7f4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_18.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.or"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%arg1, %3) : (i64, i64) -> i64 + %6 = "llvm.and"(%4, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_19.mlir b/benchmarks/MLIR_bb0_veir/7_function_19.mlir new file mode 100644 index 0000000..6f5db00 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_19.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%3, %0) : (i64, i64) -> i64 + %5 = "llvm.urem"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_2.mlir b/benchmarks/MLIR_bb0_veir/7_function_2.mlir new file mode 100644 index 0000000..941982c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_2.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_20.mlir b/benchmarks/MLIR_bb0_veir/7_function_20.mlir new file mode 100644 index 0000000..6e97556 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_20.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %2 = "llvm.urem"(%arg2, %arg1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%1, %arg0, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.sdiv"(%0, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.lshr"(%arg0, %5) <{isExact}> : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_21.mlir b/benchmarks/MLIR_bb0_veir/7_function_21.mlir new file mode 100644 index 0000000..026c301 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_21.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %arg1) <{predicate = 9 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.and"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%4, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_22.mlir b/benchmarks/MLIR_bb0_veir/7_function_22.mlir new file mode 100644 index 0000000..84e44de --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_22.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.lshr"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_23.mlir b/benchmarks/MLIR_bb0_veir/7_function_23.mlir new file mode 100644 index 0000000..c73d33b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_23.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_24.mlir b/benchmarks/MLIR_bb0_veir/7_function_24.mlir new file mode 100644 index 0000000..e51d457 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_24.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.or"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.srem"(%2, %0) : (i64, i64) -> i64 + %6 = "llvm.urem"(%4, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_25.mlir b/benchmarks/MLIR_bb0_veir/7_function_25.mlir new file mode 100644 index 0000000..043378e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_25.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.select"(%1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.zext"(%arg3) : (i32) -> i64 + %5 = "llvm.urem"(%2, %0) : (i64, i64) -> i64 + %6 = "llvm.select"(%3, %4, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_26.mlir b/benchmarks/MLIR_bb0_veir/7_function_26.mlir new file mode 100644 index 0000000..ea051d3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_26.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg2, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.ashr"(%2, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_27.mlir b/benchmarks/MLIR_bb0_veir/7_function_27.mlir new file mode 100644 index 0000000..b1617ed --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_27.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg1, %2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%2, %3) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %5 = "llvm.select"(%4, %arg0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_28.mlir b/benchmarks/MLIR_bb0_veir/7_function_28.mlir new file mode 100644 index 0000000..dc1346f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_28.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.srem"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_29.mlir b/benchmarks/MLIR_bb0_veir/7_function_29.mlir new file mode 100644 index 0000000..657c4b9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_29.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.select"(%0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.sext"(%arg3) : (i32) -> i64 + %3 = "llvm.xor"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%arg2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.and"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.and"(%5, %arg0) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_3.mlir b/benchmarks/MLIR_bb0_veir/7_function_3.mlir new file mode 100644 index 0000000..6888e5f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_3.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.zext"(%arg2) : (i32) -> i64 + %3 = "llvm.srem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.sext"(%arg2) : (i32) -> i64 + %5 = "llvm.ashr"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%3, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_30.mlir b/benchmarks/MLIR_bb0_veir/7_function_30.mlir new file mode 100644 index 0000000..0c42364 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_30.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.select"(%arg0, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.lshr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_31.mlir b/benchmarks/MLIR_bb0_veir/7_function_31.mlir new file mode 100644 index 0000000..4b9f928 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_31.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.and"(%4, %2) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%arg0, %5) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_32.mlir b/benchmarks/MLIR_bb0_veir/7_function_32.mlir new file mode 100644 index 0000000..c0e4ba8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_32.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %6 = "llvm.xor"(%4, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_33.mlir b/benchmarks/MLIR_bb0_veir/7_function_33.mlir new file mode 100644 index 0000000..ca46e1e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_33.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %arg1) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.srem"(%4, %arg0) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%arg0, %5) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_34.mlir b/benchmarks/MLIR_bb0_veir/7_function_34.mlir new file mode 100644 index 0000000..5b3ed39 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_34.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %arg1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.lshr"(%3, %1) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_35.mlir b/benchmarks/MLIR_bb0_veir/7_function_35.mlir new file mode 100644 index 0000000..43109cb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_35.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.zext"(%0) : (i32) -> i64 + %3 = "llvm.ashr"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.lshr"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.and"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_36.mlir b/benchmarks/MLIR_bb0_veir/7_function_36.mlir new file mode 100644 index 0000000..b2ab9b3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_36.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%arg1, %0) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %3 = "llvm.or"(%1, %1) : (i64, i64) -> i64 + %4 = "llvm.select"(%2, %3, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%1, %5) <{isExact}> : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_37.mlir b/benchmarks/MLIR_bb0_veir/7_function_37.mlir new file mode 100644 index 0000000..51797a1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_37.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.srem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_38.mlir b/benchmarks/MLIR_bb0_veir/7_function_38.mlir new file mode 100644 index 0000000..2db70fd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_38.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%2, %arg2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %4 = "llvm.select"(%3, %0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.or"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_39.mlir b/benchmarks/MLIR_bb0_veir/7_function_39.mlir new file mode 100644 index 0000000..150201d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_39.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_4.mlir b/benchmarks/MLIR_bb0_veir/7_function_4.mlir new file mode 100644 index 0000000..60c7369 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_4.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%arg1, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%arg0, %5) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_40.mlir b/benchmarks/MLIR_bb0_veir/7_function_40.mlir new file mode 100644 index 0000000..5a46b69 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_40.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg2) : (i32) -> i64 + %4 = "llvm.srem"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%4, %3) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.ashr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_41.mlir b/benchmarks/MLIR_bb0_veir/7_function_41.mlir new file mode 100644 index 0000000..02798fc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_41.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%0, %arg2) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_42.mlir b/benchmarks/MLIR_bb0_veir/7_function_42.mlir new file mode 100644 index 0000000..4896097 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_42.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg1, %arg0) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_43.mlir b/benchmarks/MLIR_bb0_veir/7_function_43.mlir new file mode 100644 index 0000000..e7bccb3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_43.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg0, %arg1, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_44.mlir b/benchmarks/MLIR_bb0_veir/7_function_44.mlir new file mode 100644 index 0000000..e9196bc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_44.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg2, %arg0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.xor"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_45.mlir b/benchmarks/MLIR_bb0_veir/7_function_45.mlir new file mode 100644 index 0000000..eb56ac0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_45.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg2, %arg1) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.and"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_46.mlir b/benchmarks/MLIR_bb0_veir/7_function_46.mlir new file mode 100644 index 0000000..21e36ef --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_46.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.ashr"(%arg1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.select"(%0, %1, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_47.mlir b/benchmarks/MLIR_bb0_veir/7_function_47.mlir new file mode 100644 index 0000000..886cc83 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_47.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %arg0, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.xor"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_48.mlir b/benchmarks/MLIR_bb0_veir/7_function_48.mlir new file mode 100644 index 0000000..592bb7e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_48.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_49.mlir b/benchmarks/MLIR_bb0_veir/7_function_49.mlir new file mode 100644 index 0000000..cbabc9e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_49.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%2, %1) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.or"(%3, %4) <{isDisjoint}> : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_5.mlir b/benchmarks/MLIR_bb0_veir/7_function_5.mlir new file mode 100644 index 0000000..da125e6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_5.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_50.mlir b/benchmarks/MLIR_bb0_veir/7_function_50.mlir new file mode 100644 index 0000000..58ba536 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_50.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg2, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%2, %arg1) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_51.mlir b/benchmarks/MLIR_bb0_veir/7_function_51.mlir new file mode 100644 index 0000000..30ec8f6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_51.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg3, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg3, %1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.udiv"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%arg2, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%0, %5) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_52.mlir b/benchmarks/MLIR_bb0_veir/7_function_52.mlir new file mode 100644 index 0000000..cfb1c52 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_52.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.sext"(%0) : (i32) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%1, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_53.mlir b/benchmarks/MLIR_bb0_veir/7_function_53.mlir new file mode 100644 index 0000000..591308f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_53.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.or"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_54.mlir b/benchmarks/MLIR_bb0_veir/7_function_54.mlir new file mode 100644 index 0000000..d7cc3ac --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_54.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_55.mlir b/benchmarks/MLIR_bb0_veir/7_function_55.mlir new file mode 100644 index 0000000..a26ed72 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_55.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_56.mlir b/benchmarks/MLIR_bb0_veir/7_function_56.mlir new file mode 100644 index 0000000..35e1179 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_56.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.or"(%1, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_57.mlir b/benchmarks/MLIR_bb0_veir/7_function_57.mlir new file mode 100644 index 0000000..3c0cbd4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_57.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%arg2, %arg2) : (i64, i64) -> i64 + %3 = "llvm.and"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_58.mlir b/benchmarks/MLIR_bb0_veir/7_function_58.mlir new file mode 100644 index 0000000..c1d2e52 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_58.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.and"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%3, %5) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_59.mlir b/benchmarks/MLIR_bb0_veir/7_function_59.mlir new file mode 100644 index 0000000..871d616 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_59.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_6.mlir b/benchmarks/MLIR_bb0_veir/7_function_6.mlir new file mode 100644 index 0000000..7f3636d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_6.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_60.mlir b/benchmarks/MLIR_bb0_veir/7_function_60.mlir new file mode 100644 index 0000000..e5f516a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_60.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.or"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%3, %arg0) : (i64, i64) -> i64 + %5 = "llvm.srem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_61.mlir b/benchmarks/MLIR_bb0_veir/7_function_61.mlir new file mode 100644 index 0000000..955258c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_61.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.zext"(%arg2) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.select"(%1, %4, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.icmp"(%5, %4) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_62.mlir b/benchmarks/MLIR_bb0_veir/7_function_62.mlir new file mode 100644 index 0000000..f357541 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_62.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.or"(%1, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_63.mlir b/benchmarks/MLIR_bb0_veir/7_function_63.mlir new file mode 100644 index 0000000..d10e040 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_63.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.sdiv"(%4, %arg0) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_64.mlir b/benchmarks/MLIR_bb0_veir/7_function_64.mlir new file mode 100644 index 0000000..c586660 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_64.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%arg1, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_65.mlir b/benchmarks/MLIR_bb0_veir/7_function_65.mlir new file mode 100644 index 0000000..26055a2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_65.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.and"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%4, %arg2) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_66.mlir b/benchmarks/MLIR_bb0_veir/7_function_66.mlir new file mode 100644 index 0000000..032c0f7 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_66.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.icmp"(%1, %2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %4 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %5 = "llvm.urem"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.select"(%3, %arg1, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_67.mlir b/benchmarks/MLIR_bb0_veir/7_function_67.mlir new file mode 100644 index 0000000..5dbe332 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_67.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%4, %2) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_68.mlir b/benchmarks/MLIR_bb0_veir/7_function_68.mlir new file mode 100644 index 0000000..d79c6b5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_68.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %5 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %6 = "llvm.select"(%4, %3, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_69.mlir b/benchmarks/MLIR_bb0_veir/7_function_69.mlir new file mode 100644 index 0000000..1138fac --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_69.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.or"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.or"(%2, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_7.mlir b/benchmarks/MLIR_bb0_veir/7_function_7.mlir new file mode 100644 index 0000000..83357bd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_7.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.lshr"(%arg2, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.sext"(%arg3) : (i32) -> i64 + %5 = "llvm.or"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%3, %5) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_70.mlir b/benchmarks/MLIR_bb0_veir/7_function_70.mlir new file mode 100644 index 0000000..3f1612b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_70.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.xor"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_71.mlir b/benchmarks/MLIR_bb0_veir/7_function_71.mlir new file mode 100644 index 0000000..5c7db56 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_71.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %6 = "llvm.srem"(%4, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_72.mlir b/benchmarks/MLIR_bb0_veir/7_function_72.mlir new file mode 100644 index 0000000..448552f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_72.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_73.mlir b/benchmarks/MLIR_bb0_veir/7_function_73.mlir new file mode 100644 index 0000000..f857ab5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_73.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32, %arg1: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_74.mlir b/benchmarks/MLIR_bb0_veir/7_function_74.mlir new file mode 100644 index 0000000..9ebe4b5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_74.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.zext"(%arg2) : (i32) -> i64 + %1 = "llvm.lshr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_75.mlir b/benchmarks/MLIR_bb0_veir/7_function_75.mlir new file mode 100644 index 0000000..e63f259 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_75.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %arg0) : (i64, i64) -> i64 + %4 = "llvm.xor"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.select"(%1, %arg2, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_76.mlir b/benchmarks/MLIR_bb0_veir/7_function_76.mlir new file mode 100644 index 0000000..a7dcc39 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_76.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.or"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_77.mlir b/benchmarks/MLIR_bb0_veir/7_function_77.mlir new file mode 100644 index 0000000..f526723 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_77.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.sdiv"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %0) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%3, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_78.mlir b/benchmarks/MLIR_bb0_veir/7_function_78.mlir new file mode 100644 index 0000000..b89ac75 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_78.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg1) : (i32) -> i64 + %2 = "llvm.udiv"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.or"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%0, %5) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_79.mlir b/benchmarks/MLIR_bb0_veir/7_function_79.mlir new file mode 100644 index 0000000..12fb291 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_79.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.srem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.or"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_8.mlir b/benchmarks/MLIR_bb0_veir/7_function_8.mlir new file mode 100644 index 0000000..bb1b79e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_8.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg1, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.select"(%arg0, %arg1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.urem"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.or"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%2, %5) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_80.mlir b/benchmarks/MLIR_bb0_veir/7_function_80.mlir new file mode 100644 index 0000000..bb0e281 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_80.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %1 = "llvm.udiv"(%arg2, %arg1) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %arg2) : (i64, i64) -> i64 + %4 = "llvm.icmp"(%arg1, %3) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %5 = "llvm.select"(%4, %2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.ashr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_81.mlir b/benchmarks/MLIR_bb0_veir/7_function_81.mlir new file mode 100644 index 0000000..c67727c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_81.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.lshr"(%0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg0) : (i32) -> i64 + %4 = "llvm.xor"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.or"(%2, %5) <{isDisjoint}> : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_82.mlir b/benchmarks/MLIR_bb0_veir/7_function_82.mlir new file mode 100644 index 0000000..b4c3145 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_82.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.ashr"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.or"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_83.mlir b/benchmarks/MLIR_bb0_veir/7_function_83.mlir new file mode 100644 index 0000000..83bafac --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_83.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.sdiv"(%4, %arg2) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_84.mlir b/benchmarks/MLIR_bb0_veir/7_function_84.mlir new file mode 100644 index 0000000..59debd8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_84.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.and"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.and"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%4, %0) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_85.mlir b/benchmarks/MLIR_bb0_veir/7_function_85.mlir new file mode 100644 index 0000000..2eb246d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_85.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.select"(%arg0, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%0, %arg2) : (i64, i64) -> i64 + %5 = "llvm.urem"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_86.mlir b/benchmarks/MLIR_bb0_veir/7_function_86.mlir new file mode 100644 index 0000000..7d83b06 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_86.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.or"(%0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.srem"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_87.mlir b/benchmarks/MLIR_bb0_veir/7_function_87.mlir new file mode 100644 index 0000000..1fe33f9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_87.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.xor"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.icmp"(%2, %5) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_88.mlir b/benchmarks/MLIR_bb0_veir/7_function_88.mlir new file mode 100644 index 0000000..e3feeb0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_88.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.select"(%arg1, %arg0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%2, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_89.mlir b/benchmarks/MLIR_bb0_veir/7_function_89.mlir new file mode 100644 index 0000000..d906b9a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_89.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg2) : (i32) -> i64 + %2 = "llvm.udiv"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_9.mlir b/benchmarks/MLIR_bb0_veir/7_function_9.mlir new file mode 100644 index 0000000..af77f52 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_9.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.or"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_90.mlir b/benchmarks/MLIR_bb0_veir/7_function_90.mlir new file mode 100644 index 0000000..b2582a6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_90.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_91.mlir b/benchmarks/MLIR_bb0_veir/7_function_91.mlir new file mode 100644 index 0000000..2321a9b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_91.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.sext"(%arg3) : (i32) -> i64 + %5 = "llvm.urem"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.icmp"(%3, %5) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_92.mlir b/benchmarks/MLIR_bb0_veir/7_function_92.mlir new file mode 100644 index 0000000..4786aae --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_92.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.and"(%arg1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %5 = "llvm.select"(%4, %arg2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_93.mlir b/benchmarks/MLIR_bb0_veir/7_function_93.mlir new file mode 100644 index 0000000..42c8e22 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_93.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.udiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_94.mlir b/benchmarks/MLIR_bb0_veir/7_function_94.mlir new file mode 100644 index 0000000..ce6b976 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_94.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%3, %arg0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%6) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_95.mlir b/benchmarks/MLIR_bb0_veir/7_function_95.mlir new file mode 100644 index 0000000..225685d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_95.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_96.mlir b/benchmarks/MLIR_bb0_veir/7_function_96.mlir new file mode 100644 index 0000000..2486908 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_96.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%0, %arg1) : (i64, i64) -> i64 + %5 = "llvm.xor"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%6) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_97.mlir b/benchmarks/MLIR_bb0_veir/7_function_97.mlir new file mode 100644 index 0000000..82965a1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_97.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.lshr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.xor"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%arg0, %5) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_98.mlir b/benchmarks/MLIR_bb0_veir/7_function_98.mlir new file mode 100644 index 0000000..4c2dacd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_98.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%1, %0) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %3 = "llvm.ashr"(%0, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%2, %3, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.and"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%5, %1) : (i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/7_function_99.mlir b/benchmarks/MLIR_bb0_veir/7_function_99.mlir new file mode 100644 index 0000000..303200c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/7_function_99.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.select"(%3, %arg1, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%6) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_0.mlir b/benchmarks/MLIR_bb0_veir/8_function_0.mlir new file mode 100644 index 0000000..558bee9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_0.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.ashr"(%arg0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.or"(%arg1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %arg2) : (i64, i64) -> i64 + %6 = "llvm.and"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_1.mlir b/benchmarks/MLIR_bb0_veir/8_function_1.mlir new file mode 100644 index 0000000..0cad7cf --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_1.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i32, %arg2: i1): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.srem"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.sext"(%arg1) : (i32) -> i64 + %5 = "llvm.select"(%arg2, %0, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.srem"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.srem"(%3, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_10.mlir b/benchmarks/MLIR_bb0_veir/8_function_10.mlir new file mode 100644 index 0000000..6d0ef9c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_10.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.lshr"(%0, %arg2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%4, %2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %6 = "llvm.select"(%5, %0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.select"(%3, %6, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_11.mlir b/benchmarks/MLIR_bb0_veir/8_function_11.mlir new file mode 100644 index 0000000..bfaa479 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_11.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.lshr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.zext"(%arg3) : (i32) -> i64 + %6 = "llvm.and"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_12.mlir b/benchmarks/MLIR_bb0_veir/8_function_12.mlir new file mode 100644 index 0000000..b7a9b35 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_12.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%arg1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.lshr"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_13.mlir b/benchmarks/MLIR_bb0_veir/8_function_13.mlir new file mode 100644 index 0000000..717ee0b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_13.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.urem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.or"(%0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.and"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %7 = "llvm.zext"(%6) : (i32) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_14.mlir b/benchmarks/MLIR_bb0_veir/8_function_14.mlir new file mode 100644 index 0000000..0b8e364 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_14.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32, %arg3: i1): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.ashr"(%arg1, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.urem"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %arg1, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.lshr"(%4, %3) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.urem"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_15.mlir b/benchmarks/MLIR_bb0_veir/8_function_15.mlir new file mode 100644 index 0000000..b1c0b1d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_15.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg0, %1) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %3 = "llvm.sdiv"(%arg0, %0) : (i64, i64) -> i64 + %4 = "llvm.select"(%2, %arg2, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.zext"(%arg3) : (i32) -> i64 + %6 = "llvm.and"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_16.mlir b/benchmarks/MLIR_bb0_veir/8_function_16.mlir new file mode 100644 index 0000000..958bb97 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_16.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%5, %arg2) : (i64, i64) -> i64 + %7 = "llvm.sdiv"(%1, %6) <{isExact}> : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_17.mlir b/benchmarks/MLIR_bb0_veir/8_function_17.mlir new file mode 100644 index 0000000..fae6927 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_17.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.urem"(%arg1, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg1, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_18.mlir b/benchmarks/MLIR_bb0_veir/8_function_18.mlir new file mode 100644 index 0000000..a1ba0b6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_18.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.lshr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%4, %6) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_19.mlir b/benchmarks/MLIR_bb0_veir/8_function_19.mlir new file mode 100644 index 0000000..8480ed5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_19.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.select"(%3, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%6, %4) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_2.mlir b/benchmarks/MLIR_bb0_veir/8_function_2.mlir new file mode 100644 index 0000000..de26285 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_2.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.sext"(%arg1) : (i32) -> i64 + %1 = "llvm.and"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.sext"(%arg1) : (i32) -> i64 + %3 = "llvm.urem"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.and"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%arg2, %0) : (i64, i64) -> i64 + %7 = "llvm.urem"(%5, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_20.mlir b/benchmarks/MLIR_bb0_veir/8_function_20.mlir new file mode 100644 index 0000000..f190b22 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_20.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.lshr"(%3, %1) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.and"(%5, %arg0) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_21.mlir b/benchmarks/MLIR_bb0_veir/8_function_21.mlir new file mode 100644 index 0000000..108866c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_21.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.srem"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%arg2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_22.mlir b/benchmarks/MLIR_bb0_veir/8_function_22.mlir new file mode 100644 index 0000000..9eaf0fc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_22.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.lshr"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.ashr"(%1, %arg2) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.urem"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg2, %arg1) : (i64, i64) -> i64 + %5 = "llvm.select"(%0, %4, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.select"(%0, %3, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_23.mlir b/benchmarks/MLIR_bb0_veir/8_function_23.mlir new file mode 100644 index 0000000..3aad950 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_23.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.udiv"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%arg1, %1) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.srem"(%2, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_24.mlir b/benchmarks/MLIR_bb0_veir/8_function_24.mlir new file mode 100644 index 0000000..13ba10f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_24.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.udiv"(%arg2, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%0, %6) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_25.mlir b/benchmarks/MLIR_bb0_veir/8_function_25.mlir new file mode 100644 index 0000000..eb35d71 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_25.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64, %arg3: i32): + %0 = "llvm.select"(%arg1, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.sext"(%arg3) : (i32) -> i64 + %3 = "llvm.lshr"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.lshr"(%3, %2) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_26.mlir b/benchmarks/MLIR_bb0_veir/8_function_26.mlir new file mode 100644 index 0000000..97ac6fb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_26.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sext"(%arg1) : (i32) -> i64 + %2 = "llvm.udiv"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.ashr"(%3, %2) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.sdiv"(%6, %4) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_27.mlir b/benchmarks/MLIR_bb0_veir/8_function_27.mlir new file mode 100644 index 0000000..474945d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_27.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.ashr"(%0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.and"(%arg0, %1) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.ashr"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.urem"(%arg0, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_28.mlir b/benchmarks/MLIR_bb0_veir/8_function_28.mlir new file mode 100644 index 0000000..3867449 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_28.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.select"(%0, %1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.zext"(%arg1) : (i32) -> i64 + %4 = "llvm.ashr"(%2, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%4, %6) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_29.mlir b/benchmarks/MLIR_bb0_veir/8_function_29.mlir new file mode 100644 index 0000000..69a7aee --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_29.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg3, %0, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.srem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%5, %arg0) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_3.mlir b/benchmarks/MLIR_bb0_veir/8_function_3.mlir new file mode 100644 index 0000000..e175a3d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_3.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.ashr"(%1, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.urem"(%arg0, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_30.mlir b/benchmarks/MLIR_bb0_veir/8_function_30.mlir new file mode 100644 index 0000000..92dd0d5 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_30.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg1) : (i32) -> i64 + %2 = "llvm.and"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.and"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_31.mlir b/benchmarks/MLIR_bb0_veir/8_function_31.mlir new file mode 100644 index 0000000..c47e97b --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_31.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.lshr"(%1, %arg2) : (i64, i64) -> i64 + %5 = "llvm.icmp"(%3, %4) <{predicate = 6 : i64}> : (i64, i64) -> i1 + %6 = "llvm.srem"(%3, %0) : (i64, i64) -> i64 + %7 = "llvm.select"(%5, %arg2, %6) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_32.mlir b/benchmarks/MLIR_bb0_veir/8_function_32.mlir new file mode 100644 index 0000000..8f5b0f2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_32.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i1, %arg2: i64): + %0 = "llvm.select"(%arg1, %arg2, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %0) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.lshr"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.select"(%arg0, %5, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_33.mlir b/benchmarks/MLIR_bb0_veir/8_function_33.mlir new file mode 100644 index 0000000..8152923 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_33.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.select"(%3, %2, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.and"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_34.mlir b/benchmarks/MLIR_bb0_veir/8_function_34.mlir new file mode 100644 index 0000000..4f255e0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_34.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg2, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.or"(%0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.or"(%0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%4, %2) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.srem"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_35.mlir b/benchmarks/MLIR_bb0_veir/8_function_35.mlir new file mode 100644 index 0000000..4fa9720 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_35.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_36.mlir b/benchmarks/MLIR_bb0_veir/8_function_36.mlir new file mode 100644 index 0000000..8e56cc6 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_36.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.urem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg3) : (i32) -> i64 + %2 = "llvm.urem"(%1, %1) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %0) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%arg1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.select"(%arg0, %0, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_37.mlir b/benchmarks/MLIR_bb0_veir/8_function_37.mlir new file mode 100644 index 0000000..dc6b684 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_37.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%5, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_38.mlir b/benchmarks/MLIR_bb0_veir/8_function_38.mlir new file mode 100644 index 0000000..56e6c6a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_38.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %1 = "llvm.or"(%arg0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.zext"(%arg3) : (i32) -> i64 + %7 = "llvm.select"(%0, %5, %6) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_39.mlir b/benchmarks/MLIR_bb0_veir/8_function_39.mlir new file mode 100644 index 0000000..d24ccee --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_39.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.ashr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.select"(%arg1, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.and"(%2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %2) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %4) : (i64, i64) -> i64 + %6 = "llvm.or"(%1, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_4.mlir b/benchmarks/MLIR_bb0_veir/8_function_4.mlir new file mode 100644 index 0000000..8b17888 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_4.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.select"(%arg3, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.ashr"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.or"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%arg2, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%5, %6) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_40.mlir b/benchmarks/MLIR_bb0_veir/8_function_40.mlir new file mode 100644 index 0000000..6a58775 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_40.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.icmp"(%1, %1) <{predicate = 9 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.or"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%arg2, %arg2) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.or"(%arg1, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.ashr"(%4, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_41.mlir b/benchmarks/MLIR_bb0_veir/8_function_41.mlir new file mode 100644 index 0000000..9ad2e59 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_41.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 5 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.ashr"(%arg2, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.and"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.xor"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%1, %4) : (i64, i64) -> i64 + %6 = "llvm.select"(%0, %3, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_42.mlir b/benchmarks/MLIR_bb0_veir/8_function_42.mlir new file mode 100644 index 0000000..d525e69 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_42.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.lshr"(%0, %arg2) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.srem"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%5, %2) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.select"(%1, %arg2, %6) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_43.mlir b/benchmarks/MLIR_bb0_veir/8_function_43.mlir new file mode 100644 index 0000000..7d2597f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_43.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i32, %arg1: i1, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.select"(%arg1, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.urem"(%0, %arg2) : (i64, i64) -> i64 + %6 = "llvm.udiv"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_44.mlir b/benchmarks/MLIR_bb0_veir/8_function_44.mlir new file mode 100644 index 0000000..356113c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_44.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.urem"(%0, %0) : (i64, i64) -> i64 + %4 = "llvm.and"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%arg1, %arg0) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.or"(%4, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 5 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_45.mlir b/benchmarks/MLIR_bb0_veir/8_function_45.mlir new file mode 100644 index 0000000..39f700a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_45.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i32, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg1) : (i32) -> i64 + %4 = "llvm.ashr"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%arg2, %arg2) : (i64, i64) -> i64 + %6 = "llvm.srem"(%5, %2) : (i64, i64) -> i64 + %7 = "llvm.lshr"(%4, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_46.mlir b/benchmarks/MLIR_bb0_veir/8_function_46.mlir new file mode 100644 index 0000000..a3bf0cf --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_46.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg1) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.udiv"(%arg0, %arg2) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %arg0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_47.mlir b/benchmarks/MLIR_bb0_veir/8_function_47.mlir new file mode 100644 index 0000000..0342447 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_47.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.srem"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %2, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.xor"(%arg1, %arg1) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %arg2) : (i64, i64) -> i64 + %6 = "llvm.srem"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_48.mlir b/benchmarks/MLIR_bb0_veir/8_function_48.mlir new file mode 100644 index 0000000..b43917a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_48.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.sdiv"(%arg0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.udiv"(%arg0, %arg2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg1, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.urem"(%1, %arg1) : (i64, i64) -> i64 + %6 = "llvm.xor"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.srem"(%2, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_49.mlir b/benchmarks/MLIR_bb0_veir/8_function_49.mlir new file mode 100644 index 0000000..9e7361d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_49.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1, %arg3: i32): + %0 = "llvm.select"(%arg2, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %1 = "llvm.sext"(%arg3) : (i32) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg2, %3, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.and"(%arg0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_5.mlir b/benchmarks/MLIR_bb0_veir/8_function_5.mlir new file mode 100644 index 0000000..a6d5078 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_5.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg1, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg1, %arg2) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.srem"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%arg0, %6) <{predicate = 1 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_50.mlir b/benchmarks/MLIR_bb0_veir/8_function_50.mlir new file mode 100644 index 0000000..edc90db --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_50.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.ashr"(%arg0, %arg0) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%0, %2) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %3) : (i64, i64) -> i64 + %5 = "llvm.select"(%arg3, %4, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.lshr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_51.mlir b/benchmarks/MLIR_bb0_veir/8_function_51.mlir new file mode 100644 index 0000000..347281c --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_51.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) <{isDisjoint}> : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.zext"(%arg3) : (i32) -> i64 + %5 = "llvm.lshr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.sdiv"(%2, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_52.mlir b/benchmarks/MLIR_bb0_veir/8_function_52.mlir new file mode 100644 index 0000000..9a5703d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_52.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.urem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %3) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_53.mlir b/benchmarks/MLIR_bb0_veir/8_function_53.mlir new file mode 100644 index 0000000..bac0b0a --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_53.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %2 = "llvm.select"(%0, %1, %1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.lshr"(%2, %arg1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_54.mlir b/benchmarks/MLIR_bb0_veir/8_function_54.mlir new file mode 100644 index 0000000..1adf9ae --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_54.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.lshr"(%arg1, %1) : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg2) : (i32) -> i64 + %4 = "llvm.urem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_55.mlir b/benchmarks/MLIR_bb0_veir/8_function_55.mlir new file mode 100644 index 0000000..a537fa3 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_55.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.or"(%0, %arg2) : (i64, i64) -> i64 + %2 = "llvm.udiv"(%arg2, %0) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg0, %3) : (i64, i64) -> i64 + %5 = "llvm.urem"(%0, %4) : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %7 = "llvm.zext"(%6) : (i32) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_56.mlir b/benchmarks/MLIR_bb0_veir/8_function_56.mlir new file mode 100644 index 0000000..d1f7253 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_56.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.zext"(%1) : (i32) -> i64 + %3 = "llvm.or"(%arg1, %arg0) : (i64, i64) -> i64 + %4 = "llvm.urem"(%arg2, %3) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_57.mlir b/benchmarks/MLIR_bb0_veir/8_function_57.mlir new file mode 100644 index 0000000..2a6d9e4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_57.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.icmp"(%arg1, %arg2) <{predicate = 2 : i64}> : (i64, i64) -> i1 + %3 = "llvm.select"(%2, %0, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.icmp"(%3, %1) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %5 = "llvm.select"(%4, %arg0, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.or"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%1, %6) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_58.mlir b/benchmarks/MLIR_bb0_veir/8_function_58.mlir new file mode 100644 index 0000000..fc6a2a2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_58.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%3, %6) <{predicate = 2 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_59.mlir b/benchmarks/MLIR_bb0_veir/8_function_59.mlir new file mode 100644 index 0000000..56a1aeb --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_59.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.udiv"(%arg2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%3, %arg1) : (i64, i64) -> i64 + %6 = "llvm.srem"(%4, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_6.mlir b/benchmarks/MLIR_bb0_veir/8_function_6.mlir new file mode 100644 index 0000000..ca9dd43 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_6.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.select"(%arg3, %arg2, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.or"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.srem"(%2, %1) : (i64, i64) -> i64 + %4 = "llvm.xor"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%4, %2) : (i64, i64) -> i64 + %6 = "llvm.srem"(%arg1, %5) : (i64, i64) -> i64 + %7 = "llvm.ashr"(%0, %6) <{isExact}> : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_60.mlir b/benchmarks/MLIR_bb0_veir/8_function_60.mlir new file mode 100644 index 0000000..4f93c20 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_60.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.srem"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.sdiv"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_61.mlir b/benchmarks/MLIR_bb0_veir/8_function_61.mlir new file mode 100644 index 0000000..61a8b91 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_61.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.zext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg0, %arg0) : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.xor"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%arg0, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_62.mlir b/benchmarks/MLIR_bb0_veir/8_function_62.mlir new file mode 100644 index 0000000..8288971 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_62.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.ashr"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.and"(%6, %arg2) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_63.mlir b/benchmarks/MLIR_bb0_veir/8_function_63.mlir new file mode 100644 index 0000000..bba968e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_63.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg0) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg2) <{predicate = 7 : i64}> : (i64, i64) -> i1 + %2 = "llvm.lshr"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%0, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.select"(%1, %arg1, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.urem"(%arg0, %4) : (i64, i64) -> i64 + %6 = "llvm.lshr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%5, %6) <{predicate = 7 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_64.mlir b/benchmarks/MLIR_bb0_veir/8_function_64.mlir new file mode 100644 index 0000000..bc2f088 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_64.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.lshr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.or"(%arg1, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.udiv"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%arg2, %arg0) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %arg2) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.urem"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_65.mlir b/benchmarks/MLIR_bb0_veir/8_function_65.mlir new file mode 100644 index 0000000..16c2d13 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_65.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.lshr"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.srem"(%5, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_66.mlir b/benchmarks/MLIR_bb0_veir/8_function_66.mlir new file mode 100644 index 0000000..2e1cbfd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_66.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.sdiv"(%0, %arg2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.srem"(%2, %5) : (i64, i64) -> i64 + %7 = "llvm.and"(%0, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_67.mlir b/benchmarks/MLIR_bb0_veir/8_function_67.mlir new file mode 100644 index 0000000..627ccfc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_67.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg2, %arg0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg2, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%0, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.or"(%0, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%6, %6) <{predicate = 9 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_68.mlir b/benchmarks/MLIR_bb0_veir/8_function_68.mlir new file mode 100644 index 0000000..5225dfc --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_68.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.sdiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.srem"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.sext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_69.mlir b/benchmarks/MLIR_bb0_veir/8_function_69.mlir new file mode 100644 index 0000000..1a4e974 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_69.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.srem"(%0, %0) : (i64, i64) -> i64 + %4 = "llvm.or"(%1, %3) <{isDisjoint}> : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%1, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.sdiv"(%5, %arg2) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.srem"(%2, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_7.mlir b/benchmarks/MLIR_bb0_veir/8_function_7.mlir new file mode 100644 index 0000000..115bdb4 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_7.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.and"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg3, %1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.and"(%arg1, %3) : (i64, i64) -> i64 + %5 = "llvm.and"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%arg2, %5) : (i64, i64) -> i64 + %7 = "llvm.or"(%2, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_70.mlir b/benchmarks/MLIR_bb0_veir/8_function_70.mlir new file mode 100644 index 0000000..a7ef673 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_70.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i1, %arg2: i32): + %0 = "llvm.sext"(%arg2) : (i32) -> i64 + %1 = "llvm.icmp"(%0, %arg0) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%arg1, %arg0, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.select"(%1, %0, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.lshr"(%arg0, %0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.select"(%arg1, %3, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.lshr"(%arg0, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_71.mlir b/benchmarks/MLIR_bb0_veir/8_function_71.mlir new file mode 100644 index 0000000..1c0f07e --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_71.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.or"(%arg0, %arg0) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.select"(%1, %0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %4 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %5 = "llvm.lshr"(%arg0, %2) : (i64, i64) -> i64 + %6 = "llvm.select"(%4, %arg2, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.select"(%3, %2, %6) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_72.mlir b/benchmarks/MLIR_bb0_veir/8_function_72.mlir new file mode 100644 index 0000000..96bf8b9 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_72.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%arg0, %arg0) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.udiv"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_73.mlir b/benchmarks/MLIR_bb0_veir/8_function_73.mlir new file mode 100644 index 0000000..4976c66 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_73.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.udiv"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%3, %3) : (i64, i64) -> i64 + %5 = "llvm.xor"(%4, %3) : (i64, i64) -> i64 + %6 = "llvm.ashr"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_74.mlir b/benchmarks/MLIR_bb0_veir/8_function_74.mlir new file mode 100644 index 0000000..4701c68 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_74.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.and"(%0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %4 = "llvm.or"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.and"(%arg1, %arg2) : (i64, i64) -> i64 + %6 = "llvm.select"(%2, %4, %5) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_75.mlir b/benchmarks/MLIR_bb0_veir/8_function_75.mlir new file mode 100644 index 0000000..b701fa2 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_75.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.xor"(%arg2, %arg2) : (i64, i64) -> i64 + %4 = "llvm.and"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.or"(%4, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_76.mlir b/benchmarks/MLIR_bb0_veir/8_function_76.mlir new file mode 100644 index 0000000..a2cc6be --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_76.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %3 = "llvm.select"(%2, %arg0, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.srem"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_77.mlir b/benchmarks/MLIR_bb0_veir/8_function_77.mlir new file mode 100644 index 0000000..145885f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_77.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg2, %2, %arg0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.sdiv"(%arg1, %arg0) : (i64, i64) -> i64 + %5 = "llvm.srem"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.or"(%arg0, %5) <{isDisjoint}> : (i64, i64) -> i64 + %7 = "llvm.xor"(%2, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_78.mlir b/benchmarks/MLIR_bb0_veir/8_function_78.mlir new file mode 100644 index 0000000..6681508 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_78.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1): + %0 = "llvm.zext"(%arg0) : (i32) -> i64 + %1 = "llvm.or"(%arg1, %arg2) : (i64, i64) -> i64 + %2 = "llvm.select"(%arg3, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %3 = "llvm.select"(%arg3, %arg2, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.sdiv"(%2, %0) <{isExact}> : (i64, i64) -> i64 + %5 = "llvm.lshr"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.urem"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.udiv"(%0, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_79.mlir b/benchmarks/MLIR_bb0_veir/8_function_79.mlir new file mode 100644 index 0000000..dd4e118 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_79.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.select"(%arg2, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.sdiv"(%arg1, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 6 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_8.mlir b/benchmarks/MLIR_bb0_veir/8_function_8.mlir new file mode 100644 index 0000000..4f611fd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_8.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.or"(%arg0, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %1 = "llvm.and"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %4 = "llvm.zext"(%arg3) : (i32) -> i64 + %5 = "llvm.and"(%4, %arg0) : (i64, i64) -> i64 + %6 = "llvm.or"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%2, %6) <{predicate = 0 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_80.mlir b/benchmarks/MLIR_bb0_veir/8_function_80.mlir new file mode 100644 index 0000000..9fa10d8 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_80.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%arg2, %1) : (i64, i64) -> i64 + %3 = "llvm.or"(%arg1, %arg1) <{isDisjoint}> : (i64, i64) -> i64 + %4 = "llvm.srem"(%3, %2) : (i64, i64) -> i64 + %5 = "llvm.lshr"(%2, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.srem"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_81.mlir b/benchmarks/MLIR_bb0_veir/8_function_81.mlir new file mode 100644 index 0000000..d660213 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_81.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %1 = "llvm.select"(%0, %arg0, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.sdiv"(%arg2, %arg1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.ashr"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.and"(%3, %1) : (i64, i64) -> i64 + %5 = "llvm.sdiv"(%4, %arg1) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.sdiv"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.ashr"(%4, %6) <{isExact}> : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_82.mlir b/benchmarks/MLIR_bb0_veir/8_function_82.mlir new file mode 100644 index 0000000..6df5426 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_82.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i1): + %0 = "llvm.urem"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.select"(%arg2, %arg1, %arg1) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %2 = "llvm.icmp"(%0, %1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %3 = "llvm.or"(%arg1, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%2, %3, %0) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_83.mlir b/benchmarks/MLIR_bb0_veir/8_function_83.mlir new file mode 100644 index 0000000..ec632bd --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_83.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.udiv"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %2 = "llvm.urem"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.ashr"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.lshr"(%2, %5) <{isExact}> : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_84.mlir b/benchmarks/MLIR_bb0_veir/8_function_84.mlir new file mode 100644 index 0000000..2a2b381 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_84.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.zext"(%arg1) : (i32) -> i64 + %3 = "llvm.srem"(%arg0, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.and"(%1, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_85.mlir b/benchmarks/MLIR_bb0_veir/8_function_85.mlir new file mode 100644 index 0000000..77bca81 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_85.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i1 + %2 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.zext"(%2) : (i32) -> i64 + %4 = "llvm.urem"(%3, %arg2) : (i64, i64) -> i64 + %5 = "llvm.select"(%1, %4, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.udiv"(%arg2, %3) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%5, %6) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_86.mlir b/benchmarks/MLIR_bb0_veir/8_function_86.mlir new file mode 100644 index 0000000..20e799f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_86.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.zext"(%arg2) : (i32) -> i64 + %2 = "llvm.lshr"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.and"(%arg1, %2) : (i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.xor"(%2, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%6, %6) <{predicate = 3 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_87.mlir b/benchmarks/MLIR_bb0_veir/8_function_87.mlir new file mode 100644 index 0000000..e871fa0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_87.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i32, %arg1: i64, %arg2: i64): + %0 = "llvm.sext"(%arg0) : (i32) -> i64 + %1 = "llvm.urem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.ashr"(%2, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.trunc"(%5) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %7 = "llvm.sext"(%6) : (i32) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_88.mlir b/benchmarks/MLIR_bb0_veir/8_function_88.mlir new file mode 100644 index 0000000..e78fb7f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_88.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.xor"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.xor"(%arg1, %arg2) : (i64, i64) -> i64 + %3 = "llvm.xor"(%0, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%1, %3) : (i64, i64) -> i64 + %5 = "llvm.srem"(%4, %arg1) : (i64, i64) -> i64 + %6 = "llvm.xor"(%arg2, %arg0) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%5, %6) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_89.mlir b/benchmarks/MLIR_bb0_veir/8_function_89.mlir new file mode 100644 index 0000000..de32575 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_89.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.xor"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.and"(%arg1, %arg0) : (i64, i64) -> i64 + %2 = "llvm.sdiv"(%0, %1) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.trunc"(%2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %4 = "llvm.zext"(%3) : (i32) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_9.mlir b/benchmarks/MLIR_bb0_veir/8_function_9.mlir new file mode 100644 index 0000000..0a33455 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_9.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.trunc"(%arg2) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.urem"(%2, %0) : (i64, i64) -> i64 + %4 = "llvm.and"(%0, %arg1) : (i64, i64) -> i64 + %5 = "llvm.udiv"(%3, %4) : (i64, i64) -> i64 + %6 = "llvm.srem"(%5, %4) : (i64, i64) -> i64 + %7 = "llvm.sdiv"(%0, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_90.mlir b/benchmarks/MLIR_bb0_veir/8_function_90.mlir new file mode 100644 index 0000000..6f74bd0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_90.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.and"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.icmp"(%arg0, %2) <{predicate = 0 : i64}> : (i64, i64) -> i1 + %4 = "llvm.select"(%3, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.zext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_91.mlir b/benchmarks/MLIR_bb0_veir/8_function_91.mlir new file mode 100644 index 0000000..2721aa1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_91.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64): + %0 = "llvm.srem"(%arg0, %arg0) : (i64, i64) -> i64 + %1 = "llvm.or"(%arg0, %0) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.xor"(%1, %arg0) : (i64, i64) -> i64 + %3 = "llvm.udiv"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.sdiv"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.icmp"(%6, %1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_92.mlir b/benchmarks/MLIR_bb0_veir/8_function_92.mlir new file mode 100644 index 0000000..d86550f --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_92.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i1, %arg1: i64): + %0 = "llvm.and"(%arg1, %arg1) : (i64, i64) -> i64 + %1 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %1) : (i64, i64) -> i64 + %3 = "llvm.select"(%arg0, %arg1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.sext"(%4) : (i32) -> i64 + %6 = "llvm.and"(%5, %arg1) : (i64, i64) -> i64 + %7 = "llvm.urem"(%5, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_93.mlir b/benchmarks/MLIR_bb0_veir/8_function_93.mlir new file mode 100644 index 0000000..ca1cecf --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_93.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i1, %arg1: i64, %arg2: i64): + %0 = "llvm.srem"(%arg1, %arg2) : (i64, i64) -> i64 + %1 = "llvm.trunc"(%0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %2 = "llvm.sext"(%1) : (i32) -> i64 + %3 = "llvm.udiv"(%2, %arg1) : (i64, i64) -> i64 + %4 = "llvm.select"(%arg0, %2, %3) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.trunc"(%4) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %6 = "llvm.sext"(%5) : (i32) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_94.mlir b/benchmarks/MLIR_bb0_veir/8_function_94.mlir new file mode 100644 index 0000000..9c5a04d --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_94.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32): + %0 = "llvm.sdiv"(%arg0, %arg1) <{isExact}> : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg1) <{predicate = 4 : i64}> : (i64, i64) -> i1 + %2 = "llvm.ashr"(%arg2, %0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.sext"(%arg3) : (i32) -> i64 + %4 = "llvm.srem"(%2, %3) : (i64, i64) -> i64 + %5 = "llvm.select"(%1, %0, %4) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %6 = "llvm.srem"(%arg2, %3) : (i64, i64) -> i64 + %7 = "llvm.ashr"(%5, %6) <{isExact}> : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_95.mlir b/benchmarks/MLIR_bb0_veir/8_function_95.mlir new file mode 100644 index 0000000..e966552 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_95.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.ashr"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.icmp"(%0, %arg2) <{predicate = 9 : i64}> : (i64, i64) -> i1 + %2 = "llvm.urem"(%arg2, %arg1) : (i64, i64) -> i64 + %3 = "llvm.select"(%1, %arg1, %2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %4 = "llvm.udiv"(%arg1, %0) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.udiv"(%3, %5) : (i64, i64) -> i64 + %7 = "llvm.icmp"(%6, %3) <{predicate = 8 : i64}> : (i64, i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_96.mlir b/benchmarks/MLIR_bb0_veir/8_function_96.mlir new file mode 100644 index 0000000..d9bbbc0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_96.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%arg0, %0) : (i64, i64) -> i64 + %2 = "llvm.trunc"(%1) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %3 = "llvm.sext"(%2) : (i32) -> i64 + %4 = "llvm.trunc"(%3) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %5 = "llvm.zext"(%4) : (i32) -> i64 + %6 = "llvm.urem"(%arg2, %arg2) : (i64, i64) -> i64 + %7 = "llvm.udiv"(%5, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_97.mlir b/benchmarks/MLIR_bb0_veir/8_function_97.mlir new file mode 100644 index 0000000..2fc0fa0 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_97.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i64}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i32): + %0 = "llvm.trunc"(%arg0) <{overflowFlags = 0 : i32}> : (i64) -> i32 + %1 = "llvm.sext"(%0) : (i32) -> i64 + %2 = "llvm.xor"(%1, %arg1) : (i64, i64) -> i64 + %3 = "llvm.zext"(%arg2) : (i32) -> i64 + %4 = "llvm.urem"(%3, %arg1) : (i64, i64) -> i64 + %5 = "llvm.or"(%2, %4) : (i64, i64) -> i64 + %6 = "llvm.sext"(%arg2) : (i32) -> i64 + %7 = "llvm.udiv"(%5, %6) : (i64, i64) -> i64 + "func.return"(%7) : (i64) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_98.mlir b/benchmarks/MLIR_bb0_veir/8_function_98.mlir new file mode 100644 index 0000000..3944521 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_98.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i32}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.udiv"(%arg0, %arg1) : (i64, i64) -> i64 + %1 = "llvm.srem"(%0, %arg1) : (i64, i64) -> i64 + %2 = "llvm.or"(%0, %0) : (i64, i64) -> i64 + %3 = "llvm.xor"(%1, %2) : (i64, i64) -> i64 + %4 = "llvm.udiv"(%arg1, %arg2) : (i64, i64) -> i64 + %5 = "llvm.ashr"(%3, %4) <{isExact}> : (i64, i64) -> i64 + %6 = "llvm.udiv"(%0, %5) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i32 + "func.return"(%7) : (i32) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_bb0_veir/8_function_99.mlir b/benchmarks/MLIR_bb0_veir/8_function_99.mlir new file mode 100644 index 0000000..14c7fa1 --- /dev/null +++ b/benchmarks/MLIR_bb0_veir/8_function_99.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + "func.func"() <{sym_name = "func0", function_type = () -> i1}> ({ + ^bb0(%arg0: i64, %arg1: i64, %arg2: i64): + %0 = "llvm.icmp"(%arg0, %arg0) <{predicate = 8 : i64}> : (i64, i64) -> i1 + %1 = "llvm.or"(%arg1, %arg2) <{isDisjoint}> : (i64, i64) -> i64 + %2 = "llvm.lshr"(%1, %arg0) <{isExact}> : (i64, i64) -> i64 + %3 = "llvm.sdiv"(%1, %2) <{isExact}> : (i64, i64) -> i64 + %4 = "llvm.select"(%0, %3, %arg2) <{fastmathFlags = #llvm.fastmath}> : (i1, i64, i64) -> i64 + %5 = "llvm.xor"(%4, %arg0) : (i64, i64) -> i64 + %6 = "llvm.urem"(%5, %3) : (i64, i64) -> i64 + %7 = "llvm.trunc"(%6) <{overflowFlags = 0 : i32}> : (i64) -> i1 + "func.return"(%7) : (i1) -> () + }): () -> () +}) : () -> () diff --git a/benchmarks/MLIR_single/3_function_0.mlir b/benchmarks/MLIR_single/3_function_0.mlir new file mode 100644 index 0000000..204c17c --- /dev/null +++ b/benchmarks/MLIR_single/3_function_0.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_1.mlir b/benchmarks/MLIR_single/3_function_1.mlir new file mode 100644 index 0000000..810b63a --- /dev/null +++ b/benchmarks/MLIR_single/3_function_1.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i32) -> i1 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.urem %0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_10.mlir b/benchmarks/MLIR_single/3_function_10.mlir new file mode 100644 index 0000000..14cecee --- /dev/null +++ b/benchmarks/MLIR_single/3_function_10.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.srem %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_11.mlir b/benchmarks/MLIR_single/3_function_11.mlir new file mode 100644 index 0000000..83c04f9 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_11.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_12.mlir b/benchmarks/MLIR_single/3_function_12.mlir new file mode 100644 index 0000000..4fa7baf --- /dev/null +++ b/benchmarks/MLIR_single/3_function_12.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.lshr %arg0, %arg0 : i64 + %1 = llvm.udiv %arg1, %arg1 : i64 + %2 = llvm.and %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_13.mlir b/benchmarks/MLIR_single/3_function_13.mlir new file mode 100644 index 0000000..b5dcc3f --- /dev/null +++ b/benchmarks/MLIR_single/3_function_13.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.udiv %arg1, %arg2 : i64 + %1 = llvm.and %arg1, %0 : i64 + %2 = llvm.icmp "sle" %arg0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_14.mlir b/benchmarks/MLIR_single/3_function_14.mlir new file mode 100644 index 0000000..bde0444 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_14.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.xor %0, %arg2 : i64 + %2 = llvm.srem %1, %arg1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_15.mlir b/benchmarks/MLIR_single/3_function_15.mlir new file mode 100644 index 0000000..94e319f --- /dev/null +++ b/benchmarks/MLIR_single/3_function_15.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.or disjoint %arg0, %0 : i64 + %2 = llvm.icmp "ult" %1, %arg1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_16.mlir b/benchmarks/MLIR_single/3_function_16.mlir new file mode 100644 index 0000000..6f4bc6d --- /dev/null +++ b/benchmarks/MLIR_single/3_function_16.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.sdiv %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_17.mlir b/benchmarks/MLIR_single/3_function_17.mlir new file mode 100644 index 0000000..12b8109 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_17.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.and %0, %arg1 : i64 + %2 = llvm.and %1, %arg2 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_18.mlir b/benchmarks/MLIR_single/3_function_18.mlir new file mode 100644 index 0000000..455f3ff --- /dev/null +++ b/benchmarks/MLIR_single/3_function_18.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.lshr %arg1, %arg0 : i64 + %1 = llvm.sdiv exact %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_19.mlir b/benchmarks/MLIR_single/3_function_19.mlir new file mode 100644 index 0000000..a3efd66 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_19.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_2.mlir b/benchmarks/MLIR_single/3_function_2.mlir new file mode 100644 index 0000000..54bb98e --- /dev/null +++ b/benchmarks/MLIR_single/3_function_2.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.lshr exact %arg1, %arg1 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_20.mlir b/benchmarks/MLIR_single/3_function_20.mlir new file mode 100644 index 0000000..a579dbf --- /dev/null +++ b/benchmarks/MLIR_single/3_function_20.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.lshr exact %arg1, %arg0 : i64 + %1 = llvm.lshr exact %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_21.mlir b/benchmarks/MLIR_single/3_function_21.mlir new file mode 100644 index 0000000..d3802ed --- /dev/null +++ b/benchmarks/MLIR_single/3_function_21.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.icmp "eq" %arg0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_22.mlir b/benchmarks/MLIR_single/3_function_22.mlir new file mode 100644 index 0000000..85c59a6 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_22.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.ashr %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_23.mlir b/benchmarks/MLIR_single/3_function_23.mlir new file mode 100644 index 0000000..89386f8 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_23.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.or %arg1, %arg2 : i64 + %1 = llvm.select %arg0, %0, %arg1 : i1, i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_24.mlir b/benchmarks/MLIR_single/3_function_24.mlir new file mode 100644 index 0000000..4c68c08 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_24.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.select %arg0, %arg1, %1 : i1, i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_25.mlir b/benchmarks/MLIR_single/3_function_25.mlir new file mode 100644 index 0000000..8b89d06 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_25.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_26.mlir b/benchmarks/MLIR_single/3_function_26.mlir new file mode 100644 index 0000000..1e1e8a0 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_26.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.and %0, %arg0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_27.mlir b/benchmarks/MLIR_single/3_function_27.mlir new file mode 100644 index 0000000..1ae7c5d --- /dev/null +++ b/benchmarks/MLIR_single/3_function_27.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.or disjoint %arg0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_28.mlir b/benchmarks/MLIR_single/3_function_28.mlir new file mode 100644 index 0000000..3263692 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_28.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or disjoint %arg2, %arg1 : i64 + %1 = llvm.select %arg0, %arg1, %0 : i1, i64 + %2 = llvm.icmp "eq" %1, %arg2 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_29.mlir b/benchmarks/MLIR_single/3_function_29.mlir new file mode 100644 index 0000000..4875d6e --- /dev/null +++ b/benchmarks/MLIR_single/3_function_29.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.icmp "sge" %1, %arg0 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_3.mlir b/benchmarks/MLIR_single/3_function_3.mlir new file mode 100644 index 0000000..225199e --- /dev/null +++ b/benchmarks/MLIR_single/3_function_3.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.xor %0, %arg2 : i64 + %2 = llvm.icmp "sle" %0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_30.mlir b/benchmarks/MLIR_single/3_function_30.mlir new file mode 100644 index 0000000..cd4aaa4 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_30.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.or %arg0, %0 : i64 + %2 = llvm.icmp "sle" %arg0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_31.mlir b/benchmarks/MLIR_single/3_function_31.mlir new file mode 100644 index 0000000..c12b650 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_31.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.ashr exact %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_32.mlir b/benchmarks/MLIR_single/3_function_32.mlir new file mode 100644 index 0000000..e5fb862 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_32.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr %arg0, %arg1 : i64 + %1 = llvm.sdiv exact %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_33.mlir b/benchmarks/MLIR_single/3_function_33.mlir new file mode 100644 index 0000000..5010dbe --- /dev/null +++ b/benchmarks/MLIR_single/3_function_33.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_34.mlir b/benchmarks/MLIR_single/3_function_34.mlir new file mode 100644 index 0000000..3fd72b3 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_34.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.ashr %arg0, %arg0 : i64 + %1 = llvm.sdiv %0, %0 : i64 + %2 = llvm.xor %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_35.mlir b/benchmarks/MLIR_single/3_function_35.mlir new file mode 100644 index 0000000..9c57cde --- /dev/null +++ b/benchmarks/MLIR_single/3_function_35.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv exact %arg0, %arg1 : i64 + %1 = llvm.xor %0, %arg2 : i64 + %2 = llvm.icmp "ult" %arg0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_36.mlir b/benchmarks/MLIR_single/3_function_36.mlir new file mode 100644 index 0000000..8b89d06 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_36.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_37.mlir b/benchmarks/MLIR_single/3_function_37.mlir new file mode 100644 index 0000000..3b3505f --- /dev/null +++ b/benchmarks/MLIR_single/3_function_37.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_38.mlir b/benchmarks/MLIR_single/3_function_38.mlir new file mode 100644 index 0000000..b9a135a --- /dev/null +++ b/benchmarks/MLIR_single/3_function_38.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.icmp "sle" %1, %arg0 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_39.mlir b/benchmarks/MLIR_single/3_function_39.mlir new file mode 100644 index 0000000..6fa3b2a --- /dev/null +++ b/benchmarks/MLIR_single/3_function_39.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg1, %arg2 : i64 + %1 = llvm.select %arg0, %arg1, %0 : i1, i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_4.mlir b/benchmarks/MLIR_single/3_function_4.mlir new file mode 100644 index 0000000..d6902a4 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_4.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.xor %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_40.mlir b/benchmarks/MLIR_single/3_function_40.mlir new file mode 100644 index 0000000..da2c8d2 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_40.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.or %arg1, %arg0 : i64 + %2 = llvm.srem %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_41.mlir b/benchmarks/MLIR_single/3_function_41.mlir new file mode 100644 index 0000000..a3efd66 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_41.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_42.mlir b/benchmarks/MLIR_single/3_function_42.mlir new file mode 100644 index 0000000..11be7bd --- /dev/null +++ b/benchmarks/MLIR_single/3_function_42.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_43.mlir b/benchmarks/MLIR_single/3_function_43.mlir new file mode 100644 index 0000000..03191fe --- /dev/null +++ b/benchmarks/MLIR_single/3_function_43.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sdiv %arg1, %arg2 : i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.and %1, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_44.mlir b/benchmarks/MLIR_single/3_function_44.mlir new file mode 100644 index 0000000..e7ace8a --- /dev/null +++ b/benchmarks/MLIR_single/3_function_44.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.ashr exact %arg1, %0 : i64 + %2 = llvm.lshr %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_45.mlir b/benchmarks/MLIR_single/3_function_45.mlir new file mode 100644 index 0000000..976adf1 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_45.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.ashr %arg0, %arg0 : i64 + %1 = llvm.srem %0, %arg0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_46.mlir b/benchmarks/MLIR_single/3_function_46.mlir new file mode 100644 index 0000000..f995b99 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_46.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.sdiv %arg2, %0 : i64 + %2 = llvm.icmp "eq" %0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_47.mlir b/benchmarks/MLIR_single/3_function_47.mlir new file mode 100644 index 0000000..38b8442 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_47.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.sdiv exact %arg2, %arg2 : i64 + %2 = llvm.urem %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_48.mlir b/benchmarks/MLIR_single/3_function_48.mlir new file mode 100644 index 0000000..5010dbe --- /dev/null +++ b/benchmarks/MLIR_single/3_function_48.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_49.mlir b/benchmarks/MLIR_single/3_function_49.mlir new file mode 100644 index 0000000..5de545f --- /dev/null +++ b/benchmarks/MLIR_single/3_function_49.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.xor %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_5.mlir b/benchmarks/MLIR_single/3_function_5.mlir new file mode 100644 index 0000000..bdf1391 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_5.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv %arg1, %arg2 : i64 + %1 = llvm.ashr exact %arg0, %0 : i64 + %2 = llvm.icmp "ne" %1, %arg1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_50.mlir b/benchmarks/MLIR_single/3_function_50.mlir new file mode 100644 index 0000000..b08e255 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_50.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.or %0, %arg0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_51.mlir b/benchmarks/MLIR_single/3_function_51.mlir new file mode 100644 index 0000000..9bd31ff --- /dev/null +++ b/benchmarks/MLIR_single/3_function_51.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_52.mlir b/benchmarks/MLIR_single/3_function_52.mlir new file mode 100644 index 0000000..5010dbe --- /dev/null +++ b/benchmarks/MLIR_single/3_function_52.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_53.mlir b/benchmarks/MLIR_single/3_function_53.mlir new file mode 100644 index 0000000..ae10a28 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_53.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.sdiv %1, %arg1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_54.mlir b/benchmarks/MLIR_single/3_function_54.mlir new file mode 100644 index 0000000..c3bcaeb --- /dev/null +++ b/benchmarks/MLIR_single/3_function_54.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.icmp "sge" %arg0, %arg0 : i64 + %1 = llvm.select %0, %arg0, %arg0 : i1, i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_55.mlir b/benchmarks/MLIR_single/3_function_55.mlir new file mode 100644 index 0000000..a677fb3 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_55.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.urem %arg1, %arg0 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_56.mlir b/benchmarks/MLIR_single/3_function_56.mlir new file mode 100644 index 0000000..8b89d06 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_56.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_57.mlir b/benchmarks/MLIR_single/3_function_57.mlir new file mode 100644 index 0000000..a3e4e77 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_57.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.trunc %arg1 : i64 to i1 + %1 = llvm.select %0, %arg2, %arg2 : i1, i64 + %2 = llvm.icmp "ule" %arg0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_58.mlir b/benchmarks/MLIR_single/3_function_58.mlir new file mode 100644 index 0000000..63896c1 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_58.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.icmp "ule" %1, %arg1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_59.mlir b/benchmarks/MLIR_single/3_function_59.mlir new file mode 100644 index 0000000..bdbdbb1 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_59.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.xor %arg1, %arg0 : i64 + %1 = llvm.ashr %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_6.mlir b/benchmarks/MLIR_single/3_function_6.mlir new file mode 100644 index 0000000..9bd31ff --- /dev/null +++ b/benchmarks/MLIR_single/3_function_6.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_60.mlir b/benchmarks/MLIR_single/3_function_60.mlir new file mode 100644 index 0000000..d8b5167 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_60.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.sdiv exact %arg1, %arg0 : i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_61.mlir b/benchmarks/MLIR_single/3_function_61.mlir new file mode 100644 index 0000000..6f8f4b8 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_61.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.sdiv exact %arg0, %0 : i64 + %2 = llvm.sdiv exact %1, %arg1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_62.mlir b/benchmarks/MLIR_single/3_function_62.mlir new file mode 100644 index 0000000..7ab8bf1 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_62.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.lshr %0, %arg1 : i64 + %2 = llvm.urem %1, %0 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_63.mlir b/benchmarks/MLIR_single/3_function_63.mlir new file mode 100644 index 0000000..8b89d06 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_63.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_64.mlir b/benchmarks/MLIR_single/3_function_64.mlir new file mode 100644 index 0000000..df173bf --- /dev/null +++ b/benchmarks/MLIR_single/3_function_64.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.ashr exact %0, %arg1 : i64 + %2 = llvm.lshr exact %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_65.mlir b/benchmarks/MLIR_single/3_function_65.mlir new file mode 100644 index 0000000..cd1eea4 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_65.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.ashr exact %arg0, %arg1 : i64 + %1 = llvm.urem %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_66.mlir b/benchmarks/MLIR_single/3_function_66.mlir new file mode 100644 index 0000000..3552736 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_66.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.lshr exact %arg0, %arg1 : i64 + %1 = llvm.zext %arg2 : i32 to i64 + %2 = llvm.ashr %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_67.mlir b/benchmarks/MLIR_single/3_function_67.mlir new file mode 100644 index 0000000..13851ab --- /dev/null +++ b/benchmarks/MLIR_single/3_function_67.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.ashr %arg0, %arg0 : i64 + %1 = llvm.or disjoint %arg1, %0 : i64 + %2 = llvm.udiv %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_68.mlir b/benchmarks/MLIR_single/3_function_68.mlir new file mode 100644 index 0000000..30c5ace --- /dev/null +++ b/benchmarks/MLIR_single/3_function_68.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.srem %arg1, %arg2 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_69.mlir b/benchmarks/MLIR_single/3_function_69.mlir new file mode 100644 index 0000000..fbf31dd --- /dev/null +++ b/benchmarks/MLIR_single/3_function_69.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.xor %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_7.mlir b/benchmarks/MLIR_single/3_function_7.mlir new file mode 100644 index 0000000..cd6c6b3 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_7.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.lshr %arg2, %arg2 : i64 + %1 = llvm.lshr exact %arg1, %0 : i64 + %2 = llvm.lshr %arg0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_70.mlir b/benchmarks/MLIR_single/3_function_70.mlir new file mode 100644 index 0000000..6300db7 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_70.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.ashr %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_71.mlir b/benchmarks/MLIR_single/3_function_71.mlir new file mode 100644 index 0000000..99ca965 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_71.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i32) -> i32 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.srem %0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_72.mlir b/benchmarks/MLIR_single/3_function_72.mlir new file mode 100644 index 0000000..4c9a642 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_72.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i1 { + %0 = llvm.zext %arg1 : i32 to i64 + %1 = llvm.xor %0, %0 : i64 + %2 = llvm.icmp "sle" %arg0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_73.mlir b/benchmarks/MLIR_single/3_function_73.mlir new file mode 100644 index 0000000..08d9a14 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_73.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_74.mlir b/benchmarks/MLIR_single/3_function_74.mlir new file mode 100644 index 0000000..9ad2166 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_74.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.ashr exact %arg1, %arg1 : i64 + %1 = llvm.ashr %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_75.mlir b/benchmarks/MLIR_single/3_function_75.mlir new file mode 100644 index 0000000..2cb62ee --- /dev/null +++ b/benchmarks/MLIR_single/3_function_75.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.sdiv exact %arg0, %arg0 : i64 + %1 = llvm.ashr %0, %arg1 : i64 + %2 = llvm.srem %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_76.mlir b/benchmarks/MLIR_single/3_function_76.mlir new file mode 100644 index 0000000..589d7f2 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_76.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i1 { + %0 = llvm.zext %arg1 : i32 to i64 + %1 = llvm.or %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_77.mlir b/benchmarks/MLIR_single/3_function_77.mlir new file mode 100644 index 0000000..57e0360 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_77.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.lshr %arg0, %arg0 : i64 + %2 = llvm.icmp "ule" %0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_78.mlir b/benchmarks/MLIR_single/3_function_78.mlir new file mode 100644 index 0000000..a5c60b8 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_78.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i32, %arg1: i64) -> i1 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.and %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_79.mlir b/benchmarks/MLIR_single/3_function_79.mlir new file mode 100644 index 0000000..9740672 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_79.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i32, %arg1: i64) -> i1 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.urem %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_8.mlir b/benchmarks/MLIR_single/3_function_8.mlir new file mode 100644 index 0000000..e6a7486 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_8.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.xor %arg1, %arg2 : i64 + %2 = llvm.icmp "sge" %0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_80.mlir b/benchmarks/MLIR_single/3_function_80.mlir new file mode 100644 index 0000000..8391506 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_80.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i32, %arg1: i64) -> i1 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.sdiv %0, %0 : i64 + %2 = llvm.icmp "sge" %1, %arg1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_81.mlir b/benchmarks/MLIR_single/3_function_81.mlir new file mode 100644 index 0000000..f18a7cf --- /dev/null +++ b/benchmarks/MLIR_single/3_function_81.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.icmp "sge" %arg0, %arg1 : i64 + %1 = llvm.select %0, %arg2, %arg0 : i1, i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_82.mlir b/benchmarks/MLIR_single/3_function_82.mlir new file mode 100644 index 0000000..85d2a8d --- /dev/null +++ b/benchmarks/MLIR_single/3_function_82.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg1, %arg2 : i64 + %1 = llvm.lshr %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_83.mlir b/benchmarks/MLIR_single/3_function_83.mlir new file mode 100644 index 0000000..894d2b1 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_83.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.icmp "ule" %arg0, %arg1 : i64 + %1 = llvm.select %0, %arg1, %arg2 : i1, i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_84.mlir b/benchmarks/MLIR_single/3_function_84.mlir new file mode 100644 index 0000000..654bf6c --- /dev/null +++ b/benchmarks/MLIR_single/3_function_84.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.srem %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_85.mlir b/benchmarks/MLIR_single/3_function_85.mlir new file mode 100644 index 0000000..57ca4cd --- /dev/null +++ b/benchmarks/MLIR_single/3_function_85.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.or %arg0, %0 : i64 + %2 = llvm.sdiv exact %arg0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_86.mlir b/benchmarks/MLIR_single/3_function_86.mlir new file mode 100644 index 0000000..ee8f1d8 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_86.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i32, %arg2: i64) -> i32 { + %0 = llvm.zext %arg1 : i32 to i64 + %1 = llvm.select %arg0, %0, %arg2 : i1, i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_87.mlir b/benchmarks/MLIR_single/3_function_87.mlir new file mode 100644 index 0000000..0bd5dc5 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_87.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.icmp "ugt" %arg0, %arg1 : i64 + %1 = llvm.select %0, %arg0, %arg2 : i1, i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_88.mlir b/benchmarks/MLIR_single/3_function_88.mlir new file mode 100644 index 0000000..15356a7 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_88.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i32) -> i32 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.udiv %0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_89.mlir b/benchmarks/MLIR_single/3_function_89.mlir new file mode 100644 index 0000000..d973af7 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_89.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_9.mlir b/benchmarks/MLIR_single/3_function_9.mlir new file mode 100644 index 0000000..225bfb2 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_9.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.icmp "ne" %arg0, %arg0 : i64 + %1 = llvm.select %0, %arg0, %arg0 : i1, i64 + %2 = llvm.icmp "sle" %1, %arg0 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_90.mlir b/benchmarks/MLIR_single/3_function_90.mlir new file mode 100644 index 0000000..ec95867 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_90.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.srem %arg1, %arg1 : i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_91.mlir b/benchmarks/MLIR_single/3_function_91.mlir new file mode 100644 index 0000000..a73bb41 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_91.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.udiv %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_92.mlir b/benchmarks/MLIR_single/3_function_92.mlir new file mode 100644 index 0000000..0c39bba --- /dev/null +++ b/benchmarks/MLIR_single/3_function_92.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.ashr exact %0, %arg0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_93.mlir b/benchmarks/MLIR_single/3_function_93.mlir new file mode 100644 index 0000000..ce0fb05 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_93.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.icmp "ule" %arg0, %arg1 : i64 + %1 = llvm.select %0, %arg2, %arg0 : i1, i64 + %2 = llvm.icmp "sge" %arg0, %1 : i64 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_94.mlir b/benchmarks/MLIR_single/3_function_94.mlir new file mode 100644 index 0000000..43a2692 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_94.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i32 { + %0 = llvm.zext %arg1 : i32 to i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/3_function_95.mlir b/benchmarks/MLIR_single/3_function_95.mlir new file mode 100644 index 0000000..485666f --- /dev/null +++ b/benchmarks/MLIR_single/3_function_95.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.and %arg1, %arg0 : i64 + %1 = llvm.sdiv %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_96.mlir b/benchmarks/MLIR_single/3_function_96.mlir new file mode 100644 index 0000000..d14f790 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_96.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.sext %arg2 : i32 to i64 + %2 = llvm.udiv %0, %1 : i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_97.mlir b/benchmarks/MLIR_single/3_function_97.mlir new file mode 100644 index 0000000..961ffa4 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_97.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i1 + %1 = llvm.or %arg1, %arg0 : i64 + %2 = llvm.select %0, %arg0, %1 : i1, i64 + return %2 : i64 +} + diff --git a/benchmarks/MLIR_single/3_function_98.mlir b/benchmarks/MLIR_single/3_function_98.mlir new file mode 100644 index 0000000..9bd31ff --- /dev/null +++ b/benchmarks/MLIR_single/3_function_98.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i1 + return %2 : i1 +} + diff --git a/benchmarks/MLIR_single/3_function_99.mlir b/benchmarks/MLIR_single/3_function_99.mlir new file mode 100644 index 0000000..853f8a9 --- /dev/null +++ b/benchmarks/MLIR_single/3_function_99.mlir @@ -0,0 +1,7 @@ +func.func @main(%arg0: i1, %arg1: i64) -> i32 { + %0 = llvm.sdiv %arg1, %arg1 : i64 + %1 = llvm.select %arg0, %0, %0 : i1, i64 + %2 = llvm.trunc %1 : i64 to i32 + return %2 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_0.mlir b/benchmarks/MLIR_single/4_function_0.mlir new file mode 100644 index 0000000..95ac0df --- /dev/null +++ b/benchmarks/MLIR_single/4_function_0.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.lshr exact %1, %arg2 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_1.mlir b/benchmarks/MLIR_single/4_function_1.mlir new file mode 100644 index 0000000..36b2d5f --- /dev/null +++ b/benchmarks/MLIR_single/4_function_1.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_10.mlir b/benchmarks/MLIR_single/4_function_10.mlir new file mode 100644 index 0000000..dc164ef --- /dev/null +++ b/benchmarks/MLIR_single/4_function_10.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.sdiv exact %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_11.mlir b/benchmarks/MLIR_single/4_function_11.mlir new file mode 100644 index 0000000..ea7543e --- /dev/null +++ b/benchmarks/MLIR_single/4_function_11.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.sdiv exact %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_12.mlir b/benchmarks/MLIR_single/4_function_12.mlir new file mode 100644 index 0000000..c35e549 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_12.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.and %arg0, %arg0 : i64 + %3 = llvm.icmp "ule" %1, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_13.mlir b/benchmarks/MLIR_single/4_function_13.mlir new file mode 100644 index 0000000..1699777 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_13.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.sdiv exact %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.icmp "ugt" %arg0, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_14.mlir b/benchmarks/MLIR_single/4_function_14.mlir new file mode 100644 index 0000000..f488f2f --- /dev/null +++ b/benchmarks/MLIR_single/4_function_14.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.urem %arg0, %0 : i64 + %2 = llvm.udiv %arg2, %1 : i64 + %3 = llvm.urem %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_15.mlir b/benchmarks/MLIR_single/4_function_15.mlir new file mode 100644 index 0000000..8495d6f --- /dev/null +++ b/benchmarks/MLIR_single/4_function_15.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.urem %0, %arg2 : i64 + %2 = llvm.lshr exact %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_16.mlir b/benchmarks/MLIR_single/4_function_16.mlir new file mode 100644 index 0000000..9a21cb4 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_16.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr %arg1, %arg2 : i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.srem %1, %arg0 : i64 + %3 = llvm.icmp "ule" %1, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_17.mlir b/benchmarks/MLIR_single/4_function_17.mlir new file mode 100644 index 0000000..ed1cd50 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_17.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.sext %arg2 : i32 to i64 + %1 = llvm.udiv %0, %arg1 : i64 + %2 = llvm.select %arg0, %arg1, %1 : i1, i64 + %3 = llvm.srem %2, %arg1 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_18.mlir b/benchmarks/MLIR_single/4_function_18.mlir new file mode 100644 index 0000000..6672a35 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_18.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg1, %arg1 : i64 + %1 = llvm.xor %arg2, %arg1 : i64 + %2 = llvm.or disjoint %0, %1 : i64 + %3 = llvm.urem %arg0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_19.mlir b/benchmarks/MLIR_single/4_function_19.mlir new file mode 100644 index 0000000..5850de3 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_19.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_2.mlir b/benchmarks/MLIR_single/4_function_2.mlir new file mode 100644 index 0000000..d7365df --- /dev/null +++ b/benchmarks/MLIR_single/4_function_2.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.ashr %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_20.mlir b/benchmarks/MLIR_single/4_function_20.mlir new file mode 100644 index 0000000..ecf2565 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_20.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64, %arg3: i32) -> i64 { + %0 = llvm.xor %arg2, %arg2 : i64 + %1 = llvm.zext %arg3 : i32 to i64 + %2 = llvm.select %arg1, %0, %1 : i1, i64 + %3 = llvm.ashr exact %arg0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_21.mlir b/benchmarks/MLIR_single/4_function_21.mlir new file mode 100644 index 0000000..31638ec --- /dev/null +++ b/benchmarks/MLIR_single/4_function_21.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv exact %arg1, %arg1 : i64 + %1 = llvm.udiv %arg2, %0 : i64 + %2 = llvm.ashr exact %arg1, %1 : i64 + %3 = llvm.icmp "sgt" %arg0, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_22.mlir b/benchmarks/MLIR_single/4_function_22.mlir new file mode 100644 index 0000000..324bf31 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_22.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.lshr %0, %0 : i64 + %2 = llvm.urem %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_23.mlir b/benchmarks/MLIR_single/4_function_23.mlir new file mode 100644 index 0000000..451c833 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_23.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i32, %arg1: i32, %arg2: i64) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.zext %arg1 : i32 to i64 + %2 = llvm.or disjoint %1, %arg2 : i64 + %3 = llvm.urem %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_24.mlir b/benchmarks/MLIR_single/4_function_24.mlir new file mode 100644 index 0000000..74d05e4 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_24.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.srem %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i1 + %3 = llvm.select %2, %arg2, %0 : i1, i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_25.mlir b/benchmarks/MLIR_single/4_function_25.mlir new file mode 100644 index 0000000..8209f6a --- /dev/null +++ b/benchmarks/MLIR_single/4_function_25.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.ashr exact %arg0, %arg2 : i64 + %1 = llvm.select %arg1, %0, %arg2 : i1, i64 + %2 = llvm.lshr exact %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_26.mlir b/benchmarks/MLIR_single/4_function_26.mlir new file mode 100644 index 0000000..6a3e47b --- /dev/null +++ b/benchmarks/MLIR_single/4_function_26.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.icmp "eq" %0, %arg2 : i64 + %2 = llvm.select %1, %arg2, %arg1 : i1, i64 + %3 = llvm.xor %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_27.mlir b/benchmarks/MLIR_single/4_function_27.mlir new file mode 100644 index 0000000..cba3abd --- /dev/null +++ b/benchmarks/MLIR_single/4_function_27.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_28.mlir b/benchmarks/MLIR_single/4_function_28.mlir new file mode 100644 index 0000000..5f783f9 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_28.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i32, %arg1: i64) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.srem %arg1, %arg1 : i64 + %2 = llvm.or %0, %1 : i64 + %3 = llvm.sdiv %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_29.mlir b/benchmarks/MLIR_single/4_function_29.mlir new file mode 100644 index 0000000..9fe4d35 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_29.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv exact %arg1, %arg2 : i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.xor %1, %arg0 : i64 + %3 = llvm.icmp "slt" %1, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_3.mlir b/benchmarks/MLIR_single/4_function_3.mlir new file mode 100644 index 0000000..57161e9 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_3.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.trunc %arg2 : i64 to i1 + %2 = llvm.select %1, %0, %arg0 : i1, i64 + %3 = llvm.lshr %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_30.mlir b/benchmarks/MLIR_single/4_function_30.mlir new file mode 100644 index 0000000..1e08970 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_30.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.icmp "ule" %2, %arg2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_31.mlir b/benchmarks/MLIR_single/4_function_31.mlir new file mode 100644 index 0000000..01d05a6 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_31.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.ashr %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_32.mlir b/benchmarks/MLIR_single/4_function_32.mlir new file mode 100644 index 0000000..80a1aa9 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_32.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i32) -> i1 { + %0 = llvm.sext %arg2 : i32 to i64 + %1 = llvm.select %arg1, %0, %arg0 : i1, i64 + %2 = llvm.urem %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_33.mlir b/benchmarks/MLIR_single/4_function_33.mlir new file mode 100644 index 0000000..85585fc --- /dev/null +++ b/benchmarks/MLIR_single/4_function_33.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.icmp "eq" %arg1, %arg2 : i64 + %1 = llvm.select %0, %arg0, %arg0 : i1, i64 + %2 = llvm.xor %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_34.mlir b/benchmarks/MLIR_single/4_function_34.mlir new file mode 100644 index 0000000..a23f639 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_34.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.ashr exact %0, %arg1 : i64 + %2 = llvm.or %0, %1 : i64 + %3 = llvm.lshr %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_35.mlir b/benchmarks/MLIR_single/4_function_35.mlir new file mode 100644 index 0000000..cb30f98 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_35.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_36.mlir b/benchmarks/MLIR_single/4_function_36.mlir new file mode 100644 index 0000000..76e576a --- /dev/null +++ b/benchmarks/MLIR_single/4_function_36.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.urem %arg2, %arg2 : i64 + %2 = llvm.xor %1, %arg0 : i64 + %3 = llvm.urem %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_37.mlir b/benchmarks/MLIR_single/4_function_37.mlir new file mode 100644 index 0000000..ceefe9c --- /dev/null +++ b/benchmarks/MLIR_single/4_function_37.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.srem %arg1, %arg0 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_38.mlir b/benchmarks/MLIR_single/4_function_38.mlir new file mode 100644 index 0000000..44178f6 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_38.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i1 { + %0 = llvm.sext %arg1 : i32 to i64 + %1 = llvm.or disjoint %arg0, %0 : i64 + %2 = llvm.urem %arg0, %1 : i64 + %3 = llvm.icmp "ule" %2, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_39.mlir b/benchmarks/MLIR_single/4_function_39.mlir new file mode 100644 index 0000000..07b4120 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_39.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg2, %arg1 : i64 + %1 = llvm.or disjoint %arg1, %0 : i64 + %2 = llvm.urem %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_4.mlir b/benchmarks/MLIR_single/4_function_4.mlir new file mode 100644 index 0000000..5bc4702 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_4.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i32 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.zext %arg2 : i32 to i64 + %2 = llvm.xor %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_40.mlir b/benchmarks/MLIR_single/4_function_40.mlir new file mode 100644 index 0000000..12d3700 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_40.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.select %arg1, %arg2, %arg0 : i1, i64 + %1 = llvm.udiv %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_41.mlir b/benchmarks/MLIR_single/4_function_41.mlir new file mode 100644 index 0000000..b0bd992 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_41.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.sdiv %arg1, %arg0 : i64 + %1 = llvm.srem %0, %arg2 : i64 + %2 = llvm.srem %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_42.mlir b/benchmarks/MLIR_single/4_function_42.mlir new file mode 100644 index 0000000..5aad75b --- /dev/null +++ b/benchmarks/MLIR_single/4_function_42.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i32, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.srem %0, %arg2 : i64 + %2 = llvm.select %arg1, %1, %1 : i1, i64 + %3 = llvm.and %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_43.mlir b/benchmarks/MLIR_single/4_function_43.mlir new file mode 100644 index 0000000..22f4814 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_43.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i1) -> i32 { + %0 = llvm.select %arg1, %arg0, %arg0 : i1, i64 + %1 = llvm.urem %0, %arg0 : i64 + %2 = llvm.or %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_44.mlir b/benchmarks/MLIR_single/4_function_44.mlir new file mode 100644 index 0000000..a473edc --- /dev/null +++ b/benchmarks/MLIR_single/4_function_44.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i32, %arg1: i32) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.srem %0, %0 : i64 + %2 = llvm.sext %arg1 : i32 to i64 + %3 = llvm.urem %1, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_45.mlir b/benchmarks/MLIR_single/4_function_45.mlir new file mode 100644 index 0000000..fbeb371 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_45.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i1 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.select %arg2, %arg0, %0 : i1, i64 + %2 = llvm.lshr %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_46.mlir b/benchmarks/MLIR_single/4_function_46.mlir new file mode 100644 index 0000000..b7e3a08 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_46.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or %arg0, %arg0 : i64 + %1 = llvm.or disjoint %arg0, %arg1 : i64 + %2 = llvm.xor %1, %arg2 : i64 + %3 = llvm.icmp "ule" %0, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_47.mlir b/benchmarks/MLIR_single/4_function_47.mlir new file mode 100644 index 0000000..3d1612c --- /dev/null +++ b/benchmarks/MLIR_single/4_function_47.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.urem %arg0, %0 : i64 + %2 = llvm.ashr exact %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_48.mlir b/benchmarks/MLIR_single/4_function_48.mlir new file mode 100644 index 0000000..401e17e --- /dev/null +++ b/benchmarks/MLIR_single/4_function_48.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i32) -> i32 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_49.mlir b/benchmarks/MLIR_single/4_function_49.mlir new file mode 100644 index 0000000..a437342 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_49.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.udiv %arg0, %arg2 : i64 + %1 = llvm.lshr exact %arg1, %0 : i64 + %2 = llvm.lshr exact %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_5.mlir b/benchmarks/MLIR_single/4_function_5.mlir new file mode 100644 index 0000000..8389249 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_5.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i32 { + %0 = llvm.ashr %arg0, %arg0 : i64 + %1 = llvm.select %arg1, %arg2, %arg2 : i1, i64 + %2 = llvm.ashr %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_50.mlir b/benchmarks/MLIR_single/4_function_50.mlir new file mode 100644 index 0000000..ea7aaac --- /dev/null +++ b/benchmarks/MLIR_single/4_function_50.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.ashr %arg0, %0 : i64 + %2 = llvm.or disjoint %1, %0 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_51.mlir b/benchmarks/MLIR_single/4_function_51.mlir new file mode 100644 index 0000000..549ff83 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_51.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i32, %arg1: i64) -> i32 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.lshr %arg1, %0 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_52.mlir b/benchmarks/MLIR_single/4_function_52.mlir new file mode 100644 index 0000000..6d0f6cf --- /dev/null +++ b/benchmarks/MLIR_single/4_function_52.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.xor %arg0, %arg1 : i64 + %2 = llvm.lshr exact %1, %arg2 : i64 + %3 = llvm.icmp "sgt" %0, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_53.mlir b/benchmarks/MLIR_single/4_function_53.mlir new file mode 100644 index 0000000..ace0af9 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_53.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.ashr %arg0, %0 : i64 + %2 = llvm.sdiv exact %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_54.mlir b/benchmarks/MLIR_single/4_function_54.mlir new file mode 100644 index 0000000..30e5fb1 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_54.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.urem %arg0, %arg2 : i64 + %1 = llvm.udiv %arg1, %0 : i64 + %2 = llvm.urem %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_55.mlir b/benchmarks/MLIR_single/4_function_55.mlir new file mode 100644 index 0000000..6f61971 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_55.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.urem %arg2, %arg0 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_56.mlir b/benchmarks/MLIR_single/4_function_56.mlir new file mode 100644 index 0000000..d675285 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_56.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.lshr exact %arg0, %arg2 : i64 + %1 = llvm.select %arg1, %arg2, %0 : i1, i64 + %2 = llvm.udiv %1, %0 : i64 + %3 = llvm.srem %arg0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_57.mlir b/benchmarks/MLIR_single/4_function_57.mlir new file mode 100644 index 0000000..d0720ed --- /dev/null +++ b/benchmarks/MLIR_single/4_function_57.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.or %1, %arg1 : i64 + %3 = llvm.or disjoint %2, %arg2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_58.mlir b/benchmarks/MLIR_single/4_function_58.mlir new file mode 100644 index 0000000..1f0b51b --- /dev/null +++ b/benchmarks/MLIR_single/4_function_58.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.xor %arg0, %arg2 : i64 + %2 = llvm.sdiv %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_59.mlir b/benchmarks/MLIR_single/4_function_59.mlir new file mode 100644 index 0000000..4a16252 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_59.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.ashr exact %1, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_6.mlir b/benchmarks/MLIR_single/4_function_6.mlir new file mode 100644 index 0000000..c270683 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_6.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.zext %arg2 : i32 to i64 + %1 = llvm.lshr %arg1, %0 : i64 + %2 = llvm.select %arg0, %1, %1 : i1, i64 + %3 = llvm.or disjoint %2, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_60.mlir b/benchmarks/MLIR_single/4_function_60.mlir new file mode 100644 index 0000000..cb30f98 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_60.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_61.mlir b/benchmarks/MLIR_single/4_function_61.mlir new file mode 100644 index 0000000..579d5c7 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_61.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.or %arg0, %arg1 : i64 + %1 = llvm.sdiv exact %0, %arg0 : i64 + %2 = llvm.or %1, %1 : i64 + %3 = llvm.or disjoint %2, %arg0 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_62.mlir b/benchmarks/MLIR_single/4_function_62.mlir new file mode 100644 index 0000000..449d490 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_62.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr exact %arg2, %arg0 : i64 + %1 = llvm.udiv %arg1, %0 : i64 + %2 = llvm.urem %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_63.mlir b/benchmarks/MLIR_single/4_function_63.mlir new file mode 100644 index 0000000..85b31d3 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_63.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.ashr exact %arg2, %arg2 : i64 + %2 = llvm.srem %arg1, %1 : i64 + %3 = llvm.icmp "ne" %0, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_64.mlir b/benchmarks/MLIR_single/4_function_64.mlir new file mode 100644 index 0000000..1b83f7e --- /dev/null +++ b/benchmarks/MLIR_single/4_function_64.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.ashr exact %1, %arg2 : i64 + %3 = llvm.select %arg0, %2, %arg1 : i1, i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_65.mlir b/benchmarks/MLIR_single/4_function_65.mlir new file mode 100644 index 0000000..4784af9 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_65.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.urem %arg0, %0 : i64 + %2 = llvm.xor %1, %1 : i64 + %3 = llvm.icmp "ult" %1, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_66.mlir b/benchmarks/MLIR_single/4_function_66.mlir new file mode 100644 index 0000000..abd7347 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_66.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_67.mlir b/benchmarks/MLIR_single/4_function_67.mlir new file mode 100644 index 0000000..e30e32f --- /dev/null +++ b/benchmarks/MLIR_single/4_function_67.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_68.mlir b/benchmarks/MLIR_single/4_function_68.mlir new file mode 100644 index 0000000..bc65b54 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_68.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_69.mlir b/benchmarks/MLIR_single/4_function_69.mlir new file mode 100644 index 0000000..6a56f6c --- /dev/null +++ b/benchmarks/MLIR_single/4_function_69.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i1, %arg1: i64) -> i64 { + %0 = llvm.urem %arg1, %arg1 : i64 + %1 = llvm.ashr exact %arg1, %0 : i64 + %2 = llvm.lshr %1, %arg1 : i64 + %3 = llvm.select %arg0, %2, %2 : i1, i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_7.mlir b/benchmarks/MLIR_single/4_function_7.mlir new file mode 100644 index 0000000..9ab4751 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_7.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.icmp "sgt" %arg0, %0 : i64 + %2 = llvm.udiv %0, %0 : i64 + %3 = llvm.select %1, %arg2, %2 : i1, i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_70.mlir b/benchmarks/MLIR_single/4_function_70.mlir new file mode 100644 index 0000000..dfb602e --- /dev/null +++ b/benchmarks/MLIR_single/4_function_70.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i64 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.ashr %0, %arg0 : i64 + %2 = llvm.zext %arg1 : i32 to i64 + %3 = llvm.xor %1, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_71.mlir b/benchmarks/MLIR_single/4_function_71.mlir new file mode 100644 index 0000000..b61e576 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_71.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.lshr %0, %arg1 : i64 + %2 = llvm.sdiv %arg0, %arg0 : i64 + %3 = llvm.udiv %1, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_72.mlir b/benchmarks/MLIR_single/4_function_72.mlir new file mode 100644 index 0000000..d6b244c --- /dev/null +++ b/benchmarks/MLIR_single/4_function_72.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr exact %arg0, %arg1 : i64 + %1 = llvm.ashr exact %0, %arg2 : i64 + %2 = llvm.lshr exact %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_73.mlir b/benchmarks/MLIR_single/4_function_73.mlir new file mode 100644 index 0000000..aff8787 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_73.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg1 : i64 to i1 + %1 = llvm.select %0, %arg2, %arg2 : i1, i64 + %2 = llvm.xor %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_74.mlir b/benchmarks/MLIR_single/4_function_74.mlir new file mode 100644 index 0000000..9c97c28 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_74.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.icmp "ult" %arg0, %arg1 : i64 + %1 = llvm.select %0, %arg1, %arg0 : i1, i64 + %2 = llvm.trunc %1 : i64 to i1 + %3 = llvm.select %2, %arg2, %1 : i1, i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_75.mlir b/benchmarks/MLIR_single/4_function_75.mlir new file mode 100644 index 0000000..283c971 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_75.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.zext %arg2 : i32 to i64 + %2 = llvm.icmp "eq" %0, %1 : i64 + %3 = llvm.select %2, %arg1, %0 : i1, i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_76.mlir b/benchmarks/MLIR_single/4_function_76.mlir new file mode 100644 index 0000000..a64e253 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_76.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.lshr exact %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_77.mlir b/benchmarks/MLIR_single/4_function_77.mlir new file mode 100644 index 0000000..db7a891 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_77.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.lshr exact %arg0, %arg0 : i64 + %1 = llvm.trunc %arg1 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.sdiv exact %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_78.mlir b/benchmarks/MLIR_single/4_function_78.mlir new file mode 100644 index 0000000..6e10c28 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_78.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.ashr exact %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_79.mlir b/benchmarks/MLIR_single/4_function_79.mlir new file mode 100644 index 0000000..36b2d5f --- /dev/null +++ b/benchmarks/MLIR_single/4_function_79.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_8.mlir b/benchmarks/MLIR_single/4_function_8.mlir new file mode 100644 index 0000000..5d8ca76 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_8.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.icmp "eq" %arg0, %arg1 : i64 + %1 = llvm.xor %arg1, %arg0 : i64 + %2 = llvm.select %0, %1, %1 : i1, i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_80.mlir b/benchmarks/MLIR_single/4_function_80.mlir new file mode 100644 index 0000000..7fa386e --- /dev/null +++ b/benchmarks/MLIR_single/4_function_80.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.urem %arg0, %0 : i64 + %2 = llvm.and %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_81.mlir b/benchmarks/MLIR_single/4_function_81.mlir new file mode 100644 index 0000000..6aa6b7f --- /dev/null +++ b/benchmarks/MLIR_single/4_function_81.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.or disjoint %arg2, %arg1 : i64 + %2 = llvm.xor %0, %1 : i64 + %3 = llvm.srem %2, %1 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_82.mlir b/benchmarks/MLIR_single/4_function_82.mlir new file mode 100644 index 0000000..a4ce2b2 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_82.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.or disjoint %arg0, %arg0 : i64 + %1 = llvm.trunc %arg1 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.xor %0, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_83.mlir b/benchmarks/MLIR_single/4_function_83.mlir new file mode 100644 index 0000000..d639975 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_83.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.sdiv exact %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_84.mlir b/benchmarks/MLIR_single/4_function_84.mlir new file mode 100644 index 0000000..3acaf34 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_84.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.urem %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_85.mlir b/benchmarks/MLIR_single/4_function_85.mlir new file mode 100644 index 0000000..7b4f007 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_85.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.or %0, %arg0 : i64 + %2 = llvm.lshr exact %0, %1 : i64 + %3 = llvm.lshr %2, %arg1 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_86.mlir b/benchmarks/MLIR_single/4_function_86.mlir new file mode 100644 index 0000000..74de5db --- /dev/null +++ b/benchmarks/MLIR_single/4_function_86.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.or disjoint %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.select %1, %arg0, %arg1 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_87.mlir b/benchmarks/MLIR_single/4_function_87.mlir new file mode 100644 index 0000000..11dadc8 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_87.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.and %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_88.mlir b/benchmarks/MLIR_single/4_function_88.mlir new file mode 100644 index 0000000..e5d5d3b --- /dev/null +++ b/benchmarks/MLIR_single/4_function_88.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.and %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_89.mlir b/benchmarks/MLIR_single/4_function_89.mlir new file mode 100644 index 0000000..a78531e --- /dev/null +++ b/benchmarks/MLIR_single/4_function_89.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr %arg1, %arg2 : i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.or disjoint %1, %arg2 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_9.mlir b/benchmarks/MLIR_single/4_function_9.mlir new file mode 100644 index 0000000..af0029e --- /dev/null +++ b/benchmarks/MLIR_single/4_function_9.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or %arg0, %arg1 : i64 + %1 = llvm.ashr exact %arg2, %0 : i64 + %2 = llvm.sdiv exact %arg2, %1 : i64 + %3 = llvm.icmp "slt" %0, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_90.mlir b/benchmarks/MLIR_single/4_function_90.mlir new file mode 100644 index 0000000..a1d36ad --- /dev/null +++ b/benchmarks/MLIR_single/4_function_90.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr %arg1, %arg2 : i64 + %1 = llvm.urem %0, %arg2 : i64 + %2 = llvm.xor %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_91.mlir b/benchmarks/MLIR_single/4_function_91.mlir new file mode 100644 index 0000000..12056ac --- /dev/null +++ b/benchmarks/MLIR_single/4_function_91.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.ashr exact %arg1, %arg2 : i64 + %1 = llvm.or disjoint %arg0, %0 : i64 + %2 = llvm.ashr %arg1, %0 : i64 + %3 = llvm.sdiv %1, %2 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_92.mlir b/benchmarks/MLIR_single/4_function_92.mlir new file mode 100644 index 0000000..fb5407e --- /dev/null +++ b/benchmarks/MLIR_single/4_function_92.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.sdiv exact %0, %arg1 : i64 + %2 = llvm.and %1, %arg2 : i64 + %3 = llvm.xor %2, %1 : i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_93.mlir b/benchmarks/MLIR_single/4_function_93.mlir new file mode 100644 index 0000000..9d048aa --- /dev/null +++ b/benchmarks/MLIR_single/4_function_93.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.xor %arg1, %0 : i64 + %2 = llvm.or disjoint %1, %arg0 : i64 + %3 = llvm.icmp "ugt" %0, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_94.mlir b/benchmarks/MLIR_single/4_function_94.mlir new file mode 100644 index 0000000..f3c9cfa --- /dev/null +++ b/benchmarks/MLIR_single/4_function_94.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.trunc %arg1 : i64 to i1 + %2 = llvm.select %1, %arg2, %0 : i1, i64 + %3 = llvm.icmp "ugt" %0, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_95.mlir b/benchmarks/MLIR_single/4_function_95.mlir new file mode 100644 index 0000000..2cd0484 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_95.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.urem %arg1, %arg2 : i64 + %2 = llvm.and %0, %1 : i64 + %3 = llvm.icmp "ule" %2, %1 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_96.mlir b/benchmarks/MLIR_single/4_function_96.mlir new file mode 100644 index 0000000..1d81e56 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_96.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i1 { + %0 = llvm.zext %arg1 : i32 to i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.lshr %arg2, %arg2 : i64 + %3 = llvm.icmp "slt" %1, %2 : i64 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/4_function_97.mlir b/benchmarks/MLIR_single/4_function_97.mlir new file mode 100644 index 0000000..af8d695 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_97.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.ashr exact %1, %arg0 : i64 + %3 = llvm.trunc %2 : i64 to i32 + return %3 : i32 +} + diff --git a/benchmarks/MLIR_single/4_function_98.mlir b/benchmarks/MLIR_single/4_function_98.mlir new file mode 100644 index 0000000..d93c7e1 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_98.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + return %3 : i64 +} + diff --git a/benchmarks/MLIR_single/4_function_99.mlir b/benchmarks/MLIR_single/4_function_99.mlir new file mode 100644 index 0000000..f9fe4f6 --- /dev/null +++ b/benchmarks/MLIR_single/4_function_99.mlir @@ -0,0 +1,8 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.or disjoint %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + return %3 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_0.mlir b/benchmarks/MLIR_single/5_function_0.mlir new file mode 100644 index 0000000..2bad61f --- /dev/null +++ b/benchmarks/MLIR_single/5_function_0.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.urem %0, %arg1 : i64 + %2 = llvm.sdiv %0, %1 : i64 + %3 = llvm.urem %2, %arg2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_1.mlir b/benchmarks/MLIR_single/5_function_1.mlir new file mode 100644 index 0000000..9edb50c --- /dev/null +++ b/benchmarks/MLIR_single/5_function_1.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i32) -> i1 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.ashr exact %0, %0 : i64 + %2 = llvm.zext %arg0 : i32 to i64 + %3 = llvm.urem %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_10.mlir b/benchmarks/MLIR_single/5_function_10.mlir new file mode 100644 index 0000000..f507a05 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_10.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.lshr exact %1, %arg1 : i64 + %3 = llvm.srem %2, %arg0 : i64 + %4 = llvm.urem %1, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_11.mlir b/benchmarks/MLIR_single/5_function_11.mlir new file mode 100644 index 0000000..36b7e11 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_11.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.sdiv %arg1, %1 : i64 + %3 = llvm.sdiv %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_12.mlir b/benchmarks/MLIR_single/5_function_12.mlir new file mode 100644 index 0000000..26f0fee --- /dev/null +++ b/benchmarks/MLIR_single/5_function_12.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr exact %arg1, %arg1 : i64 + %1 = llvm.sdiv %arg0, %0 : i64 + %2 = llvm.icmp "sgt" %1, %arg2 : i64 + %3 = llvm.select %2, %arg1, %arg2 : i1, i64 + %4 = llvm.icmp "sle" %1, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_13.mlir b/benchmarks/MLIR_single/5_function_13.mlir new file mode 100644 index 0000000..f2339da --- /dev/null +++ b/benchmarks/MLIR_single/5_function_13.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.sdiv exact %arg0, %arg1 : i64 + %1 = llvm.zext %arg2 : i32 to i64 + %2 = llvm.lshr %1, %0 : i64 + %3 = llvm.sdiv %2, %1 : i64 + %4 = llvm.icmp "slt" %0, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_14.mlir b/benchmarks/MLIR_single/5_function_14.mlir new file mode 100644 index 0000000..8abc8aa --- /dev/null +++ b/benchmarks/MLIR_single/5_function_14.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.icmp "uge" %arg0, %arg0 : i64 + %1 = llvm.urem %arg1, %arg0 : i64 + %2 = llvm.or disjoint %1, %1 : i64 + %3 = llvm.urem %arg2, %2 : i64 + %4 = llvm.select %0, %1, %3 : i1, i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_15.mlir b/benchmarks/MLIR_single/5_function_15.mlir new file mode 100644 index 0000000..ec39522 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_15.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.or %arg0, %arg1 : i64 + %1 = llvm.icmp "slt" %0, %arg0 : i64 + %2 = llvm.select %1, %arg2, %arg0 : i1, i64 + %3 = llvm.sdiv exact %2, %arg2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_16.mlir b/benchmarks/MLIR_single/5_function_16.mlir new file mode 100644 index 0000000..f8b2a5f --- /dev/null +++ b/benchmarks/MLIR_single/5_function_16.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.sdiv exact %arg0, %0 : i64 + %2 = llvm.udiv %1, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_17.mlir b/benchmarks/MLIR_single/5_function_17.mlir new file mode 100644 index 0000000..beb879d --- /dev/null +++ b/benchmarks/MLIR_single/5_function_17.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i32 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.or %0, %arg0 : i64 + %2 = llvm.zext %arg1 : i32 to i64 + %3 = llvm.ashr %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_18.mlir b/benchmarks/MLIR_single/5_function_18.mlir new file mode 100644 index 0000000..b4e4afb --- /dev/null +++ b/benchmarks/MLIR_single/5_function_18.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.srem %0, %arg1 : i64 + %2 = llvm.sdiv exact %0, %1 : i64 + %3 = llvm.urem %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_19.mlir b/benchmarks/MLIR_single/5_function_19.mlir new file mode 100644 index 0000000..c33e194 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_19.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.ashr exact %arg0, %arg0 : i64 + %2 = llvm.urem %0, %1 : i64 + %3 = llvm.zext %arg2 : i32 to i64 + %4 = llvm.icmp "ult" %2, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_2.mlir b/benchmarks/MLIR_single/5_function_2.mlir new file mode 100644 index 0000000..4f098da --- /dev/null +++ b/benchmarks/MLIR_single/5_function_2.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg1, %arg2 : i64 + %1 = llvm.udiv %arg1, %0 : i64 + %2 = llvm.and %0, %1 : i64 + %3 = llvm.ashr exact %2, %arg1 : i64 + %4 = llvm.urem %arg0, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_20.mlir b/benchmarks/MLIR_single/5_function_20.mlir new file mode 100644 index 0000000..61d47ad --- /dev/null +++ b/benchmarks/MLIR_single/5_function_20.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.or disjoint %arg2, %arg0 : i64 + %1 = llvm.lshr %arg1, %0 : i64 + %2 = llvm.udiv %arg1, %1 : i64 + %3 = llvm.xor %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_21.mlir b/benchmarks/MLIR_single/5_function_21.mlir new file mode 100644 index 0000000..acfe7bc --- /dev/null +++ b/benchmarks/MLIR_single/5_function_21.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.lshr %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.select %1, %0, %arg0 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_22.mlir b/benchmarks/MLIR_single/5_function_22.mlir new file mode 100644 index 0000000..8d4b1ee --- /dev/null +++ b/benchmarks/MLIR_single/5_function_22.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_23.mlir b/benchmarks/MLIR_single/5_function_23.mlir new file mode 100644 index 0000000..04b039b --- /dev/null +++ b/benchmarks/MLIR_single/5_function_23.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_24.mlir b/benchmarks/MLIR_single/5_function_24.mlir new file mode 100644 index 0000000..4dc3d3c --- /dev/null +++ b/benchmarks/MLIR_single/5_function_24.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.xor %arg2, %arg1 : i64 + %2 = llvm.and %1, %arg2 : i64 + %3 = llvm.lshr %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_25.mlir b/benchmarks/MLIR_single/5_function_25.mlir new file mode 100644 index 0000000..ed3cdf7 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_25.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.sdiv exact %arg0, %arg0 : i64 + %1 = llvm.select %arg1, %arg0, %arg0 : i1, i64 + %2 = llvm.urem %0, %1 : i64 + %3 = llvm.and %2, %arg2 : i64 + %4 = llvm.or disjoint %0, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_26.mlir b/benchmarks/MLIR_single/5_function_26.mlir new file mode 100644 index 0000000..e7cbebb --- /dev/null +++ b/benchmarks/MLIR_single/5_function_26.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_27.mlir b/benchmarks/MLIR_single/5_function_27.mlir new file mode 100644 index 0000000..a8bc01c --- /dev/null +++ b/benchmarks/MLIR_single/5_function_27.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.and %arg1, %arg2 : i64 + %1 = llvm.icmp "sgt" %arg0, %0 : i64 + %2 = llvm.srem %arg1, %arg0 : i64 + %3 = llvm.select %1, %arg2, %2 : i1, i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_28.mlir b/benchmarks/MLIR_single/5_function_28.mlir new file mode 100644 index 0000000..7373583 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_28.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg1, %arg1 : i64 + %1 = llvm.sdiv %0, %0 : i64 + %2 = llvm.srem %1, %arg2 : i64 + %3 = llvm.select %arg0, %1, %2 : i1, i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_29.mlir b/benchmarks/MLIR_single/5_function_29.mlir new file mode 100644 index 0000000..de32254 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_29.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.sdiv exact %0, %arg2 : i64 + %2 = llvm.trunc %arg1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.srem %1, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_3.mlir b/benchmarks/MLIR_single/5_function_3.mlir new file mode 100644 index 0000000..8efbbd9 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_3.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.ashr %0, %arg0 : i64 + %2 = llvm.or disjoint %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_30.mlir b/benchmarks/MLIR_single/5_function_30.mlir new file mode 100644 index 0000000..65ae099 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_30.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv exact %arg2, %arg1 : i64 + %1 = llvm.udiv %arg1, %0 : i64 + %2 = llvm.sdiv exact %1, %1 : i64 + %3 = llvm.or disjoint %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_31.mlir b/benchmarks/MLIR_single/5_function_31.mlir new file mode 100644 index 0000000..fe31bb0 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_31.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i64 { + %0 = llvm.lshr exact %arg1, %arg2 : i64 + %1 = llvm.icmp "sge" %arg0, %0 : i64 + %2 = llvm.zext %arg3 : i32 to i64 + %3 = llvm.select %1, %arg0, %2 : i1, i64 + %4 = llvm.xor %3, %arg1 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_32.mlir b/benchmarks/MLIR_single/5_function_32.mlir new file mode 100644 index 0000000..2546b2f --- /dev/null +++ b/benchmarks/MLIR_single/5_function_32.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.xor %0, %arg0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_33.mlir b/benchmarks/MLIR_single/5_function_33.mlir new file mode 100644 index 0000000..c820a62 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_33.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.udiv %arg2, %arg2 : i64 + %1 = llvm.and %arg2, %0 : i64 + %2 = llvm.select %arg1, %arg0, %1 : i1, i64 + %3 = llvm.and %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_34.mlir b/benchmarks/MLIR_single/5_function_34.mlir new file mode 100644 index 0000000..014674c --- /dev/null +++ b/benchmarks/MLIR_single/5_function_34.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.xor %arg1, %0 : i64 + %2 = llvm.xor %0, %1 : i64 + %3 = llvm.or disjoint %arg2, %0 : i64 + %4 = llvm.icmp "ne" %2, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_35.mlir b/benchmarks/MLIR_single/5_function_35.mlir new file mode 100644 index 0000000..692407e --- /dev/null +++ b/benchmarks/MLIR_single/5_function_35.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.and %arg2, %arg1 : i64 + %1 = llvm.ashr exact %arg2, %0 : i64 + %2 = llvm.udiv %arg1, %1 : i64 + %3 = llvm.lshr %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_36.mlir b/benchmarks/MLIR_single/5_function_36.mlir new file mode 100644 index 0000000..ca796f6 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_36.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.lshr exact %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_37.mlir b/benchmarks/MLIR_single/5_function_37.mlir new file mode 100644 index 0000000..cec488f --- /dev/null +++ b/benchmarks/MLIR_single/5_function_37.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i1 + %1 = llvm.zext %arg2 : i32 to i64 + %2 = llvm.or disjoint %arg1, %1 : i64 + %3 = llvm.select %0, %arg0, %2 : i1, i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_38.mlir b/benchmarks/MLIR_single/5_function_38.mlir new file mode 100644 index 0000000..532969d --- /dev/null +++ b/benchmarks/MLIR_single/5_function_38.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i32 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.and %0, %arg2 : i64 + %2 = llvm.select %arg1, %0, %1 : i1, i64 + %3 = llvm.sdiv %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_39.mlir b/benchmarks/MLIR_single/5_function_39.mlir new file mode 100644 index 0000000..5311756 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_39.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i32) -> i1 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.xor %0, %0 : i64 + %3 = llvm.select %1, %0, %2 : i1, i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_4.mlir b/benchmarks/MLIR_single/5_function_4.mlir new file mode 100644 index 0000000..8bded37 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_4.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i32 { + %0 = llvm.sext %arg1 : i32 to i64 + %1 = llvm.sdiv %arg0, %0 : i64 + %2 = llvm.udiv %arg0, %1 : i64 + %3 = llvm.or disjoint %2, %arg2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_40.mlir b/benchmarks/MLIR_single/5_function_40.mlir new file mode 100644 index 0000000..ed565f0 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_40.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.and %arg1, %arg1 : i64 + %2 = llvm.urem %0, %1 : i64 + %3 = llvm.ashr exact %arg2, %arg1 : i64 + %4 = llvm.ashr %2, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_41.mlir b/benchmarks/MLIR_single/5_function_41.mlir new file mode 100644 index 0000000..cb08234 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_41.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.or disjoint %2, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_42.mlir b/benchmarks/MLIR_single/5_function_42.mlir new file mode 100644 index 0000000..83dc8dd --- /dev/null +++ b/benchmarks/MLIR_single/5_function_42.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.xor %0, %arg0 : i64 + %2 = llvm.or disjoint %0, %1 : i64 + %3 = llvm.udiv %arg1, %arg2 : i64 + %4 = llvm.icmp "eq" %2, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_43.mlir b/benchmarks/MLIR_single/5_function_43.mlir new file mode 100644 index 0000000..1ce3463 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_43.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.lshr %arg0, %arg1 : i64 + %1 = llvm.srem %0, %arg2 : i64 + %2 = llvm.urem %0, %1 : i64 + %3 = llvm.and %2, %arg2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_44.mlir b/benchmarks/MLIR_single/5_function_44.mlir new file mode 100644 index 0000000..49222dd --- /dev/null +++ b/benchmarks/MLIR_single/5_function_44.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.or disjoint %0, %arg2 : i64 + %2 = llvm.or %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_45.mlir b/benchmarks/MLIR_single/5_function_45.mlir new file mode 100644 index 0000000..17db826 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_45.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.zext %arg2 : i32 to i64 + %1 = llvm.sdiv exact %arg1, %0 : i64 + %2 = llvm.xor %arg0, %1 : i64 + %3 = llvm.or %2, %arg1 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_46.mlir b/benchmarks/MLIR_single/5_function_46.mlir new file mode 100644 index 0000000..7769fbc --- /dev/null +++ b/benchmarks/MLIR_single/5_function_46.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_47.mlir b/benchmarks/MLIR_single/5_function_47.mlir new file mode 100644 index 0000000..37b4e5d --- /dev/null +++ b/benchmarks/MLIR_single/5_function_47.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.udiv %arg2, %arg1 : i64 + %1 = llvm.select %arg0, %arg1, %0 : i1, i64 + %2 = llvm.urem %1, %1 : i64 + %3 = llvm.srem %0, %2 : i64 + %4 = llvm.icmp "eq" %1, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_48.mlir b/benchmarks/MLIR_single/5_function_48.mlir new file mode 100644 index 0000000..32d05bb --- /dev/null +++ b/benchmarks/MLIR_single/5_function_48.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.udiv %arg0, %0 : i64 + %2 = llvm.xor %0, %0 : i64 + %3 = llvm.ashr %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_49.mlir b/benchmarks/MLIR_single/5_function_49.mlir new file mode 100644 index 0000000..271f884 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_49.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.srem %arg2, %arg0 : i64 + %1 = llvm.sdiv exact %arg1, %0 : i64 + %2 = llvm.xor %arg0, %1 : i64 + %3 = llvm.lshr exact %2, %arg0 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_5.mlir b/benchmarks/MLIR_single/5_function_5.mlir new file mode 100644 index 0000000..df100f2 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_5.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.udiv %0, %arg2 : i64 + %2 = llvm.udiv %1, %arg0 : i64 + %3 = llvm.udiv %2, %1 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_50.mlir b/benchmarks/MLIR_single/5_function_50.mlir new file mode 100644 index 0000000..d01cb5b --- /dev/null +++ b/benchmarks/MLIR_single/5_function_50.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.lshr %arg0, %arg1 : i64 + %1 = llvm.and %0, %arg0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_51.mlir b/benchmarks/MLIR_single/5_function_51.mlir new file mode 100644 index 0000000..ab57a18 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_51.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or disjoint %arg1, %arg2 : i64 + %1 = llvm.lshr exact %arg0, %0 : i64 + %2 = llvm.urem %1, %arg0 : i64 + %3 = llvm.and %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_52.mlir b/benchmarks/MLIR_single/5_function_52.mlir new file mode 100644 index 0000000..a50c893 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_52.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.lshr %1, %arg0 : i64 + %3 = llvm.sdiv %2, %arg0 : i64 + %4 = llvm.or disjoint %3, %arg1 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_53.mlir b/benchmarks/MLIR_single/5_function_53.mlir new file mode 100644 index 0000000..81dea13 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_53.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.icmp "eq" %0, %0 : i64 + %2 = llvm.select %1, %arg0, %arg1 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_54.mlir b/benchmarks/MLIR_single/5_function_54.mlir new file mode 100644 index 0000000..1e5b743 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_54.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.sdiv exact %arg0, %arg1 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.and %2, %0 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_55.mlir b/benchmarks/MLIR_single/5_function_55.mlir new file mode 100644 index 0000000..ee16107 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_55.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.icmp "sge" %arg0, %arg1 : i64 + %1 = llvm.select %0, %arg2, %arg2 : i1, i64 + %2 = llvm.urem %1, %arg1 : i64 + %3 = llvm.select %0, %arg2, %2 : i1, i64 + %4 = llvm.icmp "sge" %3, %arg0 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_56.mlir b/benchmarks/MLIR_single/5_function_56.mlir new file mode 100644 index 0000000..a3c4576 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_56.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.sdiv exact %arg1, %arg1 : i64 + %3 = llvm.udiv %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_57.mlir b/benchmarks/MLIR_single/5_function_57.mlir new file mode 100644 index 0000000..c51683f --- /dev/null +++ b/benchmarks/MLIR_single/5_function_57.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.lshr exact %arg1, %arg0 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.ashr %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + %4 = llvm.select %3, %arg2, %arg1 : i1, i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_58.mlir b/benchmarks/MLIR_single/5_function_58.mlir new file mode 100644 index 0000000..8c63318 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_58.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i32, %arg1: i64) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.or %arg1, %0 : i64 + %2 = llvm.xor %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_59.mlir b/benchmarks/MLIR_single/5_function_59.mlir new file mode 100644 index 0000000..331455e --- /dev/null +++ b/benchmarks/MLIR_single/5_function_59.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.ashr %arg1, %arg1 : i64 + %1 = llvm.and %0, %arg1 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.and %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_6.mlir b/benchmarks/MLIR_single/5_function_6.mlir new file mode 100644 index 0000000..b5c3ac8 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_6.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i1) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.select %arg1, %0, %0 : i1, i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.icmp "eq" %arg0, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_60.mlir b/benchmarks/MLIR_single/5_function_60.mlir new file mode 100644 index 0000000..0769905 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_60.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.and %arg0, %1 : i64 + %3 = llvm.select %arg1, %arg2, %2 : i1, i64 + %4 = llvm.icmp "eq" %2, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_61.mlir b/benchmarks/MLIR_single/5_function_61.mlir new file mode 100644 index 0000000..242b533 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_61.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i32, %arg1: i32) -> i32 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.zext %arg1 : i32 to i64 + %2 = llvm.sdiv exact %1, %0 : i64 + %3 = llvm.lshr %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_62.mlir b/benchmarks/MLIR_single/5_function_62.mlir new file mode 100644 index 0000000..977f631 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_62.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i32 { + %0 = llvm.lshr exact %arg0, %arg1 : i64 + %1 = llvm.select %arg2, %0, %arg0 : i1, i64 + %2 = llvm.or %arg0, %1 : i64 + %3 = llvm.srem %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_63.mlir b/benchmarks/MLIR_single/5_function_63.mlir new file mode 100644 index 0000000..676a13b --- /dev/null +++ b/benchmarks/MLIR_single/5_function_63.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.trunc %arg2 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.sdiv %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_64.mlir b/benchmarks/MLIR_single/5_function_64.mlir new file mode 100644 index 0000000..51a7aa1 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_64.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.or %0, %arg0 : i64 + %2 = llvm.urem %1, %arg1 : i64 + %3 = llvm.or %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_65.mlir b/benchmarks/MLIR_single/5_function_65.mlir new file mode 100644 index 0000000..e6f47a9 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_65.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.srem %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_66.mlir b/benchmarks/MLIR_single/5_function_66.mlir new file mode 100644 index 0000000..4970943 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_66.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.urem %arg0, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_67.mlir b/benchmarks/MLIR_single/5_function_67.mlir new file mode 100644 index 0000000..1c0152f --- /dev/null +++ b/benchmarks/MLIR_single/5_function_67.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.lshr %arg0, %arg0 : i64 + %1 = llvm.udiv %0, %arg1 : i64 + %2 = llvm.udiv %1, %arg2 : i64 + %3 = llvm.lshr %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_68.mlir b/benchmarks/MLIR_single/5_function_68.mlir new file mode 100644 index 0000000..879f107 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_68.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.sdiv %arg2, %arg0 : i64 + %2 = llvm.srem %1, %1 : i64 + %3 = llvm.sdiv exact %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_69.mlir b/benchmarks/MLIR_single/5_function_69.mlir new file mode 100644 index 0000000..7442e7c --- /dev/null +++ b/benchmarks/MLIR_single/5_function_69.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or %arg1, %arg2 : i64 + %1 = llvm.or %arg2, %arg1 : i64 + %2 = llvm.sdiv exact %0, %1 : i64 + %3 = llvm.and %2, %arg1 : i64 + %4 = llvm.icmp "ugt" %arg0, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_7.mlir b/benchmarks/MLIR_single/5_function_7.mlir new file mode 100644 index 0000000..9eb676c --- /dev/null +++ b/benchmarks/MLIR_single/5_function_7.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr exact %arg1, %arg2 : i64 + %1 = llvm.or %arg1, %0 : i64 + %2 = llvm.sdiv exact %0, %1 : i64 + %3 = llvm.urem %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_70.mlir b/benchmarks/MLIR_single/5_function_70.mlir new file mode 100644 index 0000000..4d56794 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_70.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64) -> i1 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.lshr exact %arg1, %1 : i64 + %3 = llvm.select %arg0, %2, %arg1 : i1, i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_71.mlir b/benchmarks/MLIR_single/5_function_71.mlir new file mode 100644 index 0000000..0483176 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_71.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_72.mlir b/benchmarks/MLIR_single/5_function_72.mlir new file mode 100644 index 0000000..b167a3e --- /dev/null +++ b/benchmarks/MLIR_single/5_function_72.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.srem %arg0, %1 : i64 + %3 = llvm.or %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_73.mlir b/benchmarks/MLIR_single/5_function_73.mlir new file mode 100644 index 0000000..d252c61 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_73.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.ashr %arg0, %0 : i64 + %2 = llvm.udiv %1, %arg2 : i64 + %3 = llvm.urem %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_74.mlir b/benchmarks/MLIR_single/5_function_74.mlir new file mode 100644 index 0000000..525ab6e --- /dev/null +++ b/benchmarks/MLIR_single/5_function_74.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i32) -> i32 { + %0 = llvm.sext %arg2 : i32 to i64 + %1 = llvm.select %arg1, %arg0, %0 : i1, i64 + %2 = llvm.and %arg0, %1 : i64 + %3 = llvm.lshr exact %2, %arg0 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_75.mlir b/benchmarks/MLIR_single/5_function_75.mlir new file mode 100644 index 0000000..cba528b --- /dev/null +++ b/benchmarks/MLIR_single/5_function_75.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.sdiv %arg1, %0 : i64 + %2 = llvm.and %arg0, %1 : i64 + %3 = llvm.sdiv %arg1, %1 : i64 + %4 = llvm.srem %2, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_76.mlir b/benchmarks/MLIR_single/5_function_76.mlir new file mode 100644 index 0000000..ee2b4ce --- /dev/null +++ b/benchmarks/MLIR_single/5_function_76.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i1 { + %0 = llvm.or %arg0, %arg0 : i64 + %1 = llvm.zext %arg1 : i32 to i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.ashr exact %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_77.mlir b/benchmarks/MLIR_single/5_function_77.mlir new file mode 100644 index 0000000..fe64b35 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_77.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.lshr %arg0, %arg1 : i64 + %1 = llvm.sdiv %0, %0 : i64 + %2 = llvm.and %1, %arg2 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_78.mlir b/benchmarks/MLIR_single/5_function_78.mlir new file mode 100644 index 0000000..1d232d1 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_78.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i32 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.lshr exact %0, %arg1 : i64 + %2 = llvm.zext %arg2 : i32 to i64 + %3 = llvm.srem %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_79.mlir b/benchmarks/MLIR_single/5_function_79.mlir new file mode 100644 index 0000000..80f94ec --- /dev/null +++ b/benchmarks/MLIR_single/5_function_79.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.or disjoint %arg0, %arg0 : i64 + %1 = llvm.lshr %0, %arg0 : i64 + %2 = llvm.trunc %arg1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.icmp "ule" %1, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_8.mlir b/benchmarks/MLIR_single/5_function_8.mlir new file mode 100644 index 0000000..f5532d4 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_8.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.sdiv %arg0, %arg2 : i64 + %1 = llvm.xor %arg1, %0 : i64 + %2 = llvm.udiv %arg0, %1 : i64 + %3 = llvm.srem %2, %1 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_80.mlir b/benchmarks/MLIR_single/5_function_80.mlir new file mode 100644 index 0000000..0f40d2e --- /dev/null +++ b/benchmarks/MLIR_single/5_function_80.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.sdiv exact %arg0, %arg1 : i64 + %1 = llvm.ashr exact %arg0, %0 : i64 + %2 = llvm.ashr exact %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_81.mlir b/benchmarks/MLIR_single/5_function_81.mlir new file mode 100644 index 0000000..601de7c --- /dev/null +++ b/benchmarks/MLIR_single/5_function_81.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.trunc %arg2 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.and %0, %2 : i64 + %4 = llvm.icmp "ule" %3, %0 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_82.mlir b/benchmarks/MLIR_single/5_function_82.mlir new file mode 100644 index 0000000..6f42cda --- /dev/null +++ b/benchmarks/MLIR_single/5_function_82.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.or disjoint %1, %arg0 : i64 + %3 = llvm.lshr exact %arg1, %arg2 : i64 + %4 = llvm.icmp "uge" %2, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_83.mlir b/benchmarks/MLIR_single/5_function_83.mlir new file mode 100644 index 0000000..c7fbbf9 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_83.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.or %arg0, %arg1 : i64 + %1 = llvm.sext %arg2 : i32 to i64 + %2 = llvm.ashr %0, %1 : i64 + %3 = llvm.sdiv exact %arg0, %2 : i64 + %4 = llvm.icmp "sge" %2, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_84.mlir b/benchmarks/MLIR_single/5_function_84.mlir new file mode 100644 index 0000000..685fef5 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_84.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.select %arg1, %arg2, %arg0 : i1, i64 + %1 = llvm.or disjoint %arg0, %0 : i64 + %2 = llvm.and %1, %arg2 : i64 + %3 = llvm.ashr %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_85.mlir b/benchmarks/MLIR_single/5_function_85.mlir new file mode 100644 index 0000000..e8c4782 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_85.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.zext %0 : i32 to i64 + %3 = llvm.lshr %arg1, %2 : i64 + %4 = llvm.sdiv exact %1, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_86.mlir b/benchmarks/MLIR_single/5_function_86.mlir new file mode 100644 index 0000000..e762da9 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_86.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.sdiv exact %arg0, %arg0 : i64 + %1 = llvm.and %arg0, %arg0 : i64 + %2 = llvm.select %arg1, %0, %1 : i1, i64 + %3 = llvm.urem %2, %arg2 : i64 + %4 = llvm.or %0, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_87.mlir b/benchmarks/MLIR_single/5_function_87.mlir new file mode 100644 index 0000000..2f6befb --- /dev/null +++ b/benchmarks/MLIR_single/5_function_87.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg1 : i64 to i1 + %1 = llvm.sdiv %arg2, %arg1 : i64 + %2 = llvm.select %0, %arg2, %1 : i1, i64 + %3 = llvm.or disjoint %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_88.mlir b/benchmarks/MLIR_single/5_function_88.mlir new file mode 100644 index 0000000..fb17054 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_88.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.or disjoint %arg0, %arg0 : i64 + %1 = llvm.lshr exact %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_89.mlir b/benchmarks/MLIR_single/5_function_89.mlir new file mode 100644 index 0000000..b5d19a9 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_89.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.ashr %arg1, %arg2 : i64 + %1 = llvm.select %arg0, %0, %arg2 : i1, i64 + %2 = llvm.select %arg0, %arg2, %arg2 : i1, i64 + %3 = llvm.and %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_9.mlir b/benchmarks/MLIR_single/5_function_9.mlir new file mode 100644 index 0000000..d3a4011 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_9.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.xor %arg1, %arg2 : i64 + %2 = llvm.ashr exact %arg1, %1 : i64 + %3 = llvm.ashr %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_90.mlir b/benchmarks/MLIR_single/5_function_90.mlir new file mode 100644 index 0000000..66b14f3 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_90.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.ashr %0, %arg1 : i64 + %2 = llvm.ashr exact %arg1, %0 : i64 + %3 = llvm.srem %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_91.mlir b/benchmarks/MLIR_single/5_function_91.mlir new file mode 100644 index 0000000..3f1ccd4 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_91.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i1 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.zext %arg1 : i32 to i64 + %2 = llvm.and %arg0, %1 : i64 + %3 = llvm.and %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_92.mlir b/benchmarks/MLIR_single/5_function_92.mlir new file mode 100644 index 0000000..cfb398b --- /dev/null +++ b/benchmarks/MLIR_single/5_function_92.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.xor %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_93.mlir b/benchmarks/MLIR_single/5_function_93.mlir new file mode 100644 index 0000000..e4f2b7d --- /dev/null +++ b/benchmarks/MLIR_single/5_function_93.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg1, %arg2 : i64 + %1 = llvm.trunc %arg0 : i64 to i1 + %2 = llvm.select %1, %arg2, %arg2 : i1, i64 + %3 = llvm.udiv %0, %2 : i64 + %4 = llvm.icmp "sge" %arg0, %3 : i64 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/5_function_94.mlir b/benchmarks/MLIR_single/5_function_94.mlir new file mode 100644 index 0000000..e0f3ef4 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_94.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.lshr %arg2, %0 : i64 + %4 = llvm.sdiv exact %2, %3 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_95.mlir b/benchmarks/MLIR_single/5_function_95.mlir new file mode 100644 index 0000000..05c82fa --- /dev/null +++ b/benchmarks/MLIR_single/5_function_95.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.or %arg1, %arg0 : i64 + %1 = llvm.or disjoint %0, %arg0 : i64 + %2 = llvm.lshr exact %1, %arg2 : i64 + %3 = llvm.lshr exact %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_96.mlir b/benchmarks/MLIR_single/5_function_96.mlir new file mode 100644 index 0000000..0da2ef1 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_96.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg1, %arg2 : i64 + %1 = llvm.lshr exact %0, %arg0 : i64 + %2 = llvm.and %arg0, %1 : i64 + %3 = llvm.srem %2, %arg0 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_97.mlir b/benchmarks/MLIR_single/5_function_97.mlir new file mode 100644 index 0000000..91619f3 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_97.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.sext %0 : i32 to i64 + %3 = llvm.or disjoint %1, %2 : i64 + %4 = llvm.srem %3, %arg1 : i64 + return %4 : i64 +} + diff --git a/benchmarks/MLIR_single/5_function_98.mlir b/benchmarks/MLIR_single/5_function_98.mlir new file mode 100644 index 0000000..7137098 --- /dev/null +++ b/benchmarks/MLIR_single/5_function_98.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.lshr %arg1, %0 : i64 + %2 = llvm.sdiv exact %1, %arg1 : i64 + %3 = llvm.and %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + return %4 : i32 +} + diff --git a/benchmarks/MLIR_single/5_function_99.mlir b/benchmarks/MLIR_single/5_function_99.mlir new file mode 100644 index 0000000..d14b64c --- /dev/null +++ b/benchmarks/MLIR_single/5_function_99.mlir @@ -0,0 +1,9 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.xor %0, %arg2 : i64 + %2 = llvm.sdiv %arg2, %arg2 : i64 + %3 = llvm.udiv %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + return %4 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_0.mlir b/benchmarks/MLIR_single/6_function_0.mlir new file mode 100644 index 0000000..f759030 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_0.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.select %arg1, %arg0, %arg0 : i1, i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.select %arg1, %arg2, %arg0 : i1, i64 + %3 = llvm.sdiv %1, %2 : i64 + %4 = llvm.urem %3, %1 : i64 + %5 = llvm.or %4, %1 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_1.mlir b/benchmarks/MLIR_single/6_function_1.mlir new file mode 100644 index 0000000..b589cd6 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_1.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.lshr exact %arg2, %arg0 : i64 + %4 = llvm.xor %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_10.mlir b/benchmarks/MLIR_single/6_function_10.mlir new file mode 100644 index 0000000..dd24c99 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_10.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg1, %arg2 : i64 + %1 = llvm.sdiv exact %arg1, %arg2 : i64 + %2 = llvm.sdiv %arg1, %1 : i64 + %3 = llvm.udiv %0, %2 : i64 + %4 = llvm.lshr %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_11.mlir b/benchmarks/MLIR_single/6_function_11.mlir new file mode 100644 index 0000000..e7e62a6 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_11.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.trunc %arg1 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.and %0, %2 : i64 + %4 = llvm.select %arg2, %0, %arg0 : i1, i64 + %5 = llvm.lshr %3, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_12.mlir b/benchmarks/MLIR_single/6_function_12.mlir new file mode 100644 index 0000000..43b5c07 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_12.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.and %arg1, %arg1 : i64 + %2 = llvm.ashr exact %0, %1 : i64 + %3 = llvm.urem %arg0, %2 : i64 + %4 = llvm.and %3, %arg1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_13.mlir b/benchmarks/MLIR_single/6_function_13.mlir new file mode 100644 index 0000000..ea68b3d --- /dev/null +++ b/benchmarks/MLIR_single/6_function_13.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i1 { + %0 = llvm.zext %arg1 : i32 to i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.lshr %arg2, %arg2 : i64 + %3 = llvm.sdiv %arg2, %2 : i64 + %4 = llvm.ashr %1, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_14.mlir b/benchmarks/MLIR_single/6_function_14.mlir new file mode 100644 index 0000000..797959a --- /dev/null +++ b/benchmarks/MLIR_single/6_function_14.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i1) -> i64 { + %0 = llvm.srem %arg1, %arg1 : i64 + %1 = llvm.select %arg2, %0, %arg1 : i1, i64 + %2 = llvm.select %arg0, %arg1, %1 : i1, i64 + %3 = llvm.srem %2, %0 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_15.mlir b/benchmarks/MLIR_single/6_function_15.mlir new file mode 100644 index 0000000..bd2aef8 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_15.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr %arg0, %arg1 : i64 + %1 = llvm.lshr %0, %arg0 : i64 + %2 = llvm.srem %arg0, %1 : i64 + %3 = llvm.urem %arg2, %1 : i64 + %4 = llvm.urem %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_16.mlir b/benchmarks/MLIR_single/6_function_16.mlir new file mode 100644 index 0000000..2437304 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_16.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.sext %arg2 : i32 to i64 + %2 = llvm.lshr exact %0, %1 : i64 + %3 = llvm.urem %0, %0 : i64 + %4 = llvm.sdiv %3, %arg1 : i64 + %5 = llvm.icmp "eq" %2, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_17.mlir b/benchmarks/MLIR_single/6_function_17.mlir new file mode 100644 index 0000000..b7e6636 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_17.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.xor %0, %arg2 : i64 + %5 = llvm.xor %3, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_18.mlir b/benchmarks/MLIR_single/6_function_18.mlir new file mode 100644 index 0000000..5eb74fa --- /dev/null +++ b/benchmarks/MLIR_single/6_function_18.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i1 { + %0 = llvm.or %arg0, %arg1 : i64 + %1 = llvm.select %arg2, %arg0, %arg0 : i1, i64 + %2 = llvm.ashr %arg1, %arg0 : i64 + %3 = llvm.select %arg2, %2, %2 : i1, i64 + %4 = llvm.lshr %1, %3 : i64 + %5 = llvm.icmp "ne" %0, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_19.mlir b/benchmarks/MLIR_single/6_function_19.mlir new file mode 100644 index 0000000..a65b71e --- /dev/null +++ b/benchmarks/MLIR_single/6_function_19.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.sdiv %arg2, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i1 + %3 = llvm.select %2, %arg2, %1 : i1, i64 + %4 = llvm.sdiv %0, %3 : i64 + %5 = llvm.lshr exact %4, %1 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_2.mlir b/benchmarks/MLIR_single/6_function_2.mlir new file mode 100644 index 0000000..0b12c7e --- /dev/null +++ b/benchmarks/MLIR_single/6_function_2.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.xor %arg1, %arg2 : i64 + %3 = llvm.xor %2, %1 : i64 + %4 = llvm.srem %1, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_20.mlir b/benchmarks/MLIR_single/6_function_20.mlir new file mode 100644 index 0000000..27d42b9 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_20.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.and %arg0, %2 : i64 + %4 = llvm.srem %3, %arg1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_21.mlir b/benchmarks/MLIR_single/6_function_21.mlir new file mode 100644 index 0000000..3975b98 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_21.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.sext %arg2 : i32 to i64 + %1 = llvm.select %arg0, %arg1, %0 : i1, i64 + %2 = llvm.sdiv exact %0, %0 : i64 + %3 = llvm.xor %1, %2 : i64 + %4 = llvm.xor %arg1, %2 : i64 + %5 = llvm.or %3, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_22.mlir b/benchmarks/MLIR_single/6_function_22.mlir new file mode 100644 index 0000000..204d389 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_22.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.or disjoint %arg1, %arg2 : i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.srem %1, %arg0 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_23.mlir b/benchmarks/MLIR_single/6_function_23.mlir new file mode 100644 index 0000000..9e731e0 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_23.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.or %arg2, %0 : i64 + %2 = llvm.lshr %1, %arg1 : i64 + %3 = llvm.urem %1, %2 : i64 + %4 = llvm.srem %3, %3 : i64 + %5 = llvm.icmp "sge" %0, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_24.mlir b/benchmarks/MLIR_single/6_function_24.mlir new file mode 100644 index 0000000..76ed70e --- /dev/null +++ b/benchmarks/MLIR_single/6_function_24.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.sdiv %arg2, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i1 + %3 = llvm.select %2, %arg2, %0 : i1, i64 + %4 = llvm.udiv %0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_25.mlir b/benchmarks/MLIR_single/6_function_25.mlir new file mode 100644 index 0000000..56991c6 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_25.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.srem %0, %arg1 : i64 + %2 = llvm.urem %0, %1 : i64 + %3 = llvm.trunc %arg2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.ashr %2, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_26.mlir b/benchmarks/MLIR_single/6_function_26.mlir new file mode 100644 index 0000000..82edbf1 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_26.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.select %arg1, %arg2, %arg2 : i1, i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.srem %arg0, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_27.mlir b/benchmarks/MLIR_single/6_function_27.mlir new file mode 100644 index 0000000..e25236b --- /dev/null +++ b/benchmarks/MLIR_single/6_function_27.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.and %arg2, %arg1 : i64 + %3 = llvm.or %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_28.mlir b/benchmarks/MLIR_single/6_function_28.mlir new file mode 100644 index 0000000..3bef4e4 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_28.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv %arg1, %arg2 : i64 + %1 = llvm.and %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.ashr exact %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_29.mlir b/benchmarks/MLIR_single/6_function_29.mlir new file mode 100644 index 0000000..8724e99 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_29.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.sdiv exact %arg0, %arg0 : i64 + %1 = llvm.lshr exact %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.or %3, %arg1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_3.mlir b/benchmarks/MLIR_single/6_function_3.mlir new file mode 100644 index 0000000..09057f8 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_3.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.icmp "sge" %arg0, %arg0 : i64 + %1 = llvm.srem %arg1, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.select %0, %1, %3 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_30.mlir b/benchmarks/MLIR_single/6_function_30.mlir new file mode 100644 index 0000000..67f9ab0 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_30.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.ashr exact %arg1, %arg0 : i64 + %1 = llvm.lshr %0, %arg2 : i64 + %2 = llvm.lshr %1, %1 : i64 + %3 = llvm.udiv %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_31.mlir b/benchmarks/MLIR_single/6_function_31.mlir new file mode 100644 index 0000000..f29a2b2 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_31.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.zext %0 : i32 to i64 + %3 = llvm.sdiv exact %1, %2 : i64 + %4 = llvm.ashr exact %3, %2 : i64 + %5 = llvm.icmp "ule" %arg0, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_32.mlir b/benchmarks/MLIR_single/6_function_32.mlir new file mode 100644 index 0000000..8da689e --- /dev/null +++ b/benchmarks/MLIR_single/6_function_32.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i32) -> i32 { + %0 = llvm.zext %arg1 : i32 to i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.sext %arg2 : i32 to i64 + %3 = llvm.udiv %2, %2 : i64 + %4 = llvm.srem %1, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_33.mlir b/benchmarks/MLIR_single/6_function_33.mlir new file mode 100644 index 0000000..898c736 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_33.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.or disjoint %arg0, %arg0 : i64 + %4 = llvm.ashr exact %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_34.mlir b/benchmarks/MLIR_single/6_function_34.mlir new file mode 100644 index 0000000..f66727f --- /dev/null +++ b/benchmarks/MLIR_single/6_function_34.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i1 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.select %1, %arg0, %arg1 : i1, i64 + %3 = llvm.select %arg2, %0, %arg1 : i1, i64 + %4 = llvm.srem %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_35.mlir b/benchmarks/MLIR_single/6_function_35.mlir new file mode 100644 index 0000000..97c0030 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_35.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i64 { + %0 = llvm.sext %arg1 : i32 to i64 + %1 = llvm.srem %arg2, %arg0 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.zext %arg1 : i32 to i64 + %4 = llvm.lshr %2, %3 : i64 + %5 = llvm.sdiv exact %arg0, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_36.mlir b/benchmarks/MLIR_single/6_function_36.mlir new file mode 100644 index 0000000..364129c --- /dev/null +++ b/benchmarks/MLIR_single/6_function_36.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.xor %2, %2 : i64 + %4 = llvm.lshr exact %0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_37.mlir b/benchmarks/MLIR_single/6_function_37.mlir new file mode 100644 index 0000000..da3bff5 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_37.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.sdiv exact %0, %arg2 : i64 + %2 = llvm.urem %arg0, %arg0 : i64 + %3 = llvm.sdiv %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_38.mlir b/benchmarks/MLIR_single/6_function_38.mlir new file mode 100644 index 0000000..8f2fba4 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_38.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i32 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.urem %arg0, %0 : i64 + %2 = llvm.lshr %arg0, %1 : i64 + %3 = llvm.zext %arg2 : i32 to i64 + %4 = llvm.and %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_39.mlir b/benchmarks/MLIR_single/6_function_39.mlir new file mode 100644 index 0000000..eb2faeb --- /dev/null +++ b/benchmarks/MLIR_single/6_function_39.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.trunc %arg2 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.srem %0, %2 : i64 + %4 = llvm.udiv %3, %arg2 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_4.mlir b/benchmarks/MLIR_single/6_function_4.mlir new file mode 100644 index 0000000..84bcd54 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_4.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.lshr exact %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.ashr exact %2, %arg0 : i64 + %4 = llvm.xor %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_40.mlir b/benchmarks/MLIR_single/6_function_40.mlir new file mode 100644 index 0000000..bec9688 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_40.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.udiv %0, %arg1 : i64 + %2 = llvm.srem %0, %1 : i64 + %3 = llvm.xor %2, %arg2 : i64 + %4 = llvm.udiv %0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_41.mlir b/benchmarks/MLIR_single/6_function_41.mlir new file mode 100644 index 0000000..644b031 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_41.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.select %arg1, %arg0, %arg2 : i1, i64 + %1 = llvm.udiv %arg0, %0 : i64 + %2 = llvm.urem %arg2, %arg2 : i64 + %3 = llvm.srem %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_42.mlir b/benchmarks/MLIR_single/6_function_42.mlir new file mode 100644 index 0000000..bf294b5 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_42.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.urem %0, %arg2 : i64 + %2 = llvm.trunc %arg2 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.lshr exact %1, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_43.mlir b/benchmarks/MLIR_single/6_function_43.mlir new file mode 100644 index 0000000..e6b63ce --- /dev/null +++ b/benchmarks/MLIR_single/6_function_43.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.srem %0, %arg1 : i64 + %2 = llvm.ashr exact %arg2, %arg1 : i64 + %3 = llvm.icmp "slt" %1, %2 : i64 + %4 = llvm.select %3, %2, %arg1 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_44.mlir b/benchmarks/MLIR_single/6_function_44.mlir new file mode 100644 index 0000000..efeba2c --- /dev/null +++ b/benchmarks/MLIR_single/6_function_44.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.udiv %1, %arg2 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.lshr %arg0, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_45.mlir b/benchmarks/MLIR_single/6_function_45.mlir new file mode 100644 index 0000000..998e17b --- /dev/null +++ b/benchmarks/MLIR_single/6_function_45.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i1) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.select %arg1, %1, %1 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.icmp "sgt" %1, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_46.mlir b/benchmarks/MLIR_single/6_function_46.mlir new file mode 100644 index 0000000..79e89c2 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_46.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.icmp "sle" %arg0, %arg0 : i64 + %1 = llvm.xor %arg0, %arg0 : i64 + %2 = llvm.urem %1, %1 : i64 + %3 = llvm.and %1, %arg1 : i64 + %4 = llvm.select %0, %2, %3 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_47.mlir b/benchmarks/MLIR_single/6_function_47.mlir new file mode 100644 index 0000000..4e5aa5b --- /dev/null +++ b/benchmarks/MLIR_single/6_function_47.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.xor %0, %arg2 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_48.mlir b/benchmarks/MLIR_single/6_function_48.mlir new file mode 100644 index 0000000..35b65e8 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_48.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.srem %arg2, %arg2 : i64 + %1 = llvm.select %arg1, %0, %0 : i1, i64 + %2 = llvm.srem %arg2, %1 : i64 + %3 = llvm.select %arg0, %1, %2 : i1, i64 + %4 = llvm.trunc %3 : i64 to i1 + %5 = llvm.select %4, %1, %3 : i1, i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_49.mlir b/benchmarks/MLIR_single/6_function_49.mlir new file mode 100644 index 0000000..7157f69 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_49.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.urem %1, %arg0 : i64 + %3 = llvm.trunc %arg1 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.or disjoint %2, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_5.mlir b/benchmarks/MLIR_single/6_function_5.mlir new file mode 100644 index 0000000..cab7030 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_5.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i32) -> i1 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.select %1, %0, %0 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.icmp "uge" %0, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_50.mlir b/benchmarks/MLIR_single/6_function_50.mlir new file mode 100644 index 0000000..7280541 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_50.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i64 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.ashr %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.select %arg2, %1, %arg0 : i1, i64 + %5 = llvm.urem %3, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_51.mlir b/benchmarks/MLIR_single/6_function_51.mlir new file mode 100644 index 0000000..907f76c --- /dev/null +++ b/benchmarks/MLIR_single/6_function_51.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.trunc %arg1 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.urem %2, %arg2 : i64 + %4 = llvm.and %0, %3 : i64 + %5 = llvm.icmp "ult" %0, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_52.mlir b/benchmarks/MLIR_single/6_function_52.mlir new file mode 100644 index 0000000..2e50e4d --- /dev/null +++ b/benchmarks/MLIR_single/6_function_52.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.lshr %arg2, %arg0 : i64 + %1 = llvm.or disjoint %arg1, %0 : i64 + %2 = llvm.ashr %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_53.mlir b/benchmarks/MLIR_single/6_function_53.mlir new file mode 100644 index 0000000..85de6dc --- /dev/null +++ b/benchmarks/MLIR_single/6_function_53.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i64 { + %0 = llvm.zext %arg1 : i32 to i64 + %1 = llvm.xor %arg2, %arg2 : i64 + %2 = llvm.sdiv %0, %1 : i64 + %3 = llvm.urem %arg0, %2 : i64 + %4 = llvm.lshr %1, %0 : i64 + %5 = llvm.udiv %3, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_54.mlir b/benchmarks/MLIR_single/6_function_54.mlir new file mode 100644 index 0000000..e538977 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_54.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.lshr %arg0, %arg1 : i64 + %1 = llvm.trunc %arg0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.lshr %0, %2 : i64 + %4 = llvm.urem %3, %2 : i64 + %5 = llvm.icmp "ule" %3, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_55.mlir b/benchmarks/MLIR_single/6_function_55.mlir new file mode 100644 index 0000000..11e1843 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_55.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.sdiv exact %arg0, %arg0 : i64 + %1 = llvm.urem %arg0, %arg1 : i64 + %2 = llvm.srem %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_56.mlir b/benchmarks/MLIR_single/6_function_56.mlir new file mode 100644 index 0000000..2586a8d --- /dev/null +++ b/benchmarks/MLIR_single/6_function_56.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.ashr exact %arg1, %arg2 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.and %3, %1 : i64 + %5 = llvm.xor %arg0, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_57.mlir b/benchmarks/MLIR_single/6_function_57.mlir new file mode 100644 index 0000000..a56fdd4 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_57.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg1, %arg2 : i64 + %1 = llvm.ashr %arg0, %0 : i64 + %2 = llvm.srem %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_58.mlir b/benchmarks/MLIR_single/6_function_58.mlir new file mode 100644 index 0000000..1ea6893 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_58.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i32 { + %0 = llvm.icmp "ugt" %arg0, %arg0 : i64 + %1 = llvm.zext %arg1 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.select %0, %arg0, %3 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_59.mlir b/benchmarks/MLIR_single/6_function_59.mlir new file mode 100644 index 0000000..0cd921e --- /dev/null +++ b/benchmarks/MLIR_single/6_function_59.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.and %arg2, %arg2 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_6.mlir b/benchmarks/MLIR_single/6_function_6.mlir new file mode 100644 index 0000000..9aa9863 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_6.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg1, %arg0 : i64 + %1 = llvm.sdiv %0, %arg2 : i64 + %2 = llvm.lshr exact %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_60.mlir b/benchmarks/MLIR_single/6_function_60.mlir new file mode 100644 index 0000000..d6fc6a9 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_60.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.sdiv exact %arg0, %arg0 : i64 + %1 = llvm.trunc %arg0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.sdiv exact %0, %2 : i64 + %4 = llvm.lshr exact %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_61.mlir b/benchmarks/MLIR_single/6_function_61.mlir new file mode 100644 index 0000000..5839401 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_61.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.trunc %arg2 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.and %arg1, %3 : i64 + %5 = llvm.lshr %1, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_62.mlir b/benchmarks/MLIR_single/6_function_62.mlir new file mode 100644 index 0000000..4e0bab6 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_62.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.lshr exact %arg0, %arg1 : i64 + %1 = llvm.xor %0, %arg2 : i64 + %2 = llvm.ashr %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + %4 = llvm.select %3, %0, %arg2 : i1, i64 + %5 = llvm.urem %2, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_63.mlir b/benchmarks/MLIR_single/6_function_63.mlir new file mode 100644 index 0000000..2647833 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_63.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_64.mlir b/benchmarks/MLIR_single/6_function_64.mlir new file mode 100644 index 0000000..61402de --- /dev/null +++ b/benchmarks/MLIR_single/6_function_64.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.udiv %arg0, %arg0 : i64 + %2 = llvm.srem %1, %arg0 : i64 + %3 = llvm.ashr exact %arg2, %arg2 : i64 + %4 = llvm.srem %2, %3 : i64 + %5 = llvm.lshr %0, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_65.mlir b/benchmarks/MLIR_single/6_function_65.mlir new file mode 100644 index 0000000..f0415f8 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_65.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.lshr %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.sext %1 : i32 to i64 + %4 = llvm.sdiv exact %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_66.mlir b/benchmarks/MLIR_single/6_function_66.mlir new file mode 100644 index 0000000..d32cd31 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_66.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i32 { + %0 = llvm.select %arg1, %arg0, %arg2 : i1, i64 + %1 = llvm.sdiv %arg0, %0 : i64 + %2 = llvm.trunc %arg2 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.sdiv exact %1, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_67.mlir b/benchmarks/MLIR_single/6_function_67.mlir new file mode 100644 index 0000000..73f6316 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_67.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg1, %arg1 : i64 + %1 = llvm.lshr exact %arg1, %0 : i64 + %2 = llvm.and %arg0, %1 : i64 + %3 = llvm.xor %arg2, %2 : i64 + %4 = llvm.srem %arg1, %3 : i64 + %5 = llvm.ashr %arg0, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_68.mlir b/benchmarks/MLIR_single/6_function_68.mlir new file mode 100644 index 0000000..50ee8aa --- /dev/null +++ b/benchmarks/MLIR_single/6_function_68.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.ashr %0, %arg0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.udiv %1, %arg1 : i64 + %5 = llvm.lshr exact %3, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_69.mlir b/benchmarks/MLIR_single/6_function_69.mlir new file mode 100644 index 0000000..2c9ce72 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_69.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i32 { + %0 = llvm.icmp "eq" %arg0, %arg0 : i64 + %1 = llvm.srem %arg1, %arg2 : i64 + %2 = llvm.zext %arg3 : i32 to i64 + %3 = llvm.sdiv exact %2, %arg1 : i64 + %4 = llvm.select %0, %1, %3 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_7.mlir b/benchmarks/MLIR_single/6_function_7.mlir new file mode 100644 index 0000000..bae54c3 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_7.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.udiv %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.ashr %3, %arg1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_70.mlir b/benchmarks/MLIR_single/6_function_70.mlir new file mode 100644 index 0000000..a5efe97 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_70.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.urem %0, %0 : i64 + %2 = llvm.select %arg1, %arg2, %arg2 : i1, i64 + %3 = llvm.ashr exact %1, %2 : i64 + %4 = llvm.urem %2, %arg2 : i64 + %5 = llvm.and %3, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_71.mlir b/benchmarks/MLIR_single/6_function_71.mlir new file mode 100644 index 0000000..ef27629 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_71.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.udiv %arg1, %arg2 : i64 + %2 = llvm.ashr exact %0, %1 : i64 + %3 = llvm.lshr %2, %arg2 : i64 + %4 = llvm.ashr exact %3, %0 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_72.mlir b/benchmarks/MLIR_single/6_function_72.mlir new file mode 100644 index 0000000..d48a504 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_72.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.sdiv %arg2, %arg2 : i64 + %2 = llvm.udiv %arg0, %1 : i64 + %3 = llvm.sdiv %0, %2 : i64 + %4 = llvm.srem %3, %0 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_73.mlir b/benchmarks/MLIR_single/6_function_73.mlir new file mode 100644 index 0000000..62c2ddc --- /dev/null +++ b/benchmarks/MLIR_single/6_function_73.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.or disjoint %0, %0 : i64 + %2 = llvm.and %1, %0 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_74.mlir b/benchmarks/MLIR_single/6_function_74.mlir new file mode 100644 index 0000000..ec6a9c7 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_74.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg2, %arg2 : i64 + %1 = llvm.udiv %arg1, %0 : i64 + %2 = llvm.or disjoint %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_75.mlir b/benchmarks/MLIR_single/6_function_75.mlir new file mode 100644 index 0000000..1979b4b --- /dev/null +++ b/benchmarks/MLIR_single/6_function_75.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.ashr exact %arg0, %arg1 : i64 + %1 = llvm.lshr exact %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.sext %arg2 : i32 to i64 + %5 = llvm.ashr exact %3, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_76.mlir b/benchmarks/MLIR_single/6_function_76.mlir new file mode 100644 index 0000000..b6f1cff --- /dev/null +++ b/benchmarks/MLIR_single/6_function_76.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr %arg0, %arg0 : i64 + %1 = llvm.icmp "ult" %0, %arg0 : i64 + %2 = llvm.select %1, %arg1, %arg2 : i1, i64 + %3 = llvm.urem %arg2, %0 : i64 + %4 = llvm.sdiv exact %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_77.mlir b/benchmarks/MLIR_single/6_function_77.mlir new file mode 100644 index 0000000..f5aeb3c --- /dev/null +++ b/benchmarks/MLIR_single/6_function_77.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.lshr %arg0, %arg1 : i64 + %1 = llvm.trunc %arg2 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.udiv %arg1, %2 : i64 + %4 = llvm.ashr exact %0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_78.mlir b/benchmarks/MLIR_single/6_function_78.mlir new file mode 100644 index 0000000..46227b8 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_78.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or %arg0, %arg0 : i64 + %1 = llvm.and %0, %arg0 : i64 + %2 = llvm.trunc %arg1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.udiv %3, %arg2 : i64 + %5 = llvm.icmp "ne" %1, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_79.mlir b/benchmarks/MLIR_single/6_function_79.mlir new file mode 100644 index 0000000..5cb3f7a --- /dev/null +++ b/benchmarks/MLIR_single/6_function_79.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg1, %arg2 : i64 + %1 = llvm.select %arg0, %0, %arg2 : i1, i64 + %2 = llvm.select %arg0, %arg2, %0 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.icmp "slt" %1, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_8.mlir b/benchmarks/MLIR_single/6_function_8.mlir new file mode 100644 index 0000000..508f522 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_8.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.udiv %arg2, %arg2 : i64 + %1 = llvm.select %arg0, %arg1, %0 : i1, i64 + %2 = llvm.lshr %1, %arg2 : i64 + %3 = llvm.sdiv exact %arg2, %0 : i64 + %4 = llvm.srem %3, %arg2 : i64 + %5 = llvm.icmp "slt" %2, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_80.mlir b/benchmarks/MLIR_single/6_function_80.mlir new file mode 100644 index 0000000..e5e7827 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_80.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.zext %arg2 : i32 to i64 + %1 = llvm.select %arg0, %arg1, %0 : i1, i64 + %2 = llvm.and %arg1, %arg1 : i64 + %3 = llvm.xor %2, %1 : i64 + %4 = llvm.lshr exact %1, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_81.mlir b/benchmarks/MLIR_single/6_function_81.mlir new file mode 100644 index 0000000..77e3d5a --- /dev/null +++ b/benchmarks/MLIR_single/6_function_81.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg1, %arg2 : i64 + %1 = llvm.and %arg1, %0 : i64 + %2 = llvm.ashr exact %arg0, %1 : i64 + %3 = llvm.lshr exact %2, %1 : i64 + %4 = llvm.udiv %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_82.mlir b/benchmarks/MLIR_single/6_function_82.mlir new file mode 100644 index 0000000..1846487 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_82.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg2, %arg0 : i64 + %1 = llvm.icmp "ugt" %arg1, %0 : i64 + %2 = llvm.urem %arg2, %arg2 : i64 + %3 = llvm.select %1, %2, %arg2 : i1, i64 + %4 = llvm.udiv %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_83.mlir b/benchmarks/MLIR_single/6_function_83.mlir new file mode 100644 index 0000000..6a624c8 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_83.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.icmp "sgt" %0, %arg1 : i64 + %2 = llvm.ashr exact %arg1, %arg1 : i64 + %3 = llvm.srem %2, %arg2 : i64 + %4 = llvm.select %1, %arg1, %3 : i1, i64 + %5 = llvm.ashr exact %4, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_84.mlir b/benchmarks/MLIR_single/6_function_84.mlir new file mode 100644 index 0000000..9d4def0 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_84.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i64 { + %0 = llvm.lshr %arg1, %arg0 : i64 + %1 = llvm.sdiv exact %arg0, %0 : i64 + %2 = llvm.lshr exact %1, %arg2 : i64 + %3 = llvm.sext %arg3 : i32 to i64 + %4 = llvm.icmp "ule" %2, %3 : i64 + %5 = llvm.select %4, %2, %arg2 : i1, i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_85.mlir b/benchmarks/MLIR_single/6_function_85.mlir new file mode 100644 index 0000000..ca24167 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_85.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr %arg2, %arg1 : i64 + %1 = llvm.and %arg1, %0 : i64 + %2 = llvm.trunc %0 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.select %arg0, %1, %3 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_86.mlir b/benchmarks/MLIR_single/6_function_86.mlir new file mode 100644 index 0000000..e8aaebe --- /dev/null +++ b/benchmarks/MLIR_single/6_function_86.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i64 { + %0 = llvm.or %arg0, %arg0 : i64 + %1 = llvm.or disjoint %0, %arg1 : i64 + %2 = llvm.and %0, %1 : i64 + %3 = llvm.select %arg2, %2, %2 : i1, i64 + %4 = llvm.xor %arg0, %3 : i64 + %5 = llvm.or disjoint %2, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_87.mlir b/benchmarks/MLIR_single/6_function_87.mlir new file mode 100644 index 0000000..319edd6 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_87.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.or disjoint %arg0, %0 : i64 + %2 = llvm.or %arg1, %arg0 : i64 + %3 = llvm.udiv %1, %2 : i64 + %4 = llvm.urem %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_88.mlir b/benchmarks/MLIR_single/6_function_88.mlir new file mode 100644 index 0000000..380b3d7 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_88.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.select %arg1, %arg2, %arg0 : i1, i64 + %1 = llvm.or disjoint %0, %0 : i64 + %2 = llvm.icmp "slt" %arg0, %1 : i64 + %3 = llvm.select %2, %1, %0 : i1, i64 + %4 = llvm.srem %3, %arg0 : i64 + %5 = llvm.icmp "eq" %3, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_89.mlir b/benchmarks/MLIR_single/6_function_89.mlir new file mode 100644 index 0000000..f93bd80 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_89.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.srem %arg0, %arg0 : i64 + %3 = llvm.and %1, %2 : i64 + %4 = llvm.udiv %3, %1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_9.mlir b/benchmarks/MLIR_single/6_function_9.mlir new file mode 100644 index 0000000..79740ed --- /dev/null +++ b/benchmarks/MLIR_single/6_function_9.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i1, %arg3: i32) -> i32 { + %0 = llvm.sext %arg3 : i32 to i64 + %1 = llvm.select %arg2, %0, %0 : i1, i64 + %2 = llvm.select %arg0, %arg1, %1 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_90.mlir b/benchmarks/MLIR_single/6_function_90.mlir new file mode 100644 index 0000000..b9b043e --- /dev/null +++ b/benchmarks/MLIR_single/6_function_90.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.srem %arg0, %arg2 : i64 + %1 = llvm.lshr exact %0, %arg2 : i64 + %2 = llvm.select %arg1, %0, %1 : i1, i64 + %3 = llvm.and %1, %arg2 : i64 + %4 = llvm.or disjoint %2, %3 : i64 + %5 = llvm.icmp "ugt" %arg0, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_91.mlir b/benchmarks/MLIR_single/6_function_91.mlir new file mode 100644 index 0000000..5ce9120 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_91.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.udiv %arg0, %arg2 : i64 + %2 = llvm.sdiv %arg0, %1 : i64 + %3 = llvm.ashr %0, %2 : i64 + %4 = llvm.lshr exact %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_92.mlir b/benchmarks/MLIR_single/6_function_92.mlir new file mode 100644 index 0000000..e3cf89d --- /dev/null +++ b/benchmarks/MLIR_single/6_function_92.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.icmp "ugt" %arg0, %arg1 : i64 + %1 = llvm.srem %arg0, %arg2 : i64 + %2 = llvm.select %0, %arg2, %1 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_93.mlir b/benchmarks/MLIR_single/6_function_93.mlir new file mode 100644 index 0000000..25cd5df --- /dev/null +++ b/benchmarks/MLIR_single/6_function_93.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg2, %arg0 : i64 + %1 = llvm.lshr %arg0, %0 : i64 + %2 = llvm.srem %arg1, %1 : i64 + %3 = llvm.srem %2, %0 : i64 + %4 = llvm.lshr exact %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_94.mlir b/benchmarks/MLIR_single/6_function_94.mlir new file mode 100644 index 0000000..5c1f35f --- /dev/null +++ b/benchmarks/MLIR_single/6_function_94.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.select %arg0, %arg2, %arg2 : i1, i64 + %2 = llvm.urem %1, %1 : i64 + %3 = llvm.or %2, %1 : i64 + %4 = llvm.udiv %3, %0 : i64 + %5 = llvm.sdiv %0, %4 : i64 + return %5 : i64 +} + diff --git a/benchmarks/MLIR_single/6_function_95.mlir b/benchmarks/MLIR_single/6_function_95.mlir new file mode 100644 index 0000000..603694d --- /dev/null +++ b/benchmarks/MLIR_single/6_function_95.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.srem %arg1, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.urem %0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_96.mlir b/benchmarks/MLIR_single/6_function_96.mlir new file mode 100644 index 0000000..4bba951 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_96.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i1 + %1 = llvm.lshr %arg1, %arg0 : i64 + %2 = llvm.trunc %arg2 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.select %0, %1, %3 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_97.mlir b/benchmarks/MLIR_single/6_function_97.mlir new file mode 100644 index 0000000..da766ab --- /dev/null +++ b/benchmarks/MLIR_single/6_function_97.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i1 + %3 = llvm.select %2, %1, %1 : i1, i64 + %4 = llvm.and %1, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + return %5 : i32 +} + diff --git a/benchmarks/MLIR_single/6_function_98.mlir b/benchmarks/MLIR_single/6_function_98.mlir new file mode 100644 index 0000000..f66e686 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_98.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64) -> i1 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.and %0, %arg0 : i64 + %2 = llvm.or %arg0, %1 : i64 + %3 = llvm.trunc %arg0 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.icmp "ne" %2, %4 : i64 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/6_function_99.mlir b/benchmarks/MLIR_single/6_function_99.mlir new file mode 100644 index 0000000..1af7a85 --- /dev/null +++ b/benchmarks/MLIR_single/6_function_99.mlir @@ -0,0 +1,10 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i1 { + %0 = llvm.icmp "eq" %arg2, %arg0 : i64 + %1 = llvm.sext %arg3 : i32 to i64 + %2 = llvm.select %0, %1, %arg0 : i1, i64 + %3 = llvm.urem %arg1, %2 : i64 + %4 = llvm.and %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i1 + return %5 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_0.mlir b/benchmarks/MLIR_single/7_function_0.mlir new file mode 100644 index 0000000..406e3aa --- /dev/null +++ b/benchmarks/MLIR_single/7_function_0.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.trunc %arg2 : i64 to i1 + %2 = llvm.select %1, %arg2, %0 : i1, i64 + %3 = llvm.or disjoint %0, %2 : i64 + %4 = llvm.select %1, %arg1, %0 : i1, i64 + %5 = llvm.sdiv %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_1.mlir b/benchmarks/MLIR_single/7_function_1.mlir new file mode 100644 index 0000000..c79bc20 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_1.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.zext %arg2 : i32 to i64 + %2 = llvm.sdiv %1, %arg0 : i64 + %3 = llvm.lshr exact %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_10.mlir b/benchmarks/MLIR_single/7_function_10.mlir new file mode 100644 index 0000000..5ff113b --- /dev/null +++ b/benchmarks/MLIR_single/7_function_10.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.lshr exact %0, %0 : i64 + %2 = llvm.udiv %1, %1 : i64 + %3 = llvm.srem %arg2, %2 : i64 + %4 = llvm.urem %arg1, %3 : i64 + %5 = llvm.urem %1, %4 : i64 + %6 = llvm.icmp "sle" %2, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_11.mlir b/benchmarks/MLIR_single/7_function_11.mlir new file mode 100644 index 0000000..7732a38 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_11.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.xor %0, %arg1 : i64 + %2 = llvm.lshr exact %arg2, %0 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.sdiv exact %1, %4 : i64 + %6 = llvm.srem %0, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_12.mlir b/benchmarks/MLIR_single/7_function_12.mlir new file mode 100644 index 0000000..56bd1d6 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_12.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.ashr exact %1, %arg0 : i64 + %3 = llvm.or %arg2, %1 : i64 + %4 = llvm.sdiv exact %1, %3 : i64 + %5 = llvm.udiv %arg1, %4 : i64 + %6 = llvm.icmp "sle" %2, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_13.mlir b/benchmarks/MLIR_single/7_function_13.mlir new file mode 100644 index 0000000..0b1e4f8 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_13.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.udiv %0, %arg1 : i64 + %2 = llvm.icmp "ule" %1, %arg2 : i64 + %3 = llvm.select %2, %1, %arg0 : i1, i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_14.mlir b/benchmarks/MLIR_single/7_function_14.mlir new file mode 100644 index 0000000..6e4e5df --- /dev/null +++ b/benchmarks/MLIR_single/7_function_14.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i1) -> i32 { + %0 = llvm.sext %arg1 : i32 to i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.select %arg2, %0, %0 : i1, i64 + %5 = llvm.or disjoint %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_15.mlir b/benchmarks/MLIR_single/7_function_15.mlir new file mode 100644 index 0000000..ea17079 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_15.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i32 { + %0 = llvm.sext %arg1 : i32 to i64 + %1 = llvm.icmp "ule" %arg0, %0 : i64 + %2 = llvm.srem %arg2, %0 : i64 + %3 = llvm.sdiv %arg2, %2 : i64 + %4 = llvm.lshr %arg0, %3 : i64 + %5 = llvm.select %1, %3, %4 : i1, i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_16.mlir b/benchmarks/MLIR_single/7_function_16.mlir new file mode 100644 index 0000000..62eac28 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_16.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64, %arg3: i32) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.sdiv %0, %arg2 : i64 + %2 = llvm.zext %arg3 : i32 to i64 + %3 = llvm.ashr %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_17.mlir b/benchmarks/MLIR_single/7_function_17.mlir new file mode 100644 index 0000000..0a05029 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_17.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg2, %arg0 : i64 + %1 = llvm.or disjoint %arg2, %0 : i64 + %2 = llvm.xor %1, %arg2 : i64 + %3 = llvm.and %2, %2 : i64 + %4 = llvm.xor %arg2, %3 : i64 + %5 = llvm.xor %arg1, %4 : i64 + %6 = llvm.icmp "ne" %arg0, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_18.mlir b/benchmarks/MLIR_single/7_function_18.mlir new file mode 100644 index 0000000..f7b41ef --- /dev/null +++ b/benchmarks/MLIR_single/7_function_18.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.udiv %0, %0 : i64 + %2 = llvm.sdiv exact %arg0, %1 : i64 + %3 = llvm.or %0, %2 : i64 + %4 = llvm.ashr %arg0, %3 : i64 + %5 = llvm.urem %arg1, %3 : i64 + %6 = llvm.and %4, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_19.mlir b/benchmarks/MLIR_single/7_function_19.mlir new file mode 100644 index 0000000..98e90b5 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_19.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.and %arg1, %arg2 : i64 + %1 = llvm.lshr %arg0, %0 : i64 + %2 = llvm.urem %1, %arg1 : i64 + %3 = llvm.xor %2, %2 : i64 + %4 = llvm.xor %3, %0 : i64 + %5 = llvm.urem %4, %arg1 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_2.mlir b/benchmarks/MLIR_single/7_function_2.mlir new file mode 100644 index 0000000..781d2c5 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_2.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.ashr exact %arg0, %arg2 : i64 + %2 = llvm.urem %1, %arg1 : i64 + %3 = llvm.sdiv %2, %arg1 : i64 + %4 = llvm.lshr %2, %3 : i64 + %5 = llvm.xor %0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_20.mlir b/benchmarks/MLIR_single/7_function_20.mlir new file mode 100644 index 0000000..d85baa9 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_20.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.icmp "sge" %0, %arg1 : i64 + %2 = llvm.urem %arg2, %arg1 : i64 + %3 = llvm.srem %0, %2 : i64 + %4 = llvm.select %1, %arg0, %3 : i1, i64 + %5 = llvm.sdiv exact %0, %4 : i64 + %6 = llvm.lshr exact %arg0, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_21.mlir b/benchmarks/MLIR_single/7_function_21.mlir new file mode 100644 index 0000000..0211ab4 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_21.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.udiv %arg1, %arg2 : i64 + %2 = llvm.icmp "uge" %1, %arg1 : i64 + %3 = llvm.select %2, %arg1, %1 : i1, i64 + %4 = llvm.and %0, %3 : i64 + %5 = llvm.xor %3, %4 : i64 + %6 = llvm.udiv %4, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_22.mlir b/benchmarks/MLIR_single/7_function_22.mlir new file mode 100644 index 0000000..9c69983 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_22.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr %arg1, %arg2 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.lshr %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_23.mlir b/benchmarks/MLIR_single/7_function_23.mlir new file mode 100644 index 0000000..802ed03 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_23.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.and %arg1, %arg2 : i64 + %2 = llvm.sdiv exact %arg0, %1 : i64 + %3 = llvm.udiv %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_24.mlir b/benchmarks/MLIR_single/7_function_24.mlir new file mode 100644 index 0000000..c837db7 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_24.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.lshr exact %arg0, %0 : i64 + %2 = llvm.or %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.srem %2, %0 : i64 + %6 = llvm.urem %4, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_25.mlir b/benchmarks/MLIR_single/7_function_25.mlir new file mode 100644 index 0000000..b3f076e --- /dev/null +++ b/benchmarks/MLIR_single/7_function_25.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i64 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.select %1, %arg2, %0 : i1, i64 + %3 = llvm.trunc %2 : i64 to i1 + %4 = llvm.zext %arg3 : i32 to i64 + %5 = llvm.urem %2, %0 : i64 + %6 = llvm.select %3, %4, %5 : i1, i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_26.mlir b/benchmarks/MLIR_single/7_function_26.mlir new file mode 100644 index 0000000..7ce392b --- /dev/null +++ b/benchmarks/MLIR_single/7_function_26.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr exact %arg0, %arg0 : i64 + %1 = llvm.and %arg1, %0 : i64 + %2 = llvm.xor %0, %1 : i64 + %3 = llvm.urem %arg2, %0 : i64 + %4 = llvm.sdiv exact %3, %0 : i64 + %5 = llvm.ashr exact %2, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_27.mlir b/benchmarks/MLIR_single/7_function_27.mlir new file mode 100644 index 0000000..9fd2cb0 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_27.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.xor %1, %1 : i64 + %3 = llvm.select %arg1, %2, %arg2 : i1, i64 + %4 = llvm.icmp "slt" %2, %3 : i64 + %5 = llvm.select %4, %arg0, %1 : i1, i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_28.mlir b/benchmarks/MLIR_single/7_function_28.mlir new file mode 100644 index 0000000..282b1f4 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_28.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i32 { + %0 = llvm.zext %arg2 : i32 to i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.srem %2, %2 : i64 + %4 = llvm.srem %arg1, %3 : i64 + %5 = llvm.udiv %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_29.mlir b/benchmarks/MLIR_single/7_function_29.mlir new file mode 100644 index 0000000..71000ab --- /dev/null +++ b/benchmarks/MLIR_single/7_function_29.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i1 + %1 = llvm.select %0, %arg1, %arg1 : i1, i64 + %2 = llvm.sext %arg3 : i32 to i64 + %3 = llvm.xor %arg0, %2 : i64 + %4 = llvm.ashr exact %arg2, %3 : i64 + %5 = llvm.and %1, %4 : i64 + %6 = llvm.and %5, %arg0 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_3.mlir b/benchmarks/MLIR_single/7_function_3.mlir new file mode 100644 index 0000000..6a08611 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_3.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.or %0, %arg1 : i64 + %2 = llvm.zext %arg2 : i32 to i64 + %3 = llvm.srem %1, %2 : i64 + %4 = llvm.sext %arg2 : i32 to i64 + %5 = llvm.ashr %4, %4 : i64 + %6 = llvm.udiv %3, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_30.mlir b/benchmarks/MLIR_single/7_function_30.mlir new file mode 100644 index 0000000..1497442 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_30.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64) -> i1 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.select %arg0, %1, %1 : i1, i64 + %3 = llvm.lshr exact %1, %arg1 : i64 + %4 = llvm.and %2, %3 : i64 + %5 = llvm.urem %2, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_31.mlir b/benchmarks/MLIR_single/7_function_31.mlir new file mode 100644 index 0000000..a7b1fd8 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_31.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.select %arg1, %arg2, %arg0 : i1, i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.and %4, %2 : i64 + %6 = llvm.icmp "ult" %arg0, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_32.mlir b/benchmarks/MLIR_single/7_function_32.mlir new file mode 100644 index 0000000..5047672 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_32.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.ashr %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.xor %arg1, %arg2 : i64 + %6 = llvm.xor %4, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_33.mlir b/benchmarks/MLIR_single/7_function_33.mlir new file mode 100644 index 0000000..a8256fc --- /dev/null +++ b/benchmarks/MLIR_single/7_function_33.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.xor %arg1, %arg1 : i64 + %2 = llvm.or disjoint %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.srem %4, %arg0 : i64 + %6 = llvm.icmp "slt" %arg0, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_34.mlir b/benchmarks/MLIR_single/7_function_34.mlir new file mode 100644 index 0000000..1942998 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_34.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg2 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.xor %1, %arg2 : i64 + %3 = llvm.select %arg0, %arg1, %2 : i1, i64 + %4 = llvm.lshr exact %3, %1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_35.mlir b/benchmarks/MLIR_single/7_function_35.mlir new file mode 100644 index 0000000..2da3c6b --- /dev/null +++ b/benchmarks/MLIR_single/7_function_35.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.zext %0 : i32 to i64 + %3 = llvm.ashr exact %1, %2 : i64 + %4 = llvm.lshr %3, %arg1 : i64 + %5 = llvm.and %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_36.mlir b/benchmarks/MLIR_single/7_function_36.mlir new file mode 100644 index 0000000..b6106d6 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_36.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.ashr exact %arg1, %arg2 : i64 + %1 = llvm.select %arg0, %0, %arg2 : i1, i64 + %2 = llvm.icmp "ule" %arg1, %0 : i64 + %3 = llvm.or %1, %1 : i64 + %4 = llvm.select %2, %3, %0 : i1, i64 + %5 = llvm.udiv %4, %3 : i64 + %6 = llvm.lshr exact %1, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_37.mlir b/benchmarks/MLIR_single/7_function_37.mlir new file mode 100644 index 0000000..63e814e --- /dev/null +++ b/benchmarks/MLIR_single/7_function_37.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i32 { + %0 = llvm.or disjoint %arg0, %arg0 : i64 + %1 = llvm.select %arg1, %arg2, %0 : i1, i64 + %2 = llvm.lshr %1, %arg0 : i64 + %3 = llvm.srem %arg0, %2 : i64 + %4 = llvm.and %3, %1 : i64 + %5 = llvm.xor %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_38.mlir b/benchmarks/MLIR_single/7_function_38.mlir new file mode 100644 index 0000000..bb87004 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_38.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.urem %1, %0 : i64 + %3 = llvm.icmp "eq" %2, %arg2 : i64 + %4 = llvm.select %3, %0, %1 : i1, i64 + %5 = llvm.or %4, %arg1 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_39.mlir b/benchmarks/MLIR_single/7_function_39.mlir new file mode 100644 index 0000000..c4aa40e --- /dev/null +++ b/benchmarks/MLIR_single/7_function_39.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.urem %2, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_4.mlir b/benchmarks/MLIR_single/7_function_4.mlir new file mode 100644 index 0000000..07d12f1 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_4.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv %arg0, %arg1 : i64 + %1 = llvm.lshr exact %0, %0 : i64 + %2 = llvm.udiv %1, %arg1 : i64 + %3 = llvm.and %arg2, %2 : i64 + %4 = llvm.ashr %arg2, %3 : i64 + %5 = llvm.and %arg1, %4 : i64 + %6 = llvm.icmp "slt" %arg0, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_40.mlir b/benchmarks/MLIR_single/7_function_40.mlir new file mode 100644 index 0000000..061a2f9 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_40.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.lshr %1, %arg1 : i64 + %3 = llvm.sext %arg2 : i32 to i64 + %4 = llvm.srem %3, %arg1 : i64 + %5 = llvm.lshr exact %4, %3 : i64 + %6 = llvm.ashr exact %2, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_41.mlir b/benchmarks/MLIR_single/7_function_41.mlir new file mode 100644 index 0000000..6bf7f45 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_41.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.and %arg1, %0 : i64 + %2 = llvm.lshr %arg2, %1 : i64 + %3 = llvm.lshr %0, %2 : i64 + %4 = llvm.and %0, %arg2 : i64 + %5 = llvm.udiv %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_42.mlir b/benchmarks/MLIR_single/7_function_42.mlir new file mode 100644 index 0000000..7738fbc --- /dev/null +++ b/benchmarks/MLIR_single/7_function_42.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.ashr %arg1, %arg2 : i64 + %2 = llvm.ashr %0, %1 : i64 + %3 = llvm.xor %arg1, %arg0 : i64 + %4 = llvm.ashr exact %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_43.mlir b/benchmarks/MLIR_single/7_function_43.mlir new file mode 100644 index 0000000..d541763 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_43.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr %arg2, %arg1 : i64 + %1 = llvm.select %arg0, %arg1, %0 : i1, i64 + %2 = llvm.select %arg0, %0, %arg2 : i1, i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.urem %1, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_44.mlir b/benchmarks/MLIR_single/7_function_44.mlir new file mode 100644 index 0000000..bade851 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_44.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i32 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.urem %0, %arg1 : i64 + %2 = llvm.select %arg2, %arg0, %0 : i1, i64 + %3 = llvm.xor %2, %1 : i64 + %4 = llvm.sdiv %3, %2 : i64 + %5 = llvm.xor %1, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_45.mlir b/benchmarks/MLIR_single/7_function_45.mlir new file mode 100644 index 0000000..8c51a0e --- /dev/null +++ b/benchmarks/MLIR_single/7_function_45.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg2, %arg1 : i64 + %1 = llvm.xor %arg1, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.and %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_46.mlir b/benchmarks/MLIR_single/7_function_46.mlir new file mode 100644 index 0000000..19c0185 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_46.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.icmp "sge" %arg0, %arg0 : i64 + %1 = llvm.ashr exact %arg0, %arg0 : i64 + %2 = llvm.urem %arg0, %arg2 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.ashr exact %arg1, %4 : i64 + %6 = llvm.select %0, %1, %5 : i1, i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_47.mlir b/benchmarks/MLIR_single/7_function_47.mlir new file mode 100644 index 0000000..bb80f54 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_47.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.ashr %arg1, %arg2 : i64 + %3 = llvm.xor %1, %2 : i64 + %4 = llvm.select %arg3, %arg0, %1 : i1, i64 + %5 = llvm.xor %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_48.mlir b/benchmarks/MLIR_single/7_function_48.mlir new file mode 100644 index 0000000..a0af16c --- /dev/null +++ b/benchmarks/MLIR_single/7_function_48.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.udiv %0, %arg1 : i64 + %2 = llvm.srem %arg2, %1 : i64 + %3 = llvm.xor %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_49.mlir b/benchmarks/MLIR_single/7_function_49.mlir new file mode 100644 index 0000000..f7a1a9e --- /dev/null +++ b/benchmarks/MLIR_single/7_function_49.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.sdiv %arg0, %0 : i64 + %2 = llvm.ashr %arg0, %1 : i64 + %3 = llvm.urem %2, %arg2 : i64 + %4 = llvm.lshr exact %2, %1 : i64 + %5 = llvm.or disjoint %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_5.mlir b/benchmarks/MLIR_single/7_function_5.mlir new file mode 100644 index 0000000..3abdcde --- /dev/null +++ b/benchmarks/MLIR_single/7_function_5.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.and %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_50.mlir b/benchmarks/MLIR_single/7_function_50.mlir new file mode 100644 index 0000000..0bbad8a --- /dev/null +++ b/benchmarks/MLIR_single/7_function_50.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr exact %arg2, %arg0 : i64 + %1 = llvm.lshr exact %0, %arg2 : i64 + %2 = llvm.udiv %arg1, %1 : i64 + %3 = llvm.sdiv %arg0, %2 : i64 + %4 = llvm.udiv %2, %arg1 : i64 + %5 = llvm.lshr %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_51.mlir b/benchmarks/MLIR_single/7_function_51.mlir new file mode 100644 index 0000000..fdb88e6 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_51.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) -> i1 { + %0 = llvm.or %arg0, %arg1 : i64 + %1 = llvm.select %arg3, %arg1, %arg2 : i1, i64 + %2 = llvm.select %arg3, %1, %arg1 : i1, i64 + %3 = llvm.udiv %2, %1 : i64 + %4 = llvm.xor %arg2, %3 : i64 + %5 = llvm.udiv %arg2, %4 : i64 + %6 = llvm.icmp "uge" %0, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_52.mlir b/benchmarks/MLIR_single/7_function_52.mlir new file mode 100644 index 0000000..76b927b --- /dev/null +++ b/benchmarks/MLIR_single/7_function_52.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.srem %1, %arg2 : i64 + %3 = llvm.or %arg1, %2 : i64 + %4 = llvm.sext %0 : i32 to i64 + %5 = llvm.and %3, %4 : i64 + %6 = llvm.udiv %1, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_53.mlir b/benchmarks/MLIR_single/7_function_53.mlir new file mode 100644 index 0000000..a197175 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_53.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.srem %arg2, %arg2 : i64 + %3 = llvm.urem %2, %arg1 : i64 + %4 = llvm.udiv %arg1, %3 : i64 + %5 = llvm.or %1, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_54.mlir b/benchmarks/MLIR_single/7_function_54.mlir new file mode 100644 index 0000000..6698881 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_54.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg2 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.lshr exact %arg1, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.urem %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_55.mlir b/benchmarks/MLIR_single/7_function_55.mlir new file mode 100644 index 0000000..e7e1914 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_55.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_56.mlir b/benchmarks/MLIR_single/7_function_56.mlir new file mode 100644 index 0000000..3c7a7a6 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_56.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i32, %arg1: i64) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.and %0, %0 : i64 + %2 = llvm.trunc %arg1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.or %1, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_57.mlir b/benchmarks/MLIR_single/7_function_57.mlir new file mode 100644 index 0000000..2460693 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_57.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr exact %arg1, %arg0 : i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.or %arg2, %arg2 : i64 + %3 = llvm.and %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_58.mlir b/benchmarks/MLIR_single/7_function_58.mlir new file mode 100644 index 0000000..35b218d --- /dev/null +++ b/benchmarks/MLIR_single/7_function_58.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.and %arg2, %arg1 : i64 + %2 = llvm.urem %1, %arg1 : i64 + %3 = llvm.srem %0, %2 : i64 + %4 = llvm.srem %3, %2 : i64 + %5 = llvm.and %2, %4 : i64 + %6 = llvm.icmp "sge" %3, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_59.mlir b/benchmarks/MLIR_single/7_function_59.mlir new file mode 100644 index 0000000..81dd197 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_59.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.lshr %arg1, %0 : i64 + %2 = llvm.ashr exact %0, %1 : i64 + %3 = llvm.and %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_6.mlir b/benchmarks/MLIR_single/7_function_6.mlir new file mode 100644 index 0000000..0675597 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_6.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.lshr %arg0, %arg0 : i64 + %1 = llvm.or disjoint %0, %arg0 : i64 + %2 = llvm.xor %arg1, %arg2 : i64 + %3 = llvm.udiv %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_60.mlir b/benchmarks/MLIR_single/7_function_60.mlir new file mode 100644 index 0000000..c407925 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_60.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.sdiv %arg1, %arg1 : i64 + %1 = llvm.or %0, %arg2 : i64 + %2 = llvm.or %1, %arg0 : i64 + %3 = llvm.sdiv exact %arg0, %2 : i64 + %4 = llvm.xor %3, %arg0 : i64 + %5 = llvm.srem %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_61.mlir b/benchmarks/MLIR_single/7_function_61.mlir new file mode 100644 index 0000000..0599bba --- /dev/null +++ b/benchmarks/MLIR_single/7_function_61.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.icmp "sgt" %0, %arg1 : i64 + %2 = llvm.zext %arg2 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.select %1, %4, %arg1 : i1, i64 + %6 = llvm.icmp "uge" %5, %4 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_62.mlir b/benchmarks/MLIR_single/7_function_62.mlir new file mode 100644 index 0000000..073f3f3 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_62.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.xor %arg1, %arg2 : i64 + %3 = llvm.or disjoint %1, %2 : i64 + %4 = llvm.xor %arg0, %3 : i64 + %5 = llvm.urem %4, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_63.mlir b/benchmarks/MLIR_single/7_function_63.mlir new file mode 100644 index 0000000..7600b0b --- /dev/null +++ b/benchmarks/MLIR_single/7_function_63.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.lshr %arg2, %arg2 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.sdiv %4, %arg0 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_64.mlir b/benchmarks/MLIR_single/7_function_64.mlir new file mode 100644 index 0000000..a22be84 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_64.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg2 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.ashr exact %arg1, %1 : i64 + %3 = llvm.xor %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_65.mlir b/benchmarks/MLIR_single/7_function_65.mlir new file mode 100644 index 0000000..85472d9 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_65.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.and %0, %arg1 : i64 + %2 = llvm.and %1, %arg1 : i64 + %3 = llvm.sdiv %1, %2 : i64 + %4 = llvm.ashr %1, %3 : i64 + %5 = llvm.srem %4, %arg2 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_66.mlir b/benchmarks/MLIR_single/7_function_66.mlir new file mode 100644 index 0000000..368114e --- /dev/null +++ b/benchmarks/MLIR_single/7_function_66.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.urem %1, %arg1 : i64 + %3 = llvm.icmp "ule" %1, %2 : i64 + %4 = llvm.udiv %arg1, %arg2 : i64 + %5 = llvm.urem %4, %arg1 : i64 + %6 = llvm.select %3, %arg1, %5 : i1, i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_67.mlir b/benchmarks/MLIR_single/7_function_67.mlir new file mode 100644 index 0000000..7e598ee --- /dev/null +++ b/benchmarks/MLIR_single/7_function_67.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg1, %arg2 : i64 + %1 = llvm.xor %0, %0 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.urem %2, %0 : i64 + %4 = llvm.udiv %arg0, %3 : i64 + %5 = llvm.ashr %4, %2 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_68.mlir b/benchmarks/MLIR_single/7_function_68.mlir new file mode 100644 index 0000000..e30faf2 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_68.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.icmp "slt" %arg0, %arg0 : i64 + %1 = llvm.select %0, %arg1, %arg0 : i1, i64 + %2 = llvm.srem %1, %arg0 : i64 + %3 = llvm.and %2, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + %5 = llvm.xor %arg1, %arg2 : i64 + %6 = llvm.select %4, %3, %5 : i1, i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_69.mlir b/benchmarks/MLIR_single/7_function_69.mlir new file mode 100644 index 0000000..b63d479 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_69.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.select %arg0, %arg1, %arg2 : i1, i64 + %1 = llvm.and %arg1, %arg2 : i64 + %2 = llvm.ashr %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.or %4, %arg1 : i64 + %6 = llvm.or %2, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_7.mlir b/benchmarks/MLIR_single/7_function_7.mlir new file mode 100644 index 0000000..2d76f66 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_7.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i1 { + %0 = llvm.lshr exact %arg2, %arg0 : i64 + %1 = llvm.and %arg1, %0 : i64 + %2 = llvm.lshr exact %arg0, %1 : i64 + %3 = llvm.urem %2, %1 : i64 + %4 = llvm.sext %arg3 : i32 to i64 + %5 = llvm.or %4, %3 : i64 + %6 = llvm.icmp "ult" %3, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_70.mlir b/benchmarks/MLIR_single/7_function_70.mlir new file mode 100644 index 0000000..845715e --- /dev/null +++ b/benchmarks/MLIR_single/7_function_70.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.sdiv exact %arg0, %0 : i64 + %2 = llvm.srem %arg0, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.xor %1, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_71.mlir b/benchmarks/MLIR_single/7_function_71.mlir new file mode 100644 index 0000000..35dd745 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_71.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.srem %arg1, %arg2 : i64 + %2 = llvm.udiv %arg0, %1 : i64 + %3 = llvm.or %2, %arg2 : i64 + %4 = llvm.xor %0, %3 : i64 + %5 = llvm.xor %arg2, %arg1 : i64 + %6 = llvm.srem %4, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_72.mlir b/benchmarks/MLIR_single/7_function_72.mlir new file mode 100644 index 0000000..cab0be0 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_72.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr exact %arg2, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.sdiv %arg1, %2 : i64 + %4 = llvm.udiv %arg0, %3 : i64 + %5 = llvm.srem %4, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_73.mlir b/benchmarks/MLIR_single/7_function_73.mlir new file mode 100644 index 0000000..739a8a6 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_73.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i32, %arg1: i64) -> i32 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.and %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_74.mlir b/benchmarks/MLIR_single/7_function_74.mlir new file mode 100644 index 0000000..5822945 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_74.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i32 { + %0 = llvm.zext %arg2 : i32 to i64 + %1 = llvm.lshr exact %arg1, %0 : i64 + %2 = llvm.udiv %1, %arg0 : i64 + %3 = llvm.xor %2, %1 : i64 + %4 = llvm.xor %arg0, %3 : i64 + %5 = llvm.xor %4, %arg1 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_75.mlir b/benchmarks/MLIR_single/7_function_75.mlir new file mode 100644 index 0000000..51e8b0a --- /dev/null +++ b/benchmarks/MLIR_single/7_function_75.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.udiv %arg0, %arg0 : i64 + %3 = llvm.srem %0, %arg0 : i64 + %4 = llvm.xor %2, %3 : i64 + %5 = llvm.select %1, %arg2, %4 : i1, i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_76.mlir b/benchmarks/MLIR_single/7_function_76.mlir new file mode 100644 index 0000000..f8e7cc0 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_76.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.udiv %0, %0 : i64 + %2 = llvm.udiv %1, %arg2 : i64 + %3 = llvm.or %2, %arg0 : i64 + %4 = llvm.select %arg3, %0, %arg1 : i1, i64 + %5 = llvm.or %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_77.mlir b/benchmarks/MLIR_single/7_function_77.mlir new file mode 100644 index 0000000..d1d6c35 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_77.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) -> i64 { + %0 = llvm.sdiv exact %arg0, %arg0 : i64 + %1 = llvm.ashr %0, %arg0 : i64 + %2 = llvm.xor %1, %arg1 : i64 + %3 = llvm.and %2, %arg2 : i64 + %4 = llvm.select %arg3, %1, %3 : i1, i64 + %5 = llvm.udiv %4, %0 : i64 + %6 = llvm.udiv %3, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_78.mlir b/benchmarks/MLIR_single/7_function_78.mlir new file mode 100644 index 0000000..e189f75 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_78.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.sext %arg1 : i32 to i64 + %2 = llvm.udiv %1, %0 : i64 + %3 = llvm.trunc %1 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.or %2, %4 : i64 + %6 = llvm.icmp "ule" %0, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_79.mlir b/benchmarks/MLIR_single/7_function_79.mlir new file mode 100644 index 0000000..28d39ea --- /dev/null +++ b/benchmarks/MLIR_single/7_function_79.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.or disjoint %arg0, %arg0 : i64 + %1 = llvm.select %arg1, %arg2, %0 : i1, i64 + %2 = llvm.srem %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.or %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_8.mlir b/benchmarks/MLIR_single/7_function_8.mlir new file mode 100644 index 0000000..b3481c1 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_8.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.icmp "ule" %arg1, %arg1 : i64 + %1 = llvm.select %0, %arg2, %arg1 : i1, i64 + %2 = llvm.select %arg0, %arg1, %1 : i1, i64 + %3 = llvm.or disjoint %arg2, %arg1 : i64 + %4 = llvm.urem %1, %3 : i64 + %5 = llvm.or %4, %3 : i64 + %6 = llvm.icmp "ne" %2, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_80.mlir b/benchmarks/MLIR_single/7_function_80.mlir new file mode 100644 index 0000000..86f7a73 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_80.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.icmp "eq" %arg0, %arg1 : i64 + %1 = llvm.udiv %arg2, %arg1 : i64 + %2 = llvm.select %0, %arg2, %1 : i1, i64 + %3 = llvm.or %arg0, %arg2 : i64 + %4 = llvm.icmp "ult" %arg1, %3 : i64 + %5 = llvm.select %4, %2, %arg0 : i1, i64 + %6 = llvm.ashr exact %2, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_81.mlir b/benchmarks/MLIR_single/7_function_81.mlir new file mode 100644 index 0000000..d6a7556 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_81.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.lshr exact %0, %arg1 : i64 + %2 = llvm.lshr exact %0, %1 : i64 + %3 = llvm.zext %arg0 : i32 to i64 + %4 = llvm.xor %arg2, %3 : i64 + %5 = llvm.srem %1, %4 : i64 + %6 = llvm.or disjoint %2, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_82.mlir b/benchmarks/MLIR_single/7_function_82.mlir new file mode 100644 index 0000000..a8475ef --- /dev/null +++ b/benchmarks/MLIR_single/7_function_82.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg2 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.ashr %arg1, %3 : i64 + %5 = llvm.or %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_83.mlir b/benchmarks/MLIR_single/7_function_83.mlir new file mode 100644 index 0000000..9498c4c --- /dev/null +++ b/benchmarks/MLIR_single/7_function_83.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.sdiv %4, %arg2 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_84.mlir b/benchmarks/MLIR_single/7_function_84.mlir new file mode 100644 index 0000000..6841c94 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_84.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.or disjoint %0, %arg0 : i64 + %2 = llvm.and %arg2, %1 : i64 + %3 = llvm.xor %2, %arg1 : i64 + %4 = llvm.and %0, %3 : i64 + %5 = llvm.srem %4, %0 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_85.mlir b/benchmarks/MLIR_single/7_function_85.mlir new file mode 100644 index 0000000..a47b3a4 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_85.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.select %arg0, %arg1, %arg1 : i1, i64 + %1 = llvm.xor %0, %arg2 : i64 + %2 = llvm.xor %1, %1 : i64 + %3 = llvm.and %0, %2 : i64 + %4 = llvm.xor %0, %arg2 : i64 + %5 = llvm.urem %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_86.mlir b/benchmarks/MLIR_single/7_function_86.mlir new file mode 100644 index 0000000..9d06174 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_86.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i32 { + %0 = llvm.sext %arg1 : i32 to i64 + %1 = llvm.or disjoint %0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.srem %3, %arg2 : i64 + %5 = llvm.udiv %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_87.mlir b/benchmarks/MLIR_single/7_function_87.mlir new file mode 100644 index 0000000..5b151b5 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_87.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i1 { + %0 = llvm.select %arg1, %arg2, %arg0 : i1, i64 + %1 = llvm.urem %0, %0 : i64 + %2 = llvm.udiv %arg0, %1 : i64 + %3 = llvm.ashr exact %0, %1 : i64 + %4 = llvm.xor %3, %arg2 : i64 + %5 = llvm.lshr exact %3, %4 : i64 + %6 = llvm.icmp "slt" %2, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_88.mlir b/benchmarks/MLIR_single/7_function_88.mlir new file mode 100644 index 0000000..7a64235 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_88.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i32) -> i32 { + %0 = llvm.sext %arg2 : i32 to i64 + %1 = llvm.select %arg1, %arg0, %0 : i1, i64 + %2 = llvm.srem %arg0, %1 : i64 + %3 = llvm.or %2, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_89.mlir b/benchmarks/MLIR_single/7_function_89.mlir new file mode 100644 index 0000000..32f8d27 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_89.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i32 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.sext %arg2 : i32 to i64 + %2 = llvm.udiv %1, %arg1 : i64 + %3 = llvm.udiv %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_9.mlir b/benchmarks/MLIR_single/7_function_9.mlir new file mode 100644 index 0000000..b684b07 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_9.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.xor %arg1, %arg2 : i64 + %1 = llvm.and %arg1, %0 : i64 + %2 = llvm.urem %1, %arg1 : i64 + %3 = llvm.lshr %arg0, %2 : i64 + %4 = llvm.or %arg0, %3 : i64 + %5 = llvm.urem %arg0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_90.mlir b/benchmarks/MLIR_single/7_function_90.mlir new file mode 100644 index 0000000..a863272 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_90.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_91.mlir b/benchmarks/MLIR_single/7_function_91.mlir new file mode 100644 index 0000000..e817cf6 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_91.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i1 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.ashr exact %arg0, %0 : i64 + %2 = llvm.srem %arg0, %1 : i64 + %3 = llvm.srem %2, %arg2 : i64 + %4 = llvm.sext %arg3 : i32 to i64 + %5 = llvm.urem %4, %4 : i64 + %6 = llvm.icmp "ne" %3, %5 : i64 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_92.mlir b/benchmarks/MLIR_single/7_function_92.mlir new file mode 100644 index 0000000..e5b5f96 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_92.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.and %arg1, %arg0 : i64 + %3 = llvm.xor %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i1 + %5 = llvm.select %4, %arg2, %1 : i1, i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_93.mlir b/benchmarks/MLIR_single/7_function_93.mlir new file mode 100644 index 0000000..f6016b3 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_93.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.udiv %0, %arg1 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.xor %arg1, %arg2 : i64 + %5 = llvm.udiv %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_94.mlir b/benchmarks/MLIR_single/7_function_94.mlir new file mode 100644 index 0000000..e23c544 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_94.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv exact %arg0, %arg1 : i64 + %1 = llvm.srem %arg2, %arg2 : i64 + %2 = llvm.sdiv exact %1, %arg0 : i64 + %3 = llvm.srem %arg0, %2 : i64 + %4 = llvm.lshr exact %3, %arg0 : i64 + %5 = llvm.sdiv %0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i1 + return %6 : i1 +} + diff --git a/benchmarks/MLIR_single/7_function_95.mlir b/benchmarks/MLIR_single/7_function_95.mlir new file mode 100644 index 0000000..3a2c769 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_95.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.xor %0, %arg0 : i64 + %2 = llvm.ashr exact %arg1, %arg2 : i64 + %3 = llvm.udiv %1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_96.mlir b/benchmarks/MLIR_single/7_function_96.mlir new file mode 100644 index 0000000..e2b94c9 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_96.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.ashr %0, %arg0 : i64 + %2 = llvm.ashr exact %arg0, %1 : i64 + %3 = llvm.sdiv %arg0, %2 : i64 + %4 = llvm.xor %0, %arg1 : i64 + %5 = llvm.xor %3, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + return %6 : i32 +} + diff --git a/benchmarks/MLIR_single/7_function_97.mlir b/benchmarks/MLIR_single/7_function_97.mlir new file mode 100644 index 0000000..5998710 --- /dev/null +++ b/benchmarks/MLIR_single/7_function_97.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i64 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.zext %arg1 : i32 to i64 + %2 = llvm.lshr exact %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.xor %0, %4 : i64 + %6 = llvm.ashr %arg0, %5 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_98.mlir b/benchmarks/MLIR_single/7_function_98.mlir new file mode 100644 index 0000000..0cd885b --- /dev/null +++ b/benchmarks/MLIR_single/7_function_98.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.or %arg0, %arg0 : i64 + %1 = llvm.udiv %arg0, %0 : i64 + %2 = llvm.icmp "sgt" %1, %0 : i64 + %3 = llvm.ashr %0, %arg1 : i64 + %4 = llvm.select %2, %3, %arg2 : i1, i64 + %5 = llvm.and %arg0, %4 : i64 + %6 = llvm.ashr %5, %1 : i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/7_function_99.mlir b/benchmarks/MLIR_single/7_function_99.mlir new file mode 100644 index 0000000..19259ee --- /dev/null +++ b/benchmarks/MLIR_single/7_function_99.mlir @@ -0,0 +1,11 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sdiv %arg0, %arg1 : i64 + %1 = llvm.and %arg1, %arg2 : i64 + %2 = llvm.sdiv exact %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i1 + %4 = llvm.trunc %0 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.select %3, %arg1, %5 : i1, i64 + return %6 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_0.mlir b/benchmarks/MLIR_single/8_function_0.mlir new file mode 100644 index 0000000..1975f9e --- /dev/null +++ b/benchmarks/MLIR_single/8_function_0.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.ashr exact %arg0, %2 : i64 + %4 = llvm.or disjoint %arg1, %arg2 : i64 + %5 = llvm.udiv %4, %arg2 : i64 + %6 = llvm.and %3, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_1.mlir b/benchmarks/MLIR_single/8_function_1.mlir new file mode 100644 index 0000000..92a3e53 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_1.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i32, %arg2: i1) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.srem %0, %2 : i64 + %4 = llvm.sext %arg1 : i32 to i64 + %5 = llvm.select %arg2, %0, %4 : i1, i64 + %6 = llvm.srem %4, %5 : i64 + %7 = llvm.srem %3, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_10.mlir b/benchmarks/MLIR_single/8_function_10.mlir new file mode 100644 index 0000000..bf5fad3 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_10.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.or %arg0, %0 : i64 + %2 = llvm.xor %1, %arg2 : i64 + %3 = llvm.trunc %2 : i64 to i1 + %4 = llvm.lshr %0, %arg2 : i64 + %5 = llvm.icmp "slt" %4, %2 : i64 + %6 = llvm.select %5, %0, %2 : i1, i64 + %7 = llvm.select %3, %6, %arg2 : i1, i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_11.mlir b/benchmarks/MLIR_single/8_function_11.mlir new file mode 100644 index 0000000..e2e4609 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_11.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i32 { + %0 = llvm.lshr %arg0, %arg1 : i64 + %1 = llvm.ashr %arg0, %arg2 : i64 + %2 = llvm.urem %arg0, %1 : i64 + %3 = llvm.urem %2, %0 : i64 + %4 = llvm.sdiv %0, %3 : i64 + %5 = llvm.zext %arg3 : i32 to i64 + %6 = llvm.and %4, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_12.mlir b/benchmarks/MLIR_single/8_function_12.mlir new file mode 100644 index 0000000..e96d7d7 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_12.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.trunc %arg2 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.lshr %0, %2 : i64 + %4 = llvm.and %arg0, %0 : i64 + %5 = llvm.sdiv exact %arg1, %4 : i64 + %6 = llvm.lshr %3, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_13.mlir b/benchmarks/MLIR_single/8_function_13.mlir new file mode 100644 index 0000000..1f86e83 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_13.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.urem %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.or disjoint %0, %arg1 : i64 + %4 = llvm.and %arg0, %3 : i64 + %5 = llvm.xor %2, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + %7 = llvm.zext %6 : i32 to i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_14.mlir b/benchmarks/MLIR_single/8_function_14.mlir new file mode 100644 index 0000000..42db7b9 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_14.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32, %arg3: i1) -> i1 { + %0 = llvm.sext %arg2 : i32 to i64 + %1 = llvm.ashr exact %arg1, %0 : i64 + %2 = llvm.udiv %arg0, %1 : i64 + %3 = llvm.urem %2, %arg0 : i64 + %4 = llvm.select %arg3, %arg1, %arg0 : i1, i64 + %5 = llvm.lshr exact %4, %3 : i64 + %6 = llvm.urem %3, %5 : i64 + %7 = llvm.icmp "ule" %2, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_15.mlir b/benchmarks/MLIR_single/8_function_15.mlir new file mode 100644 index 0000000..4c6c488 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_15.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i32 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.urem %0, %arg1 : i64 + %2 = llvm.icmp "ult" %arg0, %1 : i64 + %3 = llvm.sdiv %arg0, %0 : i64 + %4 = llvm.select %2, %arg2, %3 : i1, i64 + %5 = llvm.zext %arg3 : i32 to i64 + %6 = llvm.and %4, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_16.mlir b/benchmarks/MLIR_single/8_function_16.mlir new file mode 100644 index 0000000..27d3f41 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_16.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i64 { + %0 = llvm.sext %arg1 : i32 to i64 + %1 = llvm.or disjoint %arg0, %0 : i64 + %2 = llvm.srem %0, %arg2 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.urem %arg0, %4 : i64 + %6 = llvm.urem %5, %arg2 : i64 + %7 = llvm.sdiv exact %1, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_17.mlir b/benchmarks/MLIR_single/8_function_17.mlir new file mode 100644 index 0000000..e6a80d2 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_17.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.urem %0, %arg1 : i64 + %2 = llvm.urem %arg1, %0 : i64 + %3 = llvm.sdiv exact %arg2, %0 : i64 + %4 = llvm.and %2, %3 : i64 + %5 = llvm.xor %arg1, %4 : i64 + %6 = llvm.ashr %1, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_18.mlir b/benchmarks/MLIR_single/8_function_18.mlir new file mode 100644 index 0000000..d0c3fb7 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_18.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.lshr exact %arg1, %arg2 : i64 + %3 = llvm.urem %1, %2 : i64 + %4 = llvm.lshr exact %1, %3 : i64 + %5 = llvm.trunc %arg2 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.icmp "ult" %4, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_19.mlir b/benchmarks/MLIR_single/8_function_19.mlir new file mode 100644 index 0000000..154fcbb --- /dev/null +++ b/benchmarks/MLIR_single/8_function_19.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.or %arg0, %arg1 : i64 + %1 = llvm.or disjoint %0, %arg2 : i64 + %2 = llvm.urem %1, %0 : i64 + %3 = llvm.trunc %2 : i64 to i1 + %4 = llvm.select %3, %arg2, %2 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.icmp "ugt" %6, %4 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_2.mlir b/benchmarks/MLIR_single/8_function_2.mlir new file mode 100644 index 0000000..7194f31 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_2.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i64 { + %0 = llvm.sext %arg1 : i32 to i64 + %1 = llvm.and %0, %0 : i64 + %2 = llvm.sext %arg1 : i32 to i64 + %3 = llvm.urem %arg2, %2 : i64 + %4 = llvm.lshr exact %1, %3 : i64 + %5 = llvm.and %arg0, %4 : i64 + %6 = llvm.urem %arg2, %0 : i64 + %7 = llvm.urem %5, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_20.mlir b/benchmarks/MLIR_single/8_function_20.mlir new file mode 100644 index 0000000..d160293 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_20.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.srem %0, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.lshr exact %3, %1 : i64 + %5 = llvm.udiv %0, %4 : i64 + %6 = llvm.and %5, %arg0 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_21.mlir b/benchmarks/MLIR_single/8_function_21.mlir new file mode 100644 index 0000000..c4f3b4f --- /dev/null +++ b/benchmarks/MLIR_single/8_function_21.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.srem %arg0, %1 : i64 + %3 = llvm.udiv %arg2, %arg1 : i64 + %4 = llvm.and %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_22.mlir b/benchmarks/MLIR_single/8_function_22.mlir new file mode 100644 index 0000000..3cfab44 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_22.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i1 + %1 = llvm.lshr %arg0, %arg0 : i64 + %2 = llvm.ashr exact %1, %arg2 : i64 + %3 = llvm.urem %arg1, %2 : i64 + %4 = llvm.lshr %arg2, %arg1 : i64 + %5 = llvm.select %0, %4, %arg0 : i1, i64 + %6 = llvm.select %0, %3, %5 : i1, i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_23.mlir b/benchmarks/MLIR_single/8_function_23.mlir new file mode 100644 index 0000000..93c7df0 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_23.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.udiv %1, %arg0 : i64 + %3 = llvm.sdiv %arg1, %1 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.srem %2, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_24.mlir b/benchmarks/MLIR_single/8_function_24.mlir new file mode 100644 index 0000000..ad6be09 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_24.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.trunc %arg1 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.trunc %arg2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.udiv %arg2, %4 : i64 + %6 = llvm.lshr exact %2, %5 : i64 + %7 = llvm.icmp "sle" %0, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_25.mlir b/benchmarks/MLIR_single/8_function_25.mlir new file mode 100644 index 0000000..a2a09cb --- /dev/null +++ b/benchmarks/MLIR_single/8_function_25.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64, %arg3: i32) -> i1 { + %0 = llvm.select %arg1, %arg0, %arg2 : i1, i64 + %1 = llvm.sdiv exact %arg0, %0 : i64 + %2 = llvm.sext %arg3 : i32 to i64 + %3 = llvm.lshr exact %1, %2 : i64 + %4 = llvm.lshr exact %3, %2 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_26.mlir b/benchmarks/MLIR_single/8_function_26.mlir new file mode 100644 index 0000000..b68ecc8 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_26.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i64 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.sext %arg1 : i32 to i64 + %2 = llvm.udiv %arg0, %1 : i64 + %3 = llvm.and %2, %arg2 : i64 + %4 = llvm.ashr exact %3, %2 : i64 + %5 = llvm.udiv %2, %4 : i64 + %6 = llvm.ashr %0, %5 : i64 + %7 = llvm.sdiv %6, %4 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_27.mlir b/benchmarks/MLIR_single/8_function_27.mlir new file mode 100644 index 0000000..14e4cd3 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_27.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i64 { + %0 = llvm.select %arg1, %arg0, %arg2 : i1, i64 + %1 = llvm.ashr exact %0, %arg0 : i64 + %2 = llvm.and %arg0, %1 : i64 + %3 = llvm.lshr exact %arg0, %arg0 : i64 + %4 = llvm.ashr exact %2, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.urem %arg0, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_28.mlir b/benchmarks/MLIR_single/8_function_28.mlir new file mode 100644 index 0000000..7d1440c --- /dev/null +++ b/benchmarks/MLIR_single/8_function_28.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i1 + %1 = llvm.zext %arg1 : i32 to i64 + %2 = llvm.select %0, %1, %arg2 : i1, i64 + %3 = llvm.zext %arg1 : i32 to i64 + %4 = llvm.ashr exact %2, %3 : i64 + %5 = llvm.trunc %arg2 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.icmp "uge" %4, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_29.mlir b/benchmarks/MLIR_single/8_function_29.mlir new file mode 100644 index 0000000..79e82ce --- /dev/null +++ b/benchmarks/MLIR_single/8_function_29.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) -> i32 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.srem %arg2, %arg0 : i64 + %2 = llvm.xor %0, %1 : i64 + %3 = llvm.xor %arg2, %arg1 : i64 + %4 = llvm.select %arg3, %0, %3 : i1, i64 + %5 = llvm.srem %2, %4 : i64 + %6 = llvm.lshr %5, %arg0 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_3.mlir b/benchmarks/MLIR_single/8_function_3.mlir new file mode 100644 index 0000000..53be348 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_3.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.ashr exact %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.urem %arg0, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_30.mlir b/benchmarks/MLIR_single/8_function_30.mlir new file mode 100644 index 0000000..e1dc92d --- /dev/null +++ b/benchmarks/MLIR_single/8_function_30.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i1 { + %0 = llvm.xor %arg0, %arg0 : i64 + %1 = llvm.zext %arg1 : i32 to i64 + %2 = llvm.and %0, %1 : i64 + %3 = llvm.ashr %arg0, %2 : i64 + %4 = llvm.and %3, %arg2 : i64 + %5 = llvm.lshr %2, %4 : i64 + %6 = llvm.ashr %3, %5 : i64 + %7 = llvm.icmp "slt" %2, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_31.mlir b/benchmarks/MLIR_single/8_function_31.mlir new file mode 100644 index 0000000..1563ce8 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_31.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg1, %arg0 : i64 + %1 = llvm.udiv %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.lshr %1, %arg2 : i64 + %5 = llvm.icmp "ult" %3, %4 : i64 + %6 = llvm.srem %3, %0 : i64 + %7 = llvm.select %5, %arg2, %6 : i1, i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_32.mlir b/benchmarks/MLIR_single/8_function_32.mlir new file mode 100644 index 0000000..af483f5 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_32.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i1, %arg1: i1, %arg2: i64) -> i32 { + %0 = llvm.select %arg1, %arg2, %arg2 : i1, i64 + %1 = llvm.and %arg2, %0 : i64 + %2 = llvm.lshr %1, %0 : i64 + %3 = llvm.lshr %0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.select %arg0, %5, %arg2 : i1, i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_33.mlir b/benchmarks/MLIR_single/8_function_33.mlir new file mode 100644 index 0000000..8e90b6a --- /dev/null +++ b/benchmarks/MLIR_single/8_function_33.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.urem %0, %arg2 : i64 + %2 = llvm.lshr %1, %0 : i64 + %3 = llvm.trunc %arg1 : i64 to i1 + %4 = llvm.select %3, %2, %1 : i1, i64 + %5 = llvm.urem %2, %4 : i64 + %6 = llvm.and %1, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_34.mlir b/benchmarks/MLIR_single/8_function_34.mlir new file mode 100644 index 0000000..87ea084 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_34.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.srem %0, %arg1 : i64 + %2 = llvm.sdiv exact %arg2, %1 : i64 + %3 = llvm.or disjoint %0, %2 : i64 + %4 = llvm.or disjoint %0, %0 : i64 + %5 = llvm.sdiv exact %4, %2 : i64 + %6 = llvm.srem %3, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_35.mlir b/benchmarks/MLIR_single/8_function_35.mlir new file mode 100644 index 0000000..f7d5751 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_35.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg1, %arg0 : i64 + %1 = llvm.sdiv %0, %arg2 : i64 + %2 = llvm.lshr exact %arg0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_36.mlir b/benchmarks/MLIR_single/8_function_36.mlir new file mode 100644 index 0000000..b5044d9 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_36.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64, %arg3: i32) -> i32 { + %0 = llvm.urem %arg1, %arg2 : i64 + %1 = llvm.zext %arg3 : i32 to i64 + %2 = llvm.urem %1, %1 : i64 + %3 = llvm.xor %arg1, %2 : i64 + %4 = llvm.srem %3, %0 : i64 + %5 = llvm.sdiv exact %arg1, %4 : i64 + %6 = llvm.select %arg0, %0, %5 : i1, i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_37.mlir b/benchmarks/MLIR_single/8_function_37.mlir new file mode 100644 index 0000000..ccfc15b --- /dev/null +++ b/benchmarks/MLIR_single/8_function_37.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.srem %0, %arg0 : i64 + %2 = llvm.udiv %arg1, %1 : i64 + %3 = llvm.or %arg2, %2 : i64 + %4 = llvm.xor %1, %3 : i64 + %5 = llvm.urem %0, %4 : i64 + %6 = llvm.urem %5, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_38.mlir b/benchmarks/MLIR_single/8_function_38.mlir new file mode 100644 index 0000000..1c51edb --- /dev/null +++ b/benchmarks/MLIR_single/8_function_38.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i64 { + %0 = llvm.icmp "ule" %arg0, %arg1 : i64 + %1 = llvm.or %arg0, %arg1 : i64 + %2 = llvm.udiv %arg1, %arg2 : i64 + %3 = llvm.xor %1, %2 : i64 + %4 = llvm.xor %arg0, %3 : i64 + %5 = llvm.and %3, %4 : i64 + %6 = llvm.zext %arg3 : i32 to i64 + %7 = llvm.select %0, %5, %6 : i1, i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_39.mlir b/benchmarks/MLIR_single/8_function_39.mlir new file mode 100644 index 0000000..84d1bf1 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_39.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i64) -> i32 { + %0 = llvm.or %arg0, %arg0 : i64 + %1 = llvm.ashr exact %arg0, %0 : i64 + %2 = llvm.select %arg1, %arg2, %arg0 : i1, i64 + %3 = llvm.and %2, %arg0 : i64 + %4 = llvm.or disjoint %3, %2 : i64 + %5 = llvm.udiv %4, %4 : i64 + %6 = llvm.or disjoint %1, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_4.mlir b/benchmarks/MLIR_single/8_function_4.mlir new file mode 100644 index 0000000..3a47f90 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_4.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) -> i1 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.lshr exact %arg2, %arg1 : i64 + %2 = llvm.ashr exact %0, %1 : i64 + %3 = llvm.select %arg3, %arg2, %arg0 : i1, i64 + %4 = llvm.ashr %3, %2 : i64 + %5 = llvm.or %2, %4 : i64 + %6 = llvm.urem %arg2, %5 : i64 + %7 = llvm.icmp "ult" %5, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_40.mlir b/benchmarks/MLIR_single/8_function_40.mlir new file mode 100644 index 0000000..b9556fb --- /dev/null +++ b/benchmarks/MLIR_single/8_function_40.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.icmp "uge" %1, %1 : i64 + %3 = llvm.select %2, %arg0, %arg0 : i1, i64 + %4 = llvm.or %arg0, %3 : i64 + %5 = llvm.ashr exact %arg2, %arg2 : i64 + %6 = llvm.or disjoint %arg1, %5 : i64 + %7 = llvm.ashr %4, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_41.mlir b/benchmarks/MLIR_single/8_function_41.mlir new file mode 100644 index 0000000..c50d45a --- /dev/null +++ b/benchmarks/MLIR_single/8_function_41.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.icmp "sge" %arg0, %arg1 : i64 + %1 = llvm.select %0, %arg2, %arg0 : i1, i64 + %2 = llvm.ashr exact %arg2, %1 : i64 + %3 = llvm.and %arg0, %2 : i64 + %4 = llvm.xor %1, %3 : i64 + %5 = llvm.urem %1, %4 : i64 + %6 = llvm.select %0, %3, %5 : i1, i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_42.mlir b/benchmarks/MLIR_single/8_function_42.mlir new file mode 100644 index 0000000..cbddbdd --- /dev/null +++ b/benchmarks/MLIR_single/8_function_42.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sdiv exact %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.lshr %0, %arg2 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.srem %0, %4 : i64 + %6 = llvm.lshr exact %5, %2 : i64 + %7 = llvm.select %1, %arg2, %6 : i1, i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_43.mlir b/benchmarks/MLIR_single/8_function_43.mlir new file mode 100644 index 0000000..8411ac2 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_43.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i1, %arg2: i64) -> i32 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.select %arg1, %arg2, %0 : i1, i64 + %2 = llvm.ashr exact %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.urem %0, %arg2 : i64 + %6 = llvm.udiv %4, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_44.mlir b/benchmarks/MLIR_single/8_function_44.mlir new file mode 100644 index 0000000..e33d0fe --- /dev/null +++ b/benchmarks/MLIR_single/8_function_44.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sdiv %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.urem %0, %0 : i64 + %4 = llvm.and %arg2, %3 : i64 + %5 = llvm.sdiv exact %arg1, %arg0 : i64 + %6 = llvm.or disjoint %4, %5 : i64 + %7 = llvm.icmp "sge" %2, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_45.mlir b/benchmarks/MLIR_single/8_function_45.mlir new file mode 100644 index 0000000..500718d --- /dev/null +++ b/benchmarks/MLIR_single/8_function_45.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i32, %arg2: i64) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.lshr exact %arg0, %arg0 : i64 + %2 = llvm.urem %0, %1 : i64 + %3 = llvm.sext %arg1 : i32 to i64 + %4 = llvm.ashr %2, %3 : i64 + %5 = llvm.and %arg2, %arg2 : i64 + %6 = llvm.srem %5, %2 : i64 + %7 = llvm.lshr %4, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_46.mlir b/benchmarks/MLIR_single/8_function_46.mlir new file mode 100644 index 0000000..a9bb2c5 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_46.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.icmp "ugt" %arg0, %arg1 : i64 + %1 = llvm.select %0, %arg0, %arg0 : i1, i64 + %2 = llvm.udiv %arg0, %arg2 : i64 + %3 = llvm.sdiv %1, %2 : i64 + %4 = llvm.sdiv exact %3, %arg0 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_47.mlir b/benchmarks/MLIR_single/8_function_47.mlir new file mode 100644 index 0000000..89e4dc0 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_47.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.srem %0, %0 : i64 + %3 = llvm.select %1, %2, %arg1 : i1, i64 + %4 = llvm.xor %arg1, %arg1 : i64 + %5 = llvm.udiv %4, %arg2 : i64 + %6 = llvm.srem %3, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_48.mlir b/benchmarks/MLIR_single/8_function_48.mlir new file mode 100644 index 0000000..674e52f --- /dev/null +++ b/benchmarks/MLIR_single/8_function_48.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.sdiv exact %arg0, %1 : i64 + %3 = llvm.udiv %arg0, %arg2 : i64 + %4 = llvm.lshr exact %arg1, %3 : i64 + %5 = llvm.urem %1, %arg1 : i64 + %6 = llvm.xor %4, %5 : i64 + %7 = llvm.srem %2, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_49.mlir b/benchmarks/MLIR_single/8_function_49.mlir new file mode 100644 index 0000000..f6e5e76 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_49.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1, %arg3: i32) -> i32 { + %0 = llvm.select %arg2, %arg0, %arg0 : i1, i64 + %1 = llvm.sext %arg3 : i32 to i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.and %arg1, %2 : i64 + %4 = llvm.select %arg2, %3, %arg0 : i1, i64 + %5 = llvm.and %3, %4 : i64 + %6 = llvm.and %arg0, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_5.mlir b/benchmarks/MLIR_single/8_function_5.mlir new file mode 100644 index 0000000..243f7d3 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_5.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.ashr exact %arg1, %arg1 : i64 + %1 = llvm.lshr exact %arg1, %arg2 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.srem %0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.icmp "ne" %arg0, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_50.mlir b/benchmarks/MLIR_single/8_function_50.mlir new file mode 100644 index 0000000..b51195d --- /dev/null +++ b/benchmarks/MLIR_single/8_function_50.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) -> i1 { + %0 = llvm.ashr exact %arg0, %arg0 : i64 + %1 = llvm.sdiv %arg1, %arg2 : i64 + %2 = llvm.udiv %0, %1 : i64 + %3 = llvm.or disjoint %0, %2 : i64 + %4 = llvm.or %3, %3 : i64 + %5 = llvm.select %arg3, %4, %2 : i1, i64 + %6 = llvm.lshr exact %2, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_51.mlir b/benchmarks/MLIR_single/8_function_51.mlir new file mode 100644 index 0000000..5f2ffa2 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_51.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i32 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.and %0, %0 : i64 + %2 = llvm.or disjoint %0, %1 : i64 + %3 = llvm.xor %arg2, %arg2 : i64 + %4 = llvm.zext %arg3 : i32 to i64 + %5 = llvm.lshr exact %3, %4 : i64 + %6 = llvm.sdiv exact %2, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_52.mlir b/benchmarks/MLIR_single/8_function_52.mlir new file mode 100644 index 0000000..1b1a247 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_52.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.sdiv %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.urem %arg0, %2 : i64 + %4 = llvm.lshr exact %arg0, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_53.mlir b/benchmarks/MLIR_single/8_function_53.mlir new file mode 100644 index 0000000..9a86a34 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_53.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i1 + %1 = llvm.and %arg0, %arg0 : i64 + %2 = llvm.select %0, %1, %1 : i1, i64 + %3 = llvm.lshr exact %2, %arg1 : i64 + %4 = llvm.or %3, %arg1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_54.mlir b/benchmarks/MLIR_single/8_function_54.mlir new file mode 100644 index 0000000..9b961c7 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_54.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i32 { + %0 = llvm.or %arg0, %arg0 : i64 + %1 = llvm.zext %arg2 : i32 to i64 + %2 = llvm.lshr %arg1, %1 : i64 + %3 = llvm.sext %arg2 : i32 to i64 + %4 = llvm.urem %2, %3 : i64 + %5 = llvm.and %4, %3 : i64 + %6 = llvm.srem %0, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_55.mlir b/benchmarks/MLIR_single/8_function_55.mlir new file mode 100644 index 0000000..5c03044 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_55.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.or %0, %arg2 : i64 + %2 = llvm.udiv %arg2, %0 : i64 + %3 = llvm.sdiv exact %1, %2 : i64 + %4 = llvm.udiv %arg0, %3 : i64 + %5 = llvm.urem %0, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + %7 = llvm.zext %6 : i32 to i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_56.mlir b/benchmarks/MLIR_single/8_function_56.mlir new file mode 100644 index 0000000..8ca57af --- /dev/null +++ b/benchmarks/MLIR_single/8_function_56.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.sdiv exact %arg0, %arg1 : i64 + %1 = llvm.trunc %arg0 : i64 to i32 + %2 = llvm.zext %1 : i32 to i64 + %3 = llvm.or %arg1, %arg0 : i64 + %4 = llvm.urem %arg2, %3 : i64 + %5 = llvm.sdiv %2, %4 : i64 + %6 = llvm.srem %0, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_57.mlir b/benchmarks/MLIR_single/8_function_57.mlir new file mode 100644 index 0000000..4bff35b --- /dev/null +++ b/benchmarks/MLIR_single/8_function_57.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.icmp "slt" %arg1, %arg2 : i64 + %3 = llvm.select %2, %0, %0 : i1, i64 + %4 = llvm.icmp "ugt" %3, %1 : i64 + %5 = llvm.select %4, %arg0, %3 : i1, i64 + %6 = llvm.or %3, %5 : i64 + %7 = llvm.icmp "sgt" %1, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_58.mlir b/benchmarks/MLIR_single/8_function_58.mlir new file mode 100644 index 0000000..5de7012 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_58.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.sdiv %arg1, %arg0 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.urem %0, %1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.icmp "slt" %3, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_59.mlir b/benchmarks/MLIR_single/8_function_59.mlir new file mode 100644 index 0000000..a5fa989 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_59.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.udiv %arg2, %arg0 : i64 + %4 = llvm.udiv %2, %3 : i64 + %5 = llvm.srem %3, %arg1 : i64 + %6 = llvm.srem %4, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_6.mlir b/benchmarks/MLIR_single/8_function_6.mlir new file mode 100644 index 0000000..0559811 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_6.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.select %arg3, %arg2, %0 : i1, i64 + %2 = llvm.or %arg2, %1 : i64 + %3 = llvm.srem %2, %1 : i64 + %4 = llvm.xor %2, %3 : i64 + %5 = llvm.udiv %4, %2 : i64 + %6 = llvm.srem %arg1, %5 : i64 + %7 = llvm.ashr exact %0, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_60.mlir b/benchmarks/MLIR_single/8_function_60.mlir new file mode 100644 index 0000000..5a38fa0 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_60.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.trunc %arg1 : i64 to i1 + %3 = llvm.select %2, %arg2, %arg0 : i1, i64 + %4 = llvm.srem %arg1, %3 : i64 + %5 = llvm.xor %arg0, %4 : i64 + %6 = llvm.sdiv %1, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_61.mlir b/benchmarks/MLIR_single/8_function_61.mlir new file mode 100644 index 0000000..11bd148 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_61.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.trunc %arg1 : i64 to i32 + %1 = llvm.zext %0 : i32 to i64 + %2 = llvm.xor %1, %arg2 : i64 + %3 = llvm.or %arg0, %arg0 : i64 + %4 = llvm.srem %3, %1 : i64 + %5 = llvm.xor %2, %4 : i64 + %6 = llvm.lshr exact %arg0, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_62.mlir b/benchmarks/MLIR_single/8_function_62.mlir new file mode 100644 index 0000000..87fae42 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_62.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.udiv %arg1, %arg2 : i64 + %2 = llvm.sdiv %1, %arg2 : i64 + %3 = llvm.xor %0, %2 : i64 + %4 = llvm.trunc %arg2 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.ashr %3, %5 : i64 + %7 = llvm.and %6, %arg2 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_63.mlir b/benchmarks/MLIR_single/8_function_63.mlir new file mode 100644 index 0000000..81d6631 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_63.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg1, %arg0 : i64 + %1 = llvm.icmp "ule" %0, %arg2 : i64 + %2 = llvm.lshr %arg1, %arg2 : i64 + %3 = llvm.sdiv exact %0, %2 : i64 + %4 = llvm.select %1, %arg1, %3 : i1, i64 + %5 = llvm.urem %arg0, %4 : i64 + %6 = llvm.lshr exact %3, %4 : i64 + %7 = llvm.icmp "ule" %5, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_64.mlir b/benchmarks/MLIR_single/8_function_64.mlir new file mode 100644 index 0000000..f4cc5cc --- /dev/null +++ b/benchmarks/MLIR_single/8_function_64.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.lshr exact %arg0, %arg1 : i64 + %1 = llvm.or disjoint %arg1, %arg1 : i64 + %2 = llvm.udiv %1, %arg2 : i64 + %3 = llvm.xor %arg2, %arg0 : i64 + %4 = llvm.sdiv exact %3, %arg2 : i64 + %5 = llvm.urem %2, %4 : i64 + %6 = llvm.srem %0, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_65.mlir b/benchmarks/MLIR_single/8_function_65.mlir new file mode 100644 index 0000000..0fb6e13 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_65.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.srem %arg1, %arg2 : i64 + %1 = llvm.lshr %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.srem %5, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_66.mlir b/benchmarks/MLIR_single/8_function_66.mlir new file mode 100644 index 0000000..792f85e --- /dev/null +++ b/benchmarks/MLIR_single/8_function_66.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.trunc %arg1 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.sdiv exact %0, %arg2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.srem %2, %5 : i64 + %7 = llvm.and %0, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_67.mlir b/benchmarks/MLIR_single/8_function_67.mlir new file mode 100644 index 0000000..fe52208 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_67.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.and %arg2, %arg0 : i64 + %2 = llvm.or %0, %1 : i64 + %3 = llvm.or %arg2, %2 : i64 + %4 = llvm.sdiv %0, %3 : i64 + %5 = llvm.and %3, %4 : i64 + %6 = llvm.or disjoint %0, %5 : i64 + %7 = llvm.icmp "uge" %6, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_68.mlir b/benchmarks/MLIR_single/8_function_68.mlir new file mode 100644 index 0000000..388e739 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_68.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.sdiv %arg0, %arg0 : i64 + %1 = llvm.udiv %arg0, %0 : i64 + %2 = llvm.srem %1, %arg1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.sext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_69.mlir b/benchmarks/MLIR_single/8_function_69.mlir new file mode 100644 index 0000000..37aaee9 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_69.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.srem %arg0, %arg1 : i64 + %1 = llvm.udiv %arg2, %arg2 : i64 + %2 = llvm.sdiv exact %0, %1 : i64 + %3 = llvm.srem %0, %0 : i64 + %4 = llvm.or disjoint %1, %3 : i64 + %5 = llvm.sdiv exact %1, %4 : i64 + %6 = llvm.sdiv exact %5, %arg2 : i64 + %7 = llvm.srem %2, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_7.mlir b/benchmarks/MLIR_single/8_function_7.mlir new file mode 100644 index 0000000..401d9dc --- /dev/null +++ b/benchmarks/MLIR_single/8_function_7.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.and %arg1, %0 : i64 + %2 = llvm.urem %0, %1 : i64 + %3 = llvm.select %arg3, %1, %2 : i1, i64 + %4 = llvm.and %arg1, %3 : i64 + %5 = llvm.and %2, %4 : i64 + %6 = llvm.urem %arg2, %5 : i64 + %7 = llvm.or %2, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_70.mlir b/benchmarks/MLIR_single/8_function_70.mlir new file mode 100644 index 0000000..dac9899 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_70.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i1, %arg2: i32) -> i1 { + %0 = llvm.sext %arg2 : i32 to i64 + %1 = llvm.icmp "eq" %0, %arg0 : i64 + %2 = llvm.select %arg1, %arg0, %arg0 : i1, i64 + %3 = llvm.select %1, %0, %2 : i1, i64 + %4 = llvm.lshr exact %arg0, %0 : i64 + %5 = llvm.select %arg1, %3, %4 : i1, i64 + %6 = llvm.lshr exact %arg0, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_71.mlir b/benchmarks/MLIR_single/8_function_71.mlir new file mode 100644 index 0000000..59d5f54 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_71.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.or disjoint %arg0, %arg0 : i64 + %1 = llvm.icmp "sgt" %0, %arg1 : i64 + %2 = llvm.select %1, %0, %arg2 : i1, i64 + %3 = llvm.trunc %2 : i64 to i1 + %4 = llvm.trunc %2 : i64 to i1 + %5 = llvm.lshr %arg0, %2 : i64 + %6 = llvm.select %4, %arg2, %5 : i1, i64 + %7 = llvm.select %3, %2, %6 : i1, i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_72.mlir b/benchmarks/MLIR_single/8_function_72.mlir new file mode 100644 index 0000000..1dd25a7 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_72.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.xor %arg0, %arg0 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.udiv %4, %arg1 : i64 + %6 = llvm.ashr %1, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_73.mlir b/benchmarks/MLIR_single/8_function_73.mlir new file mode 100644 index 0000000..613cffd --- /dev/null +++ b/benchmarks/MLIR_single/8_function_73.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.srem %arg1, %arg2 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.udiv %arg0, %2 : i64 + %4 = llvm.udiv %3, %3 : i64 + %5 = llvm.xor %4, %3 : i64 + %6 = llvm.ashr %3, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_74.mlir b/benchmarks/MLIR_single/8_function_74.mlir new file mode 100644 index 0000000..e14e1ec --- /dev/null +++ b/benchmarks/MLIR_single/8_function_74.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.and %0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i1 + %3 = llvm.udiv %arg0, %arg0 : i64 + %4 = llvm.or %3, %1 : i64 + %5 = llvm.and %arg1, %arg2 : i64 + %6 = llvm.select %2, %4, %5 : i1, i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_75.mlir b/benchmarks/MLIR_single/8_function_75.mlir new file mode 100644 index 0000000..ac2c1ee --- /dev/null +++ b/benchmarks/MLIR_single/8_function_75.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.xor %arg2, %arg2 : i64 + %4 = llvm.and %2, %3 : i64 + %5 = llvm.trunc %arg2 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.or %4, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_76.mlir b/benchmarks/MLIR_single/8_function_76.mlir new file mode 100644 index 0000000..b496552 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_76.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.sdiv %0, %arg1 : i64 + %2 = llvm.trunc %arg2 : i64 to i1 + %3 = llvm.select %2, %arg0, %arg2 : i1, i64 + %4 = llvm.srem %1, %3 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_77.mlir b/benchmarks/MLIR_single/8_function_77.mlir new file mode 100644 index 0000000..dfa1c99 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_77.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.xor %1, %arg1 : i64 + %3 = llvm.select %arg2, %2, %arg0 : i1, i64 + %4 = llvm.sdiv %arg1, %arg0 : i64 + %5 = llvm.srem %3, %4 : i64 + %6 = llvm.or disjoint %arg0, %5 : i64 + %7 = llvm.xor %2, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_78.mlir b/benchmarks/MLIR_single/8_function_78.mlir new file mode 100644 index 0000000..b5a730b --- /dev/null +++ b/benchmarks/MLIR_single/8_function_78.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64, %arg3: i1) -> i64 { + %0 = llvm.zext %arg0 : i32 to i64 + %1 = llvm.or %arg1, %arg2 : i64 + %2 = llvm.select %arg3, %arg1, %arg2 : i1, i64 + %3 = llvm.select %arg3, %arg2, %2 : i1, i64 + %4 = llvm.sdiv exact %2, %0 : i64 + %5 = llvm.lshr %3, %4 : i64 + %6 = llvm.urem %1, %5 : i64 + %7 = llvm.udiv %0, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_79.mlir b/benchmarks/MLIR_single/8_function_79.mlir new file mode 100644 index 0000000..bb9336c --- /dev/null +++ b/benchmarks/MLIR_single/8_function_79.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i1 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.select %arg2, %arg0, %arg1 : i1, i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.sdiv exact %arg1, %5 : i64 + %7 = llvm.icmp "ult" %2, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_8.mlir b/benchmarks/MLIR_single/8_function_8.mlir new file mode 100644 index 0000000..074303a --- /dev/null +++ b/benchmarks/MLIR_single/8_function_8.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i1 { + %0 = llvm.or disjoint %arg0, %arg1 : i64 + %1 = llvm.and %arg0, %0 : i64 + %2 = llvm.xor %1, %arg2 : i64 + %3 = llvm.and %arg1, %arg1 : i64 + %4 = llvm.zext %arg3 : i32 to i64 + %5 = llvm.and %4, %arg0 : i64 + %6 = llvm.or %3, %5 : i64 + %7 = llvm.icmp "eq" %2, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_80.mlir b/benchmarks/MLIR_single/8_function_80.mlir new file mode 100644 index 0000000..515aa29 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_80.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.urem %arg2, %arg2 : i64 + %2 = llvm.lshr %arg2, %1 : i64 + %3 = llvm.or disjoint %arg1, %arg1 : i64 + %4 = llvm.srem %3, %2 : i64 + %5 = llvm.lshr exact %2, %4 : i64 + %6 = llvm.srem %0, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_81.mlir b/benchmarks/MLIR_single/8_function_81.mlir new file mode 100644 index 0000000..d910825 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_81.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i1 + %1 = llvm.select %0, %arg0, %arg1 : i1, i64 + %2 = llvm.sdiv exact %arg2, %arg1 : i64 + %3 = llvm.ashr exact %1, %2 : i64 + %4 = llvm.and %3, %1 : i64 + %5 = llvm.sdiv exact %4, %arg1 : i64 + %6 = llvm.sdiv %3, %5 : i64 + %7 = llvm.ashr exact %4, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_82.mlir b/benchmarks/MLIR_single/8_function_82.mlir new file mode 100644 index 0000000..3dafb2f --- /dev/null +++ b/benchmarks/MLIR_single/8_function_82.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i1) -> i32 { + %0 = llvm.urem %arg0, %arg1 : i64 + %1 = llvm.select %arg2, %arg1, %arg1 : i1, i64 + %2 = llvm.icmp "sgt" %0, %1 : i64 + %3 = llvm.or %arg1, %arg1 : i64 + %4 = llvm.select %2, %3, %0 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_83.mlir b/benchmarks/MLIR_single/8_function_83.mlir new file mode 100644 index 0000000..a62f439 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_83.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.udiv %arg0, %arg0 : i64 + %1 = llvm.sdiv exact %arg0, %arg1 : i64 + %2 = llvm.urem %0, %1 : i64 + %3 = llvm.ashr exact %0, %1 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.lshr exact %2, %5 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_84.mlir b/benchmarks/MLIR_single/8_function_84.mlir new file mode 100644 index 0000000..f1ed286 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_84.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i32) -> i32 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.zext %arg1 : i32 to i64 + %3 = llvm.srem %arg0, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.and %1, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_85.mlir b/benchmarks/MLIR_single/8_function_85.mlir new file mode 100644 index 0000000..6ebe050 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_85.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.and %arg0, %arg1 : i64 + %1 = llvm.trunc %0 : i64 to i1 + %2 = llvm.trunc %arg0 : i64 to i32 + %3 = llvm.zext %2 : i32 to i64 + %4 = llvm.urem %3, %arg2 : i64 + %5 = llvm.select %1, %4, %4 : i1, i64 + %6 = llvm.udiv %arg2, %3 : i64 + %7 = llvm.icmp "sgt" %5, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_86.mlir b/benchmarks/MLIR_single/8_function_86.mlir new file mode 100644 index 0000000..a15584f --- /dev/null +++ b/benchmarks/MLIR_single/8_function_86.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i1 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.zext %arg2 : i32 to i64 + %2 = llvm.lshr %0, %1 : i64 + %3 = llvm.and %arg1, %2 : i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.xor %2, %5 : i64 + %7 = llvm.icmp "sle" %6, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_87.mlir b/benchmarks/MLIR_single/8_function_87.mlir new file mode 100644 index 0000000..2607fb7 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_87.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i32, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.sext %arg0 : i32 to i64 + %1 = llvm.urem %0, %arg1 : i64 + %2 = llvm.lshr %1, %arg1 : i64 + %3 = llvm.trunc %arg2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.ashr exact %2, %4 : i64 + %6 = llvm.trunc %5 : i64 to i32 + %7 = llvm.sext %6 : i32 to i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_88.mlir b/benchmarks/MLIR_single/8_function_88.mlir new file mode 100644 index 0000000..d7ff897 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_88.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.xor %arg0, %0 : i64 + %2 = llvm.xor %arg1, %arg2 : i64 + %3 = llvm.xor %0, %2 : i64 + %4 = llvm.sdiv %1, %3 : i64 + %5 = llvm.srem %4, %arg1 : i64 + %6 = llvm.xor %arg2, %arg0 : i64 + %7 = llvm.icmp "ugt" %5, %6 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_89.mlir b/benchmarks/MLIR_single/8_function_89.mlir new file mode 100644 index 0000000..c83e761 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_89.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i32 { + %0 = llvm.xor %arg0, %arg1 : i64 + %1 = llvm.and %arg1, %arg0 : i64 + %2 = llvm.sdiv exact %0, %1 : i64 + %3 = llvm.trunc %2 : i64 to i32 + %4 = llvm.zext %3 : i32 to i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_9.mlir b/benchmarks/MLIR_single/8_function_9.mlir new file mode 100644 index 0000000..6d8d4f6 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_9.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.ashr exact %arg0, %arg1 : i64 + %1 = llvm.trunc %arg2 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.urem %2, %0 : i64 + %4 = llvm.and %0, %arg1 : i64 + %5 = llvm.udiv %3, %4 : i64 + %6 = llvm.srem %5, %4 : i64 + %7 = llvm.sdiv %0, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_90.mlir b/benchmarks/MLIR_single/8_function_90.mlir new file mode 100644 index 0000000..d5dacc0 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_90.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.and %arg0, %arg0 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.icmp "eq" %arg0, %2 : i64 + %4 = llvm.select %3, %arg1, %arg2 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.zext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_91.mlir b/benchmarks/MLIR_single/8_function_91.mlir new file mode 100644 index 0000000..b78fffd --- /dev/null +++ b/benchmarks/MLIR_single/8_function_91.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64) -> i1 { + %0 = llvm.srem %arg0, %arg0 : i64 + %1 = llvm.or disjoint %arg0, %0 : i64 + %2 = llvm.xor %1, %arg0 : i64 + %3 = llvm.udiv %1, %2 : i64 + %4 = llvm.sdiv %3, %arg1 : i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.icmp "sgt" %6, %1 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_92.mlir b/benchmarks/MLIR_single/8_function_92.mlir new file mode 100644 index 0000000..b11f5f7 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_92.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i1, %arg1: i64) -> i64 { + %0 = llvm.and %arg1, %arg1 : i64 + %1 = llvm.udiv %arg1, %0 : i64 + %2 = llvm.or %0, %1 : i64 + %3 = llvm.select %arg0, %arg1, %2 : i1, i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.sext %4 : i32 to i64 + %6 = llvm.and %5, %arg1 : i64 + %7 = llvm.urem %5, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_93.mlir b/benchmarks/MLIR_single/8_function_93.mlir new file mode 100644 index 0000000..b2902a3 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_93.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i1, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.srem %arg1, %arg2 : i64 + %1 = llvm.trunc %0 : i64 to i32 + %2 = llvm.sext %1 : i32 to i64 + %3 = llvm.udiv %2, %arg1 : i64 + %4 = llvm.select %arg0, %2, %3 : i1, i64 + %5 = llvm.trunc %4 : i64 to i32 + %6 = llvm.sext %5 : i32 to i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_94.mlir b/benchmarks/MLIR_single/8_function_94.mlir new file mode 100644 index 0000000..fa940ea --- /dev/null +++ b/benchmarks/MLIR_single/8_function_94.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i32) -> i64 { + %0 = llvm.sdiv exact %arg0, %arg1 : i64 + %1 = llvm.icmp "sgt" %0, %arg1 : i64 + %2 = llvm.ashr exact %arg2, %0 : i64 + %3 = llvm.sext %arg3 : i32 to i64 + %4 = llvm.srem %2, %3 : i64 + %5 = llvm.select %1, %0, %4 : i1, i64 + %6 = llvm.srem %arg2, %3 : i64 + %7 = llvm.ashr exact %5, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_95.mlir b/benchmarks/MLIR_single/8_function_95.mlir new file mode 100644 index 0000000..cd6fea9 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_95.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.ashr %arg0, %arg1 : i64 + %1 = llvm.icmp "uge" %0, %arg2 : i64 + %2 = llvm.urem %arg2, %arg1 : i64 + %3 = llvm.select %1, %arg1, %2 : i1, i64 + %4 = llvm.udiv %arg1, %0 : i64 + %5 = llvm.ashr exact %3, %4 : i64 + %6 = llvm.udiv %3, %5 : i64 + %7 = llvm.icmp "ugt" %6, %3 : i64 + return %7 : i1 +} + diff --git a/benchmarks/MLIR_single/8_function_96.mlir b/benchmarks/MLIR_single/8_function_96.mlir new file mode 100644 index 0000000..95b5b18 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_96.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i64 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.srem %arg0, %0 : i64 + %2 = llvm.trunc %1 : i64 to i32 + %3 = llvm.sext %2 : i32 to i64 + %4 = llvm.trunc %3 : i64 to i32 + %5 = llvm.zext %4 : i32 to i64 + %6 = llvm.urem %arg2, %arg2 : i64 + %7 = llvm.udiv %5, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_97.mlir b/benchmarks/MLIR_single/8_function_97.mlir new file mode 100644 index 0000000..0cea20f --- /dev/null +++ b/benchmarks/MLIR_single/8_function_97.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i32) -> i64 { + %0 = llvm.trunc %arg0 : i64 to i32 + %1 = llvm.sext %0 : i32 to i64 + %2 = llvm.xor %1, %arg1 : i64 + %3 = llvm.zext %arg2 : i32 to i64 + %4 = llvm.urem %3, %arg1 : i64 + %5 = llvm.or %2, %4 : i64 + %6 = llvm.sext %arg2 : i32 to i64 + %7 = llvm.udiv %5, %6 : i64 + return %7 : i64 +} + diff --git a/benchmarks/MLIR_single/8_function_98.mlir b/benchmarks/MLIR_single/8_function_98.mlir new file mode 100644 index 0000000..c011b27 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_98.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i32 { + %0 = llvm.udiv %arg0, %arg1 : i64 + %1 = llvm.srem %0, %arg1 : i64 + %2 = llvm.or %0, %0 : i64 + %3 = llvm.xor %1, %2 : i64 + %4 = llvm.udiv %arg1, %arg2 : i64 + %5 = llvm.ashr exact %3, %4 : i64 + %6 = llvm.udiv %0, %5 : i64 + %7 = llvm.trunc %6 : i64 to i32 + return %7 : i32 +} + diff --git a/benchmarks/MLIR_single/8_function_99.mlir b/benchmarks/MLIR_single/8_function_99.mlir new file mode 100644 index 0000000..cfeeb64 --- /dev/null +++ b/benchmarks/MLIR_single/8_function_99.mlir @@ -0,0 +1,12 @@ +func.func @main(%arg0: i64, %arg1: i64, %arg2: i64) -> i1 { + %0 = llvm.icmp "ugt" %arg0, %arg0 : i64 + %1 = llvm.or disjoint %arg1, %arg2 : i64 + %2 = llvm.lshr exact %1, %arg0 : i64 + %3 = llvm.sdiv exact %1, %2 : i64 + %4 = llvm.select %0, %3, %arg2 : i1, i64 + %5 = llvm.xor %4, %arg0 : i64 + %6 = llvm.urem %5, %3 : i64 + %7 = llvm.trunc %6 : i64 to i1 + return %7 : i1 +} + diff --git a/benchmarks/VEIR_ASM/3_function_0.mlir b/benchmarks/VEIR_ASM/3_function_0.mlir new file mode 100644 index 0000000..cb9c2cb --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_0.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.remu"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %13 = "builtin.unrealized_conversion_cast"(%17) : (i32) -> !riscv.reg + %14 = "riscv.zext.w"(%13) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%14) : (!riscv.reg) -> i64 + "func.return"(%15) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_1.mlir b/benchmarks/VEIR_ASM/3_function_1.mlir new file mode 100644 index 0000000..87d1fce --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_1.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %17 = "riscv.remu"(%20, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_10.mlir b/benchmarks/VEIR_ASM/3_function_10.mlir new file mode 100644 index 0000000..2bf42f8 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_10.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.or"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.rem"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_11.mlir b/benchmarks/VEIR_ASM/3_function_11.mlir new file mode 100644 index 0000000..74f46f0 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_11.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.and"(%19, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %13 = "builtin.unrealized_conversion_cast"(%17) : (i32) -> !riscv.reg + %14 = "riscv.sext.w"(%13) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%14) : (!riscv.reg) -> i64 + "func.return"(%15) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_12.mlir b/benchmarks/VEIR_ASM/3_function_12.mlir new file mode 100644 index 0000000..ae8405f --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_12.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.srl"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.divu"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.and"(%19, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_13.mlir b/benchmarks/VEIR_ASM/3_function_13.mlir new file mode 100644 index 0000000..ea663b3 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_13.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.divu"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.and"(%24, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.slt"(%20, %13) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_14.mlir b/benchmarks/VEIR_ASM/3_function_14.mlir new file mode 100644 index 0000000..22a4096 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_14.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %24 = "riscv.czero.eqz"(%21, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.czero.nez"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "riscv.xor"(%18, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %15 = "riscv.rem"(%19, %14) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_15.mlir b/benchmarks/VEIR_ASM/3_function_15.mlir new file mode 100644 index 0000000..92aeae6 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_15.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.and"(%22, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.or"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %15 = "riscv.sltu"(%19, %14) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_16.mlir b/benchmarks/VEIR_ASM/3_function_16.mlir new file mode 100644 index 0000000..c44a7f7 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_16.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.xor"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.div"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_17.mlir b/benchmarks/VEIR_ASM/3_function_17.mlir new file mode 100644 index 0000000..56b0a05 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_17.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %22 = "riscv.sext.w"(%21) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.and"(%18, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %15 = "riscv.and"(%14, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_18.mlir b/benchmarks/VEIR_ASM/3_function_18.mlir new file mode 100644 index 0000000..fe8045a --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_18.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.srl"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.div"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_19.mlir b/benchmarks/VEIR_ASM/3_function_19.mlir new file mode 100644 index 0000000..fcd81bd --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_19.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_2.mlir b/benchmarks/VEIR_ASM/3_function_2.mlir new file mode 100644 index 0000000..e616544 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_2.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.srl"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.and"(%21, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_20.mlir b/benchmarks/VEIR_ASM/3_function_20.mlir new file mode 100644 index 0000000..c7f951d --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_20.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.srl"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.srl"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_21.mlir b/benchmarks/VEIR_ASM/3_function_21.mlir new file mode 100644 index 0000000..196cdae --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_21.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.xor"(%19, %13) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltiu"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_22.mlir b/benchmarks/VEIR_ASM/3_function_22.mlir new file mode 100644 index 0000000..74a3da2 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_22.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.divu"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %17 = "riscv.sra"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_23.mlir b/benchmarks/VEIR_ASM/3_function_23.mlir new file mode 100644 index 0000000..f8ce1b0 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_23.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.or"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%24, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_24.mlir b/benchmarks/VEIR_ASM/3_function_24.mlir new file mode 100644 index 0000000..e37a254 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_24.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %16 = "riscv.czero.eqz"(%13, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.czero.nez"(%21, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.or"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_25.mlir b/benchmarks/VEIR_ASM/3_function_25.mlir new file mode 100644 index 0000000..74414d3 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_25.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_26.mlir b/benchmarks/VEIR_ASM/3_function_26.mlir new file mode 100644 index 0000000..8fbf2e1 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_26.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.and"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_27.mlir b/benchmarks/VEIR_ASM/3_function_27.mlir new file mode 100644 index 0000000..350f184 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_27.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.or"(%18, %13) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_28.mlir b/benchmarks/VEIR_ASM/3_function_28.mlir new file mode 100644 index 0000000..f4bd50b --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_28.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.or"(%26, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %15 = "riscv.xor"(%14, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltiu"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_29.mlir b/benchmarks/VEIR_ASM/3_function_29.mlir new file mode 100644 index 0000000..22e05b1 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_29.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.slt"(%19, %14) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_3.mlir b/benchmarks/VEIR_ASM/3_function_3.mlir new file mode 100644 index 0000000..d6dcaa9 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_3.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.xor"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.xor"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.slt"(%20, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_30.mlir b/benchmarks/VEIR_ASM/3_function_30.mlir new file mode 100644 index 0000000..6f734b8 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_30.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.rem"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.or"(%24, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.slt"(%20, %13) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_31.mlir b/benchmarks/VEIR_ASM/3_function_31.mlir new file mode 100644 index 0000000..9222ade --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_31.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %17 = "riscv.sra"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_32.mlir b/benchmarks/VEIR_ASM/3_function_32.mlir new file mode 100644 index 0000000..88ab77f --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_32.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.srl"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %17 = "riscv.div"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_33.mlir b/benchmarks/VEIR_ASM/3_function_33.mlir new file mode 100644 index 0000000..68bf16c --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_33.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_34.mlir b/benchmarks/VEIR_ASM/3_function_34.mlir new file mode 100644 index 0000000..7da92d5 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_34.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.sra"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.div"(%23, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.xor"(%19, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_35.mlir b/benchmarks/VEIR_ASM/3_function_35.mlir new file mode 100644 index 0000000..5cbf640 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_35.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "riscv.xor"(%18, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.sltu"(%13, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_36.mlir b/benchmarks/VEIR_ASM/3_function_36.mlir new file mode 100644 index 0000000..74414d3 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_36.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_37.mlir b/benchmarks/VEIR_ASM/3_function_37.mlir new file mode 100644 index 0000000..a1592e8 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_37.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.rem"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %13 = "builtin.unrealized_conversion_cast"(%17) : (i32) -> !riscv.reg + %14 = "riscv.sext.w"(%13) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%14) : (!riscv.reg) -> i64 + "func.return"(%15) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_38.mlir b/benchmarks/VEIR_ASM/3_function_38.mlir new file mode 100644 index 0000000..40c56f0 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_38.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.slt"(%14, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_39.mlir b/benchmarks/VEIR_ASM/3_function_39.mlir new file mode 100644 index 0000000..0968b31 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_39.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.rem"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%15, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%24, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_4.mlir b/benchmarks/VEIR_ASM/3_function_4.mlir new file mode 100644 index 0000000..76f9458 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_4.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.xor"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.xor"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_40.mlir b/benchmarks/VEIR_ASM/3_function_40.mlir new file mode 100644 index 0000000..3eb2b80 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_40.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.and"(%22, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.or"(%18, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.rem"(%23, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_41.mlir b/benchmarks/VEIR_ASM/3_function_41.mlir new file mode 100644 index 0000000..fcd81bd --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_41.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_42.mlir b/benchmarks/VEIR_ASM/3_function_42.mlir new file mode 100644 index 0000000..ead560e --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_42.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.or"(%19, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %13 = "builtin.unrealized_conversion_cast"(%17) : (i32) -> !riscv.reg + %14 = "riscv.sext.w"(%13) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%14) : (!riscv.reg) -> i64 + "func.return"(%15) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_43.mlir b/benchmarks/VEIR_ASM/3_function_43.mlir new file mode 100644 index 0000000..be83356 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_43.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.xor"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.and"(%19, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_44.mlir b/benchmarks/VEIR_ASM/3_function_44.mlir new file mode 100644 index 0000000..f9d9194 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_44.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %24 = "riscv.czero.eqz"(%21, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.czero.nez"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.sra"(%17, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.srl"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_45.mlir b/benchmarks/VEIR_ASM/3_function_45.mlir new file mode 100644 index 0000000..58415fc --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_45.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.rem"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_46.mlir b/benchmarks/VEIR_ASM/3_function_46.mlir new file mode 100644 index 0000000..803e9ad --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_46.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.sra"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.div"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.xor"(%20, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltiu"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_47.mlir b/benchmarks/VEIR_ASM/3_function_47.mlir new file mode 100644 index 0000000..17ddac9 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_47.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.rem"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "riscv.div"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.remu"(%23, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_48.mlir b/benchmarks/VEIR_ASM/3_function_48.mlir new file mode 100644 index 0000000..68bf16c --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_48.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_49.mlir b/benchmarks/VEIR_ASM/3_function_49.mlir new file mode 100644 index 0000000..79af7b0 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_49.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.div"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.xor"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_5.mlir b/benchmarks/VEIR_ASM/3_function_5.mlir new file mode 100644 index 0000000..3fb38af --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_5.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "riscv.div"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%19, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %15 = "riscv.xor"(%14, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %17 = "riscv.sltu"(%16, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_50.mlir b/benchmarks/VEIR_ASM/3_function_50.mlir new file mode 100644 index 0000000..5b6365b --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_50.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.divu"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.or"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_51.mlir b/benchmarks/VEIR_ASM/3_function_51.mlir new file mode 100644 index 0000000..88c5a6e --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_51.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_52.mlir b/benchmarks/VEIR_ASM/3_function_52.mlir new file mode 100644 index 0000000..68bf16c --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_52.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_53.mlir b/benchmarks/VEIR_ASM/3_function_53.mlir new file mode 100644 index 0000000..71982f6 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_53.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.rem"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %15 = "riscv.div"(%19, %14) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_54.mlir b/benchmarks/VEIR_ASM/3_function_54.mlir new file mode 100644 index 0000000..e3f82e7 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_54.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.slt"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.xori"(%24) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i1 + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%26) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%15, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_55.mlir b/benchmarks/VEIR_ASM/3_function_55.mlir new file mode 100644 index 0000000..4d0e5ee --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_55.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.and"(%21, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_56.mlir b/benchmarks/VEIR_ASM/3_function_56.mlir new file mode 100644 index 0000000..74414d3 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_56.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_57.mlir b/benchmarks/VEIR_ASM/3_function_57.mlir new file mode 100644 index 0000000..db8a6b3 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_57.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i1 + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%26) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.sltu"(%23, %13) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_58.mlir b/benchmarks/VEIR_ASM/3_function_58.mlir new file mode 100644 index 0000000..320d617 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_58.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %15 = "riscv.sltu"(%14, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_59.mlir b/benchmarks/VEIR_ASM/3_function_59.mlir new file mode 100644 index 0000000..cd1e706 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_59.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.xor"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.sra"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_6.mlir b/benchmarks/VEIR_ASM/3_function_6.mlir new file mode 100644 index 0000000..88c5a6e --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_6.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_60.mlir b/benchmarks/VEIR_ASM/3_function_60.mlir new file mode 100644 index 0000000..48fe348 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_60.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.div"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.xor"(%21, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_61.mlir b/benchmarks/VEIR_ASM/3_function_61.mlir new file mode 100644 index 0000000..e7d5a73 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_61.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.remu"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.div"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %15 = "riscv.div"(%19, %14) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_62.mlir b/benchmarks/VEIR_ASM/3_function_62.mlir new file mode 100644 index 0000000..dcd3eee --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_62.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.srl"(%23, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.remu"(%19, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_63.mlir b/benchmarks/VEIR_ASM/3_function_63.mlir new file mode 100644 index 0000000..74414d3 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_63.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_64.mlir b/benchmarks/VEIR_ASM/3_function_64.mlir new file mode 100644 index 0000000..8621455 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_64.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.sra"(%23, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.srl"(%23, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_65.mlir b/benchmarks/VEIR_ASM/3_function_65.mlir new file mode 100644 index 0000000..449e608 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_65.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.remu"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_66.mlir b/benchmarks/VEIR_ASM/3_function_66.mlir new file mode 100644 index 0000000..81b671f --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_66.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.srl"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %15 = "riscv.sra"(%22, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_67.mlir b/benchmarks/VEIR_ASM/3_function_67.mlir new file mode 100644 index 0000000..ab9c5a5 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_67.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.sra"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.or"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.divu"(%23, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_68.mlir b/benchmarks/VEIR_ASM/3_function_68.mlir new file mode 100644 index 0000000..5db31e8 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_68.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.rem"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.and"(%21, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_69.mlir b/benchmarks/VEIR_ASM/3_function_69.mlir new file mode 100644 index 0000000..8f0df20 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_69.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.and"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %17 = "riscv.xor"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_7.mlir b/benchmarks/VEIR_ASM/3_function_7.mlir new file mode 100644 index 0000000..677b4c2 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_7.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.srl"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.srl"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.srl"(%13, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_70.mlir b/benchmarks/VEIR_ASM/3_function_70.mlir new file mode 100644 index 0000000..2a132ca --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_70.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %17 = "riscv.sra"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_71.mlir b/benchmarks/VEIR_ASM/3_function_71.mlir new file mode 100644 index 0000000..12be410 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_71.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %17 = "riscv.rem"(%20, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_72.mlir b/benchmarks/VEIR_ASM/3_function_72.mlir new file mode 100644 index 0000000..0e23d26 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_72.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.xor"(%23, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.slt"(%20, %13) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_73.mlir b/benchmarks/VEIR_ASM/3_function_73.mlir new file mode 100644 index 0000000..a359836 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_73.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.and"(%19, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %13 = "builtin.unrealized_conversion_cast"(%17) : (i32) -> !riscv.reg + %14 = "riscv.zext.w"(%13) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%14) : (!riscv.reg) -> i64 + "func.return"(%15) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_74.mlir b/benchmarks/VEIR_ASM/3_function_74.mlir new file mode 100644 index 0000000..7919035 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_74.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.sra"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_75.mlir b/benchmarks/VEIR_ASM/3_function_75.mlir new file mode 100644 index 0000000..122145f --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_75.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.sra"(%23, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.rem"(%23, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_76.mlir b/benchmarks/VEIR_ASM/3_function_76.mlir new file mode 100644 index 0000000..a250c25 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_76.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.or"(%20, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_77.mlir b/benchmarks/VEIR_ASM/3_function_77.mlir new file mode 100644 index 0000000..17b2b67 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_77.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.and"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.srl"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.sltu"(%20, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_78.mlir b/benchmarks/VEIR_ASM/3_function_78.mlir new file mode 100644 index 0000000..33189c0 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_78.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.and"(%16, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_79.mlir b/benchmarks/VEIR_ASM/3_function_79.mlir new file mode 100644 index 0000000..8e022ad --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_79.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.remu"(%20, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_8.mlir b/benchmarks/VEIR_ASM/3_function_8.mlir new file mode 100644 index 0000000..747d3ce --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_8.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.rem"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.xor"(%19, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "riscv.slt"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_80.mlir b/benchmarks/VEIR_ASM/3_function_80.mlir new file mode 100644 index 0000000..b3511ea --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_80.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.div"(%23, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %15 = "riscv.slt"(%20, %14) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_81.mlir b/benchmarks/VEIR_ASM/3_function_81.mlir new file mode 100644 index 0000000..f0eb931 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_81.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.slt"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.xori"(%24) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i1 + %15 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%26) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%15, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_82.mlir b/benchmarks/VEIR_ASM/3_function_82.mlir new file mode 100644 index 0000000..dc4bc51 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_82.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.xor"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.srl"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_83.mlir b/benchmarks/VEIR_ASM/3_function_83.mlir new file mode 100644 index 0000000..3526211 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_83.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.sltu"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.xori"(%24) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i1 + %15 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%26) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%15, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_84.mlir b/benchmarks/VEIR_ASM/3_function_84.mlir new file mode 100644 index 0000000..c536bbf --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_84.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %22 = "riscv.czero.eqz"(%19, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.czero.nez"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.or"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.rem"(%24, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_85.mlir b/benchmarks/VEIR_ASM/3_function_85.mlir new file mode 100644 index 0000000..62f861e --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_85.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.and"(%22, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.or"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.div"(%13, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_86.mlir b/benchmarks/VEIR_ASM/3_function_86.mlir new file mode 100644 index 0000000..4bf52ae --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_86.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i32, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_87.mlir b/benchmarks/VEIR_ASM/3_function_87.mlir new file mode 100644 index 0000000..f05f9d3 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_87.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.sltu"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i1 + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%25) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%15, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_88.mlir b/benchmarks/VEIR_ASM/3_function_88.mlir new file mode 100644 index 0000000..b5908ed --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_88.mlir @@ -0,0 +1,11 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %17 = "riscv.divu"(%20, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_89.mlir b/benchmarks/VEIR_ASM/3_function_89.mlir new file mode 100644 index 0000000..3617088 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_89.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %13 = "builtin.unrealized_conversion_cast"(%17) : (i32) -> !riscv.reg + %14 = "riscv.zext.w"(%13) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%14) : (!riscv.reg) -> i64 + "func.return"(%15) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_9.mlir b/benchmarks/VEIR_ASM/3_function_9.mlir new file mode 100644 index 0000000..d65f8dd --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_9.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%26, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %29 = "riscv.sltu"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i1 + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%30) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.slt"(%14, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_90.mlir b/benchmarks/VEIR_ASM/3_function_90.mlir new file mode 100644 index 0000000..dbff567 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_90.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.rem"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.xor"(%21, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_91.mlir b/benchmarks/VEIR_ASM/3_function_91.mlir new file mode 100644 index 0000000..db9fc9a --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_91.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.divu"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_92.mlir b/benchmarks/VEIR_ASM/3_function_92.mlir new file mode 100644 index 0000000..be8ee8e --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_92.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.sra"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_93.mlir b/benchmarks/VEIR_ASM/3_function_93.mlir new file mode 100644 index 0000000..afc7eb8 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_93.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.sltu"(%26, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.xori"(%27) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i1 + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%29) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "riscv.slt"(%13, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xori"(%15) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_94.mlir b/benchmarks/VEIR_ASM/3_function_94.mlir new file mode 100644 index 0000000..c7c3237 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_94.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.xor"(%20, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_95.mlir b/benchmarks/VEIR_ASM/3_function_95.mlir new file mode 100644 index 0000000..ca14a59 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_95.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.and"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.div"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_96.mlir b/benchmarks/VEIR_ASM/3_function_96.mlir new file mode 100644 index 0000000..2e0078a --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_96.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.rem"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %18 = "riscv.sext.w"(%17) : (!riscv.reg) -> !riscv.reg + %15 = "riscv.divu"(%22, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_97.mlir b/benchmarks/VEIR_ASM/3_function_97.mlir new file mode 100644 index 0000000..40d2bca --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_97.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i1 + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.or"(%21, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%25) : (i1) -> !riscv.reg + %16 = "riscv.czero.eqz"(%13, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.czero.nez"(%22, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.or"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_98.mlir b/benchmarks/VEIR_ASM/3_function_98.mlir new file mode 100644 index 0000000..88c5a6e --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_98.mlir @@ -0,0 +1,12 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%14) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/3_function_99.mlir b/benchmarks/VEIR_ASM/3_function_99.mlir new file mode 100644 index 0000000..11c8c59 --- /dev/null +++ b/benchmarks/VEIR_ASM/3_function_99.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.div"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%24, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%24, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%14) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_0.mlir b/benchmarks/VEIR_ASM/4_function_0.mlir new file mode 100644 index 0000000..2b1c0d5 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_0.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%25, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.and"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %18 = "riscv.srl"(%22, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_1.mlir b/benchmarks/VEIR_ASM/4_function_1.mlir new file mode 100644 index 0000000..3e1f134 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_1.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.rem"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.zext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_10.mlir b/benchmarks/VEIR_ASM/4_function_10.mlir new file mode 100644 index 0000000..6c56d0a --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_10.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.sext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_11.mlir b/benchmarks/VEIR_ASM/4_function_11.mlir new file mode 100644 index 0000000..bb7b9d8 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_11.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "riscv.div"(%21, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_12.mlir b/benchmarks/VEIR_ASM/4_function_12.mlir new file mode 100644 index 0000000..05a75bf --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_12.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.and"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltu"(%21, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xori"(%16) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_13.mlir b/benchmarks/VEIR_ASM/4_function_13.mlir new file mode 100644 index 0000000..fdc86bb --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_13.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.div"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %16 = "riscv.sltu"(%19, %14) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_14.mlir b/benchmarks/VEIR_ASM/4_function_14.mlir new file mode 100644 index 0000000..e966c61 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_14.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.divu"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.divu"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.remu"(%28, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_15.mlir b/benchmarks/VEIR_ASM/4_function_15.mlir new file mode 100644 index 0000000..568c9f7 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_15.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %27 = "riscv.czero.eqz"(%24, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.czero.nez"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.remu"(%29, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "riscv.srl"(%22, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_16.mlir b/benchmarks/VEIR_ASM/4_function_16.mlir new file mode 100644 index 0000000..6ee6f56 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_16.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.srl"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.rem"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltu"(%21, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xori"(%16) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_17.mlir b/benchmarks/VEIR_ASM/4_function_17.mlir new file mode 100644 index 0000000..d6be1da --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_17.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i32): + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %30 = "riscv.sext.w"(%29) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.divu"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %16 = "riscv.rem"(%23, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_18.mlir b/benchmarks/VEIR_ASM/4_function_18.mlir new file mode 100644 index 0000000..1700204 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_18.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.xor"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.xor"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%24, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %16 = "riscv.remu"(%14, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_19.mlir b/benchmarks/VEIR_ASM/4_function_19.mlir new file mode 100644 index 0000000..1afccc7 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_19.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.zext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_2.mlir b/benchmarks/VEIR_ASM/4_function_2.mlir new file mode 100644 index 0000000..7bf871e --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_2.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.sra"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.sext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_20.mlir b/benchmarks/VEIR_ASM/4_function_20.mlir new file mode 100644 index 0000000..f07d584 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_20.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64, %arg6_3 : i32): + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.xor"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%30, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %16 = "riscv.sra"(%14, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_21.mlir b/benchmarks/VEIR_ASM/4_function_21.mlir new file mode 100644 index 0000000..1c2cb0d --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_21.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.div"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.divu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.sra"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %16 = "riscv.slt"(%20, %14) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_22.mlir b/benchmarks/VEIR_ASM/4_function_22.mlir new file mode 100644 index 0000000..9dc0bdb --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_22.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.or"(%25, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.srl"(%26, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "riscv.remu"(%22, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_23.mlir b/benchmarks/VEIR_ASM/4_function_23.mlir new file mode 100644 index 0000000..7a17813 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_23.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i32, %arg6_2 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.or"(%19, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.remu"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_24.mlir b/benchmarks/VEIR_ASM/4_function_24.mlir new file mode 100644 index 0000000..d9bf456 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_24.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.rem"(%29, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i1 + %14 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%22) : (i1) -> !riscv.reg + %17 = "riscv.czero.eqz"(%14, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.czero.nez"(%29, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_25.mlir b/benchmarks/VEIR_ASM/4_function_25.mlir new file mode 100644 index 0000000..baae97a --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_25.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.sra"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%29, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.srl"(%16, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_26.mlir b/benchmarks/VEIR_ASM/4_function_26.mlir new file mode 100644 index 0000000..0fb0498 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_26.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %33 = "riscv.czero.eqz"(%30, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.czero.nez"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.or"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%26, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.sltiu"(%27) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i1 + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%29) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xor"(%23, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_27.mlir b/benchmarks/VEIR_ASM/4_function_27.mlir new file mode 100644 index 0000000..02e7ef3 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_27.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.and"(%22, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.sext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_28.mlir b/benchmarks/VEIR_ASM/4_function_28.mlir new file mode 100644 index 0000000..55d811c --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_28.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.rem"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%24, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.div"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_29.mlir b/benchmarks/VEIR_ASM/4_function_29.mlir new file mode 100644 index 0000000..0c59059 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_29.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "riscv.div"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.rem"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.xor"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.slt"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_3.mlir b/benchmarks/VEIR_ASM/4_function_3.mlir new file mode 100644 index 0000000..6362d05 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_3.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.divu"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i1 + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%26) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%29, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.srl"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_30.mlir b/benchmarks/VEIR_ASM/4_function_30.mlir new file mode 100644 index 0000000..061c734 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_30.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%25, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %16 = "riscv.sltu"(%15, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xori"(%16) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_31.mlir b/benchmarks/VEIR_ASM/4_function_31.mlir new file mode 100644 index 0000000..7008d9f --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_31.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%24, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %14 = "builtin.unrealized_conversion_cast"(%18) : (i32) -> !riscv.reg + %15 = "riscv.zext.w"(%14) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_32.mlir b/benchmarks/VEIR_ASM/4_function_32.mlir new file mode 100644 index 0000000..6ff504f --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_32.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i32): + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%28, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.remu"(%16, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_33.mlir b/benchmarks/VEIR_ASM/4_function_33.mlir new file mode 100644 index 0000000..a0790fb --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_33.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.xor"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.sltiu"(%29) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i1 + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%31) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.xor"(%25, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_34.mlir b/benchmarks/VEIR_ASM/4_function_34.mlir new file mode 100644 index 0000000..3e28a76 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_34.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.divu"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.sra"(%28, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%24, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.srl"(%28, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_35.mlir b/benchmarks/VEIR_ASM/4_function_35.mlir new file mode 100644 index 0000000..f8ee7de --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_35.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %14 = "builtin.unrealized_conversion_cast"(%18) : (i32) -> !riscv.reg + %15 = "riscv.sext.w"(%14) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_36.mlir b/benchmarks/VEIR_ASM/4_function_36.mlir new file mode 100644 index 0000000..0340d3a --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_36.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.or"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.xor"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.remu"(%28, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_37.mlir b/benchmarks/VEIR_ASM/4_function_37.mlir new file mode 100644 index 0000000..891a777 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_37.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.rem"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.and"(%25, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %14 = "builtin.unrealized_conversion_cast"(%18) : (i32) -> !riscv.reg + %15 = "riscv.zext.w"(%14) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_38.mlir b/benchmarks/VEIR_ASM/4_function_38.mlir new file mode 100644 index 0000000..bf4069a --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_38.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.or"(%28, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%19, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltu"(%21, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xori"(%16) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_39.mlir b/benchmarks/VEIR_ASM/4_function_39.mlir new file mode 100644 index 0000000..7de2a20 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_39.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%25, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.or"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.remu"(%16, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_4.mlir b/benchmarks/VEIR_ASM/4_function_4.mlir new file mode 100644 index 0000000..1b49d76 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_4.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.or"(%24, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.xor"(%21, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_40.mlir b/benchmarks/VEIR_ASM/4_function_40.mlir new file mode 100644 index 0000000..e58d3a9 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_40.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%23, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.divu"(%19, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %14 = "builtin.unrealized_conversion_cast"(%18) : (i32) -> !riscv.reg + %15 = "riscv.sext.w"(%14) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_41.mlir b/benchmarks/VEIR_ASM/4_function_41.mlir new file mode 100644 index 0000000..20d0060 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_41.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.div"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.rem"(%26, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.rem"(%16, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_42.mlir b/benchmarks/VEIR_ASM/4_function_42.mlir new file mode 100644 index 0000000..f48fd8b --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_42.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i1, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %30 = "riscv.zext.w"(%29) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.rem"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.and"(%23, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_43.mlir b/benchmarks/VEIR_ASM/4_function_43.mlir new file mode 100644 index 0000000..d5b8b7b --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_43.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %27 = "riscv.czero.eqz"(%24, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.czero.nez"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.remu"(%29, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.or"(%22, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_44.mlir b/benchmarks/VEIR_ASM/4_function_44.mlir new file mode 100644 index 0000000..728629b --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_44.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i32): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.rem"(%26, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %16 = "riscv.remu"(%23, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_45.mlir b/benchmarks/VEIR_ASM/4_function_45.mlir new file mode 100644 index 0000000..3c37058 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_45.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.or"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%29, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.srl"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_46.mlir b/benchmarks/VEIR_ASM/4_function_46.mlir new file mode 100644 index 0000000..8f0fa5a --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_46.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.or"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.or"(%24, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.xor"(%20, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltu"(%21, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xori"(%16) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_47.mlir b/benchmarks/VEIR_ASM/4_function_47.mlir new file mode 100644 index 0000000..fc53b71 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_47.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.rem"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.remu"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.sra"(%16, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_48.mlir b/benchmarks/VEIR_ASM/4_function_48.mlir new file mode 100644 index 0000000..287b89c --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_48.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %22 = "riscv.zext.w"(%21) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.zext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_49.mlir b/benchmarks/VEIR_ASM/4_function_49.mlir new file mode 100644 index 0000000..237320f --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_49.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.divu"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.srl"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.srl"(%16, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_5.mlir b/benchmarks/VEIR_ASM/4_function_5.mlir new file mode 100644 index 0000000..d8079d9 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_5.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.sra"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.sra"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_50.mlir b/benchmarks/VEIR_ASM/4_function_50.mlir new file mode 100644 index 0000000..8ee4931 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_50.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.and"(%25, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.sra"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.or"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_51.mlir b/benchmarks/VEIR_ASM/4_function_51.mlir new file mode 100644 index 0000000..a5544ff --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_51.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.srl"(%20, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.divu"(%25, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_52.mlir b/benchmarks/VEIR_ASM/4_function_52.mlir new file mode 100644 index 0000000..e9a32bd --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_52.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.rem"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.xor"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.srl"(%24, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.slt"(%20, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_53.mlir b/benchmarks/VEIR_ASM/4_function_53.mlir new file mode 100644 index 0000000..500ed8a --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_53.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.and"(%25, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.sra"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "riscv.div"(%22, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_54.mlir b/benchmarks/VEIR_ASM/4_function_54.mlir new file mode 100644 index 0000000..4a7af44 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_54.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.remu"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.divu"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.remu"(%16, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_55.mlir b/benchmarks/VEIR_ASM/4_function_55.mlir new file mode 100644 index 0000000..aedcfca --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_55.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.and"(%25, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.remu"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.divu"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_56.mlir b/benchmarks/VEIR_ASM/4_function_56.mlir new file mode 100644 index 0000000..5477a6f --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_56.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.srl"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %25 = "riscv.czero.eqz"(%22, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.czero.nez"(%31, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.or"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.divu"(%27, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %16 = "riscv.rem"(%14, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_57.mlir b/benchmarks/VEIR_ASM/4_function_57.mlir new file mode 100644 index 0000000..22c6844 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_57.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.or"(%19, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %16 = "riscv.or"(%15, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_58.mlir b/benchmarks/VEIR_ASM/4_function_58.mlir new file mode 100644 index 0000000..a62ca8a --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_58.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.remu"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.xor"(%21, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.div"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_59.mlir b/benchmarks/VEIR_ASM/4_function_59.mlir new file mode 100644 index 0000000..8eabc0a --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_59.mlir @@ -0,0 +1,13 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.sra"(%21, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_6.mlir b/benchmarks/VEIR_ASM/4_function_6.mlir new file mode 100644 index 0000000..e21a9be --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_6.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i32): + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %30 = "riscv.zext.w"(%29) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.srl"(%25, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.or"(%23, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_60.mlir b/benchmarks/VEIR_ASM/4_function_60.mlir new file mode 100644 index 0000000..f8ee7de --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_60.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %14 = "builtin.unrealized_conversion_cast"(%18) : (i32) -> !riscv.reg + %15 = "riscv.sext.w"(%14) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_61.mlir b/benchmarks/VEIR_ASM/4_function_61.mlir new file mode 100644 index 0000000..2611cb5 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_61.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.or"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.div"(%28, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%24, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %16 = "riscv.or"(%15, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_62.mlir b/benchmarks/VEIR_ASM/4_function_62.mlir new file mode 100644 index 0000000..e901ad9 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_62.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.srl"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.divu"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.remu"(%16, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_63.mlir b/benchmarks/VEIR_ASM/4_function_63.mlir new file mode 100644 index 0000000..fe60d38 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_63.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%28, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.rem"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xor"(%22, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %18 = "riscv.sltu"(%17, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_64.mlir b/benchmarks/VEIR_ASM/4_function_64.mlir new file mode 100644 index 0000000..4d70ac3 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_64.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.sra"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %17 = "riscv.czero.eqz"(%23, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.czero.nez"(%15, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_65.mlir b/benchmarks/VEIR_ASM/4_function_65.mlir new file mode 100644 index 0000000..8704b74 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_65.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.rem"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xor"(%24, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltu"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_66.mlir b/benchmarks/VEIR_ASM/4_function_66.mlir new file mode 100644 index 0000000..21c8832 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_66.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.rem"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.sext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_67.mlir b/benchmarks/VEIR_ASM/4_function_67.mlir new file mode 100644 index 0000000..ee4fb53 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_67.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.zext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_68.mlir b/benchmarks/VEIR_ASM/4_function_68.mlir new file mode 100644 index 0000000..18b393e --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_68.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.sext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_69.mlir b/benchmarks/VEIR_ASM/4_function_69.mlir new file mode 100644 index 0000000..d2c2fab --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_69.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.remu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.sra"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.srl"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %17 = "riscv.czero.eqz"(%23, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.czero.nez"(%23, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_7.mlir b/benchmarks/VEIR_ASM/4_function_7.mlir new file mode 100644 index 0000000..0220975 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_7.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.xor"(%30, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.slt"(%31, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i1 + %23 = "riscv.divu"(%31, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%28) : (i1) -> !riscv.reg + %17 = "riscv.czero.eqz"(%14, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.czero.nez"(%23, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_70.mlir b/benchmarks/VEIR_ASM/4_function_70.mlir new file mode 100644 index 0000000..81f9e38 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_70.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.divu"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.sra"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %16 = "riscv.xor"(%19, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_71.mlir b/benchmarks/VEIR_ASM/4_function_71.mlir new file mode 100644 index 0000000..bbf42e9 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_71.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.sra"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.srl"(%28, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.div"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.divu"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_72.mlir b/benchmarks/VEIR_ASM/4_function_72.mlir new file mode 100644 index 0000000..cbbbc18 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_72.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.sra"(%26, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.srl"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_73.mlir b/benchmarks/VEIR_ASM/4_function_73.mlir new file mode 100644 index 0000000..c2dc843 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_73.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i1 + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%28) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.xor"(%25, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_74.mlir b/benchmarks/VEIR_ASM/4_function_74.mlir new file mode 100644 index 0000000..46e2f0f --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_74.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.sltu"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i1 + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%33) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%23, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i1 + %14 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%22) : (i1) -> !riscv.reg + %17 = "riscv.czero.eqz"(%14, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.czero.nez"(%28, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_75.mlir b/benchmarks/VEIR_ASM/4_function_75.mlir new file mode 100644 index 0000000..2f4aaee --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_75.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i32): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %32 = "riscv.czero.eqz"(%29, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.czero.nez"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.xor"(%27, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.sltiu"(%23) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i1 + %14 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%25) : (i1) -> !riscv.reg + %17 = "riscv.czero.eqz"(%14, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.czero.nez"(%34, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_76.mlir b/benchmarks/VEIR_ASM/4_function_76.mlir new file mode 100644 index 0000000..70e1c3c --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_76.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.srl"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_77.mlir b/benchmarks/VEIR_ASM/4_function_77.mlir new file mode 100644 index 0000000..2eec3c3 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_77.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.srl"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %16 = "riscv.div"(%25, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_78.mlir b/benchmarks/VEIR_ASM/4_function_78.mlir new file mode 100644 index 0000000..1c4fd11 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_78.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "riscv.sra"(%21, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_79.mlir b/benchmarks/VEIR_ASM/4_function_79.mlir new file mode 100644 index 0000000..3e1f134 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_79.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.rem"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.zext.w"(%16) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_8.mlir b/benchmarks/VEIR_ASM/4_function_8.mlir new file mode 100644 index 0000000..a501126 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_8.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.xor"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.sltiu"(%29) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i1 + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%24, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%31) : (i1) -> !riscv.reg + %19 = "riscv.czero.eqz"(%25, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.czero.nez"(%25, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_80.mlir b/benchmarks/VEIR_ASM/4_function_80.mlir new file mode 100644 index 0000000..4d2d98b --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_80.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.remu"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.and"(%22, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_81.mlir b/benchmarks/VEIR_ASM/4_function_81.mlir new file mode 100644 index 0000000..c178b36 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_81.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.rem"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.or"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xor"(%24, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.rem"(%20, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_82.mlir b/benchmarks/VEIR_ASM/4_function_82.mlir new file mode 100644 index 0000000..5fbad1b --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_82.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.or"(%24, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %16 = "riscv.xor"(%19, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_83.mlir b/benchmarks/VEIR_ASM/4_function_83.mlir new file mode 100644 index 0000000..fe25323 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_83.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "riscv.div"(%21, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_84.mlir b/benchmarks/VEIR_ASM/4_function_84.mlir new file mode 100644 index 0000000..9ca6e6e --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_84.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.remu"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_85.mlir b/benchmarks/VEIR_ASM/4_function_85.mlir new file mode 100644 index 0000000..9453887 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_85.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.or"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.or"(%23, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.srl"(%28, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %16 = "riscv.srl"(%20, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_86.mlir b/benchmarks/VEIR_ASM/4_function_86.mlir new file mode 100644 index 0000000..310494f --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_86.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.or"(%26, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i1 + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%24) : (i1) -> !riscv.reg + %19 = "riscv.czero.eqz"(%16, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.czero.nez"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_87.mlir b/benchmarks/VEIR_ASM/4_function_87.mlir new file mode 100644 index 0000000..909f8f1 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_87.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.and"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_88.mlir b/benchmarks/VEIR_ASM/4_function_88.mlir new file mode 100644 index 0000000..01417f6 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_88.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.divu"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.and"(%20, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %14 = "builtin.unrealized_conversion_cast"(%18) : (i32) -> !riscv.reg + %15 = "riscv.sext.w"(%14) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_89.mlir b/benchmarks/VEIR_ASM/4_function_89.mlir new file mode 100644 index 0000000..295704c --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_89.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.srl"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.xor"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %18 = "riscv.or"(%17, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_9.mlir b/benchmarks/VEIR_ASM/4_function_9.mlir new file mode 100644 index 0000000..162c17c --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_9.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.or"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.sra"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.div"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.slt"(%28, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_90.mlir b/benchmarks/VEIR_ASM/4_function_90.mlir new file mode 100644 index 0000000..0798eef --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_90.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.srl"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.remu"(%26, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.xor"(%22, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_91.mlir b/benchmarks/VEIR_ASM/4_function_91.mlir new file mode 100644 index 0000000..9554889 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_91.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "riscv.sra"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.or"(%28, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.sra"(%18, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.div"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_92.mlir b/benchmarks/VEIR_ASM/4_function_92.mlir new file mode 100644 index 0000000..98eadaa --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_92.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.div"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.and"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.xor"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_93.mlir b/benchmarks/VEIR_ASM/4_function_93.mlir new file mode 100644 index 0000000..e3197ff --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_93.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.and"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.xor"(%28, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.or"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltu"(%20, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_94.mlir b/benchmarks/VEIR_ASM/4_function_94.mlir new file mode 100644 index 0000000..abeb09b --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_94.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.divu"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i1 + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%26) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%29, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltu"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_95.mlir b/benchmarks/VEIR_ASM/4_function_95.mlir new file mode 100644 index 0000000..840b71d --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_95.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "riscv.remu"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.and"(%25, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.sltu"(%25, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xori"(%16) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_96.mlir b/benchmarks/VEIR_ASM/4_function_96.mlir new file mode 100644 index 0000000..8b1058c --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_96.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.and"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.srl"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "riscv.slt"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_97.mlir b/benchmarks/VEIR_ASM/4_function_97.mlir new file mode 100644 index 0000000..f484bf7 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_97.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.rem"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.sra"(%22, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%15) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_98.mlir b/benchmarks/VEIR_ASM/4_function_98.mlir new file mode 100644 index 0000000..fe7a2e3 --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_98.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + %14 = "builtin.unrealized_conversion_cast"(%18) : (i32) -> !riscv.reg + %15 = "riscv.zext.w"(%14) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%15) : (!riscv.reg) -> i64 + "func.return"(%16) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/4_function_99.mlir b/benchmarks/VEIR_ASM/4_function_99.mlir new file mode 100644 index 0000000..a91731f --- /dev/null +++ b/benchmarks/VEIR_ASM/4_function_99.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %18 = "riscv.or"(%17, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%15) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_0.mlir b/benchmarks/VEIR_ASM/5_function_0.mlir new file mode 100644 index 0000000..d28d8e2 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_0.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %30 = "riscv.sext.w"(%29) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.remu"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.div"(%30, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "riscv.remu"(%23, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_1.mlir b/benchmarks/VEIR_ASM/5_function_1.mlir new file mode 100644 index 0000000..dbbd21b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_1.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %26 = "riscv.sra"(%29, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %22 = "riscv.zext.w"(%21) : (!riscv.reg) -> !riscv.reg + %19 = "riscv.remu"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_10.mlir b/benchmarks/VEIR_ASM/5_function_10.mlir new file mode 100644 index 0000000..29176e5 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_10.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.zext.w"(%27) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.srl"(%28, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.rem"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.remu"(%28, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_11.mlir b/benchmarks/VEIR_ASM/5_function_11.mlir new file mode 100644 index 0000000..1a933cf --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_11.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.div"(%26, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_12.mlir b/benchmarks/VEIR_ASM/5_function_12.mlir new file mode 100644 index 0000000..6638970 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_12.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.srl"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.div"(%31, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.slt"(%28, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i1 + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%30) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.slt"(%25, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xori"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_13.mlir b/benchmarks/VEIR_ASM/5_function_13.mlir new file mode 100644 index 0000000..8182125 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_13.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.div"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %28 = "riscv.zext.w"(%27) : (!riscv.reg) -> !riscv.reg + %25 = "riscv.srl"(%28, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.div"(%25, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.slt"(%32, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_14.mlir b/benchmarks/VEIR_ASM/5_function_14.mlir new file mode 100644 index 0000000..4dd51b2 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_14.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.sltu"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.xori"(%36) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%37) : (!riscv.reg) -> i1 + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.remu"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%32, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%38) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%32, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%24, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_15.mlir b/benchmarks/VEIR_ASM/5_function_15.mlir new file mode 100644 index 0000000..48139de --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_15.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.or"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.slt"(%34, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i1 + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%31) : (i1) -> !riscv.reg + %24 = "riscv.czero.eqz"(%21, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.czero.nez"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "riscv.div"(%26, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_16.mlir b/benchmarks/VEIR_ASM/5_function_16.mlir new file mode 100644 index 0000000..51319d9 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_16.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.divu"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.div"(%24, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.divu"(%26, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_17.mlir b/benchmarks/VEIR_ASM/5_function_17.mlir new file mode 100644 index 0000000..e1d9bc7 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_17.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.divu"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.or"(%25, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %22 = "riscv.zext.w"(%21) : (!riscv.reg) -> !riscv.reg + %19 = "riscv.sra"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_18.mlir b/benchmarks/VEIR_ASM/5_function_18.mlir new file mode 100644 index 0000000..160decc --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_18.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.sra"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.rem"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.div"(%31, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.remu"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_19.mlir b/benchmarks/VEIR_ASM/5_function_19.mlir new file mode 100644 index 0000000..b5e7c14 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_19.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.or"(%31, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.sra"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.remu"(%32, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %17 = "riscv.sltu"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_2.mlir b/benchmarks/VEIR_ASM/5_function_2.mlir new file mode 100644 index 0000000..84898f0 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_2.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.xor"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.divu"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.and"(%29, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.remu"(%15, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_20.mlir b/benchmarks/VEIR_ASM/5_function_20.mlir new file mode 100644 index 0000000..3d74b5b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_20.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.or"(%30, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.srl"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.xor"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_21.mlir b/benchmarks/VEIR_ASM/5_function_21.mlir new file mode 100644 index 0000000..2dbacf0 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_21.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.srl"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i1 + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%28) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%31, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_22.mlir b/benchmarks/VEIR_ASM/5_function_22.mlir new file mode 100644 index 0000000..0239b23 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_22.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%26, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_23.mlir b/benchmarks/VEIR_ASM/5_function_23.mlir new file mode 100644 index 0000000..b78390a --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_23.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_24.mlir b/benchmarks/VEIR_ASM/5_function_24.mlir new file mode 100644 index 0000000..485ca76 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_24.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.rem"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%26, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.and"(%22, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.srl"(%31, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_25.mlir b/benchmarks/VEIR_ASM/5_function_25.mlir new file mode 100644 index 0000000..e085509 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_25.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.div"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %30 = "riscv.czero.eqz"(%27, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.czero.nez"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.or"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.remu"(%36, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.and"(%20, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.or"(%21, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_26.mlir b/benchmarks/VEIR_ASM/5_function_26.mlir new file mode 100644 index 0000000..70a354b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_26.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.remu"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.xor"(%28, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.sext.w"(%17) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_27.mlir b/benchmarks/VEIR_ASM/5_function_27.mlir new file mode 100644 index 0000000..2468510 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_27.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.and"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.slt"(%34, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i1 + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.rem"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%31) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%17, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_28.mlir b/benchmarks/VEIR_ASM/5_function_28.mlir new file mode 100644 index 0000000..9e65bc7 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_28.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.divu"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.div"(%34, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.rem"(%30, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%30, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_29.mlir b/benchmarks/VEIR_ASM/5_function_29.mlir new file mode 100644 index 0000000..3b7c43d --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_29.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.and"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.div"(%30, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %17 = "riscv.rem"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_3.mlir b/benchmarks/VEIR_ASM/5_function_3.mlir new file mode 100644 index 0000000..277c881 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_3.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.rem"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%30, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%26, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_30.mlir b/benchmarks/VEIR_ASM/5_function_30.mlir new file mode 100644 index 0000000..cd502ec --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_30.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.div"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.divu"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.div"(%27, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.or"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_31.mlir b/benchmarks/VEIR_ASM/5_function_31.mlir new file mode 100644 index 0000000..6e840a6 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_31.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.srl"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.slt"(%29, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.xori"(%31) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i1 + %26 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%33) : (i1) -> !riscv.reg + %22 = "riscv.czero.eqz"(%19, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.czero.nez"(%27, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.or"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.xor"(%16, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_32.mlir b/benchmarks/VEIR_ASM/5_function_32.mlir new file mode 100644 index 0000000..5b09836 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_32.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.and"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.xor"(%23, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_33.mlir b/benchmarks/VEIR_ASM/5_function_33.mlir new file mode 100644 index 0000000..1c9dea1 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_33.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.divu"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.and"(%34, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %24 = "riscv.czero.eqz"(%21, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.czero.nez"(%30, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.and"(%26, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_34.mlir b/benchmarks/VEIR_ASM/5_function_34.mlir new file mode 100644 index 0000000..75b007e --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_34.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %34 = "riscv.zext.w"(%33) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.xor"(%34, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.xor"(%31, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.or"(%34, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xor"(%23, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %19 = "riscv.sltu"(%18, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_35.mlir b/benchmarks/VEIR_ASM/5_function_35.mlir new file mode 100644 index 0000000..ca599e0 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_35.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.and"(%30, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.sra"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.srl"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_36.mlir b/benchmarks/VEIR_ASM/5_function_36.mlir new file mode 100644 index 0000000..9061329 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_36.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.remu"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.srl"(%28, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_37.mlir b/benchmarks/VEIR_ASM/5_function_37.mlir new file mode 100644 index 0000000..9740b26 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_37.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i1 + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.or"(%29, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%32) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%17, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_38.mlir b/benchmarks/VEIR_ASM/5_function_38.mlir new file mode 100644 index 0000000..bba4aa8 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_38.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.rem"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.and"(%29, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %24 = "riscv.czero.eqz"(%34, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.czero.nez"(%30, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.div"(%34, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_39.mlir b/benchmarks/VEIR_ASM/5_function_39.mlir new file mode 100644 index 0000000..e3bd643 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_39.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32): + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %31 = "riscv.zext.w"(%30) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i1 + %26 = "riscv.xor"(%31, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%29) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%31, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_4.mlir b/benchmarks/VEIR_ASM/5_function_4.mlir new file mode 100644 index 0000000..1bf5ee5 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_4.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %30 = "riscv.sext.w"(%29) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.div"(%25, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "riscv.or"(%18, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_40.mlir b/benchmarks/VEIR_ASM/5_function_40.mlir new file mode 100644 index 0000000..63eff78 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_40.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.xor"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.and"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.remu"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.sra"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.sra"(%25, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_41.mlir b/benchmarks/VEIR_ASM/5_function_41.mlir new file mode 100644 index 0000000..568f8bd --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_41.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%26, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %21 = "builtin.unrealized_conversion_cast"(%25) : (i32) -> !riscv.reg + %22 = "riscv.zext.w"(%21) : (!riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%22, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_42.mlir b/benchmarks/VEIR_ASM/5_function_42.mlir new file mode 100644 index 0000000..4bd6d50 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_42.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.sra"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.xor"(%29, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%30, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.divu"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xor"(%22, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.sltiu"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_43.mlir b/benchmarks/VEIR_ASM/5_function_43.mlir new file mode 100644 index 0000000..551b65f --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_43.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.srl"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.rem"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.remu"(%31, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %19 = "riscv.and"(%18, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_44.mlir b/benchmarks/VEIR_ASM/5_function_44.mlir new file mode 100644 index 0000000..c1aa7f5 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_44.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.xor"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.or"(%25, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.or"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_45.mlir b/benchmarks/VEIR_ASM/5_function_45.mlir new file mode 100644 index 0000000..69304ae --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_45.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %30 = "riscv.zext.w"(%29) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.div"(%25, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.xor"(%27, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "riscv.or"(%18, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_46.mlir b/benchmarks/VEIR_ASM/5_function_46.mlir new file mode 100644 index 0000000..e32cc25 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_46.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.sext.w"(%17) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_47.mlir b/benchmarks/VEIR_ASM/5_function_47.mlir new file mode 100644 index 0000000..a131bb0 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_47.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.divu"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%28, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.remu"(%33, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%37, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xor"(%22, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.sltiu"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_48.mlir b/benchmarks/VEIR_ASM/5_function_48.mlir new file mode 100644 index 0000000..8ee82a0 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_48.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.xor"(%30, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.divu"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.xor"(%31, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sra"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_49.mlir b/benchmarks/VEIR_ASM/5_function_49.mlir new file mode 100644 index 0000000..2988b0c --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_49.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.rem"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.div"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.xor"(%27, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.srl"(%23, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_5.mlir b/benchmarks/VEIR_ASM/5_function_5.mlir new file mode 100644 index 0000000..3e7243f --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_5.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.remu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.divu"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.divu"(%23, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_50.mlir b/benchmarks/VEIR_ASM/5_function_50.mlir new file mode 100644 index 0000000..b0ef63e --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_50.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.srl"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.and"(%23, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_51.mlir b/benchmarks/VEIR_ASM/5_function_51.mlir new file mode 100644 index 0000000..d1bd3b5 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_51.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.or"(%30, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.srl"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.remu"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.and"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_52.mlir b/benchmarks/VEIR_ASM/5_function_52.mlir new file mode 100644 index 0000000..c5ce27c --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_52.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.srl"(%28, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.div"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.or"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_53.mlir b/benchmarks/VEIR_ASM/5_function_53.mlir new file mode 100644 index 0000000..d55489b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_53.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.rem"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.xor"(%34, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.sltiu"(%29) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i1 + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%31) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_54.mlir b/benchmarks/VEIR_ASM/5_function_54.mlir new file mode 100644 index 0000000..4f36c52 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_54.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.xor"(%30, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.div"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.divu"(%31, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.and"(%31, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_55.mlir b/benchmarks/VEIR_ASM/5_function_55.mlir new file mode 100644 index 0000000..0a3fc25 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_55.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "riscv.slt"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.xori"(%40) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%41) : (!riscv.reg) -> i1 + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%42) : (i1) -> !riscv.reg + %34 = "riscv.czero.eqz"(%31, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.czero.nez"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.or"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.remu"(%36, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%42) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%29, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.slt"(%25, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xori"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_56.mlir b/benchmarks/VEIR_ASM/5_function_56.mlir new file mode 100644 index 0000000..ba0bc8b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_56.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.divu"(%26, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_57.mlir b/benchmarks/VEIR_ASM/5_function_57.mlir new file mode 100644 index 0000000..3ec0775 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_57.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.and"(%34, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%24, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i1 + %15 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (i1) -> !riscv.reg + %18 = "riscv.czero.eqz"(%15, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.czero.nez"(%16, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_58.mlir b/benchmarks/VEIR_ASM/5_function_58.mlir new file mode 100644 index 0000000..e1bbdfc --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_58.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.or"(%29, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.xor"(%26, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_59.mlir b/benchmarks/VEIR_ASM/5_function_59.mlir new file mode 100644 index 0000000..6b7f2b9 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_59.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.sra"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.and"(%26, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.divu"(%31, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.and"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_6.mlir b/benchmarks/VEIR_ASM/5_function_6.mlir new file mode 100644 index 0000000..f94a407 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_6.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.rem"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.xor"(%21, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.sltiu"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_60.mlir b/benchmarks/VEIR_ASM/5_function_60.mlir new file mode 100644 index 0000000..b61eb15 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_60.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %31 = "builtin.unrealized_conversion_cast"(%35) : (i32) -> !riscv.reg + %32 = "riscv.sext.w"(%31) : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.and"(%32, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%29, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.xor"(%25, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.sltiu"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_61.mlir b/benchmarks/VEIR_ASM/5_function_61.mlir new file mode 100644 index 0000000..ac21134 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_61.mlir @@ -0,0 +1,14 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i32): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.div"(%26, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.srl"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_62.mlir b/benchmarks/VEIR_ASM/5_function_62.mlir new file mode 100644 index 0000000..c3dce9c --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_62.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.or"(%30, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.rem"(%34, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_63.mlir b/benchmarks/VEIR_ASM/5_function_63.mlir new file mode 100644 index 0000000..a8fd10b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_63.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.xor"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %21 = "builtin.unrealized_conversion_cast"(%25) : (i32) -> !riscv.reg + %22 = "riscv.zext.w"(%21) : (!riscv.reg) -> !riscv.reg + %19 = "riscv.div"(%28, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_64.mlir b/benchmarks/VEIR_ASM/5_function_64.mlir new file mode 100644 index 0000000..fce56cc --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_64.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.divu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.or"(%26, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.remu"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.or"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_65.mlir b/benchmarks/VEIR_ASM/5_function_65.mlir new file mode 100644 index 0000000..01153d5 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_65.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.rem"(%20, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_66.mlir b/benchmarks/VEIR_ASM/5_function_66.mlir new file mode 100644 index 0000000..d8ed672 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_66.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.remu"(%15, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_67.mlir b/benchmarks/VEIR_ASM/5_function_67.mlir new file mode 100644 index 0000000..0770114 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_67.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.srl"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.divu"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.srl"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_68.mlir b/benchmarks/VEIR_ASM/5_function_68.mlir new file mode 100644 index 0000000..8d77e54 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_68.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.rem"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.div"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.rem"(%27, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.div"(%31, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_69.mlir b/benchmarks/VEIR_ASM/5_function_69.mlir new file mode 100644 index 0000000..615b58c --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_69.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.or"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.or"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.div"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.and"(%20, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.sltu"(%21, %15) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_7.mlir b/benchmarks/VEIR_ASM/5_function_7.mlir new file mode 100644 index 0000000..8a6f33a --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_7.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.sra"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.or"(%31, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.div"(%31, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.remu"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_70.mlir b/benchmarks/VEIR_ASM/5_function_70.mlir new file mode 100644 index 0000000..9d59960 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_70.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.srl"(%24, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%18, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_71.mlir b/benchmarks/VEIR_ASM/5_function_71.mlir new file mode 100644 index 0000000..f971ddb --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_71.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%25, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_72.mlir b/benchmarks/VEIR_ASM/5_function_72.mlir new file mode 100644 index 0000000..dc1a12f --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_72.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.rem"(%21, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.or"(%23, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_73.mlir b/benchmarks/VEIR_ASM/5_function_73.mlir new file mode 100644 index 0000000..5026967 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_73.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.divu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.sra"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.remu"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_74.mlir b/benchmarks/VEIR_ASM/5_function_74.mlir new file mode 100644 index 0000000..04627e8 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_74.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i32): + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %33 = "riscv.sext.w"(%32) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%25, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.and"(%30, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.srl"(%23, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_75.mlir b/benchmarks/VEIR_ASM/5_function_75.mlir new file mode 100644 index 0000000..88e7516 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_75.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.xor"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.and"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.div"(%19, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.rem"(%25, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_76.mlir b/benchmarks/VEIR_ASM/5_function_76.mlir new file mode 100644 index 0000000..ed4581b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_76.mlir @@ -0,0 +1,15 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.or"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.divu"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sra"(%30, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_77.mlir b/benchmarks/VEIR_ASM/5_function_77.mlir new file mode 100644 index 0000000..7cf26a0 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_77.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.srl"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.div"(%30, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.and"(%21, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_78.mlir b/benchmarks/VEIR_ASM/5_function_78.mlir new file mode 100644 index 0000000..cbb8736 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_78.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.div"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.srl"(%30, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %22 = "riscv.zext.w"(%21) : (!riscv.reg) -> !riscv.reg + %19 = "riscv.rem"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_79.mlir b/benchmarks/VEIR_ASM/5_function_79.mlir new file mode 100644 index 0000000..9de3836 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_79.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.or"(%30, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.srl"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %17 = "riscv.sltu"(%21, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xori"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_8.mlir b/benchmarks/VEIR_ASM/5_function_8.mlir new file mode 100644 index 0000000..2e01ffc --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_8.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.div"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%31, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.rem"(%23, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_80.mlir b/benchmarks/VEIR_ASM/5_function_80.mlir new file mode 100644 index 0000000..005263a --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_80.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.div"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%24, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.sra"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.zext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_81.mlir b/benchmarks/VEIR_ASM/5_function_81.mlir new file mode 100644 index 0000000..6420c7b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_81.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.remu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.sext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.and"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.sltu"(%31, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xori"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_82.mlir b/benchmarks/VEIR_ASM/5_function_82.mlir new file mode 100644 index 0000000..86115c3 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_82.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.or"(%25, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.srl"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.sltu"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xori"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_83.mlir b/benchmarks/VEIR_ASM/5_function_83.mlir new file mode 100644 index 0000000..875b940 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_83.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.or"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %26 = "riscv.sra"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.div"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.slt"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xori"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_84.mlir b/benchmarks/VEIR_ASM/5_function_84.mlir new file mode 100644 index 0000000..9bf38d0 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_84.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %32 = "riscv.czero.eqz"(%29, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.czero.nez"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.or"(%34, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.and"(%22, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sra"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_85.mlir b/benchmarks/VEIR_ASM/5_function_85.mlir new file mode 100644 index 0000000..6c3bba8 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_85.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %24 = "riscv.zext.w"(%23) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.srl"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.div"(%27, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_86.mlir b/benchmarks/VEIR_ASM/5_function_86.mlir new file mode 100644 index 0000000..d5fd29a --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_86.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.div"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.and"(%31, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%36, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%32, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%28, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.or"(%21, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_87.mlir b/benchmarks/VEIR_ASM/5_function_87.mlir new file mode 100644 index 0000000..7fa72ff --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_87.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i1 + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.div"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%33) : (i1) -> !riscv.reg + %24 = "riscv.czero.eqz"(%21, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.czero.nez"(%30, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.or"(%26, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_88.mlir b/benchmarks/VEIR_ASM/5_function_88.mlir new file mode 100644 index 0000000..6e6528e --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_88.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.or"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.srl"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.sext.w"(%17) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_89.mlir b/benchmarks/VEIR_ASM/5_function_89.mlir new file mode 100644 index 0000000..ef1c1fb --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_89.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.sra"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %24 = "riscv.czero.eqz"(%21, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.czero.nez"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.and"(%26, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_9.mlir b/benchmarks/VEIR_ASM/5_function_9.mlir new file mode 100644 index 0000000..cd63b6c --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_9.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %32 = "riscv.czero.eqz"(%29, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.czero.nez"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%26, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.sra"(%21, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sra"(%34, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_90.mlir b/benchmarks/VEIR_ASM/5_function_90.mlir new file mode 100644 index 0000000..8997c29 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_90.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.divu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.sra"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.sra"(%21, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.rem"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_91.mlir b/benchmarks/VEIR_ASM/5_function_91.mlir new file mode 100644 index 0000000..fc51549 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_91.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.divu"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.and"(%26, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.and"(%23, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_92.mlir b/benchmarks/VEIR_ASM/5_function_92.mlir new file mode 100644 index 0000000..e60a24a --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_92.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.sext.w"(%24) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.xor"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + %15 = "builtin.unrealized_conversion_cast"(%19) : (i32) -> !riscv.reg + %16 = "riscv.sext.w"(%15) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%16) : (!riscv.reg) -> i64 + "func.return"(%17) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_93.mlir b/benchmarks/VEIR_ASM/5_function_93.mlir new file mode 100644 index 0000000..d546dde --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_93.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.rem"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i1 + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%32) : (i1) -> !riscv.reg + %27 = "riscv.czero.eqz"(%24, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.czero.nez"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.divu"(%35, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %17 = "riscv.slt"(%15, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xori"(%17) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_94.mlir b/benchmarks/VEIR_ASM/5_function_94.mlir new file mode 100644 index 0000000..5f876fd --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_94.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.and"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.srl"(%19, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "riscv.div"(%24, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_95.mlir b/benchmarks/VEIR_ASM/5_function_95.mlir new file mode 100644 index 0000000..3aa446b --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_95.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.or"(%30, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.or"(%26, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.srl"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.srl"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_96.mlir b/benchmarks/VEIR_ASM/5_function_96.mlir new file mode 100644 index 0000000..c03d4e5 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_96.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.remu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.srl"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.and"(%27, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.rem"(%23, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_97.mlir b/benchmarks/VEIR_ASM/5_function_97.mlir new file mode 100644 index 0000000..189c896 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_97.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%24, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %17 = "riscv.rem"(%21, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_98.mlir b/benchmarks/VEIR_ASM/5_function_98.mlir new file mode 100644 index 0000000..17e3f89 --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_98.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %32 = "riscv.czero.eqz"(%29, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.czero.nez"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.srl"(%25, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.div"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.and"(%23, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%16) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/5_function_99.mlir b/benchmarks/VEIR_ASM/5_function_99.mlir new file mode 100644 index 0000000..937b50e --- /dev/null +++ b/benchmarks/VEIR_ASM/5_function_99.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %32 = "riscv.czero.eqz"(%29, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.czero.nez"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%26, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.div"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.divu"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%16) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_0.mlir b/benchmarks/VEIR_ASM/6_function_0.mlir new file mode 100644 index 0000000..4bcd050 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_0.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %42 = "riscv.czero.eqz"(%39, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.czero.nez"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.or"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.rem"(%35, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%28, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.div"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.remu"(%26, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.or"(%37, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_1.mlir b/benchmarks/VEIR_ASM/6_function_1.mlir new file mode 100644 index 0000000..d2bf5ec --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_1.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.divu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.srl"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xor"(%24, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_10.mlir b/benchmarks/VEIR_ASM/6_function_10.mlir new file mode 100644 index 0000000..340aca9 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_10.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.xor"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.div"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.div"(%26, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.divu"(%36, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.srl"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_11.mlir b/benchmarks/VEIR_ASM/6_function_11.mlir new file mode 100644 index 0000000..d5e8179 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_11.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.rem"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %31 = "builtin.unrealized_conversion_cast"(%35) : (i32) -> !riscv.reg + %32 = "riscv.sext.w"(%31) : (!riscv.reg) -> !riscv.reg + %29 = "riscv.and"(%32, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%38, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.srl"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_12.mlir b/benchmarks/VEIR_ASM/6_function_12.mlir new file mode 100644 index 0000000..88fd52e --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_12.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.div"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.and"(%31, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.sra"(%36, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.and"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_13.mlir b/benchmarks/VEIR_ASM/6_function_13.mlir new file mode 100644 index 0000000..fc5f76c --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_13.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %35 = "riscv.zext.w"(%34) : (!riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.rem"(%30, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "riscv.srl"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.div"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sra"(%32, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_14.mlir b/benchmarks/VEIR_ASM/6_function_14.mlir new file mode 100644 index 0000000..97392a6 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_14.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i1): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "riscv.rem"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%41, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%25, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%37, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.rem"(%30, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.sext.w"(%16) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_15.mlir b/benchmarks/VEIR_ASM/6_function_15.mlir new file mode 100644 index 0000000..cb9a76b --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_15.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.srl"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.srl"(%36, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.rem"(%26, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.remu"(%28, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_16.mlir b/benchmarks/VEIR_ASM/6_function_16.mlir new file mode 100644 index 0000000..222c3e7 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_16.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i32): + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %39 = "riscv.czero.eqz"(%36, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.czero.nez"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.or"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %34 = "riscv.sext.w"(%33) : (!riscv.reg) -> !riscv.reg + %31 = "riscv.srl"(%41, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.remu"(%41, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.div"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xor"(%23, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sltiu"(%18) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_17.mlir b/benchmarks/VEIR_ASM/6_function_17.mlir new file mode 100644 index 0000000..d212c54 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_17.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.rem"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.xor"(%35, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.sext.w"(%24) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.xor"(%21, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xor"(%22, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_18.mlir b/benchmarks/VEIR_ASM/6_function_18.mlir new file mode 100644 index 0000000..9116183 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_18.mlir @@ -0,0 +1,28 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.or"(%45, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %40 = "riscv.czero.eqz"(%37, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.czero.nez"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "riscv.or"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.sra"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%35, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%35, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.srl"(%42, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xor"(%24, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %20 = "riscv.sltu"(%19, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_19.mlir b/benchmarks/VEIR_ASM/6_function_19.mlir new file mode 100644 index 0000000..c182d18 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_19.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "riscv.remu"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.div"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i1 + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%32) : (i1) -> !riscv.reg + %27 = "riscv.czero.eqz"(%24, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.czero.nez"(%35, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.div"(%39, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.srl"(%22, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_2.mlir b/benchmarks/VEIR_ASM/6_function_2.mlir new file mode 100644 index 0000000..e7b032e --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_2.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.remu"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.rem"(%30, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "riscv.xor"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.xor"(%32, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.rem"(%32, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_20.mlir b/benchmarks/VEIR_ASM/6_function_20.mlir new file mode 100644 index 0000000..55744ac --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_20.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.rem"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.and"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.rem"(%24, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_21.mlir b/benchmarks/VEIR_ASM/6_function_21.mlir new file mode 100644 index 0000000..bd52530 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_21.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i32): + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %40 = "riscv.sext.w"(%39) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%32, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%40, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.div"(%40, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.xor"(%30, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.xor"(%30, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.or"(%22, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_22.mlir b/benchmarks/VEIR_ASM/6_function_22.mlir new file mode 100644 index 0000000..3e352d4 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_22.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.or"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.rem"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.rem"(%29, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_23.mlir b/benchmarks/VEIR_ASM/6_function_23.mlir new file mode 100644 index 0000000..65d7c2f --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_23.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %40 = "riscv.czero.eqz"(%37, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.czero.nez"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "riscv.or"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.or"(%42, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.srl"(%35, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.remu"(%35, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.rem"(%27, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.slt"(%42, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.xori"(%18) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_24.mlir b/benchmarks/VEIR_ASM/6_function_24.mlir new file mode 100644 index 0000000..6365263 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_24.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.xor"(%36, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.div"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i1 + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (i1) -> !riscv.reg + %25 = "riscv.czero.eqz"(%22, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.czero.nez"(%37, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.or"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.divu"(%37, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_25.mlir b/benchmarks/VEIR_ASM/6_function_25.mlir new file mode 100644 index 0000000..d45e9cb --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_25.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %34 = "riscv.sext.w"(%33) : (!riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.rem"(%34, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.remu"(%34, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.sra"(%27, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_26.mlir b/benchmarks/VEIR_ASM/6_function_26.mlir new file mode 100644 index 0000000..58cdd69 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_26.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %33 = "riscv.czero.eqz"(%30, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.czero.nez"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.or"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.rem"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_27.mlir b/benchmarks/VEIR_ASM/6_function_27.mlir new file mode 100644 index 0000000..8a646eb --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_27.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.rem"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.and"(%35, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.and"(%26, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%27, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.sext.w"(%16) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_28.mlir b/benchmarks/VEIR_ASM/6_function_28.mlir new file mode 100644 index 0000000..1dc13ef --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_28.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.div"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.and"(%28, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.sra"(%18, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_29.mlir b/benchmarks/VEIR_ASM/6_function_29.mlir new file mode 100644 index 0000000..e0aa87a --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_29.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.div"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.srl"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.or"(%19, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_3.mlir b/benchmarks/VEIR_ASM/6_function_3.mlir new file mode 100644 index 0000000..841eab5 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_3.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.slt"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.xori"(%36) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%37) : (!riscv.reg) -> i1 + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.rem"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%38) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%32, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_30.mlir b/benchmarks/VEIR_ASM/6_function_30.mlir new file mode 100644 index 0000000..e63bb79 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_30.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.sra"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.srl"(%35, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.srl"(%31, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.divu"(%21, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.zext.w"(%16) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_31.mlir b/benchmarks/VEIR_ASM/6_function_31.mlir new file mode 100644 index 0000000..b106fab --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_31.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %32 = "builtin.unrealized_conversion_cast"(%36) : (i32) -> !riscv.reg + %33 = "riscv.sext.w"(%32) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%36) : (i32) -> !riscv.reg + %30 = "riscv.zext.w"(%29) : (!riscv.reg) -> !riscv.reg + %27 = "riscv.div"(%33, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.sra"(%27, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.sltu"(%23, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.xori"(%18) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_32.mlir b/benchmarks/VEIR_ASM/6_function_32.mlir new file mode 100644 index 0000000..7cc8e95 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_32.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i32): + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %34 = "riscv.zext.w"(%33) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.xor"(%34, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %24 = "riscv.divu"(%27, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.rem"(%31, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_33.mlir b/benchmarks/VEIR_ASM/6_function_33.mlir new file mode 100644 index 0000000..7c573a1 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_33.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.or"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.or"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sra"(%27, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_34.mlir b/benchmarks/VEIR_ASM/6_function_34.mlir new file mode 100644 index 0000000..e8e6c01 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_34.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.xor"(%39, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i1 + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%37) : (i1) -> !riscv.reg + %32 = "riscv.czero.eqz"(%29, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.czero.nez"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %25 = "riscv.czero.eqz"(%40, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.czero.nez"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.or"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.rem"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_35.mlir b/benchmarks/VEIR_ASM/6_function_35.mlir new file mode 100644 index 0000000..de43a41 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_35.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %36 = "riscv.sext.w"(%35) : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.rem"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.divu"(%36, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.srl"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.div"(%16, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_36.mlir b/benchmarks/VEIR_ASM/6_function_36.mlir new file mode 100644 index 0000000..112e56a --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_36.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.or"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %24 = "riscv.xor"(%27, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.srl"(%33, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_37.mlir b/benchmarks/VEIR_ASM/6_function_37.mlir new file mode 100644 index 0000000..a6147e4 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_37.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.remu"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.div"(%35, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.remu"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.div"(%31, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.zext.w"(%16) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_38.mlir b/benchmarks/VEIR_ASM/6_function_38.mlir new file mode 100644 index 0000000..bea7841 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_38.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.xor"(%34, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.remu"(%29, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.srl"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.and"(%23, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_39.mlir b/benchmarks/VEIR_ASM/6_function_39.mlir new file mode 100644 index 0000000..9d230af --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_39.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.divu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %24 = "riscv.rem"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.divu"(%24, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_4.mlir b/benchmarks/VEIR_ASM/6_function_4.mlir new file mode 100644 index 0000000..1495ebf --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_4.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.srl"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.sra"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xor"(%24, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_40.mlir b/benchmarks/VEIR_ASM/6_function_40.mlir new file mode 100644 index 0000000..5dbe92f --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_40.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.remu"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.divu"(%36, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.rem"(%36, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.xor"(%23, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.divu"(%36, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_41.mlir b/benchmarks/VEIR_ASM/6_function_41.mlir new file mode 100644 index 0000000..61ec70f --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_41.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %36 = "riscv.czero.eqz"(%33, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.czero.nez"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.or"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.divu"(%29, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.remu"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.rem"(%31, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %16 = "builtin.unrealized_conversion_cast"(%20) : (i32) -> !riscv.reg + %17 = "riscv.zext.w"(%16) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%17) : (!riscv.reg) -> i64 + "func.return"(%18) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_42.mlir b/benchmarks/VEIR_ASM/6_function_42.mlir new file mode 100644 index 0000000..283db17 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_42.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.sra"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.remu"(%33, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.srl"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_43.mlir b/benchmarks/VEIR_ASM/6_function_43.mlir new file mode 100644 index 0000000..7f9b6a2 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_43.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %40 = "riscv.czero.eqz"(%37, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.czero.nez"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "riscv.or"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.rem"(%42, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.sra"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.slt"(%35, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i1 + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%28) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%31, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_44.mlir b/benchmarks/VEIR_ASM/6_function_44.mlir new file mode 100644 index 0000000..9b8bd34 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_44.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.rem"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.and"(%35, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.divu"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.srl"(%16, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_45.mlir b/benchmarks/VEIR_ASM/6_function_45.mlir new file mode 100644 index 0000000..e075ead --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_45.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1): + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %32 = "builtin.unrealized_conversion_cast"(%36) : (i32) -> !riscv.reg + %33 = "riscv.sext.w"(%32) : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.slt"(%21, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_46.mlir b/benchmarks/VEIR_ASM/6_function_46.mlir new file mode 100644 index 0000000..b9c12c4 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_46.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "riscv.slt"(%38, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.xori"(%39) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i1 + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.xor"(%34, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.remu"(%35, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.and"(%26, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%41) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%31, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_47.mlir b/benchmarks/VEIR_ASM/6_function_47.mlir new file mode 100644 index 0000000..deb4adf --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_47.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.divu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.xor"(%28, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.divu"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_48.mlir b/benchmarks/VEIR_ASM/6_function_48.mlir new file mode 100644 index 0000000..8673124 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_48.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i1, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %45 = "riscv.rem"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %39 = "riscv.czero.eqz"(%45, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.czero.nez"(%45, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.or"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.rem"(%32, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%41, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i1 + %18 = "builtin.unrealized_conversion_cast"(%24) : (i1) -> !riscv.reg + %19 = "riscv.czero.eqz"(%41, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.czero.nez"(%30, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i64 + "func.return"(%22) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_49.mlir b/benchmarks/VEIR_ASM/6_function_49.mlir new file mode 100644 index 0000000..5f9c637 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_49.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %29 = "builtin.unrealized_conversion_cast"(%33) : (i32) -> !riscv.reg + %30 = "riscv.sext.w"(%29) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.remu"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.or"(%21, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_5.mlir b/benchmarks/VEIR_ASM/6_function_5.mlir new file mode 100644 index 0000000..3ff0fd1 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_5.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32): + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %36 = "riscv.sext.w"(%35) : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%36) : (!riscv.reg) -> i1 + %28 = "builtin.unrealized_conversion_cast"(%34) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%36, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%36, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %21 = "builtin.unrealized_conversion_cast"(%25) : (i32) -> !riscv.reg + %22 = "riscv.zext.w"(%21) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.sltu"(%36, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.xori"(%18) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_50.mlir b/benchmarks/VEIR_ASM/6_function_50.mlir new file mode 100644 index 0000000..789f937 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_50.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.remu"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.sra"(%38, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.zext.w"(%27) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%34, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.remu"(%28, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_51.mlir b/benchmarks/VEIR_ASM/6_function_51.mlir new file mode 100644 index 0000000..ae28574 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_51.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.rem"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.remu"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.and"(%26, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.sltu"(%35, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_52.mlir b/benchmarks/VEIR_ASM/6_function_52.mlir new file mode 100644 index 0000000..6fe51b6 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_52.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.srl"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.or"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.sra"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_53.mlir b/benchmarks/VEIR_ASM/6_function_53.mlir new file mode 100644 index 0000000..60cdb15 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_53.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %37 = "riscv.zext.w"(%36) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.xor"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.div"(%37, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.remu"(%24, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.srl"(%34, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.divu"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_54.mlir b/benchmarks/VEIR_ASM/6_function_54.mlir new file mode 100644 index 0000000..c9e24e0 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_54.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.srl"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %29 = "builtin.unrealized_conversion_cast"(%33) : (i32) -> !riscv.reg + %30 = "riscv.sext.w"(%29) : (!riscv.reg) -> !riscv.reg + %27 = "riscv.srl"(%36, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.remu"(%27, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.sltu"(%23, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.xori"(%18) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_55.mlir b/benchmarks/VEIR_ASM/6_function_55.mlir new file mode 100644 index 0000000..616246b --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_55.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.div"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.remu"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.rem"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_56.mlir b/benchmarks/VEIR_ASM/6_function_56.mlir new file mode 100644 index 0000000..6ae230a --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_56.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.sra"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.and"(%35, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.and"(%31, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.xor"(%22, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_57.mlir b/benchmarks/VEIR_ASM/6_function_57.mlir new file mode 100644 index 0000000..eea2541 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_57.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.divu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.sra"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.rem"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_58.mlir b/benchmarks/VEIR_ASM/6_function_58.mlir new file mode 100644 index 0000000..bf72dbc --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_58.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.sltu"(%34, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i1 + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %31 = "riscv.zext.w"(%30) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%36) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_59.mlir b/benchmarks/VEIR_ASM/6_function_59.mlir new file mode 100644 index 0000000..806f604 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_59.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.xor"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.and"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.divu"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_6.mlir b/benchmarks/VEIR_ASM/6_function_6.mlir new file mode 100644 index 0000000..702bc98 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_6.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.remu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.div"(%33, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.srl"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_60.mlir b/benchmarks/VEIR_ASM/6_function_60.mlir new file mode 100644 index 0000000..14dd4b9 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_60.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.div"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %24 = "riscv.div"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.srl"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_61.mlir b/benchmarks/VEIR_ASM/6_function_61.mlir new file mode 100644 index 0000000..58b7690 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_61.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.xor"(%34, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.rem"(%29, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.and"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.srl"(%31, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_62.mlir b/benchmarks/VEIR_ASM/6_function_62.mlir new file mode 100644 index 0000000..b327476 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_62.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "riscv.srl"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.xor"(%34, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.sra"(%39, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i1 + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%28) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%39, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.remu"(%31, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_63.mlir b/benchmarks/VEIR_ASM/6_function_63.mlir new file mode 100644 index 0000000..6d0c1e2 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_63.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.xor"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_64.mlir b/benchmarks/VEIR_ASM/6_function_64.mlir new file mode 100644 index 0000000..afa0177 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_64.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.or"(%37, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.divu"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.rem"(%34, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.srl"(%38, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_65.mlir b/benchmarks/VEIR_ASM/6_function_65.mlir new file mode 100644 index 0000000..4f2c84c --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_65.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.srl"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.div"(%26, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_66.mlir b/benchmarks/VEIR_ASM/6_function_66.mlir new file mode 100644 index 0000000..a35ccca --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_66.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %34 = "riscv.czero.eqz"(%31, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.czero.nez"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.or"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.div"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_67.mlir b/benchmarks/VEIR_ASM/6_function_67.mlir new file mode 100644 index 0000000..5bd6631 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_67.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.xor"(%37, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%32, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.and"(%34, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%30, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.rem"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.sra"(%16, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_68.mlir b/benchmarks/VEIR_ASM/6_function_68.mlir new file mode 100644 index 0000000..e44f366 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_68.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.rem"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.sra"(%35, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "riscv.divu"(%31, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.srl"(%25, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_69.mlir b/benchmarks/VEIR_ASM/6_function_69.mlir new file mode 100644 index 0000000..f2e4dc5 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_69.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.xor"(%37, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.sltiu"(%38) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i1 + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.rem"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %30 = "riscv.zext.w"(%29) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.div"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%40) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%34, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_7.mlir b/benchmarks/VEIR_ASM/6_function_7.mlir new file mode 100644 index 0000000..72c7a62 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_7.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.remu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.divu"(%33, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %20 = "riscv.sra"(%23, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_70.mlir b/benchmarks/VEIR_ASM/6_function_70.mlir new file mode 100644 index 0000000..7ceedba --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_70.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.remu"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.remu"(%41, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%28, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.sra"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.remu"(%33, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.and"(%22, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_71.mlir b/benchmarks/VEIR_ASM/6_function_71.mlir new file mode 100644 index 0000000..2dae2b7 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_71.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.rem"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.divu"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.sra"(%36, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.srl"(%28, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sra"(%24, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_72.mlir b/benchmarks/VEIR_ASM/6_function_72.mlir new file mode 100644 index 0000000..58eb0dd --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_72.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.xor"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.div"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.divu"(%26, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.div"(%36, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.rem"(%24, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_73.mlir b/benchmarks/VEIR_ASM/6_function_73.mlir new file mode 100644 index 0000000..f72422e --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_73.mlir @@ -0,0 +1,16 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.remu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%33, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.and"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_74.mlir b/benchmarks/VEIR_ASM/6_function_74.mlir new file mode 100644 index 0000000..6f18cfe --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_74.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.divu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.divu"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.or"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_75.mlir b/benchmarks/VEIR_ASM/6_function_75.mlir new file mode 100644 index 0000000..181b5d9 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_75.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.sra"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.srl"(%28, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.sra"(%24, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_76.mlir b/benchmarks/VEIR_ASM/6_function_76.mlir new file mode 100644 index 0000000..22332d5 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_76.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "riscv.srl"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.sltu"(%39, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i1 + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%36) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%26, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.div"(%31, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_77.mlir b/benchmarks/VEIR_ASM/6_function_77.mlir new file mode 100644 index 0000000..1f7354d --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_77.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.srl"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.divu"(%22, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sra"(%33, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_78.mlir b/benchmarks/VEIR_ASM/6_function_78.mlir new file mode 100644 index 0000000..0762b2f --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_78.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.or"(%36, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.and"(%32, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.divu"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xor"(%24, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %20 = "riscv.sltu"(%19, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_79.mlir b/benchmarks/VEIR_ASM/6_function_79.mlir new file mode 100644 index 0000000..3ed67b9 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_79.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.rem"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%41, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%25, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%41, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.slt"(%37, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_8.mlir b/benchmarks/VEIR_ASM/6_function_8.mlir new file mode 100644 index 0000000..e72be47 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_8.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.divu"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%32, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%41, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.srl"(%37, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.div"(%24, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "riscv.rem"(%26, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.slt"(%30, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_80.mlir b/benchmarks/VEIR_ASM/6_function_80.mlir new file mode 100644 index 0000000..8503b22 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_80.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i32): + %37 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %38 = "riscv.zext.w"(%37) : (!riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %33 = "riscv.czero.eqz"(%30, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.czero.nez"(%38, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.or"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.and"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.xor"(%35, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.srl"(%35, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_81.mlir b/benchmarks/VEIR_ASM/6_function_81.mlir new file mode 100644 index 0000000..c98da3a --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_81.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.rem"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.and"(%36, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.sra"(%26, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.srl"(%28, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.divu"(%28, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_82.mlir b/benchmarks/VEIR_ASM/6_function_82.mlir new file mode 100644 index 0000000..e6bcf8f --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_82.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "riscv.remu"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.sltu"(%39, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i1 + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.remu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%36) : (i1) -> !riscv.reg + %25 = "riscv.czero.eqz"(%31, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.czero.nez"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.or"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.divu"(%18, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_83.mlir b/benchmarks/VEIR_ASM/6_function_83.mlir new file mode 100644 index 0000000..b5b5fad --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_83.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %40 = "riscv.sext.w"(%39) : (!riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.slt"(%36, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%37) : (!riscv.reg) -> i1 + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.sra"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.rem"(%33, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%38) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%20, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%29, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.sra"(%25, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_84.mlir b/benchmarks/VEIR_ASM/6_function_84.mlir new file mode 100644 index 0000000..594d11e --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_84.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.srl"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.div"(%35, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.srl"(%37, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %25 = "riscv.sltu"(%29, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.xori"(%25) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i1 + %17 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%27) : (i1) -> !riscv.reg + %19 = "riscv.czero.eqz"(%33, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.czero.nez"(%17, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i64 + "func.return"(%22) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_85.mlir b/benchmarks/VEIR_ASM/6_function_85.mlir new file mode 100644 index 0000000..43b8e6c --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_85.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.sra"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.and"(%36, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%36) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%32, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_86.mlir b/benchmarks/VEIR_ASM/6_function_86.mlir new file mode 100644 index 0000000..338a37f --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_86.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.or"(%40, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.or"(%36, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.and"(%37, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %27 = "riscv.czero.eqz"(%33, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.czero.nez"(%33, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.xor"(%29, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.or"(%22, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_87.mlir b/benchmarks/VEIR_ASM/6_function_87.mlir new file mode 100644 index 0000000..cbd7e07 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_87.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.rem"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.or"(%36, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.or"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.divu"(%32, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.remu"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_88.mlir b/benchmarks/VEIR_ASM/6_function_88.mlir new file mode 100644 index 0000000..f9663f6 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_88.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %43 = "riscv.czero.eqz"(%40, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.czero.nez"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "riscv.or"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.or"(%45, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.slt"(%32, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i1 + %27 = "builtin.unrealized_conversion_cast"(%35) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%38, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%45, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.rem"(%30, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.xor"(%23, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sltiu"(%18) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_89.mlir b/benchmarks/VEIR_ASM/6_function_89.mlir new file mode 100644 index 0000000..dee6003 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_89.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %30 = "builtin.unrealized_conversion_cast"(%34) : (i32) -> !riscv.reg + %31 = "riscv.zext.w"(%30) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.rem"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.and"(%28, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.divu"(%24, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_9.mlir b/benchmarks/VEIR_ASM/6_function_9.mlir new file mode 100644 index 0000000..245d7c9 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_9.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i1, %arg6_3 : i32): + %37 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %38 = "riscv.sext.w"(%37) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %33 = "riscv.czero.eqz"(%38, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.czero.nez"(%38, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.or"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%23, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%35, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_90.mlir b/benchmarks/VEIR_ASM/6_function_90.mlir new file mode 100644 index 0000000..1d65fe3 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_90.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.rem"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.srl"(%41, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%41, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.and"(%25, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%26, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %18 = "riscv.sltu"(%22, %16) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_91.mlir b/benchmarks/VEIR_ASM/6_function_91.mlir new file mode 100644 index 0000000..7d080c4 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_91.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.or"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.divu"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.div"(%26, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.sra"(%36, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.srl"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_92.mlir b/benchmarks/VEIR_ASM/6_function_92.mlir new file mode 100644 index 0000000..5f7f36c --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_92.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.sltu"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%36) : (!riscv.reg) -> i1 + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.rem"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%37) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%23, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%32, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_93.mlir b/benchmarks/VEIR_ASM/6_function_93.mlir new file mode 100644 index 0000000..2ab5cac --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_93.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.xor"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.srl"(%30, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.rem"(%26, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.rem"(%28, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.srl"(%18, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_94.mlir b/benchmarks/VEIR_ASM/6_function_94.mlir new file mode 100644 index 0000000..3af2e7c --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_94.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %42 = "riscv.czero.eqz"(%39, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.czero.nez"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.or"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%32, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.remu"(%37, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.divu"(%26, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "riscv.div"(%44, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_95.mlir b/benchmarks/VEIR_ASM/6_function_95.mlir new file mode 100644 index 0000000..77d7a1d --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_95.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.remu"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.rem"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.remu"(%33, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_96.mlir b/benchmarks/VEIR_ASM/6_function_96.mlir new file mode 100644 index 0000000..fb7d0a6 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_96.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i1 + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.srl"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%35) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%32, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_97.mlir b/benchmarks/VEIR_ASM/6_function_97.mlir new file mode 100644 index 0000000..5f7fdfe --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_97.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %31 = "builtin.unrealized_conversion_cast"(%35) : (i32) -> !riscv.reg + %32 = "riscv.sext.w"(%31) : (!riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i1 + %24 = "builtin.unrealized_conversion_cast"(%30) : (i1) -> !riscv.reg + %25 = "riscv.czero.eqz"(%32, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.czero.nez"(%32, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.or"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.and"(%27, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%17) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_98.mlir b/benchmarks/VEIR_ASM/6_function_98.mlir new file mode 100644 index 0000000..53d8ea1 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_98.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.divu"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.and"(%32, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.or"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %18 = "riscv.xor"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %20 = "riscv.sltu"(%19, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/6_function_99.mlir b/benchmarks/VEIR_ASM/6_function_99.mlir new file mode 100644 index 0000000..56ec906 --- /dev/null +++ b/benchmarks/VEIR_ASM/6_function_99.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.xor"(%37, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.sltiu"(%38) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i1 + %33 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %34 = "riscv.sext.w"(%33) : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%40) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%34, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.and"(%24, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%17) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_0.mlir b/benchmarks/VEIR_ASM/7_function_0.mlir new file mode 100644 index 0000000..0872d87 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_0.mlir @@ -0,0 +1,28 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %46 = "riscv.czero.eqz"(%43, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "riscv.czero.nez"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %48 = "riscv.or"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%41) : (!riscv.reg) -> i1 + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%42) : (i1) -> !riscv.reg + %37 = "riscv.czero.eqz"(%34, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.czero.nez"(%48, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.or"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.or"(%39, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%42) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%23, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%48, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.div"(%32, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_1.mlir b/benchmarks/VEIR_ASM/7_function_1.mlir new file mode 100644 index 0000000..3653b66 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_1.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.rem"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %33 = "riscv.zext.w"(%32) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.div"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.srl"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_10.mlir b/benchmarks/VEIR_ASM/7_function_10.mlir new file mode 100644 index 0000000..b2c3c6d --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_10.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %43 = "riscv.zext.w"(%42) : (!riscv.reg) -> !riscv.reg + %40 = "riscv.srl"(%43, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.divu"(%40, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.rem"(%30, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.remu"(%26, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.remu"(%40, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.slt"(%24, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xori"(%19) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_11.mlir b/benchmarks/VEIR_ASM/7_function_11.mlir new file mode 100644 index 0000000..30f58fe --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_11.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %39 = "riscv.zext.w"(%38) : (!riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.xor"(%35, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.srl"(%30, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.div"(%36, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.rem"(%39, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_12.mlir b/benchmarks/VEIR_ASM/7_function_12.mlir new file mode 100644 index 0000000..0fe50f9 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_12.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%41) : (!riscv.reg) -> i32 + %38 = "builtin.unrealized_conversion_cast"(%42) : (i32) -> !riscv.reg + %39 = "riscv.sext.w"(%38) : (!riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.sra"(%39, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.or"(%39, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.div"(%39, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.divu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.slt"(%24, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xori"(%19) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_13.mlir b/benchmarks/VEIR_ASM/7_function_13.mlir new file mode 100644 index 0000000..6f2ddf4 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_13.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.and"(%41, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.divu"(%42, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.sltu"(%32, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.xori"(%33) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i1 + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%35) : (i1) -> !riscv.reg + %27 = "riscv.czero.eqz"(%38, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.czero.nez"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_14.mlir b/benchmarks/VEIR_ASM/7_function_14.mlir new file mode 100644 index 0000000..a8cfb4a --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_14.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i1): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %40 = "riscv.sext.w"(%39) : (!riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.and"(%40, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%37) : (!riscv.reg) -> i32 + %30 = "builtin.unrealized_conversion_cast"(%34) : (i32) -> !riscv.reg + %31 = "riscv.zext.w"(%30) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%40, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%40, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%28, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_15.mlir b/benchmarks/VEIR_ASM/7_function_15.mlir new file mode 100644 index 0000000..a43915d --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_15.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %44 = "riscv.sext.w"(%43) : (!riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.sltu"(%44, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.xori"(%40) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%41) : (!riscv.reg) -> i1 + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.rem"(%34, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.div"(%30, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.srl"(%26, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%42) : (i1) -> !riscv.reg + %22 = "riscv.czero.eqz"(%32, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.czero.nez"(%28, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.or"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_16.mlir b/benchmarks/VEIR_ASM/7_function_16.mlir new file mode 100644 index 0000000..1367dad --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_16.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %38 = "riscv.czero.eqz"(%35, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.czero.nez"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.or"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.div"(%40, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %26 = "riscv.sra"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_17.mlir b/benchmarks/VEIR_ASM/7_function_17.mlir new file mode 100644 index 0000000..54c78df --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_17.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "riscv.rem"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.or"(%45, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.xor"(%36, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.and"(%37, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.xor"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.xor"(%25, %17) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %21 = "riscv.sltu"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_18.mlir b/benchmarks/VEIR_ASM/7_function_18.mlir new file mode 100644 index 0000000..e3ada27 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_18.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "riscv.rem"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.divu"(%43, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.div"(%33, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%35, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.sra"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.remu"(%21, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.and"(%23, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_19.mlir b/benchmarks/VEIR_ASM/7_function_19.mlir new file mode 100644 index 0000000..08fe7a2 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_19.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.and"(%40, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.srl"(%35, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.remu"(%37, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.xor"(%33, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.xor"(%41, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_2.mlir b/benchmarks/VEIR_ASM/7_function_2.mlir new file mode 100644 index 0000000..93f324f --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_2.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "riscv.remu"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.sra"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.remu"(%37, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.div"(%33, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.srl"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xor"(%25, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_20.mlir b/benchmarks/VEIR_ASM/7_function_20.mlir new file mode 100644 index 0000000..eee1e2a --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_20.mlir @@ -0,0 +1,27 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "riscv.remu"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.slt"(%47, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.xori"(%42) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i1 + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.remu"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.rem"(%47, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%44) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%25, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.div"(%47, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.srl"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_21.mlir b/benchmarks/VEIR_ASM/7_function_21.mlir new file mode 100644 index 0000000..72ac0fa --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_21.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %46 = "riscv.sext.w"(%45) : (!riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "riscv.divu"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.sltu"(%43, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.xori"(%38) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i1 + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%40) : (i1) -> !riscv.reg + %32 = "riscv.czero.eqz"(%29, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.czero.nez"(%43, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.and"(%34, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.xor"(%27, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.divu"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_22.mlir b/benchmarks/VEIR_ASM/7_function_22.mlir new file mode 100644 index 0000000..66f2c0e --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_22.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.srl"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.zext.w"(%23) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.srl"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_23.mlir b/benchmarks/VEIR_ASM/7_function_23.mlir new file mode 100644 index 0000000..5114a6e --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_23.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.sra"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.and"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.div"(%28, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.divu"(%38, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_24.mlir b/benchmarks/VEIR_ASM/7_function_24.mlir new file mode 100644 index 0000000..89056e7 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_24.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.rem"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.srl"(%34, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.or"(%36, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.rem"(%32, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.remu"(%26, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_25.mlir b/benchmarks/VEIR_ASM/7_function_25.mlir new file mode 100644 index 0000000..94da1dc --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_25.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "riscv.divu"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i1 + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%41) : (i1) -> !riscv.reg + %36 = "riscv.czero.eqz"(%33, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.czero.nez"(%44, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.or"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i1 + %28 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %26 = "riscv.remu"(%38, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%32) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%29, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i64 + "func.return"(%23) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_26.mlir b/benchmarks/VEIR_ASM/7_function_26.mlir new file mode 100644 index 0000000..c76ad43 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_26.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.srl"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.and"(%41, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.xor"(%37, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.remu"(%27, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.div"(%29, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.sra"(%33, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_27.mlir b/benchmarks/VEIR_ASM/7_function_27.mlir new file mode 100644 index 0000000..e6e1df6 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_27.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i32 + %41 = "builtin.unrealized_conversion_cast"(%45) : (i32) -> !riscv.reg + %42 = "riscv.zext.w"(%41) : (!riscv.reg) -> !riscv.reg + %39 = "riscv.xor"(%42, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %33 = "riscv.czero.eqz"(%39, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.czero.nez"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.or"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.slt"(%39, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i1 + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%29) : (i1) -> !riscv.reg + %22 = "riscv.czero.eqz"(%19, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.czero.nez"(%42, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.or"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_28.mlir b/benchmarks/VEIR_ASM/7_function_28.mlir new file mode 100644 index 0000000..e8b3267 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_28.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %37 = "riscv.zext.w"(%36) : (!riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%37) : (!riscv.reg) -> i32 + %31 = "builtin.unrealized_conversion_cast"(%35) : (i32) -> !riscv.reg + %32 = "riscv.zext.w"(%31) : (!riscv.reg) -> !riscv.reg + %29 = "riscv.rem"(%32, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.rem"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.divu"(%19, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_29.mlir b/benchmarks/VEIR_ASM/7_function_29.mlir new file mode 100644 index 0000000..634a238 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_29.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i1 + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%44) : (i1) -> !riscv.reg + %39 = "riscv.czero.eqz"(%36, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.czero.nez"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.or"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %34 = "riscv.sext.w"(%33) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.xor"(%34, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.sra"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.and"(%27, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.and"(%18, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_3.mlir b/benchmarks/VEIR_ASM/7_function_3.mlir new file mode 100644 index 0000000..93cd845 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_3.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.div"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.or"(%36, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %33 = "riscv.zext.w"(%32) : (!riscv.reg) -> !riscv.reg + %30 = "riscv.rem"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.sra"(%26, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.divu"(%30, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_30.mlir b/benchmarks/VEIR_ASM/7_function_30.mlir new file mode 100644 index 0000000..29d80dc --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_30.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%41) : (!riscv.reg) -> i32 + %38 = "builtin.unrealized_conversion_cast"(%42) : (i32) -> !riscv.reg + %39 = "riscv.sext.w"(%38) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %34 = "riscv.czero.eqz"(%39, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.czero.nez"(%39, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.or"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.srl"(%39, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.and"(%29, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.remu"(%36, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_31.mlir b/benchmarks/VEIR_ASM/7_function_31.mlir new file mode 100644 index 0000000..21c26bb --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_31.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %38 = "riscv.czero.eqz"(%35, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.czero.nez"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.or"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %30 = "builtin.unrealized_conversion_cast"(%34) : (i32) -> !riscv.reg + %31 = "riscv.sext.w"(%30) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.and"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.sltu"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_32.mlir b/benchmarks/VEIR_ASM/7_function_32.mlir new file mode 100644 index 0000000..bcaa285 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_32.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%37) : (!riscv.reg) -> i32 + %34 = "builtin.unrealized_conversion_cast"(%38) : (i32) -> !riscv.reg + %35 = "riscv.sext.w"(%34) : (!riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.sra"(%30, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "riscv.xor"(%22, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.xor"(%23, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_33.mlir b/benchmarks/VEIR_ASM/7_function_33.mlir new file mode 100644 index 0000000..f2b7428 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_33.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.remu"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.xor"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.or"(%36, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.rem"(%26, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.slt"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_34.mlir b/benchmarks/VEIR_ASM/7_function_34.mlir new file mode 100644 index 0000000..d4da4fe --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_34.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %37 = "builtin.unrealized_conversion_cast"(%41) : (i32) -> !riscv.reg + %38 = "riscv.zext.w"(%37) : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.xor"(%34, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%26, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%35, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.srl"(%31, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.sext.w"(%17) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_35.mlir b/benchmarks/VEIR_ASM/7_function_35.mlir new file mode 100644 index 0000000..cda4fbe --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_35.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%37) : (!riscv.reg) -> i32 + %34 = "builtin.unrealized_conversion_cast"(%38) : (i32) -> !riscv.reg + %35 = "riscv.zext.w"(%34) : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%38) : (i32) -> !riscv.reg + %32 = "riscv.zext.w"(%31) : (!riscv.reg) -> !riscv.reg + %29 = "riscv.sra"(%35, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.srl"(%29, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.and"(%25, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_36.mlir b/benchmarks/VEIR_ASM/7_function_36.mlir new file mode 100644 index 0000000..9f15247 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_36.mlir @@ -0,0 +1,27 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %48 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %49 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %50 = "riscv.sra"(%48, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %44 = "riscv.czero.eqz"(%50, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "riscv.czero.nez"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "riscv.or"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.sltu"(%50, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.xori"(%38) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i1 + %34 = "riscv.or"(%46, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%40) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%50, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.divu"(%30, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.srl"(%46, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_37.mlir b/benchmarks/VEIR_ASM/7_function_37.mlir new file mode 100644 index 0000000..0fcae97 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_37.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.or"(%43, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %38 = "riscv.czero.eqz"(%35, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.czero.nez"(%44, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.or"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.srl"(%40, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.rem"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.and"(%40, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.xor"(%25, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_38.mlir b/benchmarks/VEIR_ASM/7_function_38.mlir new file mode 100644 index 0000000..ed587df --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_38.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %45 = "riscv.divu"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.and"(%45, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.remu"(%41, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.xor"(%31, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.sltiu"(%32) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i1 + %25 = "builtin.unrealized_conversion_cast"(%34) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%45, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%41, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.or"(%20, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_39.mlir b/benchmarks/VEIR_ASM/7_function_39.mlir new file mode 100644 index 0000000..b6d45d5 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_39.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.remu"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %21 = "riscv.remu"(%29, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_4.mlir b/benchmarks/VEIR_ASM/7_function_4.mlir new file mode 100644 index 0000000..e9f41fb --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_4.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "riscv.div"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.srl"(%43, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.divu"(%39, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.and"(%35, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.sra"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.and"(%27, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.slt"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_40.mlir b/benchmarks/VEIR_ASM/7_function_40.mlir new file mode 100644 index 0000000..81d15c1 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_40.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.zext.w"(%36) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %30 = "riscv.sext.w"(%29) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.rem"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.srl"(%27, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sra"(%34, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_41.mlir b/benchmarks/VEIR_ASM/7_function_41.mlir new file mode 100644 index 0000000..38ee3d0 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_41.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "riscv.xor"(%40, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.and"(%41, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.srl"(%31, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.srl"(%41, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "riscv.and"(%24, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.divu"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_42.mlir b/benchmarks/VEIR_ASM/7_function_42.mlir new file mode 100644 index 0000000..b539fcb --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_42.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.xor"(%39, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.sra"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.sra"(%40, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.xor"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.sra"(%32, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_43.mlir b/benchmarks/VEIR_ASM/7_function_43.mlir new file mode 100644 index 0000000..16c6571 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_43.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "riscv.sra"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %38 = "riscv.czero.eqz"(%35, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.czero.nez"(%44, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.or"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%44, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %21 = "riscv.remu"(%40, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_44.mlir b/benchmarks/VEIR_ASM/7_function_44.mlir new file mode 100644 index 0000000..6581f15 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_44.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.remu"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "riscv.remu"(%44, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %34 = "riscv.czero.eqz"(%31, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.czero.nez"(%44, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.or"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.xor"(%40, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.div"(%29, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xor"(%25, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_45.mlir b/benchmarks/VEIR_ASM/7_function_45.mlir new file mode 100644 index 0000000..46a3344 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_45.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.rem"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.xor"(%37, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.and"(%27, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_46.mlir b/benchmarks/VEIR_ASM/7_function_46.mlir new file mode 100644 index 0000000..d85f6a0 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_46.mlir @@ -0,0 +1,28 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "riscv.slt"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.xori"(%43) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i1 + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "riscv.sra"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.remu"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.sra"(%24, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%45) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%39, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i64 + "func.return"(%23) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_47.mlir b/benchmarks/VEIR_ASM/7_function_47.mlir new file mode 100644 index 0000000..1f89d87 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_47.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%41) : (!riscv.reg) -> i32 + %38 = "builtin.unrealized_conversion_cast"(%42) : (i32) -> !riscv.reg + %39 = "riscv.zext.w"(%38) : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.sra"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.xor"(%36, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%23, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%39, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xor"(%28, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_48.mlir b/benchmarks/VEIR_ASM/7_function_48.mlir new file mode 100644 index 0000000..ff6e15d --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_48.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.and"(%37, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.divu"(%38, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.rem"(%28, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.xor"(%30, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_49.mlir b/benchmarks/VEIR_ASM/7_function_49.mlir new file mode 100644 index 0000000..e9e70f4 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_49.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "riscv.divu"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.div"(%35, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.sra"(%31, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.remu"(%33, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.srl"(%33, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%25, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_5.mlir b/benchmarks/VEIR_ASM/7_function_5.mlir new file mode 100644 index 0000000..a9e408d --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_5.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.and"(%34, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %26 = "riscv.and"(%29, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_50.mlir b/benchmarks/VEIR_ASM/7_function_50.mlir new file mode 100644 index 0000000..6d1244c --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_50.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.sra"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.srl"(%41, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.divu"(%31, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.divu"(%33, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.srl"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_51.mlir b/benchmarks/VEIR_ASM/7_function_51.mlir new file mode 100644 index 0000000..b9a7ae0 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_51.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %48 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %49 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %50 = "riscv.or"(%49, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %44 = "riscv.czero.eqz"(%41, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "riscv.czero.nez"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "riscv.or"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %37 = "riscv.czero.eqz"(%46, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.czero.nez"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.or"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.divu"(%39, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "riscv.xor"(%32, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.divu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sltu"(%50, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xori"(%19) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_52.mlir b/benchmarks/VEIR_ASM/7_function_52.mlir new file mode 100644 index 0000000..f103719 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_52.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.zext.w"(%36) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.rem"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.or"(%34, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.and"(%26, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.divu"(%37, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_53.mlir b/benchmarks/VEIR_ASM/7_function_53.mlir new file mode 100644 index 0000000..a310f2f --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_53.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i32 + %35 = "builtin.unrealized_conversion_cast"(%39) : (i32) -> !riscv.reg + %36 = "riscv.sext.w"(%35) : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.rem"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.remu"(%33, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.divu"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%25, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_54.mlir b/benchmarks/VEIR_ASM/7_function_54.mlir new file mode 100644 index 0000000..915a1a5 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_54.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %32 = "builtin.unrealized_conversion_cast"(%36) : (i32) -> !riscv.reg + %33 = "riscv.zext.w"(%32) : (!riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.srl"(%28, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_55.mlir b/benchmarks/VEIR_ASM/7_function_55.mlir new file mode 100644 index 0000000..207223a --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_55.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.rem"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i32 + %17 = "builtin.unrealized_conversion_cast"(%21) : (i32) -> !riscv.reg + %18 = "riscv.zext.w"(%17) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%18) : (!riscv.reg) -> i64 + "func.return"(%19) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_56.mlir b/benchmarks/VEIR_ASM/7_function_56.mlir new file mode 100644 index 0000000..4a91f53 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_56.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %36 = "riscv.zext.w"(%35) : (!riscv.reg) -> !riscv.reg + %33 = "riscv.and"(%36, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %21 = "builtin.unrealized_conversion_cast"(%25) : (i32) -> !riscv.reg + %22 = "riscv.sext.w"(%21) : (!riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%22, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_57.mlir b/benchmarks/VEIR_ASM/7_function_57.mlir new file mode 100644 index 0000000..fb46994 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_57.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.sra"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.rem"(%32, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.or"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.and"(%30, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_58.mlir b/benchmarks/VEIR_ASM/7_function_58.mlir new file mode 100644 index 0000000..6ccece3 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_58.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "riscv.xor"(%43, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "riscv.and"(%39, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.remu"(%40, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.rem"(%44, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.rem"(%32, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.and"(%28, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.slt"(%32, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xori"(%19) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_59.mlir b/benchmarks/VEIR_ASM/7_function_59.mlir new file mode 100644 index 0000000..bfe9ac8 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_59.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %39 = "riscv.czero.eqz"(%36, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.czero.nez"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.or"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%32, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.sra"(%41, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.and"(%30, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_6.mlir b/benchmarks/VEIR_ASM/7_function_6.mlir new file mode 100644 index 0000000..48aaef2 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_6.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.srl"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.or"(%33, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.xor"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.divu"(%34, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_60.mlir b/benchmarks/VEIR_ASM/7_function_60.mlir new file mode 100644 index 0000000..59bee10 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_60.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "riscv.div"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.or"(%36, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.or"(%32, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%24, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.rem"(%19, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_61.mlir b/benchmarks/VEIR_ASM/7_function_61.mlir new file mode 100644 index 0000000..503cfe2 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_61.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "riscv.divu"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "riscv.slt"(%38, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i1 + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %35 = "riscv.zext.w"(%34) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %29 = "builtin.unrealized_conversion_cast"(%33) : (i32) -> !riscv.reg + %30 = "riscv.zext.w"(%29) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%40) : (i1) -> !riscv.reg + %25 = "riscv.czero.eqz"(%30, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.czero.nez"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.or"(%25, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sltu"(%27, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xori"(%19) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_62.mlir b/benchmarks/VEIR_ASM/7_function_62.mlir new file mode 100644 index 0000000..663b7bf --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_62.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i32 + %35 = "builtin.unrealized_conversion_cast"(%39) : (i32) -> !riscv.reg + %36 = "riscv.sext.w"(%35) : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.xor"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%33, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.remu"(%25, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_63.mlir b/benchmarks/VEIR_ASM/7_function_63.mlir new file mode 100644 index 0000000..8196506 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_63.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.and"(%37, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.divu"(%38, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.div"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_64.mlir b/benchmarks/VEIR_ASM/7_function_64.mlir new file mode 100644 index 0000000..ae759ea --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_64.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %32 = "builtin.unrealized_conversion_cast"(%36) : (i32) -> !riscv.reg + %33 = "riscv.zext.w"(%32) : (!riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.sra"(%28, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%30, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_65.mlir b/benchmarks/VEIR_ASM/7_function_65.mlir new file mode 100644 index 0000000..3b23024 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_65.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %40 = "riscv.sext.w"(%39) : (!riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.and"(%36, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.and"(%32, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.div"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.sra"(%37, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.rem"(%25, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_66.mlir b/benchmarks/VEIR_ASM/7_function_66.mlir new file mode 100644 index 0000000..aec22b8 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_66.mlir @@ -0,0 +1,27 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i32 + %41 = "builtin.unrealized_conversion_cast"(%45) : (i32) -> !riscv.reg + %42 = "riscv.sext.w"(%41) : (!riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "riscv.remu"(%42, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.sltu"(%39, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.xori"(%34) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i1 + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.divu"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.remu"(%30, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%36) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%17, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i64 + "func.return"(%23) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_67.mlir b/benchmarks/VEIR_ASM/7_function_67.mlir new file mode 100644 index 0000000..ee17e28 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_67.mlir @@ -0,0 +1,17 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.divu"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.xor"(%41, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.divu"(%41, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.remu"(%33, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.divu"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.sra"(%25, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_68.mlir b/benchmarks/VEIR_ASM/7_function_68.mlir new file mode 100644 index 0000000..38e5efc --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_68.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "riscv.slt"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%47) : (!riscv.reg) -> i1 + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%48) : (i1) -> !riscv.reg + %41 = "riscv.czero.eqz"(%38, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "riscv.czero.nez"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.or"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.rem"(%43, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.and"(%36, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i1 + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%25, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%29) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%32, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%26, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i64 + "func.return"(%23) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_69.mlir b/benchmarks/VEIR_ASM/7_function_69.mlir new file mode 100644 index 0000000..f1456ad --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_69.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %41 = "riscv.czero.eqz"(%38, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "riscv.czero.nez"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.or"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.and"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.sra"(%43, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.or"(%22, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%23, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_7.mlir b/benchmarks/VEIR_ASM/7_function_7.mlir new file mode 100644 index 0000000..1e561e8 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_7.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "riscv.srl"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.and"(%42, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%32, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.remu"(%34, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sltu"(%30, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_70.mlir b/benchmarks/VEIR_ASM/7_function_70.mlir new file mode 100644 index 0000000..2a8495e --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_70.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.sra"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.div"(%32, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.rem"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.zext.w"(%23) : (!riscv.reg) -> !riscv.reg + %21 = "riscv.xor"(%24, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_71.mlir b/benchmarks/VEIR_ASM/7_function_71.mlir new file mode 100644 index 0000000..2f57776 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_71.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "riscv.remu"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %39 = "riscv.rem"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.divu"(%33, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "riscv.or"(%30, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.xor"(%31, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %23 = "riscv.xor"(%22, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.rem"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_72.mlir b/benchmarks/VEIR_ASM/7_function_72.mlir new file mode 100644 index 0000000..214ca35 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_72.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.srl"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i32 + %31 = "builtin.unrealized_conversion_cast"(%35) : (i32) -> !riscv.reg + %32 = "riscv.zext.w"(%31) : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.divu"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.rem"(%25, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_73.mlir b/benchmarks/VEIR_ASM/7_function_73.mlir new file mode 100644 index 0000000..185f7b0 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_73.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %34 = "riscv.zext.w"(%33) : (!riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.and"(%30, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.sext.w"(%24) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_74.mlir b/benchmarks/VEIR_ASM/7_function_74.mlir new file mode 100644 index 0000000..70214b6 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_74.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %40 = "riscv.zext.w"(%39) : (!riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.srl"(%35, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.divu"(%37, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.xor"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %21 = "riscv.xor"(%20, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_75.mlir b/benchmarks/VEIR_ASM/7_function_75.mlir new file mode 100644 index 0000000..9c5b61e --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_75.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.remu"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%42) : (!riscv.reg) -> i1 + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.divu"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.rem"(%42, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.xor"(%32, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%39) : (i1) -> !riscv.reg + %22 = "riscv.czero.eqz"(%19, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.czero.nez"(%28, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.or"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_76.mlir b/benchmarks/VEIR_ASM/7_function_76.mlir new file mode 100644 index 0000000..1632073 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_76.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "riscv.divu"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.divu"(%44, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.divu"(%40, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.or"(%31, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %26 = "riscv.czero.eqz"(%44, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.czero.nez"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.or"(%28, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_77.mlir b/benchmarks/VEIR_ASM/7_function_77.mlir new file mode 100644 index 0000000..ad21302 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_77.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "riscv.div"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "riscv.sra"(%46, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.xor"(%37, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.and"(%33, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%42, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.divu"(%30, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.divu"(%34, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_78.mlir b/benchmarks/VEIR_ASM/7_function_78.mlir new file mode 100644 index 0000000..d406366 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_78.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.rem"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %36 = "riscv.sext.w"(%35) : (!riscv.reg) -> !riscv.reg + %33 = "riscv.divu"(%36, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%36) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %24 = "riscv.or"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sltu"(%24, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xori"(%19) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_79.mlir b/benchmarks/VEIR_ASM/7_function_79.mlir new file mode 100644 index 0000000..569d878 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_79.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.or"(%40, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%32, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%41, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.rem"(%41, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.zext.w"(%23) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.or"(%24, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_8.mlir b/benchmarks/VEIR_ASM/7_function_8.mlir new file mode 100644 index 0000000..9446a21 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_8.mlir @@ -0,0 +1,32 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %49 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %50 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %51 = "riscv.sltu"(%50, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %52 = "riscv.xori"(%51) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %53 = "builtin.unrealized_conversion_cast"(%52) : (!riscv.reg) -> i1 + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%53) : (i1) -> !riscv.reg + %45 = "riscv.czero.eqz"(%42, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "riscv.czero.nez"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "riscv.or"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %38 = "riscv.czero.eqz"(%35, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.czero.nez"(%47, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.or"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.or"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.remu"(%47, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.xor"(%25, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %21 = "riscv.sltu"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_80.mlir b/benchmarks/VEIR_ASM/7_function_80.mlir new file mode 100644 index 0000000..f2a9766 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_80.mlir @@ -0,0 +1,33 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %49 = "riscv.xor"(%48, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %50 = "riscv.sltiu"(%49) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %51 = "builtin.unrealized_conversion_cast"(%50) : (!riscv.reg) -> i1 + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %45 = "riscv.divu"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%51) : (i1) -> !riscv.reg + %39 = "riscv.czero.eqz"(%36, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.czero.nez"(%45, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.or"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.or"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.sltu"(%28, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i1 + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%31) : (i1) -> !riscv.reg + %24 = "riscv.czero.eqz"(%41, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.czero.nez"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%24, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sra"(%41, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_81.mlir b/benchmarks/VEIR_ASM/7_function_81.mlir new file mode 100644 index 0000000..22d1e92 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_81.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %41 = "riscv.zext.w"(%40) : (!riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.srl"(%41, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.srl"(%41, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %30 = "riscv.zext.w"(%29) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%30, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.rem"(%38, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.or"(%23, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_82.mlir b/benchmarks/VEIR_ASM/7_function_82.mlir new file mode 100644 index 0000000..3a8af06 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_82.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %32 = "builtin.unrealized_conversion_cast"(%36) : (i32) -> !riscv.reg + %33 = "riscv.sext.w"(%32) : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.sra"(%23, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.or"(%25, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_83.mlir b/benchmarks/VEIR_ASM/7_function_83.mlir new file mode 100644 index 0000000..1be07ea --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_83.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "riscv.remu"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.sext.w"(%23) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "riscv.div"(%24, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_84.mlir b/benchmarks/VEIR_ASM/7_function_84.mlir new file mode 100644 index 0000000..8ddb618 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_84.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "riscv.or"(%40, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.or"(%36, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.and"(%37, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.xor"(%28, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.and"(%29, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.rem"(%25, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_85.mlir b/benchmarks/VEIR_ASM/7_function_85.mlir new file mode 100644 index 0000000..b613402 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_85.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %42 = "riscv.czero.eqz"(%39, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.czero.nez"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.or"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.xor"(%36, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.xor"(%37, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.and"(%33, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%24, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.remu"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_86.mlir b/benchmarks/VEIR_ASM/7_function_86.mlir new file mode 100644 index 0000000..6eeb2f7 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_86.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%37, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "riscv.rem"(%28, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.divu"(%19, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_87.mlir b/benchmarks/VEIR_ASM/7_function_87.mlir new file mode 100644 index 0000000..e36c723 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_87.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %44 = "riscv.czero.eqz"(%41, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "riscv.czero.nez"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "riscv.or"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.remu"(%46, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.divu"(%33, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.sra"(%46, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "riscv.xor"(%26, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.srl"(%31, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.slt"(%35, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i1 + "func.return"(%20) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_88.mlir b/benchmarks/VEIR_ASM/7_function_88.mlir new file mode 100644 index 0000000..2fa65e1 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_88.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i32): + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %40 = "riscv.sext.w"(%39) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%32, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%40, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.rem"(%28, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.or"(%30, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_89.mlir b/benchmarks/VEIR_ASM/7_function_89.mlir new file mode 100644 index 0000000..01958a3 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_89.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.and"(%36, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %33 = "riscv.sext.w"(%32) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.divu"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.divu"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_9.mlir b/benchmarks/VEIR_ASM/7_function_9.mlir new file mode 100644 index 0000000..ff7978a --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_9.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.xor"(%40, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.and"(%41, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.remu"(%37, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.srl"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.or"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %21 = "riscv.remu"(%19, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_90.mlir b/benchmarks/VEIR_ASM/7_function_90.mlir new file mode 100644 index 0000000..9d2ab11 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_90.mlir @@ -0,0 +1,18 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64): + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %29 = "builtin.unrealized_conversion_cast"(%33) : (i32) -> !riscv.reg + %30 = "riscv.zext.w"(%29) : (!riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.sext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_91.mlir b/benchmarks/VEIR_ASM/7_function_91.mlir new file mode 100644 index 0000000..d9d4331 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_91.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "riscv.and"(%43, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.sra"(%38, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.rem"(%34, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.rem"(%36, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %25 = "riscv.remu"(%28, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.xor"(%25, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %21 = "riscv.sltu"(%20, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_92.mlir b/benchmarks/VEIR_ASM/7_function_92.mlir new file mode 100644 index 0000000..0d4138f --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_92.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.and"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.xor"(%34, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i1 + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%27) : (i1) -> !riscv.reg + %22 = "riscv.czero.eqz"(%19, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.czero.nez"(%37, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.or"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%24) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_93.mlir b/benchmarks/VEIR_ASM/7_function_93.mlir new file mode 100644 index 0000000..c3ab745 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_93.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.divu"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%24, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.divu"(%28, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_94.mlir b/benchmarks/VEIR_ASM/7_function_94.mlir new file mode 100644 index 0000000..35e1629 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_94.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "riscv.div"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.rem"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.div"(%37, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.rem"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %25 = "riscv.srl"(%29, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.div"(%41, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%18) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_95.mlir b/benchmarks/VEIR_ASM/7_function_95.mlir new file mode 100644 index 0000000..d6db816 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_95.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.div"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.xor"(%33, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.sra"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.divu"(%34, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %19 = "builtin.unrealized_conversion_cast"(%23) : (i32) -> !riscv.reg + %20 = "riscv.zext.w"(%19) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_96.mlir b/benchmarks/VEIR_ASM/7_function_96.mlir new file mode 100644 index 0000000..796e290 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_96.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.sra"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.sra"(%41, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.sra"(%31, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %25 = "riscv.xor"(%24, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xor"(%25, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%18) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_97.mlir b/benchmarks/VEIR_ASM/7_function_97.mlir new file mode 100644 index 0000000..708467c --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_97.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "riscv.remu"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %35 = "riscv.zext.w"(%34) : (!riscv.reg) -> !riscv.reg + %32 = "riscv.srl"(%39, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %23 = "riscv.xor"(%26, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %19 = "riscv.sra"(%17, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_98.mlir b/benchmarks/VEIR_ASM/7_function_98.mlir new file mode 100644 index 0000000..992be82 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_98.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "riscv.or"(%45, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "riscv.divu"(%40, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.slt"(%46, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i1 + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.sra"(%46, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%39) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %23 = "riscv.and"(%30, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "riscv.sra"(%23, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/7_function_99.mlir b/benchmarks/VEIR_ASM/7_function_99.mlir new file mode 100644 index 0000000..f501431 --- /dev/null +++ b/benchmarks/VEIR_ASM/7_function_99.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "riscv.div"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.and"(%36, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.div"(%41, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i1 + %28 = "builtin.unrealized_conversion_cast"(%41) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.sext.w"(%24) : (!riscv.reg) -> !riscv.reg + %17 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%30) : (i1) -> !riscv.reg + %20 = "riscv.czero.eqz"(%17, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.czero.nez"(%25, %19) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%20, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i64 + "func.return"(%23) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_0.mlir b/benchmarks/VEIR_ASM/8_function_0.mlir new file mode 100644 index 0000000..e31fef9 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_0.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "riscv.divu"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.sra"(%32, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.or"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.divu"(%30, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.and"(%26, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_1.mlir b/benchmarks/VEIR_ASM/8_function_1.mlir new file mode 100644 index 0000000..2f6bac1 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_1.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i32, %arg6_2 : i1): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %46 = "riscv.zext.w"(%45) : (!riscv.reg) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%46) : (!riscv.reg) -> i32 + %40 = "builtin.unrealized_conversion_cast"(%44) : (i32) -> !riscv.reg + %41 = "riscv.zext.w"(%40) : (!riscv.reg) -> !riscv.reg + %38 = "riscv.rem"(%46, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %34 = "riscv.sext.w"(%33) : (!riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%46, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%34, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.rem"(%34, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.rem"(%38, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_10.mlir b/benchmarks/VEIR_ASM/8_function_10.mlir new file mode 100644 index 0000000..e291015 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_10.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %50 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %51 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %52 = "riscv.divu"(%50, %51) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "riscv.or"(%52, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "riscv.xor"(%43, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i1 + %37 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %38 = "riscv.srl"(%52, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.slt"(%38, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i1 + %27 = "builtin.unrealized_conversion_cast"(%35) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%52, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%44, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%41) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%30, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%19, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i64 + "func.return"(%24) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_11.mlir b/benchmarks/VEIR_ASM/8_function_11.mlir new file mode 100644 index 0000000..559f9ca --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_11.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %45 = "riscv.srl"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.sra"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.remu"(%35, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.remu"(%37, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.div"(%45, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.and"(%25, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_12.mlir b/benchmarks/VEIR_ASM/8_function_12.mlir new file mode 100644 index 0000000..cf6dd63 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_12.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "riscv.rem"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %34 = "riscv.srl"(%43, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "riscv.and"(%43, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.div"(%24, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.srl"(%34, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_13.mlir b/benchmarks/VEIR_ASM/8_function_13.mlir new file mode 100644 index 0000000..3fcc5c5 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_13.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "riscv.remu"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%42) : (!riscv.reg) -> i32 + %35 = "builtin.unrealized_conversion_cast"(%39) : (i32) -> !riscv.reg + %36 = "riscv.sext.w"(%35) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "riscv.or"(%32, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.and"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.xor"(%29, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_14.mlir b/benchmarks/VEIR_ASM/8_function_14.mlir new file mode 100644 index 0000000..98ee857 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_14.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32, %arg6_3 : i1): + %50 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %51 = "riscv.sext.w"(%50) : (!riscv.reg) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %48 = "riscv.sra"(%46, %51) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.divu"(%42, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.remu"(%44, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %34 = "riscv.czero.eqz"(%31, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.czero.nez"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.or"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.srl"(%36, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.remu"(%40, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%25, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xori"(%20) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_15.mlir b/benchmarks/VEIR_ASM/8_function_15.mlir new file mode 100644 index 0000000..6936269 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_15.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %48 = "riscv.sra"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "riscv.remu"(%48, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.sltu"(%38, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i1 + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.div"(%34, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%41) : (i1) -> !riscv.reg + %30 = "riscv.czero.eqz"(%27, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.czero.nez"(%36, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.or"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.and"(%25, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_16.mlir b/benchmarks/VEIR_ASM/8_function_16.mlir new file mode 100644 index 0000000..6066465 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_16.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %44 = "riscv.sext.w"(%43) : (!riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.or"(%44, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.rem"(%44, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%37) : (!riscv.reg) -> i32 + %30 = "builtin.unrealized_conversion_cast"(%34) : (i32) -> !riscv.reg + %31 = "riscv.zext.w"(%30) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.remu"(%26, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%28, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.div"(%41, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_17.mlir b/benchmarks/VEIR_ASM/8_function_17.mlir new file mode 100644 index 0000000..47d69ce --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_17.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %45 = "riscv.zext.w"(%44) : (!riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.remu"(%45, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.remu"(%36, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.div"(%32, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.and"(%34, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%30, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.sra"(%42, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_18.mlir b/benchmarks/VEIR_ASM/8_function_18.mlir new file mode 100644 index 0000000..221cd2e --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_18.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%42) : (!riscv.reg) -> i32 + %39 = "builtin.unrealized_conversion_cast"(%43) : (i32) -> !riscv.reg + %40 = "riscv.zext.w"(%39) : (!riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.srl"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.remu"(%40, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.srl"(%40, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%29, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_19.mlir b/benchmarks/VEIR_ASM/8_function_19.mlir new file mode 100644 index 0000000..22e6290 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_19.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.or"(%45, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "riscv.or"(%41, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.remu"(%42, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i1 + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%35) : (i1) -> !riscv.reg + %30 = "riscv.czero.eqz"(%27, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.czero.nez"(%38, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.or"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%32, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_2.mlir b/benchmarks/VEIR_ASM/8_function_2.mlir new file mode 100644 index 0000000..c53b8d6 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_2.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %46 = "riscv.sext.w"(%45) : (!riscv.reg) -> !riscv.reg + %43 = "riscv.and"(%46, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %39 = "riscv.sext.w"(%38) : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.remu"(%34, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.srl"(%43, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "riscv.and"(%32, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.remu"(%28, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_20.mlir b/benchmarks/VEIR_ASM/8_function_20.mlir new file mode 100644 index 0000000..f07f0f4 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_20.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "riscv.sra"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %39 = "riscv.rem"(%43, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %32 = "builtin.unrealized_conversion_cast"(%36) : (i32) -> !riscv.reg + %33 = "riscv.zext.w"(%32) : (!riscv.reg) -> !riscv.reg + %30 = "riscv.srl"(%33, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.divu"(%43, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.and"(%21, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_21.mlir b/benchmarks/VEIR_ASM/8_function_21.mlir new file mode 100644 index 0000000..aec5a0d --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_21.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %37 = "builtin.unrealized_conversion_cast"(%41) : (i32) -> !riscv.reg + %38 = "riscv.zext.w"(%37) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.rem"(%33, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.divu"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.and"(%31, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_22.mlir b/benchmarks/VEIR_ASM/8_function_22.mlir new file mode 100644 index 0000000..7fc45a2 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_22.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %50 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %51 = "builtin.unrealized_conversion_cast"(%50) : (!riscv.reg) -> i1 + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "riscv.srl"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "riscv.sra"(%48, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "riscv.remu"(%38, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.srl"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%51) : (i1) -> !riscv.reg + %30 = "riscv.czero.eqz"(%36, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.czero.nez"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.or"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%51) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%40, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%32, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_23.mlir b/benchmarks/VEIR_ASM/8_function_23.mlir new file mode 100644 index 0000000..81e65b9 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_23.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %37 = "builtin.unrealized_conversion_cast"(%41) : (i32) -> !riscv.reg + %38 = "riscv.zext.w"(%37) : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.divu"(%38, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.div"(%29, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%35, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_24.mlir b/benchmarks/VEIR_ASM/8_function_24.mlir new file mode 100644 index 0000000..c066528 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_24.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "riscv.and"(%42, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.zext.w"(%36) : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %31 = "builtin.unrealized_conversion_cast"(%35) : (i32) -> !riscv.reg + %32 = "riscv.sext.w"(%31) : (!riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.divu"(%27, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.srl"(%37, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.slt"(%25, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xori"(%20) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_25.mlir b/benchmarks/VEIR_ASM/8_function_25.mlir new file mode 100644 index 0000000..9603d90 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_25.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64, %arg6_3 : i32): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %43 = "riscv.czero.eqz"(%40, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.czero.nez"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "riscv.or"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.div"(%36, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %34 = "riscv.sext.w"(%33) : (!riscv.reg) -> !riscv.reg + %31 = "riscv.srl"(%38, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.srl"(%31, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_26.mlir b/benchmarks/VEIR_ASM/8_function_26.mlir new file mode 100644 index 0000000..652da51 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_26.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "riscv.and"(%46, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %43 = "riscv.sext.w"(%42) : (!riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.divu"(%38, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.and"(%35, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.sra"(%36, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.divu"(%40, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.sra"(%47, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.div"(%24, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_27.mlir b/benchmarks/VEIR_ASM/8_function_27.mlir new file mode 100644 index 0000000..03e6c5e --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_27.mlir @@ -0,0 +1,27 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %46 = "riscv.czero.eqz"(%43, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "riscv.czero.nez"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %48 = "riscv.or"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.sra"(%48, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.and"(%41, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.srl"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.sra"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.remu"(%18, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_28.mlir b/benchmarks/VEIR_ASM/8_function_28.mlir new file mode 100644 index 0000000..f9f2a2b --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_28.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%45) : (!riscv.reg) -> i1 + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %43 = "riscv.zext.w"(%42) : (!riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%46) : (i1) -> !riscv.reg + %38 = "riscv.czero.eqz"(%43, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.czero.nez"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.or"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %33 = "riscv.zext.w"(%32) : (!riscv.reg) -> !riscv.reg + %30 = "riscv.sra"(%40, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %23 = "builtin.unrealized_conversion_cast"(%27) : (i32) -> !riscv.reg + %24 = "riscv.zext.w"(%23) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%30, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xori"(%20) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_29.mlir b/benchmarks/VEIR_ASM/8_function_29.mlir new file mode 100644 index 0000000..b2d7bc7 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_29.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %49 = "riscv.and"(%48, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "riscv.rem"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.xor"(%45, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.xor"(%36, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%49, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.rem"(%41, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.srl"(%26, %21) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_3.mlir b/benchmarks/VEIR_ASM/8_function_3.mlir new file mode 100644 index 0000000..315ba7a --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_3.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.zext.w"(%36) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.sra"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%28) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.remu"(%18, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_30.mlir b/benchmarks/VEIR_ASM/8_function_30.mlir new file mode 100644 index 0000000..1b1d33e --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_30.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "riscv.xor"(%46, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %43 = "riscv.zext.w"(%42) : (!riscv.reg) -> !riscv.reg + %40 = "riscv.and"(%43, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.sra"(%34, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "riscv.and"(%31, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.srl"(%40, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.sra"(%36, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.slt"(%40, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_31.mlir b/benchmarks/VEIR_ASM/8_function_31.mlir new file mode 100644 index 0000000..15d6b59 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_31.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %46 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "riscv.rem"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.divu"(%42, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i32 + %37 = "builtin.unrealized_conversion_cast"(%41) : (i32) -> !riscv.reg + %38 = "riscv.sext.w"(%37) : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.srl"(%44, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.sltu"(%38, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i1 + %27 = "riscv.rem"(%38, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%32) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i64 + "func.return"(%24) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_32.mlir b/benchmarks/VEIR_ASM/8_function_32.mlir new file mode 100644 index 0000000..b54f9ec --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_32.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i1, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %47 = "riscv.czero.eqz"(%44, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %48 = "riscv.czero.nez"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %49 = "riscv.or"(%47, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "riscv.and"(%49, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.srl"(%42, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.srl"(%49, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%28, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_33.mlir b/benchmarks/VEIR_ASM/8_function_33.mlir new file mode 100644 index 0000000..3a1e224 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_33.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %47 = "riscv.remu"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "riscv.remu"(%47, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.srl"(%43, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i1 + %30 = "builtin.unrealized_conversion_cast"(%36) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%39, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%43, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.remu"(%39, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.and"(%26, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_34.mlir b/benchmarks/VEIR_ASM/8_function_34.mlir new file mode 100644 index 0000000..faaba23 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_34.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.sra"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.rem"(%46, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %38 = "riscv.div"(%36, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%38, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%46, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.div"(%30, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%34, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_35.mlir b/benchmarks/VEIR_ASM/8_function_35.mlir new file mode 100644 index 0000000..d6af605 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_35.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.rem"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.div"(%40, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.srl"(%30, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_36.mlir b/benchmarks/VEIR_ASM/8_function_36.mlir new file mode 100644 index 0000000..bb8fd2e --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_36.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %46 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %48 = "riscv.remu"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %44 = "riscv.zext.w"(%43) : (!riscv.reg) -> !riscv.reg + %41 = "riscv.remu"(%44, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.xor"(%41, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.rem"(%37, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%48, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%29, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_37.mlir b/benchmarks/VEIR_ASM/8_function_37.mlir new file mode 100644 index 0000000..de794af --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_37.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.xor"(%45, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "riscv.rem"(%46, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.divu"(%36, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %34 = "riscv.or"(%38, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.xor"(%34, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.remu"(%46, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.remu"(%26, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_38.mlir b/benchmarks/VEIR_ASM/8_function_38.mlir new file mode 100644 index 0000000..a7b5fd3 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_38.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %48 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %49 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %50 = "riscv.sltu"(%49, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %51 = "riscv.xori"(%50) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %52 = "builtin.unrealized_conversion_cast"(%51) : (!riscv.reg) -> i1 + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.or"(%45, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "riscv.divu"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.xor"(%42, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.xor"(%38, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.and"(%34, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%52) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%30, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i64 + "func.return"(%24) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_39.mlir b/benchmarks/VEIR_ASM/8_function_39.mlir new file mode 100644 index 0000000..f70de37 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_39.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i64): + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %49 = "riscv.or"(%48, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "riscv.sra"(%43, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %39 = "riscv.czero.eqz"(%36, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.czero.nez"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.or"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.and"(%33, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%41, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.divu"(%30, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.or"(%26, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_4.mlir b/benchmarks/VEIR_ASM/8_function_4.mlir new file mode 100644 index 0000000..2654030 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_4.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %49 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %50 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %51 = "riscv.divu"(%49, %50) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %47 = "riscv.srl"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.sra"(%51, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %37 = "riscv.czero.eqz"(%34, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.czero.nez"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.or"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.sra"(%39, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.or"(%32, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%28, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_40.mlir b/benchmarks/VEIR_ASM/8_function_40.mlir new file mode 100644 index 0000000..7f26a67 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_40.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %49 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %50 = "builtin.unrealized_conversion_cast"(%49) : (!riscv.reg) -> i32 + %46 = "builtin.unrealized_conversion_cast"(%50) : (i32) -> !riscv.reg + %47 = "riscv.zext.w"(%46) : (!riscv.reg) -> !riscv.reg + %43 = "riscv.sltu"(%47, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.xori"(%43) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i1 + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%45) : (i1) -> !riscv.reg + %37 = "riscv.czero.eqz"(%34, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.czero.nez"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.or"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.or"(%39, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "riscv.sra"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.or"(%28, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sra"(%32, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_41.mlir b/benchmarks/VEIR_ASM/8_function_41.mlir new file mode 100644 index 0000000..70abefe --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_41.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %50 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %51 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %52 = "riscv.slt"(%50, %51) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %53 = "riscv.xori"(%52) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %54 = "builtin.unrealized_conversion_cast"(%53) : (!riscv.reg) -> i1 + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%54) : (i1) -> !riscv.reg + %46 = "riscv.czero.eqz"(%43, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "riscv.czero.nez"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %48 = "riscv.or"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.sra"(%39, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.and"(%41, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.xor"(%37, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.remu"(%48, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%54) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%37, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%29, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_42.mlir b/benchmarks/VEIR_ASM/8_function_42.mlir new file mode 100644 index 0000000..5dfcf59 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_42.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.div"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%46) : (!riscv.reg) -> i1 + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "riscv.srl"(%46, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %33 = "builtin.unrealized_conversion_cast"(%37) : (i32) -> !riscv.reg + %34 = "riscv.zext.w"(%33) : (!riscv.reg) -> !riscv.reg + %31 = "riscv.rem"(%46, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.srl"(%31, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%43) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%18, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%27, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i64 + "func.return"(%24) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_43.mlir b/benchmarks/VEIR_ASM/8_function_43.mlir new file mode 100644 index 0000000..1c4f0a5 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_43.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i1, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %45 = "riscv.sext.w"(%44) : (!riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %40 = "riscv.czero.eqz"(%37, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.czero.nez"(%45, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "riscv.or"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.sra"(%45, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.sext.w"(%28) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.remu"(%45, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.divu"(%29, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_44.mlir b/benchmarks/VEIR_ASM/8_function_44.mlir new file mode 100644 index 0000000..ed82df2 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_44.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.div"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%46) : (!riscv.reg) -> i32 + %39 = "builtin.unrealized_conversion_cast"(%43) : (i32) -> !riscv.reg + %40 = "riscv.zext.w"(%39) : (!riscv.reg) -> !riscv.reg + %37 = "riscv.remu"(%46, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.and"(%37, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.div"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%29, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.slt"(%40, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xori"(%20) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_45.mlir b/benchmarks/VEIR_ASM/8_function_45.mlir new file mode 100644 index 0000000..9ef1dd8 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_45.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "riscv.rem"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "riscv.srl"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.remu"(%47, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %35 = "riscv.sext.w"(%34) : (!riscv.reg) -> !riscv.reg + %32 = "riscv.sra"(%39, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %28 = "riscv.and"(%27, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.rem"(%28, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.srl"(%32, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_46.mlir b/benchmarks/VEIR_ASM/8_function_46.mlir new file mode 100644 index 0000000..8acde42 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_46.mlir @@ -0,0 +1,27 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.sltu"(%45, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%46) : (!riscv.reg) -> i1 + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%47) : (i1) -> !riscv.reg + %40 = "riscv.czero.eqz"(%37, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.czero.nez"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "riscv.or"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.divu"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.div"(%42, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.div"(%31, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_47.mlir b/benchmarks/VEIR_ASM/8_function_47.mlir new file mode 100644 index 0000000..fd0c5d3 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_47.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %46 = "riscv.sext.w"(%45) : (!riscv.reg) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%46) : (!riscv.reg) -> i1 + %41 = "riscv.rem"(%46, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%44) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%41, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.xor"(%29, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "riscv.divu"(%30, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%37, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_48.mlir b/benchmarks/VEIR_ASM/8_function_48.mlir new file mode 100644 index 0000000..1552821 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_48.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%45) : (!riscv.reg) -> i32 + %42 = "builtin.unrealized_conversion_cast"(%46) : (i32) -> !riscv.reg + %43 = "riscv.sext.w"(%42) : (!riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.div"(%38, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "riscv.divu"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.srl"(%30, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.remu"(%43, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.xor"(%28, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.rem"(%40, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_49.mlir b/benchmarks/VEIR_ASM/8_function_49.mlir new file mode 100644 index 0000000..7178b4e --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_49.mlir @@ -0,0 +1,27 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1, %arg6_3 : i32): + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %49 = "riscv.czero.eqz"(%46, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %50 = "riscv.czero.nez"(%47, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %51 = "riscv.or"(%49, %50) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %44 = "riscv.sext.w"(%43) : (!riscv.reg) -> !riscv.reg + %41 = "riscv.divu"(%51, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.and"(%41, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.and"(%33, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.and"(%26, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_5.mlir b/benchmarks/VEIR_ASM/8_function_5.mlir new file mode 100644 index 0000000..8799792 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_5.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "riscv.sra"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "riscv.srl"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %33 = "builtin.unrealized_conversion_cast"(%37) : (i32) -> !riscv.reg + %34 = "riscv.sext.w"(%33) : (!riscv.reg) -> !riscv.reg + %31 = "riscv.rem"(%44, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.sext.w"(%24) : (!riscv.reg) -> !riscv.reg + %18 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %20 = "riscv.xor"(%25, %18) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.lui"() {immediate = 0 : i20} : () -> !riscv.reg + %22 = "riscv.sltu"(%21, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%23) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_50.mlir b/benchmarks/VEIR_ASM/8_function_50.mlir new file mode 100644 index 0000000..ceeb858 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_50.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %49 = "riscv.sra"(%47, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %45 = "riscv.div"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.divu"(%49, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%41, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%37, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %27 = "riscv.czero.eqz"(%33, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.czero.nez"(%41, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.srl"(%41, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_51.mlir b/benchmarks/VEIR_ASM/8_function_51.mlir new file mode 100644 index 0000000..ef3d3b2 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_51.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %45 = "riscv.sra"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.and"(%45, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%41, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.xor"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %26 = "riscv.srl"(%33, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.div"(%37, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_52.mlir b/benchmarks/VEIR_ASM/8_function_52.mlir new file mode 100644 index 0000000..8446909 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_52.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "riscv.div"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %33 = "builtin.unrealized_conversion_cast"(%37) : (i32) -> !riscv.reg + %34 = "riscv.sext.w"(%33) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.remu"(%29, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %27 = "riscv.srl"(%25, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_53.mlir b/benchmarks/VEIR_ASM/8_function_53.mlir new file mode 100644 index 0000000..b3e5111 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_53.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i1 + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "riscv.and"(%41, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%45) : (i1) -> !riscv.reg + %36 = "riscv.czero.eqz"(%42, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.czero.nez"(%42, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.or"(%36, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.srl"(%38, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %27 = "riscv.or"(%26, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_54.mlir b/benchmarks/VEIR_ASM/8_function_54.mlir new file mode 100644 index 0000000..9d6a6de --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_54.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.or"(%43, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %40 = "riscv.zext.w"(%39) : (!riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %37 = "riscv.srl"(%35, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %33 = "riscv.sext.w"(%32) : (!riscv.reg) -> !riscv.reg + %30 = "riscv.remu"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.and"(%33, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%44, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_55.mlir b/benchmarks/VEIR_ASM/8_function_55.mlir new file mode 100644 index 0000000..2734bfb --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_55.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %45 = "riscv.divu"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.or"(%40, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.divu"(%35, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.div"(%41, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.divu"(%27, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.remu"(%45, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.zext.w"(%18) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_56.mlir b/benchmarks/VEIR_ASM/8_function_56.mlir new file mode 100644 index 0000000..269521b --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_56.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "riscv.div"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.zext.w"(%36) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.or"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.remu"(%28, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.div"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%43, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_57.mlir b/benchmarks/VEIR_ASM/8_function_57.mlir new file mode 100644 index 0000000..3fadb27 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_57.mlir @@ -0,0 +1,30 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %52 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %53 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %54 = "riscv.and"(%53, %52) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %50 = "riscv.and"(%54, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %46 = "riscv.slt"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%46) : (!riscv.reg) -> i1 + %39 = "builtin.unrealized_conversion_cast"(%47) : (i1) -> !riscv.reg + %40 = "riscv.czero.eqz"(%54, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.czero.nez"(%54, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "riscv.or"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.sltu"(%50, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i1 + %26 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%36) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%26, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%42, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.or"(%31, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.slt"(%24, %50) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_58.mlir b/benchmarks/VEIR_ASM/8_function_58.mlir new file mode 100644 index 0000000..2d52a05 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_58.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "riscv.div"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.and"(%42, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i32 + %31 = "builtin.unrealized_conversion_cast"(%35) : (i32) -> !riscv.reg + %32 = "riscv.sext.w"(%31) : (!riscv.reg) -> !riscv.reg + %29 = "riscv.remu"(%42, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.zext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.slt"(%32, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_59.mlir b/benchmarks/VEIR_ASM/8_function_59.mlir new file mode 100644 index 0000000..889b669 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_59.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "riscv.and"(%42, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.divu"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.divu"(%37, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.rem"(%34, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%30, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_6.mlir b/benchmarks/VEIR_ASM/8_function_6.mlir new file mode 100644 index 0000000..415e063 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_6.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %49 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %50 = "riscv.zext.w"(%49) : (!riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %45 = "riscv.czero.eqz"(%42, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "riscv.czero.nez"(%50, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "riscv.or"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "riscv.or"(%47, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.rem"(%40, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.xor"(%36, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.divu"(%32, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.rem"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sra"(%50, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_60.mlir b/benchmarks/VEIR_ASM/8_function_60.mlir new file mode 100644 index 0000000..eec52a3 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_60.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i32 + %41 = "builtin.unrealized_conversion_cast"(%45) : (i32) -> !riscv.reg + %42 = "riscv.sext.w"(%41) : (!riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i1 + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%40) : (i1) -> !riscv.reg + %35 = "riscv.czero.eqz"(%32, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.czero.nez"(%33, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.or"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %30 = "riscv.rem"(%28, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%30, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.div"(%42, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_61.mlir b/benchmarks/VEIR_ASM/8_function_61.mlir new file mode 100644 index 0000000..7f2bae1 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_61.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i32 + %40 = "builtin.unrealized_conversion_cast"(%44) : (i32) -> !riscv.reg + %41 = "riscv.zext.w"(%40) : (!riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %38 = "riscv.xor"(%37, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.or"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.rem"(%34, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.xor"(%30, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.srl"(%20, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_62.mlir b/benchmarks/VEIR_ASM/8_function_62.mlir new file mode 100644 index 0000000..3819b71 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_62.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %44 = "riscv.zext.w"(%43) : (!riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "riscv.divu"(%39, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.div"(%41, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.xor"(%37, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %24 = "riscv.sra"(%33, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %20 = "riscv.and"(%19, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_63.mlir b/benchmarks/VEIR_ASM/8_function_63.mlir new file mode 100644 index 0000000..a748acb --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_63.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %51 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %52 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %53 = "riscv.rem"(%51, %52) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %48 = "riscv.sltu"(%47, %53) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %49 = "riscv.xori"(%48) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %50 = "builtin.unrealized_conversion_cast"(%49) : (!riscv.reg) -> i1 + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "riscv.srl"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.div"(%53, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%50) : (i1) -> !riscv.reg + %34 = "riscv.czero.eqz"(%31, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.czero.nez"(%40, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.or"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.remu"(%27, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.srl"(%40, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%25, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xori"(%20) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_64.mlir b/benchmarks/VEIR_ASM/8_function_64.mlir new file mode 100644 index 0000000..a164b667 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_64.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.srl"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.or"(%41, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %38 = "riscv.divu"(%42, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.xor"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.div"(%34, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.remu"(%38, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%46, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_65.mlir b/benchmarks/VEIR_ASM/8_function_65.mlir new file mode 100644 index 0000000..164f4b8 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_65.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "riscv.rem"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.srl"(%34, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%36) : (!riscv.reg) -> i32 + %29 = "builtin.unrealized_conversion_cast"(%33) : (i32) -> !riscv.reg + %30 = "riscv.sext.w"(%29) : (!riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.zext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%25, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_66.mlir b/benchmarks/VEIR_ASM/8_function_66.mlir new file mode 100644 index 0000000..8b92189 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_66.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "riscv.rem"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i32 + %35 = "builtin.unrealized_conversion_cast"(%39) : (i32) -> !riscv.reg + %36 = "riscv.sext.w"(%35) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.div"(%42, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%33) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %24 = "riscv.rem"(%36, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.and"(%24, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_67.mlir b/benchmarks/VEIR_ASM/8_function_67.mlir new file mode 100644 index 0000000..c171634 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_67.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %49 = "riscv.rem"(%47, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "riscv.and"(%44, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "riscv.or"(%45, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "riscv.or"(%41, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.div"(%49, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.and"(%33, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%29, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%25, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xori"(%20) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_68.mlir b/benchmarks/VEIR_ASM/8_function_68.mlir new file mode 100644 index 0000000..151e013 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_68.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "riscv.div"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.divu"(%34, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.rem"(%36, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.sext.w"(%25) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_69.mlir b/benchmarks/VEIR_ASM/8_function_69.mlir new file mode 100644 index 0000000..5591ef8 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_69.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %48 = "riscv.rem"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %44 = "riscv.divu"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.div"(%48, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.rem"(%48, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.or"(%36, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.div"(%44, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.div"(%28, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.rem"(%40, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_7.mlir b/benchmarks/VEIR_ASM/8_function_7.mlir new file mode 100644 index 0000000..d444c5c --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_7.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %49 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %50 = "riscv.sext.w"(%49) : (!riscv.reg) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %47 = "riscv.and"(%50, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.remu"(%50, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %37 = "riscv.czero.eqz"(%47, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.czero.nez"(%43, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.or"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.and"(%39, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.and"(%32, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%24, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_70.mlir b/benchmarks/VEIR_ASM/8_function_70.mlir new file mode 100644 index 0000000..f9a9f7a --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_70.mlir @@ -0,0 +1,32 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i1, %arg6_2 : i32): + %54 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %55 = "riscv.sext.w"(%54) : (!riscv.reg) -> !riscv.reg + %50 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %51 = "riscv.xor"(%50, %55) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %52 = "riscv.sltiu"(%51) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %53 = "builtin.unrealized_conversion_cast"(%52) : (!riscv.reg) -> i1 + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %45 = "riscv.czero.eqz"(%42, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "riscv.czero.nez"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "riscv.or"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%53) : (i1) -> !riscv.reg + %38 = "riscv.czero.eqz"(%55, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.czero.nez"(%47, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.or"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %33 = "riscv.srl"(%31, %55) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i1) -> !riscv.reg + %27 = "riscv.czero.eqz"(%40, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.czero.nez"(%33, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.or"(%27, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %22 = "riscv.srl"(%20, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_71.mlir b/benchmarks/VEIR_ASM/8_function_71.mlir new file mode 100644 index 0000000..e95023d --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_71.mlir @@ -0,0 +1,32 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %51 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %52 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %53 = "riscv.or"(%52, %51) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %49 = "riscv.slt"(%48, %53) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %50 = "builtin.unrealized_conversion_cast"(%49) : (!riscv.reg) -> i1 + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%50) : (i1) -> !riscv.reg + %43 = "riscv.czero.eqz"(%53, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.czero.nez"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "riscv.or"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%45) : (!riscv.reg) -> i1 + %37 = "builtin.unrealized_conversion_cast"(%45) : (!riscv.reg) -> i1 + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%32, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%37) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%25, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%39) : (i1) -> !riscv.reg + %21 = "riscv.czero.eqz"(%45, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.czero.nez"(%30, %20) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = "riscv.or"(%21, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%23) : (!riscv.reg) -> i64 + "func.return"(%24) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_72.mlir b/benchmarks/VEIR_ASM/8_function_72.mlir new file mode 100644 index 0000000..4c4e212 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_72.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %37 = "builtin.unrealized_conversion_cast"(%41) : (i32) -> !riscv.reg + %38 = "riscv.sext.w"(%37) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %35 = "riscv.xor"(%34, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i32 + %28 = "builtin.unrealized_conversion_cast"(%32) : (i32) -> !riscv.reg + %29 = "riscv.zext.w"(%28) : (!riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "riscv.divu"(%29, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.sra"(%38, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_73.mlir b/benchmarks/VEIR_ASM/8_function_73.mlir new file mode 100644 index 0000000..74e6757 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_73.mlir @@ -0,0 +1,19 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "riscv.rem"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.divu"(%32, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.divu"(%34, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.xor"(%34, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.sra"(%34, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_74.mlir b/benchmarks/VEIR_ASM/8_function_74.mlir new file mode 100644 index 0000000..8071bda --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_74.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %45 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "riscv.divu"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "riscv.and"(%47, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i1 + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.divu"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%43, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %29 = "riscv.and"(%28, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%40) : (i1) -> !riscv.reg + %23 = "riscv.czero.eqz"(%33, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.czero.nez"(%29, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%23, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_75.mlir b/benchmarks/VEIR_ASM/8_function_75.mlir new file mode 100644 index 0000000..8a9b010 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_75.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.remu"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%42) : (!riscv.reg) -> i32 + %35 = "builtin.unrealized_conversion_cast"(%39) : (i32) -> !riscv.reg + %36 = "riscv.sext.w"(%35) : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %33 = "riscv.xor"(%32, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.and"(%33, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.or"(%23, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_76.mlir b/benchmarks/VEIR_ASM/8_function_76.mlir new file mode 100644 index 0000000..d3f1768 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_76.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.divu"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "riscv.div"(%44, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%36) : (!riscv.reg) -> i1 + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%37) : (i1) -> !riscv.reg + %32 = "riscv.czero.eqz"(%29, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.czero.nez"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.or"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.rem"(%40, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%27) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_77.mlir b/benchmarks/VEIR_ASM/8_function_77.mlir new file mode 100644 index 0000000..c911773 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_77.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %48 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %49 = "builtin.unrealized_conversion_cast"(%48) : (!riscv.reg) -> i32 + %45 = "builtin.unrealized_conversion_cast"(%49) : (i32) -> !riscv.reg + %46 = "riscv.sext.w"(%45) : (!riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "riscv.xor"(%42, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %37 = "riscv.czero.eqz"(%43, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.czero.nez"(%35, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.or"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "riscv.div"(%30, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.rem"(%39, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.or"(%28, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xor"(%24, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_78.mlir b/benchmarks/VEIR_ASM/8_function_78.mlir new file mode 100644 index 0000000..8b93d94 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_78.mlir @@ -0,0 +1,28 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i1): + %52 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %53 = "riscv.zext.w"(%52) : (!riscv.reg) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %49 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %50 = "riscv.or"(%49, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %44 = "riscv.czero.eqz"(%41, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "riscv.czero.nez"(%42, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "riscv.or"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i1) -> !riscv.reg + %37 = "riscv.czero.eqz"(%34, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.czero.nez"(%46, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.or"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.div"(%46, %53) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.srl"(%39, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.remu"(%50, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.divu"(%53, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_79.mlir b/benchmarks/VEIR_ASM/8_function_79.mlir new file mode 100644 index 0000000..7fdd31e --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_79.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "riscv.divu"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%45) : (!riscv.reg) -> i32 + %38 = "builtin.unrealized_conversion_cast"(%42) : (i32) -> !riscv.reg + %39 = "riscv.sext.w"(%38) : (!riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %34 = "riscv.czero.eqz"(%31, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.czero.nez"(%32, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.or"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%36) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.div"(%22, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%39, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_8.mlir b/benchmarks/VEIR_ASM/8_function_8.mlir new file mode 100644 index 0000000..09ce26b --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_8.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %48 = "riscv.or"(%47, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.and"(%48, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "riscv.xor"(%39, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "riscv.and"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %32 = "riscv.zext.w"(%31) : (!riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %29 = "riscv.and"(%28, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "riscv.or"(%29, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.xor"(%25, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.sltiu"(%20) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_80.mlir b/benchmarks/VEIR_ASM/8_function_80.mlir new file mode 100644 index 0000000..4c58d5a --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_80.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.divu"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "riscv.remu"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %38 = "riscv.srl"(%36, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.or"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.rem"(%34, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.srl"(%38, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.rem"(%46, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_81.mlir b/benchmarks/VEIR_ASM/8_function_81.mlir new file mode 100644 index 0000000..27aa3c7 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_81.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %49 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %50 = "builtin.unrealized_conversion_cast"(%49) : (!riscv.reg) -> i1 + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%50) : (i1) -> !riscv.reg + %45 = "riscv.czero.eqz"(%42, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "riscv.czero.nez"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "riscv.or"(%45, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "riscv.div"(%38, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.sra"(%47, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.and"(%47, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.div"(%32, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.div"(%36, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sra"(%32, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_82.mlir b/benchmarks/VEIR_ASM/8_function_82.mlir new file mode 100644 index 0000000..c2270fb --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_82.mlir @@ -0,0 +1,29 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i1): + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %49 = "riscv.remu"(%47, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i1) -> !riscv.reg + %43 = "riscv.czero.eqz"(%40, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %44 = "riscv.czero.nez"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "riscv.or"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.slt"(%45, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i1 + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.or"(%33, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%39) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%49, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_83.mlir b/benchmarks/VEIR_ASM/8_function_83.mlir new file mode 100644 index 0000000..9c60fc0 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_83.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "riscv.divu"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "riscv.div"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.remu"(%43, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.sra"(%43, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.sext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.srl"(%35, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_84.mlir b/benchmarks/VEIR_ASM/8_function_84.mlir new file mode 100644 index 0000000..cab8d41 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_84.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i32): + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%39) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i32) -> !riscv.reg + %34 = "riscv.zext.w"(%33) : (!riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %31 = "riscv.rem"(%29, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%31) : (!riscv.reg) -> i32 + %24 = "builtin.unrealized_conversion_cast"(%28) : (i32) -> !riscv.reg + %25 = "riscv.sext.w"(%24) : (!riscv.reg) -> !riscv.reg + %22 = "riscv.and"(%25, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_85.mlir b/benchmarks/VEIR_ASM/8_function_85.mlir new file mode 100644 index 0000000..962734c --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_85.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.and"(%45, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%46) : (!riscv.reg) -> i1 + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%40) : (!riscv.reg) -> i32 + %37 = "builtin.unrealized_conversion_cast"(%41) : (i32) -> !riscv.reg + %38 = "riscv.zext.w"(%37) : (!riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %35 = "riscv.remu"(%38, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%43) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%35, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%35, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.divu"(%22, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.slt"(%24, %31) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_86.mlir b/benchmarks/VEIR_ASM/8_function_86.mlir new file mode 100644 index 0000000..ba84823 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_86.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %45 = "riscv.divu"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %41 = "riscv.zext.w"(%40) : (!riscv.reg) -> !riscv.reg + %38 = "riscv.srl"(%45, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.and"(%38, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%34) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.sext.w"(%27) : (!riscv.reg) -> !riscv.reg + %25 = "riscv.xor"(%28, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.slt"(%25, %25) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "riscv.xori"(%20) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i1 + "func.return"(%22) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_87.mlir b/benchmarks/VEIR_ASM/8_function_87.mlir new file mode 100644 index 0000000..12b71ac --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_87.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i32, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i32) -> !riscv.reg + %41 = "riscv.sext.w"(%40) : (!riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.remu"(%41, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.srl"(%38, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %27 = "builtin.unrealized_conversion_cast"(%31) : (i32) -> !riscv.reg + %28 = "riscv.zext.w"(%27) : (!riscv.reg) -> !riscv.reg + %25 = "riscv.sra"(%34, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%25) : (!riscv.reg) -> i32 + %18 = "builtin.unrealized_conversion_cast"(%22) : (i32) -> !riscv.reg + %19 = "riscv.sext.w"(%18) : (!riscv.reg) -> !riscv.reg + %20 = "builtin.unrealized_conversion_cast"(%19) : (!riscv.reg) -> i64 + "func.return"(%20) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_88.mlir b/benchmarks/VEIR_ASM/8_function_88.mlir new file mode 100644 index 0000000..98ec094 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_88.mlir @@ -0,0 +1,24 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %46 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "riscv.rem"(%46, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.xor"(%48, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %40 = "riscv.xor"(%39, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.xor"(%40, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.div"(%44, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %28 = "riscv.rem"(%32, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %24 = "riscv.xor"(%23, %22) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%24, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_89.mlir b/benchmarks/VEIR_ASM/8_function_89.mlir new file mode 100644 index 0000000..6b2333b --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_89.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %38 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %40 = "riscv.xor"(%39, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %36 = "riscv.and"(%35, %34) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.div"(%40, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %25 = "builtin.unrealized_conversion_cast"(%29) : (i32) -> !riscv.reg + %26 = "riscv.zext.w"(%25) : (!riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%26) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_9.mlir b/benchmarks/VEIR_ASM/8_function_9.mlir new file mode 100644 index 0000000..ac0a6b1 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_9.mlir @@ -0,0 +1,21 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %45 = "riscv.sra"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%41) : (!riscv.reg) -> i32 + %38 = "builtin.unrealized_conversion_cast"(%42) : (i32) -> !riscv.reg + %39 = "riscv.sext.w"(%38) : (!riscv.reg) -> !riscv.reg + %36 = "riscv.remu"(%39, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.and"(%31, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.divu"(%36, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.rem"(%28, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.div"(%45, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_90.mlir b/benchmarks/VEIR_ASM/8_function_90.mlir new file mode 100644 index 0000000..e065df2 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_90.mlir @@ -0,0 +1,27 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %42 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "riscv.and"(%43, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%44) : (!riscv.reg) -> i32 + %37 = "builtin.unrealized_conversion_cast"(%41) : (i32) -> !riscv.reg + %38 = "riscv.sext.w"(%37) : (!riscv.reg) -> !riscv.reg + %32 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %34 = "riscv.xor"(%38, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.sltiu"(%34) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%35) : (!riscv.reg) -> i1 + %25 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%36) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%25, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%26, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.zext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_91.mlir b/benchmarks/VEIR_ASM/8_function_91.mlir new file mode 100644 index 0000000..ab65725 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_91.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "riscv.rem"(%43, %44) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.or"(%45, %39) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %37 = "riscv.xor"(%36, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.divu"(%41, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "riscv.div"(%33, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "builtin.unrealized_conversion_cast"(%29) : (!riscv.reg) -> i32 + %22 = "builtin.unrealized_conversion_cast"(%26) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.slt"(%41, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_92.mlir b/benchmarks/VEIR_ASM/8_function_92.mlir new file mode 100644 index 0000000..1aa0943 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_92.mlir @@ -0,0 +1,25 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64): + %46 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %48 = "riscv.and"(%47, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "riscv.divu"(%42, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "riscv.or"(%44, %48) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %34 = "riscv.czero.eqz"(%31, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "riscv.czero.nez"(%40, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "riscv.or"(%34, %35) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%36) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.sext.w"(%26) : (!riscv.reg) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %24 = "riscv.and"(%23, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.remu"(%27, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_93.mlir b/benchmarks/VEIR_ASM/8_function_93.mlir new file mode 100644 index 0000000..0879524 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_93.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i1, %arg6_1 : i64, %arg6_2 : i64): + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %43 = "riscv.rem"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i32 + %36 = "builtin.unrealized_conversion_cast"(%40) : (i32) -> !riscv.reg + %37 = "riscv.sext.w"(%36) : (!riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %34 = "riscv.divu"(%37, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i1) -> !riscv.reg + %28 = "riscv.czero.eqz"(%37, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "riscv.czero.nez"(%34, %27) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.or"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "builtin.unrealized_conversion_cast"(%30) : (!riscv.reg) -> i32 + %20 = "builtin.unrealized_conversion_cast"(%24) : (i32) -> !riscv.reg + %21 = "riscv.sext.w"(%20) : (!riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%21) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_94.mlir b/benchmarks/VEIR_ASM/8_function_94.mlir new file mode 100644 index 0000000..b0fcb48 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_94.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64, %arg6_3 : i32): + %48 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %49 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %50 = "riscv.div"(%48, %49) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.slt"(%45, %50) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %47 = "builtin.unrealized_conversion_cast"(%46) : (!riscv.reg) -> i1 + %40 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "riscv.sra"(%40, %50) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_3) : (i32) -> !riscv.reg + %38 = "riscv.sext.w"(%37) : (!riscv.reg) -> !riscv.reg + %35 = "riscv.rem"(%42, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%47) : (i1) -> !riscv.reg + %29 = "riscv.czero.eqz"(%50, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "riscv.czero.nez"(%35, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %31 = "riscv.or"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.rem"(%22, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sra"(%31, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_95.mlir b/benchmarks/VEIR_ASM/8_function_95.mlir new file mode 100644 index 0000000..fb38131 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_95.mlir @@ -0,0 +1,28 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %50 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %51 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %52 = "riscv.sra"(%50, %51) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %46 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %47 = "riscv.sltu"(%52, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %48 = "riscv.xori"(%47) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg + %49 = "builtin.unrealized_conversion_cast"(%48) : (!riscv.reg) -> i1 + %41 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %42 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %43 = "riscv.remu"(%41, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%49) : (i1) -> !riscv.reg + %37 = "riscv.czero.eqz"(%34, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.czero.nez"(%43, %36) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %39 = "riscv.or"(%37, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %32 = "riscv.divu"(%30, %52) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "riscv.sra"(%39, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = "riscv.divu"(%39, %28) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.sltu"(%39, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i1 + "func.return"(%21) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_96.mlir b/benchmarks/VEIR_ASM/8_function_96.mlir new file mode 100644 index 0000000..4c8b0e4 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_96.mlir @@ -0,0 +1,23 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.divu"(%40, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %36 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %38 = "riscv.rem"(%36, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %35 = "builtin.unrealized_conversion_cast"(%38) : (!riscv.reg) -> i32 + %31 = "builtin.unrealized_conversion_cast"(%35) : (i32) -> !riscv.reg + %32 = "riscv.sext.w"(%31) : (!riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%32) : (!riscv.reg) -> i32 + %26 = "builtin.unrealized_conversion_cast"(%30) : (i32) -> !riscv.reg + %27 = "riscv.zext.w"(%26) : (!riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %23 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %24 = "riscv.remu"(%22, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = "riscv.divu"(%27, %24) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_97.mlir b/benchmarks/VEIR_ASM/8_function_97.mlir new file mode 100644 index 0000000..185cd11 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_97.mlir @@ -0,0 +1,22 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i64, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i32): + %43 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%43) : (!riscv.reg) -> i32 + %40 = "builtin.unrealized_conversion_cast"(%44) : (i32) -> !riscv.reg + %41 = "riscv.sext.w"(%40) : (!riscv.reg) -> !riscv.reg + %37 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %38 = "riscv.xor"(%37, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %34 = "riscv.zext.w"(%33) : (!riscv.reg) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %31 = "riscv.remu"(%34, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %27 = "riscv.or"(%31, %38) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i32) -> !riscv.reg + %23 = "riscv.sext.w"(%22) : (!riscv.reg) -> !riscv.reg + %20 = "riscv.divu"(%27, %23) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = "builtin.unrealized_conversion_cast"(%20) : (!riscv.reg) -> i64 + "func.return"(%21) : (i64) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_98.mlir b/benchmarks/VEIR_ASM/8_function_98.mlir new file mode 100644 index 0000000..37a8011 --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_98.mlir @@ -0,0 +1,20 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i32, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %44 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %45 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %46 = "riscv.divu"(%44, %45) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %41 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %42 = "riscv.rem"(%46, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %38 = "riscv.or"(%46, %46) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %34 = "riscv.xor"(%38, %42) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %28 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "riscv.divu"(%28, %29) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %26 = "riscv.sra"(%34, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.divu"(%46, %26) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i32 + "func.return"(%19) : (i32) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/VEIR_ASM/8_function_99.mlir b/benchmarks/VEIR_ASM/8_function_99.mlir new file mode 100644 index 0000000..48733eb --- /dev/null +++ b/benchmarks/VEIR_ASM/8_function_99.mlir @@ -0,0 +1,26 @@ +"builtin.module"() ({ + ^bb4(): + "func.func"() <{"function_type" = () -> i1, "sym_name" = "func0"}> ({ + ^bb6(%arg6_0 : i64, %arg6_1 : i64, %arg6_2 : i64): + %47 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %48 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %49 = "riscv.sltu"(%48, %47) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %50 = "builtin.unrealized_conversion_cast"(%49) : (!riscv.reg) -> i1 + %43 = "builtin.unrealized_conversion_cast"(%arg6_1) : (i64) -> !riscv.reg + %44 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %45 = "riscv.or"(%44, %43) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %40 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %41 = "riscv.srl"(%45, %40) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %37 = "riscv.div"(%45, %41) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %29 = "builtin.unrealized_conversion_cast"(%arg6_2) : (i64) -> !riscv.reg + %30 = "builtin.unrealized_conversion_cast"(%50) : (i1) -> !riscv.reg + %31 = "riscv.czero.eqz"(%37, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %32 = "riscv.czero.nez"(%29, %30) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %33 = "riscv.or"(%31, %32) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = "builtin.unrealized_conversion_cast"(%arg6_0) : (i64) -> !riscv.reg + %26 = "riscv.xor"(%25, %33) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = "riscv.remu"(%26, %37) : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = "builtin.unrealized_conversion_cast"(%22) : (!riscv.reg) -> i1 + "func.return"(%19) : (i1) -> () + }) : () -> () +}) : () -> () diff --git a/benchmarks/XDSL_ASM/3_function_0.mlir b/benchmarks/XDSL_ASM/3_function_0.mlir new file mode 100644 index 0000000..b14daee --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_0.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + remu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_1.mlir b/benchmarks/XDSL_ASM/3_function_1.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_10.mlir b/benchmarks/XDSL_ASM/3_function_10.mlir new file mode 100644 index 0000000..a94c29f --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_10.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + or t0, t1, t0 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_11.mlir b/benchmarks/XDSL_ASM/3_function_11.mlir new file mode 100644 index 0000000..02dd9fc --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_11.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + and t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_12.mlir b/benchmarks/XDSL_ASM/3_function_12.mlir new file mode 100644 index 0000000..07bfa13 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_12.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + srl t1, t1, t1 + divu t0, t0, t0 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_13.mlir b/benchmarks/XDSL_ASM/3_function_13.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_14.mlir b/benchmarks/XDSL_ASM/3_function_14.mlir new file mode 100644 index 0000000..d803aa9 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_14.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t0, a2 + czero.eqz t2, t1, t3 + czero.nez t3, t1, t3 + or t2, t2, t3 + xor t0, t0, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_15.mlir b/benchmarks/XDSL_ASM/3_function_15.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_16.mlir b/benchmarks/XDSL_ASM/3_function_16.mlir new file mode 100644 index 0000000..001b0a1 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_16.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + xor t1, t0, t0 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_17.mlir b/benchmarks/XDSL_ASM/3_function_17.mlir new file mode 100644 index 0000000..e1289e7 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_17.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + sext.w t2, t2 + and t1, t1, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_18.mlir b/benchmarks/XDSL_ASM/3_function_18.mlir new file mode 100644 index 0000000..a66109c --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_18.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + srl t1, t1, t0 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_19.mlir b/benchmarks/XDSL_ASM/3_function_19.mlir new file mode 100644 index 0000000..5a63a14 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_19.mlir @@ -0,0 +1,8 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_2.mlir b/benchmarks/XDSL_ASM/3_function_2.mlir new file mode 100644 index 0000000..3d058ed --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_2.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + srl t0, t0, t0 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_20.mlir b/benchmarks/XDSL_ASM/3_function_20.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_21.mlir b/benchmarks/XDSL_ASM/3_function_21.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_22.mlir b/benchmarks/XDSL_ASM/3_function_22.mlir new file mode 100644 index 0000000..2d71ce8 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_22.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + divu t0, t0, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_23.mlir b/benchmarks/XDSL_ASM/3_function_23.mlir new file mode 100644 index 0000000..f656a7d --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_23.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + or t0, t0, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_24.mlir b/benchmarks/XDSL_ASM/3_function_24.mlir new file mode 100644 index 0000000..e363004 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_24.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + sext.w t1, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_25.mlir b/benchmarks/XDSL_ASM/3_function_25.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_26.mlir b/benchmarks/XDSL_ASM/3_function_26.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_27.mlir b/benchmarks/XDSL_ASM/3_function_27.mlir new file mode 100644 index 0000000..a57b228 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_27.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + zext.w t0, t1 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_28.mlir b/benchmarks/XDSL_ASM/3_function_28.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_29.mlir b/benchmarks/XDSL_ASM/3_function_29.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_3.mlir b/benchmarks/XDSL_ASM/3_function_3.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_30.mlir b/benchmarks/XDSL_ASM/3_function_30.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_31.mlir b/benchmarks/XDSL_ASM/3_function_31.mlir new file mode 100644 index 0000000..93f3e63 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_31.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + remu t0, t0, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_32.mlir b/benchmarks/XDSL_ASM/3_function_32.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_33.mlir b/benchmarks/XDSL_ASM/3_function_33.mlir new file mode 100644 index 0000000..bf10f6f --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_33.mlir @@ -0,0 +1,8 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_34.mlir b/benchmarks/XDSL_ASM/3_function_34.mlir new file mode 100644 index 0000000..092c833 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_34.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + sra t1, t1, t1 + div t0, t1, t1 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_35.mlir b/benchmarks/XDSL_ASM/3_function_35.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_36.mlir b/benchmarks/XDSL_ASM/3_function_36.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_37.mlir b/benchmarks/XDSL_ASM/3_function_37.mlir new file mode 100644 index 0000000..f292f7d --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_37.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + rem t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_38.mlir b/benchmarks/XDSL_ASM/3_function_38.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_39.mlir b/benchmarks/XDSL_ASM/3_function_39.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_4.mlir b/benchmarks/XDSL_ASM/3_function_4.mlir new file mode 100644 index 0000000..1a21550 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_4.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + xor t1, t1, t1 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_40.mlir b/benchmarks/XDSL_ASM/3_function_40.mlir new file mode 100644 index 0000000..074e1c3 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_40.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + and t0, t1, t1 + or t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_41.mlir b/benchmarks/XDSL_ASM/3_function_41.mlir new file mode 100644 index 0000000..5a63a14 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_41.mlir @@ -0,0 +1,8 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_42.mlir b/benchmarks/XDSL_ASM/3_function_42.mlir new file mode 100644 index 0000000..46e7774 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_42.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + or t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_43.mlir b/benchmarks/XDSL_ASM/3_function_43.mlir new file mode 100644 index 0000000..e835ea3 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_43.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + div t0, t0, t2 + xor t0, t0, t1 + and t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_44.mlir b/benchmarks/XDSL_ASM/3_function_44.mlir new file mode 100644 index 0000000..30a6844 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_44.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t2, a2 + czero.eqz t0, t1, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + sra t1, t1, t0 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_45.mlir b/benchmarks/XDSL_ASM/3_function_45.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_46.mlir b/benchmarks/XDSL_ASM/3_function_46.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_47.mlir b/benchmarks/XDSL_ASM/3_function_47.mlir new file mode 100644 index 0000000..816f941 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_47.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + rem t0, t0, t2 + div t1, t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_48.mlir b/benchmarks/XDSL_ASM/3_function_48.mlir new file mode 100644 index 0000000..bf10f6f --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_48.mlir @@ -0,0 +1,8 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_49.mlir b/benchmarks/XDSL_ASM/3_function_49.mlir new file mode 100644 index 0000000..0a85636 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_49.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + div t1, t1, t1 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_5.mlir b/benchmarks/XDSL_ASM/3_function_5.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_50.mlir b/benchmarks/XDSL_ASM/3_function_50.mlir new file mode 100644 index 0000000..1705264 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_50.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + divu t1, t0, t0 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_51.mlir b/benchmarks/XDSL_ASM/3_function_51.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_52.mlir b/benchmarks/XDSL_ASM/3_function_52.mlir new file mode 100644 index 0000000..bf10f6f --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_52.mlir @@ -0,0 +1,8 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_53.mlir b/benchmarks/XDSL_ASM/3_function_53.mlir new file mode 100644 index 0000000..b99fb64 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_53.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + divu t2, t0, t0 + rem t0, t0, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_54.mlir b/benchmarks/XDSL_ASM/3_function_54.mlir new file mode 100644 index 0000000..d373e8e --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_54.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + slt t2, t1, t1 + xori t2, t2, 1 + czero.eqz t0, t1, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_55.mlir b/benchmarks/XDSL_ASM/3_function_55.mlir new file mode 100644 index 0000000..6e456f6 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_55.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + remu t0, t0, t1 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_56.mlir b/benchmarks/XDSL_ASM/3_function_56.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_57.mlir b/benchmarks/XDSL_ASM/3_function_57.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_58.mlir b/benchmarks/XDSL_ASM/3_function_58.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_59.mlir b/benchmarks/XDSL_ASM/3_function_59.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_6.mlir b/benchmarks/XDSL_ASM/3_function_6.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_60.mlir b/benchmarks/XDSL_ASM/3_function_60.mlir new file mode 100644 index 0000000..e54d7da --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_60.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + div t0, t0, t1 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_61.mlir b/benchmarks/XDSL_ASM/3_function_61.mlir new file mode 100644 index 0000000..a17d58d --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_61.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + remu t2, t0, t0 + div t0, t0, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_62.mlir b/benchmarks/XDSL_ASM/3_function_62.mlir new file mode 100644 index 0000000..a81f6e2 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_62.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + div t1, t1, t1 + srl t0, t1, t0 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_63.mlir b/benchmarks/XDSL_ASM/3_function_63.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_64.mlir b/benchmarks/XDSL_ASM/3_function_64.mlir new file mode 100644 index 0000000..2a4d35d --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_64.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + divu t0, t0, t0 + sra t1, t0, t1 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_65.mlir b/benchmarks/XDSL_ASM/3_function_65.mlir new file mode 100644 index 0000000..0417f04 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_65.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + sra t1, t0, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_66.mlir b/benchmarks/XDSL_ASM/3_function_66.mlir new file mode 100644 index 0000000..d3820a4 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_66.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + srl t0, t0, t2 + zext.w t1, t1 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_67.mlir b/benchmarks/XDSL_ASM/3_function_67.mlir new file mode 100644 index 0000000..68294d9 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_67.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + sra t0, t0, t0 + or t1, t0, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_68.mlir b/benchmarks/XDSL_ASM/3_function_68.mlir new file mode 100644 index 0000000..f6c6ef8 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_68.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + rem t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_69.mlir b/benchmarks/XDSL_ASM/3_function_69.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_7.mlir b/benchmarks/XDSL_ASM/3_function_7.mlir new file mode 100644 index 0000000..9e4ce85 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_7.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + srl t2, t2, t2 + srl t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_70.mlir b/benchmarks/XDSL_ASM/3_function_70.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_71.mlir b/benchmarks/XDSL_ASM/3_function_71.mlir new file mode 100644 index 0000000..f41692b --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_71.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sext.w t0, t0 + rem t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_72.mlir b/benchmarks/XDSL_ASM/3_function_72.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_73.mlir b/benchmarks/XDSL_ASM/3_function_73.mlir new file mode 100644 index 0000000..590208a --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_73.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + and t0, t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_74.mlir b/benchmarks/XDSL_ASM/3_function_74.mlir new file mode 100644 index 0000000..e0dd801 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_74.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + sra t1, t1, t1 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_75.mlir b/benchmarks/XDSL_ASM/3_function_75.mlir new file mode 100644 index 0000000..9070eed --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_75.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + div t0, t0, t0 + sra t1, t0, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_76.mlir b/benchmarks/XDSL_ASM/3_function_76.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_77.mlir b/benchmarks/XDSL_ASM/3_function_77.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_78.mlir b/benchmarks/XDSL_ASM/3_function_78.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_79.mlir b/benchmarks/XDSL_ASM/3_function_79.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_8.mlir b/benchmarks/XDSL_ASM/3_function_8.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_80.mlir b/benchmarks/XDSL_ASM/3_function_80.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_81.mlir b/benchmarks/XDSL_ASM/3_function_81.mlir new file mode 100644 index 0000000..2bbff6e --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_81.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + slt t2, t1, t2 + xori t2, t2, 1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_82.mlir b/benchmarks/XDSL_ASM/3_function_82.mlir new file mode 100644 index 0000000..458cda6 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_82.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + xor t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_83.mlir b/benchmarks/XDSL_ASM/3_function_83.mlir new file mode 100644 index 0000000..0e79385 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_83.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + sltu t2, t0, t2 + xori t2, t2, 1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_84.mlir b/benchmarks/XDSL_ASM/3_function_84.mlir new file mode 100644 index 0000000..811039b --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_84.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t2, a2 + czero.eqz t0, t1, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_85.mlir b/benchmarks/XDSL_ASM/3_function_85.mlir new file mode 100644 index 0000000..cc56e7e --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_85.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + and t1, t0, t0 + or t1, t1, t0 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_86.mlir b/benchmarks/XDSL_ASM/3_function_86.mlir new file mode 100644 index 0000000..f07af9c --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_86.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + zext.w t0, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_87.mlir b/benchmarks/XDSL_ASM/3_function_87.mlir new file mode 100644 index 0000000..93a4729 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_87.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sltu t2, t2, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_88.mlir b/benchmarks/XDSL_ASM/3_function_88.mlir new file mode 100644 index 0000000..dedca88 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_88.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t0, t0 + divu t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_89.mlir b/benchmarks/XDSL_ASM/3_function_89.mlir new file mode 100644 index 0000000..7cc337d --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_89.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_9.mlir b/benchmarks/XDSL_ASM/3_function_9.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_90.mlir b/benchmarks/XDSL_ASM/3_function_90.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_91.mlir b/benchmarks/XDSL_ASM/3_function_91.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_92.mlir b/benchmarks/XDSL_ASM/3_function_92.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_93.mlir b/benchmarks/XDSL_ASM/3_function_93.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_94.mlir b/benchmarks/XDSL_ASM/3_function_94.mlir new file mode 100644 index 0000000..83278d0 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_94.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + zext.w t0, t0 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_95.mlir b/benchmarks/XDSL_ASM/3_function_95.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_96.mlir b/benchmarks/XDSL_ASM/3_function_96.mlir new file mode 100644 index 0000000..d49ef2b --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_96.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + rem t0, t0, t2 + sext.w t1, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_97.mlir b/benchmarks/XDSL_ASM/3_function_97.mlir new file mode 100644 index 0000000..9993561 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_97.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + or t1, t2, t1 + czero.eqz t0, t2, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/3_function_98.mlir b/benchmarks/XDSL_ASM/3_function_98.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/3_function_99.mlir b/benchmarks/XDSL_ASM/3_function_99.mlir new file mode 100644 index 0000000..7fbbd59 --- /dev/null +++ b/benchmarks/XDSL_ASM/3_function_99.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + div t1, t1, t1 + czero.eqz t0, t1, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_0.mlir b/benchmarks/XDSL_ASM/4_function_0.mlir new file mode 100644 index 0000000..71c9c99 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_0.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + xor t0, t0, t2 + and t0, t0, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_1.mlir b/benchmarks/XDSL_ASM/4_function_1.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_10.mlir b/benchmarks/XDSL_ASM/4_function_10.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_11.mlir b/benchmarks/XDSL_ASM/4_function_11.mlir new file mode 100644 index 0000000..f336550 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_11.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t0, t0 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_12.mlir b/benchmarks/XDSL_ASM/4_function_12.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_13.mlir b/benchmarks/XDSL_ASM/4_function_13.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_14.mlir b/benchmarks/XDSL_ASM/4_function_14.mlir new file mode 100644 index 0000000..f7fd664 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_14.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + divu t0, t2, t0 + remu t2, t2, t0 + divu t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_15.mlir b/benchmarks/XDSL_ASM/4_function_15.mlir new file mode 100644 index 0000000..4e046f1 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_15.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t2, a2 + czero.eqz t0, t1, t3 + czero.nez t3, t1, t3 + or t0, t0, t3 + remu t0, t0, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_16.mlir b/benchmarks/XDSL_ASM/4_function_16.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_17.mlir b/benchmarks/XDSL_ASM/4_function_17.mlir new file mode 100644 index 0000000..ad850af --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_17.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t2, a2 + sext.w t2, t2 + divu t2, t2, t1 + czero.eqz t0, t1, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_18.mlir b/benchmarks/XDSL_ASM/4_function_18.mlir new file mode 100644 index 0000000..6664f78 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_18.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t3, a2 + xor t2, t1, t1 + xor t1, t1, t3 + or t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_19.mlir b/benchmarks/XDSL_ASM/4_function_19.mlir new file mode 100644 index 0000000..a10b3a0 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_19.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + divu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_2.mlir b/benchmarks/XDSL_ASM/4_function_2.mlir new file mode 100644 index 0000000..72a0b55 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_2.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sra t0, t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_20.mlir b/benchmarks/XDSL_ASM/4_function_20.mlir new file mode 100644 index 0000000..1cddd75 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_20.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t1, a2 + mv t2, a3 + xor t1, t1, t1 + zext.w t2, t2 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_21.mlir b/benchmarks/XDSL_ASM/4_function_21.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_22.mlir b/benchmarks/XDSL_ASM/4_function_22.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_23.mlir b/benchmarks/XDSL_ASM/4_function_23.mlir new file mode 100644 index 0000000..b2fc491 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_23.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sext.w t0, t0 + zext.w t2, t2 + or t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_24.mlir b/benchmarks/XDSL_ASM/4_function_24.mlir new file mode 100644 index 0000000..ff6fd79 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_24.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + div t1, t1, t1 + rem t2, t1, t2 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_25.mlir b/benchmarks/XDSL_ASM/4_function_25.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_26.mlir b/benchmarks/XDSL_ASM/4_function_26.mlir new file mode 100644 index 0000000..678ec4b --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_26.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t2, a1 + mv t0, a2 + czero.eqz t1, t2, t3 + czero.nez t3, t0, t3 + or t1, t1, t3 + xor t3, t0, t1 + sltiu t3, t3, 1 + czero.eqz t0, t0, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_27.mlir b/benchmarks/XDSL_ASM/4_function_27.mlir new file mode 100644 index 0000000..b736b1f --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_27.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + and t0, t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_28.mlir b/benchmarks/XDSL_ASM/4_function_28.mlir new file mode 100644 index 0000000..7f8b83d --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_28.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t0, t0 + rem t1, t1, t1 + or t1, t1, t0 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_29.mlir b/benchmarks/XDSL_ASM/4_function_29.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_3.mlir b/benchmarks/XDSL_ASM/4_function_3.mlir new file mode 100644 index 0000000..40a8196 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_3.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t3, a2 + divu t0, t2, t0 + czero.eqz t1, t0, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_30.mlir b/benchmarks/XDSL_ASM/4_function_30.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_31.mlir b/benchmarks/XDSL_ASM/4_function_31.mlir new file mode 100644 index 0000000..f65d768 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_31.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + xor t0, t0, t2 + sra t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_32.mlir b/benchmarks/XDSL_ASM/4_function_32.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_33.mlir b/benchmarks/XDSL_ASM/4_function_33.mlir new file mode 100644 index 0000000..ea46d9e --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_33.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + xor t2, t2, t0 + sltiu t2, t2, 1 + czero.eqz t0, t1, t2 + czero.nez t2, t1, t2 + or t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_34.mlir b/benchmarks/XDSL_ASM/4_function_34.mlir new file mode 100644 index 0000000..98912a5 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_34.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + divu t0, t0, t0 + sra t1, t0, t1 + or t1, t1, t0 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_35.mlir b/benchmarks/XDSL_ASM/4_function_35.mlir new file mode 100644 index 0000000..7a0bae5 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_35.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sext.w t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_36.mlir b/benchmarks/XDSL_ASM/4_function_36.mlir new file mode 100644 index 0000000..54d097a --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_36.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + or t0, t0, t1 + remu t2, t2, t2 + xor t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_37.mlir b/benchmarks/XDSL_ASM/4_function_37.mlir new file mode 100644 index 0000000..e2375ce --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_37.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + rem t0, t0, t1 + and t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_38.mlir b/benchmarks/XDSL_ASM/4_function_38.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_39.mlir b/benchmarks/XDSL_ASM/4_function_39.mlir new file mode 100644 index 0000000..662e358 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_39.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + xor t1, t2, t1 + or t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_4.mlir b/benchmarks/XDSL_ASM/4_function_4.mlir new file mode 100644 index 0000000..eedd62b --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_4.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + or t1, t1, t2 + zext.w t0, t0 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_40.mlir b/benchmarks/XDSL_ASM/4_function_40.mlir new file mode 100644 index 0000000..dc1c937 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_40.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + czero.eqz t1, t1, t2 + czero.nez t2, t0, t2 + or t1, t1, t2 + divu t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_41.mlir b/benchmarks/XDSL_ASM/4_function_41.mlir new file mode 100644 index 0000000..0c47bce --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_41.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + div t1, t1, t0 + rem t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_42.mlir b/benchmarks/XDSL_ASM/4_function_42.mlir new file mode 100644 index 0000000..717b297 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_42.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + zext.w t1, t1 + rem t2, t1, t2 + czero.eqz t0, t2, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_43.mlir b/benchmarks/XDSL_ASM/4_function_43.mlir new file mode 100644 index 0000000..60cb153 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_43.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + czero.eqz t0, t1, t2 + czero.nez t2, t1, t2 + or t0, t0, t2 + remu t0, t0, t1 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_44.mlir b/benchmarks/XDSL_ASM/4_function_44.mlir new file mode 100644 index 0000000..1c9c033 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_44.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + sext.w t0, t0 + rem t0, t0, t0 + sext.w t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_45.mlir b/benchmarks/XDSL_ASM/4_function_45.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_46.mlir b/benchmarks/XDSL_ASM/4_function_46.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_47.mlir b/benchmarks/XDSL_ASM/4_function_47.mlir new file mode 100644 index 0000000..fe5aa47 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_47.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + rem t1, t0, t0 + remu t1, t0, t1 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_48.mlir b/benchmarks/XDSL_ASM/4_function_48.mlir new file mode 100644 index 0000000..ae8f205 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_48.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_49.mlir b/benchmarks/XDSL_ASM/4_function_49.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_5.mlir b/benchmarks/XDSL_ASM/4_function_5.mlir new file mode 100644 index 0000000..8b332a7 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_5.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t2, a2 + sra t0, t0, t0 + czero.eqz t1, t2, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_50.mlir b/benchmarks/XDSL_ASM/4_function_50.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_51.mlir b/benchmarks/XDSL_ASM/4_function_51.mlir new file mode 100644 index 0000000..70ae24f --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_51.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t0, t0 + srl t1, t1, t0 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_52.mlir b/benchmarks/XDSL_ASM/4_function_52.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_53.mlir b/benchmarks/XDSL_ASM/4_function_53.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_54.mlir b/benchmarks/XDSL_ASM/4_function_54.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_55.mlir b/benchmarks/XDSL_ASM/4_function_55.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_56.mlir b/benchmarks/XDSL_ASM/4_function_56.mlir new file mode 100644 index 0000000..febfe5f --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_56.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t1, a2 + srl t2, t0, t1 + czero.eqz t1, t1, t3 + czero.nez t3, t2, t3 + or t1, t1, t3 + divu t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_57.mlir b/benchmarks/XDSL_ASM/4_function_57.mlir new file mode 100644 index 0000000..4fd9490 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_57.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + sext.w t2, t2 + or t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_58.mlir b/benchmarks/XDSL_ASM/4_function_58.mlir new file mode 100644 index 0000000..0108019 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_58.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + remu t0, t2, t0 + xor t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_59.mlir b/benchmarks/XDSL_ASM/4_function_59.mlir new file mode 100644 index 0000000..47c9304 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_59.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t0, t0 + sra t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_6.mlir b/benchmarks/XDSL_ASM/4_function_6.mlir new file mode 100644 index 0000000..5d89605 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_6.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + zext.w t0, t0 + srl t1, t1, t0 + czero.eqz t0, t1, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + or t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_60.mlir b/benchmarks/XDSL_ASM/4_function_60.mlir new file mode 100644 index 0000000..7a0bae5 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_60.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sext.w t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_61.mlir b/benchmarks/XDSL_ASM/4_function_61.mlir new file mode 100644 index 0000000..521928e --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_61.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + or t1, t1, t0 + div t1, t1, t0 + or t1, t1, t1 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_62.mlir b/benchmarks/XDSL_ASM/4_function_62.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_63.mlir b/benchmarks/XDSL_ASM/4_function_63.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_64.mlir b/benchmarks/XDSL_ASM/4_function_64.mlir new file mode 100644 index 0000000..0af0312 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_64.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t3, a2 + zext.w t0, t1 + sra t0, t0, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_65.mlir b/benchmarks/XDSL_ASM/4_function_65.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_66.mlir b/benchmarks/XDSL_ASM/4_function_66.mlir new file mode 100644 index 0000000..f292f7d --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_66.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + rem t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_67.mlir b/benchmarks/XDSL_ASM/4_function_67.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_68.mlir b/benchmarks/XDSL_ASM/4_function_68.mlir new file mode 100644 index 0000000..1aa1630 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_68.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + divu t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_69.mlir b/benchmarks/XDSL_ASM/4_function_69.mlir new file mode 100644 index 0000000..0d9bdb2 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_69.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + remu t1, t0, t0 + sra t1, t0, t1 + srl t1, t1, t0 + czero.eqz t0, t1, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_7.mlir b/benchmarks/XDSL_ASM/4_function_7.mlir new file mode 100644 index 0000000..d145332 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_7.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + xor t1, t1, t2 + slt t2, t1, t2 + divu t1, t1, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_70.mlir b/benchmarks/XDSL_ASM/4_function_70.mlir new file mode 100644 index 0000000..e4b77cc --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_70.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + divu t1, t2, t2 + sra t1, t1, t2 + zext.w t0, t0 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_71.mlir b/benchmarks/XDSL_ASM/4_function_71.mlir new file mode 100644 index 0000000..9aac2fc --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_71.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + sra t0, t1, t1 + srl t0, t0, t2 + div t1, t1, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_72.mlir b/benchmarks/XDSL_ASM/4_function_72.mlir new file mode 100644 index 0000000..bb6054d --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_72.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sra t0, t0, t2 + sra t1, t0, t1 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_73.mlir b/benchmarks/XDSL_ASM/4_function_73.mlir new file mode 100644 index 0000000..c0ef5e9 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_73.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + czero.eqz t0, t2, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_74.mlir b/benchmarks/XDSL_ASM/4_function_74.mlir new file mode 100644 index 0000000..bdd8fc6 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_74.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + sltu t3, t2, t1 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + czero.eqz t0, t0, t1 + czero.nez t1, t1, t1 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_75.mlir b/benchmarks/XDSL_ASM/4_function_75.mlir new file mode 100644 index 0000000..caebe49 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_75.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t2, a2 + czero.eqz t1, t0, t3 + czero.nez t3, t0, t3 + or t1, t1, t3 + zext.w t2, t2 + xor t2, t2, t1 + sltiu t2, t2, 1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_76.mlir b/benchmarks/XDSL_ASM/4_function_76.mlir new file mode 100644 index 0000000..22fc8c5 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_76.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t1, t1 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_77.mlir b/benchmarks/XDSL_ASM/4_function_77.mlir new file mode 100644 index 0000000..67dee9b --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_77.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + srl t0, t0, t0 + sext.w t1, t1 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_78.mlir b/benchmarks/XDSL_ASM/4_function_78.mlir new file mode 100644 index 0000000..cb0f711 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_78.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t0, t0 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_79.mlir b/benchmarks/XDSL_ASM/4_function_79.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_8.mlir b/benchmarks/XDSL_ASM/4_function_8.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_80.mlir b/benchmarks/XDSL_ASM/4_function_80.mlir new file mode 100644 index 0000000..1a64903 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_80.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sra t1, t0, t0 + remu t0, t0, t1 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_81.mlir b/benchmarks/XDSL_ASM/4_function_81.mlir new file mode 100644 index 0000000..d03b36c --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_81.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + rem t0, t0, t1 + or t1, t1, t2 + xor t0, t1, t0 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_82.mlir b/benchmarks/XDSL_ASM/4_function_82.mlir new file mode 100644 index 0000000..11f6cfa --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_82.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + or t1, t1, t1 + sext.w t0, t0 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_83.mlir b/benchmarks/XDSL_ASM/4_function_83.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_84.mlir b/benchmarks/XDSL_ASM/4_function_84.mlir new file mode 100644 index 0000000..8fa290c --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_84.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_85.mlir b/benchmarks/XDSL_ASM/4_function_85.mlir new file mode 100644 index 0000000..88338eb --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_85.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + or t0, t1, t2 + or t2, t2, t0 + srl t0, t0, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_86.mlir b/benchmarks/XDSL_ASM/4_function_86.mlir new file mode 100644 index 0000000..4406cb9 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_86.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + or t2, t0, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_87.mlir b/benchmarks/XDSL_ASM/4_function_87.mlir new file mode 100644 index 0000000..7af6dbf --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_87.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + zext.w t0, t1 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_88.mlir b/benchmarks/XDSL_ASM/4_function_88.mlir new file mode 100644 index 0000000..93ab456 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_88.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + divu t1, t1, t0 + and t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_89.mlir b/benchmarks/XDSL_ASM/4_function_89.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_9.mlir b/benchmarks/XDSL_ASM/4_function_9.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_90.mlir b/benchmarks/XDSL_ASM/4_function_90.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_91.mlir b/benchmarks/XDSL_ASM/4_function_91.mlir new file mode 100644 index 0000000..7105ae3 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_91.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + sra t2, t1, t2 + or t0, t2, t0 + sra t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_92.mlir b/benchmarks/XDSL_ASM/4_function_92.mlir new file mode 100644 index 0000000..a0dd6ed --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_92.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sext.w t0, t0 + div t0, t0, t2 + and t1, t1, t0 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_93.mlir b/benchmarks/XDSL_ASM/4_function_93.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_94.mlir b/benchmarks/XDSL_ASM/4_function_94.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_95.mlir b/benchmarks/XDSL_ASM/4_function_95.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_96.mlir b/benchmarks/XDSL_ASM/4_function_96.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/4_function_97.mlir b/benchmarks/XDSL_ASM/4_function_97.mlir new file mode 100644 index 0000000..35f717b --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_97.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + sra t0, t1, t0 + rem t0, t1, t0 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_98.mlir b/benchmarks/XDSL_ASM/4_function_98.mlir new file mode 100644 index 0000000..cd8a4e2 --- /dev/null +++ b/benchmarks/XDSL_ASM/4_function_98.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sext.w t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/4_function_99.mlir b/benchmarks/XDSL_ASM/4_function_99.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_0.mlir b/benchmarks/XDSL_ASM/5_function_0.mlir new file mode 100644 index 0000000..c16c1ba --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_0.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sext.w t0, t0 + remu t2, t0, t2 + div t0, t0, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_1.mlir b/benchmarks/XDSL_ASM/5_function_1.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_10.mlir b/benchmarks/XDSL_ASM/5_function_10.mlir new file mode 100644 index 0000000..15d80fe --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_10.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + zext.w t0, t2 + srl t1, t0, t1 + rem t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_11.mlir b/benchmarks/XDSL_ASM/5_function_11.mlir new file mode 100644 index 0000000..9d0cb05 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_11.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t0, t0 + div t1, t1, t0 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_12.mlir b/benchmarks/XDSL_ASM/5_function_12.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_13.mlir b/benchmarks/XDSL_ASM/5_function_13.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_14.mlir b/benchmarks/XDSL_ASM/5_function_14.mlir new file mode 100644 index 0000000..45192eb --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_14.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t1, a2 + sltu t2, t3, t3 + xori t2, t2, 1 + remu t0, t0, t3 + or t3, t0, t0 + remu t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_15.mlir b/benchmarks/XDSL_ASM/5_function_15.mlir new file mode 100644 index 0000000..bd86105 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_15.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t1, a2 + or t3, t3, t2 + slt t3, t3, t2 + czero.eqz t0, t1, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_16.mlir b/benchmarks/XDSL_ASM/5_function_16.mlir new file mode 100644 index 0000000..e430ac5 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_16.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + divu t1, t0, t0 + div t0, t0, t1 + divu t0, t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_17.mlir b/benchmarks/XDSL_ASM/5_function_17.mlir new file mode 100644 index 0000000..20b8be9 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_17.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + divu t2, t0, t0 + or t0, t0, t2 + zext.w t1, t1 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_18.mlir b/benchmarks/XDSL_ASM/5_function_18.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_19.mlir b/benchmarks/XDSL_ASM/5_function_19.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_2.mlir b/benchmarks/XDSL_ASM/5_function_2.mlir new file mode 100644 index 0000000..5e0ebe1 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_2.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t3, a2 + xor t3, t3, t2 + divu t1, t2, t3 + and t1, t1, t3 + sra t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_20.mlir b/benchmarks/XDSL_ASM/5_function_20.mlir new file mode 100644 index 0000000..4788856 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_20.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + or t2, t1, t2 + srl t2, t0, t2 + divu t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_21.mlir b/benchmarks/XDSL_ASM/5_function_21.mlir new file mode 100644 index 0000000..94e14d5 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_21.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + srl t2, t1, t1 + czero.eqz t0, t2, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_22.mlir b/benchmarks/XDSL_ASM/5_function_22.mlir new file mode 100644 index 0000000..5ccb8f2 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_22.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + xor t0, t0, t1 + sext.w t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_23.mlir b/benchmarks/XDSL_ASM/5_function_23.mlir new file mode 100644 index 0000000..ae8f205 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_23.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_24.mlir b/benchmarks/XDSL_ASM/5_function_24.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_25.mlir b/benchmarks/XDSL_ASM/5_function_25.mlir new file mode 100644 index 0000000..9fd9daf --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_25.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t4, a1 + mv t0, a2 + div t1, t3, t3 + czero.eqz t2, t3, t4 + czero.nez t3, t3, t4 + or t2, t2, t3 + remu t2, t1, t2 + and t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_26.mlir b/benchmarks/XDSL_ASM/5_function_26.mlir new file mode 100644 index 0000000..b60b527 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_26.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + remu t0, t1, t1 + xor t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_27.mlir b/benchmarks/XDSL_ASM/5_function_27.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_28.mlir b/benchmarks/XDSL_ASM/5_function_28.mlir new file mode 100644 index 0000000..8e3776c --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_28.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + divu t0, t0, t0 + div t0, t0, t0 + rem t1, t0, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_29.mlir b/benchmarks/XDSL_ASM/5_function_29.mlir new file mode 100644 index 0000000..387ba1b --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_29.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + and t0, t1, t0 + div t0, t0, t2 + sext.w t1, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_3.mlir b/benchmarks/XDSL_ASM/5_function_3.mlir new file mode 100644 index 0000000..4670913 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_3.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + rem t1, t0, t0 + sra t0, t1, t0 + or t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_30.mlir b/benchmarks/XDSL_ASM/5_function_30.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_31.mlir b/benchmarks/XDSL_ASM/5_function_31.mlir new file mode 100644 index 0000000..eb34f28 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_31.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t3, a2 + mv t2, a3 + srl t3, t0, t3 + slt t3, t1, t3 + xori t3, t3, 1 + zext.w t2, t2 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_32.mlir b/benchmarks/XDSL_ASM/5_function_32.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_33.mlir b/benchmarks/XDSL_ASM/5_function_33.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_34.mlir b/benchmarks/XDSL_ASM/5_function_34.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_35.mlir b/benchmarks/XDSL_ASM/5_function_35.mlir new file mode 100644 index 0000000..ceb8d1d --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_35.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + and t3, t1, t2 + sra t2, t2, t3 + divu t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_36.mlir b/benchmarks/XDSL_ASM/5_function_36.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_37.mlir b/benchmarks/XDSL_ASM/5_function_37.mlir new file mode 100644 index 0000000..fb39ada --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_37.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + zext.w t1, t1 + or t1, t1, t0 + czero.eqz t0, t2, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_38.mlir b/benchmarks/XDSL_ASM/5_function_38.mlir new file mode 100644 index 0000000..663cdda --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_38.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t2, a2 + rem t0, t0, t0 + and t2, t2, t0 + czero.eqz t1, t0, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_39.mlir b/benchmarks/XDSL_ASM/5_function_39.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_4.mlir b/benchmarks/XDSL_ASM/5_function_4.mlir new file mode 100644 index 0000000..cf0793c --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_4.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + sext.w t2, t2 + div t2, t1, t2 + divu t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_40.mlir b/benchmarks/XDSL_ASM/5_function_40.mlir new file mode 100644 index 0000000..0f89770 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_40.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + xor t0, t0, t0 + and t3, t2, t2 + remu t0, t0, t3 + sra t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_41.mlir b/benchmarks/XDSL_ASM/5_function_41.mlir new file mode 100644 index 0000000..ae7fa8b --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_41.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + zext.w t0, t0 + or t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_42.mlir b/benchmarks/XDSL_ASM/5_function_42.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_43.mlir b/benchmarks/XDSL_ASM/5_function_43.mlir new file mode 100644 index 0000000..957477d --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_43.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + srl t1, t1, t2 + rem t2, t1, t0 + remu t1, t1, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_44.mlir b/benchmarks/XDSL_ASM/5_function_44.mlir new file mode 100644 index 0000000..3be22b6 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_44.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + xor t2, t2, t1 + or t0, t0, t2 + or t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_45.mlir b/benchmarks/XDSL_ASM/5_function_45.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_46.mlir b/benchmarks/XDSL_ASM/5_function_46.mlir new file mode 100644 index 0000000..7a0bae5 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_46.mlir @@ -0,0 +1,9 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + sext.w t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_47.mlir b/benchmarks/XDSL_ASM/5_function_47.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_48.mlir b/benchmarks/XDSL_ASM/5_function_48.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_49.mlir b/benchmarks/XDSL_ASM/5_function_49.mlir new file mode 100644 index 0000000..0a70756 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_49.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + rem t2, t2, t1 + div t0, t0, t2 + xor t0, t0, t1 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_5.mlir b/benchmarks/XDSL_ASM/5_function_5.mlir new file mode 100644 index 0000000..919d327 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_5.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + remu t1, t0, t1 + divu t1, t1, t2 + divu t0, t1, t0 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_50.mlir b/benchmarks/XDSL_ASM/5_function_50.mlir new file mode 100644 index 0000000..07275e0 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_50.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + srl t1, t0, t1 + and t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_51.mlir b/benchmarks/XDSL_ASM/5_function_51.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_52.mlir b/benchmarks/XDSL_ASM/5_function_52.mlir new file mode 100644 index 0000000..e6ff44f --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_52.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + sext.w t1, t2 + srl t1, t1, t2 + div t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_53.mlir b/benchmarks/XDSL_ASM/5_function_53.mlir new file mode 100644 index 0000000..07ffe83 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_53.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + rem t2, t0, t0 + xor t2, t2, t2 + sltiu t2, t2, 1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_54.mlir b/benchmarks/XDSL_ASM/5_function_54.mlir new file mode 100644 index 0000000..56d91cc --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_54.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + xor t0, t1, t1 + div t1, t1, t2 + divu t1, t0, t1 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_55.mlir b/benchmarks/XDSL_ASM/5_function_55.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_56.mlir b/benchmarks/XDSL_ASM/5_function_56.mlir new file mode 100644 index 0000000..b72705c --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_56.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + sext.w t0, t0 + div t1, t1, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_57.mlir b/benchmarks/XDSL_ASM/5_function_57.mlir new file mode 100644 index 0000000..3d8111e --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_57.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + srl t3, t1, t2 + and t3, t3, t2 + sra t2, t2, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_58.mlir b/benchmarks/XDSL_ASM/5_function_58.mlir new file mode 100644 index 0000000..5d6bb00 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_58.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + zext.w t1, t1 + or t0, t1, t0 + xor t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_59.mlir b/benchmarks/XDSL_ASM/5_function_59.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_6.mlir b/benchmarks/XDSL_ASM/5_function_6.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_60.mlir b/benchmarks/XDSL_ASM/5_function_60.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_61.mlir b/benchmarks/XDSL_ASM/5_function_61.mlir new file mode 100644 index 0000000..0e05866 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_61.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + sext.w t0, t0 + zext.w t1, t1 + div t1, t1, t0 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_62.mlir b/benchmarks/XDSL_ASM/5_function_62.mlir new file mode 100644 index 0000000..1413815 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_62.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t3, a2 + srl t0, t2, t0 + czero.eqz t1, t0, t3 + czero.nez t3, t2, t3 + or t1, t1, t3 + or t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_63.mlir b/benchmarks/XDSL_ASM/5_function_63.mlir new file mode 100644 index 0000000..f971d45 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_63.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + xor t0, t0, t2 + zext.w t1, t1 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_64.mlir b/benchmarks/XDSL_ASM/5_function_64.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_65.mlir b/benchmarks/XDSL_ASM/5_function_65.mlir new file mode 100644 index 0000000..c707a94 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_65.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t1, t0 + rem t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_66.mlir b/benchmarks/XDSL_ASM/5_function_66.mlir new file mode 100644 index 0000000..be626c3 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_66.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t1, t1 + zext.w t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_67.mlir b/benchmarks/XDSL_ASM/5_function_67.mlir new file mode 100644 index 0000000..4c8cfbe --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_67.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t2, a2 + srl t1, t0, t0 + divu t1, t1, t3 + divu t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_68.mlir b/benchmarks/XDSL_ASM/5_function_68.mlir new file mode 100644 index 0000000..9925178 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_68.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + rem t0, t2, t0 + div t1, t1, t2 + rem t1, t1, t1 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_69.mlir b/benchmarks/XDSL_ASM/5_function_69.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_7.mlir b/benchmarks/XDSL_ASM/5_function_7.mlir new file mode 100644 index 0000000..e250438 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_7.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sra t1, t2, t1 + or t2, t1, t2 + div t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_70.mlir b/benchmarks/XDSL_ASM/5_function_70.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_71.mlir b/benchmarks/XDSL_ASM/5_function_71.mlir new file mode 100644 index 0000000..5d937b9 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_71.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + sext.w t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_72.mlir b/benchmarks/XDSL_ASM/5_function_72.mlir new file mode 100644 index 0000000..9ed7783 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_72.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + zext.w t0, t1 + rem t0, t1, t0 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_73.mlir b/benchmarks/XDSL_ASM/5_function_73.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_74.mlir b/benchmarks/XDSL_ASM/5_function_74.mlir new file mode 100644 index 0000000..0bd02be --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_74.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + sext.w t2, t2 + czero.eqz t0, t1, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + and t0, t0, t1 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_75.mlir b/benchmarks/XDSL_ASM/5_function_75.mlir new file mode 100644 index 0000000..dbf398c --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_75.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + xor t2, t0, t0 + div t2, t1, t2 + and t0, t2, t0 + div t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_76.mlir b/benchmarks/XDSL_ASM/5_function_76.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_77.mlir b/benchmarks/XDSL_ASM/5_function_77.mlir new file mode 100644 index 0000000..07f055f --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_77.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + srl t1, t1, t2 + div t1, t1, t1 + and t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_78.mlir b/benchmarks/XDSL_ASM/5_function_78.mlir new file mode 100644 index 0000000..fc0b217 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_78.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + div t0, t0, t0 + srl t0, t0, t2 + zext.w t1, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_79.mlir b/benchmarks/XDSL_ASM/5_function_79.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_8.mlir b/benchmarks/XDSL_ASM/5_function_8.mlir new file mode 100644 index 0000000..6e4a008 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_8.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + div t1, t0, t1 + xor t1, t1, t2 + divu t0, t0, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_80.mlir b/benchmarks/XDSL_ASM/5_function_80.mlir new file mode 100644 index 0000000..a11d031 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_80.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + div t1, t0, t1 + sra t1, t0, t1 + sra t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_81.mlir b/benchmarks/XDSL_ASM/5_function_81.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_82.mlir b/benchmarks/XDSL_ASM/5_function_82.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_83.mlir b/benchmarks/XDSL_ASM/5_function_83.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_84.mlir b/benchmarks/XDSL_ASM/5_function_84.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_85.mlir b/benchmarks/XDSL_ASM/5_function_85.mlir new file mode 100644 index 0000000..5e5cd1a --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_85.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + zext.w t0, t2 + zext.w t2, t2 + srl t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_86.mlir b/benchmarks/XDSL_ASM/5_function_86.mlir new file mode 100644 index 0000000..508814f --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_86.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t4, a1 + mv t2, a2 + div t1, t3, t3 + and t3, t3, t3 + czero.eqz t0, t1, t4 + czero.nez t3, t3, t4 + or t0, t0, t3 + remu t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_87.mlir b/benchmarks/XDSL_ASM/5_function_87.mlir new file mode 100644 index 0000000..d8672e0 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_87.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t0, a2 + div t2, t0, t3 + czero.eqz t0, t0, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_88.mlir b/benchmarks/XDSL_ASM/5_function_88.mlir new file mode 100644 index 0000000..48cc892 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_88.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + or t1, t0, t0 + srl t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_89.mlir b/benchmarks/XDSL_ASM/5_function_89.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_9.mlir b/benchmarks/XDSL_ASM/5_function_9.mlir new file mode 100644 index 0000000..ffb7e10 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_9.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t2, a2 + czero.eqz t0, t1, t3 + czero.nez t3, t1, t3 + or t0, t0, t3 + xor t2, t2, t1 + sra t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_90.mlir b/benchmarks/XDSL_ASM/5_function_90.mlir new file mode 100644 index 0000000..7bd6873 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_90.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + divu t2, t2, t1 + sra t0, t2, t1 + sra t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_91.mlir b/benchmarks/XDSL_ASM/5_function_91.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_92.mlir b/benchmarks/XDSL_ASM/5_function_92.mlir new file mode 100644 index 0000000..f5d7c11 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_92.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + sext.w t0, t1 + xor t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_93.mlir b/benchmarks/XDSL_ASM/5_function_93.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/5_function_94.mlir b/benchmarks/XDSL_ASM/5_function_94.mlir new file mode 100644 index 0000000..a8571fb --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_94.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + and t2, t2, t0 + sext.w t0, t2 + srl t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_95.mlir b/benchmarks/XDSL_ASM/5_function_95.mlir new file mode 100644 index 0000000..e821084 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_95.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + or t1, t0, t1 + or t1, t0, t1 + srl t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_96.mlir b/benchmarks/XDSL_ASM/5_function_96.mlir new file mode 100644 index 0000000..275fa39 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_96.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + remu t0, t0, t2 + srl t0, t0, t1 + and t0, t0, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_97.mlir b/benchmarks/XDSL_ASM/5_function_97.mlir new file mode 100644 index 0000000..9e07153 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_97.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + sext.w t2, t0 + sext.w t0, t0 + or t0, t0, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_98.mlir b/benchmarks/XDSL_ASM/5_function_98.mlir new file mode 100644 index 0000000..3a8a2b6 --- /dev/null +++ b/benchmarks/XDSL_ASM/5_function_98.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + czero.eqz t1, t2, t0 + czero.nez t0, t2, t0 + or t1, t1, t0 + srl t0, t2, t1 + div t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/5_function_99.mlir b/benchmarks/XDSL_ASM/5_function_99.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_0.mlir b/benchmarks/XDSL_ASM/6_function_0.mlir new file mode 100644 index 0000000..4484d98 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_0.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t1, a2 + czero.eqz t0, t2, t3 + czero.nez t4, t2, t3 + or t0, t0, t4 + rem t0, t2, t0 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + div t1, t0, t1 + remu t1, t1, t0 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_1.mlir b/benchmarks/XDSL_ASM/6_function_1.mlir new file mode 100644 index 0000000..5a95f19 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_1.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + divu t1, t2, t1 + zext.w t1, t1 + srl t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_10.mlir b/benchmarks/XDSL_ASM/6_function_10.mlir new file mode 100644 index 0000000..3bb2221 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_10.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t3, a2 + xor t1, t3, t2 + div t3, t2, t3 + div t2, t2, t3 + divu t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_11.mlir b/benchmarks/XDSL_ASM/6_function_11.mlir new file mode 100644 index 0000000..9aec2fd --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_11.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t3, a2 + rem t1, t2, t2 + sext.w t0, t0 + and t0, t0, t1 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_12.mlir b/benchmarks/XDSL_ASM/6_function_12.mlir new file mode 100644 index 0000000..49a9755 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_12.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + div t2, t1, t1 + and t3, t0, t0 + sra t2, t2, t3 + remu t1, t1, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_13.mlir b/benchmarks/XDSL_ASM/6_function_13.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_14.mlir b/benchmarks/XDSL_ASM/6_function_14.mlir new file mode 100644 index 0000000..5ff8d4e --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_14.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t4, a2 + rem t1, t0, t0 + czero.eqz t2, t1, t4 + czero.nez t4, t0, t4 + or t2, t2, t4 + czero.eqz t0, t0, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + rem t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_15.mlir b/benchmarks/XDSL_ASM/6_function_15.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_16.mlir b/benchmarks/XDSL_ASM/6_function_16.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_17.mlir b/benchmarks/XDSL_ASM/6_function_17.mlir new file mode 100644 index 0000000..3494ffc --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_17.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + rem t2, t1, t2 + xor t1, t2, t1 + sext.w t1, t1 + xor t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_18.mlir b/benchmarks/XDSL_ASM/6_function_18.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_19.mlir b/benchmarks/XDSL_ASM/6_function_19.mlir new file mode 100644 index 0000000..a61d158 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_19.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + remu t0, t0, t1 + div t1, t2, t2 + czero.eqz t2, t2, t1 + czero.nez t3, t1, t1 + or t2, t2, t3 + div t0, t0, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_2.mlir b/benchmarks/XDSL_ASM/6_function_2.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_20.mlir b/benchmarks/XDSL_ASM/6_function_20.mlir new file mode 100644 index 0000000..88b54e2 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_20.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + rem t0, t2, t2 + sext.w t0, t0 + and t0, t0, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_21.mlir b/benchmarks/XDSL_ASM/6_function_21.mlir new file mode 100644 index 0000000..9e9166e --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_21.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t2, a1 + mv t0, a2 + sext.w t0, t0 + czero.eqz t1, t2, t3 + czero.nez t3, t0, t3 + or t1, t1, t3 + div t0, t0, t0 + xor t1, t0, t1 + xor t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_22.mlir b/benchmarks/XDSL_ASM/6_function_22.mlir new file mode 100644 index 0000000..3bedb4a --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_22.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + or t0, t0, t2 + rem t0, t1, t0 + rem t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_23.mlir b/benchmarks/XDSL_ASM/6_function_23.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_24.mlir b/benchmarks/XDSL_ASM/6_function_24.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_25.mlir b/benchmarks/XDSL_ASM/6_function_25.mlir new file mode 100644 index 0000000..b38f0f6 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_25.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sext.w t0, t0 + rem t2, t0, t2 + remu t0, t0, t2 + sext.w t1, t1 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_26.mlir b/benchmarks/XDSL_ASM/6_function_26.mlir new file mode 100644 index 0000000..36d5d93 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_26.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t2, a2 + czero.eqz t1, t2, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + zext.w t1, t1 + zext.w t1, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_27.mlir b/benchmarks/XDSL_ASM/6_function_27.mlir new file mode 100644 index 0000000..16fb699 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_27.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t2, a2 + rem t1, t3, t0 + and t1, t1, t3 + and t0, t0, t2 + or t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_28.mlir b/benchmarks/XDSL_ASM/6_function_28.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_29.mlir b/benchmarks/XDSL_ASM/6_function_29.mlir new file mode 100644 index 0000000..0c5bf96 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_29.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + div t2, t1, t1 + srl t1, t1, t2 + zext.w t1, t1 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_3.mlir b/benchmarks/XDSL_ASM/6_function_3.mlir new file mode 100644 index 0000000..fe44630 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_3.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + slt t2, t2, t2 + xori t2, t2, 1 + rem t0, t0, t1 + sext.w t1, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_30.mlir b/benchmarks/XDSL_ASM/6_function_30.mlir new file mode 100644 index 0000000..331e09e --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_30.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + sra t1, t1, t0 + srl t1, t1, t2 + srl t1, t1, t1 + divu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_31.mlir b/benchmarks/XDSL_ASM/6_function_31.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_32.mlir b/benchmarks/XDSL_ASM/6_function_32.mlir new file mode 100644 index 0000000..f73aef0 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_32.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + zext.w t0, t0 + xor t0, t0, t2 + sext.w t1, t1 + divu t1, t1, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_33.mlir b/benchmarks/XDSL_ASM/6_function_33.mlir new file mode 100644 index 0000000..9a9c7c8 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_33.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + or t0, t0, t1 + sext.w t0, t0 + or t1, t1, t1 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_34.mlir b/benchmarks/XDSL_ASM/6_function_34.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_35.mlir b/benchmarks/XDSL_ASM/6_function_35.mlir new file mode 100644 index 0000000..1812f14 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_35.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t3, a2 + sext.w t1, t2 + rem t3, t3, t0 + divu t1, t1, t3 + zext.w t2, t2 + srl t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_36.mlir b/benchmarks/XDSL_ASM/6_function_36.mlir new file mode 100644 index 0000000..540578f --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_36.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + or t0, t0, t1 + sext.w t1, t0 + xor t1, t1, t1 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_37.mlir b/benchmarks/XDSL_ASM/6_function_37.mlir new file mode 100644 index 0000000..ccb3a0e --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_37.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + remu t0, t1, t0 + div t0, t0, t2 + remu t1, t1, t1 + div t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_38.mlir b/benchmarks/XDSL_ASM/6_function_38.mlir new file mode 100644 index 0000000..b8cf28d --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_38.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + xor t2, t2, t1 + remu t2, t1, t2 + srl t1, t1, t2 + zext.w t0, t0 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_39.mlir b/benchmarks/XDSL_ASM/6_function_39.mlir new file mode 100644 index 0000000..50989ac --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_39.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + divu t0, t0, t2 + sext.w t2, t1 + rem t0, t0, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_4.mlir b/benchmarks/XDSL_ASM/6_function_4.mlir new file mode 100644 index 0000000..6442f03 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_4.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + srl t1, t0, t1 + zext.w t1, t1 + sra t0, t1, t0 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_40.mlir b/benchmarks/XDSL_ASM/6_function_40.mlir new file mode 100644 index 0000000..52ffb8c --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_40.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + remu t0, t0, t0 + divu t2, t0, t2 + rem t2, t0, t2 + xor t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_41.mlir b/benchmarks/XDSL_ASM/6_function_41.mlir new file mode 100644 index 0000000..9e04270 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_41.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t1, a2 + czero.eqz t2, t0, t3 + czero.nez t3, t1, t3 + or t2, t2, t3 + divu t0, t0, t2 + remu t1, t1, t1 + rem t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_42.mlir b/benchmarks/XDSL_ASM/6_function_42.mlir new file mode 100644 index 0000000..fc8963d --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_42.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sra t0, t0, t2 + remu t0, t0, t1 + zext.w t1, t1 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_43.mlir b/benchmarks/XDSL_ASM/6_function_43.mlir new file mode 100644 index 0000000..55cf770 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_43.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t0, a2 + czero.eqz t2, t1, t3 + czero.nez t3, t0, t3 + or t2, t2, t3 + rem t2, t2, t1 + sra t0, t0, t1 + slt t2, t2, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_44.mlir b/benchmarks/XDSL_ASM/6_function_44.mlir new file mode 100644 index 0000000..4f0b71c --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_44.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + rem t1, t0, t1 + and t1, t1, t0 + divu t1, t1, t2 + sext.w t1, t1 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_45.mlir b/benchmarks/XDSL_ASM/6_function_45.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_46.mlir b/benchmarks/XDSL_ASM/6_function_46.mlir new file mode 100644 index 0000000..aa49ef7 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_46.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + slt t2, t3, t3 + xori t2, t2, 1 + xor t3, t3, t3 + remu t0, t3, t3 + and t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_47.mlir b/benchmarks/XDSL_ASM/6_function_47.mlir new file mode 100644 index 0000000..7be6e4b --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_47.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + divu t0, t0, t2 + xor t1, t1, t0 + divu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_48.mlir b/benchmarks/XDSL_ASM/6_function_48.mlir new file mode 100644 index 0000000..cc4fec5 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_48.mlir @@ -0,0 +1,20 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t4, a1 + mv t2, a2 + rem t1, t2, t2 + czero.eqz t0, t1, t4 + czero.nez t1, t1, t4 + or t0, t0, t1 + rem t2, t2, t0 + czero.eqz t1, t0, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + czero.eqz t0, t0, t1 + czero.nez t1, t1, t1 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_49.mlir b/benchmarks/XDSL_ASM/6_function_49.mlir new file mode 100644 index 0000000..1fbc722 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_49.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + sext.w t1, t2 + remu t1, t1, t2 + zext.w t0, t0 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_5.mlir b/benchmarks/XDSL_ASM/6_function_5.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_50.mlir b/benchmarks/XDSL_ASM/6_function_50.mlir new file mode 100644 index 0000000..fb35298 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_50.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t3, a2 + remu t1, t2, t2 + sra t1, t1, t0 + zext.w t0, t1 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_51.mlir b/benchmarks/XDSL_ASM/6_function_51.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_52.mlir b/benchmarks/XDSL_ASM/6_function_52.mlir new file mode 100644 index 0000000..484d560 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_52.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + srl t1, t1, t0 + or t1, t1, t2 + sra t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_53.mlir b/benchmarks/XDSL_ASM/6_function_53.mlir new file mode 100644 index 0000000..b96e6d4 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_53.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + zext.w t2, t2 + xor t1, t1, t1 + div t3, t2, t1 + remu t0, t0, t3 + srl t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_54.mlir b/benchmarks/XDSL_ASM/6_function_54.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_55.mlir b/benchmarks/XDSL_ASM/6_function_55.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_56.mlir b/benchmarks/XDSL_ASM/6_function_56.mlir new file mode 100644 index 0000000..925c03b --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_56.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + sra t0, t0, t2 + and t0, t0, t1 + zext.w t2, t0 + and t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_57.mlir b/benchmarks/XDSL_ASM/6_function_57.mlir new file mode 100644 index 0000000..c7da3cf --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_57.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + divu t1, t1, t2 + sra t1, t0, t1 + rem t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_58.mlir b/benchmarks/XDSL_ASM/6_function_58.mlir new file mode 100644 index 0000000..313566a --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_58.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + sltu t2, t0, t0 + zext.w t1, t1 + zext.w t1, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_59.mlir b/benchmarks/XDSL_ASM/6_function_59.mlir new file mode 100644 index 0000000..ecf038a --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_59.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + xor t0, t0, t2 + and t1, t1, t1 + divu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_6.mlir b/benchmarks/XDSL_ASM/6_function_6.mlir new file mode 100644 index 0000000..13e5224 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_6.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + remu t1, t1, t0 + div t1, t1, t2 + srl t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_60.mlir b/benchmarks/XDSL_ASM/6_function_60.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_61.mlir b/benchmarks/XDSL_ASM/6_function_61.mlir new file mode 100644 index 0000000..72ae79d --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_61.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + xor t3, t0, t0 + rem t0, t0, t3 + zext.w t1, t1 + and t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_62.mlir b/benchmarks/XDSL_ASM/6_function_62.mlir new file mode 100644 index 0000000..a129b83 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_62.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + srl t1, t1, t0 + xor t0, t2, t1 + sra t0, t1, t0 + czero.eqz t1, t1, t0 + czero.nez t2, t2, t0 + or t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_63.mlir b/benchmarks/XDSL_ASM/6_function_63.mlir new file mode 100644 index 0000000..97d0d1b --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_63.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + xor t0, t0, t0 + sext.w t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_64.mlir b/benchmarks/XDSL_ASM/6_function_64.mlir new file mode 100644 index 0000000..14bced8 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_64.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t2, a2 + or t0, t0, t3 + divu t1, t3, t3 + rem t1, t1, t3 + sra t2, t2, t2 + rem t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_65.mlir b/benchmarks/XDSL_ASM/6_function_65.mlir new file mode 100644 index 0000000..2271460 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_65.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + srl t1, t1, t1 + zext.w t0, t1 + sext.w t1, t1 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_66.mlir b/benchmarks/XDSL_ASM/6_function_66.mlir new file mode 100644 index 0000000..737da97 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_66.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t1, a2 + czero.eqz t2, t0, t3 + czero.nez t3, t1, t3 + or t2, t2, t3 + div t0, t0, t2 + zext.w t1, t1 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_67.mlir b/benchmarks/XDSL_ASM/6_function_67.mlir new file mode 100644 index 0000000..da8db99 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_67.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t3, a2 + xor t2, t1, t1 + srl t2, t1, t2 + and t2, t2, t0 + xor t2, t2, t3 + rem t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_68.mlir b/benchmarks/XDSL_ASM/6_function_68.mlir new file mode 100644 index 0000000..43a8af7 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_68.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + rem t1, t0, t0 + sra t1, t1, t0 + zext.w t0, t1 + divu t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_69.mlir b/benchmarks/XDSL_ASM/6_function_69.mlir new file mode 100644 index 0000000..a18dc44 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_69.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t0, a2 + mv t1, a3 + xor t2, t2, t2 + sltiu t2, t2, 1 + rem t0, t3, t0 + zext.w t1, t1 + div t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_7.mlir b/benchmarks/XDSL_ASM/6_function_7.mlir new file mode 100644 index 0000000..33f1bfb --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_7.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + remu t0, t0, t1 + divu t0, t0, t2 + zext.w t0, t0 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_70.mlir b/benchmarks/XDSL_ASM/6_function_70.mlir new file mode 100644 index 0000000..1e732ff --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_70.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + remu t1, t1, t1 + remu t1, t1, t1 + czero.eqz t0, t2, t3 + czero.nez t3, t2, t3 + or t0, t0, t3 + sra t1, t1, t0 + remu t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_71.mlir b/benchmarks/XDSL_ASM/6_function_71.mlir new file mode 100644 index 0000000..80ba8f0 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_71.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + rem t1, t1, t0 + divu t0, t0, t2 + sra t0, t1, t0 + srl t0, t0, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_72.mlir b/benchmarks/XDSL_ASM/6_function_72.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_73.mlir b/benchmarks/XDSL_ASM/6_function_73.mlir new file mode 100644 index 0000000..304d612 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_73.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + remu t0, t0, t1 + or t1, t0, t0 + and t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_74.mlir b/benchmarks/XDSL_ASM/6_function_74.mlir new file mode 100644 index 0000000..3f4f1f4 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_74.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + divu t2, t2, t2 + divu t0, t0, t2 + or t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_75.mlir b/benchmarks/XDSL_ASM/6_function_75.mlir new file mode 100644 index 0000000..5835773 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_75.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sra t2, t0, t2 + srl t0, t0, t2 + sext.w t0, t0 + sext.w t1, t1 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_76.mlir b/benchmarks/XDSL_ASM/6_function_76.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_77.mlir b/benchmarks/XDSL_ASM/6_function_77.mlir new file mode 100644 index 0000000..40557ba --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_77.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + srl t0, t0, t1 + sext.w t2, t2 + divu t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_78.mlir b/benchmarks/XDSL_ASM/6_function_78.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_79.mlir b/benchmarks/XDSL_ASM/6_function_79.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_8.mlir b/benchmarks/XDSL_ASM/6_function_8.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_80.mlir b/benchmarks/XDSL_ASM/6_function_80.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_81.mlir b/benchmarks/XDSL_ASM/6_function_81.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_82.mlir b/benchmarks/XDSL_ASM/6_function_82.mlir new file mode 100644 index 0000000..252892d --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_82.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + remu t3, t2, t0 + sltu t3, t3, t1 + remu t1, t2, t2 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_83.mlir b/benchmarks/XDSL_ASM/6_function_83.mlir new file mode 100644 index 0000000..9f47f4e --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_83.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t3, a2 + sext.w t2, t2 + slt t2, t0, t2 + sra t1, t0, t0 + rem t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + sra t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_84.mlir b/benchmarks/XDSL_ASM/6_function_84.mlir new file mode 100644 index 0000000..9cf7942 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_84.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t1, a2 + mv t2, a3 + srl t3, t3, t0 + div t0, t0, t3 + srl t0, t0, t1 + sext.w t2, t2 + sltu t2, t2, t0 + xori t2, t2, 1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_85.mlir b/benchmarks/XDSL_ASM/6_function_85.mlir new file mode 100644 index 0000000..aa587dd --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_85.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + sra t1, t1, t0 + and t0, t1, t0 + zext.w t1, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_86.mlir b/benchmarks/XDSL_ASM/6_function_86.mlir new file mode 100644 index 0000000..b15d1a4 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_86.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t3, a2 + or t0, t2, t2 + or t1, t1, t0 + and t1, t1, t0 + czero.eqz t0, t1, t3 + czero.nez t3, t1, t3 + or t0, t0, t3 + xor t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_87.mlir b/benchmarks/XDSL_ASM/6_function_87.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_88.mlir b/benchmarks/XDSL_ASM/6_function_88.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_89.mlir b/benchmarks/XDSL_ASM/6_function_89.mlir new file mode 100644 index 0000000..f969e99 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_89.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t1, t0 + rem t0, t0, t0 + and t0, t0, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_9.mlir b/benchmarks/XDSL_ASM/6_function_9.mlir new file mode 100644 index 0000000..d3ef793 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_9.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t4, a2 + mv t3, a3 + sext.w t3, t3 + czero.eqz t1, t3, t4 + czero.nez t3, t3, t4 + or t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_90.mlir b/benchmarks/XDSL_ASM/6_function_90.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_91.mlir b/benchmarks/XDSL_ASM/6_function_91.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_92.mlir b/benchmarks/XDSL_ASM/6_function_92.mlir new file mode 100644 index 0000000..c422ee9 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_92.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + sltu t2, t2, t1 + rem t1, t1, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_93.mlir b/benchmarks/XDSL_ASM/6_function_93.mlir new file mode 100644 index 0000000..4b928f0 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_93.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + xor t2, t0, t2 + srl t3, t0, t2 + rem t1, t1, t3 + rem t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_94.mlir b/benchmarks/XDSL_ASM/6_function_94.mlir new file mode 100644 index 0000000..a5901d9 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_94.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t2, a2 + czero.eqz t0, t0, t3 + czero.nez t1, t2, t3 + or t0, t0, t1 + czero.eqz t1, t2, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + remu t2, t1, t1 + or t1, t1, t2 + divu t1, t1, t0 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_95.mlir b/benchmarks/XDSL_ASM/6_function_95.mlir new file mode 100644 index 0000000..abc2042 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_95.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + remu t0, t0, t0 + rem t1, t1, t0 + sext.w t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_96.mlir b/benchmarks/XDSL_ASM/6_function_96.mlir new file mode 100644 index 0000000..2445892 --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_96.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + srl t0, t0, t2 + zext.w t1, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_97.mlir b/benchmarks/XDSL_ASM/6_function_97.mlir new file mode 100644 index 0000000..90dbfda --- /dev/null +++ b/benchmarks/XDSL_ASM/6_function_97.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + sext.w t1, t1 + czero.eqz t0, t1, t1 + czero.nez t2, t1, t1 + or t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/6_function_98.mlir b/benchmarks/XDSL_ASM/6_function_98.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/6_function_99.mlir b/benchmarks/XDSL_ASM/6_function_99.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_0.mlir b/benchmarks/XDSL_ASM/7_function_0.mlir new file mode 100644 index 0000000..209ef6c --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_0.mlir @@ -0,0 +1,20 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t3, a2 + czero.eqz t2, t1, t0 + czero.nez t0, t3, t0 + or t2, t2, t0 + czero.eqz t0, t3, t3 + czero.nez t4, t2, t3 + or t0, t0, t4 + or t0, t0, t2 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_1.mlir b/benchmarks/XDSL_ASM/7_function_1.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_10.mlir b/benchmarks/XDSL_ASM/7_function_10.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_11.mlir b/benchmarks/XDSL_ASM/7_function_11.mlir new file mode 100644 index 0000000..6adb141 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_11.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + zext.w t0, t0 + xor t1, t1, t0 + srl t2, t2, t0 + zext.w t2, t2 + div t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_12.mlir b/benchmarks/XDSL_ASM/7_function_12.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_13.mlir b/benchmarks/XDSL_ASM/7_function_13.mlir new file mode 100644 index 0000000..d347578 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_13.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + and t0, t3, t1 + divu t0, t0, t3 + sltu t2, t2, t0 + xori t2, t2, 1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_14.mlir b/benchmarks/XDSL_ASM/7_function_14.mlir new file mode 100644 index 0000000..5912a9b --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_14.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t3, a2 + sext.w t2, t2 + and t1, t2, t1 + zext.w t1, t1 + czero.eqz t0, t2, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_15.mlir b/benchmarks/XDSL_ASM/7_function_15.mlir new file mode 100644 index 0000000..5b33de6 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_15.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t0, a2 + sext.w t3, t3 + sltu t2, t3, t1 + xori t2, t2, 1 + rem t3, t0, t3 + div t0, t0, t3 + srl t1, t1, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_16.mlir b/benchmarks/XDSL_ASM/7_function_16.mlir new file mode 100644 index 0000000..8c124aa --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_16.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t4, a0 + mv t3, a1 + mv t2, a2 + mv t1, a3 + czero.eqz t0, t3, t4 + czero.nez t3, t3, t4 + or t0, t0, t3 + div t0, t0, t2 + zext.w t1, t1 + sra t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_17.mlir b/benchmarks/XDSL_ASM/7_function_17.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_18.mlir b/benchmarks/XDSL_ASM/7_function_18.mlir new file mode 100644 index 0000000..3886685 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_18.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + rem t3, t1, t1 + divu t2, t3, t3 + div t2, t1, t2 + or t2, t2, t3 + sra t1, t1, t2 + remu t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_19.mlir b/benchmarks/XDSL_ASM/7_function_19.mlir new file mode 100644 index 0000000..e0da2ba --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_19.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + and t0, t0, t1 + srl t2, t2, t0 + remu t2, t2, t1 + xor t2, t2, t2 + xor t0, t0, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_2.mlir b/benchmarks/XDSL_ASM/7_function_2.mlir new file mode 100644 index 0000000..01700b6 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_2.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t3, a2 + remu t1, t0, t2 + sra t0, t0, t3 + remu t0, t0, t2 + div t2, t0, t2 + srl t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_20.mlir b/benchmarks/XDSL_ASM/7_function_20.mlir new file mode 100644 index 0000000..2596693 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_20.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t3, a2 + remu t1, t0, t0 + slt t4, t1, t2 + xori t4, t4, 1 + remu t3, t3, t2 + rem t3, t1, t3 + czero.eqz t2, t0, t4 + czero.nez t3, t3, t4 + or t2, t2, t3 + div t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_21.mlir b/benchmarks/XDSL_ASM/7_function_21.mlir new file mode 100644 index 0000000..aad9245 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_21.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + sext.w t0, t0 + divu t2, t1, t2 + sltu t3, t2, t1 + xori t3, t3, 1 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + and t0, t1, t0 + xor t1, t0, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_22.mlir b/benchmarks/XDSL_ASM/7_function_22.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_23.mlir b/benchmarks/XDSL_ASM/7_function_23.mlir new file mode 100644 index 0000000..b69fcf9 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_23.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + sra t0, t1, t1 + and t2, t2, t3 + div t1, t1, t2 + divu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_24.mlir b/benchmarks/XDSL_ASM/7_function_24.mlir new file mode 100644 index 0000000..6e99200 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_24.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + rem t2, t0, t0 + srl t1, t0, t2 + or t1, t1, t0 + sext.w t0, t1 + rem t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_25.mlir b/benchmarks/XDSL_ASM/7_function_25.mlir new file mode 100644 index 0000000..5b0ccfe --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_25.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + mv t0, a3 + divu t1, t1, t3 + czero.eqz t2, t2, t1 + czero.nez t3, t1, t1 + or t2, t2, t3 + zext.w t0, t0 + remu t1, t2, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_26.mlir b/benchmarks/XDSL_ASM/7_function_26.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_27.mlir b/benchmarks/XDSL_ASM/7_function_27.mlir new file mode 100644 index 0000000..ccd4555 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_27.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t5, a1 + mv t4, a2 + zext.w t1, t0 + xor t2, t1, t1 + czero.eqz t3, t2, t5 + czero.nez t4, t4, t5 + or t3, t3, t4 + slt t2, t2, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_28.mlir b/benchmarks/XDSL_ASM/7_function_28.mlir new file mode 100644 index 0000000..5eb3ab5 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_28.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + zext.w t2, t2 + zext.w t2, t2 + rem t2, t2, t2 + rem t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_29.mlir b/benchmarks/XDSL_ASM/7_function_29.mlir new file mode 100644 index 0000000..8bd69a0 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_29.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t4, a1 + mv t1, a2 + mv t3, a3 + czero.eqz t2, t4, t0 + czero.nez t4, t4, t0 + or t2, t2, t4 + sext.w t3, t3 + xor t3, t3, t0 + sra t1, t1, t3 + and t1, t1, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_3.mlir b/benchmarks/XDSL_ASM/7_function_3.mlir new file mode 100644 index 0000000..e66fe87 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_3.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + div t2, t2, t2 + or t0, t0, t2 + zext.w t2, t1 + rem t0, t0, t2 + sext.w t1, t1 + sra t1, t1, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_30.mlir b/benchmarks/XDSL_ASM/7_function_30.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_31.mlir b/benchmarks/XDSL_ASM/7_function_31.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_32.mlir b/benchmarks/XDSL_ASM/7_function_32.mlir new file mode 100644 index 0000000..4255fb1 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_32.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + sext.w t3, t1 + sra t1, t1, t3 + zext.w t1, t1 + xor t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_33.mlir b/benchmarks/XDSL_ASM/7_function_33.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_34.mlir b/benchmarks/XDSL_ASM/7_function_34.mlir new file mode 100644 index 0000000..0a14db4 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_34.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t2, a2 + zext.w t1, t2 + xor t2, t2, t1 + czero.eqz t0, t0, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + srl t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_35.mlir b/benchmarks/XDSL_ASM/7_function_35.mlir new file mode 100644 index 0000000..6503ed9 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_35.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + zext.w t0, t1 + zext.w t3, t1 + sra t0, t0, t3 + srl t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_36.mlir b/benchmarks/XDSL_ASM/7_function_36.mlir new file mode 100644 index 0000000..3405b8a --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_36.mlir @@ -0,0 +1,21 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t4, a1 + mv t2, a2 + sra t3, t4, t2 + czero.eqz t0, t3, t1 + czero.nez t2, t2, t1 + or t0, t0, t2 + sltu t4, t3, t4 + xori t4, t4, 1 + or t2, t0, t0 + czero.eqz t1, t2, t4 + czero.nez t3, t3, t4 + or t1, t1, t3 + divu t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_37.mlir b/benchmarks/XDSL_ASM/7_function_37.mlir new file mode 100644 index 0000000..df1282d --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_37.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t0, a2 + or t2, t1, t1 + czero.eqz t0, t0, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + srl t2, t0, t1 + rem t2, t1, t2 + and t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_38.mlir b/benchmarks/XDSL_ASM/7_function_38.mlir new file mode 100644 index 0000000..de34015 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_38.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t3, a2 + divu t1, t2, t0 + and t2, t1, t2 + remu t4, t2, t1 + xor t3, t3, t4 + sltiu t3, t3, 1 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_39.mlir b/benchmarks/XDSL_ASM/7_function_39.mlir new file mode 100644 index 0000000..538ed08 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_39.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + remu t0, t0, t1 + sext.w t0, t0 + sext.w t1, t0 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_4.mlir b/benchmarks/XDSL_ASM/7_function_4.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_40.mlir b/benchmarks/XDSL_ASM/7_function_40.mlir new file mode 100644 index 0000000..a953c28 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_40.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + zext.w t0, t0 + srl t0, t0, t1 + sext.w t2, t2 + rem t1, t2, t1 + srl t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_41.mlir b/benchmarks/XDSL_ASM/7_function_41.mlir new file mode 100644 index 0000000..bca42d5 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_41.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + xor t2, t0, t2 + and t0, t2, t0 + srl t0, t1, t0 + srl t0, t2, t0 + and t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_42.mlir b/benchmarks/XDSL_ASM/7_function_42.mlir new file mode 100644 index 0000000..1dc5494 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_42.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t3, a2 + xor t0, t1, t1 + sra t3, t2, t3 + sra t0, t0, t3 + xor t1, t1, t2 + sra t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_43.mlir b/benchmarks/XDSL_ASM/7_function_43.mlir new file mode 100644 index 0000000..42b0ac6 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_43.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t2, a2 + sra t1, t2, t0 + czero.eqz t0, t0, t3 + czero.nez t4, t1, t3 + or t0, t0, t4 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + sext.w t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_44.mlir b/benchmarks/XDSL_ASM/7_function_44.mlir new file mode 100644 index 0000000..e7b61d0 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_44.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t3, a2 + remu t0, t2, t2 + remu t1, t0, t1 + czero.eqz t2, t2, t3 + czero.nez t0, t0, t3 + or t2, t2, t0 + xor t0, t1, t2 + div t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_45.mlir b/benchmarks/XDSL_ASM/7_function_45.mlir new file mode 100644 index 0000000..3c2c1de --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_45.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + rem t0, t0, t2 + xor t0, t0, t2 + sext.w t0, t0 + and t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_46.mlir b/benchmarks/XDSL_ASM/7_function_46.mlir new file mode 100644 index 0000000..34cc57e --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_46.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t4, a2 + slt t2, t3, t3 + xori t2, t2, 1 + sra t0, t3, t3 + remu t3, t3, t4 + sext.w t3, t3 + sra t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_47.mlir b/benchmarks/XDSL_ASM/7_function_47.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_48.mlir b/benchmarks/XDSL_ASM/7_function_48.mlir new file mode 100644 index 0000000..ba08315 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_48.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + and t1, t2, t1 + divu t1, t1, t2 + rem t0, t0, t1 + xor t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_49.mlir b/benchmarks/XDSL_ASM/7_function_49.mlir new file mode 100644 index 0000000..c8ca466 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_49.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + divu t2, t0, t2 + div t2, t0, t2 + sra t0, t0, t2 + remu t1, t0, t1 + srl t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_5.mlir b/benchmarks/XDSL_ASM/7_function_5.mlir new file mode 100644 index 0000000..e06c824 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_5.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + and t1, t1, t1 + sext.w t0, t1 + and t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_50.mlir b/benchmarks/XDSL_ASM/7_function_50.mlir new file mode 100644 index 0000000..24f8589 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_50.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t3, a2 + sra t1, t3, t0 + srl t1, t1, t3 + divu t1, t2, t1 + div t0, t0, t1 + divu t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_51.mlir b/benchmarks/XDSL_ASM/7_function_51.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_52.mlir b/benchmarks/XDSL_ASM/7_function_52.mlir new file mode 100644 index 0000000..8df3b81 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_52.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + zext.w t0, t1 + rem t2, t0, t2 + or t2, t2, t3 + sext.w t1, t1 + and t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_53.mlir b/benchmarks/XDSL_ASM/7_function_53.mlir new file mode 100644 index 0000000..33d6eb5 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_53.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + sext.w t1, t1 + rem t2, t2, t2 + remu t2, t2, t0 + divu t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_54.mlir b/benchmarks/XDSL_ASM/7_function_54.mlir new file mode 100644 index 0000000..238f9dc --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_54.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + zext.w t2, t2 + srl t1, t1, t2 + sext.w t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_55.mlir b/benchmarks/XDSL_ASM/7_function_55.mlir new file mode 100644 index 0000000..3212ad7 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_55.mlir @@ -0,0 +1,11 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + rem t0, t0, t0 + sext.w t0, t0 + sext.w t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_56.mlir b/benchmarks/XDSL_ASM/7_function_56.mlir new file mode 100644 index 0000000..bd37d8a --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_56.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + zext.w t1, t1 + and t1, t1, t1 + sext.w t0, t0 + sext.w t0, t0 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_57.mlir b/benchmarks/XDSL_ASM/7_function_57.mlir new file mode 100644 index 0000000..02387fa --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_57.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + sra t2, t2, t1 + rem t1, t1, t2 + or t0, t0, t0 + and t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_58.mlir b/benchmarks/XDSL_ASM/7_function_58.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_59.mlir b/benchmarks/XDSL_ASM/7_function_59.mlir new file mode 100644 index 0000000..47ef20c --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_59.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t2, a2 + czero.eqz t1, t0, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + srl t0, t0, t1 + sra t0, t1, t0 + and t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_6.mlir b/benchmarks/XDSL_ASM/7_function_6.mlir new file mode 100644 index 0000000..0f326c2 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_6.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + srl t3, t0, t0 + or t0, t0, t3 + xor t1, t1, t2 + divu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_60.mlir b/benchmarks/XDSL_ASM/7_function_60.mlir new file mode 100644 index 0000000..9971912 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_60.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + div t2, t2, t2 + or t1, t1, t2 + or t1, t0, t1 + div t1, t0, t1 + xor t1, t0, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_61.mlir b/benchmarks/XDSL_ASM/7_function_61.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_62.mlir b/benchmarks/XDSL_ASM/7_function_62.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_63.mlir b/benchmarks/XDSL_ASM/7_function_63.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_64.mlir b/benchmarks/XDSL_ASM/7_function_64.mlir new file mode 100644 index 0000000..3b5e0d1 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_64.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + zext.w t2, t2 + sra t0, t0, t2 + xor t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_65.mlir b/benchmarks/XDSL_ASM/7_function_65.mlir new file mode 100644 index 0000000..fc32d9a --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_65.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sext.w t0, t0 + and t0, t2, t0 + and t2, t2, t0 + div t2, t0, t2 + sra t0, t0, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_66.mlir b/benchmarks/XDSL_ASM/7_function_66.mlir new file mode 100644 index 0000000..3d26bb6 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_66.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t1, a2 + sext.w t3, t3 + remu t2, t3, t0 + sltu t2, t2, t3 + xori t2, t2, 1 + divu t1, t0, t1 + remu t1, t1, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_67.mlir b/benchmarks/XDSL_ASM/7_function_67.mlir new file mode 100644 index 0000000..02037a0 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_67.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + divu t2, t2, t1 + xor t1, t2, t2 + divu t1, t2, t1 + remu t2, t1, t2 + divu t0, t0, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_68.mlir b/benchmarks/XDSL_ASM/7_function_68.mlir new file mode 100644 index 0000000..3c61f57 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_68.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t1, a2 + slt t4, t3, t3 + czero.eqz t2, t0, t4 + czero.nez t4, t3, t4 + or t2, t2, t4 + rem t2, t2, t3 + and t2, t2, t2 + xor t1, t1, t0 + czero.eqz t0, t2, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_69.mlir b/benchmarks/XDSL_ASM/7_function_69.mlir new file mode 100644 index 0000000..ea012f8 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_69.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t2, a2 + czero.eqz t1, t0, t3 + czero.nez t3, t2, t3 + or t1, t1, t3 + and t2, t2, t0 + sra t1, t1, t2 + sext.w t2, t1 + or t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_7.mlir b/benchmarks/XDSL_ASM/7_function_7.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_70.mlir b/benchmarks/XDSL_ASM/7_function_70.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_71.mlir b/benchmarks/XDSL_ASM/7_function_71.mlir new file mode 100644 index 0000000..dea6a7e --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_71.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + remu t3, t0, t0 + rem t4, t1, t2 + divu t0, t0, t4 + or t0, t2, t0 + xor t0, t0, t3 + xor t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_72.mlir b/benchmarks/XDSL_ASM/7_function_72.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_73.mlir b/benchmarks/XDSL_ASM/7_function_73.mlir new file mode 100644 index 0000000..ba80ab9 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_73.mlir @@ -0,0 +1,12 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + zext.w t1, t1 + and t0, t0, t1 + sext.w t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_74.mlir b/benchmarks/XDSL_ASM/7_function_74.mlir new file mode 100644 index 0000000..b45a9fa --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_74.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + zext.w t1, t1 + srl t1, t0, t1 + divu t3, t1, t2 + xor t1, t1, t3 + xor t1, t1, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_75.mlir b/benchmarks/XDSL_ASM/7_function_75.mlir new file mode 100644 index 0000000..3b82a03 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_75.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + remu t2, t1, t2 + divu t3, t1, t1 + rem t1, t2, t1 + xor t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_76.mlir b/benchmarks/XDSL_ASM/7_function_76.mlir new file mode 100644 index 0000000..276e279 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_76.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t5, a2 + mv t3, a3 + divu t0, t1, t2 + divu t4, t0, t0 + divu t4, t4, t5 + or t1, t1, t4 + czero.eqz t0, t0, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_77.mlir b/benchmarks/XDSL_ASM/7_function_77.mlir new file mode 100644 index 0000000..3a963af --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_77.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t4, a1 + mv t0, a2 + mv t3, a3 + div t2, t1, t1 + sra t1, t2, t1 + xor t4, t4, t1 + and t0, t0, t4 + czero.eqz t1, t1, t3 + czero.nez t3, t0, t3 + or t1, t1, t3 + divu t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_78.mlir b/benchmarks/XDSL_ASM/7_function_78.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_79.mlir b/benchmarks/XDSL_ASM/7_function_79.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_8.mlir b/benchmarks/XDSL_ASM/7_function_8.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_80.mlir b/benchmarks/XDSL_ASM/7_function_80.mlir new file mode 100644 index 0000000..2cec96c --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_80.mlir @@ -0,0 +1,21 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t1, a2 + xor t5, t3, t2 + sltiu t5, t5, 1 + divu t4, t1, t3 + czero.eqz t0, t1, t5 + czero.nez t4, t4, t5 + or t0, t0, t4 + or t1, t1, t2 + sltu t3, t3, t1 + czero.eqz t1, t0, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_81.mlir b/benchmarks/XDSL_ASM/7_function_81.mlir new file mode 100644 index 0000000..2d660b7 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_81.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t3, a2 + zext.w t1, t2 + srl t0, t1, t0 + srl t1, t1, t0 + zext.w t2, t2 + xor t2, t2, t3 + rem t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_82.mlir b/benchmarks/XDSL_ASM/7_function_82.mlir new file mode 100644 index 0000000..772e5bb --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_82.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + sext.w t2, t2 + sext.w t2, t2 + sra t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_83.mlir b/benchmarks/XDSL_ASM/7_function_83.mlir new file mode 100644 index 0000000..86e4ea4 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_83.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + remu t0, t0, t2 + sext.w t0, t0 + sext.w t0, t0 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_84.mlir b/benchmarks/XDSL_ASM/7_function_84.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_85.mlir b/benchmarks/XDSL_ASM/7_function_85.mlir new file mode 100644 index 0000000..ea953c8 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_85.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t1, a2 + czero.eqz t2, t0, t3 + czero.nez t0, t0, t3 + or t2, t2, t0 + xor t0, t1, t2 + xor t0, t0, t0 + and t0, t0, t2 + xor t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_86.mlir b/benchmarks/XDSL_ASM/7_function_86.mlir new file mode 100644 index 0000000..5d98d8f --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_86.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + sext.w t1, t1 + or t1, t1, t1 + sext.w t1, t1 + rem t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_87.mlir b/benchmarks/XDSL_ASM/7_function_87.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_88.mlir b/benchmarks/XDSL_ASM/7_function_88.mlir new file mode 100644 index 0000000..a352aa3 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_88.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t2, a2 + sext.w t2, t2 + czero.eqz t1, t0, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + rem t0, t0, t1 + or t0, t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_89.mlir b/benchmarks/XDSL_ASM/7_function_89.mlir new file mode 100644 index 0000000..03f9f1a --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_89.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + and t0, t2, t0 + sext.w t1, t1 + divu t1, t1, t2 + divu t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_9.mlir b/benchmarks/XDSL_ASM/7_function_9.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_90.mlir b/benchmarks/XDSL_ASM/7_function_90.mlir new file mode 100644 index 0000000..a8605c7 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_90.mlir @@ -0,0 +1,10 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + zext.w t0, t0 + zext.w t0, t0 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_91.mlir b/benchmarks/XDSL_ASM/7_function_91.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_92.mlir b/benchmarks/XDSL_ASM/7_function_92.mlir new file mode 100644 index 0000000..c4c41ab --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_92.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t0, a2 + sext.w t1, t2 + and t2, t2, t3 + xor t2, t2, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_93.mlir b/benchmarks/XDSL_ASM/7_function_93.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_94.mlir b/benchmarks/XDSL_ASM/7_function_94.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/7_function_95.mlir b/benchmarks/XDSL_ASM/7_function_95.mlir new file mode 100644 index 0000000..fd9f736 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_95.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + div t3, t0, t0 + xor t0, t0, t3 + sra t1, t1, t2 + divu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_96.mlir b/benchmarks/XDSL_ASM/7_function_96.mlir new file mode 100644 index 0000000..389c929 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_96.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + sra t2, t1, t1 + sra t3, t2, t1 + sra t3, t1, t3 + div t1, t1, t3 + xor t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_97.mlir b/benchmarks/XDSL_ASM/7_function_97.mlir new file mode 100644 index 0000000..4e3090c --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_97.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + remu t2, t0, t0 + zext.w t1, t1 + srl t1, t2, t1 + sext.w t1, t1 + xor t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_98.mlir b/benchmarks/XDSL_ASM/7_function_98.mlir new file mode 100644 index 0000000..eba8601 --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_98.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t5, a1 + mv t3, a2 + or t0, t2, t2 + divu t1, t2, t0 + slt t4, t0, t1 + sra t0, t0, t5 + czero.eqz t0, t0, t4 + czero.nez t3, t3, t4 + or t0, t0, t3 + and t0, t0, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/7_function_99.mlir b/benchmarks/XDSL_ASM/7_function_99.mlir new file mode 100644 index 0000000..ef7b06b --- /dev/null +++ b/benchmarks/XDSL_ASM/7_function_99.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + div t1, t1, t0 + and t2, t2, t0 + div t2, t1, t2 + sext.w t1, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_0.mlir b/benchmarks/XDSL_ASM/8_function_0.mlir new file mode 100644 index 0000000..c27cfe8 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_0.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + divu t3, t1, t1 + sext.w t3, t3 + sra t1, t1, t3 + or t0, t2, t0 + divu t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_1.mlir b/benchmarks/XDSL_ASM/8_function_1.mlir new file mode 100644 index 0000000..7c2c805 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_1.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t3, a2 + zext.w t2, t2 + zext.w t0, t2 + rem t0, t2, t0 + sext.w t1, t1 + czero.eqz t2, t2, t3 + czero.nez t3, t1, t3 + or t2, t2, t3 + rem t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_10.mlir b/benchmarks/XDSL_ASM/8_function_10.mlir new file mode 100644 index 0000000..62a86ab --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_10.mlir @@ -0,0 +1,20 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + mv t1, a2 + divu t0, t2, t0 + or t2, t0, t2 + xor t2, t1, t2 + srl t3, t0, t1 + slt t3, t3, t2 + czero.eqz t0, t0, t3 + czero.nez t3, t2, t3 + or t0, t0, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_11.mlir b/benchmarks/XDSL_ASM/8_function_11.mlir new file mode 100644 index 0000000..b1d639b --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_11.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t3, a2 + mv t0, a3 + srl t1, t2, t1 + sra t3, t2, t3 + remu t2, t2, t3 + remu t2, t2, t1 + div t1, t1, t2 + zext.w t0, t0 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_12.mlir b/benchmarks/XDSL_ASM/8_function_12.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_13.mlir b/benchmarks/XDSL_ASM/8_function_13.mlir new file mode 100644 index 0000000..bcb8d2a --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_13.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t0, a1 + remu t3, t2, t2 + sext.w t1, t3 + or t0, t0, t3 + and t0, t0, t2 + xor t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_14.mlir b/benchmarks/XDSL_ASM/8_function_14.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_15.mlir b/benchmarks/XDSL_ASM/8_function_15.mlir new file mode 100644 index 0000000..be28e8b --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_15.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t1, a2 + mv t0, a3 + sra t4, t2, t3 + remu t3, t4, t3 + sltu t3, t2, t3 + div t2, t2, t4 + czero.eqz t1, t1, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + zext.w t0, t0 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_16.mlir b/benchmarks/XDSL_ASM/8_function_16.mlir new file mode 100644 index 0000000..361e641 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_16.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + sext.w t3, t3 + or t0, t3, t1 + rem t3, t3, t2 + zext.w t3, t3 + remu t1, t1, t3 + remu t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_17.mlir b/benchmarks/XDSL_ASM/8_function_17.mlir new file mode 100644 index 0000000..35f123e --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_17.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t4, a0 + mv t2, a1 + mv t1, a2 + zext.w t4, t4 + remu t0, t4, t2 + remu t3, t2, t4 + div t1, t1, t4 + and t1, t1, t3 + xor t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_18.mlir b/benchmarks/XDSL_ASM/8_function_18.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_19.mlir b/benchmarks/XDSL_ASM/8_function_19.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_2.mlir b/benchmarks/XDSL_ASM/8_function_2.mlir new file mode 100644 index 0000000..a9afda2 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_2.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t4, a1 + mv t1, a2 + sext.w t2, t4 + and t0, t2, t2 + sext.w t4, t4 + remu t4, t1, t4 + srl t0, t0, t4 + and t0, t0, t3 + remu t1, t1, t2 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_20.mlir b/benchmarks/XDSL_ASM/8_function_20.mlir new file mode 100644 index 0000000..e952862 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_20.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t3, a2 + sra t1, t0, t1 + rem t3, t1, t3 + zext.w t2, t3 + srl t2, t2, t3 + divu t1, t1, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_21.mlir b/benchmarks/XDSL_ASM/8_function_21.mlir new file mode 100644 index 0000000..048c898 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_21.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + mv t0, a2 + zext.w t3, t2 + rem t1, t1, t3 + divu t0, t0, t2 + and t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_22.mlir b/benchmarks/XDSL_ASM/8_function_22.mlir new file mode 100644 index 0000000..70d312a --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_22.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t1, a2 + srl t0, t2, t2 + sra t0, t0, t1 + remu t0, t3, t0 + srl t1, t1, t3 + czero.eqz t1, t1, t2 + czero.nez t3, t2, t2 + or t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_23.mlir b/benchmarks/XDSL_ASM/8_function_23.mlir new file mode 100644 index 0000000..63de775 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_23.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + zext.w t2, t0 + divu t0, t2, t0 + div t1, t1, t2 + zext.w t1, t1 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_24.mlir b/benchmarks/XDSL_ASM/8_function_24.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_25.mlir b/benchmarks/XDSL_ASM/8_function_25.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_26.mlir b/benchmarks/XDSL_ASM/8_function_26.mlir new file mode 100644 index 0000000..ac65bd1 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_26.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t1, a2 + and t0, t2, t2 + sext.w t3, t3 + divu t2, t2, t3 + and t1, t1, t2 + sra t1, t1, t2 + divu t2, t2, t1 + sra t0, t0, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_27.mlir b/benchmarks/XDSL_ASM/8_function_27.mlir new file mode 100644 index 0000000..9a36160 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_27.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t2, a2 + czero.eqz t1, t0, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + sra t1, t1, t0 + and t1, t1, t0 + srl t2, t0, t0 + sra t1, t1, t2 + sext.w t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_28.mlir b/benchmarks/XDSL_ASM/8_function_28.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_29.mlir b/benchmarks/XDSL_ASM/8_function_29.mlir new file mode 100644 index 0000000..e0b2b86 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_29.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t5, a2 + mv t4, a3 + and t2, t3, t1 + rem t0, t5, t1 + xor t0, t0, t2 + xor t3, t3, t5 + czero.eqz t2, t2, t4 + czero.nez t3, t3, t4 + or t2, t2, t3 + rem t0, t0, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_3.mlir b/benchmarks/XDSL_ASM/8_function_3.mlir new file mode 100644 index 0000000..a56501a --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_3.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + zext.w t1, t0 + sra t1, t1, t2 + sext.w t1, t1 + zext.w t1, t1 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_30.mlir b/benchmarks/XDSL_ASM/8_function_30.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_31.mlir b/benchmarks/XDSL_ASM/8_function_31.mlir new file mode 100644 index 0000000..7eaf622 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_31.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t0, a2 + rem t3, t3, t2 + divu t2, t2, t3 + sext.w t1, t2 + srl t2, t2, t0 + sltu t2, t1, t2 + rem t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_32.mlir b/benchmarks/XDSL_ASM/8_function_32.mlir new file mode 100644 index 0000000..6a3e18f --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_32.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t1, a2 + czero.eqz t0, t1, t3 + czero.nez t3, t1, t3 + or t0, t0, t3 + and t3, t0, t1 + srl t3, t3, t0 + srl t0, t0, t3 + sext.w t0, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_33.mlir b/benchmarks/XDSL_ASM/8_function_33.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_34.mlir b/benchmarks/XDSL_ASM/8_function_34.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_35.mlir b/benchmarks/XDSL_ASM/8_function_35.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_36.mlir b/benchmarks/XDSL_ASM/8_function_36.mlir new file mode 100644 index 0000000..65000ac --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_36.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + mv t3, a3 + remu t0, t1, t0 + zext.w t3, t3 + remu t3, t3, t3 + xor t3, t3, t1 + rem t3, t3, t0 + div t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_37.mlir b/benchmarks/XDSL_ASM/8_function_37.mlir new file mode 100644 index 0000000..5ddd0a4 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_37.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t3, a2 + xor t0, t1, t2 + rem t2, t0, t2 + divu t1, t1, t2 + or t1, t1, t3 + xor t1, t1, t2 + remu t0, t0, t1 + remu t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_38.mlir b/benchmarks/XDSL_ASM/8_function_38.mlir new file mode 100644 index 0000000..8a84f66 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_38.mlir @@ -0,0 +1,21 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t5, a2 + mv t1, a3 + sltu t2, t3, t0 + xori t2, t2, 1 + or t4, t3, t0 + divu t3, t3, t5 + xor t3, t3, t4 + xor t0, t3, t0 + and t0, t0, t3 + zext.w t1, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_39.mlir b/benchmarks/XDSL_ASM/8_function_39.mlir new file mode 100644 index 0000000..043408c --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_39.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t0, a2 + or t1, t2, t2 + sra t1, t2, t1 + czero.eqz t0, t0, t3 + czero.nez t3, t2, t3 + or t0, t0, t3 + and t2, t2, t0 + or t0, t0, t2 + divu t0, t0, t0 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_4.mlir b/benchmarks/XDSL_ASM/8_function_4.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_40.mlir b/benchmarks/XDSL_ASM/8_function_40.mlir new file mode 100644 index 0000000..67268ab --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_40.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t2, a1 + mv t1, a2 + zext.w t4, t3 + sltu t4, t4, t4 + xori t4, t4, 1 + czero.eqz t0, t3, t4 + czero.nez t4, t3, t4 + or t0, t0, t4 + or t0, t0, t3 + sra t1, t1, t1 + or t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_41.mlir b/benchmarks/XDSL_ASM/8_function_41.mlir new file mode 100644 index 0000000..0d0d18c --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_41.mlir @@ -0,0 +1,21 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t2, a1 + mv t0, a2 + slt t2, t3, t2 + xori t2, t2, 1 + czero.eqz t1, t0, t2 + czero.nez t4, t3, t2 + or t1, t1, t4 + sra t0, t0, t1 + and t0, t0, t3 + xor t3, t0, t1 + remu t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_42.mlir b/benchmarks/XDSL_ASM/8_function_42.mlir new file mode 100644 index 0000000..ce97ede --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_42.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t0, a2 + div t2, t2, t3 + srl t3, t2, t0 + zext.w t1, t3 + rem t1, t2, t1 + srl t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_43.mlir b/benchmarks/XDSL_ASM/8_function_43.mlir new file mode 100644 index 0000000..b7b37d8 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_43.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t2, a2 + sext.w t1, t1 + czero.eqz t0, t2, t3 + czero.nez t3, t1, t3 + or t0, t0, t3 + sra t0, t1, t0 + sext.w t0, t0 + remu t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_44.mlir b/benchmarks/XDSL_ASM/8_function_44.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_45.mlir b/benchmarks/XDSL_ASM/8_function_45.mlir new file mode 100644 index 0000000..271c0c3 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_45.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t1, a2 + rem t2, t3, t3 + srl t3, t3, t3 + remu t2, t2, t3 + sext.w t0, t0 + sra t0, t2, t0 + and t1, t1, t1 + rem t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_46.mlir b/benchmarks/XDSL_ASM/8_function_46.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_47.mlir b/benchmarks/XDSL_ASM/8_function_47.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_48.mlir b/benchmarks/XDSL_ASM/8_function_48.mlir new file mode 100644 index 0000000..e85bcdf --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_48.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t4, a2 + sext.w t1, t2 + div t0, t2, t1 + divu t2, t2, t4 + srl t2, t3, t2 + remu t1, t1, t3 + xor t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_49.mlir b/benchmarks/XDSL_ASM/8_function_49.mlir new file mode 100644 index 0000000..d3b303f --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_49.mlir @@ -0,0 +1,21 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t3, a2 + mv t4, a3 + czero.eqz t2, t1, t3 + czero.nez t5, t1, t3 + or t2, t2, t5 + sext.w t4, t4 + divu t2, t2, t4 + and t2, t2, t0 + czero.eqz t0, t2, t3 + czero.nez t3, t1, t3 + or t0, t0, t3 + and t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_5.mlir b/benchmarks/XDSL_ASM/8_function_5.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_50.mlir b/benchmarks/XDSL_ASM/8_function_50.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_51.mlir b/benchmarks/XDSL_ASM/8_function_51.mlir new file mode 100644 index 0000000..b488078 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_51.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t1, a2 + mv t2, a3 + sra t3, t3, t0 + and t0, t3, t3 + or t0, t0, t3 + xor t1, t1, t1 + zext.w t2, t2 + srl t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_52.mlir b/benchmarks/XDSL_ASM/8_function_52.mlir new file mode 100644 index 0000000..60ae498 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_52.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + div t1, t0, t1 + sext.w t1, t1 + remu t1, t0, t1 + srl t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_53.mlir b/benchmarks/XDSL_ASM/8_function_53.mlir new file mode 100644 index 0000000..afd1acb --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_53.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + and t2, t3, t3 + czero.eqz t1, t2, t3 + czero.nez t2, t2, t3 + or t1, t1, t2 + srl t1, t1, t0 + or t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_54.mlir b/benchmarks/XDSL_ASM/8_function_54.mlir new file mode 100644 index 0000000..a599e83 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_54.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + or t0, t0, t0 + zext.w t3, t1 + srl t2, t2, t3 + sext.w t1, t1 + remu t2, t2, t1 + and t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_55.mlir b/benchmarks/XDSL_ASM/8_function_55.mlir new file mode 100644 index 0000000..f7961e1 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_55.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t3, a2 + divu t0, t1, t0 + or t2, t3, t0 + divu t3, t3, t0 + div t2, t2, t3 + divu t1, t1, t2 + remu t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_56.mlir b/benchmarks/XDSL_ASM/8_function_56.mlir new file mode 100644 index 0000000..d82e0e7 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_56.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t4, a1 + mv t2, a2 + div t0, t3, t4 + zext.w t1, t3 + or t3, t3, t4 + remu t2, t2, t3 + div t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_57.mlir b/benchmarks/XDSL_ASM/8_function_57.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_58.mlir b/benchmarks/XDSL_ASM/8_function_58.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_59.mlir b/benchmarks/XDSL_ASM/8_function_59.mlir new file mode 100644 index 0000000..08b97a3 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_59.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t2, a1 + mv t1, a2 + and t0, t2, t3 + sext.w t0, t0 + divu t1, t1, t3 + divu t0, t0, t1 + rem t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_6.mlir b/benchmarks/XDSL_ASM/8_function_6.mlir new file mode 100644 index 0000000..28b4c0d --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_6.mlir @@ -0,0 +1,20 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t3, a2 + mv t4, a3 + zext.w t0, t0 + czero.eqz t2, t3, t4 + czero.nez t4, t0, t4 + or t2, t2, t4 + or t3, t2, t3 + rem t2, t3, t2 + xor t2, t2, t3 + divu t2, t2, t3 + rem t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_60.mlir b/benchmarks/XDSL_ASM/8_function_60.mlir new file mode 100644 index 0000000..4df9101 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_60.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t3, a2 + sext.w t0, t2 + czero.eqz t3, t3, t1 + czero.nez t4, t2, t1 + or t3, t3, t4 + rem t1, t1, t3 + xor t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_61.mlir b/benchmarks/XDSL_ASM/8_function_61.mlir new file mode 100644 index 0000000..4fc842a --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_61.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t2, a2 + zext.w t3, t3 + xor t2, t2, t3 + or t1, t0, t0 + rem t1, t1, t3 + xor t1, t1, t2 + srl t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_62.mlir b/benchmarks/XDSL_ASM/8_function_62.mlir new file mode 100644 index 0000000..6a1ddce --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_62.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + zext.w t2, t2 + divu t1, t1, t0 + div t1, t1, t0 + xor t1, t1, t2 + sext.w t2, t0 + sra t1, t1, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_63.mlir b/benchmarks/XDSL_ASM/8_function_63.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_64.mlir b/benchmarks/XDSL_ASM/8_function_64.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_65.mlir b/benchmarks/XDSL_ASM/8_function_65.mlir new file mode 100644 index 0000000..33db3a8 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_65.mlir @@ -0,0 +1,14 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + rem t1, t1, t2 + srl t0, t0, t1 + sext.w t0, t0 + zext.w t0, t0 + rem t0, t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_66.mlir b/benchmarks/XDSL_ASM/8_function_66.mlir new file mode 100644 index 0000000..a43c14e --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_66.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t2, a2 + rem t1, t1, t1 + sext.w t0, t0 + div t2, t1, t2 + zext.w t2, t2 + rem t0, t0, t2 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_67.mlir b/benchmarks/XDSL_ASM/8_function_67.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_68.mlir b/benchmarks/XDSL_ASM/8_function_68.mlir new file mode 100644 index 0000000..911bf0a --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_68.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + div t2, t0, t0 + divu t0, t0, t2 + rem t0, t0, t1 + sext.w t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_69.mlir b/benchmarks/XDSL_ASM/8_function_69.mlir new file mode 100644 index 0000000..27574c7 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_69.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + mv t2, a2 + rem t3, t3, t1 + divu t1, t2, t2 + div t0, t3, t1 + rem t3, t3, t3 + or t3, t3, t1 + div t1, t1, t3 + div t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_7.mlir b/benchmarks/XDSL_ASM/8_function_7.mlir new file mode 100644 index 0000000..a649ccd --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_7.mlir @@ -0,0 +1,20 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t3, a1 + mv t0, a2 + mv t4, a3 + sext.w t1, t1 + and t2, t1, t3 + remu t1, t1, t2 + czero.eqz t2, t2, t4 + czero.nez t4, t1, t4 + or t2, t2, t4 + and t2, t2, t3 + and t2, t2, t1 + remu t0, t0, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_70.mlir b/benchmarks/XDSL_ASM/8_function_70.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_71.mlir b/benchmarks/XDSL_ASM/8_function_71.mlir new file mode 100644 index 0000000..5316b59 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_71.mlir @@ -0,0 +1,21 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t1, a2 + or t2, t0, t0 + slt t3, t3, t2 + czero.eqz t2, t2, t3 + czero.nez t3, t1, t3 + or t2, t2, t3 + srl t0, t0, t2 + czero.eqz t1, t1, t2 + czero.nez t0, t0, t2 + or t1, t1, t0 + czero.eqz t0, t2, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_72.mlir b/benchmarks/XDSL_ASM/8_function_72.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_73.mlir b/benchmarks/XDSL_ASM/8_function_73.mlir new file mode 100644 index 0000000..88de5fb --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_73.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t1, a1 + mv t2, a2 + rem t1, t1, t2 + sext.w t1, t1 + divu t0, t0, t1 + divu t1, t0, t0 + xor t1, t0, t1 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_74.mlir b/benchmarks/XDSL_ASM/8_function_74.mlir new file mode 100644 index 0000000..b9095d6 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_74.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t1, a2 + divu t2, t0, t0 + and t2, t2, t2 + divu t0, t0, t0 + or t0, t2, t0 + and t1, t1, t3 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_75.mlir b/benchmarks/XDSL_ASM/8_function_75.mlir new file mode 100644 index 0000000..4a8ed5d --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_75.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + remu t2, t2, t1 + sext.w t2, t2 + xor t1, t0, t0 + and t1, t1, t2 + sext.w t0, t0 + or t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_76.mlir b/benchmarks/XDSL_ASM/8_function_76.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_77.mlir b/benchmarks/XDSL_ASM/8_function_77.mlir new file mode 100644 index 0000000..15af398 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_77.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t4, a2 + sext.w t1, t2 + xor t1, t3, t1 + czero.eqz t0, t1, t4 + czero.nez t4, t2, t4 + or t0, t0, t4 + div t3, t3, t2 + rem t0, t0, t3 + or t0, t0, t2 + xor t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_78.mlir b/benchmarks/XDSL_ASM/8_function_78.mlir new file mode 100644 index 0000000..7945d16 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_78.mlir @@ -0,0 +1,22 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t3, a1 + mv t2, a2 + mv t4, a3 + zext.w t0, t0 + or t1, t2, t3 + czero.eqz t3, t3, t4 + czero.nez t5, t2, t4 + or t3, t3, t5 + czero.eqz t2, t2, t4 + czero.nez t4, t3, t4 + or t2, t2, t4 + div t3, t3, t0 + srl t2, t2, t3 + remu t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_79.mlir b/benchmarks/XDSL_ASM/8_function_79.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_8.mlir b/benchmarks/XDSL_ASM/8_function_8.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_80.mlir b/benchmarks/XDSL_ASM/8_function_80.mlir new file mode 100644 index 0000000..ade7211 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_80.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + divu t0, t0, t2 + remu t3, t1, t1 + srl t1, t1, t3 + or t2, t2, t2 + rem t2, t2, t1 + srl t1, t1, t2 + rem t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_81.mlir b/benchmarks/XDSL_ASM/8_function_81.mlir new file mode 100644 index 0000000..9098b2d --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_81.mlir @@ -0,0 +1,18 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t2, a1 + mv t1, a2 + czero.eqz t0, t3, t3 + czero.nez t3, t2, t3 + or t0, t0, t3 + div t1, t1, t2 + sra t1, t0, t1 + and t0, t0, t1 + div t2, t0, t2 + div t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_82.mlir b/benchmarks/XDSL_ASM/8_function_82.mlir new file mode 100644 index 0000000..274ac6a --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_82.mlir @@ -0,0 +1,19 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t0, a1 + mv t3, a2 + remu t1, t1, t0 + czero.eqz t2, t0, t3 + czero.nez t3, t0, t3 + or t2, t2, t3 + slt t2, t2, t1 + or t0, t0, t0 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_83.mlir b/benchmarks/XDSL_ASM/8_function_83.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_84.mlir b/benchmarks/XDSL_ASM/8_function_84.mlir new file mode 100644 index 0000000..650ef48 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_84.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + sext.w t1, t0 + zext.w t2, t2 + rem t0, t0, t2 + sext.w t0, t0 + and t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_85.mlir b/benchmarks/XDSL_ASM/8_function_85.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_86.mlir b/benchmarks/XDSL_ASM/8_function_86.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_87.mlir b/benchmarks/XDSL_ASM/8_function_87.mlir new file mode 100644 index 0000000..5146e03 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_87.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sext.w t0, t0 + remu t0, t0, t2 + srl t0, t0, t2 + zext.w t1, t1 + sra t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_88.mlir b/benchmarks/XDSL_ASM/8_function_88.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_89.mlir b/benchmarks/XDSL_ASM/8_function_89.mlir new file mode 100644 index 0000000..7017c66 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_89.mlir @@ -0,0 +1,13 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t1, a0 + mv t2, a1 + xor t0, t2, t1 + and t1, t1, t2 + div t0, t0, t1 + zext.w t0, t0 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_9.mlir b/benchmarks/XDSL_ASM/8_function_9.mlir new file mode 100644 index 0000000..3a0a8e2 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_9.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + sra t0, t0, t2 + sext.w t1, t1 + remu t1, t1, t0 + and t2, t2, t0 + divu t1, t1, t2 + rem t1, t1, t2 + div t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_90.mlir b/benchmarks/XDSL_ASM/8_function_90.mlir new file mode 100644 index 0000000..12b122a --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_90.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t0, a1 + mv t1, a2 + and t2, t3, t3 + sext.w t2, t2 + xor t2, t2, t3 + sltiu t2, t2, 1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + zext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_91.mlir b/benchmarks/XDSL_ASM/8_function_91.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_92.mlir b/benchmarks/XDSL_ASM/8_function_92.mlir new file mode 100644 index 0000000..3d923c2 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_92.mlir @@ -0,0 +1,17 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t3, a0 + mv t1, a1 + and t0, t1, t1 + divu t2, t1, t0 + or t2, t2, t0 + czero.eqz t0, t1, t3 + czero.nez t2, t2, t3 + or t0, t0, t2 + sext.w t0, t0 + and t1, t1, t0 + remu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_93.mlir b/benchmarks/XDSL_ASM/8_function_93.mlir new file mode 100644 index 0000000..4e2d1b4 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_93.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t1, a1 + mv t0, a2 + rem t0, t1, t0 + sext.w t0, t0 + divu t1, t0, t1 + czero.eqz t0, t0, t2 + czero.nez t1, t1, t2 + or t0, t0, t1 + sext.w t0, t0 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_94.mlir b/benchmarks/XDSL_ASM/8_function_94.mlir new file mode 100644 index 0000000..4d96f3f --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_94.mlir @@ -0,0 +1,20 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t4, a1 + mv t1, a2 + mv t2, a3 + div t0, t0, t4 + slt t4, t4, t0 + sra t3, t1, t0 + sext.w t2, t2 + rem t3, t3, t2 + czero.eqz t0, t0, t4 + czero.nez t3, t3, t4 + or t0, t0, t3 + rem t1, t1, t2 + sra t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_95.mlir b/benchmarks/XDSL_ASM/8_function_95.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_ASM/8_function_96.mlir b/benchmarks/XDSL_ASM/8_function_96.mlir new file mode 100644 index 0000000..26a5e95 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_96.mlir @@ -0,0 +1,15 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t1, a2 + divu t2, t0, t2 + rem t0, t0, t2 + sext.w t0, t0 + zext.w t0, t0 + remu t1, t1, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_97.mlir b/benchmarks/XDSL_ASM/8_function_97.mlir new file mode 100644 index 0000000..573600f --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_97.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t2, a0 + mv t3, a1 + mv t1, a2 + sext.w t2, t2 + xor t2, t3, t2 + zext.w t0, t1 + remu t0, t0, t3 + or t0, t0, t2 + sext.w t1, t1 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_98.mlir b/benchmarks/XDSL_ASM/8_function_98.mlir new file mode 100644 index 0000000..3378a06 --- /dev/null +++ b/benchmarks/XDSL_ASM/8_function_98.mlir @@ -0,0 +1,16 @@ +.text +.globl func0 +.p2align 2 +func0: + mv t0, a0 + mv t2, a1 + mv t3, a2 + divu t0, t0, t2 + rem t4, t0, t2 + or t1, t0, t0 + xor t1, t1, t4 + divu t2, t2, t3 + sra t1, t1, t2 + divu t0, t0, t1 + mv a0, t0 + ret diff --git a/benchmarks/XDSL_ASM/8_function_99.mlir b/benchmarks/XDSL_ASM/8_function_99.mlir new file mode 100644 index 0000000..e69de29 diff --git a/benchmarks/XDSL_FUNC/3_function_0.mlir b/benchmarks/XDSL_FUNC/3_function_0.mlir new file mode 100644 index 0000000..5dde401 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_0.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_1.mlir b/benchmarks/XDSL_FUNC/3_function_1.mlir new file mode 100644 index 0000000..7387c59 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_1.mlir @@ -0,0 +1,10 @@ +builtin.module { + func.func @func0(%arg6: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.remu %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + func.return %3 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_10.mlir b/benchmarks/XDSL_FUNC/3_function_10.mlir new file mode 100644 index 0000000..16a4725 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_10.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_11.mlir b/benchmarks/XDSL_FUNC/3_function_11.mlir new file mode 100644 index 0000000..56a98e8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_11.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_12.mlir b/benchmarks/XDSL_FUNC/3_function_12.mlir new file mode 100644 index 0000000..9d59493 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_12.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.and %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_13.mlir b/benchmarks/XDSL_FUNC/3_function_13.mlir new file mode 100644 index 0000000..b364343 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_13.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.slt %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_14.mlir b/benchmarks/XDSL_FUNC/3_function_14.mlir new file mode 100644 index 0000000..fc102b7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_14.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.rem %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_15.mlir b/benchmarks/XDSL_FUNC/3_function_15.mlir new file mode 100644 index 0000000..6b82b94 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_15.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.sltu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_16.mlir b/benchmarks/XDSL_FUNC/3_function_16.mlir new file mode 100644 index 0000000..7bc6fbf --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_16.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_17.mlir b/benchmarks/XDSL_FUNC/3_function_17.mlir new file mode 100644 index 0000000..d7b1f39 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_17.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.and %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_18.mlir b/benchmarks/XDSL_FUNC/3_function_18.mlir new file mode 100644 index 0000000..175e677 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_18.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_19.mlir b/benchmarks/XDSL_FUNC/3_function_19.mlir new file mode 100644 index 0000000..cc6ec00 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_19.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + func.return %4 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_2.mlir b/benchmarks/XDSL_FUNC/3_function_2.mlir new file mode 100644 index 0000000..2079a49 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_2.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_20.mlir b/benchmarks/XDSL_FUNC/3_function_20.mlir new file mode 100644 index 0000000..90326de --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_20.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_21.mlir b/benchmarks/XDSL_FUNC/3_function_21.mlir new file mode 100644 index 0000000..7cefe92 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_21.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.xor %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sltiu %5, 1 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_22.mlir b/benchmarks/XDSL_FUNC/3_function_22.mlir new file mode 100644 index 0000000..afdb05e --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_22.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_23.mlir b/benchmarks/XDSL_FUNC/3_function_23.mlir new file mode 100644 index 0000000..af1a3ee --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_23.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_24.mlir b/benchmarks/XDSL_FUNC/3_function_24.mlir new file mode 100644 index 0000000..95fb73c --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_24.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %6 = riscv.czero.eqz %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_25.mlir b/benchmarks/XDSL_FUNC/3_function_25.mlir new file mode 100644 index 0000000..98b21fa --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_25.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_26.mlir b/benchmarks/XDSL_FUNC/3_function_26.mlir new file mode 100644 index 0000000..a6280c0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_26.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_27.mlir b/benchmarks/XDSL_FUNC/3_function_27.mlir new file mode 100644 index 0000000..7ccb132 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_27.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_28.mlir b/benchmarks/XDSL_FUNC/3_function_28.mlir new file mode 100644 index 0000000..23dee71 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_28.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.xor %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sltiu %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_29.mlir b/benchmarks/XDSL_FUNC/3_function_29.mlir new file mode 100644 index 0000000..73139c6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_29.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.slt %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xori %5, 1 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_3.mlir b/benchmarks/XDSL_FUNC/3_function_3.mlir new file mode 100644 index 0000000..74939d8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_3.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.slt %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xori %5, 1 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_30.mlir b/benchmarks/XDSL_FUNC/3_function_30.mlir new file mode 100644 index 0000000..289ad22 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_30.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.slt %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_31.mlir b/benchmarks/XDSL_FUNC/3_function_31.mlir new file mode 100644 index 0000000..10d9453 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_31.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_32.mlir b/benchmarks/XDSL_FUNC/3_function_32.mlir new file mode 100644 index 0000000..b3837e4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_32.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.div %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_33.mlir b/benchmarks/XDSL_FUNC/3_function_33.mlir new file mode 100644 index 0000000..3e0a85f --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_33.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + func.return %4 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_34.mlir b/benchmarks/XDSL_FUNC/3_function_34.mlir new file mode 100644 index 0000000..93e0a93 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_34.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.div %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i64 + func.return %5 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_35.mlir b/benchmarks/XDSL_FUNC/3_function_35.mlir new file mode 100644 index 0000000..a06b85e --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_35.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sltu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_36.mlir b/benchmarks/XDSL_FUNC/3_function_36.mlir new file mode 100644 index 0000000..98b21fa --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_36.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_37.mlir b/benchmarks/XDSL_FUNC/3_function_37.mlir new file mode 100644 index 0000000..c54318a --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_37.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_38.mlir b/benchmarks/XDSL_FUNC/3_function_38.mlir new file mode 100644 index 0000000..66c36b7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_38.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.slt %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xori %5, 1 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_39.mlir b/benchmarks/XDSL_FUNC/3_function_39.mlir new file mode 100644 index 0000000..391ed62 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_39.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_4.mlir b/benchmarks/XDSL_FUNC/3_function_4.mlir new file mode 100644 index 0000000..60871a3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_4.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_40.mlir b/benchmarks/XDSL_FUNC/3_function_40.mlir new file mode 100644 index 0000000..fe6ae48 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_40.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.rem %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_41.mlir b/benchmarks/XDSL_FUNC/3_function_41.mlir new file mode 100644 index 0000000..cc6ec00 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_41.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + func.return %4 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_42.mlir b/benchmarks/XDSL_FUNC/3_function_42.mlir new file mode 100644 index 0000000..7434dc5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_42.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_43.mlir b/benchmarks/XDSL_FUNC/3_function_43.mlir new file mode 100644 index 0000000..8dea0bb --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_43.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.and %4, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_44.mlir b/benchmarks/XDSL_FUNC/3_function_44.mlir new file mode 100644 index 0000000..a9d5f38 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_44.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.sra %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.srl %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_45.mlir b/benchmarks/XDSL_FUNC/3_function_45.mlir new file mode 100644 index 0000000..8c866ac --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_45.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_46.mlir b/benchmarks/XDSL_FUNC/3_function_46.mlir new file mode 100644 index 0000000..0833f10 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_46.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xor %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sltiu %5, 1 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_47.mlir b/benchmarks/XDSL_FUNC/3_function_47.mlir new file mode 100644 index 0000000..a72f0fc --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_47.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.remu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_48.mlir b/benchmarks/XDSL_FUNC/3_function_48.mlir new file mode 100644 index 0000000..3e0a85f --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_48.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + func.return %4 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_49.mlir b/benchmarks/XDSL_FUNC/3_function_49.mlir new file mode 100644 index 0000000..f064419 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_49.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_5.mlir b/benchmarks/XDSL_FUNC/3_function_5.mlir new file mode 100644 index 0000000..266d76d --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_5.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.lui 0 : () -> !riscv.reg + %8 = riscv.sltu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_50.mlir b/benchmarks/XDSL_FUNC/3_function_50.mlir new file mode 100644 index 0000000..10e951a --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_50.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_51.mlir b/benchmarks/XDSL_FUNC/3_function_51.mlir new file mode 100644 index 0000000..24f89a0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_51.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_52.mlir b/benchmarks/XDSL_FUNC/3_function_52.mlir new file mode 100644 index 0000000..3e0a85f --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_52.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + func.return %4 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_53.mlir b/benchmarks/XDSL_FUNC/3_function_53.mlir new file mode 100644 index 0000000..18e56fa --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_53.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.div %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_54.mlir b/benchmarks/XDSL_FUNC/3_function_54.mlir new file mode 100644 index 0000000..a6e35ac --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_54.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_55.mlir b/benchmarks/XDSL_FUNC/3_function_55.mlir new file mode 100644 index 0000000..8dbd4dd --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_55.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_56.mlir b/benchmarks/XDSL_FUNC/3_function_56.mlir new file mode 100644 index 0000000..98b21fa --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_56.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_57.mlir b/benchmarks/XDSL_FUNC/3_function_57.mlir new file mode 100644 index 0000000..78548fc --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_57.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.sltu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xori %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_58.mlir b/benchmarks/XDSL_FUNC/3_function_58.mlir new file mode 100644 index 0000000..eff1203 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_58.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.sltu %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xori %5, 1 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_59.mlir b/benchmarks/XDSL_FUNC/3_function_59.mlir new file mode 100644 index 0000000..d73befe --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_59.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_6.mlir b/benchmarks/XDSL_FUNC/3_function_6.mlir new file mode 100644 index 0000000..24f89a0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_6.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_60.mlir b/benchmarks/XDSL_FUNC/3_function_60.mlir new file mode 100644 index 0000000..d6ab94c --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_60.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_61.mlir b/benchmarks/XDSL_FUNC/3_function_61.mlir new file mode 100644 index 0000000..b873fb0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_61.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.div %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_62.mlir b/benchmarks/XDSL_FUNC/3_function_62.mlir new file mode 100644 index 0000000..e2347a2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_62.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.remu %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_63.mlir b/benchmarks/XDSL_FUNC/3_function_63.mlir new file mode 100644 index 0000000..98b21fa --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_63.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_64.mlir b/benchmarks/XDSL_FUNC/3_function_64.mlir new file mode 100644 index 0000000..72e5958 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_64.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.srl %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_65.mlir b/benchmarks/XDSL_FUNC/3_function_65.mlir new file mode 100644 index 0000000..1bcf9dc --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_65.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.remu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_66.mlir b/benchmarks/XDSL_FUNC/3_function_66.mlir new file mode 100644 index 0000000..26e2cf2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_66.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.sra %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_67.mlir b/benchmarks/XDSL_FUNC/3_function_67.mlir new file mode 100644 index 0000000..c828324 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_67.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.divu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_68.mlir b/benchmarks/XDSL_FUNC/3_function_68.mlir new file mode 100644 index 0000000..d8e2df9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_68.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_69.mlir b/benchmarks/XDSL_FUNC/3_function_69.mlir new file mode 100644 index 0000000..842b2e8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_69.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_7.mlir b/benchmarks/XDSL_FUNC/3_function_7.mlir new file mode 100644 index 0000000..a60f8f8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_7.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.srl %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_70.mlir b/benchmarks/XDSL_FUNC/3_function_70.mlir new file mode 100644 index 0000000..46daa4e --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_70.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_71.mlir b/benchmarks/XDSL_FUNC/3_function_71.mlir new file mode 100644 index 0000000..1c5e4a3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_71.mlir @@ -0,0 +1,10 @@ +builtin.module { + func.func @func0(%arg6: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.rem %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + func.return %3 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_72.mlir b/benchmarks/XDSL_FUNC/3_function_72.mlir new file mode 100644 index 0000000..5241d0e --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_72.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.xor %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.slt %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xori %4, 1 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_73.mlir b/benchmarks/XDSL_FUNC/3_function_73.mlir new file mode 100644 index 0000000..be4bc77 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_73.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_74.mlir b/benchmarks/XDSL_FUNC/3_function_74.mlir new file mode 100644 index 0000000..72b5c52 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_74.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_75.mlir b/benchmarks/XDSL_FUNC/3_function_75.mlir new file mode 100644 index 0000000..4e5e9f0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_75.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.rem %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_76.mlir b/benchmarks/XDSL_FUNC/3_function_76.mlir new file mode 100644 index 0000000..36d8073 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_76.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.or %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_77.mlir b/benchmarks/XDSL_FUNC/3_function_77.mlir new file mode 100644 index 0000000..62bcb0f --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_77.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sltu %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_78.mlir b/benchmarks/XDSL_FUNC/3_function_78.mlir new file mode 100644 index 0000000..44407ba --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_78.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.and %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_79.mlir b/benchmarks/XDSL_FUNC/3_function_79.mlir new file mode 100644 index 0000000..46425e7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_79.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.remu %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_8.mlir b/benchmarks/XDSL_FUNC/3_function_8.mlir new file mode 100644 index 0000000..47447d7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_8.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.slt %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_80.mlir b/benchmarks/XDSL_FUNC/3_function_80.mlir new file mode 100644 index 0000000..0202b88 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_80.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.div %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.slt %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xori %4, 1 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_81.mlir b/benchmarks/XDSL_FUNC/3_function_81.mlir new file mode 100644 index 0000000..ac9e3e5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_81.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_82.mlir b/benchmarks/XDSL_FUNC/3_function_82.mlir new file mode 100644 index 0000000..c97b1d6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_82.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_83.mlir b/benchmarks/XDSL_FUNC/3_function_83.mlir new file mode 100644 index 0000000..9bba890 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_83.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_84.mlir b/benchmarks/XDSL_FUNC/3_function_84.mlir new file mode 100644 index 0000000..59dc3e0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_84.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.rem %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_85.mlir b/benchmarks/XDSL_FUNC/3_function_85.mlir new file mode 100644 index 0000000..baeeb35 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_85.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.div %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_86.mlir b/benchmarks/XDSL_FUNC/3_function_86.mlir new file mode 100644 index 0000000..839768e --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_86.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i32, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %4 = riscv.czero.eqz %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_87.mlir b/benchmarks/XDSL_FUNC/3_function_87.mlir new file mode 100644 index 0000000..55ad240 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_87.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %7 = riscv.czero.eqz %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_88.mlir b/benchmarks/XDSL_FUNC/3_function_88.mlir new file mode 100644 index 0000000..2c11dc7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_88.mlir @@ -0,0 +1,10 @@ +builtin.module { + func.func @func0(%arg6: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.divu %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + func.return %3 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_89.mlir b/benchmarks/XDSL_FUNC/3_function_89.mlir new file mode 100644 index 0000000..e89025d --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_89.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_9.mlir b/benchmarks/XDSL_FUNC/3_function_9.mlir new file mode 100644 index 0000000..005c44a --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_9.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.lui 0 : () -> !riscv.reg + %4 = riscv.sltu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.slt %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.xori %13, 1 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_90.mlir b/benchmarks/XDSL_FUNC/3_function_90.mlir new file mode 100644 index 0000000..6a82d52 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_90.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_91.mlir b/benchmarks/XDSL_FUNC/3_function_91.mlir new file mode 100644 index 0000000..f01c6dd --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_91.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_92.mlir b/benchmarks/XDSL_FUNC/3_function_92.mlir new file mode 100644 index 0000000..2912129 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_92.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_93.mlir b/benchmarks/XDSL_FUNC/3_function_93.mlir new file mode 100644 index 0000000..b8f8241 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_93.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = riscv.slt %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.xori %12, 1 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_94.mlir b/benchmarks/XDSL_FUNC/3_function_94.mlir new file mode 100644 index 0000000..fc0d1d3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_94.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.xor %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + func.return %4 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_95.mlir b/benchmarks/XDSL_FUNC/3_function_95.mlir new file mode 100644 index 0000000..84fcdab --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_95.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + func.return %5 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_96.mlir b/benchmarks/XDSL_FUNC/3_function_96.mlir new file mode 100644 index 0000000..74ad976 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_96.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.sext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.divu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_97.mlir b/benchmarks/XDSL_FUNC/3_function_97.mlir new file mode 100644 index 0000000..5924432 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_97.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %7 = riscv.czero.eqz %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_98.mlir b/benchmarks/XDSL_FUNC/3_function_98.mlir new file mode 100644 index 0000000..24f89a0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_98.mlir @@ -0,0 +1,11 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + func.return %4 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/3_function_99.mlir b/benchmarks/XDSL_FUNC/3_function_99.mlir new file mode 100644 index 0000000..1278578 --- /dev/null +++ b/benchmarks/XDSL_FUNC/3_function_99.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_0.mlir b/benchmarks/XDSL_FUNC/4_function_0.mlir new file mode 100644 index 0000000..1cc2258 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_0.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.srl %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_1.mlir b/benchmarks/XDSL_FUNC/4_function_1.mlir new file mode 100644 index 0000000..29364b9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_1.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_10.mlir b/benchmarks/XDSL_FUNC/4_function_10.mlir new file mode 100644 index 0000000..94191cc --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_10.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_11.mlir b/benchmarks/XDSL_FUNC/4_function_11.mlir new file mode 100644 index 0000000..b57d45a --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_11.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_12.mlir b/benchmarks/XDSL_FUNC/4_function_12.mlir new file mode 100644 index 0000000..aa93722 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_12.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.and %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.sltu %6, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xori %7, 1 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_13.mlir b/benchmarks/XDSL_FUNC/4_function_13.mlir new file mode 100644 index 0000000..134b71d --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_13.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.sltu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_14.mlir b/benchmarks/XDSL_FUNC/4_function_14.mlir new file mode 100644 index 0000000..525b742 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_14.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.remu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.divu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.remu %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_15.mlir b/benchmarks/XDSL_FUNC/4_function_15.mlir new file mode 100644 index 0000000..06580f8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_15.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.remu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.srl %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_16.mlir b/benchmarks/XDSL_FUNC/4_function_16.mlir new file mode 100644 index 0000000..6816334 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_16.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.rem %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.sltu %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xori %7, 1 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_17.mlir b/benchmarks/XDSL_FUNC/4_function_17.mlir new file mode 100644 index 0000000..969ceb9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_17.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.divu %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %6 = riscv.czero.eqz %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.rem %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_18.mlir b/benchmarks/XDSL_FUNC/4_function_18.mlir new file mode 100644 index 0000000..939341b --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_18.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.remu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_19.mlir b/benchmarks/XDSL_FUNC/4_function_19.mlir new file mode 100644 index 0000000..1269f81 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_19.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_2.mlir b/benchmarks/XDSL_FUNC/4_function_2.mlir new file mode 100644 index 0000000..cf4d792 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_2.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_20.mlir b/benchmarks/XDSL_FUNC/4_function_20.mlir new file mode 100644 index 0000000..fddcc27 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_20.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64, %arg6_3: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %6 = riscv.czero.eqz %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.sra %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_21.mlir b/benchmarks/XDSL_FUNC/4_function_21.mlir new file mode 100644 index 0000000..061fb95 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_21.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.sra %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.slt %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_22.mlir b/benchmarks/XDSL_FUNC/4_function_22.mlir new file mode 100644 index 0000000..9319612 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_22.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.srl %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.remu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_23.mlir b/benchmarks/XDSL_FUNC/4_function_23.mlir new file mode 100644 index 0000000..5bb69c7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_23.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i32, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.remu %1, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_24.mlir b/benchmarks/XDSL_FUNC/4_function_24.mlir new file mode 100644 index 0000000..a89257e --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_24.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %8 = riscv.czero.eqz %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_25.mlir b/benchmarks/XDSL_FUNC/4_function_25.mlir new file mode 100644 index 0000000..e1a64d7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_25.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.srl %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_26.mlir b/benchmarks/XDSL_FUNC/4_function_26.mlir new file mode 100644 index 0000000..89982c3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_26.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.sltiu %7, 1 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %9 : i1 to !riscv.reg + %13 = riscv.czero.eqz %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.xor %15, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_27.mlir b/benchmarks/XDSL_FUNC/4_function_27.mlir new file mode 100644 index 0000000..58865e8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_27.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_28.mlir b/benchmarks/XDSL_FUNC/4_function_28.mlir new file mode 100644 index 0000000..3b31ccd --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_28.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %4, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %1, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_29.mlir b/benchmarks/XDSL_FUNC/4_function_29.mlir new file mode 100644 index 0000000..ff15e7f --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_29.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.slt %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_3.mlir b/benchmarks/XDSL_FUNC/4_function_3.mlir new file mode 100644 index 0000000..d7dc7b9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_3.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %7 = riscv.czero.eqz %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.srl %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_30.mlir b/benchmarks/XDSL_FUNC/4_function_30.mlir new file mode 100644 index 0000000..ea18a68 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_30.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.sltu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xori %7, 1 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_31.mlir b/benchmarks/XDSL_FUNC/4_function_31.mlir new file mode 100644 index 0000000..6bf1085 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_31.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_32.mlir b/benchmarks/XDSL_FUNC/4_function_32.mlir new file mode 100644 index 0000000..cf4b36d --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_32.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %4 = riscv.czero.eqz %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.remu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_33.mlir b/benchmarks/XDSL_FUNC/4_function_33.mlir new file mode 100644 index 0000000..f0f57e6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_33.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.sltiu %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = riscv.xor %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_34.mlir b/benchmarks/XDSL_FUNC/4_function_34.mlir new file mode 100644 index 0000000..68ba088 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_34.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.srl %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_35.mlir b/benchmarks/XDSL_FUNC/4_function_35.mlir new file mode 100644 index 0000000..9e3cabc --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_35.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_36.mlir b/benchmarks/XDSL_FUNC/4_function_36.mlir new file mode 100644 index 0000000..2a0c5dc --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_36.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.remu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.remu %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_37.mlir b/benchmarks/XDSL_FUNC/4_function_37.mlir new file mode 100644 index 0000000..4bb8fa9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_37.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_38.mlir b/benchmarks/XDSL_FUNC/4_function_38.mlir new file mode 100644 index 0000000..310cbfe --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_38.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.or %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.remu %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sltu %5, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_39.mlir b/benchmarks/XDSL_FUNC/4_function_39.mlir new file mode 100644 index 0000000..7a48fa8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_39.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.remu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_4.mlir b/benchmarks/XDSL_FUNC/4_function_4.mlir new file mode 100644 index 0000000..430baa7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_4.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.xor %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_40.mlir b/benchmarks/XDSL_FUNC/4_function_40.mlir new file mode 100644 index 0000000..0b4eac6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_40.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.divu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_41.mlir b/benchmarks/XDSL_FUNC/4_function_41.mlir new file mode 100644 index 0000000..5904e21 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_41.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.rem %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_42.mlir b/benchmarks/XDSL_FUNC/4_function_42.mlir new file mode 100644 index 0000000..f51bb15 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_42.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = riscv.rem %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.and %7, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_43.mlir b/benchmarks/XDSL_FUNC/4_function_43.mlir new file mode 100644 index 0000000..1bc3247 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_43.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_44.mlir b/benchmarks/XDSL_FUNC/4_function_44.mlir new file mode 100644 index 0000000..18f3308 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_44.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.rem %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %4 = riscv.sext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.remu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i64 + func.return %6 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_45.mlir b/benchmarks/XDSL_FUNC/4_function_45.mlir new file mode 100644 index 0000000..b6bdaf6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_45.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.srl %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_46.mlir b/benchmarks/XDSL_FUNC/4_function_46.mlir new file mode 100644 index 0000000..5ccf5fe --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_46.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.sltu %7, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.xori %8, 1 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_47.mlir b/benchmarks/XDSL_FUNC/4_function_47.mlir new file mode 100644 index 0000000..ef0a923 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_47.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.remu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sra %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_48.mlir b/benchmarks/XDSL_FUNC/4_function_48.mlir new file mode 100644 index 0000000..2fbe456 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_48.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %1 : !riscv.reg to i32 + %3 = builtin.unrealized_conversion_cast %2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_49.mlir b/benchmarks/XDSL_FUNC/4_function_49.mlir new file mode 100644 index 0000000..00214d7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_49.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.srl %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_5.mlir b/benchmarks/XDSL_FUNC/4_function_5.mlir new file mode 100644 index 0000000..5b551b2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_5.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_50.mlir b/benchmarks/XDSL_FUNC/4_function_50.mlir new file mode 100644 index 0000000..dd9b72d --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_50.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_51.mlir b/benchmarks/XDSL_FUNC/4_function_51.mlir new file mode 100644 index 0000000..368c4d6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_51.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.srl %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.divu %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_52.mlir b/benchmarks/XDSL_FUNC/4_function_52.mlir new file mode 100644 index 0000000..0b3a4ea --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_52.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.srl %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.slt %7, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_53.mlir b/benchmarks/XDSL_FUNC/4_function_53.mlir new file mode 100644 index 0000000..9a64b2c --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_53.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.div %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_54.mlir b/benchmarks/XDSL_FUNC/4_function_54.mlir new file mode 100644 index 0000000..8ed712b --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_54.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.remu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_55.mlir b/benchmarks/XDSL_FUNC/4_function_55.mlir new file mode 100644 index 0000000..f3d3c70 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_55.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.remu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.divu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_56.mlir b/benchmarks/XDSL_FUNC/4_function_56.mlir new file mode 100644 index 0000000..1da607c --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_56.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %7, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.rem %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_57.mlir b/benchmarks/XDSL_FUNC/4_function_57.mlir new file mode 100644 index 0000000..395e607 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_57.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.or %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_58.mlir b/benchmarks/XDSL_FUNC/4_function_58.mlir new file mode 100644 index 0000000..73212a8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_58.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_59.mlir b/benchmarks/XDSL_FUNC/4_function_59.mlir new file mode 100644 index 0000000..896e4ac --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_59.mlir @@ -0,0 +1,12 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = riscv.sra %3, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + func.return %5 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_6.mlir b/benchmarks/XDSL_FUNC/4_function_6.mlir new file mode 100644 index 0000000..995e082 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_6.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.srl %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %7, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_60.mlir b/benchmarks/XDSL_FUNC/4_function_60.mlir new file mode 100644 index 0000000..9e3cabc --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_60.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_61.mlir b/benchmarks/XDSL_FUNC/4_function_61.mlir new file mode 100644 index 0000000..f7d04cb --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_61.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %4, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.or %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_62.mlir b/benchmarks/XDSL_FUNC/4_function_62.mlir new file mode 100644 index 0000000..9d10dc5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_62.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.remu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_63.mlir b/benchmarks/XDSL_FUNC/4_function_63.mlir new file mode 100644 index 0000000..a24b599 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_63.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.sra %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.rem %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.lui 0 : () -> !riscv.reg + %13 = riscv.sltu %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_64.mlir b/benchmarks/XDSL_FUNC/4_function_64.mlir new file mode 100644 index 0000000..b91ba5f --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_64.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.sra %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_65.mlir b/benchmarks/XDSL_FUNC/4_function_65.mlir new file mode 100644 index 0000000..cb884a6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_65.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.remu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xor %4, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sltu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_66.mlir b/benchmarks/XDSL_FUNC/4_function_66.mlir new file mode 100644 index 0000000..0667e9a --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_66.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_67.mlir b/benchmarks/XDSL_FUNC/4_function_67.mlir new file mode 100644 index 0000000..616a60f --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_67.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_68.mlir b/benchmarks/XDSL_FUNC/4_function_68.mlir new file mode 100644 index 0000000..605e800 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_68.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_69.mlir b/benchmarks/XDSL_FUNC/4_function_69.mlir new file mode 100644 index 0000000..ad37304 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_69.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.srl %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %8 = riscv.czero.eqz %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_7.mlir b/benchmarks/XDSL_FUNC/4_function_7.mlir new file mode 100644 index 0000000..3f47e65 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_7.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.slt %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = riscv.divu %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %9 = riscv.czero.eqz %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_70.mlir b/benchmarks/XDSL_FUNC/4_function_70.mlir new file mode 100644 index 0000000..4fcdbc3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_70.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.xor %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_71.mlir b/benchmarks/XDSL_FUNC/4_function_71.mlir new file mode 100644 index 0000000..04b57aa --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_71.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.div %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %4, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_72.mlir b/benchmarks/XDSL_FUNC/4_function_72.mlir new file mode 100644 index 0000000..605ab31 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_72.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.srl %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_73.mlir b/benchmarks/XDSL_FUNC/4_function_73.mlir new file mode 100644 index 0000000..b418261 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_73.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.xor %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_74.mlir b/benchmarks/XDSL_FUNC/4_function_74.mlir new file mode 100644 index 0000000..fa1f8e9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_74.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sltu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %7 = riscv.czero.eqz %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %10 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %9, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i64 + func.return %16 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_75.mlir b/benchmarks/XDSL_FUNC/4_function_75.mlir new file mode 100644 index 0000000..f612d40 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_75.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.xor %7, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sltiu %8, 1 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %10 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %5, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i64 + func.return %16 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_76.mlir b/benchmarks/XDSL_FUNC/4_function_76.mlir new file mode 100644 index 0000000..db56ff2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_76.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.srl %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_77.mlir b/benchmarks/XDSL_FUNC/4_function_77.mlir new file mode 100644 index 0000000..805e7f4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_77.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.div %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_78.mlir b/benchmarks/XDSL_FUNC/4_function_78.mlir new file mode 100644 index 0000000..1cb8a08 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_78.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.sra %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_79.mlir b/benchmarks/XDSL_FUNC/4_function_79.mlir new file mode 100644 index 0000000..29364b9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_79.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_8.mlir b/benchmarks/XDSL_FUNC/4_function_8.mlir new file mode 100644 index 0000000..7eecbce --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_8.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.sltiu %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %9 = riscv.czero.eqz %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_80.mlir b/benchmarks/XDSL_FUNC/4_function_80.mlir new file mode 100644 index 0000000..c573d83 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_80.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.remu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.and %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_81.mlir b/benchmarks/XDSL_FUNC/4_function_81.mlir new file mode 100644 index 0000000..6a99e2c --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_81.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xor %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.rem %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_82.mlir b/benchmarks/XDSL_FUNC/4_function_82.mlir new file mode 100644 index 0000000..dcb4559 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_82.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.xor %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_83.mlir b/benchmarks/XDSL_FUNC/4_function_83.mlir new file mode 100644 index 0000000..fae570d --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_83.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_84.mlir b/benchmarks/XDSL_FUNC/4_function_84.mlir new file mode 100644 index 0000000..f77bfc6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_84.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.remu %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_85.mlir b/benchmarks/XDSL_FUNC/4_function_85.mlir new file mode 100644 index 0000000..6e1db41 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_85.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.srl %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.srl %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_86.mlir b/benchmarks/XDSL_FUNC/4_function_86.mlir new file mode 100644 index 0000000..486fc8b --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_86.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %7 = riscv.czero.eqz %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_87.mlir b/benchmarks/XDSL_FUNC/4_function_87.mlir new file mode 100644 index 0000000..1615efc --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_87.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.and %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_88.mlir b/benchmarks/XDSL_FUNC/4_function_88.mlir new file mode 100644 index 0000000..bc9a52b --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_88.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_89.mlir b/benchmarks/XDSL_FUNC/4_function_89.mlir new file mode 100644 index 0000000..1411178 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_89.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.or %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_9.mlir b/benchmarks/XDSL_FUNC/4_function_9.mlir new file mode 100644 index 0000000..89a18af --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_9.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.div %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.slt %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_90.mlir b/benchmarks/XDSL_FUNC/4_function_90.mlir new file mode 100644 index 0000000..28060e8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_90.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.remu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.xor %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_91.mlir b/benchmarks/XDSL_FUNC/4_function_91.mlir new file mode 100644 index 0000000..b073241 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_91.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.sra %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.div %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_92.mlir b/benchmarks/XDSL_FUNC/4_function_92.mlir new file mode 100644 index 0000000..67f149c --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_92.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.div %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xor %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_93.mlir b/benchmarks/XDSL_FUNC/4_function_93.mlir new file mode 100644 index 0000000..53a803e --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_93.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.or %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.sltu %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_94.mlir b/benchmarks/XDSL_FUNC/4_function_94.mlir new file mode 100644 index 0000000..4e5ae5f --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_94.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %7 = riscv.czero.eqz %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sltu %9, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_95.mlir b/benchmarks/XDSL_FUNC/4_function_95.mlir new file mode 100644 index 0000000..e076015 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_95.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.remu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.and %4, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sltu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_96.mlir b/benchmarks/XDSL_FUNC/4_function_96.mlir new file mode 100644 index 0000000..f5045a0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_96.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.and %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.srl %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.slt %3, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_97.mlir b/benchmarks/XDSL_FUNC/4_function_97.mlir new file mode 100644 index 0000000..3cac3f7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_97.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sra %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_98.mlir b/benchmarks/XDSL_FUNC/4_function_98.mlir new file mode 100644 index 0000000..78f5155 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_98.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i64 + func.return %7 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/4_function_99.mlir b/benchmarks/XDSL_FUNC/4_function_99.mlir new file mode 100644 index 0000000..d2243c6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/4_function_99.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_0.mlir b/benchmarks/XDSL_FUNC/5_function_0.mlir new file mode 100644 index 0000000..3146df9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_0.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.remu %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.div %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.remu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_1.mlir b/benchmarks/XDSL_FUNC/5_function_1.mlir new file mode 100644 index 0000000..115b6e2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_1.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.sra %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.remu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + func.return %6 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_10.mlir b/benchmarks/XDSL_FUNC/5_function_10.mlir new file mode 100644 index 0000000..1b80aeb --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_10.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.rem %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.remu %3, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_11.mlir b/benchmarks/XDSL_FUNC/5_function_11.mlir new file mode 100644 index 0000000..59b6196 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_11.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.div %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_12.mlir b/benchmarks/XDSL_FUNC/5_function_12.mlir new file mode 100644 index 0000000..72f273b --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_12.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.slt %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %7 : i1 to !riscv.reg + %11 = riscv.czero.eqz %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.slt %13, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.xori %14, 1 : (!riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i1 + func.return %16 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_13.mlir b/benchmarks/XDSL_FUNC/5_function_13.mlir new file mode 100644 index 0000000..942cdfb --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_13.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.srl %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.slt %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_14.mlir b/benchmarks/XDSL_FUNC/5_function_14.mlir new file mode 100644 index 0000000..b7ca542 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_14.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sltu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %7, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.remu %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %12 = riscv.czero.eqz %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_15.mlir b/benchmarks/XDSL_FUNC/5_function_15.mlir new file mode 100644 index 0000000..29b5d90 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_15.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.slt %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = riscv.div %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_16.mlir b/benchmarks/XDSL_FUNC/5_function_16.mlir new file mode 100644 index 0000000..7536cbd --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_16.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.divu %4, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_17.mlir b/benchmarks/XDSL_FUNC/5_function_17.mlir new file mode 100644 index 0000000..1d8a2d7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_17.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.sra %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_18.mlir b/benchmarks/XDSL_FUNC/5_function_18.mlir new file mode 100644 index 0000000..4237673 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_18.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.div %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_19.mlir b/benchmarks/XDSL_FUNC/5_function_19.mlir new file mode 100644 index 0000000..626edbd --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_19.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.sra %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.remu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.sltu %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_2.mlir b/benchmarks/XDSL_FUNC/5_function_2.mlir new file mode 100644 index 0000000..0143d96 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_2.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.and %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.sra %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.remu %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_20.mlir b/benchmarks/XDSL_FUNC/5_function_20.mlir new file mode 100644 index 0000000..6fae2c6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_20.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.divu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.xor %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_21.mlir b/benchmarks/XDSL_FUNC/5_function_21.mlir new file mode 100644 index 0000000..5d0eb5e --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_21.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %6 = riscv.czero.eqz %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_22.mlir b/benchmarks/XDSL_FUNC/5_function_22.mlir new file mode 100644 index 0000000..c5b835c --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_22.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_23.mlir b/benchmarks/XDSL_FUNC/5_function_23.mlir new file mode 100644 index 0000000..9b1e27a --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_23.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_24.mlir b/benchmarks/XDSL_FUNC/5_function_24.mlir new file mode 100644 index 0000000..f3eb627 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_24.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.and %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.srl %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_25.mlir b/benchmarks/XDSL_FUNC/5_function_25.mlir new file mode 100644 index 0000000..f62ea7c --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_25.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.remu %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.and %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %11, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_26.mlir b/benchmarks/XDSL_FUNC/5_function_26.mlir new file mode 100644 index 0000000..b3d8035 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_26.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_27.mlir b/benchmarks/XDSL_FUNC/5_function_27.mlir new file mode 100644 index 0000000..1f985b7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_27.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.slt %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.rem %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %11 = riscv.czero.eqz %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_28.mlir b/benchmarks/XDSL_FUNC/5_function_28.mlir new file mode 100644 index 0000000..c433811 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_28.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.div %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.rem %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %7 = riscv.czero.eqz %3, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_29.mlir b/benchmarks/XDSL_FUNC/5_function_29.mlir new file mode 100644 index 0000000..f33d374 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_29.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.div %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.rem %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_3.mlir b/benchmarks/XDSL_FUNC/5_function_3.mlir new file mode 100644 index 0000000..f4ae0d0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_3.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_30.mlir b/benchmarks/XDSL_FUNC/5_function_30.mlir new file mode 100644 index 0000000..3c55c10 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_30.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.div %4, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_31.mlir b/benchmarks/XDSL_FUNC/5_function_31.mlir new file mode 100644 index 0000000..98a7835 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_31.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.slt %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xori %4, 1 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %11 = riscv.czero.eqz %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %15 = riscv.xor %14, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i64 + func.return %16 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_32.mlir b/benchmarks/XDSL_FUNC/5_function_32.mlir new file mode 100644 index 0000000..c4bd047 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_32.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_33.mlir b/benchmarks/XDSL_FUNC/5_function_33.mlir new file mode 100644 index 0000000..5b0d14e --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_33.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %7 = riscv.czero.eqz %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.and %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_34.mlir b/benchmarks/XDSL_FUNC/5_function_34.mlir new file mode 100644 index 0000000..596131a --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_34.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.xor %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.xor %3, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.or %1, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xor %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.lui 0 : () -> !riscv.reg + %9 = riscv.sltu %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_35.mlir b/benchmarks/XDSL_FUNC/5_function_35.mlir new file mode 100644 index 0000000..efe5c54 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_35.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.divu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.srl %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_36.mlir b/benchmarks/XDSL_FUNC/5_function_36.mlir new file mode 100644 index 0000000..aeaed9b --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_36.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_37.mlir b/benchmarks/XDSL_FUNC/5_function_37.mlir new file mode 100644 index 0000000..6fac40d --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_37.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %8 = riscv.czero.eqz %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_38.mlir b/benchmarks/XDSL_FUNC/5_function_38.mlir new file mode 100644 index 0000000..ae30015 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_38.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %6 = riscv.czero.eqz %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.div %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_39.mlir b/benchmarks/XDSL_FUNC/5_function_39.mlir new file mode 100644 index 0000000..b3cc807 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_39.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %1 : !riscv.reg to i1 + %3 = riscv.xor %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %2 : i1 to !riscv.reg + %5 = riscv.czero.eqz %1, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_4.mlir b/benchmarks/XDSL_FUNC/5_function_4.mlir new file mode 100644 index 0000000..25979a0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_4.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.div %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.divu %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.or %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_40.mlir b/benchmarks/XDSL_FUNC/5_function_40.mlir new file mode 100644 index 0000000..c3d15f7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_40.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.remu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.sra %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sra %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_41.mlir b/benchmarks/XDSL_FUNC/5_function_41.mlir new file mode 100644 index 0000000..c526a3d --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_41.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.or %8, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_42.mlir b/benchmarks/XDSL_FUNC/5_function_42.mlir new file mode 100644 index 0000000..0de855a --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_42.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.divu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.xor %8, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sltiu %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_43.mlir b/benchmarks/XDSL_FUNC/5_function_43.mlir new file mode 100644 index 0000000..4fb208a --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_43.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.remu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.and %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_44.mlir b/benchmarks/XDSL_FUNC/5_function_44.mlir new file mode 100644 index 0000000..e92dfa5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_44.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_45.mlir b/benchmarks/XDSL_FUNC/5_function_45.mlir new file mode 100644 index 0000000..ba2e97b --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_45.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.div %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.xor %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.or %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_46.mlir b/benchmarks/XDSL_FUNC/5_function_46.mlir new file mode 100644 index 0000000..3336a8e --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_46.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + func.return %7 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_47.mlir b/benchmarks/XDSL_FUNC/5_function_47.mlir new file mode 100644 index 0000000..3977818 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_47.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.remu %7, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.rem %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xor %9, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.sltiu %10, 1 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_48.mlir b/benchmarks/XDSL_FUNC/5_function_48.mlir new file mode 100644 index 0000000..a5872e1 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_48.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xor %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sra %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_49.mlir b/benchmarks/XDSL_FUNC/5_function_49.mlir new file mode 100644 index 0000000..8488f7d --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_49.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.xor %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.srl %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_5.mlir b/benchmarks/XDSL_FUNC/5_function_5.mlir new file mode 100644 index 0000000..8181461 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_5.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.divu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.divu %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_50.mlir b/benchmarks/XDSL_FUNC/5_function_50.mlir new file mode 100644 index 0000000..fb037db --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_50.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_51.mlir b/benchmarks/XDSL_FUNC/5_function_51.mlir new file mode 100644 index 0000000..f7c61ec --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_51.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.remu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.and %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_52.mlir b/benchmarks/XDSL_FUNC/5_function_52.mlir new file mode 100644 index 0000000..aa7c23c --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_52.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.div %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.or %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_53.mlir b/benchmarks/XDSL_FUNC/5_function_53.mlir new file mode 100644 index 0000000..4204ba8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_53.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xor %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.sltiu %3, 1 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + %13 = builtin.unrealized_conversion_cast %12 : i32 to !riscv.reg + %14 = riscv.sext.w %13 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_54.mlir b/benchmarks/XDSL_FUNC/5_function_54.mlir new file mode 100644 index 0000000..86f77ac --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_54.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.divu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.and %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_55.mlir b/benchmarks/XDSL_FUNC/5_function_55.mlir new file mode 100644 index 0000000..9f6d4c9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_55.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = riscv.remu %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %14 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %15 = riscv.czero.eqz %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.czero.nez %12, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.or %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %19 = riscv.slt %17, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.xori %19, 1 : (!riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i1 + func.return %21 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_56.mlir b/benchmarks/XDSL_FUNC/5_function_56.mlir new file mode 100644 index 0000000..94a8480 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_56.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.div %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.divu %3, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_57.mlir b/benchmarks/XDSL_FUNC/5_function_57.mlir new file mode 100644 index 0000000..6bb6642 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_57.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sra %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %7 : i1 to !riscv.reg + %11 = riscv.czero.eqz %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_58.mlir b/benchmarks/XDSL_FUNC/5_function_58.mlir new file mode 100644 index 0000000..f02e5cc --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_58.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.or %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.xor %3, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i64 + func.return %8 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_59.mlir b/benchmarks/XDSL_FUNC/5_function_59.mlir new file mode 100644 index 0000000..23cca74 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_59.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.divu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.and %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_6.mlir b/benchmarks/XDSL_FUNC/5_function_6.mlir new file mode 100644 index 0000000..f43dce2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_6.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.xor %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.sltiu %11, 1 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_60.mlir b/benchmarks/XDSL_FUNC/5_function_60.mlir new file mode 100644 index 0000000..7950ba0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_60.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.and %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %8 = riscv.czero.eqz %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.sltiu %11, 1 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_61.mlir b/benchmarks/XDSL_FUNC/5_function_61.mlir new file mode 100644 index 0000000..6b3d34d --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_61.mlir @@ -0,0 +1,13 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = riscv.div %3, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.srl %1, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + func.return %6 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_62.mlir b/benchmarks/XDSL_FUNC/5_function_62.mlir new file mode 100644 index 0000000..3cfed66 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_62.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.rem %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_63.mlir b/benchmarks/XDSL_FUNC/5_function_63.mlir new file mode 100644 index 0000000..3c47d66 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_63.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.div %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_64.mlir b/benchmarks/XDSL_FUNC/5_function_64.mlir new file mode 100644 index 0000000..ed59a18 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_64.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.remu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_65.mlir b/benchmarks/XDSL_FUNC/5_function_65.mlir new file mode 100644 index 0000000..8ac235d --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_65.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.rem %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_66.mlir b/benchmarks/XDSL_FUNC/5_function_66.mlir new file mode 100644 index 0000000..bc8ca17 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_66.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.remu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_67.mlir b/benchmarks/XDSL_FUNC/5_function_67.mlir new file mode 100644 index 0000000..3f33a19 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_67.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.divu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.srl %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_68.mlir b/benchmarks/XDSL_FUNC/5_function_68.mlir new file mode 100644 index 0000000..e2f1de9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_68.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.rem %5, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.div %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_69.mlir b/benchmarks/XDSL_FUNC/5_function_69.mlir new file mode 100644 index 0000000..c0a653a --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_69.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.and %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.sltu %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_7.mlir b/benchmarks/XDSL_FUNC/5_function_7.mlir new file mode 100644 index 0000000..e4608a1 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_7.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.div %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_70.mlir b/benchmarks/XDSL_FUNC/5_function_70.mlir new file mode 100644 index 0000000..20b4a47 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_70.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.srl %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_71.mlir b/benchmarks/XDSL_FUNC/5_function_71.mlir new file mode 100644 index 0000000..56c47c1 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_71.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.sext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_72.mlir b/benchmarks/XDSL_FUNC/5_function_72.mlir new file mode 100644 index 0000000..d9796cc --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_72.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.rem %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_73.mlir b/benchmarks/XDSL_FUNC/5_function_73.mlir new file mode 100644 index 0000000..fed69d2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_73.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.divu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.remu %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_74.mlir b/benchmarks/XDSL_FUNC/5_function_74.mlir new file mode 100644 index 0000000..49c090d --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_74.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.and %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.srl %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_75.mlir b/benchmarks/XDSL_FUNC/5_function_75.mlir new file mode 100644 index 0000000..0183a02 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_75.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.and %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.div %7, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.rem %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_76.mlir b/benchmarks/XDSL_FUNC/5_function_76.mlir new file mode 100644 index 0000000..21585f3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_76.mlir @@ -0,0 +1,14 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.divu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sra %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + func.return %7 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_77.mlir b/benchmarks/XDSL_FUNC/5_function_77.mlir new file mode 100644 index 0000000..241f3bc --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_77.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.div %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_78.mlir b/benchmarks/XDSL_FUNC/5_function_78.mlir new file mode 100644 index 0000000..d410c42 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_78.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.rem %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_79.mlir b/benchmarks/XDSL_FUNC/5_function_79.mlir new file mode 100644 index 0000000..fa4457b --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_79.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.sltu %8, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xori %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_8.mlir b/benchmarks/XDSL_FUNC/5_function_8.mlir new file mode 100644 index 0000000..2817ec8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_8.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.divu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.rem %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_80.mlir b/benchmarks/XDSL_FUNC/5_function_80.mlir new file mode 100644 index 0000000..05cb9e6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_80.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sra %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_81.mlir b/benchmarks/XDSL_FUNC/5_function_81.mlir new file mode 100644 index 0000000..f8f91ed --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_81.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.and %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.sltu %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.xori %8, 1 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_82.mlir b/benchmarks/XDSL_FUNC/5_function_82.mlir new file mode 100644 index 0000000..bb45337 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_82.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.srl %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sltu %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xori %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_83.mlir b/benchmarks/XDSL_FUNC/5_function_83.mlir new file mode 100644 index 0000000..611c981 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_83.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.sext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.sra %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.div %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.slt %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.xori %8, 1 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_84.mlir b/benchmarks/XDSL_FUNC/5_function_84.mlir new file mode 100644 index 0000000..677f262 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_84.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.and %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sra %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_85.mlir b/benchmarks/XDSL_FUNC/5_function_85.mlir new file mode 100644 index 0000000..c94b3a1 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_85.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.srl %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.div %3, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_86.mlir b/benchmarks/XDSL_FUNC/5_function_86.mlir new file mode 100644 index 0000000..e8307e7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_86.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %7 = riscv.czero.eqz %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.remu %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %11, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_87.mlir b/benchmarks/XDSL_FUNC/5_function_87.mlir new file mode 100644 index 0000000..8227b9b --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_87.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.div %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %7 = riscv.czero.eqz %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_88.mlir b/benchmarks/XDSL_FUNC/5_function_88.mlir new file mode 100644 index 0000000..6b41c01 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_88.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_89.mlir b/benchmarks/XDSL_FUNC/5_function_89.mlir new file mode 100644 index 0000000..e1454e3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_89.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %11 = riscv.czero.eqz %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.and %13, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_9.mlir b/benchmarks/XDSL_FUNC/5_function_9.mlir new file mode 100644 index 0000000..848c073 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_9.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.xor %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.sra %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.sra %5, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_90.mlir b/benchmarks/XDSL_FUNC/5_function_90.mlir new file mode 100644 index 0000000..11635cc --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_90.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.sra %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.rem %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_91.mlir b/benchmarks/XDSL_FUNC/5_function_91.mlir new file mode 100644 index 0000000..74f73b3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_91.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.and %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.and %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + func.return %8 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_92.mlir b/benchmarks/XDSL_FUNC/5_function_92.mlir new file mode 100644 index 0000000..45fa553 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_92.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.xor %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_93.mlir b/benchmarks/XDSL_FUNC/5_function_93.mlir new file mode 100644 index 0000000..177067a --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_93.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.divu %2, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.slt %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.xori %13, 1 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_94.mlir b/benchmarks/XDSL_FUNC/5_function_94.mlir new file mode 100644 index 0000000..39a455c --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_94.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.srl %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.div %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_95.mlir b/benchmarks/XDSL_FUNC/5_function_95.mlir new file mode 100644 index 0000000..a5640e6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_95.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.srl %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.srl %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_96.mlir b/benchmarks/XDSL_FUNC/5_function_96.mlir new file mode 100644 index 0000000..57fc5a7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_96.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.and %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.rem %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_97.mlir b/benchmarks/XDSL_FUNC/5_function_97.mlir new file mode 100644 index 0000000..558208a --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_97.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = riscv.or %5, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.rem %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i64 + func.return %9 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_98.mlir b/benchmarks/XDSL_FUNC/5_function_98.mlir new file mode 100644 index 0000000..251c08e --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_98.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.srl %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.div %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.and %9, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/5_function_99.mlir b/benchmarks/XDSL_FUNC/5_function_99.mlir new file mode 100644 index 0000000..29aaf43 --- /dev/null +++ b/benchmarks/XDSL_FUNC/5_function_99.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.div %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.divu %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_0.mlir b/benchmarks/XDSL_FUNC/6_function_0.mlir new file mode 100644 index 0000000..e362176 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_0.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.rem %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %11 = riscv.czero.eqz %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.div %7, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.remu %14, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.or %7, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_1.mlir b/benchmarks/XDSL_FUNC/6_function_1.mlir new file mode 100644 index 0000000..5cdfaad --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_1.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.srl %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.xor %8, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_10.mlir b/benchmarks/XDSL_FUNC/6_function_10.mlir new file mode 100644 index 0000000..d4b15b4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_10.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.div %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.srl %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_11.mlir b/benchmarks/XDSL_FUNC/6_function_11.mlir new file mode 100644 index 0000000..edb7f6e --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_11.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.and %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %10 = riscv.czero.eqz %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.srl %7, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_12.mlir b/benchmarks/XDSL_FUNC/6_function_12.mlir new file mode 100644 index 0000000..69694e2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_12.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sra %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.remu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.and %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_13.mlir b/benchmarks/XDSL_FUNC/6_function_13.mlir new file mode 100644 index 0000000..dc551b6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_13.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.rem %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.srl %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.div %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %3, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_14.mlir b/benchmarks/XDSL_FUNC/6_function_14.mlir new file mode 100644 index 0000000..75f83c2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_14.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %10 = riscv.czero.eqz %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.rem %12, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + %15 = builtin.unrealized_conversion_cast %14 : i32 to !riscv.reg + %16 = riscv.sext.w %15 : (!riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_15.mlir b/benchmarks/XDSL_FUNC/6_function_15.mlir new file mode 100644 index 0000000..e940072 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_15.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.rem %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.remu %7, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.remu %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_16.mlir b/benchmarks/XDSL_FUNC/6_function_16.mlir new file mode 100644 index 0000000..9dde4ca --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_16.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.srl %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.remu %5, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.div %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.xor %11, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.sltiu %12, 1 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_17.mlir b/benchmarks/XDSL_FUNC/6_function_17.mlir new file mode 100644 index 0000000..936257f --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_17.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.xor %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xor %9, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_18.mlir b/benchmarks/XDSL_FUNC/6_function_18.mlir new file mode 100644 index 0000000..3bebf22 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_18.mlir @@ -0,0 +1,27 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.sra %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.srl %8, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.xor %16, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.lui 0 : () -> !riscv.reg + %19 = riscv.sltu %18, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = builtin.unrealized_conversion_cast %19 : !riscv.reg to i1 + func.return %20 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_19.mlir b/benchmarks/XDSL_FUNC/6_function_19.mlir new file mode 100644 index 0000000..57f7124 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_19.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %9 = riscv.czero.eqz %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.div %2, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.srl %12, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_2.mlir b/benchmarks/XDSL_FUNC/6_function_2.mlir new file mode 100644 index 0000000..8be234d --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_2.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xor %4, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.rem %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_20.mlir b/benchmarks/XDSL_FUNC/6_function_20.mlir new file mode 100644 index 0000000..c3aa00e --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_20.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.and %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.rem %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_21.mlir b/benchmarks/XDSL_FUNC/6_function_21.mlir new file mode 100644 index 0000000..3d82f7d --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_21.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.div %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xor %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.xor %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %10, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_22.mlir b/benchmarks/XDSL_FUNC/6_function_22.mlir new file mode 100644 index 0000000..7ba533c --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_22.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.rem %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_23.mlir b/benchmarks/XDSL_FUNC/6_function_23.mlir new file mode 100644 index 0000000..2aa983b --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_23.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.srl %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.remu %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.rem %10, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.slt %5, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.xori %12, 1 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_24.mlir b/benchmarks/XDSL_FUNC/6_function_24.mlir new file mode 100644 index 0000000..24f3721 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_24.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %9 = riscv.czero.eqz %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.divu %2, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_25.mlir b/benchmarks/XDSL_FUNC/6_function_25.mlir new file mode 100644 index 0000000..ce5a3e6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_25.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.rem %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.remu %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.sra %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_26.mlir b/benchmarks/XDSL_FUNC/6_function_26.mlir new file mode 100644 index 0000000..83c1175 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_26.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.rem %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_27.mlir b/benchmarks/XDSL_FUNC/6_function_27.mlir new file mode 100644 index 0000000..e9593b6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_27.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.and %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %7, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.sext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_28.mlir b/benchmarks/XDSL_FUNC/6_function_28.mlir new file mode 100644 index 0000000..96890aa --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_28.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.sra %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_29.mlir b/benchmarks/XDSL_FUNC/6_function_29.mlir new file mode 100644 index 0000000..08eee45 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_29.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.or %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_3.mlir b/benchmarks/XDSL_FUNC/6_function_3.mlir new file mode 100644 index 0000000..62d66d5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_3.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.rem %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %12 = riscv.czero.eqz %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i32 + func.return %15 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_30.mlir b/benchmarks/XDSL_FUNC/6_function_30.mlir new file mode 100644 index 0000000..68a28d6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_30.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.srl %4, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.divu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_31.mlir b/benchmarks/XDSL_FUNC/6_function_31.mlir new file mode 100644 index 0000000..a2efa2c --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_31.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = riscv.div %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.sra %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.sltu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xori %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_32.mlir b/benchmarks/XDSL_FUNC/6_function_32.mlir new file mode 100644 index 0000000..d298463 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_32.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.xor %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = riscv.divu %5, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.rem %3, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_33.mlir b/benchmarks/XDSL_FUNC/6_function_33.mlir new file mode 100644 index 0000000..cb14464 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_33.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.or %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_34.mlir b/benchmarks/XDSL_FUNC/6_function_34.mlir new file mode 100644 index 0000000..30c3c24 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_34.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %7 = riscv.czero.eqz %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %12 = riscv.czero.eqz %2, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.rem %9, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i1 + func.return %16 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_35.mlir b/benchmarks/XDSL_FUNC/6_function_35.mlir new file mode 100644 index 0000000..5a957c9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_35.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.divu %1, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.srl %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.div %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_36.mlir b/benchmarks/XDSL_FUNC/6_function_36.mlir new file mode 100644 index 0000000..421278b --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_36.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = riscv.xor %5, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.srl %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_37.mlir b/benchmarks/XDSL_FUNC/6_function_37.mlir new file mode 100644 index 0000000..55c2625 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_37.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.div %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.div %4, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_38.mlir b/benchmarks/XDSL_FUNC/6_function_38.mlir new file mode 100644 index 0000000..e7ba86a --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_38.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.remu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.srl %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.and %8, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_39.mlir b/benchmarks/XDSL_FUNC/6_function_39.mlir new file mode 100644 index 0000000..288e1d0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_39.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.rem %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.divu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_4.mlir b/benchmarks/XDSL_FUNC/6_function_4.mlir new file mode 100644 index 0000000..3670c84 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_4.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.sra %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xor %7, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_40.mlir b/benchmarks/XDSL_FUNC/6_function_40.mlir new file mode 100644 index 0000000..21ab683 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_40.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.rem %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_41.mlir b/benchmarks/XDSL_FUNC/6_function_41.mlir new file mode 100644 index 0000000..71339ec --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_41.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.divu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.remu %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.rem %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + %13 = builtin.unrealized_conversion_cast %12 : i32 to !riscv.reg + %14 = riscv.zext.w %13 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_42.mlir b/benchmarks/XDSL_FUNC/6_function_42.mlir new file mode 100644 index 0000000..537a0dd --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_42.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.remu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.srl %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_43.mlir b/benchmarks/XDSL_FUNC/6_function_43.mlir new file mode 100644 index 0000000..512c18c --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_43.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.rem %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.sra %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.slt %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + %13 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %14 = builtin.unrealized_conversion_cast %12 : i1 to !riscv.reg + %15 = riscv.czero.eqz %10, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.czero.nez %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.or %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i32 + func.return %18 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_44.mlir b/benchmarks/XDSL_FUNC/6_function_44.mlir new file mode 100644 index 0000000..ddc7ac4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_44.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.divu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.srl %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_45.mlir b/benchmarks/XDSL_FUNC/6_function_45.mlir new file mode 100644 index 0000000..6928c2b --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_45.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.slt %10, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_46.mlir b/benchmarks/XDSL_FUNC/6_function_46.mlir new file mode 100644 index 0000000..906fdc3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_46.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.slt %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.remu %7, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.and %9, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %12 = riscv.czero.eqz %8, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i32 + func.return %15 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_47.mlir b/benchmarks/XDSL_FUNC/6_function_47.mlir new file mode 100644 index 0000000..30a0d8f --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_47.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.divu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_48.mlir b/benchmarks/XDSL_FUNC/6_function_48.mlir new file mode 100644 index 0000000..4116de1 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_48.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.rem %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %10 = riscv.czero.eqz %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + %14 = builtin.unrealized_conversion_cast %13 : i1 to !riscv.reg + %15 = riscv.czero.eqz %6, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.czero.nez %12, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.or %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i64 + func.return %18 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_49.mlir b/benchmarks/XDSL_FUNC/6_function_49.mlir new file mode 100644 index 0000000..34254ee --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_49.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.remu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.or %9, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_5.mlir b/benchmarks/XDSL_FUNC/6_function_5.mlir new file mode 100644 index 0000000..3c881bc --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_5.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %1 : !riscv.reg to i1 + %3 = builtin.unrealized_conversion_cast %2 : i1 to !riscv.reg + %4 = riscv.czero.eqz %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.sltu %1, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.xori %10, 1 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_50.mlir b/benchmarks/XDSL_FUNC/6_function_50.mlir new file mode 100644 index 0000000..a6e7737 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_50.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %10 = riscv.czero.eqz %4, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.remu %7, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_51.mlir b/benchmarks/XDSL_FUNC/6_function_51.mlir new file mode 100644 index 0000000..e9ec182 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_51.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.remu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.and %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sltu %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_52.mlir b/benchmarks/XDSL_FUNC/6_function_52.mlir new file mode 100644 index 0000000..beaa57c --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_52.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sra %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_53.mlir b/benchmarks/XDSL_FUNC/6_function_53.mlir new file mode 100644 index 0000000..f6da348 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_53.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.div %1, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.srl %4, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.divu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i64 + func.return %10 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_54.mlir b/benchmarks/XDSL_FUNC/6_function_54.mlir new file mode 100644 index 0000000..f57b577 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_54.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.srl %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.remu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sltu %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xori %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_55.mlir b/benchmarks/XDSL_FUNC/6_function_55.mlir new file mode 100644 index 0000000..6e86cdc --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_55.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.remu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.rem %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_56.mlir b/benchmarks/XDSL_FUNC/6_function_56.mlir new file mode 100644 index 0000000..9c69b6e --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_56.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.and %4, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.xor %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_57.mlir b/benchmarks/XDSL_FUNC/6_function_57.mlir new file mode 100644 index 0000000..dcec939 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_57.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.rem %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_58.mlir b/benchmarks/XDSL_FUNC/6_function_58.mlir new file mode 100644 index 0000000..af3e839 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_58.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %11 = riscv.czero.eqz %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_59.mlir b/benchmarks/XDSL_FUNC/6_function_59.mlir new file mode 100644 index 0000000..0c606fc --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_59.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.divu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_6.mlir b/benchmarks/XDSL_FUNC/6_function_6.mlir new file mode 100644 index 0000000..8af63f0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_6.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.div %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.srl %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_60.mlir b/benchmarks/XDSL_FUNC/6_function_60.mlir new file mode 100644 index 0000000..dae4a59 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_60.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.div %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.srl %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_61.mlir b/benchmarks/XDSL_FUNC/6_function_61.mlir new file mode 100644 index 0000000..36e7306 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_61.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.and %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.srl %4, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_62.mlir b/benchmarks/XDSL_FUNC/6_function_62.mlir new file mode 100644 index 0000000..6bb9fdf --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_62.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.sra %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %9 = riscv.czero.eqz %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.remu %5, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_63.mlir b/benchmarks/XDSL_FUNC/6_function_63.mlir new file mode 100644 index 0000000..e6eef18 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_63.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_64.mlir b/benchmarks/XDSL_FUNC/6_function_64.mlir new file mode 100644 index 0000000..66026f0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_64.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.rem %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.sra %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.rem %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.srl %2, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_65.mlir b/benchmarks/XDSL_FUNC/6_function_65.mlir new file mode 100644 index 0000000..98278c8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_65.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.div %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_66.mlir b/benchmarks/XDSL_FUNC/6_function_66.mlir new file mode 100644 index 0000000..6f7f724 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_66.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.div %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = riscv.div %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_67.mlir b/benchmarks/XDSL_FUNC/6_function_67.mlir new file mode 100644 index 0000000..929380d --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_67.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.and %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.xor %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.rem %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = riscv.sra %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_68.mlir b/benchmarks/XDSL_FUNC/6_function_68.mlir new file mode 100644 index 0000000..5c9d75f --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_68.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.divu %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.srl %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_69.mlir b/benchmarks/XDSL_FUNC/6_function_69.mlir new file mode 100644 index 0000000..f8b5af5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_69.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.sltiu %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.rem %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.div %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %13 = riscv.czero.eqz %7, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + func.return %16 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_7.mlir b/benchmarks/XDSL_FUNC/6_function_7.mlir new file mode 100644 index 0000000..f830df4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_7.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.sra %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_70.mlir b/benchmarks/XDSL_FUNC/6_function_70.mlir new file mode 100644 index 0000000..b16563f --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_70.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.remu %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %7 = riscv.czero.eqz %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sra %3, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.remu %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.and %12, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_71.mlir b/benchmarks/XDSL_FUNC/6_function_71.mlir new file mode 100644 index 0000000..1cb4e1d --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_71.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sra %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.srl %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_72.mlir b/benchmarks/XDSL_FUNC/6_function_72.mlir new file mode 100644 index 0000000..775773d --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_72.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.divu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.div %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.rem %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_73.mlir b/benchmarks/XDSL_FUNC/6_function_73.mlir new file mode 100644 index 0000000..96573be --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_73.mlir @@ -0,0 +1,15 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.or %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + func.return %8 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_74.mlir b/benchmarks/XDSL_FUNC/6_function_74.mlir new file mode 100644 index 0000000..492e132 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_74.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_75.mlir b/benchmarks/XDSL_FUNC/6_function_75.mlir new file mode 100644 index 0000000..bb075d9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_75.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.sra %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_76.mlir b/benchmarks/XDSL_FUNC/6_function_76.mlir new file mode 100644 index 0000000..68080f4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_76.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sltu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = riscv.remu %12, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.div %11, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_77.mlir b/benchmarks/XDSL_FUNC/6_function_77.mlir new file mode 100644 index 0000000..42d6ad4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_77.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.divu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_78.mlir b/benchmarks/XDSL_FUNC/6_function_78.mlir new file mode 100644 index 0000000..ccc6639 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_78.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.divu %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.lui 0 : () -> !riscv.reg + %13 = riscv.sltu %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_79.mlir b/benchmarks/XDSL_FUNC/6_function_79.mlir new file mode 100644 index 0000000..107e860 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_79.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %10 = riscv.czero.eqz %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + %14 = builtin.unrealized_conversion_cast %13 : i32 to !riscv.reg + %15 = riscv.zext.w %14 : (!riscv.reg) -> !riscv.reg + %16 = riscv.slt %7, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i1 + func.return %17 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_8.mlir b/benchmarks/XDSL_FUNC/6_function_8.mlir new file mode 100644 index 0000000..c2b373d --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_8.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.srl %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.div %10, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = riscv.rem %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.slt %9, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_80.mlir b/benchmarks/XDSL_FUNC/6_function_80.mlir new file mode 100644 index 0000000..ba61e01 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_80.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.and %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xor %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.srl %6, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_81.mlir b/benchmarks/XDSL_FUNC/6_function_81.mlir new file mode 100644 index 0000000..1d0ee52 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_81.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sra %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.srl %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + func.return %9 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_82.mlir b/benchmarks/XDSL_FUNC/6_function_82.mlir new file mode 100644 index 0000000..291b98d --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_82.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.sltu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.remu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %11 = riscv.czero.eqz %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %15 = riscv.divu %14, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + func.return %16 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_83.mlir b/benchmarks/XDSL_FUNC/6_function_83.mlir new file mode 100644 index 0000000..b78e58a --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_83.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.slt %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.sra %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.rem %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %12 = riscv.czero.eqz %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.sra %14, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i64 + func.return %16 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_84.mlir b/benchmarks/XDSL_FUNC/6_function_84.mlir new file mode 100644 index 0000000..21ea26c --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_84.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.srl %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.sltu %8, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xori %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = builtin.unrealized_conversion_cast %11 : i1 to !riscv.reg + %14 = riscv.czero.eqz %6, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.czero.nez %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.or %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_85.mlir b/benchmarks/XDSL_FUNC/6_function_85.mlir new file mode 100644 index 0000000..6a559db --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_85.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %9 = riscv.czero.eqz %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_86.mlir b/benchmarks/XDSL_FUNC/6_function_86.mlir new file mode 100644 index 0000000..92df50a --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_86.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.and %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %7 = riscv.czero.eqz %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.xor %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %11, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_87.mlir b/benchmarks/XDSL_FUNC/6_function_87.mlir new file mode 100644 index 0000000..4192e38 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_87.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.or %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %4, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.remu %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_88.mlir b/benchmarks/XDSL_FUNC/6_function_88.mlir new file mode 100644 index 0000000..282756a --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_88.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %5, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.slt %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + %10 = builtin.unrealized_conversion_cast %9 : i1 to !riscv.reg + %11 = riscv.czero.eqz %6, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %5, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %15 = riscv.rem %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.xor %15, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.sltiu %16, 1 : (!riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i1 + func.return %18 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_89.mlir b/benchmarks/XDSL_FUNC/6_function_89.mlir new file mode 100644 index 0000000..9616160 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_89.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.rem %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.and %6, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %7, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_9.mlir b/benchmarks/XDSL_FUNC/6_function_9.mlir new file mode 100644 index 0000000..779e579 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_9.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i1, %arg6_3: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %3 = riscv.czero.eqz %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %8 = riscv.czero.eqz %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.zext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_90.mlir b/benchmarks/XDSL_FUNC/6_function_90.mlir new file mode 100644 index 0000000..00c96ba --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_90.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %6 = riscv.czero.eqz %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.and %9, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %10, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.sltu %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_91.mlir b/benchmarks/XDSL_FUNC/6_function_91.mlir new file mode 100644 index 0000000..96848bf --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_91.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.div %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.sra %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.srl %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_92.mlir b/benchmarks/XDSL_FUNC/6_function_92.mlir new file mode 100644 index 0000000..0ca1a94 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_92.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.rem %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %9 = riscv.czero.eqz %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + %13 = builtin.unrealized_conversion_cast %12 : i32 to !riscv.reg + %14 = riscv.zext.w %13 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i32 + func.return %15 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_93.mlir b/benchmarks/XDSL_FUNC/6_function_93.mlir new file mode 100644 index 0000000..862dc62 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_93.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.rem %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.rem %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.srl %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_94.mlir b/benchmarks/XDSL_FUNC/6_function_94.mlir new file mode 100644 index 0000000..776f17e --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_94.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.remu %11, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.divu %13, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.div %5, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i64 + func.return %16 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_95.mlir b/benchmarks/XDSL_FUNC/6_function_95.mlir new file mode 100644 index 0000000..f9c9cc9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_95.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.remu %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_96.mlir b/benchmarks/XDSL_FUNC/6_function_96.mlir new file mode 100644 index 0000000..9f1c7d2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_96.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %10 = riscv.czero.eqz %4, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_97.mlir b/benchmarks/XDSL_FUNC/6_function_97.mlir new file mode 100644 index 0000000..04f83c7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_97.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.and %8, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_98.mlir b/benchmarks/XDSL_FUNC/6_function_98.mlir new file mode 100644 index 0000000..75f8fe9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_98.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.lui 0 : () -> !riscv.reg + %13 = riscv.sltu %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/6_function_99.mlir b/benchmarks/XDSL_FUNC/6_function_99.mlir new file mode 100644 index 0000000..4aeedeb --- /dev/null +++ b/benchmarks/XDSL_FUNC/6_function_99.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.sltiu %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %13 = riscv.remu %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %15 = riscv.and %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i1 + func.return %16 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_0.mlir b/benchmarks/XDSL_FUNC/7_function_0.mlir new file mode 100644 index 0000000..48e2361 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_0.mlir @@ -0,0 +1,27 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %7 : i1 to !riscv.reg + %10 = riscv.czero.eqz %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %5, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %12, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %15 = builtin.unrealized_conversion_cast %7 : i1 to !riscv.reg + %16 = riscv.czero.eqz %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.czero.nez %5, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.or %16, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.div %13, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = builtin.unrealized_conversion_cast %19 : !riscv.reg to i32 + func.return %20 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_1.mlir b/benchmarks/XDSL_FUNC/7_function_1.mlir new file mode 100644 index 0000000..36581cf --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_1.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.div %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.srl %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_10.mlir b/benchmarks/XDSL_FUNC/7_function_10.mlir new file mode 100644 index 0000000..bcc5207 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_10.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.srl %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.divu %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.rem %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.remu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.remu %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.slt %8, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xori %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_11.mlir b/benchmarks/XDSL_FUNC/7_function_11.mlir new file mode 100644 index 0000000..7c710a1 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_11.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.xor %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.srl %4, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.div %3, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.rem %1, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_12.mlir b/benchmarks/XDSL_FUNC/7_function_12.mlir new file mode 100644 index 0000000..0458e58 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_12.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.sra %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.or %3, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.div %3, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.divu %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.slt %10, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.xori %11, 1 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_13.mlir b/benchmarks/XDSL_FUNC/7_function_13.mlir new file mode 100644 index 0000000..f789b65 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_13.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.sltu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %8 : i1 to !riscv.reg + %11 = riscv.czero.eqz %4, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + %15 = builtin.unrealized_conversion_cast %14 : i32 to !riscv.reg + %16 = riscv.sext.w %15 : (!riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i32 + func.return %17 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_14.mlir b/benchmarks/XDSL_FUNC/7_function_14.mlir new file mode 100644 index 0000000..5dbbf16 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_14.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i1) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.and %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %8 = riscv.czero.eqz %1, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %1, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %10, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_15.mlir b/benchmarks/XDSL_FUNC/7_function_15.mlir new file mode 100644 index 0000000..e5f84be --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_15.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.sltu %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.xori %3, 1 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.rem %6, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.div %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.srl %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %13 = riscv.czero.eqz %9, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + func.return %16 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_16.mlir b/benchmarks/XDSL_FUNC/7_function_16.mlir new file mode 100644 index 0000000..e79966f --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_16.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.div %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.sra %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.sext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_17.mlir b/benchmarks/XDSL_FUNC/7_function_17.mlir new file mode 100644 index 0000000..66e31c8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_17.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.and %6, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.xor %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.xor %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.xor %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.lui 0 : () -> !riscv.reg + %15 = riscv.sltu %14, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i1 + func.return %16 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_18.mlir b/benchmarks/XDSL_FUNC/7_function_18.mlir new file mode 100644 index 0000000..bd2a69e --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_18.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.divu %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.div %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.sra %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.remu %9, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.and %10, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_19.mlir b/benchmarks/XDSL_FUNC/7_function_19.mlir new file mode 100644 index 0000000..388a3fd --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_19.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.remu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xor %6, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xor %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.remu %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_2.mlir b/benchmarks/XDSL_FUNC/7_function_2.mlir new file mode 100644 index 0000000..7129ed5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_2.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.sra %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.remu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.div %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.srl %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_20.mlir b/benchmarks/XDSL_FUNC/7_function_20.mlir new file mode 100644 index 0000000..3467cdb --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_20.mlir @@ -0,0 +1,26 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.slt %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xori %4, 1 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.remu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.rem %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.div %2, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %18 = riscv.srl %17, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = builtin.unrealized_conversion_cast %18 : !riscv.reg to i64 + func.return %19 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_21.mlir b/benchmarks/XDSL_FUNC/7_function_21.mlir new file mode 100644 index 0000000..15489f1 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_21.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.sltu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %8 : i1 to !riscv.reg + %11 = riscv.czero.eqz %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %4, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.and %13, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.xor %14, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.divu %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_22.mlir b/benchmarks/XDSL_FUNC/7_function_22.mlir new file mode 100644 index 0000000..671a005 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_22.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.srl %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_23.mlir b/benchmarks/XDSL_FUNC/7_function_23.mlir new file mode 100644 index 0000000..5b5d7a7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_23.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.div %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_24.mlir b/benchmarks/XDSL_FUNC/7_function_24.mlir new file mode 100644 index 0000000..95b2f9a --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_24.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.rem %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.remu %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_25.mlir b/benchmarks/XDSL_FUNC/7_function_25.mlir new file mode 100644 index 0000000..e6ada1c --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_25.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %6 = riscv.czero.eqz %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + %10 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = riscv.remu %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %9 : i1 to !riscv.reg + %14 = riscv.czero.eqz %11, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.czero.nez %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.or %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_26.mlir b/benchmarks/XDSL_FUNC/7_function_26.mlir new file mode 100644 index 0000000..6007efd --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_26.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xor %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.remu %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.div %7, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + func.return %10 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_27.mlir b/benchmarks/XDSL_FUNC/7_function_27.mlir new file mode 100644 index 0000000..3f3ca1e --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_27.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = riscv.xor %3, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %7 = riscv.czero.eqz %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.slt %4, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = builtin.unrealized_conversion_cast %11 : i1 to !riscv.reg + %14 = riscv.czero.eqz %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.czero.nez %3, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.or %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i32 + func.return %17 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_28.mlir b/benchmarks/XDSL_FUNC/7_function_28.mlir new file mode 100644 index 0000000..0df40f3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_28.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %1 : !riscv.reg to i32 + %3 = builtin.unrealized_conversion_cast %2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.rem %4, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.rem %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.divu %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_29.mlir b/benchmarks/XDSL_FUNC/7_function_29.mlir new file mode 100644 index 0000000..247667b --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_29.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.xor %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = riscv.sra %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.and %13, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %16 = riscv.and %15, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_3.mlir b/benchmarks/XDSL_FUNC/7_function_3.mlir new file mode 100644 index 0000000..ed2de78 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_3.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.rem %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.sra %9, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.divu %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_30.mlir b/benchmarks/XDSL_FUNC/7_function_30.mlir new file mode 100644 index 0000000..9683121 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_30.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.srl %3, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.and %9, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.remu %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_31.mlir b/benchmarks/XDSL_FUNC/7_function_31.mlir new file mode 100644 index 0000000..2289290 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_31.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.sext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = riscv.and %8, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %14 = riscv.sltu %13, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_32.mlir b/benchmarks/XDSL_FUNC/7_function_32.mlir new file mode 100644 index 0000000..c90967f --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_32.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.sra %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.xor %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.xor %11, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_33.mlir b/benchmarks/XDSL_FUNC/7_function_33.mlir new file mode 100644 index 0000000..d4e3782 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_33.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.rem %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.slt %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_34.mlir b/benchmarks/XDSL_FUNC/7_function_34.mlir new file mode 100644 index 0000000..e537c58 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_34.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %8 = riscv.czero.eqz %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.srl %10, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + %13 = builtin.unrealized_conversion_cast %12 : i32 to !riscv.reg + %14 = riscv.sext.w %13 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_35.mlir b/benchmarks/XDSL_FUNC/7_function_35.mlir new file mode 100644 index 0000000..c662c2d --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_35.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = riscv.sra %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.srl %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.and %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_36.mlir b/benchmarks/XDSL_FUNC/7_function_36.mlir new file mode 100644 index 0000000..e9013ef --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_36.mlir @@ -0,0 +1,26 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.sltu %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xori %9, 1 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + %12 = riscv.or %7, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %11 : i1 to !riscv.reg + %14 = riscv.czero.eqz %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.czero.nez %2, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.or %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.divu %16, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.srl %7, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = builtin.unrealized_conversion_cast %18 : !riscv.reg to i64 + func.return %19 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_37.mlir b/benchmarks/XDSL_FUNC/7_function_37.mlir new file mode 100644 index 0000000..ee5a559 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_37.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.srl %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.rem %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.and %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %14 = riscv.xor %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i32 + func.return %15 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_38.mlir b/benchmarks/XDSL_FUNC/7_function_38.mlir new file mode 100644 index 0000000..8a7f032 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_38.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.remu %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.sltiu %7, 1 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + %10 = builtin.unrealized_conversion_cast %9 : i1 to !riscv.reg + %11 = riscv.czero.eqz %2, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %4, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %15 = riscv.or %14, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + func.return %16 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_39.mlir b/benchmarks/XDSL_FUNC/7_function_39.mlir new file mode 100644 index 0000000..645b906 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_39.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.remu %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_4.mlir b/benchmarks/XDSL_FUNC/7_function_4.mlir new file mode 100644 index 0000000..d5bccab --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_4.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.srl %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.and %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.sra %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.and %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.slt %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_40.mlir b/benchmarks/XDSL_FUNC/7_function_40.mlir new file mode 100644 index 0000000..6641192 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_40.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.rem %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.srl %9, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.sra %5, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_41.mlir b/benchmarks/XDSL_FUNC/7_function_41.mlir new file mode 100644 index 0000000..49ed407 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_41.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.srl %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.srl %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.and %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.divu %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_42.mlir b/benchmarks/XDSL_FUNC/7_function_42.mlir new file mode 100644 index 0000000..0734b21 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_42.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.sra %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sra %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.xor %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sra %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.zext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_43.mlir b/benchmarks/XDSL_FUNC/7_function_43.mlir new file mode 100644 index 0000000..956ae4e --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_43.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %10 = riscv.czero.eqz %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + %14 = builtin.unrealized_conversion_cast %13 : i32 to !riscv.reg + %15 = riscv.sext.w %14 : (!riscv.reg) -> !riscv.reg + %16 = riscv.remu %7, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i32 + func.return %17 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_44.mlir b/benchmarks/XDSL_FUNC/7_function_44.mlir new file mode 100644 index 0000000..471fbcb --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_44.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.remu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %7 = riscv.czero.eqz %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xor %4, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.div %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.xor %11, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_45.mlir b/benchmarks/XDSL_FUNC/7_function_45.mlir new file mode 100644 index 0000000..9ec5b90 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_45.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.and %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.zext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_46.mlir b/benchmarks/XDSL_FUNC/7_function_46.mlir new file mode 100644 index 0000000..e1ecc7f --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_46.mlir @@ -0,0 +1,27 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.sra %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.remu %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.sext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %15 = riscv.sra %14, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %17 = riscv.czero.eqz %7, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.czero.nez %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.or %17, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = builtin.unrealized_conversion_cast %19 : !riscv.reg to i64 + func.return %20 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_47.mlir b/benchmarks/XDSL_FUNC/7_function_47.mlir new file mode 100644 index 0000000..ee22907 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_47.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.sra %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xor %6, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %10 = riscv.czero.eqz %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %3, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.xor %12, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_48.mlir b/benchmarks/XDSL_FUNC/7_function_48.mlir new file mode 100644 index 0000000..a5d1747 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_48.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.rem %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xor %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_49.mlir b/benchmarks/XDSL_FUNC/7_function_49.mlir new file mode 100644 index 0000000..1f7f422 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_49.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sra %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.remu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.srl %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_5.mlir b/benchmarks/XDSL_FUNC/7_function_5.mlir new file mode 100644 index 0000000..7ee74b5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_5.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = riscv.and %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_50.mlir b/benchmarks/XDSL_FUNC/7_function_50.mlir new file mode 100644 index 0000000..3f6306e --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_50.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.divu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.div %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.divu %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.srl %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_51.mlir b/benchmarks/XDSL_FUNC/7_function_51.mlir new file mode 100644 index 0000000..e98b2f8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_51.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %11 = riscv.czero.eqz %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.divu %13, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %16 = riscv.xor %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %18 = riscv.divu %17, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.sltu %2, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.xori %19, 1 : (!riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i1 + func.return %21 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_52.mlir b/benchmarks/XDSL_FUNC/7_function_52.mlir new file mode 100644 index 0000000..787e126 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_52.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.rem %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.and %9, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.divu %3, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_53.mlir b/benchmarks/XDSL_FUNC/7_function_53.mlir new file mode 100644 index 0000000..ca9ce80 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_53.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.rem %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.remu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.divu %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %10, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_54.mlir b/benchmarks/XDSL_FUNC/7_function_54.mlir new file mode 100644 index 0000000..08cc98d --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_54.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.srl %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.remu %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_55.mlir b/benchmarks/XDSL_FUNC/7_function_55.mlir new file mode 100644 index 0000000..c7f8745 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_55.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_56.mlir b/benchmarks/XDSL_FUNC/7_function_56.mlir new file mode 100644 index 0000000..ea722b9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_56.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.and %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.or %9, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_57.mlir b/benchmarks/XDSL_FUNC/7_function_57.mlir new file mode 100644 index 0000000..51ab9b4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_57.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.or %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.and %7, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.sext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_58.mlir b/benchmarks/XDSL_FUNC/7_function_58.mlir new file mode 100644 index 0000000..fa53c3a --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_58.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.remu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.rem %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.rem %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.and %9, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.slt %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.xori %11, 1 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_59.mlir b/benchmarks/XDSL_FUNC/7_function_59.mlir new file mode 100644 index 0000000..bd44491 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_59.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.srl %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.sra %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.and %8, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.zext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_6.mlir b/benchmarks/XDSL_FUNC/7_function_6.mlir new file mode 100644 index 0000000..a5f664f --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_6.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %4, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_60.mlir b/benchmarks/XDSL_FUNC/7_function_60.mlir new file mode 100644 index 0000000..3a168de --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_60.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.or %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.div %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.xor %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = riscv.rem %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_61.mlir b/benchmarks/XDSL_FUNC/7_function_61.mlir new file mode 100644 index 0000000..aaf85cd --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_61.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.slt %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %13 = riscv.czero.eqz %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.sltu %15, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.xori %16, 1 : (!riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i1 + func.return %18 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_62.mlir b/benchmarks/XDSL_FUNC/7_function_62.mlir new file mode 100644 index 0000000..9b1e908 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_62.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %6, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.xor %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.remu %9, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_63.mlir b/benchmarks/XDSL_FUNC/7_function_63.mlir new file mode 100644 index 0000000..7bc85aa --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_63.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.divu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.div %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_64.mlir b/benchmarks/XDSL_FUNC/7_function_64.mlir new file mode 100644 index 0000000..ac90dd8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_64.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.sra %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.xor %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_65.mlir b/benchmarks/XDSL_FUNC/7_function_65.mlir new file mode 100644 index 0000000..fdbb981 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_65.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.and %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.sra %3, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.rem %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_66.mlir b/benchmarks/XDSL_FUNC/7_function_66.mlir new file mode 100644 index 0000000..4fac7c5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_66.mlir @@ -0,0 +1,26 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.remu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sltu %5, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xori %6, 1 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.divu %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %13 = riscv.remu %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %15 = builtin.unrealized_conversion_cast %8 : i1 to !riscv.reg + %16 = riscv.czero.eqz %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.czero.nez %13, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.or %16, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = builtin.unrealized_conversion_cast %18 : !riscv.reg to i64 + func.return %19 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_67.mlir b/benchmarks/XDSL_FUNC/7_function_67.mlir new file mode 100644 index 0000000..196e229 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_67.mlir @@ -0,0 +1,16 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xor %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.remu %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.divu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.sra %7, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + func.return %9 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_68.mlir b/benchmarks/XDSL_FUNC/7_function_68.mlir new file mode 100644 index 0000000..9fe63ea --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_68.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %7 = riscv.czero.eqz %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.rem %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.and %11, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + %14 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %16 = riscv.xor %15, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %13 : i1 to !riscv.reg + %18 = riscv.czero.eqz %12, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.czero.nez %16, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.or %18, %19 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i64 + func.return %21 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_69.mlir b/benchmarks/XDSL_FUNC/7_function_69.mlir new file mode 100644 index 0000000..48663a3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_69.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.and %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.sext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %14 = riscv.or %13, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %14, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i64 + func.return %16 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_7.mlir b/benchmarks/XDSL_FUNC/7_function_7.mlir new file mode 100644 index 0000000..cf51d01 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_7.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.srl %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.remu %6, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.or %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.sltu %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_70.mlir b/benchmarks/XDSL_FUNC/7_function_70.mlir new file mode 100644 index 0000000..c85a5fc --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_70.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.div %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.rem %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_71.mlir b/benchmarks/XDSL_FUNC/7_function_71.mlir new file mode 100644 index 0000000..7649ede --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_71.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.rem %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.divu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.or %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xor %9, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %13 = riscv.xor %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.rem %10, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_72.mlir b/benchmarks/XDSL_FUNC/7_function_72.mlir new file mode 100644 index 0000000..f51cc01 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_72.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.div %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.divu %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.rem %9, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_73.mlir b/benchmarks/XDSL_FUNC/7_function_73.mlir new file mode 100644 index 0000000..4446588 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_73.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.and %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_74.mlir b/benchmarks/XDSL_FUNC/7_function_74.mlir new file mode 100644 index 0000000..fdd9b29 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_74.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.srl %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xor %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.xor %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.xor %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_75.mlir b/benchmarks/XDSL_FUNC/7_function_75.mlir new file mode 100644 index 0000000..f022ebf --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_75.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.divu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.rem %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.xor %8, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %12 = riscv.czero.eqz %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i32 + func.return %15 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_76.mlir b/benchmarks/XDSL_FUNC/7_function_76.mlir new file mode 100644 index 0000000..93ca629 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_76.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.divu %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.or %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %10 = riscv.czero.eqz %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %12, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_77.mlir b/benchmarks/XDSL_FUNC/7_function_77.mlir new file mode 100644 index 0000000..038cae3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_77.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.and %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %10 = riscv.czero.eqz %4, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.divu %12, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.divu %8, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_78.mlir b/benchmarks/XDSL_FUNC/7_function_78.mlir new file mode 100644 index 0000000..e1a9ef6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_78.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %4 = riscv.sext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.divu %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.or %8, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sltu %9, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.xori %10, 1 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_79.mlir b/benchmarks/XDSL_FUNC/7_function_79.mlir new file mode 100644 index 0000000..1cc84dc --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_79.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.rem %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_8.mlir b/benchmarks/XDSL_FUNC/7_function_8.mlir new file mode 100644 index 0000000..5356321 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_8.mlir @@ -0,0 +1,31 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %17 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %18 = riscv.or %17, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.remu %10, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.or %18, %19 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = riscv.xor %20, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = riscv.lui 0 : () -> !riscv.reg + %23 = riscv.sltu %22, %21 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = builtin.unrealized_conversion_cast %23 : !riscv.reg to i1 + func.return %24 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_80.mlir b/benchmarks/XDSL_FUNC/7_function_80.mlir new file mode 100644 index 0000000..3ad1105 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_80.mlir @@ -0,0 +1,32 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.sltiu %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.divu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %10 = riscv.czero.eqz %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %15 = riscv.or %14, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %17 = riscv.sltu %16, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i1 + %19 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %20 = builtin.unrealized_conversion_cast %18 : i1 to !riscv.reg + %21 = riscv.czero.eqz %12, %20 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = riscv.czero.nez %19, %20 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = riscv.or %21, %22 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = riscv.sra %12, %23 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %25 = builtin.unrealized_conversion_cast %24 : !riscv.reg to i64 + func.return %25 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_81.mlir b/benchmarks/XDSL_FUNC/7_function_81.mlir new file mode 100644 index 0000000..7bc19ab --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_81.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.srl %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.srl %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.xor %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.rem %3, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %9, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i64 + func.return %11 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_82.mlir b/benchmarks/XDSL_FUNC/7_function_82.mlir new file mode 100644 index 0000000..aa39ea5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_82.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.sra %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_83.mlir b/benchmarks/XDSL_FUNC/7_function_83.mlir new file mode 100644 index 0000000..d4d5ab2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_83.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.div %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_84.mlir b/benchmarks/XDSL_FUNC/7_function_84.mlir new file mode 100644 index 0000000..9119c10 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_84.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.and %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.xor %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.and %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.rem %9, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_85.mlir b/benchmarks/XDSL_FUNC/7_function_85.mlir new file mode 100644 index 0000000..a84d0cd --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_85.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xor %7, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.and %8, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.xor %10, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.remu %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_86.mlir b/benchmarks/XDSL_FUNC/7_function_86.mlir new file mode 100644 index 0000000..4a25854 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_86.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.or %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.rem %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.divu %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_87.mlir b/benchmarks/XDSL_FUNC/7_function_87.mlir new file mode 100644 index 0000000..17c19d9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_87.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.remu %5, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.divu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.xor %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.srl %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.slt %8, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_88.mlir b/benchmarks/XDSL_FUNC/7_function_88.mlir new file mode 100644 index 0000000..234a8d9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_88.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.rem %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %8, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.zext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_89.mlir b/benchmarks/XDSL_FUNC/7_function_89.mlir new file mode 100644 index 0000000..b405ae2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_89.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.sext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.divu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.divu %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_9.mlir b/benchmarks/XDSL_FUNC/7_function_9.mlir new file mode 100644 index 0000000..deca47f --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_9.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.remu %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.srl %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = riscv.remu %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_90.mlir b/benchmarks/XDSL_FUNC/7_function_90.mlir new file mode 100644 index 0000000..a9b998d --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_90.mlir @@ -0,0 +1,17 @@ +builtin.module { + func.func @func0(%arg6: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + func.return %10 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_91.mlir b/benchmarks/XDSL_FUNC/7_function_91.mlir new file mode 100644 index 0000000..e5d2d96 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_91.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.rem %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.rem %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.remu %10, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.xor %11, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.lui 0 : () -> !riscv.reg + %14 = riscv.sltu %13, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_92.mlir b/benchmarks/XDSL_FUNC/7_function_92.mlir new file mode 100644 index 0000000..d349033 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_92.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.and %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xor %6, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %8 : i1 to !riscv.reg + %11 = riscv.czero.eqz %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %3, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_93.mlir b/benchmarks/XDSL_FUNC/7_function_93.mlir new file mode 100644 index 0000000..b490f1b --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_93.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.divu %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.xor %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.divu %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_94.mlir b/benchmarks/XDSL_FUNC/7_function_94.mlir new file mode 100644 index 0000000..617b559 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_94.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.rem %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.div %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.rem %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.srl %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.div %2, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_95.mlir b/benchmarks/XDSL_FUNC/7_function_95.mlir new file mode 100644 index 0000000..7fda1b9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_95.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.sra %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %4, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_96.mlir b/benchmarks/XDSL_FUNC/7_function_96.mlir new file mode 100644 index 0000000..58c52af --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_96.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sra %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.div %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.xor %9, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_97.mlir b/benchmarks/XDSL_FUNC/7_function_97.mlir new file mode 100644 index 0000000..9fe7497 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_97.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.srl %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.xor %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.sra %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i64 + func.return %12 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_98.mlir b/benchmarks/XDSL_FUNC/7_function_98.mlir new file mode 100644 index 0000000..584933f --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_98.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.slt %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.sra %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %11 = riscv.czero.eqz %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %15 = riscv.and %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.sra %15, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/7_function_99.mlir b/benchmarks/XDSL_FUNC/7_function_99.mlir new file mode 100644 index 0000000..7319388 --- /dev/null +++ b/benchmarks/XDSL_FUNC/7_function_99.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + %8 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %7 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i64 + func.return %16 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_0.mlir b/benchmarks/XDSL_FUNC/8_function_0.mlir new file mode 100644 index 0000000..bfca688 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_0.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.sra %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.or %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.divu %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.and %12, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_1.mlir b/benchmarks/XDSL_FUNC/8_function_1.mlir new file mode 100644 index 0000000..de52112 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_1.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i32, %arg6_2: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %1 : !riscv.reg to i32 + %3 = builtin.unrealized_conversion_cast %2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.rem %1, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %9 = riscv.czero.eqz %1, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.rem %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.rem %5, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_10.mlir b/benchmarks/XDSL_FUNC/8_function_10.mlir new file mode 100644 index 0000000..b8cf0ad --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_10.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.srl %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.slt %9, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + %12 = builtin.unrealized_conversion_cast %11 : i1 to !riscv.reg + %13 = riscv.czero.eqz %2, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %6, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %17 = builtin.unrealized_conversion_cast %7 : i1 to !riscv.reg + %18 = riscv.czero.eqz %15, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.czero.nez %16, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.or %18, %19 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i64 + func.return %21 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_11.mlir b/benchmarks/XDSL_FUNC/8_function_11.mlir new file mode 100644 index 0000000..0282554 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_11.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.sra %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.remu %7, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.div %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = riscv.and %11, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_12.mlir b/benchmarks/XDSL_FUNC/8_function_12.mlir new file mode 100644 index 0000000..f7cbc34 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_12.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.srl %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.and %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.div %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.srl %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_13.mlir b/benchmarks/XDSL_FUNC/8_function_13.mlir new file mode 100644 index 0000000..a4a69a9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_13.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.or %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.and %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xor %9, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.zext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_14.mlir b/benchmarks/XDSL_FUNC/8_function_14.mlir new file mode 100644 index 0000000..aa5ab0f --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_14.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32, %arg6_3: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.sra %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.divu %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %11 = riscv.czero.eqz %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.srl %13, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.remu %7, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.sltu %15, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.xori %16, 1 : (!riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i1 + func.return %18 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_15.mlir b/benchmarks/XDSL_FUNC/8_function_15.mlir new file mode 100644 index 0000000..96e8754 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_15.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.remu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.sltu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.div %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %7 : i1 to !riscv.reg + %12 = riscv.czero.eqz %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %16 = riscv.zext.w %15 : (!riscv.reg) -> !riscv.reg + %17 = riscv.and %16, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i32 + func.return %18 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_16.mlir b/benchmarks/XDSL_FUNC/8_function_16.mlir new file mode 100644 index 0000000..6af3311 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_16.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.or %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.rem %1, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.remu %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.remu %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.div %3, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_17.mlir b/benchmarks/XDSL_FUNC/8_function_17.mlir new file mode 100644 index 0000000..a873f46 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_17.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.remu %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.remu %4, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.div %6, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.and %7, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.xor %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.sra %3, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_18.mlir b/benchmarks/XDSL_FUNC/8_function_18.mlir new file mode 100644 index 0000000..00d4d86 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_18.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.srl %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.remu %3, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.srl %3, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.zext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = riscv.sltu %8, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_19.mlir b/benchmarks/XDSL_FUNC/8_function_19.mlir new file mode 100644 index 0000000..9e4362a --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_19.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.remu %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %9 = riscv.czero.eqz %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + %13 = builtin.unrealized_conversion_cast %12 : i32 to !riscv.reg + %14 = riscv.sext.w %13 : (!riscv.reg) -> !riscv.reg + %15 = riscv.sltu %11, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i1 + func.return %16 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_2.mlir b/benchmarks/XDSL_FUNC/8_function_2.mlir new file mode 100644 index 0000000..d1b9f2a --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_2.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = riscv.and %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %4 = riscv.sext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.remu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.srl %2, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.and %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.remu %10, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.remu %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_20.mlir b/benchmarks/XDSL_FUNC/8_function_20.mlir new file mode 100644 index 0000000..e760b4f --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_20.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.srl %7, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.divu %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.and %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_21.mlir b/benchmarks/XDSL_FUNC/8_function_21.mlir new file mode 100644 index 0000000..9467b36 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_21.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.rem %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.divu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.and %8, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.sext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_22.mlir b/benchmarks/XDSL_FUNC/8_function_22.mlir new file mode 100644 index 0000000..4ae0e3a --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_22.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.sra %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = riscv.remu %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.srl %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %14 = riscv.czero.eqz %11, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.czero.nez %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.or %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %18 = riscv.czero.eqz %8, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.czero.nez %16, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.or %18, %19 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i32 + func.return %21 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_23.mlir b/benchmarks/XDSL_FUNC/8_function_23.mlir new file mode 100644 index 0000000..7a13095 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_23.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.div %6, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.rem %5, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_24.mlir b/benchmarks/XDSL_FUNC/8_function_24.mlir new file mode 100644 index 0000000..3b09189 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_24.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.divu %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.srl %6, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.slt %13, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.xori %14, 1 : (!riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i1 + func.return %16 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_25.mlir b/benchmarks/XDSL_FUNC/8_function_25.mlir new file mode 100644 index 0000000..e8c879e --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_25.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64, %arg6_3: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.div %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.srl %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.srl %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + %13 = builtin.unrealized_conversion_cast %12 : i32 to !riscv.reg + %14 = riscv.sext.w %13 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_26.mlir b/benchmarks/XDSL_FUNC/8_function_26.mlir new file mode 100644 index 0000000..3e3ed1d --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_26.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %4 = riscv.sext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.divu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.and %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.sra %8, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.divu %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.sra %2, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.div %11, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_27.mlir b/benchmarks/XDSL_FUNC/8_function_27.mlir new file mode 100644 index 0000000..889abf4 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_27.mlir @@ -0,0 +1,26 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.sra %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.and %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = riscv.srl %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.sra %9, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + %15 = builtin.unrealized_conversion_cast %14 : i32 to !riscv.reg + %16 = riscv.sext.w %15 : (!riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %18 = riscv.remu %17, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = builtin.unrealized_conversion_cast %18 : !riscv.reg to i64 + func.return %19 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_28.mlir b/benchmarks/XDSL_FUNC/8_function_28.mlir new file mode 100644 index 0000000..e095135 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_28.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.sra %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + %14 = builtin.unrealized_conversion_cast %13 : i32 to !riscv.reg + %15 = riscv.zext.w %14 : (!riscv.reg) -> !riscv.reg + %16 = riscv.sltu %11, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.xori %16, 1 : (!riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i1 + func.return %18 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_29.mlir b/benchmarks/XDSL_FUNC/8_function_29.mlir new file mode 100644 index 0000000..c9ffaf9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_29.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.rem %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xor %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.xor %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %11 = riscv.czero.eqz %2, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.rem %6, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %16 = riscv.srl %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i32 + func.return %17 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_3.mlir b/benchmarks/XDSL_FUNC/8_function_3.mlir new file mode 100644 index 0000000..e87a34a --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_3.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.sra %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.remu %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_30.mlir b/benchmarks/XDSL_FUNC/8_function_30.mlir new file mode 100644 index 0000000..1b75694 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_30.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.and %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.sra %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.and %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.srl %5, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.sra %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.slt %5, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_31.mlir b/benchmarks/XDSL_FUNC/8_function_31.mlir new file mode 100644 index 0000000..f161021 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_31.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.srl %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sltu %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + %12 = riscv.rem %7, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %14 = builtin.unrealized_conversion_cast %11 : i1 to !riscv.reg + %15 = riscv.czero.eqz %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.czero.nez %12, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.or %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i64 + func.return %18 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_32.mlir b/benchmarks/XDSL_FUNC/8_function_32.mlir new file mode 100644 index 0000000..d9d164e --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_32.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i1, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.and %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.srl %7, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.srl %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.sext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %15 = riscv.czero.eqz %12, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.czero.nez %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.or %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i32 + func.return %18 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_33.mlir b/benchmarks/XDSL_FUNC/8_function_33.mlir new file mode 100644 index 0000000..0ddd889 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_33.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.remu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.srl %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i1 + %8 = builtin.unrealized_conversion_cast %7 : i1 to !riscv.reg + %9 = riscv.czero.eqz %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.remu %5, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.and %12, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_34.mlir b/benchmarks/XDSL_FUNC/8_function_34.mlir new file mode 100644 index 0000000..09585b3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_34.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.div %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.div %8, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.rem %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + func.return %11 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_35.mlir b/benchmarks/XDSL_FUNC/8_function_35.mlir new file mode 100644 index 0000000..30a267b --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_35.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.div %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.srl %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.sext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_36.mlir b/benchmarks/XDSL_FUNC/8_function_36.mlir new file mode 100644 index 0000000..758da6a --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_36.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.remu %4, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.xor %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.rem %7, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.div %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %12 = riscv.czero.eqz %2, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i32 + func.return %15 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_37.mlir b/benchmarks/XDSL_FUNC/8_function_37.mlir new file mode 100644 index 0000000..8c3f9ba --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_37.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.divu %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.xor %8, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.remu %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.remu %10, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_38.mlir b/benchmarks/XDSL_FUNC/8_function_38.mlir new file mode 100644 index 0000000..5310fee --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_38.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.or %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %10 = riscv.divu %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.xor %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.and %13, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %16 = riscv.zext.w %15 : (!riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %18 = riscv.czero.eqz %14, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.czero.nez %16, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.or %18, %19 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i64 + func.return %21 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_39.mlir b/benchmarks/XDSL_FUNC/8_function_39.mlir new file mode 100644 index 0000000..bda5b94 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_39.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.sra %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = riscv.and %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.divu %13, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %14, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + func.return %16 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_4.mlir b/benchmarks/XDSL_FUNC/8_function_4.mlir new file mode 100644 index 0000000..f91727d --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_4.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.sra %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %10 = riscv.czero.eqz %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.sra %12, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %13, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %16 = riscv.remu %15, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.sltu %14, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i1 + func.return %18 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_40.mlir b/benchmarks/XDSL_FUNC/8_function_40.mlir new file mode 100644 index 0000000..107c128 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_40.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = riscv.sltu %3, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xori %4, 1 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %10 = riscv.czero.eqz %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %16 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %17 = riscv.sra %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %19 = riscv.or %17, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.sra %14, %19 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i64 + func.return %21 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_41.mlir b/benchmarks/XDSL_FUNC/8_function_41.mlir new file mode 100644 index 0000000..d5b61ce --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_41.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.xori %2, 1 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.sra %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %14 = riscv.and %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.xor %14, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.remu %10, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %18 = riscv.czero.eqz %14, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.czero.nez %16, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.or %18, %19 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i32 + func.return %21 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_42.mlir b/benchmarks/XDSL_FUNC/8_function_42.mlir new file mode 100644 index 0000000..e0317da --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_42.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.srl %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.zext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.rem %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.srl %9, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i64 + func.return %16 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_43.mlir b/benchmarks/XDSL_FUNC/8_function_43.mlir new file mode 100644 index 0000000..70628e9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_43.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i1, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.sra %1, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.remu %1, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.divu %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_44.mlir b/benchmarks/XDSL_FUNC/8_function_44.mlir new file mode 100644 index 0000000..4b58d4a --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_44.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = riscv.remu %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.and %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = riscv.div %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %11, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.slt %5, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.xori %13, 1 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_45.mlir b/benchmarks/XDSL_FUNC/8_function_45.mlir new file mode 100644 index 0000000..f3eb227 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_45.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.remu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.sra %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.and %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.rem %12, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.srl %9, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_46.mlir b/benchmarks/XDSL_FUNC/8_function_46.mlir new file mode 100644 index 0000000..2fa62b7 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_46.mlir @@ -0,0 +1,26 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %7 = riscv.czero.eqz %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.czero.nez %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.or %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.divu %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.div %9, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %15 = riscv.div %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + %17 = builtin.unrealized_conversion_cast %16 : i32 to !riscv.reg + %18 = riscv.zext.w %17 : (!riscv.reg) -> !riscv.reg + %19 = builtin.unrealized_conversion_cast %18 : !riscv.reg to i1 + func.return %19 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_47.mlir b/benchmarks/XDSL_FUNC/8_function_47.mlir new file mode 100644 index 0000000..de4e377 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_47.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %1 : !riscv.reg to i1 + %3 = riscv.rem %1, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %2 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.xor %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = riscv.divu %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.rem %8, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_48.mlir b/benchmarks/XDSL_FUNC/8_function_48.mlir new file mode 100644 index 0000000..c40431c --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_48.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.div %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.divu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.srl %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = riscv.remu %3, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.xor %12, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.rem %5, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_49.mlir b/benchmarks/XDSL_FUNC/8_function_49.mlir new file mode 100644 index 0000000..5659252 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_49.mlir @@ -0,0 +1,26 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1, %arg6_3: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %3 = riscv.czero.eqz %0, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.czero.nez %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.divu %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.and %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %13 = riscv.czero.eqz %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.and %15, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %18 = riscv.and %16, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = builtin.unrealized_conversion_cast %18 : !riscv.reg to i32 + func.return %19 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_5.mlir b/benchmarks/XDSL_FUNC/8_function_5.mlir new file mode 100644 index 0000000..71d2ae2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_5.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i32 + %7 = builtin.unrealized_conversion_cast %6 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.rem %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.sext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %14 = riscv.xor %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.lui 0 : () -> !riscv.reg + %16 = riscv.sltu %15, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i1 + func.return %17 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_50.mlir b/benchmarks/XDSL_FUNC/8_function_50.mlir new file mode 100644 index 0000000..e455b66 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_50.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.divu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %7, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %10 = riscv.czero.eqz %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.srl %6, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_51.mlir b/benchmarks/XDSL_FUNC/8_function_51.mlir new file mode 100644 index 0000000..9161f81 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_51.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.and %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.srl %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.div %4, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_52.mlir b/benchmarks/XDSL_FUNC/8_function_52.mlir new file mode 100644 index 0000000..36e33c9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_52.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.remu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.srl %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.zext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_53.mlir b/benchmarks/XDSL_FUNC/8_function_53.mlir new file mode 100644 index 0000000..4668a35 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_53.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %6 = riscv.czero.eqz %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.srl %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = riscv.or %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + %14 = builtin.unrealized_conversion_cast %13 : i32 to !riscv.reg + %15 = riscv.sext.w %14 : (!riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + func.return %16 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_54.mlir b/benchmarks/XDSL_FUNC/8_function_54.mlir new file mode 100644 index 0000000..1d87594 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_54.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.srl %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %8 = riscv.sext.w %7 : (!riscv.reg) -> !riscv.reg + %9 = riscv.remu %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.and %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.rem %2, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_55.mlir b/benchmarks/XDSL_FUNC/8_function_55.mlir new file mode 100644 index 0000000..f37d9f9 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_55.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.divu %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.div %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.divu %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.remu %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.zext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_56.mlir b/benchmarks/XDSL_FUNC/8_function_56.mlir new file mode 100644 index 0000000..f1347f0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_56.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.zext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %9 = riscv.or %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.remu %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.div %6, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.rem %2, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_57.mlir b/benchmarks/XDSL_FUNC/8_function_57.mlir new file mode 100644 index 0000000..0de3b92 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_57.mlir @@ -0,0 +1,29 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.slt %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i1 + %9 = builtin.unrealized_conversion_cast %8 : i1 to !riscv.reg + %10 = riscv.czero.eqz %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.sltu %4, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + %15 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %16 = builtin.unrealized_conversion_cast %14 : i1 to !riscv.reg + %17 = riscv.czero.eqz %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.czero.nez %12, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.or %17, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.or %19, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = riscv.slt %20, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = builtin.unrealized_conversion_cast %21 : !riscv.reg to i1 + func.return %22 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_58.mlir b/benchmarks/XDSL_FUNC/8_function_58.mlir new file mode 100644 index 0000000..e45200f --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_58.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = riscv.remu %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = riscv.slt %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_59.mlir b/benchmarks/XDSL_FUNC/8_function_59.mlir new file mode 100644 index 0000000..4ed405e --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_59.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.divu %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.divu %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.rem %8, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.rem %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_6.mlir b/benchmarks/XDSL_FUNC/8_function_6.mlir new file mode 100644 index 0000000..03ccc81 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_6.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %4 = riscv.czero.eqz %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.czero.nez %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.rem %8, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xor %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.divu %10, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %13 = riscv.rem %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.sra %1, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_60.mlir b/benchmarks/XDSL_FUNC/8_function_60.mlir new file mode 100644 index 0000000..90569c3 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_60.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %13 = riscv.rem %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %15 = riscv.xor %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.div %3, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i32 + func.return %17 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_61.mlir b/benchmarks/XDSL_FUNC/8_function_61.mlir new file mode 100644 index 0000000..86cb11b --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_61.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.zext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.or %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.rem %8, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.xor %9, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %12 = riscv.srl %11, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_62.mlir b/benchmarks/XDSL_FUNC/8_function_62.mlir new file mode 100644 index 0000000..bd1b8da --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_62.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.divu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.div %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.xor %6, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.sext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = riscv.sra %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %14 = riscv.and %13, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_63.mlir b/benchmarks/XDSL_FUNC/8_function_63.mlir new file mode 100644 index 0000000..f2d4af0 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_63.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sltu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xori %4, 1 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.srl %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.div %2, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %17 = riscv.remu %16, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.srl %10, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.sltu %18, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.xori %19, 1 : (!riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i1 + func.return %21 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_64.mlir b/benchmarks/XDSL_FUNC/8_function_64.mlir new file mode 100644 index 0000000..16239b5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_64.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.or %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.divu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %10 = riscv.xor %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = riscv.div %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.remu %7, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.rem %2, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i1 + func.return %15 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_65.mlir b/benchmarks/XDSL_FUNC/8_function_65.mlir new file mode 100644 index 0000000..b0dc9d2 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_65.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.srl %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.rem %10, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_66.mlir b/benchmarks/XDSL_FUNC/8_function_66.mlir new file mode 100644 index 0000000..6ba89aa --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_66.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.div %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i32 + %10 = builtin.unrealized_conversion_cast %9 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = riscv.rem %6, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.and %12, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_67.mlir b/benchmarks/XDSL_FUNC/8_function_67.mlir new file mode 100644 index 0000000..01e092e --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_67.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.or %5, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.div %2, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.and %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %10, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.sltu %11, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.xori %12, 1 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_68.mlir b/benchmarks/XDSL_FUNC/8_function_68.mlir new file mode 100644 index 0000000..61d6f44 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_68.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = riscv.rem %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.zext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_69.mlir b/benchmarks/XDSL_FUNC/8_function_69.mlir new file mode 100644 index 0000000..1b73a4e --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_69.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.divu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.rem %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %7, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.div %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.div %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.rem %6, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_7.mlir b/benchmarks/XDSL_FUNC/8_function_7.mlir new file mode 100644 index 0000000..4df1dcb --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_7.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.and %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.remu %1, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.and %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.and %10, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = riscv.remu %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %13, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_70.mlir b/benchmarks/XDSL_FUNC/8_function_70.mlir new file mode 100644 index 0000000..5b45e93 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_70.mlir @@ -0,0 +1,31 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i1, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = riscv.xor %2, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = riscv.sltiu %3, 1 : (!riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %13 = riscv.czero.eqz %1, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %17 = riscv.srl %16, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %arg6_1 : i1 to !riscv.reg + %19 = riscv.czero.eqz %15, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = riscv.czero.nez %17, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %21 = riscv.or %19, %20 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %23 = riscv.srl %22, %21 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = builtin.unrealized_conversion_cast %23 : !riscv.reg to i1 + func.return %24 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_71.mlir b/benchmarks/XDSL_FUNC/8_function_71.mlir new file mode 100644 index 0000000..2110da5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_71.mlir @@ -0,0 +1,31 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.slt %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %8 = riscv.czero.eqz %2, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + %12 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i1 + %13 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %14 = riscv.srl %13, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %16 = builtin.unrealized_conversion_cast %12 : i1 to !riscv.reg + %17 = riscv.czero.eqz %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.czero.nez %14, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.or %17, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = builtin.unrealized_conversion_cast %11 : i1 to !riscv.reg + %21 = riscv.czero.eqz %10, %20 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %22 = riscv.czero.nez %19, %20 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %23 = riscv.or %21, %22 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %24 = builtin.unrealized_conversion_cast %23 : !riscv.reg to i64 + func.return %24 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_72.mlir b/benchmarks/XDSL_FUNC/8_function_72.mlir new file mode 100644 index 0000000..e8cd541 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_72.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.divu %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.sra %3, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i1 + func.return %13 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_73.mlir b/benchmarks/XDSL_FUNC/8_function_73.mlir new file mode 100644 index 0000000..a7ad789 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_73.mlir @@ -0,0 +1,18 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.divu %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.divu %7, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.xor %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sra %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + func.return %11 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_74.mlir b/benchmarks/XDSL_FUNC/8_function_74.mlir new file mode 100644 index 0000000..b407bdc --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_74.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = riscv.and %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i1 + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.divu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %3, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = riscv.and %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %4 : i1 to !riscv.reg + %13 = riscv.czero.eqz %8, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + func.return %16 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_75.mlir b/benchmarks/XDSL_FUNC/8_function_75.mlir new file mode 100644 index 0000000..6c000f6 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_75.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = riscv.xor %7, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.and %8, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.sext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = riscv.or %13, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_76.mlir b/benchmarks/XDSL_FUNC/8_function_76.mlir new file mode 100644 index 0000000..a3a1f6a --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_76.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.div %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %10 = riscv.czero.eqz %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.czero.nez %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.or %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.rem %4, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + %15 = builtin.unrealized_conversion_cast %14 : i32 to !riscv.reg + %16 = riscv.zext.w %15 : (!riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i1 + func.return %17 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_77.mlir b/benchmarks/XDSL_FUNC/8_function_77.mlir new file mode 100644 index 0000000..b1f7689 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_77.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.div %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.rem %10, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %16 = riscv.or %14, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.xor %16, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i64 + func.return %18 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_78.mlir b/benchmarks/XDSL_FUNC/8_function_78.mlir new file mode 100644 index 0000000..8b54962 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_78.mlir @@ -0,0 +1,27 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64, %arg6_3: i1) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.or %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %8 = riscv.czero.eqz %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_3 : i1 to !riscv.reg + %13 = riscv.czero.eqz %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.div %10, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.srl %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.remu %4, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.divu %1, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = builtin.unrealized_conversion_cast %19 : !riscv.reg to i64 + func.return %20 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_79.mlir b/benchmarks/XDSL_FUNC/8_function_79.mlir new file mode 100644 index 0000000..4d2fcbb --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_79.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %9 = riscv.czero.eqz %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + %13 = builtin.unrealized_conversion_cast %12 : i32 to !riscv.reg + %14 = riscv.zext.w %13 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %16 = riscv.div %15, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.sltu %5, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i1 + func.return %18 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_8.mlir b/benchmarks/XDSL_FUNC/8_function_8.mlir new file mode 100644 index 0000000..0f08320 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_8.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.or %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.and %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.and %8, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %11 = riscv.zext.w %10 : (!riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %13 = riscv.and %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %13, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.xor %14, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.sltiu %15, 1 : (!riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i1 + func.return %17 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_80.mlir b/benchmarks/XDSL_FUNC/8_function_80.mlir new file mode 100644 index 0000000..a020e36 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_80.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %5 = riscv.remu %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.srl %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.or %9, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.rem %10, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.srl %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.rem %2, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i32 + func.return %14 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_81.mlir b/benchmarks/XDSL_FUNC/8_function_81.mlir new file mode 100644 index 0000000..d07a2dc --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_81.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i1 + %2 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %1 : i1 to !riscv.reg + %5 = riscv.czero.eqz %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.czero.nez %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.or %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %10 = riscv.div %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.sra %7, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.and %7, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %14 = riscv.div %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.div %11, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.sra %12, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_82.mlir b/benchmarks/XDSL_FUNC/8_function_82.mlir new file mode 100644 index 0000000..79d2766 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_82.mlir @@ -0,0 +1,28 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i1) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i1 to !riscv.reg + %6 = riscv.czero.eqz %3, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.czero.nez %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.or %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.slt %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i1 + %11 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %13 = riscv.or %12, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %10 : i1 to !riscv.reg + %15 = riscv.czero.eqz %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.czero.nez %2, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.or %15, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i32 + %19 = builtin.unrealized_conversion_cast %18 : i32 to !riscv.reg + %20 = riscv.sext.w %19 : (!riscv.reg) -> !riscv.reg + %21 = builtin.unrealized_conversion_cast %20 : !riscv.reg to i32 + func.return %21 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_83.mlir b/benchmarks/XDSL_FUNC/8_function_83.mlir new file mode 100644 index 0000000..1ddbba5 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_83.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.div %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.remu %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.sra %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.srl %6, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i1 + func.return %12 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_84.mlir b/benchmarks/XDSL_FUNC/8_function_84.mlir new file mode 100644 index 0000000..0d2433e --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_84.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i32) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i32 to !riscv.reg + %5 = riscv.zext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.rem %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.and %10, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_85.mlir b/benchmarks/XDSL_FUNC/8_function_85.mlir new file mode 100644 index 0000000..5393b5b --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_85.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.remu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %11 = riscv.czero.eqz %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.czero.nez %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.or %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %15 = riscv.divu %14, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.slt %15, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i1 + func.return %17 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_86.mlir b/benchmarks/XDSL_FUNC/8_function_86.mlir new file mode 100644 index 0000000..63a4b77 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_86.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %4 = riscv.zext.w %3 : (!riscv.reg) -> !riscv.reg + %5 = riscv.srl %2, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.and %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.sext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = riscv.xor %10, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.slt %11, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.xori %12, 1 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_87.mlir b/benchmarks/XDSL_FUNC/8_function_87.mlir new file mode 100644 index 0000000..106199d --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_87.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i32, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i32 to !riscv.reg + %1 = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg + %2 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %3 = riscv.remu %1, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.srl %3, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.sra %5, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.sext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_88.mlir b/benchmarks/XDSL_FUNC/8_function_88.mlir new file mode 100644 index 0000000..a7870cb --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_88.mlir @@ -0,0 +1,23 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.xor %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.xor %6, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.xor %7, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.div %4, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = riscv.rem %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %14 = riscv.xor %13, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.sltu %14, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i1 + func.return %16 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_89.mlir b/benchmarks/XDSL_FUNC/8_function_89.mlir new file mode 100644 index 0000000..e36bb3c --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_89.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.xor %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %5 = riscv.and %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.div %2, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %6 : !riscv.reg to i32 + %8 = builtin.unrealized_conversion_cast %7 : i32 to !riscv.reg + %9 = riscv.zext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.zext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i32 + func.return %13 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_9.mlir b/benchmarks/XDSL_FUNC/8_function_9.mlir new file mode 100644 index 0000000..2d9c0ba --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_9.mlir @@ -0,0 +1,20 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = builtin.unrealized_conversion_cast %3 : !riscv.reg to i32 + %5 = builtin.unrealized_conversion_cast %4 : i32 to !riscv.reg + %6 = riscv.sext.w %5 : (!riscv.reg) -> !riscv.reg + %7 = riscv.remu %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.and %8, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.divu %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.rem %10, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = riscv.div %2, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = builtin.unrealized_conversion_cast %12 : !riscv.reg to i64 + func.return %13 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_90.mlir b/benchmarks/XDSL_FUNC/8_function_90.mlir new file mode 100644 index 0000000..a105181 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_90.mlir @@ -0,0 +1,26 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %7 = riscv.xor %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = riscv.sltiu %7, 1 : (!riscv.reg) -> !riscv.reg + %9 = builtin.unrealized_conversion_cast %8 : !riscv.reg to i1 + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %9 : i1 to !riscv.reg + %13 = riscv.czero.eqz %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.czero.nez %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = riscv.or %13, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = builtin.unrealized_conversion_cast %15 : !riscv.reg to i32 + %17 = builtin.unrealized_conversion_cast %16 : i32 to !riscv.reg + %18 = riscv.zext.w %17 : (!riscv.reg) -> !riscv.reg + %19 = builtin.unrealized_conversion_cast %18 : !riscv.reg to i32 + func.return %19 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_91.mlir b/benchmarks/XDSL_FUNC/8_function_91.mlir new file mode 100644 index 0000000..822e1ce --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_91.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.or %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = riscv.divu %4, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.div %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %9 : !riscv.reg to i32 + %11 = builtin.unrealized_conversion_cast %10 : i32 to !riscv.reg + %12 = riscv.sext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = riscv.slt %4, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i1 + func.return %14 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_92.mlir b/benchmarks/XDSL_FUNC/8_function_92.mlir new file mode 100644 index 0000000..8ebdf9b --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_92.mlir @@ -0,0 +1,24 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.and %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.divu %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %4, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %8 = riscv.czero.eqz %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.czero.nez %5, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %8, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %10 : !riscv.reg to i32 + %12 = builtin.unrealized_conversion_cast %11 : i32 to !riscv.reg + %13 = riscv.sext.w %12 : (!riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %15 = riscv.and %14, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %16 = riscv.remu %13, %15 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = builtin.unrealized_conversion_cast %16 : !riscv.reg to i64 + func.return %17 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_93.mlir b/benchmarks/XDSL_FUNC/8_function_93.mlir new file mode 100644 index 0000000..528324e --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_93.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i1, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %2 = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i32 + %4 = builtin.unrealized_conversion_cast %3 : i32 to !riscv.reg + %5 = riscv.sext.w %4 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %7 = riscv.divu %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6 : i1 to !riscv.reg + %9 = riscv.czero.eqz %5, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.czero.nez %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.or %9, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + %13 = builtin.unrealized_conversion_cast %12 : i32 to !riscv.reg + %14 = riscv.sext.w %13 : (!riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i32 + func.return %15 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_94.mlir b/benchmarks/XDSL_FUNC/8_function_94.mlir new file mode 100644 index 0000000..d2baba8 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_94.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64, %arg6_3: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.slt %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i1 + %6 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %7 = riscv.sra %6, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_3 : i32 to !riscv.reg + %9 = riscv.sext.w %8 : (!riscv.reg) -> !riscv.reg + %10 = riscv.rem %7, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %5 : i1 to !riscv.reg + %12 = riscv.czero.eqz %2, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %16 = riscv.rem %15, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.sra %14, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i64 + func.return %18 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_95.mlir b/benchmarks/XDSL_FUNC/8_function_95.mlir new file mode 100644 index 0000000..ac5c30f --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_95.mlir @@ -0,0 +1,27 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %4 = riscv.sltu %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.xori %4, 1 : (!riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %5 : !riscv.reg to i1 + %7 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.remu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %6 : i1 to !riscv.reg + %12 = riscv.czero.eqz %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %16 = riscv.divu %15, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.sra %14, %16 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = riscv.divu %14, %17 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %19 = riscv.sltu %14, %18 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %20 = builtin.unrealized_conversion_cast %19 : !riscv.reg to i1 + func.return %20 : i1 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_96.mlir b/benchmarks/XDSL_FUNC/8_function_96.mlir new file mode 100644 index 0000000..9418a5b --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_96.mlir @@ -0,0 +1,22 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %4 = riscv.rem %3, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = builtin.unrealized_conversion_cast %4 : !riscv.reg to i32 + %6 = builtin.unrealized_conversion_cast %5 : i32 to !riscv.reg + %7 = riscv.sext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %7 : !riscv.reg to i32 + %9 = builtin.unrealized_conversion_cast %8 : i32 to !riscv.reg + %10 = riscv.zext.w %9 : (!riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %12 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %13 = riscv.remu %11, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.divu %10, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %14 : !riscv.reg to i64 + func.return %15 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_97.mlir b/benchmarks/XDSL_FUNC/8_function_97.mlir new file mode 100644 index 0000000..6aac91e --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_97.mlir @@ -0,0 +1,21 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i32) -> i64 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to i32 + %2 = builtin.unrealized_conversion_cast %1 : i32 to !riscv.reg + %3 = riscv.sext.w %2 : (!riscv.reg) -> !riscv.reg + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = riscv.xor %4, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %7 = riscv.zext.w %6 : (!riscv.reg) -> !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %9 = riscv.remu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.or %9, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = builtin.unrealized_conversion_cast %arg6_2 : i32 to !riscv.reg + %12 = riscv.sext.w %11 : (!riscv.reg) -> !riscv.reg + %13 = riscv.divu %10, %12 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = builtin.unrealized_conversion_cast %13 : !riscv.reg to i64 + func.return %14 : i64 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_98.mlir b/benchmarks/XDSL_FUNC/8_function_98.mlir new file mode 100644 index 0000000..13e3738 --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_98.mlir @@ -0,0 +1,19 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i32 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %2 = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %4 = riscv.rem %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %5 = riscv.or %2, %2 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %6 = riscv.xor %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %8 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %9 = riscv.divu %7, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = riscv.sra %6, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %11 = riscv.divu %2, %10 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %12 = builtin.unrealized_conversion_cast %11 : !riscv.reg to i32 + func.return %12 : i32 + } +} + diff --git a/benchmarks/XDSL_FUNC/8_function_99.mlir b/benchmarks/XDSL_FUNC/8_function_99.mlir new file mode 100644 index 0000000..1ee7eab --- /dev/null +++ b/benchmarks/XDSL_FUNC/8_function_99.mlir @@ -0,0 +1,25 @@ +builtin.module { + func.func @func0(%arg6: i64, %arg6_1: i64, %arg6_2: i64) -> i1 { + %0 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %1 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %2 = riscv.sltu %1, %0 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %3 = builtin.unrealized_conversion_cast %2 : !riscv.reg to i1 + %4 = builtin.unrealized_conversion_cast %arg6_1 : i64 to !riscv.reg + %5 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %6 = riscv.or %5, %4 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %7 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %8 = riscv.srl %6, %7 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %9 = riscv.div %6, %8 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %10 = builtin.unrealized_conversion_cast %arg6_2 : i64 to !riscv.reg + %11 = builtin.unrealized_conversion_cast %3 : i1 to !riscv.reg + %12 = riscv.czero.eqz %9, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %13 = riscv.czero.nez %10, %11 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %14 = riscv.or %12, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %15 = builtin.unrealized_conversion_cast %arg6 : i64 to !riscv.reg + %16 = riscv.xor %15, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %17 = riscv.remu %16, %9 : (!riscv.reg, !riscv.reg) -> !riscv.reg + %18 = builtin.unrealized_conversion_cast %17 : !riscv.reg to i1 + func.return %18 : i1 + } +} + diff --git a/benchmarks/logs/3_function_25_xdsl_reg_alloc.log b/benchmarks/logs/3_function_25_xdsl_reg_alloc.log new file mode 100644 index 0000000..ce3a033 --- /dev/null +++ b/benchmarks/logs/3_function_25_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/3_function_25.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/3_function_28_xdsl_reg_alloc.log b/benchmarks/logs/3_function_28_xdsl_reg_alloc.log new file mode 100644 index 0000000..3203574 --- /dev/null +++ b/benchmarks/logs/3_function_28_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/3_function_28.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/3_function_57_xdsl_reg_alloc.log b/benchmarks/logs/3_function_57_xdsl_reg_alloc.log new file mode 100644 index 0000000..3e7582d --- /dev/null +++ b/benchmarks/logs/3_function_57_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/3_function_57.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/3_function_8_xdsl_reg_alloc.log b/benchmarks/logs/3_function_8_xdsl_reg_alloc.log new file mode 100644 index 0000000..d7bfebb --- /dev/null +++ b/benchmarks/logs/3_function_8_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/3_function_8.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/3_function_90_xdsl_reg_alloc.log b/benchmarks/logs/3_function_90_xdsl_reg_alloc.log new file mode 100644 index 0000000..bb800fa --- /dev/null +++ b/benchmarks/logs/3_function_90_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/3_function_90.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/3_function_91_xdsl_reg_alloc.log b/benchmarks/logs/3_function_91_xdsl_reg_alloc.log new file mode 100644 index 0000000..39eafe3 --- /dev/null +++ b/benchmarks/logs/3_function_91_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/3_function_91.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/3_function_95_xdsl_reg_alloc.log b/benchmarks/logs/3_function_95_xdsl_reg_alloc.log new file mode 100644 index 0000000..a6dff2a --- /dev/null +++ b/benchmarks/logs/3_function_95_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/3_function_95.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/4_function_22_xdsl_reg_alloc.log b/benchmarks/logs/4_function_22_xdsl_reg_alloc.log new file mode 100644 index 0000000..955db76 --- /dev/null +++ b/benchmarks/logs/4_function_22_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/4_function_22.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/4_function_30_xdsl_reg_alloc.log b/benchmarks/logs/4_function_30_xdsl_reg_alloc.log new file mode 100644 index 0000000..102507c --- /dev/null +++ b/benchmarks/logs/4_function_30_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/4_function_30.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/4_function_62_xdsl_reg_alloc.log b/benchmarks/logs/4_function_62_xdsl_reg_alloc.log new file mode 100644 index 0000000..29478b2 --- /dev/null +++ b/benchmarks/logs/4_function_62_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/4_function_62.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/4_function_63_xdsl_reg_alloc.log b/benchmarks/logs/4_function_63_xdsl_reg_alloc.log new file mode 100644 index 0000000..3999e19 --- /dev/null +++ b/benchmarks/logs/4_function_63_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/4_function_63.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/4_function_89_xdsl_reg_alloc.log b/benchmarks/logs/4_function_89_xdsl_reg_alloc.log new file mode 100644 index 0000000..4c0ff37 --- /dev/null +++ b/benchmarks/logs/4_function_89_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/4_function_89.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/4_function_90_xdsl_reg_alloc.log b/benchmarks/logs/4_function_90_xdsl_reg_alloc.log new file mode 100644 index 0000000..67a00c6 --- /dev/null +++ b/benchmarks/logs/4_function_90_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/4_function_90.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/4_function_94_xdsl_reg_alloc.log b/benchmarks/logs/4_function_94_xdsl_reg_alloc.log new file mode 100644 index 0000000..1d429a9 --- /dev/null +++ b/benchmarks/logs/4_function_94_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/4_function_94.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_12_xdsl_reg_alloc.log b/benchmarks/logs/5_function_12_xdsl_reg_alloc.log new file mode 100644 index 0000000..4c4c04f --- /dev/null +++ b/benchmarks/logs/5_function_12_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_12.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_19_xdsl_reg_alloc.log b/benchmarks/logs/5_function_19_xdsl_reg_alloc.log new file mode 100644 index 0000000..887f553 --- /dev/null +++ b/benchmarks/logs/5_function_19_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_19.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_1_xdsl_reg_alloc.log b/benchmarks/logs/5_function_1_xdsl_reg_alloc.log new file mode 100644 index 0000000..0b82034 --- /dev/null +++ b/benchmarks/logs/5_function_1_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_1.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_24_xdsl_reg_alloc.log b/benchmarks/logs/5_function_24_xdsl_reg_alloc.log new file mode 100644 index 0000000..ef04e29 --- /dev/null +++ b/benchmarks/logs/5_function_24_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_24.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_27_xdsl_reg_alloc.log b/benchmarks/logs/5_function_27_xdsl_reg_alloc.log new file mode 100644 index 0000000..6a488dc --- /dev/null +++ b/benchmarks/logs/5_function_27_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_27.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_30_xdsl_reg_alloc.log b/benchmarks/logs/5_function_30_xdsl_reg_alloc.log new file mode 100644 index 0000000..ab2a323 --- /dev/null +++ b/benchmarks/logs/5_function_30_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_30.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_36_xdsl_reg_alloc.log b/benchmarks/logs/5_function_36_xdsl_reg_alloc.log new file mode 100644 index 0000000..55c1343 --- /dev/null +++ b/benchmarks/logs/5_function_36_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_36.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_45_xdsl_reg_alloc.log b/benchmarks/logs/5_function_45_xdsl_reg_alloc.log new file mode 100644 index 0000000..d83ffcd --- /dev/null +++ b/benchmarks/logs/5_function_45_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_45.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_48_xdsl_reg_alloc.log b/benchmarks/logs/5_function_48_xdsl_reg_alloc.log new file mode 100644 index 0000000..a9e0912 --- /dev/null +++ b/benchmarks/logs/5_function_48_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_48.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_55_xdsl_reg_alloc.log b/benchmarks/logs/5_function_55_xdsl_reg_alloc.log new file mode 100644 index 0000000..6b0b36a --- /dev/null +++ b/benchmarks/logs/5_function_55_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_55.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_79_xdsl_reg_alloc.log b/benchmarks/logs/5_function_79_xdsl_reg_alloc.log new file mode 100644 index 0000000..61eba70 --- /dev/null +++ b/benchmarks/logs/5_function_79_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_79.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_81_xdsl_reg_alloc.log b/benchmarks/logs/5_function_81_xdsl_reg_alloc.log new file mode 100644 index 0000000..3f8b109 --- /dev/null +++ b/benchmarks/logs/5_function_81_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_81.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_83_xdsl_reg_alloc.log b/benchmarks/logs/5_function_83_xdsl_reg_alloc.log new file mode 100644 index 0000000..e462cd8 --- /dev/null +++ b/benchmarks/logs/5_function_83_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_83.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/5_function_84_xdsl_reg_alloc.log b/benchmarks/logs/5_function_84_xdsl_reg_alloc.log new file mode 100644 index 0000000..9c3ea7e --- /dev/null +++ b/benchmarks/logs/5_function_84_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/5_function_84.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/6_function_13_xdsl_reg_alloc.log b/benchmarks/logs/6_function_13_xdsl_reg_alloc.log new file mode 100644 index 0000000..2767d90 --- /dev/null +++ b/benchmarks/logs/6_function_13_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/6_function_13.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/6_function_24_xdsl_reg_alloc.log b/benchmarks/logs/6_function_24_xdsl_reg_alloc.log new file mode 100644 index 0000000..9f06583 --- /dev/null +++ b/benchmarks/logs/6_function_24_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/6_function_24.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/6_function_45_xdsl_reg_alloc.log b/benchmarks/logs/6_function_45_xdsl_reg_alloc.log new file mode 100644 index 0000000..1a9343f --- /dev/null +++ b/benchmarks/logs/6_function_45_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/6_function_45.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/6_function_72_xdsl_reg_alloc.log b/benchmarks/logs/6_function_72_xdsl_reg_alloc.log new file mode 100644 index 0000000..d96ab30 --- /dev/null +++ b/benchmarks/logs/6_function_72_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/6_function_72.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/6_function_88_xdsl_reg_alloc.log b/benchmarks/logs/6_function_88_xdsl_reg_alloc.log new file mode 100644 index 0000000..02d60b3 --- /dev/null +++ b/benchmarks/logs/6_function_88_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/6_function_88.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/6_function_90_xdsl_reg_alloc.log b/benchmarks/logs/6_function_90_xdsl_reg_alloc.log new file mode 100644 index 0000000..c71ab81 --- /dev/null +++ b/benchmarks/logs/6_function_90_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/6_function_90.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_17_xdsl_reg_alloc.log b/benchmarks/logs/7_function_17_xdsl_reg_alloc.log new file mode 100644 index 0000000..ff8266a --- /dev/null +++ b/benchmarks/logs/7_function_17_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_17.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_26_xdsl_reg_alloc.log b/benchmarks/logs/7_function_26_xdsl_reg_alloc.log new file mode 100644 index 0000000..f1a4610 --- /dev/null +++ b/benchmarks/logs/7_function_26_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_26.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_30_xdsl_reg_alloc.log b/benchmarks/logs/7_function_30_xdsl_reg_alloc.log new file mode 100644 index 0000000..8764b19 --- /dev/null +++ b/benchmarks/logs/7_function_30_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_30.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_70_xdsl_reg_alloc.log b/benchmarks/logs/7_function_70_xdsl_reg_alloc.log new file mode 100644 index 0000000..9751690 --- /dev/null +++ b/benchmarks/logs/7_function_70_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_70.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_72_xdsl_reg_alloc.log b/benchmarks/logs/7_function_72_xdsl_reg_alloc.log new file mode 100644 index 0000000..95dd1fb --- /dev/null +++ b/benchmarks/logs/7_function_72_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_72.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_78_xdsl_reg_alloc.log b/benchmarks/logs/7_function_78_xdsl_reg_alloc.log new file mode 100644 index 0000000..c51d0a4 --- /dev/null +++ b/benchmarks/logs/7_function_78_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_78.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_79_xdsl_reg_alloc.log b/benchmarks/logs/7_function_79_xdsl_reg_alloc.log new file mode 100644 index 0000000..2ab297a --- /dev/null +++ b/benchmarks/logs/7_function_79_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_79.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_84_xdsl_reg_alloc.log b/benchmarks/logs/7_function_84_xdsl_reg_alloc.log new file mode 100644 index 0000000..9720e3b --- /dev/null +++ b/benchmarks/logs/7_function_84_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_84.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_8_xdsl_reg_alloc.log b/benchmarks/logs/7_function_8_xdsl_reg_alloc.log new file mode 100644 index 0000000..5ad4310 --- /dev/null +++ b/benchmarks/logs/7_function_8_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_8.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/7_function_9_xdsl_reg_alloc.log b/benchmarks/logs/7_function_9_xdsl_reg_alloc.log new file mode 100644 index 0000000..5af47da --- /dev/null +++ b/benchmarks/logs/7_function_9_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/7_function_9.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_34_xdsl_reg_alloc.log b/benchmarks/logs/8_function_34_xdsl_reg_alloc.log new file mode 100644 index 0000000..6408357 --- /dev/null +++ b/benchmarks/logs/8_function_34_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_34.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_47_xdsl_reg_alloc.log b/benchmarks/logs/8_function_47_xdsl_reg_alloc.log new file mode 100644 index 0000000..196eaaa --- /dev/null +++ b/benchmarks/logs/8_function_47_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_47.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_4_xdsl_reg_alloc.log b/benchmarks/logs/8_function_4_xdsl_reg_alloc.log new file mode 100644 index 0000000..4bf0831 --- /dev/null +++ b/benchmarks/logs/8_function_4_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_4.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_5_xdsl_reg_alloc.log b/benchmarks/logs/8_function_5_xdsl_reg_alloc.log new file mode 100644 index 0000000..ce80c55 --- /dev/null +++ b/benchmarks/logs/8_function_5_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_5.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_70_xdsl_reg_alloc.log b/benchmarks/logs/8_function_70_xdsl_reg_alloc.log new file mode 100644 index 0000000..6d1e38a --- /dev/null +++ b/benchmarks/logs/8_function_70_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_70.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_76_xdsl_reg_alloc.log b/benchmarks/logs/8_function_76_xdsl_reg_alloc.log new file mode 100644 index 0000000..1d5c41f --- /dev/null +++ b/benchmarks/logs/8_function_76_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_76.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_83_xdsl_reg_alloc.log b/benchmarks/logs/8_function_83_xdsl_reg_alloc.log new file mode 100644 index 0000000..e9557f8 --- /dev/null +++ b/benchmarks/logs/8_function_83_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_83.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_85_xdsl_reg_alloc.log b/benchmarks/logs/8_function_85_xdsl_reg_alloc.log new file mode 100644 index 0000000..7eff1ea --- /dev/null +++ b/benchmarks/logs/8_function_85_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_85.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_88_xdsl_reg_alloc.log b/benchmarks/logs/8_function_88_xdsl_reg_alloc.log new file mode 100644 index 0000000..94d4b21 --- /dev/null +++ b/benchmarks/logs/8_function_88_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_88.mlir with error: Unsupported bit width: i1 diff --git a/benchmarks/logs/8_function_95_xdsl_reg_alloc.log b/benchmarks/logs/8_function_95_xdsl_reg_alloc.log new file mode 100644 index 0000000..245b640 --- /dev/null +++ b/benchmarks/logs/8_function_95_xdsl_reg_alloc.log @@ -0,0 +1 @@ +XDSL_reg_alloc failed for /home/lc985/llvm-riscv-backend-evaluation/benchmarks/XDSL_FUNC/8_function_95.mlir with error: Unsupported bit width: i1 diff --git a/mca-analysis/plot.py b/mca-analysis/plot.py index 6cffb24..a597f5d 100755 --- a/mca-analysis/plot.py +++ b/mca-analysis/plot.py @@ -517,6 +517,8 @@ def violin_plot(parameter, selector1, selector2): print(f"Max ratio for {parameter} between {selector1} and {selector2} is {max_ratio}") + + if max_ratio > 200: plt.yticks(np.arange(0, 270, 50)) else: @@ -949,10 +951,16 @@ def create_latex_command(parameters, filename): latex_command_similarity_tot_sdag = f"\\newcommand{{\\PercIdenticalSdagTot}}{{{tot_similarity_sdag_true:.1f}\%}}\n" f.write(latex_command_similarity_tot_sdag) f.close() - - - +def print_worst_performers(n=5): + for param in ["tot_instructions", "tot_cycles", "tot_uops"]: + df = pd.read_csv(data_dir + param + ".csv") + df["ratio_gisel"] = df[f"VEIR_{param}"] / df[f"LLVM_globalisel_{param}"] + df["ratio_sdag"] = df[f"VEIR_{param}"] / df[f"LLVM_selectiondag_{param}"] + df["max_ratio"] = df[["ratio_gisel", "ratio_sdag"]].max(axis=1) + top = df.nlargest(n, "max_ratio")[["function_name", "ratio_gisel", "ratio_sdag", "max_ratio"]] + print(f"\n=== {param} — top {n} worst (max ratio) ===") + print(top.to_string(index=False)) def main(): @@ -998,6 +1006,7 @@ def main(): df_instructions.to_csv(data_dir + "tot_instructions.csv", index=False) df_cycles.to_csv(data_dir + "tot_cycles.csv", index=False) df_uops.to_csv(data_dir + "tot_uops.csv", index=False) + print_worst_performers() numeric_params = [p for p in params_to_evaluate if p != "similarity"] for parameter in numeric_params: diff --git a/mca-analysis/plots/geomean_comparison.pdf b/mca-analysis/plots/geomean_comparison.pdf index 78b7354..2289375 100644 Binary files a/mca-analysis/plots/geomean_comparison.pdf and b/mca-analysis/plots/geomean_comparison.pdf differ diff --git a/mca-analysis/plots/numerical_commands.tex b/mca-analysis/plots/numerical_commands.tex index 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