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common
common
 
 
managed_helpers
managed_helpers
 
 
nanoBooter
nanoBooter
 
 
nanoCLR
nanoCLR
 
 
CMakeLists.txt
CMakeLists.txt
 
 
CMakePresets.json
CMakePresets.json
 
 
README.md
README.md
 
 
board.c
board.c
 
 
board.h
board.h
 
 
launch.json
launch.json
 
 
target_BlockStorage.c
target_BlockStorage.c
 
 
target_BlockStorage.h
target_BlockStorage.h
 
 
target_common.c
target_common.c
 
 
target_common.h.in
target_common.h.in
 
 
target_system_device_adc_config.cpp
target_system_device_adc_config.cpp
 
 
target_system_device_i2c_config.cpp
target_system_device_i2c_config.cpp
 
 
target_system_device_pwm_config.cpp
target_system_device_pwm_config.cpp
 
 
target_system_device_spi_config.cpp
target_system_device_spi_config.cpp
 
 
target_system_devices_dac_config.cpp
target_system_devices_dac_config.cpp
 
 
target_system_io_ports_config.cpp
target_system_io_ports_config.cpp
 
 
target_system_io_ports_config.h
target_system_io_ports_config.h
 
 

README.md

GHI FEZ CERBERUS

Board introduction

The board here used is a GHI Fez Cerberus based upon an STM32F405RGT6.

The code is a fork from the GHI_FEZ_CERB40 initial port

The available pins have been set as can be read in the board.h file and it is there where you can set the pin usage for your required use. Visiting the official site here and per datasheet looking at Table 9. Alternate function mapping you will find possible alternative uses of the various pins. In its initial release the following pin configuration and usage has been verified. Looking at the board from the above (MCU visible) and with the USB connector at the top we have pin 1 on the left hand side.

For more information on the board specifics you can have a look at the GHI Electronics Cerberus schema

NOTE: this configuration was successfully tested in a GHI_FEZ_CERBERUS_NF board using the USB Client SP on socket 8.