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Add images to docs
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docs/src/img/uart-rx-proto.svg

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docs/src/index.md

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motivation
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specification
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core
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uart
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fpgas
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testing
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log

docs/src/uart.md

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# UART
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To communicate with the outside world, a memory-mapped UART module was added to
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the system. It contains a receiver and a transmitter.
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## Hardware block
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The receiver uses an oversampling technique to estimate transmitted bits on the
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data line. In the absence of a clock line, detection of a start bit (0 value)
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followed by sampling of data at the middle of a bit's transmission ensures
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accurate retrieval. A standard oversampling factor of 16 minimizes the error to
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1/16 from the middle point.
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```{figure} img/uart-rx-proto.svg
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:width: 200px
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:align: center
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Transmission of a byte
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```
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Specification:
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- 8 data bit
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- 1 stop bit
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- parity bit supported
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- AHB data interface
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The hardware has been tested at baud rates of 115200, 19200 and 9600.
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## Software interface

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