Update docs and set up sim flow

Author: matiasilva

.python-version docs/.python-version

@@ -21,5 +21,4 @@ fpgas
 testing
 log
 tools
-resources
 ```

docs/src/index.md

@@ -28,7 +28,7 @@
 
 ### Memory Access Instructions
 
-- [ ] LB: Load Byte (Signed)
+- [x] LB: Load Byte (Signed)
 - [ ] LH: Load Halfword (Signed)
 - [ ] LW: Load Word
 - [ ] LBU: Load Byte Unsigned

docs/src/log.md

@@ -0,0 +1 @@
+3.12.7

docs/src/resources.md

@@ -0,0 +1,10 @@
+[project]
+name = "sim"
+version = "0.1.0"
+description = "Add your description here"
+readme = "README.md"
+requires-python = ">=3.12.7"
+dependencies = [
+    "cocotb>=1.9.2",
+    "pytest>=8.3.4",
+]

sim/.python-version

@@ -0,0 +1,52 @@
+# Smoke test for UART module
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import FallingEdge, Timer, ClockCycles
+
+
+@cocotb.test()
+async def smoke_test(dut):
+    cocotb.start_soon(Clock(dut.clk, 1, units="ns").start())
+    dut.rst.value = 0
+    await ClockCycles(dut.clk, 2)
+    dut.rst.value = 1
+    await Timer(1, units="us")  # wait a bit
+    await FallingEdge(dut.clk)  # wait for falling edge/"negedge"
+    dut._log.info("test finished")
+
+
+import os
+from pathlib import Path
+from cocotb_tools import runner
+
+
+def test_lcd_runner():
+    sim = runner.Icarus()
+    root = Path(os.getenv("ROOT")) / "hdl"
+
+    sources = [
+        "lcd_st7789v3.v",
+        "serdes.v",
+        "fifo.v",
+        "decoder.v",
+        "stall.v",
+        "ram_writer.v",
+    ]
+    sources = [root / s for s in sources]
+
+    sim.build(
+        sources=sources,
+        includes=[root],
+        hdl_toplevel="lcd_st7789v3",
+        timescale=("1ns", "1ps"),
+        build_dir=f"build/build_lcd",
+        waves=True,
+    )
+
+    test_opts = {"waves": True, "test_module": "tb", "timescale": ("1ns", "1ps")}
+    sim.test(hdl_toplevel="lcd_st7789v3", **test_opts)
+
+
+if __name__ == "__main__":
+    test_lcd_runner()