Tidy up motivation

Author: matiasilva

docs/src/index.md

@@ -23,6 +23,3 @@ log
 tools
 resources
 ```
-
-Use the table of contents above to navigate to the next section or use the
-sidebar to read at your own will!

docs/src/motivation.md

@@ -1,11 +1,22 @@
 # Motivation
 
+## Aims
+
+My main goals with the project were to:
+
+1. to understand the role of each tool involved in a tapeout
+1. develop a deeper understanding of digital design, verification and compilers
+1. to understand the hardware stack from the bottom up: gates to kernel to
+   userland software
+1. learn about RISC-V, computer architecture and ISAs
+
+## The story
+
 I've
 [written about how I got into ASIC work](https://matiasilva.com/journal/riscv-from-scratch/)
 in my journal before. In a nutshell, it was very much accidentally. It wasn't by
 accident, though, that from a young age I was interested in computers and how
-they work. I was the family IT kid, even though what I knew back then is vastly
-dwarfed by what I know now.
+they work. I was the family IT kid.
 
 My years spent coding everything from physics simulations, to microcontrollers,
 to entire ticketing platforms had taught me about the limitations of the
@@ -18,11 +29,11 @@ not a physicist).
 
 I followed an unusual path into digital design. Most tend to experiment on FPGAs
 and back up RTL with simulations, with very few ever getting to take part in
-real ASIC design as costs are prohibitive. Because I got a job at an fabless
-ASIC shop, interestingly, I was missing the exact opposite. Coming from the
-software world, the inflexibility of hardware is incredibly frustrating and more
-so are the arcane development practices in that sector. I needed a reason to get
-some FPGA experience and I wanted a challenge.
+real ASIC design as costs are prohibitive. Because I got a job at a fabless ASIC
+shop, interestingly, I was missing the exact opposite. Coming from the software
+world, the inflexibility of hardware is incredibly frustrating and more so are
+the arcane development practices in that sector. I needed a reason to get some
+FPGA experience and I wanted a challenge.
 
 What better project to work on than a RISC-V core? Well, that was what I thought
 until I saw that everyone and their uncle had gotten to that challenge years
@@ -40,14 +51,6 @@ kind of hazards. So, this is where I set myself the challenge. It meant that I'd
 learn a little more about real chips, AMBA protocols like AHB and APB, and could
 be on my way to understanding modern superscalar CPUs.
 
-My main goals with the project were to:
-
-1. to understand the role of each tool involved in a tapeout
-1. develop a deeper understanding of digital design, verification and compilers
-1. to understand the hardware stack from the bottom up: gates to kernel to
-   userland software
-1. learn about RISC-V, computer architecture and ISAs
-
 Along the way, I greatly refined my command of Neovim for documentation writing
 and code, which I'd been trying to pick up for forever.