Add UART rx subsystem

Author: matiasilva

docs/src/uart.md

@@ -1,9 +1,17 @@
 # UART
 
 To communicate with the outside world, a memory-mapped UART module was added to
-the system. It contains a receiver and a transmitter.
+the system. It contains a receiver and a transmitter, both tested at baud rates
+of 115200, 19200 and 9600.
 
-## Hardware block
+## Receiver hardware
+
+Specification:
+
+- 8 data bit
+- 1 stop bit
+- parity bit supported
+- AHB data interface
 
 The receiver uses an oversampling technique to estimate transmitted bits on the
 data line. In the absence of a clock line, detection of a start bit (0 value)
@@ -18,13 +26,14 @@ accurate retrieval. A standard oversampling factor of 16 minimizes the error to
 Transmission of a byte
 ```
 
-Specification:
+A stop bit (1 value) indicates the end of a transfer and historically provided a
+crude method of data pacing for slower processors.
 
-- 8 data bit
-- 1 stop bit
-- parity bit supported
-- AHB data interface
+### Parity
+
+The parity bit is 0 when the popcount is odd. A simple scheme to generate this
+is to negate a reduction XOR operation.
 
-The hardware has been tested at baud rates of 115200, 19200 and 9600.
+## Transmitter hardware
 
 ## Software interface

hdl/uart/baud_gen.v

@@ -1,9 +1,10 @@
 `include "platform.vh"
 `default_nettype none
 
-module baud_gen
-   #(parameter OVERSAMPLING = 16,
-   parameter BAUD_RATE = 115200) (
+module baud_gen #(
+   parameter OVERSAMPLING = 16,
+   parameter BAUD_RATE = 115200
+) (
    input wire clk,
    input wire rst_n,
 

hdl/uart/uart_rx.v

@@ -1,17 +1,75 @@
 `default_nettype none
 
-module uart_rx (
+module uart_rx #(
+   parameter WORD_WIDTH = 8,
+   parameter OVERSAMPLING = 16
+)(
    input wire clk,
    input wire rst_n,
-   input wire sd
+   input wire din,
+
+   // read interface
+   output reg rd_valid,
+   output wire [WORD_WIDTH-1:0] rd_data,
+   input wire rd_ready
 );
 
+localparam DATA_WIDTH = WORD_WIDTH + 1;
+wire parity = 1'b1;
+
 wire tick;
+wire des_done;
+wire [DATA_WIDTH-1:0] data;
+
+// errors
+wire frame_err;
+reg parity_err;
+reg overflow_err;
 
-baud_gen baud_gen0 (
+baud_gen #( .OVERSAMPLING(OVERSAMPLING) ) baud_gen0 (
    .clk(clk),
    .rst_n(rst_n),
    .tick(tick)
 );
 
+uart_rx_des #( .OVERSAMPLING(OVERSAMPLING), .WORD_WIDTH(WORD_WIDTH) )
+   uart_rx_des0 (
+   .clk(clk),
+   .rst_n(rst_n),
+   .tick(tick),
+   .din(din),
+   .parity_en(parity),
+   .dout(data),
+   .frame_err(frame_err),
+   .done(des_done)
+);
+
+// UART interface
+reg [WORD_WIDTH-1:0] dbuf;
+
+always @(posedge clk or negedge rst_n) begin
+   if (~rst_n) begin
+      dbuf <= 0;
+      parity_err <= 1'b0;
+      overflow_err <= 1'b0;
+      rd_valid <= 1'b0;
+   end else begin
+      if (rd_valid && rd_ready)
+         rd_valid <= 1'b0;
+      // order matters here, fresh data added even if consumed in same cycle
+      if (des_done) begin
+         if (parity && (data[DATA_WIDTH-1] != ~(^data[DATA_WIDTH-2:0])))
+            parity_err <= 1'b1;
+         else begin
+            dbuf <= data[DATA_WIDTH-2:0];
+            if (rd_valid) // valid data but we write new data
+               overflow_err <= 1'b1;
+            rd_valid <= 1'b1;
+         end
+      end
+   end
+end
+
+assign rd_data = dbuf;
+
 endmodule

hdl/uart/uart_rx_des.v

@@ -1,15 +1,17 @@
 `default_nettype none
 
-module uart_rx_des
-   #( parameter WORD_WIDTH = 8,
-      parameter OVERSAMPLING = 16) (
+module uart_rx_des #(
+   parameter WORD_WIDTH = 8,
+   parameter OVERSAMPLING = 16
+) (
    input wire clk,
    input wire rst_n,
    input wire tick,
    input wire din,
    input wire parity_en,
-   output wire ready_tick,
-   output wire [DATA_WIDTH-1:0] dout
+   output wire [DATA_WIDTH-1:0] dout,
+   output reg frame_err,
+   output reg done
 );
 
 localparam TICK_MID_VAL = OVERSAMPLING / 2 - 1;
@@ -21,7 +23,7 @@ localparam [2:0]
    DATA       = 3'b010,
    STOP_BIT   = 3'b011;
 
-reg [2:0                     ] state, state_nxt;
+reg [2:0] state, state_nxt;
 
 // config
 reg parity, parity_nxt;
@@ -32,8 +34,7 @@ reg [$clog2(DATA_WIDTH)-1:0  ] bit_ctr, bit_ctr_nxt;
 wire [$clog2(DATA_WIDTH)-1:0] N = parity ? DATA_WIDTH : WORD_WIDTH;
 
 // outputs
-reg [DATA_WIDTH-1:0          ] d, d_nxt;
-reg ready;
+reg [DATA_WIDTH-1:0] d, d_nxt;
 
 always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
@@ -57,7 +58,8 @@ always @(*) begin
    bit_ctr_nxt  = bit_ctr;
    d_nxt        = d;
    parity_nxt   = parity;
-   ready        = 1'b0;
+   done        = 1'b0;
+   frame_err    = 1'b0;
 
    case (state)
       IDLE: begin
@@ -94,15 +96,16 @@ always @(*) begin
             if (tick_ctr == 0) begin
                state_nxt = IDLE;
                if (din) // check data line deasserted
-                  ready = 1'b1;
+                  done = 1'b1;
+               else
+                  frame_err = 1'b1;
             end else
                tick_ctr_nxt = tick_ctr - 1;
          end
       end
    endcase
 end
 
-assign ready_tick = ready;
 assign dout = d;
 
 endmodule