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[ written about how I got into ASIC work] ( https://matiasilva.com/journal/riscv-from-scratch/ )
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in my journal before. In a nutshell, it was very much accidentally. It wasn't by
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accident, though, that from a young age I was interested in computers and how
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- they work. I was the family IT kid, even though what I knew back then vastly
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- dwarfs what I know now.
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+ they work. I was the family IT kid, even though what I knew back then is vastly
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+ dwarfed by what I know now.
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My years spent coding everything from physics simulations, to microcontrollers,
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to entire ticketing platforms had taught me about the limitations of the
@@ -26,10 +26,11 @@ some FPGA experience and I wanted a challenge.
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What better project to work on than a RISC-V core? Well, that was what I thought
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until I saw that everyone and their uncle had gotten to that challenge years
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- ago. While I've never looked at anyone else's cores before finishing my own, the
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- vulgarity of the RISC-V core meant that it fell short of the learning tool I
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- wanted it to be. The upshot was that there was plenty of good material online,
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- with help ranging from tooling, to environment setup, to microarchitecture.
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+ ago[ ^ defence ] . While I've never looked at anyone else's cores before finishing
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+ my own, the vulgarity of the RISC-V core meant that it fell short of the
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+ learning tool I wanted it to be. The upshot was that there was plenty of good
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+ material online, with help ranging from tooling, to environment setup, to
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+ microarchitecture.
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A glaring similarity among many RISC-V projects out there was that few were ever
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able to "talk to" anything. In the real world, this is not how things work. CPU
@@ -49,3 +50,7 @@ My main goals with the project were to:
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Along the way, I greatly refined my command of Neovim for documentation writing
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and code, which I'd been trying to pick up for forever.
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+
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+ [ ^ defence ] :
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+ In my defence, I was 12 when the first RISC-V ISA came out and 16 when
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+ homemade cores began entering the mainstream.
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