info.yaml

# Tiny Tapeout project information
project:
  title:        "DIGI_OTA"      # Project title
  author:       "ABNER"      # Your name
  discord:      "UABC"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "Operational transconductance amplifier"      # One line description of what your project does
  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     10000000       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_DIGI_OTA"

  # List your project's source files here.
  # Source files must be in ./src and you must list each source file separately, one per line.
  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
  source_files:
    - "tt_um_DIGI_OTA.v"

# Indicate if the project has analog components
  is_analog: true  # New field added to indicate analog behavior

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: 
    name: "Vip"
    is_analog: true     # Indicating that this is an analog signal
  ui[1]: 
    name: "Vin"
    is_analog: true     # Indicating that this is an analog signal
  ui[2]: "UI2"
  ui[3]: "UI3"
  ui[4]: "UI4"
  ui[5]: "UI5"
  ui[6]: "UI6"
  ui[7]: "UI7"

  # Outputs
  uo[0]: 
    name: "Out"
    is_analog: true     # Indicating analog signal
  uo[1]: "UO1"
  uo[2]: "UO2"
  uo[3]: "UO3"
  uo[4]: "UO4"
  uo[5]: "UO5"
  uo[6]: "UO6"
  uo[7]: "UO7"

  # Bidirectional pins
  uio[0]: "UIO0"
  uio[1]: "UIO1"
  uio[2]: "UIO"
  uio[3]: "UIO3"
  uio[4]: "UIO4"
  uio[5]: "UIO5"
  uio[6]: "UIO6"
  uio[7]: "UIO7"

# Do not change!
yaml_version: 6